pciide.c revision 1.161
1 /* $NetBSD: pciide.c,v 1.161 2002/07/26 10:23:30 onoe Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.161 2002/07/26 10:23:30 onoe Exp $"); 80 81 #ifndef WDCDEBUG 82 #define WDCDEBUG 83 #endif 84 85 #define DEBUG_DMA 0x01 86 #define DEBUG_XFERS 0x02 87 #define DEBUG_FUNCS 0x08 88 #define DEBUG_PROBE 0x10 89 #ifdef WDCDEBUG 90 int wdcdebug_pciide_mask = 0; 91 #define WDCDEBUG_PRINT(args, level) \ 92 if (wdcdebug_pciide_mask & (level)) printf args 93 #else 94 #define WDCDEBUG_PRINT(args, level) 95 #endif 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <machine/endian.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/pciide_sl82c105_reg.h> 122 #include <dev/pci/cy82c693var.h> 123 124 #include "opt_pciide.h" 125 126 /* inlines for reading/writing 8-bit PCI registers */ 127 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 128 int)); 129 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 130 int, u_int8_t)); 131 132 static __inline u_int8_t 133 pciide_pci_read(pc, pa, reg) 134 pci_chipset_tag_t pc; 135 pcitag_t pa; 136 int reg; 137 { 138 139 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 140 ((reg & 0x03) * 8) & 0xff); 141 } 142 143 static __inline void 144 pciide_pci_write(pc, pa, reg, val) 145 pci_chipset_tag_t pc; 146 pcitag_t pa; 147 int reg; 148 u_int8_t val; 149 { 150 pcireg_t pcival; 151 152 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 153 pcival &= ~(0xff << ((reg & 0x03) * 8)); 154 pcival |= (val << ((reg & 0x03) * 8)); 155 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 156 } 157 158 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 160 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 void piix_setup_channel __P((struct channel_softc*)); 162 void piix3_4_setup_channel __P((struct channel_softc*)); 163 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 165 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 166 167 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void amd7x6_setup_channel __P((struct channel_softc*)); 169 170 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void apollo_setup_channel __P((struct channel_softc*)); 172 173 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cmd0643_9_setup_channel __P((struct channel_softc*)); 176 void cmd_channel_map __P((struct pci_attach_args *, 177 struct pciide_softc *, int)); 178 int cmd_pci_intr __P((void *)); 179 void cmd646_9_irqack __P((struct channel_softc *)); 180 void cmd680_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void cmd680_setup_channel __P((struct channel_softc*)); 182 void cmd680_channel_map __P((struct pci_attach_args *, 183 struct pciide_softc *, int)); 184 185 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 186 void cy693_setup_channel __P((struct channel_softc*)); 187 188 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void sis_setup_channel __P((struct channel_softc*)); 190 static int sis_hostbr_match __P(( struct pci_attach_args *)); 191 192 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void acer_setup_channel __P((struct channel_softc*)); 194 int acer_pci_intr __P((void *)); 195 196 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 197 void pdc202xx_setup_channel __P((struct channel_softc*)); 198 void pdc20268_setup_channel __P((struct channel_softc*)); 199 int pdc202xx_pci_intr __P((void *)); 200 int pdc20265_pci_intr __P((void *)); 201 202 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 203 void opti_setup_channel __P((struct channel_softc*)); 204 205 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 206 void hpt_setup_channel __P((struct channel_softc*)); 207 int hpt_pci_intr __P((void *)); 208 209 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 210 void acard_setup_channel __P((struct channel_softc*)); 211 int acard_pci_intr __P((void *)); 212 213 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 214 void serverworks_setup_channel __P((struct channel_softc*)); 215 int serverworks_pci_intr __P((void *)); 216 217 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 218 void sl82c105_setup_channel __P((struct channel_softc*)); 219 220 void pciide_channel_dma_setup __P((struct pciide_channel *)); 221 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 222 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 223 void pciide_dma_start __P((void*, int, int)); 224 int pciide_dma_finish __P((void*, int, int, int)); 225 void pciide_irqack __P((struct channel_softc *)); 226 void pciide_print_modes __P((struct pciide_channel *)); 227 228 struct pciide_product_desc { 229 u_int32_t ide_product; 230 int ide_flags; 231 const char *ide_name; 232 /* map and setup chip, probe drives */ 233 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 234 }; 235 236 /* Flags for ide_flags */ 237 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 238 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 239 240 /* Default product description for devices not known from this controller */ 241 const struct pciide_product_desc default_product_desc = { 242 0, 243 0, 244 "Generic PCI IDE controller", 245 default_chip_map, 246 }; 247 248 const struct pciide_product_desc pciide_intel_products[] = { 249 { PCI_PRODUCT_INTEL_82092AA, 250 0, 251 "Intel 82092AA IDE controller", 252 default_chip_map, 253 }, 254 { PCI_PRODUCT_INTEL_82371FB_IDE, 255 0, 256 "Intel 82371FB IDE controller (PIIX)", 257 piix_chip_map, 258 }, 259 { PCI_PRODUCT_INTEL_82371SB_IDE, 260 0, 261 "Intel 82371SB IDE Interface (PIIX3)", 262 piix_chip_map, 263 }, 264 { PCI_PRODUCT_INTEL_82371AB_IDE, 265 0, 266 "Intel 82371AB IDE controller (PIIX4)", 267 piix_chip_map, 268 }, 269 { PCI_PRODUCT_INTEL_82440MX_IDE, 270 0, 271 "Intel 82440MX IDE controller", 272 piix_chip_map 273 }, 274 { PCI_PRODUCT_INTEL_82801AA_IDE, 275 0, 276 "Intel 82801AA IDE Controller (ICH)", 277 piix_chip_map, 278 }, 279 { PCI_PRODUCT_INTEL_82801AB_IDE, 280 0, 281 "Intel 82801AB IDE Controller (ICH0)", 282 piix_chip_map, 283 }, 284 { PCI_PRODUCT_INTEL_82801BA_IDE, 285 0, 286 "Intel 82801BA IDE Controller (ICH2)", 287 piix_chip_map, 288 }, 289 { PCI_PRODUCT_INTEL_82801BAM_IDE, 290 0, 291 "Intel 82801BAM IDE Controller (ICH2)", 292 piix_chip_map, 293 }, 294 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 295 0, 296 "Intel 82201CA IDE Controller", 297 piix_chip_map, 298 }, 299 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 300 0, 301 "Intel 82201CA IDE Controller", 302 piix_chip_map, 303 }, 304 { 0, 305 0, 306 NULL, 307 NULL 308 } 309 }; 310 311 const struct pciide_product_desc pciide_amd_products[] = { 312 { PCI_PRODUCT_AMD_PBC756_IDE, 313 0, 314 "Advanced Micro Devices AMD756 IDE Controller", 315 amd7x6_chip_map 316 }, 317 { PCI_PRODUCT_AMD_PBC766_IDE, 318 0, 319 "Advanced Micro Devices AMD766 IDE Controller", 320 amd7x6_chip_map 321 }, 322 { PCI_PRODUCT_AMD_PBC768_IDE, 323 0, 324 "Advanced Micro Devices AMD768 IDE Controller", 325 amd7x6_chip_map 326 }, 327 { PCI_PRODUCT_AMD_PBC8111_IDE, 328 0, 329 "Advanced Micro Devices AMD8111 IDE Controller", 330 amd7x6_chip_map 331 }, 332 { 0, 333 0, 334 NULL, 335 NULL 336 } 337 }; 338 339 const struct pciide_product_desc pciide_cmd_products[] = { 340 { PCI_PRODUCT_CMDTECH_640, 341 0, 342 "CMD Technology PCI0640", 343 cmd_chip_map 344 }, 345 { PCI_PRODUCT_CMDTECH_643, 346 0, 347 "CMD Technology PCI0643", 348 cmd0643_9_chip_map, 349 }, 350 { PCI_PRODUCT_CMDTECH_646, 351 0, 352 "CMD Technology PCI0646", 353 cmd0643_9_chip_map, 354 }, 355 { PCI_PRODUCT_CMDTECH_648, 356 IDE_PCI_CLASS_OVERRIDE, 357 "CMD Technology PCI0648", 358 cmd0643_9_chip_map, 359 }, 360 { PCI_PRODUCT_CMDTECH_649, 361 IDE_PCI_CLASS_OVERRIDE, 362 "CMD Technology PCI0649", 363 cmd0643_9_chip_map, 364 }, 365 { PCI_PRODUCT_CMDTECH_680, 366 IDE_PCI_CLASS_OVERRIDE, 367 "Silicon Image 0680", 368 cmd680_chip_map, 369 }, 370 { 0, 371 0, 372 NULL, 373 NULL 374 } 375 }; 376 377 const struct pciide_product_desc pciide_via_products[] = { 378 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 379 0, 380 NULL, 381 apollo_chip_map, 382 }, 383 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 384 0, 385 NULL, 386 apollo_chip_map, 387 }, 388 { 0, 389 0, 390 NULL, 391 NULL 392 } 393 }; 394 395 const struct pciide_product_desc pciide_cypress_products[] = { 396 { PCI_PRODUCT_CONTAQ_82C693, 397 IDE_16BIT_IOSPACE, 398 "Cypress 82C693 IDE Controller", 399 cy693_chip_map, 400 }, 401 { 0, 402 0, 403 NULL, 404 NULL 405 } 406 }; 407 408 const struct pciide_product_desc pciide_sis_products[] = { 409 { PCI_PRODUCT_SIS_5597_IDE, 410 0, 411 "Silicon Integrated System 5597/5598 IDE controller", 412 sis_chip_map, 413 }, 414 { 0, 415 0, 416 NULL, 417 NULL 418 } 419 }; 420 421 const struct pciide_product_desc pciide_acer_products[] = { 422 { PCI_PRODUCT_ALI_M5229, 423 0, 424 "Acer Labs M5229 UDMA IDE Controller", 425 acer_chip_map, 426 }, 427 { 0, 428 0, 429 NULL, 430 NULL 431 } 432 }; 433 434 const struct pciide_product_desc pciide_promise_products[] = { 435 { PCI_PRODUCT_PROMISE_ULTRA33, 436 IDE_PCI_CLASS_OVERRIDE, 437 "Promise Ultra33/ATA Bus Master IDE Accelerator", 438 pdc202xx_chip_map, 439 }, 440 { PCI_PRODUCT_PROMISE_ULTRA66, 441 IDE_PCI_CLASS_OVERRIDE, 442 "Promise Ultra66/ATA Bus Master IDE Accelerator", 443 pdc202xx_chip_map, 444 }, 445 { PCI_PRODUCT_PROMISE_ULTRA100, 446 IDE_PCI_CLASS_OVERRIDE, 447 "Promise Ultra100/ATA Bus Master IDE Accelerator", 448 pdc202xx_chip_map, 449 }, 450 { PCI_PRODUCT_PROMISE_ULTRA100X, 451 IDE_PCI_CLASS_OVERRIDE, 452 "Promise Ultra100/ATA Bus Master IDE Accelerator", 453 pdc202xx_chip_map, 454 }, 455 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 456 IDE_PCI_CLASS_OVERRIDE, 457 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 458 pdc202xx_chip_map, 459 }, 460 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 461 IDE_PCI_CLASS_OVERRIDE, 462 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 463 pdc202xx_chip_map, 464 }, 465 { PCI_PRODUCT_PROMISE_ULTRA133, 466 IDE_PCI_CLASS_OVERRIDE, 467 "Promise Ultra133/ATA Bus Master IDE Accelerator", 468 pdc202xx_chip_map, 469 }, 470 { 0, 471 0, 472 NULL, 473 NULL 474 } 475 }; 476 477 const struct pciide_product_desc pciide_opti_products[] = { 478 { PCI_PRODUCT_OPTI_82C621, 479 0, 480 "OPTi 82c621 PCI IDE controller", 481 opti_chip_map, 482 }, 483 { PCI_PRODUCT_OPTI_82C568, 484 0, 485 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 486 opti_chip_map, 487 }, 488 { PCI_PRODUCT_OPTI_82D568, 489 0, 490 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 491 opti_chip_map, 492 }, 493 { 0, 494 0, 495 NULL, 496 NULL 497 } 498 }; 499 500 const struct pciide_product_desc pciide_triones_products[] = { 501 { PCI_PRODUCT_TRIONES_HPT366, 502 IDE_PCI_CLASS_OVERRIDE, 503 NULL, 504 hpt_chip_map, 505 }, 506 { PCI_PRODUCT_TRIONES_HPT374, 507 IDE_PCI_CLASS_OVERRIDE, 508 NULL, 509 hpt_chip_map 510 }, 511 { 0, 512 0, 513 NULL, 514 NULL 515 } 516 }; 517 518 const struct pciide_product_desc pciide_acard_products[] = { 519 { PCI_PRODUCT_ACARD_ATP850U, 520 IDE_PCI_CLASS_OVERRIDE, 521 "Acard ATP850U Ultra33 IDE Controller", 522 acard_chip_map, 523 }, 524 { PCI_PRODUCT_ACARD_ATP860, 525 IDE_PCI_CLASS_OVERRIDE, 526 "Acard ATP860 Ultra66 IDE Controller", 527 acard_chip_map, 528 }, 529 { PCI_PRODUCT_ACARD_ATP860A, 530 IDE_PCI_CLASS_OVERRIDE, 531 "Acard ATP860-A Ultra66 IDE Controller", 532 acard_chip_map, 533 }, 534 { 0, 535 0, 536 NULL, 537 NULL 538 } 539 }; 540 541 const struct pciide_product_desc pciide_serverworks_products[] = { 542 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 543 0, 544 "ServerWorks OSB4 IDE Controller", 545 serverworks_chip_map, 546 }, 547 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 548 0, 549 "ServerWorks CSB5 IDE Controller", 550 serverworks_chip_map, 551 }, 552 { 0, 553 0, 554 NULL, 555 } 556 }; 557 558 const struct pciide_product_desc pciide_symphony_products[] = { 559 { PCI_PRODUCT_SYMPHONY_82C105, 560 0, 561 "Symphony Labs 82C105 IDE controller", 562 sl82c105_chip_map, 563 }, 564 { 0, 565 0, 566 NULL, 567 } 568 }; 569 570 const struct pciide_product_desc pciide_winbond_products[] = { 571 { PCI_PRODUCT_WINBOND_W83C553F_1, 572 0, 573 "Winbond W83C553F IDE controller", 574 sl82c105_chip_map, 575 }, 576 { 0, 577 0, 578 NULL, 579 } 580 }; 581 582 struct pciide_vendor_desc { 583 u_int32_t ide_vendor; 584 const struct pciide_product_desc *ide_products; 585 }; 586 587 const struct pciide_vendor_desc pciide_vendors[] = { 588 { PCI_VENDOR_INTEL, pciide_intel_products }, 589 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 590 { PCI_VENDOR_VIATECH, pciide_via_products }, 591 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 592 { PCI_VENDOR_SIS, pciide_sis_products }, 593 { PCI_VENDOR_ALI, pciide_acer_products }, 594 { PCI_VENDOR_PROMISE, pciide_promise_products }, 595 { PCI_VENDOR_AMD, pciide_amd_products }, 596 { PCI_VENDOR_OPTI, pciide_opti_products }, 597 { PCI_VENDOR_TRIONES, pciide_triones_products }, 598 { PCI_VENDOR_ACARD, pciide_acard_products }, 599 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 600 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 601 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 602 { 0, NULL } 603 }; 604 605 /* options passed via the 'flags' config keyword */ 606 #define PCIIDE_OPTIONS_DMA 0x01 607 #define PCIIDE_OPTIONS_NODMA 0x02 608 609 int pciide_match __P((struct device *, struct cfdata *, void *)); 610 void pciide_attach __P((struct device *, struct device *, void *)); 611 612 struct cfattach pciide_ca = { 613 sizeof(struct pciide_softc), pciide_match, pciide_attach 614 }; 615 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 616 int pciide_mapregs_compat __P(( struct pci_attach_args *, 617 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 618 int pciide_mapregs_native __P((struct pci_attach_args *, 619 struct pciide_channel *, bus_size_t *, bus_size_t *, 620 int (*pci_intr) __P((void *)))); 621 void pciide_mapreg_dma __P((struct pciide_softc *, 622 struct pci_attach_args *)); 623 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 624 void pciide_mapchan __P((struct pci_attach_args *, 625 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 626 int (*pci_intr) __P((void *)))); 627 int pciide_chan_candisable __P((struct pciide_channel *)); 628 void pciide_map_compat_intr __P(( struct pci_attach_args *, 629 struct pciide_channel *, int, int)); 630 int pciide_compat_intr __P((void *)); 631 int pciide_pci_intr __P((void *)); 632 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 633 634 const struct pciide_product_desc * 635 pciide_lookup_product(id) 636 u_int32_t id; 637 { 638 const struct pciide_product_desc *pp; 639 const struct pciide_vendor_desc *vp; 640 641 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 642 if (PCI_VENDOR(id) == vp->ide_vendor) 643 break; 644 645 if ((pp = vp->ide_products) == NULL) 646 return NULL; 647 648 for (; pp->chip_map != NULL; pp++) 649 if (PCI_PRODUCT(id) == pp->ide_product) 650 break; 651 652 if (pp->chip_map == NULL) 653 return NULL; 654 return pp; 655 } 656 657 int 658 pciide_match(parent, match, aux) 659 struct device *parent; 660 struct cfdata *match; 661 void *aux; 662 { 663 struct pci_attach_args *pa = aux; 664 const struct pciide_product_desc *pp; 665 666 /* 667 * Check the ID register to see that it's a PCI IDE controller. 668 * If it is, we assume that we can deal with it; it _should_ 669 * work in a standardized way... 670 */ 671 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 672 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 673 return (1); 674 } 675 676 /* 677 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 678 * controllers. Let see if we can deal with it anyway. 679 */ 680 pp = pciide_lookup_product(pa->pa_id); 681 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 682 return (1); 683 } 684 685 return (0); 686 } 687 688 void 689 pciide_attach(parent, self, aux) 690 struct device *parent, *self; 691 void *aux; 692 { 693 struct pci_attach_args *pa = aux; 694 pci_chipset_tag_t pc = pa->pa_pc; 695 pcitag_t tag = pa->pa_tag; 696 struct pciide_softc *sc = (struct pciide_softc *)self; 697 pcireg_t csr; 698 char devinfo[256]; 699 const char *displaydev; 700 701 sc->sc_pp = pciide_lookup_product(pa->pa_id); 702 if (sc->sc_pp == NULL) { 703 sc->sc_pp = &default_product_desc; 704 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 705 displaydev = devinfo; 706 } else 707 displaydev = sc->sc_pp->ide_name; 708 709 /* if displaydev == NULL, printf is done in chip-specific map */ 710 if (displaydev) 711 printf(": %s (rev. 0x%02x)\n", displaydev, 712 PCI_REVISION(pa->pa_class)); 713 714 sc->sc_pc = pa->pa_pc; 715 sc->sc_tag = pa->pa_tag; 716 #ifdef WDCDEBUG 717 if (wdcdebug_pciide_mask & DEBUG_PROBE) 718 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 719 #endif 720 sc->sc_pp->chip_map(sc, pa); 721 722 if (sc->sc_dma_ok) { 723 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 724 csr |= PCI_COMMAND_MASTER_ENABLE; 725 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 726 } 727 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 728 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 729 } 730 731 /* tell wether the chip is enabled or not */ 732 int 733 pciide_chipen(sc, pa) 734 struct pciide_softc *sc; 735 struct pci_attach_args *pa; 736 { 737 pcireg_t csr; 738 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 739 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 740 PCI_COMMAND_STATUS_REG); 741 printf("%s: device disabled (at %s)\n", 742 sc->sc_wdcdev.sc_dev.dv_xname, 743 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 744 "device" : "bridge"); 745 return 0; 746 } 747 return 1; 748 } 749 750 int 751 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 752 struct pci_attach_args *pa; 753 struct pciide_channel *cp; 754 int compatchan; 755 bus_size_t *cmdsizep, *ctlsizep; 756 { 757 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 758 struct channel_softc *wdc_cp = &cp->wdc_channel; 759 760 cp->compat = 1; 761 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 762 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 763 764 wdc_cp->cmd_iot = pa->pa_iot; 765 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 766 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 767 printf("%s: couldn't map %s channel cmd regs\n", 768 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 769 return (0); 770 } 771 772 wdc_cp->ctl_iot = pa->pa_iot; 773 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 774 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 775 printf("%s: couldn't map %s channel ctl regs\n", 776 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 777 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 778 PCIIDE_COMPAT_CMD_SIZE); 779 return (0); 780 } 781 782 return (1); 783 } 784 785 int 786 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 787 struct pci_attach_args * pa; 788 struct pciide_channel *cp; 789 bus_size_t *cmdsizep, *ctlsizep; 790 int (*pci_intr) __P((void *)); 791 { 792 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 793 struct channel_softc *wdc_cp = &cp->wdc_channel; 794 const char *intrstr; 795 pci_intr_handle_t intrhandle; 796 797 cp->compat = 0; 798 799 if (sc->sc_pci_ih == NULL) { 800 if (pci_intr_map(pa, &intrhandle) != 0) { 801 printf("%s: couldn't map native-PCI interrupt\n", 802 sc->sc_wdcdev.sc_dev.dv_xname); 803 return 0; 804 } 805 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 806 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 807 intrhandle, IPL_BIO, pci_intr, sc); 808 if (sc->sc_pci_ih != NULL) { 809 printf("%s: using %s for native-PCI interrupt\n", 810 sc->sc_wdcdev.sc_dev.dv_xname, 811 intrstr ? intrstr : "unknown interrupt"); 812 } else { 813 printf("%s: couldn't establish native-PCI interrupt", 814 sc->sc_wdcdev.sc_dev.dv_xname); 815 if (intrstr != NULL) 816 printf(" at %s", intrstr); 817 printf("\n"); 818 return 0; 819 } 820 } 821 cp->ih = sc->sc_pci_ih; 822 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 823 PCI_MAPREG_TYPE_IO, 0, 824 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 825 printf("%s: couldn't map %s channel cmd regs\n", 826 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 827 return 0; 828 } 829 830 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 831 PCI_MAPREG_TYPE_IO, 0, 832 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 833 printf("%s: couldn't map %s channel ctl regs\n", 834 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 835 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 836 return 0; 837 } 838 /* 839 * In native mode, 4 bytes of I/O space are mapped for the control 840 * register, the control register is at offset 2. Pass the generic 841 * code a handle for only one byte at the rigth offset. 842 */ 843 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 844 &wdc_cp->ctl_ioh) != 0) { 845 printf("%s: unable to subregion %s channel ctl regs\n", 846 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 847 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 848 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 849 return 0; 850 } 851 return (1); 852 } 853 854 void 855 pciide_mapreg_dma(sc, pa) 856 struct pciide_softc *sc; 857 struct pci_attach_args *pa; 858 { 859 pcireg_t maptype; 860 bus_addr_t addr; 861 862 /* 863 * Map DMA registers 864 * 865 * Note that sc_dma_ok is the right variable to test to see if 866 * DMA can be done. If the interface doesn't support DMA, 867 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 868 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 869 * non-zero if the interface supports DMA and the registers 870 * could be mapped. 871 * 872 * XXX Note that despite the fact that the Bus Master IDE specs 873 * XXX say that "The bus master IDE function uses 16 bytes of IO 874 * XXX space," some controllers (at least the United 875 * XXX Microelectronics UM8886BF) place it in memory space. 876 */ 877 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 878 PCIIDE_REG_BUS_MASTER_DMA); 879 880 switch (maptype) { 881 case PCI_MAPREG_TYPE_IO: 882 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 883 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 884 &addr, NULL, NULL) == 0); 885 if (sc->sc_dma_ok == 0) { 886 printf(", but unused (couldn't query registers)"); 887 break; 888 } 889 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 890 && addr >= 0x10000) { 891 sc->sc_dma_ok = 0; 892 printf(", but unused (registers at unsafe address " 893 "%#lx)", (unsigned long)addr); 894 break; 895 } 896 /* FALLTHROUGH */ 897 898 case PCI_MAPREG_MEM_TYPE_32BIT: 899 sc->sc_dma_ok = (pci_mapreg_map(pa, 900 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 901 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 902 sc->sc_dmat = pa->pa_dmat; 903 if (sc->sc_dma_ok == 0) { 904 printf(", but unused (couldn't map registers)"); 905 } else { 906 sc->sc_wdcdev.dma_arg = sc; 907 sc->sc_wdcdev.dma_init = pciide_dma_init; 908 sc->sc_wdcdev.dma_start = pciide_dma_start; 909 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 910 } 911 912 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 913 PCIIDE_OPTIONS_NODMA) { 914 printf(", but unused (forced off by config file)"); 915 sc->sc_dma_ok = 0; 916 } 917 break; 918 919 default: 920 sc->sc_dma_ok = 0; 921 printf(", but unsupported register maptype (0x%x)", maptype); 922 } 923 } 924 925 int 926 pciide_compat_intr(arg) 927 void *arg; 928 { 929 struct pciide_channel *cp = arg; 930 931 #ifdef DIAGNOSTIC 932 /* should only be called for a compat channel */ 933 if (cp->compat == 0) 934 panic("pciide compat intr called for non-compat chan %p\n", cp); 935 #endif 936 return (wdcintr(&cp->wdc_channel)); 937 } 938 939 int 940 pciide_pci_intr(arg) 941 void *arg; 942 { 943 struct pciide_softc *sc = arg; 944 struct pciide_channel *cp; 945 struct channel_softc *wdc_cp; 946 int i, rv, crv; 947 948 rv = 0; 949 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 950 cp = &sc->pciide_channels[i]; 951 wdc_cp = &cp->wdc_channel; 952 953 /* If a compat channel skip. */ 954 if (cp->compat) 955 continue; 956 /* if this channel not waiting for intr, skip */ 957 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 958 continue; 959 960 crv = wdcintr(wdc_cp); 961 if (crv == 0) 962 ; /* leave rv alone */ 963 else if (crv == 1) 964 rv = 1; /* claim the intr */ 965 else if (rv == 0) /* crv should be -1 in this case */ 966 rv = crv; /* if we've done no better, take it */ 967 } 968 return (rv); 969 } 970 971 void 972 pciide_channel_dma_setup(cp) 973 struct pciide_channel *cp; 974 { 975 int drive; 976 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 977 struct ata_drive_datas *drvp; 978 979 for (drive = 0; drive < 2; drive++) { 980 drvp = &cp->wdc_channel.ch_drive[drive]; 981 /* If no drive, skip */ 982 if ((drvp->drive_flags & DRIVE) == 0) 983 continue; 984 /* setup DMA if needed */ 985 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 986 (drvp->drive_flags & DRIVE_UDMA) == 0) || 987 sc->sc_dma_ok == 0) { 988 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 989 continue; 990 } 991 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 992 != 0) { 993 /* Abort DMA setup */ 994 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 995 continue; 996 } 997 } 998 } 999 1000 int 1001 pciide_dma_table_setup(sc, channel, drive) 1002 struct pciide_softc *sc; 1003 int channel, drive; 1004 { 1005 bus_dma_segment_t seg; 1006 int error, rseg; 1007 const bus_size_t dma_table_size = 1008 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1009 struct pciide_dma_maps *dma_maps = 1010 &sc->pciide_channels[channel].dma_maps[drive]; 1011 1012 /* If table was already allocated, just return */ 1013 if (dma_maps->dma_table) 1014 return 0; 1015 1016 /* Allocate memory for the DMA tables and map it */ 1017 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1018 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1019 BUS_DMA_NOWAIT)) != 0) { 1020 printf("%s:%d: unable to allocate table DMA for " 1021 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1022 channel, drive, error); 1023 return error; 1024 } 1025 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1026 dma_table_size, 1027 (caddr_t *)&dma_maps->dma_table, 1028 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1029 printf("%s:%d: unable to map table DMA for" 1030 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1031 channel, drive, error); 1032 return error; 1033 } 1034 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1035 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1036 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1037 1038 /* Create and load table DMA map for this disk */ 1039 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1040 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1041 &dma_maps->dmamap_table)) != 0) { 1042 printf("%s:%d: unable to create table DMA map for " 1043 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1044 channel, drive, error); 1045 return error; 1046 } 1047 if ((error = bus_dmamap_load(sc->sc_dmat, 1048 dma_maps->dmamap_table, 1049 dma_maps->dma_table, 1050 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1051 printf("%s:%d: unable to load table DMA map for " 1052 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1053 channel, drive, error); 1054 return error; 1055 } 1056 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1057 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1058 DEBUG_PROBE); 1059 /* Create a xfer DMA map for this drive */ 1060 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1061 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1062 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1063 &dma_maps->dmamap_xfer)) != 0) { 1064 printf("%s:%d: unable to create xfer DMA map for " 1065 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1066 channel, drive, error); 1067 return error; 1068 } 1069 return 0; 1070 } 1071 1072 int 1073 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1074 void *v; 1075 int channel, drive; 1076 void *databuf; 1077 size_t datalen; 1078 int flags; 1079 { 1080 struct pciide_softc *sc = v; 1081 int error, seg; 1082 struct pciide_dma_maps *dma_maps = 1083 &sc->pciide_channels[channel].dma_maps[drive]; 1084 1085 error = bus_dmamap_load(sc->sc_dmat, 1086 dma_maps->dmamap_xfer, 1087 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1088 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1089 if (error) { 1090 printf("%s:%d: unable to load xfer DMA map for" 1091 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1092 channel, drive, error); 1093 return error; 1094 } 1095 1096 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1097 dma_maps->dmamap_xfer->dm_mapsize, 1098 (flags & WDC_DMA_READ) ? 1099 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1100 1101 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1102 #ifdef DIAGNOSTIC 1103 /* A segment must not cross a 64k boundary */ 1104 { 1105 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1106 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1107 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1108 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1109 printf("pciide_dma: segment %d physical addr 0x%lx" 1110 " len 0x%lx not properly aligned\n", 1111 seg, phys, len); 1112 panic("pciide_dma: buf align"); 1113 } 1114 } 1115 #endif 1116 dma_maps->dma_table[seg].base_addr = 1117 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1118 dma_maps->dma_table[seg].byte_count = 1119 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1120 IDEDMA_BYTE_COUNT_MASK); 1121 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1122 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1123 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1124 1125 } 1126 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1127 htole32(IDEDMA_BYTE_COUNT_EOT); 1128 1129 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1130 dma_maps->dmamap_table->dm_mapsize, 1131 BUS_DMASYNC_PREWRITE); 1132 1133 /* Maps are ready. Start DMA function */ 1134 #ifdef DIAGNOSTIC 1135 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1136 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1137 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1138 panic("pciide_dma_init: table align"); 1139 } 1140 #endif 1141 1142 /* Clear status bits */ 1143 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1144 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1145 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1146 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1147 /* Write table addr */ 1148 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1149 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1150 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1151 /* set read/write */ 1152 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1153 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1154 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1155 /* remember flags */ 1156 dma_maps->dma_flags = flags; 1157 return 0; 1158 } 1159 1160 void 1161 pciide_dma_start(v, channel, drive) 1162 void *v; 1163 int channel, drive; 1164 { 1165 struct pciide_softc *sc = v; 1166 1167 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1168 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1169 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1170 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1171 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1172 } 1173 1174 int 1175 pciide_dma_finish(v, channel, drive, force) 1176 void *v; 1177 int channel, drive; 1178 int force; 1179 { 1180 struct pciide_softc *sc = v; 1181 u_int8_t status; 1182 int error = 0; 1183 struct pciide_dma_maps *dma_maps = 1184 &sc->pciide_channels[channel].dma_maps[drive]; 1185 1186 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1187 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1188 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1189 DEBUG_XFERS); 1190 1191 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1192 return WDC_DMAST_NOIRQ; 1193 1194 /* stop DMA channel */ 1195 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1196 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1197 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1198 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1199 1200 /* Unload the map of the data buffer */ 1201 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1202 dma_maps->dmamap_xfer->dm_mapsize, 1203 (dma_maps->dma_flags & WDC_DMA_READ) ? 1204 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1205 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1206 1207 if ((status & IDEDMA_CTL_ERR) != 0) { 1208 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1209 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1210 error |= WDC_DMAST_ERR; 1211 } 1212 1213 if ((status & IDEDMA_CTL_INTR) == 0) { 1214 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1215 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1216 drive, status); 1217 error |= WDC_DMAST_NOIRQ; 1218 } 1219 1220 if ((status & IDEDMA_CTL_ACT) != 0) { 1221 /* data underrun, may be a valid condition for ATAPI */ 1222 error |= WDC_DMAST_UNDER; 1223 } 1224 return error; 1225 } 1226 1227 void 1228 pciide_irqack(chp) 1229 struct channel_softc *chp; 1230 { 1231 struct pciide_channel *cp = (struct pciide_channel*)chp; 1232 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1233 1234 /* clear status bits in IDE DMA registers */ 1235 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1236 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1237 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1238 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1239 } 1240 1241 /* some common code used by several chip_map */ 1242 int 1243 pciide_chansetup(sc, channel, interface) 1244 struct pciide_softc *sc; 1245 int channel; 1246 pcireg_t interface; 1247 { 1248 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1249 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1250 cp->name = PCIIDE_CHANNEL_NAME(channel); 1251 cp->wdc_channel.channel = channel; 1252 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1253 cp->wdc_channel.ch_queue = 1254 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1255 if (cp->wdc_channel.ch_queue == NULL) { 1256 printf("%s %s channel: " 1257 "can't allocate memory for command queue", 1258 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1259 return 0; 1260 } 1261 printf("%s: %s channel %s to %s mode\n", 1262 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1263 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1264 "configured" : "wired", 1265 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1266 "native-PCI" : "compatibility"); 1267 return 1; 1268 } 1269 1270 /* some common code used by several chip channel_map */ 1271 void 1272 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1273 struct pci_attach_args *pa; 1274 struct pciide_channel *cp; 1275 pcireg_t interface; 1276 bus_size_t *cmdsizep, *ctlsizep; 1277 int (*pci_intr) __P((void *)); 1278 { 1279 struct channel_softc *wdc_cp = &cp->wdc_channel; 1280 1281 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1282 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1283 pci_intr); 1284 else 1285 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1286 wdc_cp->channel, cmdsizep, ctlsizep); 1287 1288 if (cp->hw_ok == 0) 1289 return; 1290 wdc_cp->data32iot = wdc_cp->cmd_iot; 1291 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1292 wdcattach(wdc_cp); 1293 } 1294 1295 /* 1296 * Generic code to call to know if a channel can be disabled. Return 1 1297 * if channel can be disabled, 0 if not 1298 */ 1299 int 1300 pciide_chan_candisable(cp) 1301 struct pciide_channel *cp; 1302 { 1303 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1304 struct channel_softc *wdc_cp = &cp->wdc_channel; 1305 1306 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1307 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1308 printf("%s: disabling %s channel (no drives)\n", 1309 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1310 cp->hw_ok = 0; 1311 return 1; 1312 } 1313 return 0; 1314 } 1315 1316 /* 1317 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1318 * Set hw_ok=0 on failure 1319 */ 1320 void 1321 pciide_map_compat_intr(pa, cp, compatchan, interface) 1322 struct pci_attach_args *pa; 1323 struct pciide_channel *cp; 1324 int compatchan, interface; 1325 { 1326 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1327 struct channel_softc *wdc_cp = &cp->wdc_channel; 1328 1329 if (cp->hw_ok == 0) 1330 return; 1331 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1332 return; 1333 1334 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1335 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1336 pa, compatchan, pciide_compat_intr, cp); 1337 if (cp->ih == NULL) { 1338 #endif 1339 printf("%s: no compatibility interrupt for use by %s " 1340 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1341 cp->hw_ok = 0; 1342 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1343 } 1344 #endif 1345 } 1346 1347 void 1348 pciide_print_modes(cp) 1349 struct pciide_channel *cp; 1350 { 1351 wdc_print_modes(&cp->wdc_channel); 1352 } 1353 1354 void 1355 default_chip_map(sc, pa) 1356 struct pciide_softc *sc; 1357 struct pci_attach_args *pa; 1358 { 1359 struct pciide_channel *cp; 1360 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1361 pcireg_t csr; 1362 int channel, drive; 1363 struct ata_drive_datas *drvp; 1364 u_int8_t idedma_ctl; 1365 bus_size_t cmdsize, ctlsize; 1366 char *failreason; 1367 1368 if (pciide_chipen(sc, pa) == 0) 1369 return; 1370 1371 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1372 printf("%s: bus-master DMA support present", 1373 sc->sc_wdcdev.sc_dev.dv_xname); 1374 if (sc->sc_pp == &default_product_desc && 1375 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1376 PCIIDE_OPTIONS_DMA) == 0) { 1377 printf(", but unused (no driver support)"); 1378 sc->sc_dma_ok = 0; 1379 } else { 1380 pciide_mapreg_dma(sc, pa); 1381 if (sc->sc_dma_ok != 0) 1382 printf(", used without full driver " 1383 "support"); 1384 } 1385 } else { 1386 printf("%s: hardware does not support DMA", 1387 sc->sc_wdcdev.sc_dev.dv_xname); 1388 sc->sc_dma_ok = 0; 1389 } 1390 printf("\n"); 1391 if (sc->sc_dma_ok) { 1392 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1393 sc->sc_wdcdev.irqack = pciide_irqack; 1394 } 1395 sc->sc_wdcdev.PIO_cap = 0; 1396 sc->sc_wdcdev.DMA_cap = 0; 1397 1398 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1399 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1400 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1401 1402 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1403 cp = &sc->pciide_channels[channel]; 1404 if (pciide_chansetup(sc, channel, interface) == 0) 1405 continue; 1406 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1407 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1408 &ctlsize, pciide_pci_intr); 1409 } else { 1410 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1411 channel, &cmdsize, &ctlsize); 1412 } 1413 if (cp->hw_ok == 0) 1414 continue; 1415 /* 1416 * Check to see if something appears to be there. 1417 */ 1418 failreason = NULL; 1419 if (!wdcprobe(&cp->wdc_channel)) { 1420 failreason = "not responding; disabled or no drives?"; 1421 goto next; 1422 } 1423 /* 1424 * Now, make sure it's actually attributable to this PCI IDE 1425 * channel by trying to access the channel again while the 1426 * PCI IDE controller's I/O space is disabled. (If the 1427 * channel no longer appears to be there, it belongs to 1428 * this controller.) YUCK! 1429 */ 1430 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1431 PCI_COMMAND_STATUS_REG); 1432 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1433 csr & ~PCI_COMMAND_IO_ENABLE); 1434 if (wdcprobe(&cp->wdc_channel)) 1435 failreason = "other hardware responding at addresses"; 1436 pci_conf_write(sc->sc_pc, sc->sc_tag, 1437 PCI_COMMAND_STATUS_REG, csr); 1438 next: 1439 if (failreason) { 1440 printf("%s: %s channel ignored (%s)\n", 1441 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1442 failreason); 1443 cp->hw_ok = 0; 1444 bus_space_unmap(cp->wdc_channel.cmd_iot, 1445 cp->wdc_channel.cmd_ioh, cmdsize); 1446 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1447 bus_space_unmap(cp->wdc_channel.ctl_iot, 1448 cp->ctl_baseioh, ctlsize); 1449 else 1450 bus_space_unmap(cp->wdc_channel.ctl_iot, 1451 cp->wdc_channel.ctl_ioh, ctlsize); 1452 } else { 1453 pciide_map_compat_intr(pa, cp, channel, interface); 1454 } 1455 if (cp->hw_ok) { 1456 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1457 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1458 wdcattach(&cp->wdc_channel); 1459 } 1460 } 1461 1462 if (sc->sc_dma_ok == 0) 1463 return; 1464 1465 /* Allocate DMA maps */ 1466 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1467 idedma_ctl = 0; 1468 cp = &sc->pciide_channels[channel]; 1469 for (drive = 0; drive < 2; drive++) { 1470 drvp = &cp->wdc_channel.ch_drive[drive]; 1471 /* If no drive, skip */ 1472 if ((drvp->drive_flags & DRIVE) == 0) 1473 continue; 1474 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1475 continue; 1476 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1477 /* Abort DMA setup */ 1478 printf("%s:%d:%d: can't allocate DMA maps, " 1479 "using PIO transfers\n", 1480 sc->sc_wdcdev.sc_dev.dv_xname, 1481 channel, drive); 1482 drvp->drive_flags &= ~DRIVE_DMA; 1483 } 1484 printf("%s:%d:%d: using DMA data transfers\n", 1485 sc->sc_wdcdev.sc_dev.dv_xname, 1486 channel, drive); 1487 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1488 } 1489 if (idedma_ctl != 0) { 1490 /* Add software bits in status register */ 1491 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1492 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1493 idedma_ctl); 1494 } 1495 } 1496 } 1497 1498 void 1499 piix_chip_map(sc, pa) 1500 struct pciide_softc *sc; 1501 struct pci_attach_args *pa; 1502 { 1503 struct pciide_channel *cp; 1504 int channel; 1505 u_int32_t idetim; 1506 bus_size_t cmdsize, ctlsize; 1507 1508 if (pciide_chipen(sc, pa) == 0) 1509 return; 1510 1511 printf("%s: bus-master DMA support present", 1512 sc->sc_wdcdev.sc_dev.dv_xname); 1513 pciide_mapreg_dma(sc, pa); 1514 printf("\n"); 1515 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1516 WDC_CAPABILITY_MODE; 1517 if (sc->sc_dma_ok) { 1518 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1519 sc->sc_wdcdev.irqack = pciide_irqack; 1520 switch(sc->sc_pp->ide_product) { 1521 case PCI_PRODUCT_INTEL_82371AB_IDE: 1522 case PCI_PRODUCT_INTEL_82440MX_IDE: 1523 case PCI_PRODUCT_INTEL_82801AA_IDE: 1524 case PCI_PRODUCT_INTEL_82801AB_IDE: 1525 case PCI_PRODUCT_INTEL_82801BA_IDE: 1526 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1527 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1528 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1529 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1530 } 1531 } 1532 sc->sc_wdcdev.PIO_cap = 4; 1533 sc->sc_wdcdev.DMA_cap = 2; 1534 switch(sc->sc_pp->ide_product) { 1535 case PCI_PRODUCT_INTEL_82801AA_IDE: 1536 sc->sc_wdcdev.UDMA_cap = 4; 1537 break; 1538 case PCI_PRODUCT_INTEL_82801BA_IDE: 1539 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1540 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1541 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1542 sc->sc_wdcdev.UDMA_cap = 5; 1543 break; 1544 default: 1545 sc->sc_wdcdev.UDMA_cap = 2; 1546 } 1547 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1548 sc->sc_wdcdev.set_modes = piix_setup_channel; 1549 else 1550 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1551 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1552 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1553 1554 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1555 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1556 DEBUG_PROBE); 1557 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1558 WDCDEBUG_PRINT((", sidetim=0x%x", 1559 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1560 DEBUG_PROBE); 1561 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1562 WDCDEBUG_PRINT((", udamreg 0x%x", 1563 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1564 DEBUG_PROBE); 1565 } 1566 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1567 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1568 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1569 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1570 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1571 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1572 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1573 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1574 DEBUG_PROBE); 1575 } 1576 1577 } 1578 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1579 1580 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1581 cp = &sc->pciide_channels[channel]; 1582 /* PIIX is compat-only */ 1583 if (pciide_chansetup(sc, channel, 0) == 0) 1584 continue; 1585 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1586 if ((PIIX_IDETIM_READ(idetim, channel) & 1587 PIIX_IDETIM_IDE) == 0) { 1588 printf("%s: %s channel ignored (disabled)\n", 1589 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1590 continue; 1591 } 1592 /* PIIX are compat-only pciide devices */ 1593 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1594 if (cp->hw_ok == 0) 1595 continue; 1596 if (pciide_chan_candisable(cp)) { 1597 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1598 channel); 1599 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1600 idetim); 1601 } 1602 pciide_map_compat_intr(pa, cp, channel, 0); 1603 if (cp->hw_ok == 0) 1604 continue; 1605 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1606 } 1607 1608 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1609 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1610 DEBUG_PROBE); 1611 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1612 WDCDEBUG_PRINT((", sidetim=0x%x", 1613 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1614 DEBUG_PROBE); 1615 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1616 WDCDEBUG_PRINT((", udamreg 0x%x", 1617 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1618 DEBUG_PROBE); 1619 } 1620 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1621 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1622 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1623 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1624 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1625 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1626 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1627 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1628 DEBUG_PROBE); 1629 } 1630 } 1631 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1632 } 1633 1634 void 1635 piix_setup_channel(chp) 1636 struct channel_softc *chp; 1637 { 1638 u_int8_t mode[2], drive; 1639 u_int32_t oidetim, idetim, idedma_ctl; 1640 struct pciide_channel *cp = (struct pciide_channel*)chp; 1641 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1642 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1643 1644 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1645 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1646 idedma_ctl = 0; 1647 1648 /* set up new idetim: Enable IDE registers decode */ 1649 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1650 chp->channel); 1651 1652 /* setup DMA */ 1653 pciide_channel_dma_setup(cp); 1654 1655 /* 1656 * Here we have to mess up with drives mode: PIIX can't have 1657 * different timings for master and slave drives. 1658 * We need to find the best combination. 1659 */ 1660 1661 /* If both drives supports DMA, take the lower mode */ 1662 if ((drvp[0].drive_flags & DRIVE_DMA) && 1663 (drvp[1].drive_flags & DRIVE_DMA)) { 1664 mode[0] = mode[1] = 1665 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1666 drvp[0].DMA_mode = mode[0]; 1667 drvp[1].DMA_mode = mode[1]; 1668 goto ok; 1669 } 1670 /* 1671 * If only one drive supports DMA, use its mode, and 1672 * put the other one in PIO mode 0 if mode not compatible 1673 */ 1674 if (drvp[0].drive_flags & DRIVE_DMA) { 1675 mode[0] = drvp[0].DMA_mode; 1676 mode[1] = drvp[1].PIO_mode; 1677 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1678 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1679 mode[1] = drvp[1].PIO_mode = 0; 1680 goto ok; 1681 } 1682 if (drvp[1].drive_flags & DRIVE_DMA) { 1683 mode[1] = drvp[1].DMA_mode; 1684 mode[0] = drvp[0].PIO_mode; 1685 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1686 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1687 mode[0] = drvp[0].PIO_mode = 0; 1688 goto ok; 1689 } 1690 /* 1691 * If both drives are not DMA, takes the lower mode, unless 1692 * one of them is PIO mode < 2 1693 */ 1694 if (drvp[0].PIO_mode < 2) { 1695 mode[0] = drvp[0].PIO_mode = 0; 1696 mode[1] = drvp[1].PIO_mode; 1697 } else if (drvp[1].PIO_mode < 2) { 1698 mode[1] = drvp[1].PIO_mode = 0; 1699 mode[0] = drvp[0].PIO_mode; 1700 } else { 1701 mode[0] = mode[1] = 1702 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1703 drvp[0].PIO_mode = mode[0]; 1704 drvp[1].PIO_mode = mode[1]; 1705 } 1706 ok: /* The modes are setup */ 1707 for (drive = 0; drive < 2; drive++) { 1708 if (drvp[drive].drive_flags & DRIVE_DMA) { 1709 idetim |= piix_setup_idetim_timings( 1710 mode[drive], 1, chp->channel); 1711 goto end; 1712 } 1713 } 1714 /* If we are there, none of the drives are DMA */ 1715 if (mode[0] >= 2) 1716 idetim |= piix_setup_idetim_timings( 1717 mode[0], 0, chp->channel); 1718 else 1719 idetim |= piix_setup_idetim_timings( 1720 mode[1], 0, chp->channel); 1721 end: /* 1722 * timing mode is now set up in the controller. Enable 1723 * it per-drive 1724 */ 1725 for (drive = 0; drive < 2; drive++) { 1726 /* If no drive, skip */ 1727 if ((drvp[drive].drive_flags & DRIVE) == 0) 1728 continue; 1729 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1730 if (drvp[drive].drive_flags & DRIVE_DMA) 1731 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1732 } 1733 if (idedma_ctl != 0) { 1734 /* Add software bits in status register */ 1735 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1736 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1737 idedma_ctl); 1738 } 1739 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1740 pciide_print_modes(cp); 1741 } 1742 1743 void 1744 piix3_4_setup_channel(chp) 1745 struct channel_softc *chp; 1746 { 1747 struct ata_drive_datas *drvp; 1748 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1749 struct pciide_channel *cp = (struct pciide_channel*)chp; 1750 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1751 int drive; 1752 int channel = chp->channel; 1753 1754 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1755 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1756 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1757 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1758 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1759 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1760 PIIX_SIDETIM_RTC_MASK(channel)); 1761 1762 idedma_ctl = 0; 1763 /* If channel disabled, no need to go further */ 1764 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1765 return; 1766 /* set up new idetim: Enable IDE registers decode */ 1767 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1768 1769 /* setup DMA if needed */ 1770 pciide_channel_dma_setup(cp); 1771 1772 for (drive = 0; drive < 2; drive++) { 1773 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1774 PIIX_UDMATIM_SET(0x3, channel, drive)); 1775 drvp = &chp->ch_drive[drive]; 1776 /* If no drive, skip */ 1777 if ((drvp->drive_flags & DRIVE) == 0) 1778 continue; 1779 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1780 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1781 goto pio; 1782 1783 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1784 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1785 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1786 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1787 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1788 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1789 ideconf |= PIIX_CONFIG_PINGPONG; 1790 } 1791 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1792 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1793 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1794 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2) { 1795 /* setup Ultra/100 */ 1796 if (drvp->UDMA_mode > 2 && 1797 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1798 drvp->UDMA_mode = 2; 1799 if (drvp->UDMA_mode > 4) { 1800 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1801 } else { 1802 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1803 if (drvp->UDMA_mode > 2) { 1804 ideconf |= PIIX_CONFIG_UDMA66(channel, 1805 drive); 1806 } else { 1807 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1808 drive); 1809 } 1810 } 1811 } 1812 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1813 /* setup Ultra/66 */ 1814 if (drvp->UDMA_mode > 2 && 1815 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1816 drvp->UDMA_mode = 2; 1817 if (drvp->UDMA_mode > 2) 1818 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1819 else 1820 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1821 } 1822 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1823 (drvp->drive_flags & DRIVE_UDMA)) { 1824 /* use Ultra/DMA */ 1825 drvp->drive_flags &= ~DRIVE_DMA; 1826 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1827 udmareg |= PIIX_UDMATIM_SET( 1828 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1829 } else { 1830 /* use Multiword DMA */ 1831 drvp->drive_flags &= ~DRIVE_UDMA; 1832 if (drive == 0) { 1833 idetim |= piix_setup_idetim_timings( 1834 drvp->DMA_mode, 1, channel); 1835 } else { 1836 sidetim |= piix_setup_sidetim_timings( 1837 drvp->DMA_mode, 1, channel); 1838 idetim =PIIX_IDETIM_SET(idetim, 1839 PIIX_IDETIM_SITRE, channel); 1840 } 1841 } 1842 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1843 1844 pio: /* use PIO mode */ 1845 idetim |= piix_setup_idetim_drvs(drvp); 1846 if (drive == 0) { 1847 idetim |= piix_setup_idetim_timings( 1848 drvp->PIO_mode, 0, channel); 1849 } else { 1850 sidetim |= piix_setup_sidetim_timings( 1851 drvp->PIO_mode, 0, channel); 1852 idetim =PIIX_IDETIM_SET(idetim, 1853 PIIX_IDETIM_SITRE, channel); 1854 } 1855 } 1856 if (idedma_ctl != 0) { 1857 /* Add software bits in status register */ 1858 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1859 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1860 idedma_ctl); 1861 } 1862 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1863 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1864 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1865 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1866 pciide_print_modes(cp); 1867 } 1868 1869 1870 /* setup ISP and RTC fields, based on mode */ 1871 static u_int32_t 1872 piix_setup_idetim_timings(mode, dma, channel) 1873 u_int8_t mode; 1874 u_int8_t dma; 1875 u_int8_t channel; 1876 { 1877 1878 if (dma) 1879 return PIIX_IDETIM_SET(0, 1880 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1881 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1882 channel); 1883 else 1884 return PIIX_IDETIM_SET(0, 1885 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1886 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1887 channel); 1888 } 1889 1890 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1891 static u_int32_t 1892 piix_setup_idetim_drvs(drvp) 1893 struct ata_drive_datas *drvp; 1894 { 1895 u_int32_t ret = 0; 1896 struct channel_softc *chp = drvp->chnl_softc; 1897 u_int8_t channel = chp->channel; 1898 u_int8_t drive = drvp->drive; 1899 1900 /* 1901 * If drive is using UDMA, timings setups are independant 1902 * So just check DMA and PIO here. 1903 */ 1904 if (drvp->drive_flags & DRIVE_DMA) { 1905 /* if mode = DMA mode 0, use compatible timings */ 1906 if ((drvp->drive_flags & DRIVE_DMA) && 1907 drvp->DMA_mode == 0) { 1908 drvp->PIO_mode = 0; 1909 return ret; 1910 } 1911 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1912 /* 1913 * PIO and DMA timings are the same, use fast timings for PIO 1914 * too, else use compat timings. 1915 */ 1916 if ((piix_isp_pio[drvp->PIO_mode] != 1917 piix_isp_dma[drvp->DMA_mode]) || 1918 (piix_rtc_pio[drvp->PIO_mode] != 1919 piix_rtc_dma[drvp->DMA_mode])) 1920 drvp->PIO_mode = 0; 1921 /* if PIO mode <= 2, use compat timings for PIO */ 1922 if (drvp->PIO_mode <= 2) { 1923 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1924 channel); 1925 return ret; 1926 } 1927 } 1928 1929 /* 1930 * Now setup PIO modes. If mode < 2, use compat timings. 1931 * Else enable fast timings. Enable IORDY and prefetch/post 1932 * if PIO mode >= 3. 1933 */ 1934 1935 if (drvp->PIO_mode < 2) 1936 return ret; 1937 1938 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1939 if (drvp->PIO_mode >= 3) { 1940 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1941 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1942 } 1943 return ret; 1944 } 1945 1946 /* setup values in SIDETIM registers, based on mode */ 1947 static u_int32_t 1948 piix_setup_sidetim_timings(mode, dma, channel) 1949 u_int8_t mode; 1950 u_int8_t dma; 1951 u_int8_t channel; 1952 { 1953 if (dma) 1954 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1955 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1956 else 1957 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1958 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1959 } 1960 1961 void 1962 amd7x6_chip_map(sc, pa) 1963 struct pciide_softc *sc; 1964 struct pci_attach_args *pa; 1965 { 1966 struct pciide_channel *cp; 1967 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1968 int channel; 1969 pcireg_t chanenable; 1970 bus_size_t cmdsize, ctlsize; 1971 1972 if (pciide_chipen(sc, pa) == 0) 1973 return; 1974 printf("%s: bus-master DMA support present", 1975 sc->sc_wdcdev.sc_dev.dv_xname); 1976 pciide_mapreg_dma(sc, pa); 1977 printf("\n"); 1978 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1979 WDC_CAPABILITY_MODE; 1980 if (sc->sc_dma_ok) { 1981 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1982 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1983 sc->sc_wdcdev.irqack = pciide_irqack; 1984 } 1985 sc->sc_wdcdev.PIO_cap = 4; 1986 sc->sc_wdcdev.DMA_cap = 2; 1987 1988 switch (sc->sc_pp->ide_product) { 1989 case PCI_PRODUCT_AMD_PBC766_IDE: 1990 case PCI_PRODUCT_AMD_PBC768_IDE: 1991 case PCI_PRODUCT_AMD_PBC8111_IDE: 1992 sc->sc_wdcdev.UDMA_cap = 5; 1993 break; 1994 default: 1995 sc->sc_wdcdev.UDMA_cap = 4; 1996 } 1997 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1998 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1999 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2000 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 2001 2002 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 2003 DEBUG_PROBE); 2004 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2005 cp = &sc->pciide_channels[channel]; 2006 if (pciide_chansetup(sc, channel, interface) == 0) 2007 continue; 2008 2009 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 2010 printf("%s: %s channel ignored (disabled)\n", 2011 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2012 continue; 2013 } 2014 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2015 pciide_pci_intr); 2016 2017 if (pciide_chan_candisable(cp)) 2018 chanenable &= ~AMD7X6_CHAN_EN(channel); 2019 pciide_map_compat_intr(pa, cp, channel, interface); 2020 if (cp->hw_ok == 0) 2021 continue; 2022 2023 amd7x6_setup_channel(&cp->wdc_channel); 2024 } 2025 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 2026 chanenable); 2027 return; 2028 } 2029 2030 void 2031 amd7x6_setup_channel(chp) 2032 struct channel_softc *chp; 2033 { 2034 u_int32_t udmatim_reg, datatim_reg; 2035 u_int8_t idedma_ctl; 2036 int mode, drive; 2037 struct ata_drive_datas *drvp; 2038 struct pciide_channel *cp = (struct pciide_channel*)chp; 2039 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2040 #ifndef PCIIDE_AMD756_ENABLEDMA 2041 int rev = PCI_REVISION( 2042 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2043 #endif 2044 2045 idedma_ctl = 0; 2046 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 2047 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 2048 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2049 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2050 2051 /* setup DMA if needed */ 2052 pciide_channel_dma_setup(cp); 2053 2054 for (drive = 0; drive < 2; drive++) { 2055 drvp = &chp->ch_drive[drive]; 2056 /* If no drive, skip */ 2057 if ((drvp->drive_flags & DRIVE) == 0) 2058 continue; 2059 /* add timing values, setup DMA if needed */ 2060 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2061 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2062 mode = drvp->PIO_mode; 2063 goto pio; 2064 } 2065 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2066 (drvp->drive_flags & DRIVE_UDMA)) { 2067 /* use Ultra/DMA */ 2068 drvp->drive_flags &= ~DRIVE_DMA; 2069 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2070 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2071 AMD7X6_UDMA_TIME(chp->channel, drive, 2072 amd7x6_udma_tim[drvp->UDMA_mode]); 2073 /* can use PIO timings, MW DMA unused */ 2074 mode = drvp->PIO_mode; 2075 } else { 2076 /* use Multiword DMA, but only if revision is OK */ 2077 drvp->drive_flags &= ~DRIVE_UDMA; 2078 #ifndef PCIIDE_AMD756_ENABLEDMA 2079 /* 2080 * The workaround doesn't seem to be necessary 2081 * with all drives, so it can be disabled by 2082 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2083 * triggered. 2084 */ 2085 if (sc->sc_pp->ide_product == 2086 PCI_PRODUCT_AMD_PBC756_IDE && 2087 AMD756_CHIPREV_DISABLEDMA(rev)) { 2088 printf("%s:%d:%d: multi-word DMA disabled due " 2089 "to chip revision\n", 2090 sc->sc_wdcdev.sc_dev.dv_xname, 2091 chp->channel, drive); 2092 mode = drvp->PIO_mode; 2093 drvp->drive_flags &= ~DRIVE_DMA; 2094 goto pio; 2095 } 2096 #endif 2097 /* mode = min(pio, dma+2) */ 2098 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2099 mode = drvp->PIO_mode; 2100 else 2101 mode = drvp->DMA_mode + 2; 2102 } 2103 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2104 2105 pio: /* setup PIO mode */ 2106 if (mode <= 2) { 2107 drvp->DMA_mode = 0; 2108 drvp->PIO_mode = 0; 2109 mode = 0; 2110 } else { 2111 drvp->PIO_mode = mode; 2112 drvp->DMA_mode = mode - 2; 2113 } 2114 datatim_reg |= 2115 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2116 amd7x6_pio_set[mode]) | 2117 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2118 amd7x6_pio_rec[mode]); 2119 } 2120 if (idedma_ctl != 0) { 2121 /* Add software bits in status register */ 2122 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2123 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2124 idedma_ctl); 2125 } 2126 pciide_print_modes(cp); 2127 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2128 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2129 } 2130 2131 void 2132 apollo_chip_map(sc, pa) 2133 struct pciide_softc *sc; 2134 struct pci_attach_args *pa; 2135 { 2136 struct pciide_channel *cp; 2137 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2138 int channel; 2139 u_int32_t ideconf; 2140 bus_size_t cmdsize, ctlsize; 2141 pcitag_t pcib_tag; 2142 pcireg_t pcib_id, pcib_class; 2143 2144 if (pciide_chipen(sc, pa) == 0) 2145 return; 2146 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2147 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2148 /* and read ID and rev of the ISA bridge */ 2149 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2150 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2151 printf(": VIA Technologies "); 2152 switch (PCI_PRODUCT(pcib_id)) { 2153 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2154 printf("VT82C586 (Apollo VP) "); 2155 if(PCI_REVISION(pcib_class) >= 0x02) { 2156 printf("ATA33 controller\n"); 2157 sc->sc_wdcdev.UDMA_cap = 2; 2158 } else { 2159 printf("controller\n"); 2160 sc->sc_wdcdev.UDMA_cap = 0; 2161 } 2162 break; 2163 case PCI_PRODUCT_VIATECH_VT82C596A: 2164 printf("VT82C596A (Apollo Pro) "); 2165 if (PCI_REVISION(pcib_class) >= 0x12) { 2166 printf("ATA66 controller\n"); 2167 sc->sc_wdcdev.UDMA_cap = 4; 2168 } else { 2169 printf("ATA33 controller\n"); 2170 sc->sc_wdcdev.UDMA_cap = 2; 2171 } 2172 break; 2173 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2174 printf("VT82C686A (Apollo KX133) "); 2175 if (PCI_REVISION(pcib_class) >= 0x40) { 2176 printf("ATA100 controller\n"); 2177 sc->sc_wdcdev.UDMA_cap = 5; 2178 } else { 2179 printf("ATA66 controller\n"); 2180 sc->sc_wdcdev.UDMA_cap = 4; 2181 } 2182 break; 2183 case PCI_PRODUCT_VIATECH_VT8231: 2184 printf("VT8231 ATA100 controller\n"); 2185 sc->sc_wdcdev.UDMA_cap = 5; 2186 break; 2187 case PCI_PRODUCT_VIATECH_VT8233: 2188 printf("VT8233 ATA100 controller\n"); 2189 sc->sc_wdcdev.UDMA_cap = 5; 2190 break; 2191 case PCI_PRODUCT_VIATECH_VT8233A: 2192 printf("VT8233A ATA133 controller\n"); 2193 /* XXX use ATA100 untill ATA133 is supported */ 2194 sc->sc_wdcdev.UDMA_cap = 5; 2195 break; 2196 default: 2197 printf("unknown ATA controller\n"); 2198 sc->sc_wdcdev.UDMA_cap = 0; 2199 } 2200 2201 printf("%s: bus-master DMA support present", 2202 sc->sc_wdcdev.sc_dev.dv_xname); 2203 pciide_mapreg_dma(sc, pa); 2204 printf("\n"); 2205 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2206 WDC_CAPABILITY_MODE; 2207 if (sc->sc_dma_ok) { 2208 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2209 sc->sc_wdcdev.irqack = pciide_irqack; 2210 if (sc->sc_wdcdev.UDMA_cap > 0) 2211 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2212 } 2213 sc->sc_wdcdev.PIO_cap = 4; 2214 sc->sc_wdcdev.DMA_cap = 2; 2215 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2216 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2217 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2218 2219 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2220 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2221 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2222 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2223 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2224 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2225 DEBUG_PROBE); 2226 2227 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2228 cp = &sc->pciide_channels[channel]; 2229 if (pciide_chansetup(sc, channel, interface) == 0) 2230 continue; 2231 2232 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2233 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2234 printf("%s: %s channel ignored (disabled)\n", 2235 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2236 continue; 2237 } 2238 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2239 pciide_pci_intr); 2240 if (cp->hw_ok == 0) 2241 continue; 2242 if (pciide_chan_candisable(cp)) { 2243 ideconf &= ~APO_IDECONF_EN(channel); 2244 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2245 ideconf); 2246 } 2247 pciide_map_compat_intr(pa, cp, channel, interface); 2248 2249 if (cp->hw_ok == 0) 2250 continue; 2251 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2252 } 2253 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2254 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2255 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2256 } 2257 2258 void 2259 apollo_setup_channel(chp) 2260 struct channel_softc *chp; 2261 { 2262 u_int32_t udmatim_reg, datatim_reg; 2263 u_int8_t idedma_ctl; 2264 int mode, drive; 2265 struct ata_drive_datas *drvp; 2266 struct pciide_channel *cp = (struct pciide_channel*)chp; 2267 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2268 2269 idedma_ctl = 0; 2270 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2271 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2272 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2273 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2274 2275 /* setup DMA if needed */ 2276 pciide_channel_dma_setup(cp); 2277 2278 for (drive = 0; drive < 2; drive++) { 2279 drvp = &chp->ch_drive[drive]; 2280 /* If no drive, skip */ 2281 if ((drvp->drive_flags & DRIVE) == 0) 2282 continue; 2283 /* add timing values, setup DMA if needed */ 2284 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2285 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2286 mode = drvp->PIO_mode; 2287 goto pio; 2288 } 2289 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2290 (drvp->drive_flags & DRIVE_UDMA)) { 2291 /* use Ultra/DMA */ 2292 drvp->drive_flags &= ~DRIVE_DMA; 2293 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2294 APO_UDMA_EN_MTH(chp->channel, drive); 2295 if (sc->sc_wdcdev.UDMA_cap == 5) { 2296 /* 686b */ 2297 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2298 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2299 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2300 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2301 /* 596b or 686a */ 2302 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2303 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2304 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2305 } else { 2306 /* 596a or 586b */ 2307 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2308 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2309 } 2310 /* can use PIO timings, MW DMA unused */ 2311 mode = drvp->PIO_mode; 2312 } else { 2313 /* use Multiword DMA */ 2314 drvp->drive_flags &= ~DRIVE_UDMA; 2315 /* mode = min(pio, dma+2) */ 2316 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2317 mode = drvp->PIO_mode; 2318 else 2319 mode = drvp->DMA_mode + 2; 2320 } 2321 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2322 2323 pio: /* setup PIO mode */ 2324 if (mode <= 2) { 2325 drvp->DMA_mode = 0; 2326 drvp->PIO_mode = 0; 2327 mode = 0; 2328 } else { 2329 drvp->PIO_mode = mode; 2330 drvp->DMA_mode = mode - 2; 2331 } 2332 datatim_reg |= 2333 APO_DATATIM_PULSE(chp->channel, drive, 2334 apollo_pio_set[mode]) | 2335 APO_DATATIM_RECOV(chp->channel, drive, 2336 apollo_pio_rec[mode]); 2337 } 2338 if (idedma_ctl != 0) { 2339 /* Add software bits in status register */ 2340 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2341 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2342 idedma_ctl); 2343 } 2344 pciide_print_modes(cp); 2345 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2346 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2347 } 2348 2349 void 2350 cmd_channel_map(pa, sc, channel) 2351 struct pci_attach_args *pa; 2352 struct pciide_softc *sc; 2353 int channel; 2354 { 2355 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2356 bus_size_t cmdsize, ctlsize; 2357 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2358 int interface, one_channel; 2359 2360 /* 2361 * The 0648/0649 can be told to identify as a RAID controller. 2362 * In this case, we have to fake interface 2363 */ 2364 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2365 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2366 PCIIDE_INTERFACE_SETTABLE(1); 2367 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2368 CMD_CONF_DSA1) 2369 interface |= PCIIDE_INTERFACE_PCI(0) | 2370 PCIIDE_INTERFACE_PCI(1); 2371 } else { 2372 interface = PCI_INTERFACE(pa->pa_class); 2373 } 2374 2375 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2376 cp->name = PCIIDE_CHANNEL_NAME(channel); 2377 cp->wdc_channel.channel = channel; 2378 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2379 2380 /* 2381 * Older CMD64X doesn't have independant channels 2382 */ 2383 switch (sc->sc_pp->ide_product) { 2384 case PCI_PRODUCT_CMDTECH_649: 2385 one_channel = 0; 2386 break; 2387 default: 2388 one_channel = 1; 2389 break; 2390 } 2391 2392 if (channel > 0 && one_channel) { 2393 cp->wdc_channel.ch_queue = 2394 sc->pciide_channels[0].wdc_channel.ch_queue; 2395 } else { 2396 cp->wdc_channel.ch_queue = 2397 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2398 } 2399 if (cp->wdc_channel.ch_queue == NULL) { 2400 printf("%s %s channel: " 2401 "can't allocate memory for command queue", 2402 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2403 return; 2404 } 2405 2406 printf("%s: %s channel %s to %s mode\n", 2407 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2408 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2409 "configured" : "wired", 2410 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2411 "native-PCI" : "compatibility"); 2412 2413 /* 2414 * with a CMD PCI64x, if we get here, the first channel is enabled: 2415 * there's no way to disable the first channel without disabling 2416 * the whole device 2417 */ 2418 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2419 printf("%s: %s channel ignored (disabled)\n", 2420 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2421 return; 2422 } 2423 2424 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2425 if (cp->hw_ok == 0) 2426 return; 2427 if (channel == 1) { 2428 if (pciide_chan_candisable(cp)) { 2429 ctrl &= ~CMD_CTRL_2PORT; 2430 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2431 CMD_CTRL, ctrl); 2432 } 2433 } 2434 pciide_map_compat_intr(pa, cp, channel, interface); 2435 } 2436 2437 int 2438 cmd_pci_intr(arg) 2439 void *arg; 2440 { 2441 struct pciide_softc *sc = arg; 2442 struct pciide_channel *cp; 2443 struct channel_softc *wdc_cp; 2444 int i, rv, crv; 2445 u_int32_t priirq, secirq; 2446 2447 rv = 0; 2448 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2449 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2450 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2451 cp = &sc->pciide_channels[i]; 2452 wdc_cp = &cp->wdc_channel; 2453 /* If a compat channel skip. */ 2454 if (cp->compat) 2455 continue; 2456 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2457 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2458 crv = wdcintr(wdc_cp); 2459 if (crv == 0) 2460 printf("%s:%d: bogus intr\n", 2461 sc->sc_wdcdev.sc_dev.dv_xname, i); 2462 else 2463 rv = 1; 2464 } 2465 } 2466 return rv; 2467 } 2468 2469 void 2470 cmd_chip_map(sc, pa) 2471 struct pciide_softc *sc; 2472 struct pci_attach_args *pa; 2473 { 2474 int channel; 2475 2476 /* 2477 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2478 * and base adresses registers can be disabled at 2479 * hardware level. In this case, the device is wired 2480 * in compat mode and its first channel is always enabled, 2481 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2482 * In fact, it seems that the first channel of the CMD PCI0640 2483 * can't be disabled. 2484 */ 2485 2486 #ifdef PCIIDE_CMD064x_DISABLE 2487 if (pciide_chipen(sc, pa) == 0) 2488 return; 2489 #endif 2490 2491 printf("%s: hardware does not support DMA\n", 2492 sc->sc_wdcdev.sc_dev.dv_xname); 2493 sc->sc_dma_ok = 0; 2494 2495 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2496 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2497 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2498 2499 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2500 cmd_channel_map(pa, sc, channel); 2501 } 2502 } 2503 2504 void 2505 cmd0643_9_chip_map(sc, pa) 2506 struct pciide_softc *sc; 2507 struct pci_attach_args *pa; 2508 { 2509 struct pciide_channel *cp; 2510 int channel; 2511 pcireg_t rev = PCI_REVISION(pa->pa_class); 2512 2513 /* 2514 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2515 * and base adresses registers can be disabled at 2516 * hardware level. In this case, the device is wired 2517 * in compat mode and its first channel is always enabled, 2518 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2519 * In fact, it seems that the first channel of the CMD PCI0640 2520 * can't be disabled. 2521 */ 2522 2523 #ifdef PCIIDE_CMD064x_DISABLE 2524 if (pciide_chipen(sc, pa) == 0) 2525 return; 2526 #endif 2527 printf("%s: bus-master DMA support present", 2528 sc->sc_wdcdev.sc_dev.dv_xname); 2529 pciide_mapreg_dma(sc, pa); 2530 printf("\n"); 2531 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2532 WDC_CAPABILITY_MODE; 2533 if (sc->sc_dma_ok) { 2534 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2535 switch (sc->sc_pp->ide_product) { 2536 case PCI_PRODUCT_CMDTECH_649: 2537 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2538 sc->sc_wdcdev.UDMA_cap = 5; 2539 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2540 break; 2541 case PCI_PRODUCT_CMDTECH_648: 2542 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2543 sc->sc_wdcdev.UDMA_cap = 4; 2544 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2545 break; 2546 case PCI_PRODUCT_CMDTECH_646: 2547 if (rev >= CMD0646U2_REV) { 2548 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2549 sc->sc_wdcdev.UDMA_cap = 2; 2550 } else if (rev >= CMD0646U_REV) { 2551 /* 2552 * Linux's driver claims that the 646U is broken 2553 * with UDMA. Only enable it if we know what we're 2554 * doing 2555 */ 2556 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2557 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2558 sc->sc_wdcdev.UDMA_cap = 2; 2559 #endif 2560 /* explicitly disable UDMA */ 2561 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2562 CMD_UDMATIM(0), 0); 2563 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2564 CMD_UDMATIM(1), 0); 2565 } 2566 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2567 break; 2568 default: 2569 sc->sc_wdcdev.irqack = pciide_irqack; 2570 } 2571 } 2572 2573 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2574 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2575 sc->sc_wdcdev.PIO_cap = 4; 2576 sc->sc_wdcdev.DMA_cap = 2; 2577 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2578 2579 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2580 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2581 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2582 DEBUG_PROBE); 2583 2584 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2585 cp = &sc->pciide_channels[channel]; 2586 cmd_channel_map(pa, sc, channel); 2587 if (cp->hw_ok == 0) 2588 continue; 2589 cmd0643_9_setup_channel(&cp->wdc_channel); 2590 } 2591 /* 2592 * note - this also makes sure we clear the irq disable and reset 2593 * bits 2594 */ 2595 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2596 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2597 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2598 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2599 DEBUG_PROBE); 2600 } 2601 2602 void 2603 cmd0643_9_setup_channel(chp) 2604 struct channel_softc *chp; 2605 { 2606 struct ata_drive_datas *drvp; 2607 u_int8_t tim; 2608 u_int32_t idedma_ctl, udma_reg; 2609 int drive; 2610 struct pciide_channel *cp = (struct pciide_channel*)chp; 2611 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2612 2613 idedma_ctl = 0; 2614 /* setup DMA if needed */ 2615 pciide_channel_dma_setup(cp); 2616 2617 for (drive = 0; drive < 2; drive++) { 2618 drvp = &chp->ch_drive[drive]; 2619 /* If no drive, skip */ 2620 if ((drvp->drive_flags & DRIVE) == 0) 2621 continue; 2622 /* add timing values, setup DMA if needed */ 2623 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2624 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2625 if (drvp->drive_flags & DRIVE_UDMA) { 2626 /* UltraDMA on a 646U2, 0648 or 0649 */ 2627 drvp->drive_flags &= ~DRIVE_DMA; 2628 udma_reg = pciide_pci_read(sc->sc_pc, 2629 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2630 if (drvp->UDMA_mode > 2 && 2631 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2632 CMD_BICSR) & 2633 CMD_BICSR_80(chp->channel)) == 0) 2634 drvp->UDMA_mode = 2; 2635 if (drvp->UDMA_mode > 2) 2636 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2637 else if (sc->sc_wdcdev.UDMA_cap > 2) 2638 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2639 udma_reg |= CMD_UDMATIM_UDMA(drive); 2640 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2641 CMD_UDMATIM_TIM_OFF(drive)); 2642 udma_reg |= 2643 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2644 CMD_UDMATIM_TIM_OFF(drive)); 2645 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2646 CMD_UDMATIM(chp->channel), udma_reg); 2647 } else { 2648 /* 2649 * use Multiword DMA. 2650 * Timings will be used for both PIO and DMA, 2651 * so adjust DMA mode if needed 2652 * if we have a 0646U2/8/9, turn off UDMA 2653 */ 2654 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2655 udma_reg = pciide_pci_read(sc->sc_pc, 2656 sc->sc_tag, 2657 CMD_UDMATIM(chp->channel)); 2658 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2659 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2660 CMD_UDMATIM(chp->channel), 2661 udma_reg); 2662 } 2663 if (drvp->PIO_mode >= 3 && 2664 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2665 drvp->DMA_mode = drvp->PIO_mode - 2; 2666 } 2667 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2668 } 2669 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2670 } 2671 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2672 CMD_DATA_TIM(chp->channel, drive), tim); 2673 } 2674 if (idedma_ctl != 0) { 2675 /* Add software bits in status register */ 2676 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2677 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2678 idedma_ctl); 2679 } 2680 pciide_print_modes(cp); 2681 } 2682 2683 void 2684 cmd646_9_irqack(chp) 2685 struct channel_softc *chp; 2686 { 2687 u_int32_t priirq, secirq; 2688 struct pciide_channel *cp = (struct pciide_channel*)chp; 2689 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2690 2691 if (chp->channel == 0) { 2692 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2693 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2694 } else { 2695 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2696 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2697 } 2698 pciide_irqack(chp); 2699 } 2700 2701 void 2702 cmd680_chip_map(sc, pa) 2703 struct pciide_softc *sc; 2704 struct pci_attach_args *pa; 2705 { 2706 struct pciide_channel *cp; 2707 int channel; 2708 2709 if (pciide_chipen(sc, pa) == 0) 2710 return; 2711 printf("%s: bus-master DMA support present", 2712 sc->sc_wdcdev.sc_dev.dv_xname); 2713 pciide_mapreg_dma(sc, pa); 2714 printf("\n"); 2715 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2716 WDC_CAPABILITY_MODE; 2717 if (sc->sc_dma_ok) { 2718 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2719 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2720 sc->sc_wdcdev.UDMA_cap = 6; 2721 sc->sc_wdcdev.irqack = pciide_irqack; 2722 } 2723 2724 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2725 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2726 sc->sc_wdcdev.PIO_cap = 4; 2727 sc->sc_wdcdev.DMA_cap = 2; 2728 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 2729 2730 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 2731 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 2732 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 2733 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 2734 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2735 cp = &sc->pciide_channels[channel]; 2736 cmd680_channel_map(pa, sc, channel); 2737 if (cp->hw_ok == 0) 2738 continue; 2739 cmd680_setup_channel(&cp->wdc_channel); 2740 } 2741 } 2742 2743 void 2744 cmd680_channel_map(pa, sc, channel) 2745 struct pci_attach_args *pa; 2746 struct pciide_softc *sc; 2747 int channel; 2748 { 2749 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2750 bus_size_t cmdsize, ctlsize; 2751 int interface, i, reg; 2752 static const u_int8_t init_val[] = 2753 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 2754 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 2755 2756 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2757 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2758 PCIIDE_INTERFACE_SETTABLE(1); 2759 interface |= PCIIDE_INTERFACE_PCI(0) | 2760 PCIIDE_INTERFACE_PCI(1); 2761 } else { 2762 interface = PCI_INTERFACE(pa->pa_class); 2763 } 2764 2765 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2766 cp->name = PCIIDE_CHANNEL_NAME(channel); 2767 cp->wdc_channel.channel = channel; 2768 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2769 2770 cp->wdc_channel.ch_queue = 2771 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2772 if (cp->wdc_channel.ch_queue == NULL) { 2773 printf("%s %s channel: " 2774 "can't allocate memory for command queue", 2775 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2776 return; 2777 } 2778 2779 /* XXX */ 2780 reg = 0xa2 + channel * 16; 2781 for (i = 0; i < sizeof(init_val); i++) 2782 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 2783 2784 printf("%s: %s channel %s to %s mode\n", 2785 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2786 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2787 "configured" : "wired", 2788 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2789 "native-PCI" : "compatibility"); 2790 2791 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 2792 if (cp->hw_ok == 0) 2793 return; 2794 pciide_map_compat_intr(pa, cp, channel, interface); 2795 } 2796 2797 void 2798 cmd680_setup_channel(chp) 2799 struct channel_softc *chp; 2800 { 2801 struct ata_drive_datas *drvp; 2802 u_int8_t mode, off, scsc; 2803 u_int16_t val; 2804 u_int32_t idedma_ctl; 2805 int drive; 2806 struct pciide_channel *cp = (struct pciide_channel*)chp; 2807 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2808 pci_chipset_tag_t pc = sc->sc_pc; 2809 pcitag_t pa = sc->sc_tag; 2810 static const u_int8_t udma2_tbl[] = 2811 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 2812 static const u_int8_t udma_tbl[] = 2813 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 2814 static const u_int16_t dma_tbl[] = 2815 { 0x2208, 0x10c2, 0x10c1 }; 2816 static const u_int16_t pio_tbl[] = 2817 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 2818 2819 idedma_ctl = 0; 2820 pciide_channel_dma_setup(cp); 2821 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 2822 2823 for (drive = 0; drive < 2; drive++) { 2824 drvp = &chp->ch_drive[drive]; 2825 /* If no drive, skip */ 2826 if ((drvp->drive_flags & DRIVE) == 0) 2827 continue; 2828 mode &= ~(0x03 << (drive * 4)); 2829 if (drvp->drive_flags & DRIVE_UDMA) { 2830 drvp->drive_flags &= ~DRIVE_DMA; 2831 off = 0xa0 + chp->channel * 16; 2832 if (drvp->UDMA_mode > 2 && 2833 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 2834 drvp->UDMA_mode = 2; 2835 scsc = pciide_pci_read(pc, pa, 0x8a); 2836 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 2837 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 2838 scsc = pciide_pci_read(pc, pa, 0x8a); 2839 if ((scsc & 0x30) == 0) 2840 drvp->UDMA_mode = 5; 2841 } 2842 mode |= 0x03 << (drive * 4); 2843 off = 0xac + chp->channel * 16 + drive * 2; 2844 val = pciide_pci_read(pc, pa, off) & ~0x3f; 2845 if (scsc & 0x30) 2846 val |= udma2_tbl[drvp->UDMA_mode]; 2847 else 2848 val |= udma_tbl[drvp->UDMA_mode]; 2849 pciide_pci_write(pc, pa, off, val); 2850 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2851 } else if (drvp->drive_flags & DRIVE_DMA) { 2852 mode |= 0x02 << (drive * 4); 2853 off = 0xa8 + chp->channel * 16 + drive * 2; 2854 val = dma_tbl[drvp->DMA_mode]; 2855 pciide_pci_write(pc, pa, off, val & 0xff); 2856 pciide_pci_write(pc, pa, off, val >> 8); 2857 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2858 } else { 2859 mode |= 0x01 << (drive * 4); 2860 off = 0xa4 + chp->channel * 16 + drive * 2; 2861 val = pio_tbl[drvp->PIO_mode]; 2862 pciide_pci_write(pc, pa, off, val & 0xff); 2863 pciide_pci_write(pc, pa, off, val >> 8); 2864 } 2865 } 2866 2867 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 2868 if (idedma_ctl != 0) { 2869 /* Add software bits in status register */ 2870 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2871 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2872 idedma_ctl); 2873 } 2874 pciide_print_modes(cp); 2875 } 2876 2877 void 2878 cy693_chip_map(sc, pa) 2879 struct pciide_softc *sc; 2880 struct pci_attach_args *pa; 2881 { 2882 struct pciide_channel *cp; 2883 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2884 bus_size_t cmdsize, ctlsize; 2885 2886 if (pciide_chipen(sc, pa) == 0) 2887 return; 2888 /* 2889 * this chip has 2 PCI IDE functions, one for primary and one for 2890 * secondary. So we need to call pciide_mapregs_compat() with 2891 * the real channel 2892 */ 2893 if (pa->pa_function == 1) { 2894 sc->sc_cy_compatchan = 0; 2895 } else if (pa->pa_function == 2) { 2896 sc->sc_cy_compatchan = 1; 2897 } else { 2898 printf("%s: unexpected PCI function %d\n", 2899 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2900 return; 2901 } 2902 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2903 printf("%s: bus-master DMA support present", 2904 sc->sc_wdcdev.sc_dev.dv_xname); 2905 pciide_mapreg_dma(sc, pa); 2906 } else { 2907 printf("%s: hardware does not support DMA", 2908 sc->sc_wdcdev.sc_dev.dv_xname); 2909 sc->sc_dma_ok = 0; 2910 } 2911 printf("\n"); 2912 2913 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2914 if (sc->sc_cy_handle == NULL) { 2915 printf("%s: unable to map hyperCache control registers\n", 2916 sc->sc_wdcdev.sc_dev.dv_xname); 2917 sc->sc_dma_ok = 0; 2918 } 2919 2920 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2921 WDC_CAPABILITY_MODE; 2922 if (sc->sc_dma_ok) { 2923 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2924 sc->sc_wdcdev.irqack = pciide_irqack; 2925 } 2926 sc->sc_wdcdev.PIO_cap = 4; 2927 sc->sc_wdcdev.DMA_cap = 2; 2928 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2929 2930 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2931 sc->sc_wdcdev.nchannels = 1; 2932 2933 /* Only one channel for this chip; if we are here it's enabled */ 2934 cp = &sc->pciide_channels[0]; 2935 sc->wdc_chanarray[0] = &cp->wdc_channel; 2936 cp->name = PCIIDE_CHANNEL_NAME(0); 2937 cp->wdc_channel.channel = 0; 2938 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2939 cp->wdc_channel.ch_queue = 2940 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2941 if (cp->wdc_channel.ch_queue == NULL) { 2942 printf("%s primary channel: " 2943 "can't allocate memory for command queue", 2944 sc->sc_wdcdev.sc_dev.dv_xname); 2945 return; 2946 } 2947 printf("%s: primary channel %s to ", 2948 sc->sc_wdcdev.sc_dev.dv_xname, 2949 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2950 "configured" : "wired"); 2951 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2952 printf("native-PCI"); 2953 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2954 pciide_pci_intr); 2955 } else { 2956 printf("compatibility"); 2957 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2958 &cmdsize, &ctlsize); 2959 } 2960 printf(" mode\n"); 2961 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2962 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2963 wdcattach(&cp->wdc_channel); 2964 if (pciide_chan_candisable(cp)) { 2965 pci_conf_write(sc->sc_pc, sc->sc_tag, 2966 PCI_COMMAND_STATUS_REG, 0); 2967 } 2968 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2969 if (cp->hw_ok == 0) 2970 return; 2971 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2972 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2973 cy693_setup_channel(&cp->wdc_channel); 2974 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2975 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2976 } 2977 2978 void 2979 cy693_setup_channel(chp) 2980 struct channel_softc *chp; 2981 { 2982 struct ata_drive_datas *drvp; 2983 int drive; 2984 u_int32_t cy_cmd_ctrl; 2985 u_int32_t idedma_ctl; 2986 struct pciide_channel *cp = (struct pciide_channel*)chp; 2987 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2988 int dma_mode = -1; 2989 2990 cy_cmd_ctrl = idedma_ctl = 0; 2991 2992 /* setup DMA if needed */ 2993 pciide_channel_dma_setup(cp); 2994 2995 for (drive = 0; drive < 2; drive++) { 2996 drvp = &chp->ch_drive[drive]; 2997 /* If no drive, skip */ 2998 if ((drvp->drive_flags & DRIVE) == 0) 2999 continue; 3000 /* add timing values, setup DMA if needed */ 3001 if (drvp->drive_flags & DRIVE_DMA) { 3002 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3003 /* use Multiword DMA */ 3004 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 3005 dma_mode = drvp->DMA_mode; 3006 } 3007 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3008 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 3009 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3010 CY_CMD_CTRL_IOW_REC_OFF(drive)); 3011 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3012 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 3013 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3014 CY_CMD_CTRL_IOR_REC_OFF(drive)); 3015 } 3016 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 3017 chp->ch_drive[0].DMA_mode = dma_mode; 3018 chp->ch_drive[1].DMA_mode = dma_mode; 3019 3020 if (dma_mode == -1) 3021 dma_mode = 0; 3022 3023 if (sc->sc_cy_handle != NULL) { 3024 /* Note: `multiple' is implied. */ 3025 cy82c693_write(sc->sc_cy_handle, 3026 (sc->sc_cy_compatchan == 0) ? 3027 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 3028 } 3029 3030 pciide_print_modes(cp); 3031 3032 if (idedma_ctl != 0) { 3033 /* Add software bits in status register */ 3034 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3035 IDEDMA_CTL, idedma_ctl); 3036 } 3037 } 3038 3039 static int 3040 sis_hostbr_match(pa) 3041 struct pci_attach_args *pa; 3042 { 3043 return ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) && 3044 ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_645) || 3045 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_650) || 3046 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_730) || 3047 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_735))); 3048 } 3049 3050 void 3051 sis_chip_map(sc, pa) 3052 struct pciide_softc *sc; 3053 struct pci_attach_args *pa; 3054 { 3055 struct pciide_channel *cp; 3056 int channel; 3057 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 3058 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3059 pcireg_t rev = PCI_REVISION(pa->pa_class); 3060 bus_size_t cmdsize, ctlsize; 3061 pcitag_t pchb_tag; 3062 pcireg_t pchb_id, pchb_class; 3063 3064 if (pciide_chipen(sc, pa) == 0) 3065 return; 3066 printf("%s: bus-master DMA support present", 3067 sc->sc_wdcdev.sc_dev.dv_xname); 3068 pciide_mapreg_dma(sc, pa); 3069 printf("\n"); 3070 3071 /* get a PCI tag for the host bridge (function 0 of the same device) */ 3072 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 3073 /* and read ID and rev of the ISA bridge */ 3074 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 3075 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 3076 3077 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3078 WDC_CAPABILITY_MODE; 3079 if (sc->sc_dma_ok) { 3080 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3081 sc->sc_wdcdev.irqack = pciide_irqack; 3082 /* 3083 * controllers associated to a rev 0x2 530 Host to PCI Bridge 3084 * have problems with UDMA (info provided by Christos) 3085 */ 3086 if (rev >= 0xd0 && 3087 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 3088 PCI_REVISION(pchb_class) >= 0x03)) 3089 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3090 } 3091 3092 sc->sc_wdcdev.PIO_cap = 4; 3093 sc->sc_wdcdev.DMA_cap = 2; 3094 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 3095 /* 3096 * Use UDMA/100 on SiS 735 chipset and UDMA/33 on other 3097 * chipsets. 3098 */ 3099 sc->sc_wdcdev.UDMA_cap = 3100 pci_find_device(pa, sis_hostbr_match) ? 5 : 2; 3101 sc->sc_wdcdev.set_modes = sis_setup_channel; 3102 3103 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3104 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3105 3106 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 3107 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 3108 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 3109 3110 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3111 cp = &sc->pciide_channels[channel]; 3112 if (pciide_chansetup(sc, channel, interface) == 0) 3113 continue; 3114 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 3115 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 3116 printf("%s: %s channel ignored (disabled)\n", 3117 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3118 continue; 3119 } 3120 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3121 pciide_pci_intr); 3122 if (cp->hw_ok == 0) 3123 continue; 3124 if (pciide_chan_candisable(cp)) { 3125 if (channel == 0) 3126 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 3127 else 3128 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 3129 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 3130 sis_ctr0); 3131 } 3132 pciide_map_compat_intr(pa, cp, channel, interface); 3133 if (cp->hw_ok == 0) 3134 continue; 3135 sis_setup_channel(&cp->wdc_channel); 3136 } 3137 } 3138 3139 void 3140 sis_setup_channel(chp) 3141 struct channel_softc *chp; 3142 { 3143 struct ata_drive_datas *drvp; 3144 int drive; 3145 u_int32_t sis_tim; 3146 u_int32_t idedma_ctl; 3147 struct pciide_channel *cp = (struct pciide_channel*)chp; 3148 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3149 3150 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 3151 "channel %d 0x%x\n", chp->channel, 3152 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 3153 DEBUG_PROBE); 3154 sis_tim = 0; 3155 idedma_ctl = 0; 3156 /* setup DMA if needed */ 3157 pciide_channel_dma_setup(cp); 3158 3159 for (drive = 0; drive < 2; drive++) { 3160 drvp = &chp->ch_drive[drive]; 3161 /* If no drive, skip */ 3162 if ((drvp->drive_flags & DRIVE) == 0) 3163 continue; 3164 /* add timing values, setup DMA if needed */ 3165 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3166 (drvp->drive_flags & DRIVE_UDMA) == 0) 3167 goto pio; 3168 3169 if (drvp->drive_flags & DRIVE_UDMA) { 3170 /* use Ultra/DMA */ 3171 drvp->drive_flags &= ~DRIVE_DMA; 3172 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 3173 SIS_TIM_UDMA_TIME_OFF(drive); 3174 sis_tim |= SIS_TIM_UDMA_EN(drive); 3175 } else { 3176 /* 3177 * use Multiword DMA 3178 * Timings will be used for both PIO and DMA, 3179 * so adjust DMA mode if needed 3180 */ 3181 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3182 drvp->PIO_mode = drvp->DMA_mode + 2; 3183 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3184 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3185 drvp->PIO_mode - 2 : 0; 3186 if (drvp->DMA_mode == 0) 3187 drvp->PIO_mode = 0; 3188 } 3189 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3190 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 3191 SIS_TIM_ACT_OFF(drive); 3192 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3193 SIS_TIM_REC_OFF(drive); 3194 } 3195 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 3196 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 3197 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 3198 if (idedma_ctl != 0) { 3199 /* Add software bits in status register */ 3200 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3201 IDEDMA_CTL, idedma_ctl); 3202 } 3203 pciide_print_modes(cp); 3204 } 3205 3206 void 3207 acer_chip_map(sc, pa) 3208 struct pciide_softc *sc; 3209 struct pci_attach_args *pa; 3210 { 3211 struct pciide_channel *cp; 3212 int channel; 3213 pcireg_t cr, interface; 3214 bus_size_t cmdsize, ctlsize; 3215 pcireg_t rev = PCI_REVISION(pa->pa_class); 3216 3217 if (pciide_chipen(sc, pa) == 0) 3218 return; 3219 printf("%s: bus-master DMA support present", 3220 sc->sc_wdcdev.sc_dev.dv_xname); 3221 pciide_mapreg_dma(sc, pa); 3222 printf("\n"); 3223 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3224 WDC_CAPABILITY_MODE; 3225 if (sc->sc_dma_ok) { 3226 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3227 if (rev >= 0x20) { 3228 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3229 if (rev >= 0xC4) 3230 sc->sc_wdcdev.UDMA_cap = 5; 3231 else if (rev >= 0xC2) 3232 sc->sc_wdcdev.UDMA_cap = 4; 3233 else 3234 sc->sc_wdcdev.UDMA_cap = 2; 3235 } 3236 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3237 sc->sc_wdcdev.irqack = pciide_irqack; 3238 } 3239 3240 sc->sc_wdcdev.PIO_cap = 4; 3241 sc->sc_wdcdev.DMA_cap = 2; 3242 sc->sc_wdcdev.set_modes = acer_setup_channel; 3243 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3244 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3245 3246 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3247 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3248 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3249 3250 /* Enable "microsoft register bits" R/W. */ 3251 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3252 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3253 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3254 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3255 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3256 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3257 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3258 ~ACER_CHANSTATUSREGS_RO); 3259 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3260 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3261 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3262 /* Don't use cr, re-read the real register content instead */ 3263 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3264 PCI_CLASS_REG)); 3265 3266 /* From linux: enable "Cable Detection" */ 3267 if (rev >= 0xC2) { 3268 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3269 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3270 | ACER_0x4B_CDETECT); 3271 } 3272 3273 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3274 cp = &sc->pciide_channels[channel]; 3275 if (pciide_chansetup(sc, channel, interface) == 0) 3276 continue; 3277 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3278 printf("%s: %s channel ignored (disabled)\n", 3279 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3280 continue; 3281 } 3282 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3283 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3284 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3285 if (cp->hw_ok == 0) 3286 continue; 3287 if (pciide_chan_candisable(cp)) { 3288 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3289 pci_conf_write(sc->sc_pc, sc->sc_tag, 3290 PCI_CLASS_REG, cr); 3291 } 3292 pciide_map_compat_intr(pa, cp, channel, interface); 3293 acer_setup_channel(&cp->wdc_channel); 3294 } 3295 } 3296 3297 void 3298 acer_setup_channel(chp) 3299 struct channel_softc *chp; 3300 { 3301 struct ata_drive_datas *drvp; 3302 int drive; 3303 u_int32_t acer_fifo_udma; 3304 u_int32_t idedma_ctl; 3305 struct pciide_channel *cp = (struct pciide_channel*)chp; 3306 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3307 3308 idedma_ctl = 0; 3309 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3310 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3311 acer_fifo_udma), DEBUG_PROBE); 3312 /* setup DMA if needed */ 3313 pciide_channel_dma_setup(cp); 3314 3315 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3316 DRIVE_UDMA) { /* check 80 pins cable */ 3317 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3318 ACER_0x4A_80PIN(chp->channel)) { 3319 if (chp->ch_drive[0].UDMA_mode > 2) 3320 chp->ch_drive[0].UDMA_mode = 2; 3321 if (chp->ch_drive[1].UDMA_mode > 2) 3322 chp->ch_drive[1].UDMA_mode = 2; 3323 } 3324 } 3325 3326 for (drive = 0; drive < 2; drive++) { 3327 drvp = &chp->ch_drive[drive]; 3328 /* If no drive, skip */ 3329 if ((drvp->drive_flags & DRIVE) == 0) 3330 continue; 3331 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3332 "channel %d drive %d 0x%x\n", chp->channel, drive, 3333 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3334 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3335 /* clear FIFO/DMA mode */ 3336 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3337 ACER_UDMA_EN(chp->channel, drive) | 3338 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3339 3340 /* add timing values, setup DMA if needed */ 3341 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3342 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3343 acer_fifo_udma |= 3344 ACER_FTH_OPL(chp->channel, drive, 0x1); 3345 goto pio; 3346 } 3347 3348 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3349 if (drvp->drive_flags & DRIVE_UDMA) { 3350 /* use Ultra/DMA */ 3351 drvp->drive_flags &= ~DRIVE_DMA; 3352 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3353 acer_fifo_udma |= 3354 ACER_UDMA_TIM(chp->channel, drive, 3355 acer_udma[drvp->UDMA_mode]); 3356 /* XXX disable if one drive < UDMA3 ? */ 3357 if (drvp->UDMA_mode >= 3) { 3358 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3359 ACER_0x4B, 3360 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3361 ACER_0x4B) | ACER_0x4B_UDMA66); 3362 } 3363 } else { 3364 /* 3365 * use Multiword DMA 3366 * Timings will be used for both PIO and DMA, 3367 * so adjust DMA mode if needed 3368 */ 3369 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3370 drvp->PIO_mode = drvp->DMA_mode + 2; 3371 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3372 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3373 drvp->PIO_mode - 2 : 0; 3374 if (drvp->DMA_mode == 0) 3375 drvp->PIO_mode = 0; 3376 } 3377 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3378 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3379 ACER_IDETIM(chp->channel, drive), 3380 acer_pio[drvp->PIO_mode]); 3381 } 3382 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3383 acer_fifo_udma), DEBUG_PROBE); 3384 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3385 if (idedma_ctl != 0) { 3386 /* Add software bits in status register */ 3387 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3388 IDEDMA_CTL, idedma_ctl); 3389 } 3390 pciide_print_modes(cp); 3391 } 3392 3393 int 3394 acer_pci_intr(arg) 3395 void *arg; 3396 { 3397 struct pciide_softc *sc = arg; 3398 struct pciide_channel *cp; 3399 struct channel_softc *wdc_cp; 3400 int i, rv, crv; 3401 u_int32_t chids; 3402 3403 rv = 0; 3404 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3405 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3406 cp = &sc->pciide_channels[i]; 3407 wdc_cp = &cp->wdc_channel; 3408 /* If a compat channel skip. */ 3409 if (cp->compat) 3410 continue; 3411 if (chids & ACER_CHIDS_INT(i)) { 3412 crv = wdcintr(wdc_cp); 3413 if (crv == 0) 3414 printf("%s:%d: bogus intr\n", 3415 sc->sc_wdcdev.sc_dev.dv_xname, i); 3416 else 3417 rv = 1; 3418 } 3419 } 3420 return rv; 3421 } 3422 3423 void 3424 hpt_chip_map(sc, pa) 3425 struct pciide_softc *sc; 3426 struct pci_attach_args *pa; 3427 { 3428 struct pciide_channel *cp; 3429 int i, compatchan, revision; 3430 pcireg_t interface; 3431 bus_size_t cmdsize, ctlsize; 3432 3433 if (pciide_chipen(sc, pa) == 0) 3434 return; 3435 revision = PCI_REVISION(pa->pa_class); 3436 printf(": Triones/Highpoint "); 3437 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3438 printf("HPT374 IDE Controller\n"); 3439 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 3440 if (revision == HPT370_REV) 3441 printf("HPT370 IDE Controller\n"); 3442 else if (revision == HPT370A_REV) 3443 printf("HPT370A IDE Controller\n"); 3444 else if (revision == HPT366_REV) 3445 printf("HPT366 IDE Controller\n"); 3446 else 3447 printf("unknown HPT IDE controller rev %d\n", revision); 3448 } else 3449 printf("unknown HPT IDE controller 0x%x\n", 3450 sc->sc_pp->ide_product); 3451 3452 /* 3453 * when the chip is in native mode it identifies itself as a 3454 * 'misc mass storage'. Fake interface in this case. 3455 */ 3456 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3457 interface = PCI_INTERFACE(pa->pa_class); 3458 } else { 3459 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3460 PCIIDE_INTERFACE_PCI(0); 3461 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3462 (revision == HPT370_REV || revision == HPT370A_REV)) || 3463 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3464 interface |= PCIIDE_INTERFACE_PCI(1); 3465 } 3466 3467 printf("%s: bus-master DMA support present", 3468 sc->sc_wdcdev.sc_dev.dv_xname); 3469 pciide_mapreg_dma(sc, pa); 3470 printf("\n"); 3471 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3472 WDC_CAPABILITY_MODE; 3473 if (sc->sc_dma_ok) { 3474 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3475 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3476 sc->sc_wdcdev.irqack = pciide_irqack; 3477 } 3478 sc->sc_wdcdev.PIO_cap = 4; 3479 sc->sc_wdcdev.DMA_cap = 2; 3480 3481 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3482 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3483 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3484 revision == HPT366_REV) { 3485 sc->sc_wdcdev.UDMA_cap = 4; 3486 /* 3487 * The 366 has 2 PCI IDE functions, one for primary and one 3488 * for secondary. So we need to call pciide_mapregs_compat() 3489 * with the real channel 3490 */ 3491 if (pa->pa_function == 0) { 3492 compatchan = 0; 3493 } else if (pa->pa_function == 1) { 3494 compatchan = 1; 3495 } else { 3496 printf("%s: unexpected PCI function %d\n", 3497 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3498 return; 3499 } 3500 sc->sc_wdcdev.nchannels = 1; 3501 } else { 3502 sc->sc_wdcdev.nchannels = 2; 3503 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3504 sc->sc_wdcdev.UDMA_cap = 6; 3505 else 3506 sc->sc_wdcdev.UDMA_cap = 5; 3507 } 3508 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3509 cp = &sc->pciide_channels[i]; 3510 if (sc->sc_wdcdev.nchannels > 1) { 3511 compatchan = i; 3512 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3513 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3514 printf("%s: %s channel ignored (disabled)\n", 3515 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3516 continue; 3517 } 3518 } 3519 if (pciide_chansetup(sc, i, interface) == 0) 3520 continue; 3521 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3522 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3523 &ctlsize, hpt_pci_intr); 3524 } else { 3525 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3526 &cmdsize, &ctlsize); 3527 } 3528 if (cp->hw_ok == 0) 3529 return; 3530 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3531 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3532 wdcattach(&cp->wdc_channel); 3533 hpt_setup_channel(&cp->wdc_channel); 3534 } 3535 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3536 (revision == HPT370_REV || revision == HPT370A_REV)) || 3537 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 3538 /* 3539 * HPT370_REV and highter has a bit to disable interrupts, 3540 * make sure to clear it 3541 */ 3542 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3543 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3544 ~HPT_CSEL_IRQDIS); 3545 } 3546 /* set clocks, etc (mandatory on 374, optional otherwise) */ 3547 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3548 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 3549 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 3550 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 3551 return; 3552 } 3553 3554 void 3555 hpt_setup_channel(chp) 3556 struct channel_softc *chp; 3557 { 3558 struct ata_drive_datas *drvp; 3559 int drive; 3560 int cable; 3561 u_int32_t before, after; 3562 u_int32_t idedma_ctl; 3563 struct pciide_channel *cp = (struct pciide_channel*)chp; 3564 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3565 3566 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3567 3568 /* setup DMA if needed */ 3569 pciide_channel_dma_setup(cp); 3570 3571 idedma_ctl = 0; 3572 3573 /* Per drive settings */ 3574 for (drive = 0; drive < 2; drive++) { 3575 drvp = &chp->ch_drive[drive]; 3576 /* If no drive, skip */ 3577 if ((drvp->drive_flags & DRIVE) == 0) 3578 continue; 3579 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3580 HPT_IDETIM(chp->channel, drive)); 3581 3582 /* add timing values, setup DMA if needed */ 3583 if (drvp->drive_flags & DRIVE_UDMA) { 3584 /* use Ultra/DMA */ 3585 drvp->drive_flags &= ~DRIVE_DMA; 3586 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3587 drvp->UDMA_mode > 2) 3588 drvp->UDMA_mode = 2; 3589 after = (sc->sc_wdcdev.nchannels == 2) ? 3590 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3591 hpt374_udma[drvp->UDMA_mode] : 3592 hpt370_udma[drvp->UDMA_mode]) : 3593 hpt366_udma[drvp->UDMA_mode]; 3594 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3595 } else if (drvp->drive_flags & DRIVE_DMA) { 3596 /* 3597 * use Multiword DMA. 3598 * Timings will be used for both PIO and DMA, so adjust 3599 * DMA mode if needed 3600 */ 3601 if (drvp->PIO_mode >= 3 && 3602 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3603 drvp->DMA_mode = drvp->PIO_mode - 2; 3604 } 3605 after = (sc->sc_wdcdev.nchannels == 2) ? 3606 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3607 hpt374_dma[drvp->DMA_mode] : 3608 hpt370_dma[drvp->DMA_mode]) : 3609 hpt366_dma[drvp->DMA_mode]; 3610 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3611 } else { 3612 /* PIO only */ 3613 after = (sc->sc_wdcdev.nchannels == 2) ? 3614 ( (sc->sc_wdcdev.UDMA_cap == 6) ? 3615 hpt374_pio[drvp->PIO_mode] : 3616 hpt370_pio[drvp->PIO_mode]) : 3617 hpt366_pio[drvp->PIO_mode]; 3618 } 3619 pci_conf_write(sc->sc_pc, sc->sc_tag, 3620 HPT_IDETIM(chp->channel, drive), after); 3621 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3622 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3623 after, before), DEBUG_PROBE); 3624 } 3625 if (idedma_ctl != 0) { 3626 /* Add software bits in status register */ 3627 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3628 IDEDMA_CTL, idedma_ctl); 3629 } 3630 pciide_print_modes(cp); 3631 } 3632 3633 int 3634 hpt_pci_intr(arg) 3635 void *arg; 3636 { 3637 struct pciide_softc *sc = arg; 3638 struct pciide_channel *cp; 3639 struct channel_softc *wdc_cp; 3640 int rv = 0; 3641 int dmastat, i, crv; 3642 3643 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3644 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3645 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3646 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 3647 IDEDMA_CTL_INTR) 3648 continue; 3649 cp = &sc->pciide_channels[i]; 3650 wdc_cp = &cp->wdc_channel; 3651 crv = wdcintr(wdc_cp); 3652 if (crv == 0) { 3653 printf("%s:%d: bogus intr\n", 3654 sc->sc_wdcdev.sc_dev.dv_xname, i); 3655 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3656 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3657 } else 3658 rv = 1; 3659 } 3660 return rv; 3661 } 3662 3663 3664 /* Macros to test product */ 3665 #define PDC_IS_262(sc) \ 3666 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3667 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3668 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3669 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3670 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3671 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3672 #define PDC_IS_265(sc) \ 3673 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3674 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 3675 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3676 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3677 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3678 #define PDC_IS_268(sc) \ 3679 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 3680 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 3681 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133) 3682 3683 void 3684 pdc202xx_chip_map(sc, pa) 3685 struct pciide_softc *sc; 3686 struct pci_attach_args *pa; 3687 { 3688 struct pciide_channel *cp; 3689 int channel; 3690 pcireg_t interface, st, mode; 3691 bus_size_t cmdsize, ctlsize; 3692 3693 if (!PDC_IS_268(sc)) { 3694 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3695 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 3696 st), DEBUG_PROBE); 3697 } 3698 if (pciide_chipen(sc, pa) == 0) 3699 return; 3700 3701 /* turn off RAID mode */ 3702 if (!PDC_IS_268(sc)) 3703 st &= ~PDC2xx_STATE_IDERAID; 3704 3705 /* 3706 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3707 * mode. We have to fake interface 3708 */ 3709 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3710 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 3711 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3712 3713 printf("%s: bus-master DMA support present", 3714 sc->sc_wdcdev.sc_dev.dv_xname); 3715 pciide_mapreg_dma(sc, pa); 3716 printf("\n"); 3717 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3718 WDC_CAPABILITY_MODE; 3719 if (sc->sc_dma_ok) { 3720 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3721 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3722 sc->sc_wdcdev.irqack = pciide_irqack; 3723 } 3724 sc->sc_wdcdev.PIO_cap = 4; 3725 sc->sc_wdcdev.DMA_cap = 2; 3726 if (PDC_IS_265(sc)) 3727 sc->sc_wdcdev.UDMA_cap = 5; 3728 else if (PDC_IS_262(sc)) 3729 sc->sc_wdcdev.UDMA_cap = 4; 3730 else 3731 sc->sc_wdcdev.UDMA_cap = 2; 3732 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 3733 pdc20268_setup_channel : pdc202xx_setup_channel; 3734 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3735 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3736 3737 if (!PDC_IS_268(sc)) { 3738 /* setup failsafe defaults */ 3739 mode = 0; 3740 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3741 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3742 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3743 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3744 for (channel = 0; 3745 channel < sc->sc_wdcdev.nchannels; 3746 channel++) { 3747 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3748 "drive 0 initial timings 0x%x, now 0x%x\n", 3749 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3750 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3751 DEBUG_PROBE); 3752 pci_conf_write(sc->sc_pc, sc->sc_tag, 3753 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 3754 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 3755 "drive 1 initial timings 0x%x, now 0x%x\n", 3756 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 3757 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3758 pci_conf_write(sc->sc_pc, sc->sc_tag, 3759 PDC2xx_TIM(channel, 1), mode); 3760 } 3761 3762 mode = PDC2xx_SCR_DMA; 3763 if (PDC_IS_262(sc)) { 3764 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3765 } else { 3766 /* the BIOS set it up this way */ 3767 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3768 } 3769 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3770 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3771 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 3772 "now 0x%x\n", 3773 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3774 PDC2xx_SCR), 3775 mode), DEBUG_PROBE); 3776 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3777 PDC2xx_SCR, mode); 3778 3779 /* controller initial state register is OK even without BIOS */ 3780 /* Set DMA mode to IDE DMA compatibility */ 3781 mode = 3782 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3783 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 3784 DEBUG_PROBE); 3785 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3786 mode | 0x1); 3787 mode = 3788 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3789 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3790 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3791 mode | 0x1); 3792 } 3793 3794 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3795 cp = &sc->pciide_channels[channel]; 3796 if (pciide_chansetup(sc, channel, interface) == 0) 3797 continue; 3798 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 3799 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3800 printf("%s: %s channel ignored (disabled)\n", 3801 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3802 continue; 3803 } 3804 if (PDC_IS_265(sc)) 3805 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3806 pdc20265_pci_intr); 3807 else 3808 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3809 pdc202xx_pci_intr); 3810 if (cp->hw_ok == 0) 3811 continue; 3812 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 3813 st &= ~(PDC_IS_262(sc) ? 3814 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3815 pciide_map_compat_intr(pa, cp, channel, interface); 3816 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 3817 } 3818 if (!PDC_IS_268(sc)) { 3819 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 3820 "0x%x\n", st), DEBUG_PROBE); 3821 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3822 } 3823 return; 3824 } 3825 3826 void 3827 pdc202xx_setup_channel(chp) 3828 struct channel_softc *chp; 3829 { 3830 struct ata_drive_datas *drvp; 3831 int drive; 3832 pcireg_t mode, st; 3833 u_int32_t idedma_ctl, scr, atapi; 3834 struct pciide_channel *cp = (struct pciide_channel*)chp; 3835 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3836 int channel = chp->channel; 3837 3838 /* setup DMA if needed */ 3839 pciide_channel_dma_setup(cp); 3840 3841 idedma_ctl = 0; 3842 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3843 sc->sc_wdcdev.sc_dev.dv_xname, 3844 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3845 DEBUG_PROBE); 3846 3847 /* Per channel settings */ 3848 if (PDC_IS_262(sc)) { 3849 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3850 PDC262_U66); 3851 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3852 /* Trim UDMA mode */ 3853 if ((st & PDC262_STATE_80P(channel)) != 0 || 3854 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3855 chp->ch_drive[0].UDMA_mode <= 2) || 3856 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3857 chp->ch_drive[1].UDMA_mode <= 2)) { 3858 if (chp->ch_drive[0].UDMA_mode > 2) 3859 chp->ch_drive[0].UDMA_mode = 2; 3860 if (chp->ch_drive[1].UDMA_mode > 2) 3861 chp->ch_drive[1].UDMA_mode = 2; 3862 } 3863 /* Set U66 if needed */ 3864 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3865 chp->ch_drive[0].UDMA_mode > 2) || 3866 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3867 chp->ch_drive[1].UDMA_mode > 2)) 3868 scr |= PDC262_U66_EN(channel); 3869 else 3870 scr &= ~PDC262_U66_EN(channel); 3871 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3872 PDC262_U66, scr); 3873 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3874 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3875 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3876 PDC262_ATAPI(channel))), DEBUG_PROBE); 3877 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3878 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3879 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3880 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3881 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3882 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3883 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3884 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3885 atapi = 0; 3886 else 3887 atapi = PDC262_ATAPI_UDMA; 3888 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3889 PDC262_ATAPI(channel), atapi); 3890 } 3891 } 3892 for (drive = 0; drive < 2; drive++) { 3893 drvp = &chp->ch_drive[drive]; 3894 /* If no drive, skip */ 3895 if ((drvp->drive_flags & DRIVE) == 0) 3896 continue; 3897 mode = 0; 3898 if (drvp->drive_flags & DRIVE_UDMA) { 3899 /* use Ultra/DMA */ 3900 drvp->drive_flags &= ~DRIVE_DMA; 3901 mode = PDC2xx_TIM_SET_MB(mode, 3902 pdc2xx_udma_mb[drvp->UDMA_mode]); 3903 mode = PDC2xx_TIM_SET_MC(mode, 3904 pdc2xx_udma_mc[drvp->UDMA_mode]); 3905 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3906 } else if (drvp->drive_flags & DRIVE_DMA) { 3907 mode = PDC2xx_TIM_SET_MB(mode, 3908 pdc2xx_dma_mb[drvp->DMA_mode]); 3909 mode = PDC2xx_TIM_SET_MC(mode, 3910 pdc2xx_dma_mc[drvp->DMA_mode]); 3911 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3912 } else { 3913 mode = PDC2xx_TIM_SET_MB(mode, 3914 pdc2xx_dma_mb[0]); 3915 mode = PDC2xx_TIM_SET_MC(mode, 3916 pdc2xx_dma_mc[0]); 3917 } 3918 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3919 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3920 if (drvp->drive_flags & DRIVE_ATA) 3921 mode |= PDC2xx_TIM_PRE; 3922 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3923 if (drvp->PIO_mode >= 3) { 3924 mode |= PDC2xx_TIM_IORDY; 3925 if (drive == 0) 3926 mode |= PDC2xx_TIM_IORDYp; 3927 } 3928 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3929 "timings 0x%x\n", 3930 sc->sc_wdcdev.sc_dev.dv_xname, 3931 chp->channel, drive, mode), DEBUG_PROBE); 3932 pci_conf_write(sc->sc_pc, sc->sc_tag, 3933 PDC2xx_TIM(chp->channel, drive), mode); 3934 } 3935 if (idedma_ctl != 0) { 3936 /* Add software bits in status register */ 3937 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3938 IDEDMA_CTL, idedma_ctl); 3939 } 3940 pciide_print_modes(cp); 3941 } 3942 3943 void 3944 pdc20268_setup_channel(chp) 3945 struct channel_softc *chp; 3946 { 3947 struct ata_drive_datas *drvp; 3948 int drive; 3949 u_int32_t idedma_ctl; 3950 struct pciide_channel *cp = (struct pciide_channel*)chp; 3951 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3952 int u100; 3953 3954 /* setup DMA if needed */ 3955 pciide_channel_dma_setup(cp); 3956 3957 idedma_ctl = 0; 3958 3959 /* I don't know what this is for, FreeBSD does it ... */ 3960 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3961 IDEDMA_CMD + 0x1, 0x0b); 3962 3963 /* 3964 * I don't know what this is for; FreeBSD checks this ... this is not 3965 * cable type detect. 3966 */ 3967 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3968 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 3969 3970 for (drive = 0; drive < 2; drive++) { 3971 drvp = &chp->ch_drive[drive]; 3972 /* If no drive, skip */ 3973 if ((drvp->drive_flags & DRIVE) == 0) 3974 continue; 3975 if (drvp->drive_flags & DRIVE_UDMA) { 3976 /* use Ultra/DMA */ 3977 drvp->drive_flags &= ~DRIVE_DMA; 3978 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3979 if (drvp->UDMA_mode > 2 && u100 == 0) 3980 drvp->UDMA_mode = 2; 3981 } else if (drvp->drive_flags & DRIVE_DMA) { 3982 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3983 } 3984 } 3985 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 3986 if (idedma_ctl != 0) { 3987 /* Add software bits in status register */ 3988 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3989 IDEDMA_CTL, idedma_ctl); 3990 } 3991 pciide_print_modes(cp); 3992 } 3993 3994 int 3995 pdc202xx_pci_intr(arg) 3996 void *arg; 3997 { 3998 struct pciide_softc *sc = arg; 3999 struct pciide_channel *cp; 4000 struct channel_softc *wdc_cp; 4001 int i, rv, crv; 4002 u_int32_t scr; 4003 4004 rv = 0; 4005 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 4006 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4007 cp = &sc->pciide_channels[i]; 4008 wdc_cp = &cp->wdc_channel; 4009 /* If a compat channel skip. */ 4010 if (cp->compat) 4011 continue; 4012 if (scr & PDC2xx_SCR_INT(i)) { 4013 crv = wdcintr(wdc_cp); 4014 if (crv == 0) 4015 printf("%s:%d: bogus intr (reg 0x%x)\n", 4016 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 4017 else 4018 rv = 1; 4019 } 4020 } 4021 return rv; 4022 } 4023 4024 int 4025 pdc20265_pci_intr(arg) 4026 void *arg; 4027 { 4028 struct pciide_softc *sc = arg; 4029 struct pciide_channel *cp; 4030 struct channel_softc *wdc_cp; 4031 int i, rv, crv; 4032 u_int32_t dmastat; 4033 4034 rv = 0; 4035 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4036 cp = &sc->pciide_channels[i]; 4037 wdc_cp = &cp->wdc_channel; 4038 /* If a compat channel skip. */ 4039 if (cp->compat) 4040 continue; 4041 /* 4042 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 4043 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 4044 * So use it instead (requires 2 reg reads instead of 1, 4045 * but we can't do it another way). 4046 */ 4047 dmastat = bus_space_read_1(sc->sc_dma_iot, 4048 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4049 if((dmastat & IDEDMA_CTL_INTR) == 0) 4050 continue; 4051 crv = wdcintr(wdc_cp); 4052 if (crv == 0) 4053 printf("%s:%d: bogus intr\n", 4054 sc->sc_wdcdev.sc_dev.dv_xname, i); 4055 else 4056 rv = 1; 4057 } 4058 return rv; 4059 } 4060 4061 void 4062 opti_chip_map(sc, pa) 4063 struct pciide_softc *sc; 4064 struct pci_attach_args *pa; 4065 { 4066 struct pciide_channel *cp; 4067 bus_size_t cmdsize, ctlsize; 4068 pcireg_t interface; 4069 u_int8_t init_ctrl; 4070 int channel; 4071 4072 if (pciide_chipen(sc, pa) == 0) 4073 return; 4074 printf("%s: bus-master DMA support present", 4075 sc->sc_wdcdev.sc_dev.dv_xname); 4076 4077 /* 4078 * XXXSCW: 4079 * There seem to be a couple of buggy revisions/implementations 4080 * of the OPTi pciide chipset. This kludge seems to fix one of 4081 * the reported problems (PR/11644) but still fails for the 4082 * other (PR/13151), although the latter may be due to other 4083 * issues too... 4084 */ 4085 if (PCI_REVISION(pa->pa_class) <= 0x12) { 4086 printf(" but disabled due to chip rev. <= 0x12"); 4087 sc->sc_dma_ok = 0; 4088 } else 4089 pciide_mapreg_dma(sc, pa); 4090 4091 printf("\n"); 4092 4093 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4094 WDC_CAPABILITY_MODE; 4095 sc->sc_wdcdev.PIO_cap = 4; 4096 if (sc->sc_dma_ok) { 4097 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4098 sc->sc_wdcdev.irqack = pciide_irqack; 4099 sc->sc_wdcdev.DMA_cap = 2; 4100 } 4101 sc->sc_wdcdev.set_modes = opti_setup_channel; 4102 4103 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4104 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4105 4106 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 4107 OPTI_REG_INIT_CONTROL); 4108 4109 interface = PCI_INTERFACE(pa->pa_class); 4110 4111 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4112 cp = &sc->pciide_channels[channel]; 4113 if (pciide_chansetup(sc, channel, interface) == 0) 4114 continue; 4115 if (channel == 1 && 4116 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 4117 printf("%s: %s channel ignored (disabled)\n", 4118 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4119 continue; 4120 } 4121 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4122 pciide_pci_intr); 4123 if (cp->hw_ok == 0) 4124 continue; 4125 pciide_map_compat_intr(pa, cp, channel, interface); 4126 if (cp->hw_ok == 0) 4127 continue; 4128 opti_setup_channel(&cp->wdc_channel); 4129 } 4130 } 4131 4132 void 4133 opti_setup_channel(chp) 4134 struct channel_softc *chp; 4135 { 4136 struct ata_drive_datas *drvp; 4137 struct pciide_channel *cp = (struct pciide_channel*)chp; 4138 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4139 int drive, spd; 4140 int mode[2]; 4141 u_int8_t rv, mr; 4142 4143 /* 4144 * The `Delay' and `Address Setup Time' fields of the 4145 * Miscellaneous Register are always zero initially. 4146 */ 4147 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 4148 mr &= ~(OPTI_MISC_DELAY_MASK | 4149 OPTI_MISC_ADDR_SETUP_MASK | 4150 OPTI_MISC_INDEX_MASK); 4151 4152 /* Prime the control register before setting timing values */ 4153 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 4154 4155 /* Determine the clockrate of the PCIbus the chip is attached to */ 4156 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 4157 spd &= OPTI_STRAP_PCI_SPEED_MASK; 4158 4159 /* setup DMA if needed */ 4160 pciide_channel_dma_setup(cp); 4161 4162 for (drive = 0; drive < 2; drive++) { 4163 drvp = &chp->ch_drive[drive]; 4164 /* If no drive, skip */ 4165 if ((drvp->drive_flags & DRIVE) == 0) { 4166 mode[drive] = -1; 4167 continue; 4168 } 4169 4170 if ((drvp->drive_flags & DRIVE_DMA)) { 4171 /* 4172 * Timings will be used for both PIO and DMA, 4173 * so adjust DMA mode if needed 4174 */ 4175 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 4176 drvp->PIO_mode = drvp->DMA_mode + 2; 4177 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 4178 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 4179 drvp->PIO_mode - 2 : 0; 4180 if (drvp->DMA_mode == 0) 4181 drvp->PIO_mode = 0; 4182 4183 mode[drive] = drvp->DMA_mode + 5; 4184 } else 4185 mode[drive] = drvp->PIO_mode; 4186 4187 if (drive && mode[0] >= 0 && 4188 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 4189 /* 4190 * Can't have two drives using different values 4191 * for `Address Setup Time'. 4192 * Slow down the faster drive to compensate. 4193 */ 4194 int d = (opti_tim_as[spd][mode[0]] > 4195 opti_tim_as[spd][mode[1]]) ? 0 : 1; 4196 4197 mode[d] = mode[1-d]; 4198 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4199 chp->ch_drive[d].DMA_mode = 0; 4200 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 4201 } 4202 } 4203 4204 for (drive = 0; drive < 2; drive++) { 4205 int m; 4206 if ((m = mode[drive]) < 0) 4207 continue; 4208 4209 /* Set the Address Setup Time and select appropriate index */ 4210 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4211 rv |= OPTI_MISC_INDEX(drive); 4212 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4213 4214 /* Set the pulse width and recovery timing parameters */ 4215 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4216 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4217 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4218 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4219 4220 /* Set the Enhanced Mode register appropriately */ 4221 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4222 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4223 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4224 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4225 } 4226 4227 /* Finally, enable the timings */ 4228 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4229 4230 pciide_print_modes(cp); 4231 } 4232 4233 #define ACARD_IS_850(sc) \ 4234 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4235 4236 void 4237 acard_chip_map(sc, pa) 4238 struct pciide_softc *sc; 4239 struct pci_attach_args *pa; 4240 { 4241 struct pciide_channel *cp; 4242 int i; 4243 pcireg_t interface; 4244 bus_size_t cmdsize, ctlsize; 4245 4246 if (pciide_chipen(sc, pa) == 0) 4247 return; 4248 4249 /* 4250 * when the chip is in native mode it identifies itself as a 4251 * 'misc mass storage'. Fake interface in this case. 4252 */ 4253 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4254 interface = PCI_INTERFACE(pa->pa_class); 4255 } else { 4256 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4257 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4258 } 4259 4260 printf("%s: bus-master DMA support present", 4261 sc->sc_wdcdev.sc_dev.dv_xname); 4262 pciide_mapreg_dma(sc, pa); 4263 printf("\n"); 4264 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4265 WDC_CAPABILITY_MODE; 4266 4267 if (sc->sc_dma_ok) { 4268 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4269 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4270 sc->sc_wdcdev.irqack = pciide_irqack; 4271 } 4272 sc->sc_wdcdev.PIO_cap = 4; 4273 sc->sc_wdcdev.DMA_cap = 2; 4274 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4275 4276 sc->sc_wdcdev.set_modes = acard_setup_channel; 4277 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4278 sc->sc_wdcdev.nchannels = 2; 4279 4280 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4281 cp = &sc->pciide_channels[i]; 4282 if (pciide_chansetup(sc, i, interface) == 0) 4283 continue; 4284 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4285 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4286 &ctlsize, pciide_pci_intr); 4287 } else { 4288 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4289 &cmdsize, &ctlsize); 4290 } 4291 if (cp->hw_ok == 0) 4292 return; 4293 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4294 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4295 wdcattach(&cp->wdc_channel); 4296 acard_setup_channel(&cp->wdc_channel); 4297 } 4298 if (!ACARD_IS_850(sc)) { 4299 u_int32_t reg; 4300 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4301 reg &= ~ATP860_CTRL_INT; 4302 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4303 } 4304 } 4305 4306 void 4307 acard_setup_channel(chp) 4308 struct channel_softc *chp; 4309 { 4310 struct ata_drive_datas *drvp; 4311 struct pciide_channel *cp = (struct pciide_channel*)chp; 4312 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4313 int channel = chp->channel; 4314 int drive; 4315 u_int32_t idetime, udma_mode; 4316 u_int32_t idedma_ctl; 4317 4318 /* setup DMA if needed */ 4319 pciide_channel_dma_setup(cp); 4320 4321 if (ACARD_IS_850(sc)) { 4322 idetime = 0; 4323 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4324 udma_mode &= ~ATP850_UDMA_MASK(channel); 4325 } else { 4326 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4327 idetime &= ~ATP860_SETTIME_MASK(channel); 4328 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4329 udma_mode &= ~ATP860_UDMA_MASK(channel); 4330 4331 /* check 80 pins cable */ 4332 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4333 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4334 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4335 & ATP860_CTRL_80P(chp->channel)) { 4336 if (chp->ch_drive[0].UDMA_mode > 2) 4337 chp->ch_drive[0].UDMA_mode = 2; 4338 if (chp->ch_drive[1].UDMA_mode > 2) 4339 chp->ch_drive[1].UDMA_mode = 2; 4340 } 4341 } 4342 } 4343 4344 idedma_ctl = 0; 4345 4346 /* Per drive settings */ 4347 for (drive = 0; drive < 2; drive++) { 4348 drvp = &chp->ch_drive[drive]; 4349 /* If no drive, skip */ 4350 if ((drvp->drive_flags & DRIVE) == 0) 4351 continue; 4352 /* add timing values, setup DMA if needed */ 4353 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4354 (drvp->drive_flags & DRIVE_UDMA)) { 4355 /* use Ultra/DMA */ 4356 if (ACARD_IS_850(sc)) { 4357 idetime |= ATP850_SETTIME(drive, 4358 acard_act_udma[drvp->UDMA_mode], 4359 acard_rec_udma[drvp->UDMA_mode]); 4360 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4361 acard_udma_conf[drvp->UDMA_mode]); 4362 } else { 4363 idetime |= ATP860_SETTIME(channel, drive, 4364 acard_act_udma[drvp->UDMA_mode], 4365 acard_rec_udma[drvp->UDMA_mode]); 4366 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4367 acard_udma_conf[drvp->UDMA_mode]); 4368 } 4369 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4370 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4371 (drvp->drive_flags & DRIVE_DMA)) { 4372 /* use Multiword DMA */ 4373 drvp->drive_flags &= ~DRIVE_UDMA; 4374 if (ACARD_IS_850(sc)) { 4375 idetime |= ATP850_SETTIME(drive, 4376 acard_act_dma[drvp->DMA_mode], 4377 acard_rec_dma[drvp->DMA_mode]); 4378 } else { 4379 idetime |= ATP860_SETTIME(channel, drive, 4380 acard_act_dma[drvp->DMA_mode], 4381 acard_rec_dma[drvp->DMA_mode]); 4382 } 4383 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4384 } else { 4385 /* PIO only */ 4386 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4387 if (ACARD_IS_850(sc)) { 4388 idetime |= ATP850_SETTIME(drive, 4389 acard_act_pio[drvp->PIO_mode], 4390 acard_rec_pio[drvp->PIO_mode]); 4391 } else { 4392 idetime |= ATP860_SETTIME(channel, drive, 4393 acard_act_pio[drvp->PIO_mode], 4394 acard_rec_pio[drvp->PIO_mode]); 4395 } 4396 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4397 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4398 | ATP8x0_CTRL_EN(channel)); 4399 } 4400 } 4401 4402 if (idedma_ctl != 0) { 4403 /* Add software bits in status register */ 4404 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4405 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4406 } 4407 pciide_print_modes(cp); 4408 4409 if (ACARD_IS_850(sc)) { 4410 pci_conf_write(sc->sc_pc, sc->sc_tag, 4411 ATP850_IDETIME(channel), idetime); 4412 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4413 } else { 4414 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4415 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4416 } 4417 } 4418 4419 int 4420 acard_pci_intr(arg) 4421 void *arg; 4422 { 4423 struct pciide_softc *sc = arg; 4424 struct pciide_channel *cp; 4425 struct channel_softc *wdc_cp; 4426 int rv = 0; 4427 int dmastat, i, crv; 4428 4429 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4430 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4431 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4432 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4433 continue; 4434 cp = &sc->pciide_channels[i]; 4435 wdc_cp = &cp->wdc_channel; 4436 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4437 (void)wdcintr(wdc_cp); 4438 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4439 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4440 continue; 4441 } 4442 crv = wdcintr(wdc_cp); 4443 if (crv == 0) 4444 printf("%s:%d: bogus intr\n", 4445 sc->sc_wdcdev.sc_dev.dv_xname, i); 4446 else if (crv == 1) 4447 rv = 1; 4448 else if (rv == 0) 4449 rv = crv; 4450 } 4451 return rv; 4452 } 4453 4454 static int 4455 sl82c105_bugchk(struct pci_attach_args *pa) 4456 { 4457 4458 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 4459 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 4460 return (0); 4461 4462 if (PCI_REVISION(pa->pa_class) <= 0x05) 4463 return (1); 4464 4465 return (0); 4466 } 4467 4468 void 4469 sl82c105_chip_map(sc, pa) 4470 struct pciide_softc *sc; 4471 struct pci_attach_args *pa; 4472 { 4473 struct pciide_channel *cp; 4474 bus_size_t cmdsize, ctlsize; 4475 pcireg_t interface, idecr; 4476 int channel; 4477 4478 if (pciide_chipen(sc, pa) == 0) 4479 return; 4480 4481 printf("%s: bus-master DMA support present", 4482 sc->sc_wdcdev.sc_dev.dv_xname); 4483 4484 /* 4485 * Check to see if we're part of the Winbond 83c553 Southbridge. 4486 * If so, we need to disable DMA on rev. <= 5 of that chip. 4487 */ 4488 if (pci_find_device(pa, sl82c105_bugchk)) { 4489 printf(" but disabled due to 83c553 rev. <= 0x05"); 4490 sc->sc_dma_ok = 0; 4491 } else 4492 pciide_mapreg_dma(sc, pa); 4493 printf("\n"); 4494 4495 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4496 WDC_CAPABILITY_MODE; 4497 sc->sc_wdcdev.PIO_cap = 4; 4498 if (sc->sc_dma_ok) { 4499 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4500 sc->sc_wdcdev.irqack = pciide_irqack; 4501 sc->sc_wdcdev.DMA_cap = 2; 4502 } 4503 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 4504 4505 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4506 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4507 4508 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 4509 4510 interface = PCI_INTERFACE(pa->pa_class); 4511 4512 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4513 cp = &sc->pciide_channels[channel]; 4514 if (pciide_chansetup(sc, channel, interface) == 0) 4515 continue; 4516 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 4517 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 4518 printf("%s: %s channel ignored (disabled)\n", 4519 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4520 continue; 4521 } 4522 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4523 pciide_pci_intr); 4524 if (cp->hw_ok == 0) 4525 continue; 4526 pciide_map_compat_intr(pa, cp, channel, interface); 4527 if (cp->hw_ok == 0) 4528 continue; 4529 sl82c105_setup_channel(&cp->wdc_channel); 4530 } 4531 } 4532 4533 void 4534 sl82c105_setup_channel(chp) 4535 struct channel_softc *chp; 4536 { 4537 struct ata_drive_datas *drvp; 4538 struct pciide_channel *cp = (struct pciide_channel*)chp; 4539 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4540 int pxdx_reg, drive; 4541 pcireg_t pxdx; 4542 4543 /* Set up DMA if needed. */ 4544 pciide_channel_dma_setup(cp); 4545 4546 for (drive = 0; drive < 2; drive++) { 4547 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 4548 : SYMPH_P1D0CR) + (drive * 4); 4549 4550 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 4551 4552 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 4553 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 4554 4555 drvp = &chp->ch_drive[drive]; 4556 /* If no drive, skip. */ 4557 if ((drvp->drive_flags & DRIVE) == 0) { 4558 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4559 continue; 4560 } 4561 4562 if (drvp->drive_flags & DRIVE_DMA) { 4563 /* 4564 * Timings will be used for both PIO and DMA, 4565 * so adjust DMA mode if needed. 4566 */ 4567 if (drvp->PIO_mode >= 3) { 4568 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 4569 drvp->DMA_mode = drvp->PIO_mode - 2; 4570 if (drvp->DMA_mode < 1) { 4571 /* 4572 * Can't mix both PIO and DMA. 4573 * Disable DMA. 4574 */ 4575 drvp->drive_flags &= ~DRIVE_DMA; 4576 } 4577 } else { 4578 /* 4579 * Can't mix both PIO and DMA. Disable 4580 * DMA. 4581 */ 4582 drvp->drive_flags &= ~DRIVE_DMA; 4583 } 4584 } 4585 4586 if (drvp->drive_flags & DRIVE_DMA) { 4587 /* Use multi-word DMA. */ 4588 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 4589 PxDx_CMD_ON_SHIFT; 4590 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 4591 } else { 4592 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 4593 PxDx_CMD_ON_SHIFT; 4594 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 4595 } 4596 4597 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 4598 4599 /* ...and set the mode for this drive. */ 4600 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4601 } 4602 4603 pciide_print_modes(cp); 4604 } 4605 4606 void 4607 serverworks_chip_map(sc, pa) 4608 struct pciide_softc *sc; 4609 struct pci_attach_args *pa; 4610 { 4611 struct pciide_channel *cp; 4612 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 4613 pcitag_t pcib_tag; 4614 int channel; 4615 bus_size_t cmdsize, ctlsize; 4616 4617 if (pciide_chipen(sc, pa) == 0) 4618 return; 4619 4620 printf("%s: bus-master DMA support present", 4621 sc->sc_wdcdev.sc_dev.dv_xname); 4622 pciide_mapreg_dma(sc, pa); 4623 printf("\n"); 4624 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4625 WDC_CAPABILITY_MODE; 4626 4627 if (sc->sc_dma_ok) { 4628 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4629 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4630 sc->sc_wdcdev.irqack = pciide_irqack; 4631 } 4632 sc->sc_wdcdev.PIO_cap = 4; 4633 sc->sc_wdcdev.DMA_cap = 2; 4634 switch (sc->sc_pp->ide_product) { 4635 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 4636 sc->sc_wdcdev.UDMA_cap = 2; 4637 break; 4638 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 4639 if (PCI_REVISION(pa->pa_class) < 0x92) 4640 sc->sc_wdcdev.UDMA_cap = 4; 4641 else 4642 sc->sc_wdcdev.UDMA_cap = 5; 4643 break; 4644 } 4645 4646 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 4647 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4648 sc->sc_wdcdev.nchannels = 2; 4649 4650 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4651 cp = &sc->pciide_channels[channel]; 4652 if (pciide_chansetup(sc, channel, interface) == 0) 4653 continue; 4654 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4655 serverworks_pci_intr); 4656 if (cp->hw_ok == 0) 4657 return; 4658 pciide_map_compat_intr(pa, cp, channel, interface); 4659 if (cp->hw_ok == 0) 4660 return; 4661 serverworks_setup_channel(&cp->wdc_channel); 4662 } 4663 4664 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 4665 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 4666 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 4667 } 4668 4669 void 4670 serverworks_setup_channel(chp) 4671 struct channel_softc *chp; 4672 { 4673 struct ata_drive_datas *drvp; 4674 struct pciide_channel *cp = (struct pciide_channel*)chp; 4675 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4676 int channel = chp->channel; 4677 int drive, unit; 4678 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 4679 u_int32_t idedma_ctl; 4680 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 4681 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 4682 4683 /* setup DMA if needed */ 4684 pciide_channel_dma_setup(cp); 4685 4686 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 4687 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 4688 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 4689 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 4690 4691 pio_time &= ~(0xffff << (16 * channel)); 4692 dma_time &= ~(0xffff << (16 * channel)); 4693 pio_mode &= ~(0xff << (8 * channel + 16)); 4694 udma_mode &= ~(0xff << (8 * channel + 16)); 4695 udma_mode &= ~(3 << (2 * channel)); 4696 4697 idedma_ctl = 0; 4698 4699 /* Per drive settings */ 4700 for (drive = 0; drive < 2; drive++) { 4701 drvp = &chp->ch_drive[drive]; 4702 /* If no drive, skip */ 4703 if ((drvp->drive_flags & DRIVE) == 0) 4704 continue; 4705 unit = drive + 2 * channel; 4706 /* add timing values, setup DMA if needed */ 4707 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 4708 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 4709 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4710 (drvp->drive_flags & DRIVE_UDMA)) { 4711 /* use Ultra/DMA, check for 80-pin cable */ 4712 if (drvp->UDMA_mode > 2 && 4713 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 4714 drvp->UDMA_mode = 2; 4715 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4716 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 4717 udma_mode |= 1 << unit; 4718 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4719 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4720 (drvp->drive_flags & DRIVE_DMA)) { 4721 /* use Multiword DMA */ 4722 drvp->drive_flags &= ~DRIVE_UDMA; 4723 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 4724 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4725 } else { 4726 /* PIO only */ 4727 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4728 } 4729 } 4730 4731 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 4732 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 4733 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 4734 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 4735 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 4736 4737 if (idedma_ctl != 0) { 4738 /* Add software bits in status register */ 4739 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4740 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4741 } 4742 pciide_print_modes(cp); 4743 } 4744 4745 int 4746 serverworks_pci_intr(arg) 4747 void *arg; 4748 { 4749 struct pciide_softc *sc = arg; 4750 struct pciide_channel *cp; 4751 struct channel_softc *wdc_cp; 4752 int rv = 0; 4753 int dmastat, i, crv; 4754 4755 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4756 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4757 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4758 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4759 IDEDMA_CTL_INTR) 4760 continue; 4761 cp = &sc->pciide_channels[i]; 4762 wdc_cp = &cp->wdc_channel; 4763 crv = wdcintr(wdc_cp); 4764 if (crv == 0) { 4765 printf("%s:%d: bogus intr\n", 4766 sc->sc_wdcdev.sc_dev.dv_xname, i); 4767 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4768 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4769 } else 4770 rv = 1; 4771 } 4772 return rv; 4773 } 4774
Indexes created Tue Sep 23 02:09:52 GMT 2025