pciide.c revision 1.183
1 /* $NetBSD: pciide.c,v 1.183 2003/03/15 12:23:34 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.183 2003/03/15 12:23:34 bouyer Exp $"); 80 81 #ifndef WDCDEBUG 82 #define WDCDEBUG 83 #endif 84 85 #define DEBUG_DMA 0x01 86 #define DEBUG_XFERS 0x02 87 #define DEBUG_FUNCS 0x08 88 #define DEBUG_PROBE 0x10 89 #ifdef WDCDEBUG 90 int wdcdebug_pciide_mask = 0; 91 #define WDCDEBUG_PRINT(args, level) \ 92 if (wdcdebug_pciide_mask & (level)) printf args 93 #else 94 #define WDCDEBUG_PRINT(args, level) 95 #endif 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <machine/endian.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/pciide_sl82c105_reg.h> 122 #include <dev/pci/cy82c693var.h> 123 124 #include "opt_pciide.h" 125 126 /* inlines for reading/writing 8-bit PCI registers */ 127 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 128 int)); 129 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 130 int, u_int8_t)); 131 132 static __inline u_int8_t 133 pciide_pci_read(pc, pa, reg) 134 pci_chipset_tag_t pc; 135 pcitag_t pa; 136 int reg; 137 { 138 139 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 140 ((reg & 0x03) * 8) & 0xff); 141 } 142 143 static __inline void 144 pciide_pci_write(pc, pa, reg, val) 145 pci_chipset_tag_t pc; 146 pcitag_t pa; 147 int reg; 148 u_int8_t val; 149 { 150 pcireg_t pcival; 151 152 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 153 pcival &= ~(0xff << ((reg & 0x03) * 8)); 154 pcival |= (val << ((reg & 0x03) * 8)); 155 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 156 } 157 158 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 160 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 void piix_setup_channel __P((struct channel_softc*)); 162 void piix3_4_setup_channel __P((struct channel_softc*)); 163 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 165 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 166 167 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void amd7x6_setup_channel __P((struct channel_softc*)); 169 170 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void apollo_setup_channel __P((struct channel_softc*)); 172 173 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cmd0643_9_setup_channel __P((struct channel_softc*)); 176 void cmd_channel_map __P((struct pci_attach_args *, 177 struct pciide_softc *, int)); 178 int cmd_pci_intr __P((void *)); 179 void cmd646_9_irqack __P((struct channel_softc *)); 180 void cmd680_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void cmd680_setup_channel __P((struct channel_softc*)); 182 void cmd680_channel_map __P((struct pci_attach_args *, 183 struct pciide_softc *, int)); 184 185 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 186 void cy693_setup_channel __P((struct channel_softc*)); 187 188 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void sis_setup_channel __P((struct channel_softc*)); 190 void sis96x_setup_channel __P((struct channel_softc*)); 191 static int sis_hostbr_match __P(( struct pci_attach_args *)); 192 static int sis_south_match __P(( struct pci_attach_args *)); 193 194 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 195 void acer_setup_channel __P((struct channel_softc*)); 196 int acer_pci_intr __P((void *)); 197 198 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 199 void pdc202xx_setup_channel __P((struct channel_softc*)); 200 void pdc20268_setup_channel __P((struct channel_softc*)); 201 int pdc202xx_pci_intr __P((void *)); 202 int pdc20265_pci_intr __P((void *)); 203 204 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 205 void opti_setup_channel __P((struct channel_softc*)); 206 207 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 208 void hpt_setup_channel __P((struct channel_softc*)); 209 int hpt_pci_intr __P((void *)); 210 211 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 212 void acard_setup_channel __P((struct channel_softc*)); 213 int acard_pci_intr __P((void *)); 214 215 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 216 void serverworks_setup_channel __P((struct channel_softc*)); 217 int serverworks_pci_intr __P((void *)); 218 219 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 220 void sl82c105_setup_channel __P((struct channel_softc*)); 221 222 void pciide_channel_dma_setup __P((struct pciide_channel *)); 223 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 224 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 225 void pciide_dma_start __P((void*, int, int)); 226 int pciide_dma_finish __P((void*, int, int, int)); 227 void pciide_irqack __P((struct channel_softc *)); 228 void pciide_print_modes __P((struct pciide_channel *)); 229 230 struct pciide_product_desc { 231 u_int32_t ide_product; 232 int ide_flags; 233 const char *ide_name; 234 /* map and setup chip, probe drives */ 235 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 236 }; 237 238 /* Flags for ide_flags */ 239 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 240 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 241 242 /* Default product description for devices not known from this controller */ 243 const struct pciide_product_desc default_product_desc = { 244 0, 245 0, 246 "Generic PCI IDE controller", 247 default_chip_map, 248 }; 249 250 const struct pciide_product_desc pciide_intel_products[] = { 251 { PCI_PRODUCT_INTEL_82092AA, 252 0, 253 "Intel 82092AA IDE controller", 254 default_chip_map, 255 }, 256 { PCI_PRODUCT_INTEL_82371FB_IDE, 257 0, 258 "Intel 82371FB IDE controller (PIIX)", 259 piix_chip_map, 260 }, 261 { PCI_PRODUCT_INTEL_82371SB_IDE, 262 0, 263 "Intel 82371SB IDE Interface (PIIX3)", 264 piix_chip_map, 265 }, 266 { PCI_PRODUCT_INTEL_82371AB_IDE, 267 0, 268 "Intel 82371AB IDE controller (PIIX4)", 269 piix_chip_map, 270 }, 271 { PCI_PRODUCT_INTEL_82440MX_IDE, 272 0, 273 "Intel 82440MX IDE controller", 274 piix_chip_map 275 }, 276 { PCI_PRODUCT_INTEL_82801AA_IDE, 277 0, 278 "Intel 82801AA IDE Controller (ICH)", 279 piix_chip_map, 280 }, 281 { PCI_PRODUCT_INTEL_82801AB_IDE, 282 0, 283 "Intel 82801AB IDE Controller (ICH0)", 284 piix_chip_map, 285 }, 286 { PCI_PRODUCT_INTEL_82801BA_IDE, 287 0, 288 "Intel 82801BA IDE Controller (ICH2)", 289 piix_chip_map, 290 }, 291 { PCI_PRODUCT_INTEL_82801BAM_IDE, 292 0, 293 "Intel 82801BAM IDE Controller (ICH2)", 294 piix_chip_map, 295 }, 296 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 297 0, 298 "Intel 82801CA IDE Controller", 299 piix_chip_map, 300 }, 301 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 302 0, 303 "Intel 82801CA IDE Controller", 304 piix_chip_map, 305 }, 306 { PCI_PRODUCT_INTEL_82801DB_IDE, 307 0, 308 "Intel 82801DB IDE Controller (ICH4)", 309 piix_chip_map, 310 }, 311 { 0, 312 0, 313 NULL, 314 NULL 315 } 316 }; 317 318 const struct pciide_product_desc pciide_amd_products[] = { 319 { PCI_PRODUCT_AMD_PBC756_IDE, 320 0, 321 "Advanced Micro Devices AMD756 IDE Controller", 322 amd7x6_chip_map 323 }, 324 { PCI_PRODUCT_AMD_PBC766_IDE, 325 0, 326 "Advanced Micro Devices AMD766 IDE Controller", 327 amd7x6_chip_map 328 }, 329 { PCI_PRODUCT_AMD_PBC768_IDE, 330 0, 331 "Advanced Micro Devices AMD768 IDE Controller", 332 amd7x6_chip_map 333 }, 334 { PCI_PRODUCT_AMD_PBC8111_IDE, 335 0, 336 "Advanced Micro Devices AMD8111 IDE Controller", 337 amd7x6_chip_map 338 }, 339 { 0, 340 0, 341 NULL, 342 NULL 343 } 344 }; 345 346 const struct pciide_product_desc pciide_nvidia_products[] = { 347 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 348 0, 349 "NVIDIA nForce IDE Controller", 350 amd7x6_chip_map 351 }, 352 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 353 0, 354 "NVIDIA nForce2 IDE Controller", 355 amd7x6_chip_map 356 }, 357 { 0, 358 0, 359 NULL, 360 NULL 361 } 362 }; 363 364 const struct pciide_product_desc pciide_cmd_products[] = { 365 { PCI_PRODUCT_CMDTECH_640, 366 0, 367 "CMD Technology PCI0640", 368 cmd_chip_map 369 }, 370 { PCI_PRODUCT_CMDTECH_643, 371 0, 372 "CMD Technology PCI0643", 373 cmd0643_9_chip_map, 374 }, 375 { PCI_PRODUCT_CMDTECH_646, 376 0, 377 "CMD Technology PCI0646", 378 cmd0643_9_chip_map, 379 }, 380 { PCI_PRODUCT_CMDTECH_648, 381 IDE_PCI_CLASS_OVERRIDE, 382 "CMD Technology PCI0648", 383 cmd0643_9_chip_map, 384 }, 385 { PCI_PRODUCT_CMDTECH_649, 386 IDE_PCI_CLASS_OVERRIDE, 387 "CMD Technology PCI0649", 388 cmd0643_9_chip_map, 389 }, 390 { PCI_PRODUCT_CMDTECH_680, 391 IDE_PCI_CLASS_OVERRIDE, 392 "Silicon Image 0680", 393 cmd680_chip_map, 394 }, 395 { 0, 396 0, 397 NULL, 398 NULL 399 } 400 }; 401 402 const struct pciide_product_desc pciide_via_products[] = { 403 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 404 0, 405 NULL, 406 apollo_chip_map, 407 }, 408 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 409 0, 410 NULL, 411 apollo_chip_map, 412 }, 413 { 0, 414 0, 415 NULL, 416 NULL 417 } 418 }; 419 420 const struct pciide_product_desc pciide_cypress_products[] = { 421 { PCI_PRODUCT_CONTAQ_82C693, 422 IDE_16BIT_IOSPACE, 423 "Cypress 82C693 IDE Controller", 424 cy693_chip_map, 425 }, 426 { 0, 427 0, 428 NULL, 429 NULL 430 } 431 }; 432 433 const struct pciide_product_desc pciide_sis_products[] = { 434 { PCI_PRODUCT_SIS_5597_IDE, 435 0, 436 NULL, 437 sis_chip_map, 438 }, 439 { 0, 440 0, 441 NULL, 442 NULL 443 } 444 }; 445 446 const struct pciide_product_desc pciide_acer_products[] = { 447 { PCI_PRODUCT_ALI_M5229, 448 0, 449 "Acer Labs M5229 UDMA IDE Controller", 450 acer_chip_map, 451 }, 452 { 0, 453 0, 454 NULL, 455 NULL 456 } 457 }; 458 459 const struct pciide_product_desc pciide_promise_products[] = { 460 { PCI_PRODUCT_PROMISE_ULTRA33, 461 IDE_PCI_CLASS_OVERRIDE, 462 "Promise Ultra33/ATA Bus Master IDE Accelerator", 463 pdc202xx_chip_map, 464 }, 465 { PCI_PRODUCT_PROMISE_ULTRA66, 466 IDE_PCI_CLASS_OVERRIDE, 467 "Promise Ultra66/ATA Bus Master IDE Accelerator", 468 pdc202xx_chip_map, 469 }, 470 { PCI_PRODUCT_PROMISE_ULTRA100, 471 IDE_PCI_CLASS_OVERRIDE, 472 "Promise Ultra100/ATA Bus Master IDE Accelerator", 473 pdc202xx_chip_map, 474 }, 475 { PCI_PRODUCT_PROMISE_ULTRA100X, 476 IDE_PCI_CLASS_OVERRIDE, 477 "Promise Ultra100/ATA Bus Master IDE Accelerator", 478 pdc202xx_chip_map, 479 }, 480 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 481 IDE_PCI_CLASS_OVERRIDE, 482 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 483 pdc202xx_chip_map, 484 }, 485 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 486 IDE_PCI_CLASS_OVERRIDE, 487 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 488 pdc202xx_chip_map, 489 }, 490 { PCI_PRODUCT_PROMISE_ULTRA133, 491 IDE_PCI_CLASS_OVERRIDE, 492 "Promise Ultra133/ATA Bus Master IDE Accelerator", 493 pdc202xx_chip_map, 494 }, 495 { PCI_PRODUCT_PROMISE_ULTRA133TX2, 496 IDE_PCI_CLASS_OVERRIDE, 497 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 498 pdc202xx_chip_map, 499 }, 500 { PCI_PRODUCT_PROMISE_MBULTRA133, 501 IDE_PCI_CLASS_OVERRIDE, 502 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 503 pdc202xx_chip_map, 504 }, 505 { PCI_PRODUCT_PROMISE_ULTRA133TX2v2, 506 IDE_PCI_CLASS_OVERRIDE, 507 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 508 pdc202xx_chip_map, 509 }, 510 { PCI_PRODUCT_PROMISE_FASTTRAK133LITE, 511 IDE_PCI_CLASS_OVERRIDE, 512 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 513 pdc202xx_chip_map, 514 }, 515 { PCI_PRODUCT_PROMISE_SATA150TX2PLUS, 516 IDE_PCI_CLASS_OVERRIDE, 517 "Promise Serial ATA/150 TX2plus Bus Master IDE Accelerator", 518 pdc202xx_chip_map, 519 }, 520 { 0, 521 0, 522 NULL, 523 NULL 524 } 525 }; 526 527 const struct pciide_product_desc pciide_opti_products[] = { 528 { PCI_PRODUCT_OPTI_82C621, 529 0, 530 "OPTi 82c621 PCI IDE controller", 531 opti_chip_map, 532 }, 533 { PCI_PRODUCT_OPTI_82C568, 534 0, 535 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 536 opti_chip_map, 537 }, 538 { PCI_PRODUCT_OPTI_82D568, 539 0, 540 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 541 opti_chip_map, 542 }, 543 { 0, 544 0, 545 NULL, 546 NULL 547 } 548 }; 549 550 const struct pciide_product_desc pciide_triones_products[] = { 551 { PCI_PRODUCT_TRIONES_HPT366, 552 IDE_PCI_CLASS_OVERRIDE, 553 NULL, 554 hpt_chip_map, 555 }, 556 { PCI_PRODUCT_TRIONES_HPT372, 557 IDE_PCI_CLASS_OVERRIDE, 558 NULL, 559 hpt_chip_map 560 }, 561 { PCI_PRODUCT_TRIONES_HPT374, 562 IDE_PCI_CLASS_OVERRIDE, 563 NULL, 564 hpt_chip_map 565 }, 566 { 0, 567 0, 568 NULL, 569 NULL 570 } 571 }; 572 573 const struct pciide_product_desc pciide_acard_products[] = { 574 { PCI_PRODUCT_ACARD_ATP850U, 575 IDE_PCI_CLASS_OVERRIDE, 576 "Acard ATP850U Ultra33 IDE Controller", 577 acard_chip_map, 578 }, 579 { PCI_PRODUCT_ACARD_ATP860, 580 IDE_PCI_CLASS_OVERRIDE, 581 "Acard ATP860 Ultra66 IDE Controller", 582 acard_chip_map, 583 }, 584 { PCI_PRODUCT_ACARD_ATP860A, 585 IDE_PCI_CLASS_OVERRIDE, 586 "Acard ATP860-A Ultra66 IDE Controller", 587 acard_chip_map, 588 }, 589 { 0, 590 0, 591 NULL, 592 NULL 593 } 594 }; 595 596 const struct pciide_product_desc pciide_serverworks_products[] = { 597 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 598 0, 599 "ServerWorks OSB4 IDE Controller", 600 serverworks_chip_map, 601 }, 602 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 603 0, 604 "ServerWorks CSB5 IDE Controller", 605 serverworks_chip_map, 606 }, 607 { PCI_PRODUCT_SERVERWORKS_CSB6_IDE, 608 0, 609 "ServerWorks CSB6 RAID/IDE Controller", 610 serverworks_chip_map, 611 }, 612 { 0, 613 0, 614 NULL, 615 } 616 }; 617 618 const struct pciide_product_desc pciide_symphony_products[] = { 619 { PCI_PRODUCT_SYMPHONY_82C105, 620 0, 621 "Symphony Labs 82C105 IDE controller", 622 sl82c105_chip_map, 623 }, 624 { 0, 625 0, 626 NULL, 627 } 628 }; 629 630 const struct pciide_product_desc pciide_winbond_products[] = { 631 { PCI_PRODUCT_WINBOND_W83C553F_1, 632 0, 633 "Winbond W83C553F IDE controller", 634 sl82c105_chip_map, 635 }, 636 { 0, 637 0, 638 NULL, 639 } 640 }; 641 642 struct pciide_vendor_desc { 643 u_int32_t ide_vendor; 644 const struct pciide_product_desc *ide_products; 645 }; 646 647 const struct pciide_vendor_desc pciide_vendors[] = { 648 { PCI_VENDOR_INTEL, pciide_intel_products }, 649 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 650 { PCI_VENDOR_VIATECH, pciide_via_products }, 651 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 652 { PCI_VENDOR_SIS, pciide_sis_products }, 653 { PCI_VENDOR_ALI, pciide_acer_products }, 654 { PCI_VENDOR_PROMISE, pciide_promise_products }, 655 { PCI_VENDOR_AMD, pciide_amd_products }, 656 { PCI_VENDOR_OPTI, pciide_opti_products }, 657 { PCI_VENDOR_TRIONES, pciide_triones_products }, 658 { PCI_VENDOR_ACARD, pciide_acard_products }, 659 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 660 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 661 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 662 { PCI_VENDOR_NVIDIA, pciide_nvidia_products }, 663 { 0, NULL } 664 }; 665 666 /* options passed via the 'flags' config keyword */ 667 #define PCIIDE_OPTIONS_DMA 0x01 668 #define PCIIDE_OPTIONS_NODMA 0x02 669 670 int pciide_match __P((struct device *, struct cfdata *, void *)); 671 void pciide_attach __P((struct device *, struct device *, void *)); 672 673 CFATTACH_DECL(pciide, sizeof(struct pciide_softc), 674 pciide_match, pciide_attach, NULL, NULL); 675 676 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 677 int pciide_mapregs_compat __P(( struct pci_attach_args *, 678 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 679 int pciide_mapregs_native __P((struct pci_attach_args *, 680 struct pciide_channel *, bus_size_t *, bus_size_t *, 681 int (*pci_intr) __P((void *)))); 682 void pciide_mapreg_dma __P((struct pciide_softc *, 683 struct pci_attach_args *)); 684 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 685 void pciide_mapchan __P((struct pci_attach_args *, 686 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 687 int (*pci_intr) __P((void *)))); 688 int pciide_chan_candisable __P((struct pciide_channel *)); 689 void pciide_map_compat_intr __P(( struct pci_attach_args *, 690 struct pciide_channel *, int, int)); 691 int pciide_compat_intr __P((void *)); 692 int pciide_pci_intr __P((void *)); 693 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 694 695 const struct pciide_product_desc * 696 pciide_lookup_product(id) 697 u_int32_t id; 698 { 699 const struct pciide_product_desc *pp; 700 const struct pciide_vendor_desc *vp; 701 702 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 703 if (PCI_VENDOR(id) == vp->ide_vendor) 704 break; 705 706 if ((pp = vp->ide_products) == NULL) 707 return NULL; 708 709 for (; pp->chip_map != NULL; pp++) 710 if (PCI_PRODUCT(id) == pp->ide_product) 711 break; 712 713 if (pp->chip_map == NULL) 714 return NULL; 715 return pp; 716 } 717 718 int 719 pciide_match(parent, match, aux) 720 struct device *parent; 721 struct cfdata *match; 722 void *aux; 723 { 724 struct pci_attach_args *pa = aux; 725 const struct pciide_product_desc *pp; 726 727 /* 728 * Check the ID register to see that it's a PCI IDE controller. 729 * If it is, we assume that we can deal with it; it _should_ 730 * work in a standardized way... 731 */ 732 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 733 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 734 return (1); 735 } 736 737 /* 738 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 739 * controllers. Let see if we can deal with it anyway. 740 */ 741 pp = pciide_lookup_product(pa->pa_id); 742 if (pp != NULL && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 743 return (1); 744 } 745 746 return (0); 747 } 748 749 void 750 pciide_attach(parent, self, aux) 751 struct device *parent, *self; 752 void *aux; 753 { 754 struct pci_attach_args *pa = aux; 755 pci_chipset_tag_t pc = pa->pa_pc; 756 pcitag_t tag = pa->pa_tag; 757 struct pciide_softc *sc = (struct pciide_softc *)self; 758 pcireg_t csr; 759 char devinfo[256]; 760 const char *displaydev; 761 762 sc->sc_pci_vendor = PCI_VENDOR(pa->pa_id); 763 sc->sc_pp = pciide_lookup_product(pa->pa_id); 764 if (sc->sc_pp == NULL) { 765 sc->sc_pp = &default_product_desc; 766 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 767 displaydev = devinfo; 768 } else 769 displaydev = sc->sc_pp->ide_name; 770 771 /* if displaydev == NULL, printf is done in chip-specific map */ 772 if (displaydev) 773 printf(": %s (rev. 0x%02x)\n", displaydev, 774 PCI_REVISION(pa->pa_class)); 775 776 sc->sc_pc = pa->pa_pc; 777 sc->sc_tag = pa->pa_tag; 778 #ifdef WDCDEBUG 779 if (wdcdebug_pciide_mask & DEBUG_PROBE) 780 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 781 #endif 782 sc->sc_pp->chip_map(sc, pa); 783 784 if (sc->sc_dma_ok) { 785 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 786 csr |= PCI_COMMAND_MASTER_ENABLE; 787 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 788 } 789 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 790 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 791 } 792 793 /* tell whether the chip is enabled or not */ 794 int 795 pciide_chipen(sc, pa) 796 struct pciide_softc *sc; 797 struct pci_attach_args *pa; 798 { 799 pcireg_t csr; 800 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 801 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 802 PCI_COMMAND_STATUS_REG); 803 printf("%s: device disabled (at %s)\n", 804 sc->sc_wdcdev.sc_dev.dv_xname, 805 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 806 "device" : "bridge"); 807 return 0; 808 } 809 return 1; 810 } 811 812 int 813 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 814 struct pci_attach_args *pa; 815 struct pciide_channel *cp; 816 int compatchan; 817 bus_size_t *cmdsizep, *ctlsizep; 818 { 819 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 820 struct channel_softc *wdc_cp = &cp->wdc_channel; 821 822 cp->compat = 1; 823 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 824 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 825 826 wdc_cp->cmd_iot = pa->pa_iot; 827 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 828 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 829 printf("%s: couldn't map %s channel cmd regs\n", 830 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 831 return (0); 832 } 833 834 wdc_cp->ctl_iot = pa->pa_iot; 835 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 836 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 837 printf("%s: couldn't map %s channel ctl regs\n", 838 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 839 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 840 PCIIDE_COMPAT_CMD_SIZE); 841 return (0); 842 } 843 844 return (1); 845 } 846 847 int 848 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 849 struct pci_attach_args * pa; 850 struct pciide_channel *cp; 851 bus_size_t *cmdsizep, *ctlsizep; 852 int (*pci_intr) __P((void *)); 853 { 854 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 855 struct channel_softc *wdc_cp = &cp->wdc_channel; 856 const char *intrstr; 857 pci_intr_handle_t intrhandle; 858 859 cp->compat = 0; 860 861 if (sc->sc_pci_ih == NULL) { 862 if (pci_intr_map(pa, &intrhandle) != 0) { 863 printf("%s: couldn't map native-PCI interrupt\n", 864 sc->sc_wdcdev.sc_dev.dv_xname); 865 return 0; 866 } 867 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 868 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 869 intrhandle, IPL_BIO, pci_intr, sc); 870 if (sc->sc_pci_ih != NULL) { 871 printf("%s: using %s for native-PCI interrupt\n", 872 sc->sc_wdcdev.sc_dev.dv_xname, 873 intrstr ? intrstr : "unknown interrupt"); 874 } else { 875 printf("%s: couldn't establish native-PCI interrupt", 876 sc->sc_wdcdev.sc_dev.dv_xname); 877 if (intrstr != NULL) 878 printf(" at %s", intrstr); 879 printf("\n"); 880 return 0; 881 } 882 } 883 cp->ih = sc->sc_pci_ih; 884 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 885 PCI_MAPREG_TYPE_IO, 0, 886 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 887 printf("%s: couldn't map %s channel cmd regs\n", 888 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 889 return 0; 890 } 891 892 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 893 PCI_MAPREG_TYPE_IO, 0, 894 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 895 printf("%s: couldn't map %s channel ctl regs\n", 896 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 897 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 898 return 0; 899 } 900 /* 901 * In native mode, 4 bytes of I/O space are mapped for the control 902 * register, the control register is at offset 2. Pass the generic 903 * code a handle for only one byte at the right offset. 904 */ 905 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 906 &wdc_cp->ctl_ioh) != 0) { 907 printf("%s: unable to subregion %s channel ctl regs\n", 908 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 909 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 910 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 911 return 0; 912 } 913 return (1); 914 } 915 916 void 917 pciide_mapreg_dma(sc, pa) 918 struct pciide_softc *sc; 919 struct pci_attach_args *pa; 920 { 921 pcireg_t maptype; 922 bus_addr_t addr; 923 924 /* 925 * Map DMA registers 926 * 927 * Note that sc_dma_ok is the right variable to test to see if 928 * DMA can be done. If the interface doesn't support DMA, 929 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 930 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 931 * non-zero if the interface supports DMA and the registers 932 * could be mapped. 933 * 934 * XXX Note that despite the fact that the Bus Master IDE specs 935 * XXX say that "The bus master IDE function uses 16 bytes of IO 936 * XXX space," some controllers (at least the United 937 * XXX Microelectronics UM8886BF) place it in memory space. 938 */ 939 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 940 PCIIDE_REG_BUS_MASTER_DMA); 941 942 switch (maptype) { 943 case PCI_MAPREG_TYPE_IO: 944 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 945 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 946 &addr, NULL, NULL) == 0); 947 if (sc->sc_dma_ok == 0) { 948 printf(", but unused (couldn't query registers)"); 949 break; 950 } 951 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 952 && addr >= 0x10000) { 953 sc->sc_dma_ok = 0; 954 printf(", but unused (registers at unsafe address " 955 "%#lx)", (unsigned long)addr); 956 break; 957 } 958 /* FALLTHROUGH */ 959 960 case PCI_MAPREG_MEM_TYPE_32BIT: 961 sc->sc_dma_ok = (pci_mapreg_map(pa, 962 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 963 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 964 sc->sc_dmat = pa->pa_dmat; 965 if (sc->sc_dma_ok == 0) { 966 printf(", but unused (couldn't map registers)"); 967 } else { 968 sc->sc_wdcdev.dma_arg = sc; 969 sc->sc_wdcdev.dma_init = pciide_dma_init; 970 sc->sc_wdcdev.dma_start = pciide_dma_start; 971 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 972 } 973 974 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 975 PCIIDE_OPTIONS_NODMA) { 976 printf(", but unused (forced off by config file)"); 977 sc->sc_dma_ok = 0; 978 } 979 break; 980 981 default: 982 sc->sc_dma_ok = 0; 983 printf(", but unsupported register maptype (0x%x)", maptype); 984 } 985 } 986 987 int 988 pciide_compat_intr(arg) 989 void *arg; 990 { 991 struct pciide_channel *cp = arg; 992 993 #ifdef DIAGNOSTIC 994 /* should only be called for a compat channel */ 995 if (cp->compat == 0) 996 panic("pciide compat intr called for non-compat chan %p", cp); 997 #endif 998 return (wdcintr(&cp->wdc_channel)); 999 } 1000 1001 int 1002 pciide_pci_intr(arg) 1003 void *arg; 1004 { 1005 struct pciide_softc *sc = arg; 1006 struct pciide_channel *cp; 1007 struct channel_softc *wdc_cp; 1008 int i, rv, crv; 1009 1010 rv = 0; 1011 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1012 cp = &sc->pciide_channels[i]; 1013 wdc_cp = &cp->wdc_channel; 1014 1015 /* If a compat channel skip. */ 1016 if (cp->compat) 1017 continue; 1018 /* if this channel not waiting for intr, skip */ 1019 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 1020 continue; 1021 1022 crv = wdcintr(wdc_cp); 1023 if (crv == 0) 1024 ; /* leave rv alone */ 1025 else if (crv == 1) 1026 rv = 1; /* claim the intr */ 1027 else if (rv == 0) /* crv should be -1 in this case */ 1028 rv = crv; /* if we've done no better, take it */ 1029 } 1030 return (rv); 1031 } 1032 1033 void 1034 pciide_channel_dma_setup(cp) 1035 struct pciide_channel *cp; 1036 { 1037 int drive; 1038 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1039 struct ata_drive_datas *drvp; 1040 1041 for (drive = 0; drive < 2; drive++) { 1042 drvp = &cp->wdc_channel.ch_drive[drive]; 1043 /* If no drive, skip */ 1044 if ((drvp->drive_flags & DRIVE) == 0) 1045 continue; 1046 /* setup DMA if needed */ 1047 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1048 (drvp->drive_flags & DRIVE_UDMA) == 0) || 1049 sc->sc_dma_ok == 0) { 1050 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1051 continue; 1052 } 1053 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 1054 != 0) { 1055 /* Abort DMA setup */ 1056 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1057 continue; 1058 } 1059 } 1060 } 1061 1062 int 1063 pciide_dma_table_setup(sc, channel, drive) 1064 struct pciide_softc *sc; 1065 int channel, drive; 1066 { 1067 bus_dma_segment_t seg; 1068 int error, rseg; 1069 const bus_size_t dma_table_size = 1070 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1071 struct pciide_dma_maps *dma_maps = 1072 &sc->pciide_channels[channel].dma_maps[drive]; 1073 1074 /* If table was already allocated, just return */ 1075 if (dma_maps->dma_table) 1076 return 0; 1077 1078 /* Allocate memory for the DMA tables and map it */ 1079 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1080 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1081 BUS_DMA_NOWAIT)) != 0) { 1082 printf("%s:%d: unable to allocate table DMA for " 1083 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1084 channel, drive, error); 1085 return error; 1086 } 1087 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1088 dma_table_size, 1089 (caddr_t *)&dma_maps->dma_table, 1090 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1091 printf("%s:%d: unable to map table DMA for" 1092 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1093 channel, drive, error); 1094 return error; 1095 } 1096 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1097 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1098 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1099 1100 /* Create and load table DMA map for this disk */ 1101 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1102 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1103 &dma_maps->dmamap_table)) != 0) { 1104 printf("%s:%d: unable to create table DMA map for " 1105 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1106 channel, drive, error); 1107 return error; 1108 } 1109 if ((error = bus_dmamap_load(sc->sc_dmat, 1110 dma_maps->dmamap_table, 1111 dma_maps->dma_table, 1112 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1113 printf("%s:%d: unable to load table DMA map for " 1114 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1115 channel, drive, error); 1116 return error; 1117 } 1118 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1119 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1120 DEBUG_PROBE); 1121 /* Create a xfer DMA map for this drive */ 1122 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1123 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1124 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1125 &dma_maps->dmamap_xfer)) != 0) { 1126 printf("%s:%d: unable to create xfer DMA map for " 1127 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1128 channel, drive, error); 1129 return error; 1130 } 1131 return 0; 1132 } 1133 1134 int 1135 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1136 void *v; 1137 int channel, drive; 1138 void *databuf; 1139 size_t datalen; 1140 int flags; 1141 { 1142 struct pciide_softc *sc = v; 1143 int error, seg; 1144 struct pciide_dma_maps *dma_maps = 1145 &sc->pciide_channels[channel].dma_maps[drive]; 1146 1147 error = bus_dmamap_load(sc->sc_dmat, 1148 dma_maps->dmamap_xfer, 1149 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1150 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1151 if (error) { 1152 printf("%s:%d: unable to load xfer DMA map for" 1153 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1154 channel, drive, error); 1155 return error; 1156 } 1157 1158 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1159 dma_maps->dmamap_xfer->dm_mapsize, 1160 (flags & WDC_DMA_READ) ? 1161 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1162 1163 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1164 #ifdef DIAGNOSTIC 1165 /* A segment must not cross a 64k boundary */ 1166 { 1167 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1168 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1169 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1170 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1171 printf("pciide_dma: segment %d physical addr 0x%lx" 1172 " len 0x%lx not properly aligned\n", 1173 seg, phys, len); 1174 panic("pciide_dma: buf align"); 1175 } 1176 } 1177 #endif 1178 dma_maps->dma_table[seg].base_addr = 1179 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1180 dma_maps->dma_table[seg].byte_count = 1181 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1182 IDEDMA_BYTE_COUNT_MASK); 1183 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1184 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1185 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1186 1187 } 1188 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1189 htole32(IDEDMA_BYTE_COUNT_EOT); 1190 1191 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1192 dma_maps->dmamap_table->dm_mapsize, 1193 BUS_DMASYNC_PREWRITE); 1194 1195 /* Maps are ready. Start DMA function */ 1196 #ifdef DIAGNOSTIC 1197 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1198 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1199 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1200 panic("pciide_dma_init: table align"); 1201 } 1202 #endif 1203 1204 /* Clear status bits */ 1205 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1206 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1207 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1208 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1209 /* Write table addr */ 1210 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1211 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1212 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1213 /* set read/write */ 1214 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1215 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1216 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1217 /* remember flags */ 1218 dma_maps->dma_flags = flags; 1219 return 0; 1220 } 1221 1222 void 1223 pciide_dma_start(v, channel, drive) 1224 void *v; 1225 int channel, drive; 1226 { 1227 struct pciide_softc *sc = v; 1228 1229 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1230 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1231 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1232 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1233 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1234 } 1235 1236 int 1237 pciide_dma_finish(v, channel, drive, force) 1238 void *v; 1239 int channel, drive; 1240 int force; 1241 { 1242 struct pciide_softc *sc = v; 1243 u_int8_t status; 1244 int error = 0; 1245 struct pciide_dma_maps *dma_maps = 1246 &sc->pciide_channels[channel].dma_maps[drive]; 1247 1248 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1249 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1250 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1251 DEBUG_XFERS); 1252 1253 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1254 return WDC_DMAST_NOIRQ; 1255 1256 /* stop DMA channel */ 1257 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1258 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1259 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1260 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1261 1262 /* Unload the map of the data buffer */ 1263 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1264 dma_maps->dmamap_xfer->dm_mapsize, 1265 (dma_maps->dma_flags & WDC_DMA_READ) ? 1266 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1267 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1268 1269 if ((status & IDEDMA_CTL_ERR) != 0) { 1270 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1271 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1272 error |= WDC_DMAST_ERR; 1273 } 1274 1275 if ((status & IDEDMA_CTL_INTR) == 0) { 1276 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1277 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1278 drive, status); 1279 error |= WDC_DMAST_NOIRQ; 1280 } 1281 1282 if ((status & IDEDMA_CTL_ACT) != 0) { 1283 /* data underrun, may be a valid condition for ATAPI */ 1284 error |= WDC_DMAST_UNDER; 1285 } 1286 return error; 1287 } 1288 1289 void 1290 pciide_irqack(chp) 1291 struct channel_softc *chp; 1292 { 1293 struct pciide_channel *cp = (struct pciide_channel*)chp; 1294 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1295 1296 /* clear status bits in IDE DMA registers */ 1297 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1298 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1299 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1300 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1301 } 1302 1303 /* some common code used by several chip_map */ 1304 int 1305 pciide_chansetup(sc, channel, interface) 1306 struct pciide_softc *sc; 1307 int channel; 1308 pcireg_t interface; 1309 { 1310 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1311 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1312 cp->name = PCIIDE_CHANNEL_NAME(channel); 1313 cp->wdc_channel.channel = channel; 1314 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1315 cp->wdc_channel.ch_queue = 1316 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1317 if (cp->wdc_channel.ch_queue == NULL) { 1318 printf("%s %s channel: " 1319 "can't allocate memory for command queue", 1320 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1321 return 0; 1322 } 1323 printf("%s: %s channel %s to %s mode\n", 1324 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1325 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1326 "configured" : "wired", 1327 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1328 "native-PCI" : "compatibility"); 1329 return 1; 1330 } 1331 1332 /* some common code used by several chip channel_map */ 1333 void 1334 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1335 struct pci_attach_args *pa; 1336 struct pciide_channel *cp; 1337 pcireg_t interface; 1338 bus_size_t *cmdsizep, *ctlsizep; 1339 int (*pci_intr) __P((void *)); 1340 { 1341 struct channel_softc *wdc_cp = &cp->wdc_channel; 1342 1343 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1344 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1345 pci_intr); 1346 else 1347 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1348 wdc_cp->channel, cmdsizep, ctlsizep); 1349 1350 if (cp->hw_ok == 0) 1351 return; 1352 wdc_cp->data32iot = wdc_cp->cmd_iot; 1353 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1354 wdcattach(wdc_cp); 1355 } 1356 1357 /* 1358 * Generic code to call to know if a channel can be disabled. Return 1 1359 * if channel can be disabled, 0 if not 1360 */ 1361 int 1362 pciide_chan_candisable(cp) 1363 struct pciide_channel *cp; 1364 { 1365 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1366 struct channel_softc *wdc_cp = &cp->wdc_channel; 1367 1368 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1369 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1370 printf("%s: disabling %s channel (no drives)\n", 1371 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1372 cp->hw_ok = 0; 1373 return 1; 1374 } 1375 return 0; 1376 } 1377 1378 /* 1379 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1380 * Set hw_ok=0 on failure 1381 */ 1382 void 1383 pciide_map_compat_intr(pa, cp, compatchan, interface) 1384 struct pci_attach_args *pa; 1385 struct pciide_channel *cp; 1386 int compatchan, interface; 1387 { 1388 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1389 struct channel_softc *wdc_cp = &cp->wdc_channel; 1390 1391 if (cp->hw_ok == 0) 1392 return; 1393 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1394 return; 1395 1396 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1397 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1398 pa, compatchan, pciide_compat_intr, cp); 1399 if (cp->ih == NULL) { 1400 #endif 1401 printf("%s: no compatibility interrupt for use by %s " 1402 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1403 cp->hw_ok = 0; 1404 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1405 } 1406 #endif 1407 } 1408 1409 void 1410 pciide_print_modes(cp) 1411 struct pciide_channel *cp; 1412 { 1413 wdc_print_modes(&cp->wdc_channel); 1414 } 1415 1416 void 1417 default_chip_map(sc, pa) 1418 struct pciide_softc *sc; 1419 struct pci_attach_args *pa; 1420 { 1421 struct pciide_channel *cp; 1422 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1423 pcireg_t csr; 1424 int channel, drive; 1425 struct ata_drive_datas *drvp; 1426 u_int8_t idedma_ctl; 1427 bus_size_t cmdsize, ctlsize; 1428 char *failreason; 1429 1430 if (pciide_chipen(sc, pa) == 0) 1431 return; 1432 1433 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1434 printf("%s: bus-master DMA support present", 1435 sc->sc_wdcdev.sc_dev.dv_xname); 1436 if (sc->sc_pp == &default_product_desc && 1437 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1438 PCIIDE_OPTIONS_DMA) == 0) { 1439 printf(", but unused (no driver support)"); 1440 sc->sc_dma_ok = 0; 1441 } else { 1442 pciide_mapreg_dma(sc, pa); 1443 if (sc->sc_dma_ok != 0) 1444 printf(", used without full driver " 1445 "support"); 1446 } 1447 } else { 1448 printf("%s: hardware does not support DMA", 1449 sc->sc_wdcdev.sc_dev.dv_xname); 1450 sc->sc_dma_ok = 0; 1451 } 1452 printf("\n"); 1453 if (sc->sc_dma_ok) { 1454 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1455 sc->sc_wdcdev.irqack = pciide_irqack; 1456 } 1457 sc->sc_wdcdev.PIO_cap = 0; 1458 sc->sc_wdcdev.DMA_cap = 0; 1459 1460 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1461 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1462 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1463 1464 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1465 cp = &sc->pciide_channels[channel]; 1466 if (pciide_chansetup(sc, channel, interface) == 0) 1467 continue; 1468 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1469 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1470 &ctlsize, pciide_pci_intr); 1471 } else { 1472 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1473 channel, &cmdsize, &ctlsize); 1474 } 1475 if (cp->hw_ok == 0) 1476 continue; 1477 /* 1478 * Check to see if something appears to be there. 1479 */ 1480 failreason = NULL; 1481 if (!wdcprobe(&cp->wdc_channel)) { 1482 failreason = "not responding; disabled or no drives?"; 1483 goto next; 1484 } 1485 /* 1486 * Now, make sure it's actually attributable to this PCI IDE 1487 * channel by trying to access the channel again while the 1488 * PCI IDE controller's I/O space is disabled. (If the 1489 * channel no longer appears to be there, it belongs to 1490 * this controller.) YUCK! 1491 */ 1492 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1493 PCI_COMMAND_STATUS_REG); 1494 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1495 csr & ~PCI_COMMAND_IO_ENABLE); 1496 if (wdcprobe(&cp->wdc_channel)) 1497 failreason = "other hardware responding at addresses"; 1498 pci_conf_write(sc->sc_pc, sc->sc_tag, 1499 PCI_COMMAND_STATUS_REG, csr); 1500 next: 1501 if (failreason) { 1502 printf("%s: %s channel ignored (%s)\n", 1503 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1504 failreason); 1505 cp->hw_ok = 0; 1506 bus_space_unmap(cp->wdc_channel.cmd_iot, 1507 cp->wdc_channel.cmd_ioh, cmdsize); 1508 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1509 bus_space_unmap(cp->wdc_channel.ctl_iot, 1510 cp->ctl_baseioh, ctlsize); 1511 else 1512 bus_space_unmap(cp->wdc_channel.ctl_iot, 1513 cp->wdc_channel.ctl_ioh, ctlsize); 1514 } else { 1515 pciide_map_compat_intr(pa, cp, channel, interface); 1516 } 1517 if (cp->hw_ok) { 1518 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1519 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1520 wdcattach(&cp->wdc_channel); 1521 } 1522 } 1523 1524 if (sc->sc_dma_ok == 0) 1525 return; 1526 1527 /* Allocate DMA maps */ 1528 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1529 idedma_ctl = 0; 1530 cp = &sc->pciide_channels[channel]; 1531 for (drive = 0; drive < 2; drive++) { 1532 drvp = &cp->wdc_channel.ch_drive[drive]; 1533 /* If no drive, skip */ 1534 if ((drvp->drive_flags & DRIVE) == 0) 1535 continue; 1536 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1537 continue; 1538 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1539 /* Abort DMA setup */ 1540 printf("%s:%d:%d: can't allocate DMA maps, " 1541 "using PIO transfers\n", 1542 sc->sc_wdcdev.sc_dev.dv_xname, 1543 channel, drive); 1544 drvp->drive_flags &= ~DRIVE_DMA; 1545 } 1546 printf("%s:%d:%d: using DMA data transfers\n", 1547 sc->sc_wdcdev.sc_dev.dv_xname, 1548 channel, drive); 1549 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1550 } 1551 if (idedma_ctl != 0) { 1552 /* Add software bits in status register */ 1553 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1554 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1555 idedma_ctl); 1556 } 1557 } 1558 } 1559 1560 void 1561 piix_chip_map(sc, pa) 1562 struct pciide_softc *sc; 1563 struct pci_attach_args *pa; 1564 { 1565 struct pciide_channel *cp; 1566 int channel; 1567 u_int32_t idetim; 1568 bus_size_t cmdsize, ctlsize; 1569 1570 if (pciide_chipen(sc, pa) == 0) 1571 return; 1572 1573 printf("%s: bus-master DMA support present", 1574 sc->sc_wdcdev.sc_dev.dv_xname); 1575 pciide_mapreg_dma(sc, pa); 1576 printf("\n"); 1577 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1578 WDC_CAPABILITY_MODE; 1579 if (sc->sc_dma_ok) { 1580 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1581 sc->sc_wdcdev.irqack = pciide_irqack; 1582 switch(sc->sc_pp->ide_product) { 1583 case PCI_PRODUCT_INTEL_82371AB_IDE: 1584 case PCI_PRODUCT_INTEL_82440MX_IDE: 1585 case PCI_PRODUCT_INTEL_82801AA_IDE: 1586 case PCI_PRODUCT_INTEL_82801AB_IDE: 1587 case PCI_PRODUCT_INTEL_82801BA_IDE: 1588 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1589 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1590 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1591 case PCI_PRODUCT_INTEL_82801DB_IDE: 1592 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1593 } 1594 } 1595 sc->sc_wdcdev.PIO_cap = 4; 1596 sc->sc_wdcdev.DMA_cap = 2; 1597 switch(sc->sc_pp->ide_product) { 1598 case PCI_PRODUCT_INTEL_82801AA_IDE: 1599 sc->sc_wdcdev.UDMA_cap = 4; 1600 break; 1601 case PCI_PRODUCT_INTEL_82801BA_IDE: 1602 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1603 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1604 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1605 case PCI_PRODUCT_INTEL_82801DB_IDE: 1606 sc->sc_wdcdev.UDMA_cap = 5; 1607 break; 1608 default: 1609 sc->sc_wdcdev.UDMA_cap = 2; 1610 } 1611 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1612 sc->sc_wdcdev.set_modes = piix_setup_channel; 1613 else 1614 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1615 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1616 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1617 1618 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1619 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1620 DEBUG_PROBE); 1621 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1622 WDCDEBUG_PRINT((", sidetim=0x%x", 1623 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1624 DEBUG_PROBE); 1625 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1626 WDCDEBUG_PRINT((", udamreg 0x%x", 1627 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1628 DEBUG_PROBE); 1629 } 1630 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1631 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1632 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1633 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1634 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1635 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1636 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1637 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1638 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1639 DEBUG_PROBE); 1640 } 1641 1642 } 1643 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1644 1645 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1646 cp = &sc->pciide_channels[channel]; 1647 /* PIIX is compat-only */ 1648 if (pciide_chansetup(sc, channel, 0) == 0) 1649 continue; 1650 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1651 if ((PIIX_IDETIM_READ(idetim, channel) & 1652 PIIX_IDETIM_IDE) == 0) { 1653 printf("%s: %s channel ignored (disabled)\n", 1654 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1655 continue; 1656 } 1657 /* PIIX are compat-only pciide devices */ 1658 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1659 if (cp->hw_ok == 0) 1660 continue; 1661 if (pciide_chan_candisable(cp)) { 1662 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1663 channel); 1664 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1665 idetim); 1666 } 1667 pciide_map_compat_intr(pa, cp, channel, 0); 1668 if (cp->hw_ok == 0) 1669 continue; 1670 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1671 } 1672 1673 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1674 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1675 DEBUG_PROBE); 1676 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1677 WDCDEBUG_PRINT((", sidetim=0x%x", 1678 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1679 DEBUG_PROBE); 1680 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1681 WDCDEBUG_PRINT((", udamreg 0x%x", 1682 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1683 DEBUG_PROBE); 1684 } 1685 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1686 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1687 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1688 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1689 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1690 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1691 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1692 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1693 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1694 DEBUG_PROBE); 1695 } 1696 } 1697 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1698 } 1699 1700 void 1701 piix_setup_channel(chp) 1702 struct channel_softc *chp; 1703 { 1704 u_int8_t mode[2], drive; 1705 u_int32_t oidetim, idetim, idedma_ctl; 1706 struct pciide_channel *cp = (struct pciide_channel*)chp; 1707 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1708 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1709 1710 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1711 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1712 idedma_ctl = 0; 1713 1714 /* set up new idetim: Enable IDE registers decode */ 1715 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1716 chp->channel); 1717 1718 /* setup DMA */ 1719 pciide_channel_dma_setup(cp); 1720 1721 /* 1722 * Here we have to mess up with drives mode: PIIX can't have 1723 * different timings for master and slave drives. 1724 * We need to find the best combination. 1725 */ 1726 1727 /* If both drives supports DMA, take the lower mode */ 1728 if ((drvp[0].drive_flags & DRIVE_DMA) && 1729 (drvp[1].drive_flags & DRIVE_DMA)) { 1730 mode[0] = mode[1] = 1731 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1732 drvp[0].DMA_mode = mode[0]; 1733 drvp[1].DMA_mode = mode[1]; 1734 goto ok; 1735 } 1736 /* 1737 * If only one drive supports DMA, use its mode, and 1738 * put the other one in PIO mode 0 if mode not compatible 1739 */ 1740 if (drvp[0].drive_flags & DRIVE_DMA) { 1741 mode[0] = drvp[0].DMA_mode; 1742 mode[1] = drvp[1].PIO_mode; 1743 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1744 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1745 mode[1] = drvp[1].PIO_mode = 0; 1746 goto ok; 1747 } 1748 if (drvp[1].drive_flags & DRIVE_DMA) { 1749 mode[1] = drvp[1].DMA_mode; 1750 mode[0] = drvp[0].PIO_mode; 1751 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1752 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1753 mode[0] = drvp[0].PIO_mode = 0; 1754 goto ok; 1755 } 1756 /* 1757 * If both drives are not DMA, takes the lower mode, unless 1758 * one of them is PIO mode < 2 1759 */ 1760 if (drvp[0].PIO_mode < 2) { 1761 mode[0] = drvp[0].PIO_mode = 0; 1762 mode[1] = drvp[1].PIO_mode; 1763 } else if (drvp[1].PIO_mode < 2) { 1764 mode[1] = drvp[1].PIO_mode = 0; 1765 mode[0] = drvp[0].PIO_mode; 1766 } else { 1767 mode[0] = mode[1] = 1768 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1769 drvp[0].PIO_mode = mode[0]; 1770 drvp[1].PIO_mode = mode[1]; 1771 } 1772 ok: /* The modes are setup */ 1773 for (drive = 0; drive < 2; drive++) { 1774 if (drvp[drive].drive_flags & DRIVE_DMA) { 1775 idetim |= piix_setup_idetim_timings( 1776 mode[drive], 1, chp->channel); 1777 goto end; 1778 } 1779 } 1780 /* If we are there, none of the drives are DMA */ 1781 if (mode[0] >= 2) 1782 idetim |= piix_setup_idetim_timings( 1783 mode[0], 0, chp->channel); 1784 else 1785 idetim |= piix_setup_idetim_timings( 1786 mode[1], 0, chp->channel); 1787 end: /* 1788 * timing mode is now set up in the controller. Enable 1789 * it per-drive 1790 */ 1791 for (drive = 0; drive < 2; drive++) { 1792 /* If no drive, skip */ 1793 if ((drvp[drive].drive_flags & DRIVE) == 0) 1794 continue; 1795 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1796 if (drvp[drive].drive_flags & DRIVE_DMA) 1797 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1798 } 1799 if (idedma_ctl != 0) { 1800 /* Add software bits in status register */ 1801 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1802 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1803 idedma_ctl); 1804 } 1805 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1806 pciide_print_modes(cp); 1807 } 1808 1809 void 1810 piix3_4_setup_channel(chp) 1811 struct channel_softc *chp; 1812 { 1813 struct ata_drive_datas *drvp; 1814 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1815 struct pciide_channel *cp = (struct pciide_channel*)chp; 1816 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1817 int drive; 1818 int channel = chp->channel; 1819 1820 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1821 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1822 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1823 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1824 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1825 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1826 PIIX_SIDETIM_RTC_MASK(channel)); 1827 1828 idedma_ctl = 0; 1829 /* If channel disabled, no need to go further */ 1830 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1831 return; 1832 /* set up new idetim: Enable IDE registers decode */ 1833 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1834 1835 /* setup DMA if needed */ 1836 pciide_channel_dma_setup(cp); 1837 1838 for (drive = 0; drive < 2; drive++) { 1839 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1840 PIIX_UDMATIM_SET(0x3, channel, drive)); 1841 drvp = &chp->ch_drive[drive]; 1842 /* If no drive, skip */ 1843 if ((drvp->drive_flags & DRIVE) == 0) 1844 continue; 1845 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1846 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1847 goto pio; 1848 1849 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1850 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1851 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1852 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1853 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1854 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1855 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1856 ideconf |= PIIX_CONFIG_PINGPONG; 1857 } 1858 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1859 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1860 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1861 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1862 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1863 /* setup Ultra/100 */ 1864 if (drvp->UDMA_mode > 2 && 1865 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1866 drvp->UDMA_mode = 2; 1867 if (drvp->UDMA_mode > 4) { 1868 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1869 } else { 1870 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1871 if (drvp->UDMA_mode > 2) { 1872 ideconf |= PIIX_CONFIG_UDMA66(channel, 1873 drive); 1874 } else { 1875 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1876 drive); 1877 } 1878 } 1879 } 1880 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1881 /* setup Ultra/66 */ 1882 if (drvp->UDMA_mode > 2 && 1883 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1884 drvp->UDMA_mode = 2; 1885 if (drvp->UDMA_mode > 2) 1886 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1887 else 1888 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1889 } 1890 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1891 (drvp->drive_flags & DRIVE_UDMA)) { 1892 /* use Ultra/DMA */ 1893 drvp->drive_flags &= ~DRIVE_DMA; 1894 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1895 udmareg |= PIIX_UDMATIM_SET( 1896 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1897 } else { 1898 /* use Multiword DMA */ 1899 drvp->drive_flags &= ~DRIVE_UDMA; 1900 if (drive == 0) { 1901 idetim |= piix_setup_idetim_timings( 1902 drvp->DMA_mode, 1, channel); 1903 } else { 1904 sidetim |= piix_setup_sidetim_timings( 1905 drvp->DMA_mode, 1, channel); 1906 idetim =PIIX_IDETIM_SET(idetim, 1907 PIIX_IDETIM_SITRE, channel); 1908 } 1909 } 1910 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1911 1912 pio: /* use PIO mode */ 1913 idetim |= piix_setup_idetim_drvs(drvp); 1914 if (drive == 0) { 1915 idetim |= piix_setup_idetim_timings( 1916 drvp->PIO_mode, 0, channel); 1917 } else { 1918 sidetim |= piix_setup_sidetim_timings( 1919 drvp->PIO_mode, 0, channel); 1920 idetim =PIIX_IDETIM_SET(idetim, 1921 PIIX_IDETIM_SITRE, channel); 1922 } 1923 } 1924 if (idedma_ctl != 0) { 1925 /* Add software bits in status register */ 1926 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1927 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1928 idedma_ctl); 1929 } 1930 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1931 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1932 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1933 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1934 pciide_print_modes(cp); 1935 } 1936 1937 1938 /* setup ISP and RTC fields, based on mode */ 1939 static u_int32_t 1940 piix_setup_idetim_timings(mode, dma, channel) 1941 u_int8_t mode; 1942 u_int8_t dma; 1943 u_int8_t channel; 1944 { 1945 1946 if (dma) 1947 return PIIX_IDETIM_SET(0, 1948 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1949 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1950 channel); 1951 else 1952 return PIIX_IDETIM_SET(0, 1953 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1954 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1955 channel); 1956 } 1957 1958 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1959 static u_int32_t 1960 piix_setup_idetim_drvs(drvp) 1961 struct ata_drive_datas *drvp; 1962 { 1963 u_int32_t ret = 0; 1964 struct channel_softc *chp = drvp->chnl_softc; 1965 u_int8_t channel = chp->channel; 1966 u_int8_t drive = drvp->drive; 1967 1968 /* 1969 * If drive is using UDMA, timings setups are independant 1970 * So just check DMA and PIO here. 1971 */ 1972 if (drvp->drive_flags & DRIVE_DMA) { 1973 /* if mode = DMA mode 0, use compatible timings */ 1974 if ((drvp->drive_flags & DRIVE_DMA) && 1975 drvp->DMA_mode == 0) { 1976 drvp->PIO_mode = 0; 1977 return ret; 1978 } 1979 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1980 /* 1981 * PIO and DMA timings are the same, use fast timings for PIO 1982 * too, else use compat timings. 1983 */ 1984 if ((piix_isp_pio[drvp->PIO_mode] != 1985 piix_isp_dma[drvp->DMA_mode]) || 1986 (piix_rtc_pio[drvp->PIO_mode] != 1987 piix_rtc_dma[drvp->DMA_mode])) 1988 drvp->PIO_mode = 0; 1989 /* if PIO mode <= 2, use compat timings for PIO */ 1990 if (drvp->PIO_mode <= 2) { 1991 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1992 channel); 1993 return ret; 1994 } 1995 } 1996 1997 /* 1998 * Now setup PIO modes. If mode < 2, use compat timings. 1999 * Else enable fast timings. Enable IORDY and prefetch/post 2000 * if PIO mode >= 3. 2001 */ 2002 2003 if (drvp->PIO_mode < 2) 2004 return ret; 2005 2006 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2007 if (drvp->PIO_mode >= 3) { 2008 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 2009 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 2010 } 2011 return ret; 2012 } 2013 2014 /* setup values in SIDETIM registers, based on mode */ 2015 static u_int32_t 2016 piix_setup_sidetim_timings(mode, dma, channel) 2017 u_int8_t mode; 2018 u_int8_t dma; 2019 u_int8_t channel; 2020 { 2021 if (dma) 2022 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 2023 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 2024 else 2025 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 2026 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 2027 } 2028 2029 void 2030 amd7x6_chip_map(sc, pa) 2031 struct pciide_softc *sc; 2032 struct pci_attach_args *pa; 2033 { 2034 struct pciide_channel *cp; 2035 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2036 int channel; 2037 pcireg_t chanenable; 2038 bus_size_t cmdsize, ctlsize; 2039 2040 if (pciide_chipen(sc, pa) == 0) 2041 return; 2042 printf("%s: bus-master DMA support present", 2043 sc->sc_wdcdev.sc_dev.dv_xname); 2044 pciide_mapreg_dma(sc, pa); 2045 printf("\n"); 2046 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2047 WDC_CAPABILITY_MODE; 2048 if (sc->sc_dma_ok) { 2049 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2050 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2051 sc->sc_wdcdev.irqack = pciide_irqack; 2052 } 2053 sc->sc_wdcdev.PIO_cap = 4; 2054 sc->sc_wdcdev.DMA_cap = 2; 2055 2056 switch (sc->sc_pci_vendor) { 2057 case PCI_VENDOR_AMD: 2058 switch (sc->sc_pp->ide_product) { 2059 case PCI_PRODUCT_AMD_PBC766_IDE: 2060 case PCI_PRODUCT_AMD_PBC768_IDE: 2061 case PCI_PRODUCT_AMD_PBC8111_IDE: 2062 sc->sc_wdcdev.UDMA_cap = 5; 2063 break; 2064 default: 2065 sc->sc_wdcdev.UDMA_cap = 4; 2066 } 2067 sc->sc_amd_regbase = AMD7X6_AMD_REGBASE; 2068 break; 2069 2070 case PCI_VENDOR_NVIDIA: 2071 switch (sc->sc_pp->ide_product) { 2072 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 2073 sc->sc_wdcdev.UDMA_cap = 5; 2074 break; 2075 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 2076 sc->sc_wdcdev.UDMA_cap = 6; 2077 break; 2078 } 2079 sc->sc_amd_regbase = AMD7X6_NVIDIA_REGBASE; 2080 break; 2081 2082 default: 2083 panic("amd7x6_chip_map: unknown vendor"); 2084 } 2085 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 2086 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2087 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2088 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, 2089 AMD7X6_CHANSTATUS_EN(sc)); 2090 2091 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 2092 DEBUG_PROBE); 2093 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2094 cp = &sc->pciide_channels[channel]; 2095 if (pciide_chansetup(sc, channel, interface) == 0) 2096 continue; 2097 2098 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 2099 printf("%s: %s channel ignored (disabled)\n", 2100 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2101 continue; 2102 } 2103 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2104 pciide_pci_intr); 2105 2106 if (pciide_chan_candisable(cp)) 2107 chanenable &= ~AMD7X6_CHAN_EN(channel); 2108 pciide_map_compat_intr(pa, cp, channel, interface); 2109 if (cp->hw_ok == 0) 2110 continue; 2111 2112 amd7x6_setup_channel(&cp->wdc_channel); 2113 } 2114 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN(sc), 2115 chanenable); 2116 return; 2117 } 2118 2119 void 2120 amd7x6_setup_channel(chp) 2121 struct channel_softc *chp; 2122 { 2123 u_int32_t udmatim_reg, datatim_reg; 2124 u_int8_t idedma_ctl; 2125 int mode, drive; 2126 struct ata_drive_datas *drvp; 2127 struct pciide_channel *cp = (struct pciide_channel*)chp; 2128 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2129 #ifndef PCIIDE_AMD756_ENABLEDMA 2130 int rev = PCI_REVISION( 2131 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2132 #endif 2133 2134 idedma_ctl = 0; 2135 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc)); 2136 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc)); 2137 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2138 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2139 2140 /* setup DMA if needed */ 2141 pciide_channel_dma_setup(cp); 2142 2143 for (drive = 0; drive < 2; drive++) { 2144 drvp = &chp->ch_drive[drive]; 2145 /* If no drive, skip */ 2146 if ((drvp->drive_flags & DRIVE) == 0) 2147 continue; 2148 /* add timing values, setup DMA if needed */ 2149 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2150 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2151 mode = drvp->PIO_mode; 2152 goto pio; 2153 } 2154 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2155 (drvp->drive_flags & DRIVE_UDMA)) { 2156 /* use Ultra/DMA */ 2157 drvp->drive_flags &= ~DRIVE_DMA; 2158 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2159 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2160 AMD7X6_UDMA_TIME(chp->channel, drive, 2161 amd7x6_udma_tim[drvp->UDMA_mode]); 2162 /* can use PIO timings, MW DMA unused */ 2163 mode = drvp->PIO_mode; 2164 } else { 2165 /* use Multiword DMA, but only if revision is OK */ 2166 drvp->drive_flags &= ~DRIVE_UDMA; 2167 #ifndef PCIIDE_AMD756_ENABLEDMA 2168 /* 2169 * The workaround doesn't seem to be necessary 2170 * with all drives, so it can be disabled by 2171 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2172 * triggered. 2173 */ 2174 if (sc->sc_pci_vendor == PCI_VENDOR_AMD && 2175 sc->sc_pp->ide_product == 2176 PCI_PRODUCT_AMD_PBC756_IDE && 2177 AMD756_CHIPREV_DISABLEDMA(rev)) { 2178 printf("%s:%d:%d: multi-word DMA disabled due " 2179 "to chip revision\n", 2180 sc->sc_wdcdev.sc_dev.dv_xname, 2181 chp->channel, drive); 2182 mode = drvp->PIO_mode; 2183 drvp->drive_flags &= ~DRIVE_DMA; 2184 goto pio; 2185 } 2186 #endif 2187 /* mode = min(pio, dma+2) */ 2188 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2189 mode = drvp->PIO_mode; 2190 else 2191 mode = drvp->DMA_mode + 2; 2192 } 2193 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2194 2195 pio: /* setup PIO mode */ 2196 if (mode <= 2) { 2197 drvp->DMA_mode = 0; 2198 drvp->PIO_mode = 0; 2199 mode = 0; 2200 } else { 2201 drvp->PIO_mode = mode; 2202 drvp->DMA_mode = mode - 2; 2203 } 2204 datatim_reg |= 2205 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2206 amd7x6_pio_set[mode]) | 2207 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2208 amd7x6_pio_rec[mode]); 2209 } 2210 if (idedma_ctl != 0) { 2211 /* Add software bits in status register */ 2212 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2213 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2214 idedma_ctl); 2215 } 2216 pciide_print_modes(cp); 2217 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc), datatim_reg); 2218 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc), udmatim_reg); 2219 } 2220 2221 void 2222 apollo_chip_map(sc, pa) 2223 struct pciide_softc *sc; 2224 struct pci_attach_args *pa; 2225 { 2226 struct pciide_channel *cp; 2227 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2228 int channel; 2229 u_int32_t ideconf; 2230 bus_size_t cmdsize, ctlsize; 2231 pcitag_t pcib_tag; 2232 pcireg_t pcib_id, pcib_class; 2233 2234 if (pciide_chipen(sc, pa) == 0) 2235 return; 2236 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2237 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2238 /* and read ID and rev of the ISA bridge */ 2239 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2240 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2241 printf(": VIA Technologies "); 2242 switch (PCI_PRODUCT(pcib_id)) { 2243 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2244 printf("VT82C586 (Apollo VP) "); 2245 if(PCI_REVISION(pcib_class) >= 0x02) { 2246 printf("ATA33 controller\n"); 2247 sc->sc_wdcdev.UDMA_cap = 2; 2248 } else { 2249 printf("controller\n"); 2250 sc->sc_wdcdev.UDMA_cap = 0; 2251 } 2252 break; 2253 case PCI_PRODUCT_VIATECH_VT82C596A: 2254 printf("VT82C596A (Apollo Pro) "); 2255 if (PCI_REVISION(pcib_class) >= 0x12) { 2256 printf("ATA66 controller\n"); 2257 sc->sc_wdcdev.UDMA_cap = 4; 2258 } else { 2259 printf("ATA33 controller\n"); 2260 sc->sc_wdcdev.UDMA_cap = 2; 2261 } 2262 break; 2263 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2264 printf("VT82C686A (Apollo KX133) "); 2265 if (PCI_REVISION(pcib_class) >= 0x40) { 2266 printf("ATA100 controller\n"); 2267 sc->sc_wdcdev.UDMA_cap = 5; 2268 } else { 2269 printf("ATA66 controller\n"); 2270 sc->sc_wdcdev.UDMA_cap = 4; 2271 } 2272 break; 2273 case PCI_PRODUCT_VIATECH_VT8231: 2274 printf("VT8231 ATA100 controller\n"); 2275 sc->sc_wdcdev.UDMA_cap = 5; 2276 break; 2277 case PCI_PRODUCT_VIATECH_VT8233: 2278 printf("VT8233 ATA100 controller\n"); 2279 sc->sc_wdcdev.UDMA_cap = 5; 2280 break; 2281 case PCI_PRODUCT_VIATECH_VT8233A: 2282 printf("VT8233A ATA133 controller\n"); 2283 sc->sc_wdcdev.UDMA_cap = 6; 2284 break; 2285 case PCI_PRODUCT_VIATECH_VT8235: 2286 printf("VT8235 ATA133 controller\n"); 2287 sc->sc_wdcdev.UDMA_cap = 6; 2288 break; 2289 default: 2290 printf("unknown ATA controller\n"); 2291 sc->sc_wdcdev.UDMA_cap = 0; 2292 } 2293 2294 printf("%s: bus-master DMA support present", 2295 sc->sc_wdcdev.sc_dev.dv_xname); 2296 pciide_mapreg_dma(sc, pa); 2297 printf("\n"); 2298 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2299 WDC_CAPABILITY_MODE; 2300 if (sc->sc_dma_ok) { 2301 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2302 sc->sc_wdcdev.irqack = pciide_irqack; 2303 if (sc->sc_wdcdev.UDMA_cap > 0) 2304 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2305 } 2306 sc->sc_wdcdev.PIO_cap = 4; 2307 sc->sc_wdcdev.DMA_cap = 2; 2308 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2309 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2310 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2311 2312 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2313 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2314 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2315 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2316 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2317 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2318 DEBUG_PROBE); 2319 2320 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2321 cp = &sc->pciide_channels[channel]; 2322 if (pciide_chansetup(sc, channel, interface) == 0) 2323 continue; 2324 2325 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2326 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2327 printf("%s: %s channel ignored (disabled)\n", 2328 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2329 continue; 2330 } 2331 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2332 pciide_pci_intr); 2333 if (cp->hw_ok == 0) 2334 continue; 2335 if (pciide_chan_candisable(cp)) { 2336 ideconf &= ~APO_IDECONF_EN(channel); 2337 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2338 ideconf); 2339 } 2340 pciide_map_compat_intr(pa, cp, channel, interface); 2341 2342 if (cp->hw_ok == 0) 2343 continue; 2344 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2345 } 2346 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2347 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2348 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2349 } 2350 2351 void 2352 apollo_setup_channel(chp) 2353 struct channel_softc *chp; 2354 { 2355 u_int32_t udmatim_reg, datatim_reg; 2356 u_int8_t idedma_ctl; 2357 int mode, drive; 2358 struct ata_drive_datas *drvp; 2359 struct pciide_channel *cp = (struct pciide_channel*)chp; 2360 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2361 2362 idedma_ctl = 0; 2363 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2364 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2365 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2366 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2367 2368 /* setup DMA if needed */ 2369 pciide_channel_dma_setup(cp); 2370 2371 for (drive = 0; drive < 2; drive++) { 2372 drvp = &chp->ch_drive[drive]; 2373 /* If no drive, skip */ 2374 if ((drvp->drive_flags & DRIVE) == 0) 2375 continue; 2376 /* add timing values, setup DMA if needed */ 2377 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2378 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2379 mode = drvp->PIO_mode; 2380 goto pio; 2381 } 2382 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2383 (drvp->drive_flags & DRIVE_UDMA)) { 2384 /* use Ultra/DMA */ 2385 drvp->drive_flags &= ~DRIVE_DMA; 2386 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2387 APO_UDMA_EN_MTH(chp->channel, drive); 2388 if (sc->sc_wdcdev.UDMA_cap == 6) { 2389 /* 8233a */ 2390 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2391 drive, apollo_udma133_tim[drvp->UDMA_mode]); 2392 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 2393 /* 686b */ 2394 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2395 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2396 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2397 /* 596b or 686a */ 2398 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2399 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2400 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2401 } else { 2402 /* 596a or 586b */ 2403 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2404 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2405 } 2406 /* can use PIO timings, MW DMA unused */ 2407 mode = drvp->PIO_mode; 2408 } else { 2409 /* use Multiword DMA */ 2410 drvp->drive_flags &= ~DRIVE_UDMA; 2411 /* mode = min(pio, dma+2) */ 2412 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2413 mode = drvp->PIO_mode; 2414 else 2415 mode = drvp->DMA_mode + 2; 2416 } 2417 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2418 2419 pio: /* setup PIO mode */ 2420 if (mode <= 2) { 2421 drvp->DMA_mode = 0; 2422 drvp->PIO_mode = 0; 2423 mode = 0; 2424 } else { 2425 drvp->PIO_mode = mode; 2426 drvp->DMA_mode = mode - 2; 2427 } 2428 datatim_reg |= 2429 APO_DATATIM_PULSE(chp->channel, drive, 2430 apollo_pio_set[mode]) | 2431 APO_DATATIM_RECOV(chp->channel, drive, 2432 apollo_pio_rec[mode]); 2433 } 2434 if (idedma_ctl != 0) { 2435 /* Add software bits in status register */ 2436 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2437 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2438 idedma_ctl); 2439 } 2440 pciide_print_modes(cp); 2441 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2442 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2443 } 2444 2445 void 2446 cmd_channel_map(pa, sc, channel) 2447 struct pci_attach_args *pa; 2448 struct pciide_softc *sc; 2449 int channel; 2450 { 2451 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2452 bus_size_t cmdsize, ctlsize; 2453 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2454 int interface, one_channel; 2455 2456 /* 2457 * The 0648/0649 can be told to identify as a RAID controller. 2458 * In this case, we have to fake interface 2459 */ 2460 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2461 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2462 PCIIDE_INTERFACE_SETTABLE(1); 2463 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2464 CMD_CONF_DSA1) 2465 interface |= PCIIDE_INTERFACE_PCI(0) | 2466 PCIIDE_INTERFACE_PCI(1); 2467 } else { 2468 interface = PCI_INTERFACE(pa->pa_class); 2469 } 2470 2471 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2472 cp->name = PCIIDE_CHANNEL_NAME(channel); 2473 cp->wdc_channel.channel = channel; 2474 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2475 2476 /* 2477 * Older CMD64X doesn't have independant channels 2478 */ 2479 switch (sc->sc_pp->ide_product) { 2480 case PCI_PRODUCT_CMDTECH_649: 2481 one_channel = 0; 2482 break; 2483 default: 2484 one_channel = 1; 2485 break; 2486 } 2487 2488 if (channel > 0 && one_channel) { 2489 cp->wdc_channel.ch_queue = 2490 sc->pciide_channels[0].wdc_channel.ch_queue; 2491 } else { 2492 cp->wdc_channel.ch_queue = 2493 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2494 } 2495 if (cp->wdc_channel.ch_queue == NULL) { 2496 printf("%s %s channel: " 2497 "can't allocate memory for command queue", 2498 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2499 return; 2500 } 2501 2502 printf("%s: %s channel %s to %s mode\n", 2503 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2504 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2505 "configured" : "wired", 2506 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2507 "native-PCI" : "compatibility"); 2508 2509 /* 2510 * with a CMD PCI64x, if we get here, the first channel is enabled: 2511 * there's no way to disable the first channel without disabling 2512 * the whole device 2513 */ 2514 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2515 printf("%s: %s channel ignored (disabled)\n", 2516 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2517 return; 2518 } 2519 2520 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2521 if (cp->hw_ok == 0) 2522 return; 2523 if (channel == 1) { 2524 if (pciide_chan_candisable(cp)) { 2525 ctrl &= ~CMD_CTRL_2PORT; 2526 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2527 CMD_CTRL, ctrl); 2528 } 2529 } 2530 pciide_map_compat_intr(pa, cp, channel, interface); 2531 } 2532 2533 int 2534 cmd_pci_intr(arg) 2535 void *arg; 2536 { 2537 struct pciide_softc *sc = arg; 2538 struct pciide_channel *cp; 2539 struct channel_softc *wdc_cp; 2540 int i, rv, crv; 2541 u_int32_t priirq, secirq; 2542 2543 rv = 0; 2544 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2545 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2546 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2547 cp = &sc->pciide_channels[i]; 2548 wdc_cp = &cp->wdc_channel; 2549 /* If a compat channel skip. */ 2550 if (cp->compat) 2551 continue; 2552 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2553 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2554 crv = wdcintr(wdc_cp); 2555 if (crv == 0) 2556 printf("%s:%d: bogus intr\n", 2557 sc->sc_wdcdev.sc_dev.dv_xname, i); 2558 else 2559 rv = 1; 2560 } 2561 } 2562 return rv; 2563 } 2564 2565 void 2566 cmd_chip_map(sc, pa) 2567 struct pciide_softc *sc; 2568 struct pci_attach_args *pa; 2569 { 2570 int channel; 2571 2572 /* 2573 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2574 * and base adresses registers can be disabled at 2575 * hardware level. In this case, the device is wired 2576 * in compat mode and its first channel is always enabled, 2577 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2578 * In fact, it seems that the first channel of the CMD PCI0640 2579 * can't be disabled. 2580 */ 2581 2582 #ifdef PCIIDE_CMD064x_DISABLE 2583 if (pciide_chipen(sc, pa) == 0) 2584 return; 2585 #endif 2586 2587 printf("%s: hardware does not support DMA\n", 2588 sc->sc_wdcdev.sc_dev.dv_xname); 2589 sc->sc_dma_ok = 0; 2590 2591 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2592 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2593 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2594 2595 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2596 cmd_channel_map(pa, sc, channel); 2597 } 2598 } 2599 2600 void 2601 cmd0643_9_chip_map(sc, pa) 2602 struct pciide_softc *sc; 2603 struct pci_attach_args *pa; 2604 { 2605 struct pciide_channel *cp; 2606 int channel; 2607 pcireg_t rev = PCI_REVISION(pa->pa_class); 2608 2609 /* 2610 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2611 * and base adresses registers can be disabled at 2612 * hardware level. In this case, the device is wired 2613 * in compat mode and its first channel is always enabled, 2614 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2615 * In fact, it seems that the first channel of the CMD PCI0640 2616 * can't be disabled. 2617 */ 2618 2619 #ifdef PCIIDE_CMD064x_DISABLE 2620 if (pciide_chipen(sc, pa) == 0) 2621 return; 2622 #endif 2623 printf("%s: bus-master DMA support present", 2624 sc->sc_wdcdev.sc_dev.dv_xname); 2625 pciide_mapreg_dma(sc, pa); 2626 printf("\n"); 2627 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2628 WDC_CAPABILITY_MODE; 2629 if (sc->sc_dma_ok) { 2630 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2631 switch (sc->sc_pp->ide_product) { 2632 case PCI_PRODUCT_CMDTECH_649: 2633 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2634 sc->sc_wdcdev.UDMA_cap = 5; 2635 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2636 break; 2637 case PCI_PRODUCT_CMDTECH_648: 2638 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2639 sc->sc_wdcdev.UDMA_cap = 4; 2640 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2641 break; 2642 case PCI_PRODUCT_CMDTECH_646: 2643 if (rev >= CMD0646U2_REV) { 2644 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2645 sc->sc_wdcdev.UDMA_cap = 2; 2646 } else if (rev >= CMD0646U_REV) { 2647 /* 2648 * Linux's driver claims that the 646U is broken 2649 * with UDMA. Only enable it if we know what we're 2650 * doing 2651 */ 2652 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2653 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2654 sc->sc_wdcdev.UDMA_cap = 2; 2655 #endif 2656 /* explicitly disable UDMA */ 2657 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2658 CMD_UDMATIM(0), 0); 2659 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2660 CMD_UDMATIM(1), 0); 2661 } 2662 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2663 break; 2664 default: 2665 sc->sc_wdcdev.irqack = pciide_irqack; 2666 } 2667 } 2668 2669 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2670 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2671 sc->sc_wdcdev.PIO_cap = 4; 2672 sc->sc_wdcdev.DMA_cap = 2; 2673 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2674 2675 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2676 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2677 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2678 DEBUG_PROBE); 2679 2680 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2681 cp = &sc->pciide_channels[channel]; 2682 cmd_channel_map(pa, sc, channel); 2683 if (cp->hw_ok == 0) 2684 continue; 2685 cmd0643_9_setup_channel(&cp->wdc_channel); 2686 } 2687 /* 2688 * note - this also makes sure we clear the irq disable and reset 2689 * bits 2690 */ 2691 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2692 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2693 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2694 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2695 DEBUG_PROBE); 2696 } 2697 2698 void 2699 cmd0643_9_setup_channel(chp) 2700 struct channel_softc *chp; 2701 { 2702 struct ata_drive_datas *drvp; 2703 u_int8_t tim; 2704 u_int32_t idedma_ctl, udma_reg; 2705 int drive; 2706 struct pciide_channel *cp = (struct pciide_channel*)chp; 2707 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2708 2709 idedma_ctl = 0; 2710 /* setup DMA if needed */ 2711 pciide_channel_dma_setup(cp); 2712 2713 for (drive = 0; drive < 2; drive++) { 2714 drvp = &chp->ch_drive[drive]; 2715 /* If no drive, skip */ 2716 if ((drvp->drive_flags & DRIVE) == 0) 2717 continue; 2718 /* add timing values, setup DMA if needed */ 2719 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2720 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2721 if (drvp->drive_flags & DRIVE_UDMA) { 2722 /* UltraDMA on a 646U2, 0648 or 0649 */ 2723 drvp->drive_flags &= ~DRIVE_DMA; 2724 udma_reg = pciide_pci_read(sc->sc_pc, 2725 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2726 if (drvp->UDMA_mode > 2 && 2727 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2728 CMD_BICSR) & 2729 CMD_BICSR_80(chp->channel)) == 0) 2730 drvp->UDMA_mode = 2; 2731 if (drvp->UDMA_mode > 2) 2732 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2733 else if (sc->sc_wdcdev.UDMA_cap > 2) 2734 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2735 udma_reg |= CMD_UDMATIM_UDMA(drive); 2736 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2737 CMD_UDMATIM_TIM_OFF(drive)); 2738 udma_reg |= 2739 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2740 CMD_UDMATIM_TIM_OFF(drive)); 2741 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2742 CMD_UDMATIM(chp->channel), udma_reg); 2743 } else { 2744 /* 2745 * use Multiword DMA. 2746 * Timings will be used for both PIO and DMA, 2747 * so adjust DMA mode if needed 2748 * if we have a 0646U2/8/9, turn off UDMA 2749 */ 2750 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2751 udma_reg = pciide_pci_read(sc->sc_pc, 2752 sc->sc_tag, 2753 CMD_UDMATIM(chp->channel)); 2754 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2755 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2756 CMD_UDMATIM(chp->channel), 2757 udma_reg); 2758 } 2759 if (drvp->PIO_mode >= 3 && 2760 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2761 drvp->DMA_mode = drvp->PIO_mode - 2; 2762 } 2763 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2764 } 2765 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2766 } 2767 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2768 CMD_DATA_TIM(chp->channel, drive), tim); 2769 } 2770 if (idedma_ctl != 0) { 2771 /* Add software bits in status register */ 2772 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2773 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2774 idedma_ctl); 2775 } 2776 pciide_print_modes(cp); 2777 } 2778 2779 void 2780 cmd646_9_irqack(chp) 2781 struct channel_softc *chp; 2782 { 2783 u_int32_t priirq, secirq; 2784 struct pciide_channel *cp = (struct pciide_channel*)chp; 2785 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2786 2787 if (chp->channel == 0) { 2788 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2789 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2790 } else { 2791 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2792 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2793 } 2794 pciide_irqack(chp); 2795 } 2796 2797 void 2798 cmd680_chip_map(sc, pa) 2799 struct pciide_softc *sc; 2800 struct pci_attach_args *pa; 2801 { 2802 struct pciide_channel *cp; 2803 int channel; 2804 2805 if (pciide_chipen(sc, pa) == 0) 2806 return; 2807 printf("%s: bus-master DMA support present", 2808 sc->sc_wdcdev.sc_dev.dv_xname); 2809 pciide_mapreg_dma(sc, pa); 2810 printf("\n"); 2811 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2812 WDC_CAPABILITY_MODE; 2813 if (sc->sc_dma_ok) { 2814 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2815 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2816 sc->sc_wdcdev.UDMA_cap = 6; 2817 sc->sc_wdcdev.irqack = pciide_irqack; 2818 } 2819 2820 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2821 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2822 sc->sc_wdcdev.PIO_cap = 4; 2823 sc->sc_wdcdev.DMA_cap = 2; 2824 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 2825 2826 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 2827 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 2828 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 2829 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 2830 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2831 cp = &sc->pciide_channels[channel]; 2832 cmd680_channel_map(pa, sc, channel); 2833 if (cp->hw_ok == 0) 2834 continue; 2835 cmd680_setup_channel(&cp->wdc_channel); 2836 } 2837 } 2838 2839 void 2840 cmd680_channel_map(pa, sc, channel) 2841 struct pci_attach_args *pa; 2842 struct pciide_softc *sc; 2843 int channel; 2844 { 2845 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2846 bus_size_t cmdsize, ctlsize; 2847 int interface, i, reg; 2848 static const u_int8_t init_val[] = 2849 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 2850 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 2851 2852 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2853 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2854 PCIIDE_INTERFACE_SETTABLE(1); 2855 interface |= PCIIDE_INTERFACE_PCI(0) | 2856 PCIIDE_INTERFACE_PCI(1); 2857 } else { 2858 interface = PCI_INTERFACE(pa->pa_class); 2859 } 2860 2861 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2862 cp->name = PCIIDE_CHANNEL_NAME(channel); 2863 cp->wdc_channel.channel = channel; 2864 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2865 2866 cp->wdc_channel.ch_queue = 2867 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2868 if (cp->wdc_channel.ch_queue == NULL) { 2869 printf("%s %s channel: " 2870 "can't allocate memory for command queue", 2871 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2872 return; 2873 } 2874 2875 /* XXX */ 2876 reg = 0xa2 + channel * 16; 2877 for (i = 0; i < sizeof(init_val); i++) 2878 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 2879 2880 printf("%s: %s channel %s to %s mode\n", 2881 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2882 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2883 "configured" : "wired", 2884 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2885 "native-PCI" : "compatibility"); 2886 2887 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 2888 if (cp->hw_ok == 0) 2889 return; 2890 pciide_map_compat_intr(pa, cp, channel, interface); 2891 } 2892 2893 void 2894 cmd680_setup_channel(chp) 2895 struct channel_softc *chp; 2896 { 2897 struct ata_drive_datas *drvp; 2898 u_int8_t mode, off, scsc; 2899 u_int16_t val; 2900 u_int32_t idedma_ctl; 2901 int drive; 2902 struct pciide_channel *cp = (struct pciide_channel*)chp; 2903 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2904 pci_chipset_tag_t pc = sc->sc_pc; 2905 pcitag_t pa = sc->sc_tag; 2906 static const u_int8_t udma2_tbl[] = 2907 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 2908 static const u_int8_t udma_tbl[] = 2909 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 2910 static const u_int16_t dma_tbl[] = 2911 { 0x2208, 0x10c2, 0x10c1 }; 2912 static const u_int16_t pio_tbl[] = 2913 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 2914 2915 idedma_ctl = 0; 2916 pciide_channel_dma_setup(cp); 2917 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 2918 2919 for (drive = 0; drive < 2; drive++) { 2920 drvp = &chp->ch_drive[drive]; 2921 /* If no drive, skip */ 2922 if ((drvp->drive_flags & DRIVE) == 0) 2923 continue; 2924 mode &= ~(0x03 << (drive * 4)); 2925 if (drvp->drive_flags & DRIVE_UDMA) { 2926 drvp->drive_flags &= ~DRIVE_DMA; 2927 off = 0xa0 + chp->channel * 16; 2928 if (drvp->UDMA_mode > 2 && 2929 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 2930 drvp->UDMA_mode = 2; 2931 scsc = pciide_pci_read(pc, pa, 0x8a); 2932 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 2933 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 2934 scsc = pciide_pci_read(pc, pa, 0x8a); 2935 if ((scsc & 0x30) == 0) 2936 drvp->UDMA_mode = 5; 2937 } 2938 mode |= 0x03 << (drive * 4); 2939 off = 0xac + chp->channel * 16 + drive * 2; 2940 val = pciide_pci_read(pc, pa, off) & ~0x3f; 2941 if (scsc & 0x30) 2942 val |= udma2_tbl[drvp->UDMA_mode]; 2943 else 2944 val |= udma_tbl[drvp->UDMA_mode]; 2945 pciide_pci_write(pc, pa, off, val); 2946 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2947 } else if (drvp->drive_flags & DRIVE_DMA) { 2948 mode |= 0x02 << (drive * 4); 2949 off = 0xa8 + chp->channel * 16 + drive * 2; 2950 val = dma_tbl[drvp->DMA_mode]; 2951 pciide_pci_write(pc, pa, off, val & 0xff); 2952 pciide_pci_write(pc, pa, off, val >> 8); 2953 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2954 } else { 2955 mode |= 0x01 << (drive * 4); 2956 off = 0xa4 + chp->channel * 16 + drive * 2; 2957 val = pio_tbl[drvp->PIO_mode]; 2958 pciide_pci_write(pc, pa, off, val & 0xff); 2959 pciide_pci_write(pc, pa, off, val >> 8); 2960 } 2961 } 2962 2963 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 2964 if (idedma_ctl != 0) { 2965 /* Add software bits in status register */ 2966 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2967 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2968 idedma_ctl); 2969 } 2970 pciide_print_modes(cp); 2971 } 2972 2973 void 2974 cy693_chip_map(sc, pa) 2975 struct pciide_softc *sc; 2976 struct pci_attach_args *pa; 2977 { 2978 struct pciide_channel *cp; 2979 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2980 bus_size_t cmdsize, ctlsize; 2981 2982 if (pciide_chipen(sc, pa) == 0) 2983 return; 2984 /* 2985 * this chip has 2 PCI IDE functions, one for primary and one for 2986 * secondary. So we need to call pciide_mapregs_compat() with 2987 * the real channel 2988 */ 2989 if (pa->pa_function == 1) { 2990 sc->sc_cy_compatchan = 0; 2991 } else if (pa->pa_function == 2) { 2992 sc->sc_cy_compatchan = 1; 2993 } else { 2994 printf("%s: unexpected PCI function %d\n", 2995 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2996 return; 2997 } 2998 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2999 printf("%s: bus-master DMA support present", 3000 sc->sc_wdcdev.sc_dev.dv_xname); 3001 pciide_mapreg_dma(sc, pa); 3002 } else { 3003 printf("%s: hardware does not support DMA", 3004 sc->sc_wdcdev.sc_dev.dv_xname); 3005 sc->sc_dma_ok = 0; 3006 } 3007 printf("\n"); 3008 3009 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 3010 if (sc->sc_cy_handle == NULL) { 3011 printf("%s: unable to map hyperCache control registers\n", 3012 sc->sc_wdcdev.sc_dev.dv_xname); 3013 sc->sc_dma_ok = 0; 3014 } 3015 3016 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3017 WDC_CAPABILITY_MODE; 3018 if (sc->sc_dma_ok) { 3019 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3020 sc->sc_wdcdev.irqack = pciide_irqack; 3021 } 3022 sc->sc_wdcdev.PIO_cap = 4; 3023 sc->sc_wdcdev.DMA_cap = 2; 3024 sc->sc_wdcdev.set_modes = cy693_setup_channel; 3025 3026 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3027 sc->sc_wdcdev.nchannels = 1; 3028 3029 /* Only one channel for this chip; if we are here it's enabled */ 3030 cp = &sc->pciide_channels[0]; 3031 sc->wdc_chanarray[0] = &cp->wdc_channel; 3032 cp->name = PCIIDE_CHANNEL_NAME(0); 3033 cp->wdc_channel.channel = 0; 3034 cp->wdc_channel.wdc = &sc->sc_wdcdev; 3035 cp->wdc_channel.ch_queue = 3036 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 3037 if (cp->wdc_channel.ch_queue == NULL) { 3038 printf("%s primary channel: " 3039 "can't allocate memory for command queue", 3040 sc->sc_wdcdev.sc_dev.dv_xname); 3041 return; 3042 } 3043 printf("%s: primary channel %s to ", 3044 sc->sc_wdcdev.sc_dev.dv_xname, 3045 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 3046 "configured" : "wired"); 3047 if (interface & PCIIDE_INTERFACE_PCI(0)) { 3048 printf("native-PCI"); 3049 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 3050 pciide_pci_intr); 3051 } else { 3052 printf("compatibility"); 3053 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 3054 &cmdsize, &ctlsize); 3055 } 3056 printf(" mode\n"); 3057 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3058 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3059 wdcattach(&cp->wdc_channel); 3060 if (pciide_chan_candisable(cp)) { 3061 pci_conf_write(sc->sc_pc, sc->sc_tag, 3062 PCI_COMMAND_STATUS_REG, 0); 3063 } 3064 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 3065 if (cp->hw_ok == 0) 3066 return; 3067 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 3068 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 3069 cy693_setup_channel(&cp->wdc_channel); 3070 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 3071 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 3072 } 3073 3074 void 3075 cy693_setup_channel(chp) 3076 struct channel_softc *chp; 3077 { 3078 struct ata_drive_datas *drvp; 3079 int drive; 3080 u_int32_t cy_cmd_ctrl; 3081 u_int32_t idedma_ctl; 3082 struct pciide_channel *cp = (struct pciide_channel*)chp; 3083 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3084 int dma_mode = -1; 3085 3086 cy_cmd_ctrl = idedma_ctl = 0; 3087 3088 /* setup DMA if needed */ 3089 pciide_channel_dma_setup(cp); 3090 3091 for (drive = 0; drive < 2; drive++) { 3092 drvp = &chp->ch_drive[drive]; 3093 /* If no drive, skip */ 3094 if ((drvp->drive_flags & DRIVE) == 0) 3095 continue; 3096 /* add timing values, setup DMA if needed */ 3097 if (drvp->drive_flags & DRIVE_DMA) { 3098 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3099 /* use Multiword DMA */ 3100 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 3101 dma_mode = drvp->DMA_mode; 3102 } 3103 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3104 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 3105 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3106 CY_CMD_CTRL_IOW_REC_OFF(drive)); 3107 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3108 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 3109 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3110 CY_CMD_CTRL_IOR_REC_OFF(drive)); 3111 } 3112 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 3113 chp->ch_drive[0].DMA_mode = dma_mode; 3114 chp->ch_drive[1].DMA_mode = dma_mode; 3115 3116 if (dma_mode == -1) 3117 dma_mode = 0; 3118 3119 if (sc->sc_cy_handle != NULL) { 3120 /* Note: `multiple' is implied. */ 3121 cy82c693_write(sc->sc_cy_handle, 3122 (sc->sc_cy_compatchan == 0) ? 3123 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 3124 } 3125 3126 pciide_print_modes(cp); 3127 3128 if (idedma_ctl != 0) { 3129 /* Add software bits in status register */ 3130 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3131 IDEDMA_CTL, idedma_ctl); 3132 } 3133 } 3134 3135 static struct sis_hostbr_type { 3136 u_int16_t id; 3137 u_int8_t rev; 3138 u_int8_t udma_mode; 3139 char *name; 3140 u_int8_t type; 3141 #define SIS_TYPE_NOUDMA 0 3142 #define SIS_TYPE_66 1 3143 #define SIS_TYPE_100OLD 2 3144 #define SIS_TYPE_100NEW 3 3145 #define SIS_TYPE_133OLD 4 3146 #define SIS_TYPE_133NEW 5 3147 #define SIS_TYPE_SOUTH 6 3148 } sis_hostbr_type[] = { 3149 /* Most infos here are from sos (at) freebsd.org */ 3150 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 3151 #if 0 3152 /* 3153 * controllers associated to a rev 0x2 530 Host to PCI Bridge 3154 * have problems with UDMA (info provided by Christos) 3155 */ 3156 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 3157 #endif 3158 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 3159 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 3160 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 3161 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 3162 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 3163 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 3164 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 3165 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 3166 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 3167 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 3168 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 3169 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 3170 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 3171 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 3172 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 3173 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 3174 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 3175 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 3176 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 3177 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 3178 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 3179 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 3180 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 3181 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 3182 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 3183 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 3184 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 3185 /* 3186 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 3187 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 3188 */ 3189 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 3190 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 3191 }; 3192 3193 static struct sis_hostbr_type *sis_hostbr_type_match; 3194 3195 static int 3196 sis_hostbr_match(pa) 3197 struct pci_attach_args *pa; 3198 { 3199 int i; 3200 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 3201 return 0; 3202 sis_hostbr_type_match = NULL; 3203 for (i = 0; 3204 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 3205 i++) { 3206 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 3207 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 3208 sis_hostbr_type_match = &sis_hostbr_type[i]; 3209 } 3210 return (sis_hostbr_type_match != NULL); 3211 } 3212 3213 static int sis_south_match(pa) 3214 struct pci_attach_args *pa; 3215 { 3216 return(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 3217 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 3218 PCI_REVISION(pa->pa_class) >= 0x10); 3219 } 3220 3221 void 3222 sis_chip_map(sc, pa) 3223 struct pciide_softc *sc; 3224 struct pci_attach_args *pa; 3225 { 3226 struct pciide_channel *cp; 3227 int channel; 3228 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 3229 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3230 pcireg_t rev = PCI_REVISION(pa->pa_class); 3231 bus_size_t cmdsize, ctlsize; 3232 3233 if (pciide_chipen(sc, pa) == 0) 3234 return; 3235 printf(": Silicon Integrated System "); 3236 pci_find_device(NULL, sis_hostbr_match); 3237 if (sis_hostbr_type_match) { 3238 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 3239 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 3240 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3241 SIS_REG_57) & 0x7f); 3242 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 3243 PCI_ID_REG)) == SIS_PRODUCT_5518) { 3244 printf("96X UDMA%d", 3245 sis_hostbr_type_match->udma_mode); 3246 sc->sis_type = SIS_TYPE_133NEW; 3247 sc->sc_wdcdev.UDMA_cap = 3248 sis_hostbr_type_match->udma_mode; 3249 } else { 3250 if (pci_find_device(NULL, sis_south_match)) { 3251 sc->sis_type = SIS_TYPE_133OLD; 3252 sc->sc_wdcdev.UDMA_cap = 3253 sis_hostbr_type_match->udma_mode; 3254 } else { 3255 sc->sis_type = SIS_TYPE_100NEW; 3256 sc->sc_wdcdev.UDMA_cap = 3257 sis_hostbr_type_match->udma_mode; 3258 } 3259 } 3260 } else { 3261 sc->sis_type = sis_hostbr_type_match->type; 3262 sc->sc_wdcdev.UDMA_cap = 3263 sis_hostbr_type_match->udma_mode; 3264 } 3265 printf(sis_hostbr_type_match->name); 3266 } else { 3267 printf("5597/5598"); 3268 if (rev >= 0xd0) { 3269 sc->sc_wdcdev.UDMA_cap = 2; 3270 sc->sis_type = SIS_TYPE_66; 3271 } else { 3272 sc->sc_wdcdev.UDMA_cap = 0; 3273 sc->sis_type = SIS_TYPE_NOUDMA; 3274 } 3275 } 3276 printf(" IDE controller (rev. 0x%02x)\n", PCI_REVISION(pa->pa_class)); 3277 printf("%s: bus-master DMA support present", 3278 sc->sc_wdcdev.sc_dev.dv_xname); 3279 pciide_mapreg_dma(sc, pa); 3280 printf("\n"); 3281 3282 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3283 WDC_CAPABILITY_MODE; 3284 if (sc->sc_dma_ok) { 3285 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3286 sc->sc_wdcdev.irqack = pciide_irqack; 3287 if (sc->sis_type >= SIS_TYPE_66) 3288 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3289 } 3290 3291 sc->sc_wdcdev.PIO_cap = 4; 3292 sc->sc_wdcdev.DMA_cap = 2; 3293 3294 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3295 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3296 switch(sc->sis_type) { 3297 case SIS_TYPE_NOUDMA: 3298 case SIS_TYPE_66: 3299 case SIS_TYPE_100OLD: 3300 sc->sc_wdcdev.set_modes = sis_setup_channel; 3301 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 3302 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 3303 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 3304 break; 3305 case SIS_TYPE_100NEW: 3306 case SIS_TYPE_133OLD: 3307 sc->sc_wdcdev.set_modes = sis_setup_channel; 3308 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 3309 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 3310 break; 3311 case SIS_TYPE_133NEW: 3312 sc->sc_wdcdev.set_modes = sis96x_setup_channel; 3313 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 3314 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 3315 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 3316 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 3317 break; 3318 } 3319 3320 3321 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3322 cp = &sc->pciide_channels[channel]; 3323 if (pciide_chansetup(sc, channel, interface) == 0) 3324 continue; 3325 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 3326 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 3327 printf("%s: %s channel ignored (disabled)\n", 3328 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3329 continue; 3330 } 3331 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3332 pciide_pci_intr); 3333 if (cp->hw_ok == 0) 3334 continue; 3335 if (pciide_chan_candisable(cp)) { 3336 if (channel == 0) 3337 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 3338 else 3339 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 3340 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 3341 sis_ctr0); 3342 } 3343 pciide_map_compat_intr(pa, cp, channel, interface); 3344 if (cp->hw_ok == 0) 3345 continue; 3346 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 3347 } 3348 } 3349 3350 void 3351 sis96x_setup_channel(chp) 3352 struct channel_softc *chp; 3353 { 3354 struct ata_drive_datas *drvp; 3355 int drive; 3356 u_int32_t sis_tim; 3357 u_int32_t idedma_ctl; 3358 int regtim; 3359 struct pciide_channel *cp = (struct pciide_channel*)chp; 3360 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3361 3362 sis_tim = 0; 3363 idedma_ctl = 0; 3364 /* setup DMA if needed */ 3365 pciide_channel_dma_setup(cp); 3366 3367 for (drive = 0; drive < 2; drive++) { 3368 regtim = SIS_TIM133( 3369 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 3370 chp->channel, drive); 3371 drvp = &chp->ch_drive[drive]; 3372 /* If no drive, skip */ 3373 if ((drvp->drive_flags & DRIVE) == 0) 3374 continue; 3375 /* add timing values, setup DMA if needed */ 3376 if (drvp->drive_flags & DRIVE_UDMA) { 3377 /* use Ultra/DMA */ 3378 drvp->drive_flags &= ~DRIVE_DMA; 3379 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3380 SIS96x_REG_CBL(chp->channel)) & SIS96x_REG_CBL_33) { 3381 if (drvp->UDMA_mode > 2) 3382 drvp->UDMA_mode = 2; 3383 } 3384 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 3385 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3386 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3387 } else if (drvp->drive_flags & DRIVE_DMA) { 3388 /* 3389 * use Multiword DMA 3390 * Timings will be used for both PIO and DMA, 3391 * so adjust DMA mode if needed 3392 */ 3393 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3394 drvp->PIO_mode = drvp->DMA_mode + 2; 3395 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3396 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3397 drvp->PIO_mode - 2 : 0; 3398 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 3399 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3400 } else { 3401 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3402 } 3403 WDCDEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 3404 "channel %d drive %d: 0x%x (reg 0x%x)\n", 3405 chp->channel, drive, sis_tim, regtim), DEBUG_PROBE); 3406 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 3407 } 3408 if (idedma_ctl != 0) { 3409 /* Add software bits in status register */ 3410 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3411 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3412 idedma_ctl); 3413 } 3414 pciide_print_modes(cp); 3415 } 3416 3417 void 3418 sis_setup_channel(chp) 3419 struct channel_softc *chp; 3420 { 3421 struct ata_drive_datas *drvp; 3422 int drive; 3423 u_int32_t sis_tim; 3424 u_int32_t idedma_ctl; 3425 struct pciide_channel *cp = (struct pciide_channel*)chp; 3426 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3427 3428 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 3429 "channel %d 0x%x\n", chp->channel, 3430 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 3431 DEBUG_PROBE); 3432 sis_tim = 0; 3433 idedma_ctl = 0; 3434 /* setup DMA if needed */ 3435 pciide_channel_dma_setup(cp); 3436 3437 for (drive = 0; drive < 2; drive++) { 3438 drvp = &chp->ch_drive[drive]; 3439 /* If no drive, skip */ 3440 if ((drvp->drive_flags & DRIVE) == 0) 3441 continue; 3442 /* add timing values, setup DMA if needed */ 3443 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3444 (drvp->drive_flags & DRIVE_UDMA) == 0) 3445 goto pio; 3446 3447 if (drvp->drive_flags & DRIVE_UDMA) { 3448 /* use Ultra/DMA */ 3449 drvp->drive_flags &= ~DRIVE_DMA; 3450 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3451 SIS_REG_CBL) & SIS_REG_CBL_33(chp->channel)) { 3452 if (drvp->UDMA_mode > 2) 3453 drvp->UDMA_mode = 2; 3454 } 3455 switch (sc->sis_type) { 3456 case SIS_TYPE_66: 3457 case SIS_TYPE_100OLD: 3458 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 3459 SIS_TIM66_UDMA_TIME_OFF(drive); 3460 break; 3461 case SIS_TYPE_100NEW: 3462 sis_tim |= 3463 sis_udma100new_tim[drvp->UDMA_mode] << 3464 SIS_TIM100_UDMA_TIME_OFF(drive); 3465 case SIS_TYPE_133OLD: 3466 sis_tim |= 3467 sis_udma133old_tim[drvp->UDMA_mode] << 3468 SIS_TIM100_UDMA_TIME_OFF(drive); 3469 break; 3470 default: 3471 printf("unknown SiS IDE type %d\n", 3472 sc->sis_type); 3473 } 3474 } else { 3475 /* 3476 * use Multiword DMA 3477 * Timings will be used for both PIO and DMA, 3478 * so adjust DMA mode if needed 3479 */ 3480 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3481 drvp->PIO_mode = drvp->DMA_mode + 2; 3482 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3483 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3484 drvp->PIO_mode - 2 : 0; 3485 if (drvp->DMA_mode == 0) 3486 drvp->PIO_mode = 0; 3487 } 3488 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3489 pio: switch (sc->sis_type) { 3490 case SIS_TYPE_NOUDMA: 3491 case SIS_TYPE_66: 3492 case SIS_TYPE_100OLD: 3493 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3494 SIS_TIM66_ACT_OFF(drive); 3495 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3496 SIS_TIM66_REC_OFF(drive); 3497 break; 3498 case SIS_TYPE_100NEW: 3499 case SIS_TYPE_133OLD: 3500 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3501 SIS_TIM100_ACT_OFF(drive); 3502 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3503 SIS_TIM100_REC_OFF(drive); 3504 break; 3505 default: 3506 printf("unknown SiS IDE type %d\n", 3507 sc->sis_type); 3508 } 3509 } 3510 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 3511 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 3512 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 3513 if (idedma_ctl != 0) { 3514 /* Add software bits in status register */ 3515 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3516 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3517 idedma_ctl); 3518 } 3519 pciide_print_modes(cp); 3520 } 3521 3522 void 3523 acer_chip_map(sc, pa) 3524 struct pciide_softc *sc; 3525 struct pci_attach_args *pa; 3526 { 3527 struct pciide_channel *cp; 3528 int channel; 3529 pcireg_t cr, interface; 3530 bus_size_t cmdsize, ctlsize; 3531 pcireg_t rev = PCI_REVISION(pa->pa_class); 3532 3533 if (pciide_chipen(sc, pa) == 0) 3534 return; 3535 printf("%s: bus-master DMA support present", 3536 sc->sc_wdcdev.sc_dev.dv_xname); 3537 pciide_mapreg_dma(sc, pa); 3538 printf("\n"); 3539 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3540 WDC_CAPABILITY_MODE; 3541 if (sc->sc_dma_ok) { 3542 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3543 if (rev >= 0x20) { 3544 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3545 if (rev >= 0xC4) 3546 sc->sc_wdcdev.UDMA_cap = 5; 3547 else if (rev >= 0xC2) 3548 sc->sc_wdcdev.UDMA_cap = 4; 3549 else 3550 sc->sc_wdcdev.UDMA_cap = 2; 3551 } 3552 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3553 sc->sc_wdcdev.irqack = pciide_irqack; 3554 } 3555 3556 sc->sc_wdcdev.PIO_cap = 4; 3557 sc->sc_wdcdev.DMA_cap = 2; 3558 sc->sc_wdcdev.set_modes = acer_setup_channel; 3559 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3560 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3561 3562 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3563 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3564 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3565 3566 /* Enable "microsoft register bits" R/W. */ 3567 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3568 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3569 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3570 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3571 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3572 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3573 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3574 ~ACER_CHANSTATUSREGS_RO); 3575 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3576 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3577 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3578 /* Don't use cr, re-read the real register content instead */ 3579 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3580 PCI_CLASS_REG)); 3581 3582 /* From linux: enable "Cable Detection" */ 3583 if (rev >= 0xC2) { 3584 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3585 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3586 | ACER_0x4B_CDETECT); 3587 } 3588 3589 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3590 cp = &sc->pciide_channels[channel]; 3591 if (pciide_chansetup(sc, channel, interface) == 0) 3592 continue; 3593 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3594 printf("%s: %s channel ignored (disabled)\n", 3595 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3596 continue; 3597 } 3598 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3599 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3600 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3601 if (cp->hw_ok == 0) 3602 continue; 3603 if (pciide_chan_candisable(cp)) { 3604 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3605 pci_conf_write(sc->sc_pc, sc->sc_tag, 3606 PCI_CLASS_REG, cr); 3607 } 3608 pciide_map_compat_intr(pa, cp, channel, interface); 3609 acer_setup_channel(&cp->wdc_channel); 3610 } 3611 } 3612 3613 void 3614 acer_setup_channel(chp) 3615 struct channel_softc *chp; 3616 { 3617 struct ata_drive_datas *drvp; 3618 int drive; 3619 u_int32_t acer_fifo_udma; 3620 u_int32_t idedma_ctl; 3621 struct pciide_channel *cp = (struct pciide_channel*)chp; 3622 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3623 3624 idedma_ctl = 0; 3625 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3626 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3627 acer_fifo_udma), DEBUG_PROBE); 3628 /* setup DMA if needed */ 3629 pciide_channel_dma_setup(cp); 3630 3631 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3632 DRIVE_UDMA) { /* check 80 pins cable */ 3633 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3634 ACER_0x4A_80PIN(chp->channel)) { 3635 if (chp->ch_drive[0].UDMA_mode > 2) 3636 chp->ch_drive[0].UDMA_mode = 2; 3637 if (chp->ch_drive[1].UDMA_mode > 2) 3638 chp->ch_drive[1].UDMA_mode = 2; 3639 } 3640 } 3641 3642 for (drive = 0; drive < 2; drive++) { 3643 drvp = &chp->ch_drive[drive]; 3644 /* If no drive, skip */ 3645 if ((drvp->drive_flags & DRIVE) == 0) 3646 continue; 3647 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3648 "channel %d drive %d 0x%x\n", chp->channel, drive, 3649 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3650 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3651 /* clear FIFO/DMA mode */ 3652 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3653 ACER_UDMA_EN(chp->channel, drive) | 3654 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3655 3656 /* add timing values, setup DMA if needed */ 3657 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3658 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3659 acer_fifo_udma |= 3660 ACER_FTH_OPL(chp->channel, drive, 0x1); 3661 goto pio; 3662 } 3663 3664 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3665 if (drvp->drive_flags & DRIVE_UDMA) { 3666 /* use Ultra/DMA */ 3667 drvp->drive_flags &= ~DRIVE_DMA; 3668 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3669 acer_fifo_udma |= 3670 ACER_UDMA_TIM(chp->channel, drive, 3671 acer_udma[drvp->UDMA_mode]); 3672 /* XXX disable if one drive < UDMA3 ? */ 3673 if (drvp->UDMA_mode >= 3) { 3674 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3675 ACER_0x4B, 3676 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3677 ACER_0x4B) | ACER_0x4B_UDMA66); 3678 } 3679 } else { 3680 /* 3681 * use Multiword DMA 3682 * Timings will be used for both PIO and DMA, 3683 * so adjust DMA mode if needed 3684 */ 3685 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3686 drvp->PIO_mode = drvp->DMA_mode + 2; 3687 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3688 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3689 drvp->PIO_mode - 2 : 0; 3690 if (drvp->DMA_mode == 0) 3691 drvp->PIO_mode = 0; 3692 } 3693 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3694 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3695 ACER_IDETIM(chp->channel, drive), 3696 acer_pio[drvp->PIO_mode]); 3697 } 3698 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3699 acer_fifo_udma), DEBUG_PROBE); 3700 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3701 if (idedma_ctl != 0) { 3702 /* Add software bits in status register */ 3703 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3704 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3705 idedma_ctl); 3706 } 3707 pciide_print_modes(cp); 3708 } 3709 3710 int 3711 acer_pci_intr(arg) 3712 void *arg; 3713 { 3714 struct pciide_softc *sc = arg; 3715 struct pciide_channel *cp; 3716 struct channel_softc *wdc_cp; 3717 int i, rv, crv; 3718 u_int32_t chids; 3719 3720 rv = 0; 3721 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3722 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3723 cp = &sc->pciide_channels[i]; 3724 wdc_cp = &cp->wdc_channel; 3725 /* If a compat channel skip. */ 3726 if (cp->compat) 3727 continue; 3728 if (chids & ACER_CHIDS_INT(i)) { 3729 crv = wdcintr(wdc_cp); 3730 if (crv == 0) 3731 printf("%s:%d: bogus intr\n", 3732 sc->sc_wdcdev.sc_dev.dv_xname, i); 3733 else 3734 rv = 1; 3735 } 3736 } 3737 return rv; 3738 } 3739 3740 void 3741 hpt_chip_map(sc, pa) 3742 struct pciide_softc *sc; 3743 struct pci_attach_args *pa; 3744 { 3745 struct pciide_channel *cp; 3746 int i, compatchan, revision; 3747 pcireg_t interface; 3748 bus_size_t cmdsize, ctlsize; 3749 3750 if (pciide_chipen(sc, pa) == 0) 3751 return; 3752 revision = PCI_REVISION(pa->pa_class); 3753 printf(": Triones/Highpoint "); 3754 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3755 printf("HPT374 IDE Controller\n"); 3756 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372) 3757 printf("HPT372 IDE Controller\n"); 3758 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 3759 if (revision == HPT372_REV) 3760 printf("HPT372 IDE Controller\n"); 3761 else if (revision == HPT370_REV) 3762 printf("HPT370 IDE Controller\n"); 3763 else if (revision == HPT370A_REV) 3764 printf("HPT370A IDE Controller\n"); 3765 else if (revision == HPT366_REV) 3766 printf("HPT366 IDE Controller\n"); 3767 else 3768 printf("unknown HPT IDE controller rev %d\n", revision); 3769 } else 3770 printf("unknown HPT IDE controller 0x%x\n", 3771 sc->sc_pp->ide_product); 3772 3773 /* 3774 * when the chip is in native mode it identifies itself as a 3775 * 'misc mass storage'. Fake interface in this case. 3776 */ 3777 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3778 interface = PCI_INTERFACE(pa->pa_class); 3779 } else { 3780 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3781 PCIIDE_INTERFACE_PCI(0); 3782 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3783 (revision == HPT370_REV || revision == HPT370A_REV || 3784 revision == HPT372_REV)) || 3785 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3786 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3787 interface |= PCIIDE_INTERFACE_PCI(1); 3788 } 3789 3790 printf("%s: bus-master DMA support present", 3791 sc->sc_wdcdev.sc_dev.dv_xname); 3792 pciide_mapreg_dma(sc, pa); 3793 printf("\n"); 3794 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3795 WDC_CAPABILITY_MODE; 3796 if (sc->sc_dma_ok) { 3797 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3798 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3799 sc->sc_wdcdev.irqack = pciide_irqack; 3800 } 3801 sc->sc_wdcdev.PIO_cap = 4; 3802 sc->sc_wdcdev.DMA_cap = 2; 3803 3804 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3805 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3806 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3807 revision == HPT366_REV) { 3808 sc->sc_wdcdev.UDMA_cap = 4; 3809 /* 3810 * The 366 has 2 PCI IDE functions, one for primary and one 3811 * for secondary. So we need to call pciide_mapregs_compat() 3812 * with the real channel 3813 */ 3814 if (pa->pa_function == 0) { 3815 compatchan = 0; 3816 } else if (pa->pa_function == 1) { 3817 compatchan = 1; 3818 } else { 3819 printf("%s: unexpected PCI function %d\n", 3820 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3821 return; 3822 } 3823 sc->sc_wdcdev.nchannels = 1; 3824 } else { 3825 sc->sc_wdcdev.nchannels = 2; 3826 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 3827 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3828 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3829 revision == HPT372_REV)) 3830 sc->sc_wdcdev.UDMA_cap = 6; 3831 else 3832 sc->sc_wdcdev.UDMA_cap = 5; 3833 } 3834 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3835 cp = &sc->pciide_channels[i]; 3836 if (sc->sc_wdcdev.nchannels > 1) { 3837 compatchan = i; 3838 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3839 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3840 printf("%s: %s channel ignored (disabled)\n", 3841 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3842 continue; 3843 } 3844 } 3845 if (pciide_chansetup(sc, i, interface) == 0) 3846 continue; 3847 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3848 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3849 &ctlsize, hpt_pci_intr); 3850 } else { 3851 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3852 &cmdsize, &ctlsize); 3853 } 3854 if (cp->hw_ok == 0) 3855 return; 3856 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3857 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3858 wdcattach(&cp->wdc_channel); 3859 hpt_setup_channel(&cp->wdc_channel); 3860 } 3861 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3862 (revision == HPT370_REV || revision == HPT370A_REV || 3863 revision == HPT372_REV)) || 3864 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3865 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 3866 /* 3867 * HPT370_REV and highter has a bit to disable interrupts, 3868 * make sure to clear it 3869 */ 3870 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3871 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3872 ~HPT_CSEL_IRQDIS); 3873 } 3874 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 3875 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3876 revision == HPT372_REV ) || 3877 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3878 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3879 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 3880 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 3881 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 3882 return; 3883 } 3884 3885 void 3886 hpt_setup_channel(chp) 3887 struct channel_softc *chp; 3888 { 3889 struct ata_drive_datas *drvp; 3890 int drive; 3891 int cable; 3892 u_int32_t before, after; 3893 u_int32_t idedma_ctl; 3894 struct pciide_channel *cp = (struct pciide_channel*)chp; 3895 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3896 int revision = 3897 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 3898 3899 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3900 3901 /* setup DMA if needed */ 3902 pciide_channel_dma_setup(cp); 3903 3904 idedma_ctl = 0; 3905 3906 /* Per drive settings */ 3907 for (drive = 0; drive < 2; drive++) { 3908 drvp = &chp->ch_drive[drive]; 3909 /* If no drive, skip */ 3910 if ((drvp->drive_flags & DRIVE) == 0) 3911 continue; 3912 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3913 HPT_IDETIM(chp->channel, drive)); 3914 3915 /* add timing values, setup DMA if needed */ 3916 if (drvp->drive_flags & DRIVE_UDMA) { 3917 /* use Ultra/DMA */ 3918 drvp->drive_flags &= ~DRIVE_DMA; 3919 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3920 drvp->UDMA_mode > 2) 3921 drvp->UDMA_mode = 2; 3922 switch (sc->sc_pp->ide_product) { 3923 case PCI_PRODUCT_TRIONES_HPT374: 3924 after = hpt374_udma[drvp->UDMA_mode]; 3925 break; 3926 case PCI_PRODUCT_TRIONES_HPT372: 3927 after = hpt372_udma[drvp->UDMA_mode]; 3928 break; 3929 case PCI_PRODUCT_TRIONES_HPT366: 3930 default: 3931 switch(revision) { 3932 case HPT372_REV: 3933 after = hpt372_udma[drvp->UDMA_mode]; 3934 break; 3935 case HPT370_REV: 3936 case HPT370A_REV: 3937 after = hpt370_udma[drvp->UDMA_mode]; 3938 break; 3939 case HPT366_REV: 3940 default: 3941 after = hpt366_udma[drvp->UDMA_mode]; 3942 break; 3943 } 3944 } 3945 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3946 } else if (drvp->drive_flags & DRIVE_DMA) { 3947 /* 3948 * use Multiword DMA. 3949 * Timings will be used for both PIO and DMA, so adjust 3950 * DMA mode if needed 3951 */ 3952 if (drvp->PIO_mode >= 3 && 3953 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3954 drvp->DMA_mode = drvp->PIO_mode - 2; 3955 } 3956 switch (sc->sc_pp->ide_product) { 3957 case PCI_PRODUCT_TRIONES_HPT374: 3958 after = hpt374_dma[drvp->DMA_mode]; 3959 break; 3960 case PCI_PRODUCT_TRIONES_HPT372: 3961 after = hpt372_dma[drvp->DMA_mode]; 3962 break; 3963 case PCI_PRODUCT_TRIONES_HPT366: 3964 default: 3965 switch(revision) { 3966 case HPT372_REV: 3967 after = hpt372_dma[drvp->DMA_mode]; 3968 break; 3969 case HPT370_REV: 3970 case HPT370A_REV: 3971 after = hpt370_dma[drvp->DMA_mode]; 3972 break; 3973 case HPT366_REV: 3974 default: 3975 after = hpt366_dma[drvp->DMA_mode]; 3976 break; 3977 } 3978 } 3979 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3980 } else { 3981 /* PIO only */ 3982 switch (sc->sc_pp->ide_product) { 3983 case PCI_PRODUCT_TRIONES_HPT374: 3984 after = hpt374_pio[drvp->PIO_mode]; 3985 break; 3986 case PCI_PRODUCT_TRIONES_HPT372: 3987 after = hpt372_pio[drvp->PIO_mode]; 3988 break; 3989 case PCI_PRODUCT_TRIONES_HPT366: 3990 default: 3991 switch(revision) { 3992 case HPT372_REV: 3993 after = hpt372_pio[drvp->PIO_mode]; 3994 break; 3995 case HPT370_REV: 3996 case HPT370A_REV: 3997 after = hpt370_pio[drvp->PIO_mode]; 3998 break; 3999 case HPT366_REV: 4000 default: 4001 after = hpt366_pio[drvp->PIO_mode]; 4002 break; 4003 } 4004 } 4005 } 4006 pci_conf_write(sc->sc_pc, sc->sc_tag, 4007 HPT_IDETIM(chp->channel, drive), after); 4008 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 4009 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 4010 after, before), DEBUG_PROBE); 4011 } 4012 if (idedma_ctl != 0) { 4013 /* Add software bits in status register */ 4014 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4015 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4016 idedma_ctl); 4017 } 4018 pciide_print_modes(cp); 4019 } 4020 4021 int 4022 hpt_pci_intr(arg) 4023 void *arg; 4024 { 4025 struct pciide_softc *sc = arg; 4026 struct pciide_channel *cp; 4027 struct channel_softc *wdc_cp; 4028 int rv = 0; 4029 int dmastat, i, crv; 4030 4031 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4032 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4033 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4034 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4035 IDEDMA_CTL_INTR) 4036 continue; 4037 cp = &sc->pciide_channels[i]; 4038 wdc_cp = &cp->wdc_channel; 4039 crv = wdcintr(wdc_cp); 4040 if (crv == 0) { 4041 printf("%s:%d: bogus intr\n", 4042 sc->sc_wdcdev.sc_dev.dv_xname, i); 4043 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4044 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4045 } else 4046 rv = 1; 4047 } 4048 return rv; 4049 } 4050 4051 4052 /* Macros to test product */ 4053 #define PDC_IS_262(sc) \ 4054 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 4055 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 4056 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 4057 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4058 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4059 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4060 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4061 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4062 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4063 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4064 #define PDC_IS_265(sc) \ 4065 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 4066 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 4067 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4068 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4069 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4070 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4071 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4072 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4073 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4074 #define PDC_IS_268(sc) \ 4075 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4076 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4077 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4078 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4079 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4080 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4081 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4082 #define PDC_IS_276(sc) \ 4083 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4084 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4085 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4086 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4087 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4088 4089 void 4090 pdc202xx_chip_map(sc, pa) 4091 struct pciide_softc *sc; 4092 struct pci_attach_args *pa; 4093 { 4094 struct pciide_channel *cp; 4095 int channel; 4096 pcireg_t interface, st, mode; 4097 bus_size_t cmdsize, ctlsize; 4098 4099 if (!PDC_IS_268(sc)) { 4100 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4101 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 4102 st), DEBUG_PROBE); 4103 } 4104 if (pciide_chipen(sc, pa) == 0) 4105 return; 4106 4107 /* turn off RAID mode */ 4108 if (!PDC_IS_268(sc)) 4109 st &= ~PDC2xx_STATE_IDERAID; 4110 4111 /* 4112 * can't rely on the PCI_CLASS_REG content if the chip was in raid 4113 * mode. We have to fake interface 4114 */ 4115 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 4116 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 4117 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4118 4119 printf("%s: bus-master DMA support present", 4120 sc->sc_wdcdev.sc_dev.dv_xname); 4121 pciide_mapreg_dma(sc, pa); 4122 printf("\n"); 4123 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4124 WDC_CAPABILITY_MODE; 4125 if (sc->sc_dma_ok) { 4126 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4127 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4128 sc->sc_wdcdev.irqack = pciide_irqack; 4129 } 4130 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 4131 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 4132 sc->sc_wdcdev.cap |= WDC_CAPABILITY_RAID; 4133 sc->sc_wdcdev.PIO_cap = 4; 4134 sc->sc_wdcdev.DMA_cap = 2; 4135 if (PDC_IS_276(sc)) 4136 sc->sc_wdcdev.UDMA_cap = 6; 4137 else if (PDC_IS_265(sc)) 4138 sc->sc_wdcdev.UDMA_cap = 5; 4139 else if (PDC_IS_262(sc)) 4140 sc->sc_wdcdev.UDMA_cap = 4; 4141 else 4142 sc->sc_wdcdev.UDMA_cap = 2; 4143 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 4144 pdc20268_setup_channel : pdc202xx_setup_channel; 4145 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4146 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4147 4148 if (!PDC_IS_268(sc)) { 4149 /* setup failsafe defaults */ 4150 mode = 0; 4151 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 4152 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 4153 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 4154 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 4155 for (channel = 0; 4156 channel < sc->sc_wdcdev.nchannels; 4157 channel++) { 4158 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 4159 "drive 0 initial timings 0x%x, now 0x%x\n", 4160 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 4161 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 4162 DEBUG_PROBE); 4163 pci_conf_write(sc->sc_pc, sc->sc_tag, 4164 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 4165 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 4166 "drive 1 initial timings 0x%x, now 0x%x\n", 4167 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 4168 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 4169 pci_conf_write(sc->sc_pc, sc->sc_tag, 4170 PDC2xx_TIM(channel, 1), mode); 4171 } 4172 4173 mode = PDC2xx_SCR_DMA; 4174 if (PDC_IS_262(sc)) { 4175 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 4176 } else { 4177 /* the BIOS set it up this way */ 4178 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 4179 } 4180 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 4181 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 4182 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 4183 "now 0x%x\n", 4184 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4185 PDC2xx_SCR), 4186 mode), DEBUG_PROBE); 4187 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4188 PDC2xx_SCR, mode); 4189 4190 /* controller initial state register is OK even without BIOS */ 4191 /* Set DMA mode to IDE DMA compatibility */ 4192 mode = 4193 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 4194 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 4195 DEBUG_PROBE); 4196 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 4197 mode | 0x1); 4198 mode = 4199 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 4200 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 4201 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 4202 mode | 0x1); 4203 } 4204 4205 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4206 cp = &sc->pciide_channels[channel]; 4207 if (pciide_chansetup(sc, channel, interface) == 0) 4208 continue; 4209 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 4210 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 4211 printf("%s: %s channel ignored (disabled)\n", 4212 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4213 continue; 4214 } 4215 if (PDC_IS_265(sc)) 4216 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4217 pdc20265_pci_intr); 4218 else 4219 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4220 pdc202xx_pci_intr); 4221 if (cp->hw_ok == 0) 4222 continue; 4223 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 4224 st &= ~(PDC_IS_262(sc) ? 4225 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 4226 pciide_map_compat_intr(pa, cp, channel, interface); 4227 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 4228 } 4229 if (!PDC_IS_268(sc)) { 4230 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 4231 "0x%x\n", st), DEBUG_PROBE); 4232 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 4233 } 4234 return; 4235 } 4236 4237 void 4238 pdc202xx_setup_channel(chp) 4239 struct channel_softc *chp; 4240 { 4241 struct ata_drive_datas *drvp; 4242 int drive; 4243 pcireg_t mode, st; 4244 u_int32_t idedma_ctl, scr, atapi; 4245 struct pciide_channel *cp = (struct pciide_channel*)chp; 4246 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4247 int channel = chp->channel; 4248 4249 /* setup DMA if needed */ 4250 pciide_channel_dma_setup(cp); 4251 4252 idedma_ctl = 0; 4253 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 4254 sc->sc_wdcdev.sc_dev.dv_xname, 4255 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 4256 DEBUG_PROBE); 4257 4258 /* Per channel settings */ 4259 if (PDC_IS_262(sc)) { 4260 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4261 PDC262_U66); 4262 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4263 /* Trim UDMA mode */ 4264 if ((st & PDC262_STATE_80P(channel)) != 0 || 4265 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4266 chp->ch_drive[0].UDMA_mode <= 2) || 4267 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4268 chp->ch_drive[1].UDMA_mode <= 2)) { 4269 if (chp->ch_drive[0].UDMA_mode > 2) 4270 chp->ch_drive[0].UDMA_mode = 2; 4271 if (chp->ch_drive[1].UDMA_mode > 2) 4272 chp->ch_drive[1].UDMA_mode = 2; 4273 } 4274 /* Set U66 if needed */ 4275 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4276 chp->ch_drive[0].UDMA_mode > 2) || 4277 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4278 chp->ch_drive[1].UDMA_mode > 2)) 4279 scr |= PDC262_U66_EN(channel); 4280 else 4281 scr &= ~PDC262_U66_EN(channel); 4282 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4283 PDC262_U66, scr); 4284 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 4285 sc->sc_wdcdev.sc_dev.dv_xname, channel, 4286 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4287 PDC262_ATAPI(channel))), DEBUG_PROBE); 4288 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 4289 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 4290 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4291 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4292 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 4293 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4294 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4295 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 4296 atapi = 0; 4297 else 4298 atapi = PDC262_ATAPI_UDMA; 4299 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4300 PDC262_ATAPI(channel), atapi); 4301 } 4302 } 4303 for (drive = 0; drive < 2; drive++) { 4304 drvp = &chp->ch_drive[drive]; 4305 /* If no drive, skip */ 4306 if ((drvp->drive_flags & DRIVE) == 0) 4307 continue; 4308 mode = 0; 4309 if (drvp->drive_flags & DRIVE_UDMA) { 4310 /* use Ultra/DMA */ 4311 drvp->drive_flags &= ~DRIVE_DMA; 4312 mode = PDC2xx_TIM_SET_MB(mode, 4313 pdc2xx_udma_mb[drvp->UDMA_mode]); 4314 mode = PDC2xx_TIM_SET_MC(mode, 4315 pdc2xx_udma_mc[drvp->UDMA_mode]); 4316 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4317 } else if (drvp->drive_flags & DRIVE_DMA) { 4318 mode = PDC2xx_TIM_SET_MB(mode, 4319 pdc2xx_dma_mb[drvp->DMA_mode]); 4320 mode = PDC2xx_TIM_SET_MC(mode, 4321 pdc2xx_dma_mc[drvp->DMA_mode]); 4322 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4323 } else { 4324 mode = PDC2xx_TIM_SET_MB(mode, 4325 pdc2xx_dma_mb[0]); 4326 mode = PDC2xx_TIM_SET_MC(mode, 4327 pdc2xx_dma_mc[0]); 4328 } 4329 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 4330 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 4331 if (drvp->drive_flags & DRIVE_ATA) 4332 mode |= PDC2xx_TIM_PRE; 4333 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 4334 if (drvp->PIO_mode >= 3) { 4335 mode |= PDC2xx_TIM_IORDY; 4336 if (drive == 0) 4337 mode |= PDC2xx_TIM_IORDYp; 4338 } 4339 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 4340 "timings 0x%x\n", 4341 sc->sc_wdcdev.sc_dev.dv_xname, 4342 chp->channel, drive, mode), DEBUG_PROBE); 4343 pci_conf_write(sc->sc_pc, sc->sc_tag, 4344 PDC2xx_TIM(chp->channel, drive), mode); 4345 } 4346 if (idedma_ctl != 0) { 4347 /* Add software bits in status register */ 4348 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4349 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4350 idedma_ctl); 4351 } 4352 pciide_print_modes(cp); 4353 } 4354 4355 void 4356 pdc20268_setup_channel(chp) 4357 struct channel_softc *chp; 4358 { 4359 struct ata_drive_datas *drvp; 4360 int drive; 4361 u_int32_t idedma_ctl; 4362 struct pciide_channel *cp = (struct pciide_channel*)chp; 4363 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4364 int u100; 4365 4366 /* setup DMA if needed */ 4367 pciide_channel_dma_setup(cp); 4368 4369 idedma_ctl = 0; 4370 4371 /* I don't know what this is for, FreeBSD does it ... */ 4372 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4373 IDEDMA_CMD + 0x1, 0x0b); 4374 4375 /* 4376 * I don't know what this is for; FreeBSD checks this ... this is not 4377 * cable type detect. 4378 */ 4379 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4380 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 4381 4382 for (drive = 0; drive < 2; drive++) { 4383 drvp = &chp->ch_drive[drive]; 4384 /* If no drive, skip */ 4385 if ((drvp->drive_flags & DRIVE) == 0) 4386 continue; 4387 if (drvp->drive_flags & DRIVE_UDMA) { 4388 /* use Ultra/DMA */ 4389 drvp->drive_flags &= ~DRIVE_DMA; 4390 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4391 if (drvp->UDMA_mode > 2 && u100 == 0) 4392 drvp->UDMA_mode = 2; 4393 } else if (drvp->drive_flags & DRIVE_DMA) { 4394 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4395 } 4396 } 4397 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 4398 if (idedma_ctl != 0) { 4399 /* Add software bits in status register */ 4400 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4401 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4402 idedma_ctl); 4403 } 4404 pciide_print_modes(cp); 4405 } 4406 4407 int 4408 pdc202xx_pci_intr(arg) 4409 void *arg; 4410 { 4411 struct pciide_softc *sc = arg; 4412 struct pciide_channel *cp; 4413 struct channel_softc *wdc_cp; 4414 int i, rv, crv; 4415 u_int32_t scr; 4416 4417 rv = 0; 4418 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 4419 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4420 cp = &sc->pciide_channels[i]; 4421 wdc_cp = &cp->wdc_channel; 4422 /* If a compat channel skip. */ 4423 if (cp->compat) 4424 continue; 4425 if (scr & PDC2xx_SCR_INT(i)) { 4426 crv = wdcintr(wdc_cp); 4427 if (crv == 0) 4428 printf("%s:%d: bogus intr (reg 0x%x)\n", 4429 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 4430 else 4431 rv = 1; 4432 } 4433 } 4434 return rv; 4435 } 4436 4437 int 4438 pdc20265_pci_intr(arg) 4439 void *arg; 4440 { 4441 struct pciide_softc *sc = arg; 4442 struct pciide_channel *cp; 4443 struct channel_softc *wdc_cp; 4444 int i, rv, crv; 4445 u_int32_t dmastat; 4446 4447 rv = 0; 4448 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4449 cp = &sc->pciide_channels[i]; 4450 wdc_cp = &cp->wdc_channel; 4451 /* If a compat channel skip. */ 4452 if (cp->compat) 4453 continue; 4454 /* 4455 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 4456 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 4457 * So use it instead (requires 2 reg reads instead of 1, 4458 * but we can't do it another way). 4459 */ 4460 dmastat = bus_space_read_1(sc->sc_dma_iot, 4461 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4462 if((dmastat & IDEDMA_CTL_INTR) == 0) 4463 continue; 4464 crv = wdcintr(wdc_cp); 4465 if (crv == 0) 4466 printf("%s:%d: bogus intr\n", 4467 sc->sc_wdcdev.sc_dev.dv_xname, i); 4468 else 4469 rv = 1; 4470 } 4471 return rv; 4472 } 4473 4474 void 4475 opti_chip_map(sc, pa) 4476 struct pciide_softc *sc; 4477 struct pci_attach_args *pa; 4478 { 4479 struct pciide_channel *cp; 4480 bus_size_t cmdsize, ctlsize; 4481 pcireg_t interface; 4482 u_int8_t init_ctrl; 4483 int channel; 4484 4485 if (pciide_chipen(sc, pa) == 0) 4486 return; 4487 printf("%s: bus-master DMA support present", 4488 sc->sc_wdcdev.sc_dev.dv_xname); 4489 4490 /* 4491 * XXXSCW: 4492 * There seem to be a couple of buggy revisions/implementations 4493 * of the OPTi pciide chipset. This kludge seems to fix one of 4494 * the reported problems (PR/11644) but still fails for the 4495 * other (PR/13151), although the latter may be due to other 4496 * issues too... 4497 */ 4498 if (PCI_REVISION(pa->pa_class) <= 0x12) { 4499 printf(" but disabled due to chip rev. <= 0x12"); 4500 sc->sc_dma_ok = 0; 4501 } else 4502 pciide_mapreg_dma(sc, pa); 4503 4504 printf("\n"); 4505 4506 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4507 WDC_CAPABILITY_MODE; 4508 sc->sc_wdcdev.PIO_cap = 4; 4509 if (sc->sc_dma_ok) { 4510 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4511 sc->sc_wdcdev.irqack = pciide_irqack; 4512 sc->sc_wdcdev.DMA_cap = 2; 4513 } 4514 sc->sc_wdcdev.set_modes = opti_setup_channel; 4515 4516 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4517 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4518 4519 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 4520 OPTI_REG_INIT_CONTROL); 4521 4522 interface = PCI_INTERFACE(pa->pa_class); 4523 4524 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4525 cp = &sc->pciide_channels[channel]; 4526 if (pciide_chansetup(sc, channel, interface) == 0) 4527 continue; 4528 if (channel == 1 && 4529 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 4530 printf("%s: %s channel ignored (disabled)\n", 4531 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4532 continue; 4533 } 4534 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4535 pciide_pci_intr); 4536 if (cp->hw_ok == 0) 4537 continue; 4538 pciide_map_compat_intr(pa, cp, channel, interface); 4539 if (cp->hw_ok == 0) 4540 continue; 4541 opti_setup_channel(&cp->wdc_channel); 4542 } 4543 } 4544 4545 void 4546 opti_setup_channel(chp) 4547 struct channel_softc *chp; 4548 { 4549 struct ata_drive_datas *drvp; 4550 struct pciide_channel *cp = (struct pciide_channel*)chp; 4551 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4552 int drive, spd; 4553 int mode[2]; 4554 u_int8_t rv, mr; 4555 4556 /* 4557 * The `Delay' and `Address Setup Time' fields of the 4558 * Miscellaneous Register are always zero initially. 4559 */ 4560 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 4561 mr &= ~(OPTI_MISC_DELAY_MASK | 4562 OPTI_MISC_ADDR_SETUP_MASK | 4563 OPTI_MISC_INDEX_MASK); 4564 4565 /* Prime the control register before setting timing values */ 4566 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 4567 4568 /* Determine the clockrate of the PCIbus the chip is attached to */ 4569 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 4570 spd &= OPTI_STRAP_PCI_SPEED_MASK; 4571 4572 /* setup DMA if needed */ 4573 pciide_channel_dma_setup(cp); 4574 4575 for (drive = 0; drive < 2; drive++) { 4576 drvp = &chp->ch_drive[drive]; 4577 /* If no drive, skip */ 4578 if ((drvp->drive_flags & DRIVE) == 0) { 4579 mode[drive] = -1; 4580 continue; 4581 } 4582 4583 if ((drvp->drive_flags & DRIVE_DMA)) { 4584 /* 4585 * Timings will be used for both PIO and DMA, 4586 * so adjust DMA mode if needed 4587 */ 4588 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 4589 drvp->PIO_mode = drvp->DMA_mode + 2; 4590 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 4591 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 4592 drvp->PIO_mode - 2 : 0; 4593 if (drvp->DMA_mode == 0) 4594 drvp->PIO_mode = 0; 4595 4596 mode[drive] = drvp->DMA_mode + 5; 4597 } else 4598 mode[drive] = drvp->PIO_mode; 4599 4600 if (drive && mode[0] >= 0 && 4601 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 4602 /* 4603 * Can't have two drives using different values 4604 * for `Address Setup Time'. 4605 * Slow down the faster drive to compensate. 4606 */ 4607 int d = (opti_tim_as[spd][mode[0]] > 4608 opti_tim_as[spd][mode[1]]) ? 0 : 1; 4609 4610 mode[d] = mode[1-d]; 4611 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4612 chp->ch_drive[d].DMA_mode = 0; 4613 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 4614 } 4615 } 4616 4617 for (drive = 0; drive < 2; drive++) { 4618 int m; 4619 if ((m = mode[drive]) < 0) 4620 continue; 4621 4622 /* Set the Address Setup Time and select appropriate index */ 4623 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4624 rv |= OPTI_MISC_INDEX(drive); 4625 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4626 4627 /* Set the pulse width and recovery timing parameters */ 4628 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4629 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4630 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4631 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4632 4633 /* Set the Enhanced Mode register appropriately */ 4634 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4635 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4636 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4637 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4638 } 4639 4640 /* Finally, enable the timings */ 4641 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4642 4643 pciide_print_modes(cp); 4644 } 4645 4646 #define ACARD_IS_850(sc) \ 4647 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4648 4649 void 4650 acard_chip_map(sc, pa) 4651 struct pciide_softc *sc; 4652 struct pci_attach_args *pa; 4653 { 4654 struct pciide_channel *cp; 4655 int i; 4656 pcireg_t interface; 4657 bus_size_t cmdsize, ctlsize; 4658 4659 if (pciide_chipen(sc, pa) == 0) 4660 return; 4661 4662 /* 4663 * when the chip is in native mode it identifies itself as a 4664 * 'misc mass storage'. Fake interface in this case. 4665 */ 4666 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4667 interface = PCI_INTERFACE(pa->pa_class); 4668 } else { 4669 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4670 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4671 } 4672 4673 printf("%s: bus-master DMA support present", 4674 sc->sc_wdcdev.sc_dev.dv_xname); 4675 pciide_mapreg_dma(sc, pa); 4676 printf("\n"); 4677 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4678 WDC_CAPABILITY_MODE; 4679 4680 if (sc->sc_dma_ok) { 4681 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4682 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4683 sc->sc_wdcdev.irqack = pciide_irqack; 4684 } 4685 sc->sc_wdcdev.PIO_cap = 4; 4686 sc->sc_wdcdev.DMA_cap = 2; 4687 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4688 4689 sc->sc_wdcdev.set_modes = acard_setup_channel; 4690 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4691 sc->sc_wdcdev.nchannels = 2; 4692 4693 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4694 cp = &sc->pciide_channels[i]; 4695 if (pciide_chansetup(sc, i, interface) == 0) 4696 continue; 4697 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4698 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4699 &ctlsize, pciide_pci_intr); 4700 } else { 4701 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4702 &cmdsize, &ctlsize); 4703 } 4704 if (cp->hw_ok == 0) 4705 return; 4706 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4707 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4708 wdcattach(&cp->wdc_channel); 4709 acard_setup_channel(&cp->wdc_channel); 4710 } 4711 if (!ACARD_IS_850(sc)) { 4712 u_int32_t reg; 4713 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4714 reg &= ~ATP860_CTRL_INT; 4715 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4716 } 4717 } 4718 4719 void 4720 acard_setup_channel(chp) 4721 struct channel_softc *chp; 4722 { 4723 struct ata_drive_datas *drvp; 4724 struct pciide_channel *cp = (struct pciide_channel*)chp; 4725 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4726 int channel = chp->channel; 4727 int drive; 4728 u_int32_t idetime, udma_mode; 4729 u_int32_t idedma_ctl; 4730 4731 /* setup DMA if needed */ 4732 pciide_channel_dma_setup(cp); 4733 4734 if (ACARD_IS_850(sc)) { 4735 idetime = 0; 4736 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4737 udma_mode &= ~ATP850_UDMA_MASK(channel); 4738 } else { 4739 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4740 idetime &= ~ATP860_SETTIME_MASK(channel); 4741 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4742 udma_mode &= ~ATP860_UDMA_MASK(channel); 4743 4744 /* check 80 pins cable */ 4745 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4746 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4747 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4748 & ATP860_CTRL_80P(chp->channel)) { 4749 if (chp->ch_drive[0].UDMA_mode > 2) 4750 chp->ch_drive[0].UDMA_mode = 2; 4751 if (chp->ch_drive[1].UDMA_mode > 2) 4752 chp->ch_drive[1].UDMA_mode = 2; 4753 } 4754 } 4755 } 4756 4757 idedma_ctl = 0; 4758 4759 /* Per drive settings */ 4760 for (drive = 0; drive < 2; drive++) { 4761 drvp = &chp->ch_drive[drive]; 4762 /* If no drive, skip */ 4763 if ((drvp->drive_flags & DRIVE) == 0) 4764 continue; 4765 /* add timing values, setup DMA if needed */ 4766 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4767 (drvp->drive_flags & DRIVE_UDMA)) { 4768 /* use Ultra/DMA */ 4769 if (ACARD_IS_850(sc)) { 4770 idetime |= ATP850_SETTIME(drive, 4771 acard_act_udma[drvp->UDMA_mode], 4772 acard_rec_udma[drvp->UDMA_mode]); 4773 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4774 acard_udma_conf[drvp->UDMA_mode]); 4775 } else { 4776 idetime |= ATP860_SETTIME(channel, drive, 4777 acard_act_udma[drvp->UDMA_mode], 4778 acard_rec_udma[drvp->UDMA_mode]); 4779 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4780 acard_udma_conf[drvp->UDMA_mode]); 4781 } 4782 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4783 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4784 (drvp->drive_flags & DRIVE_DMA)) { 4785 /* use Multiword DMA */ 4786 drvp->drive_flags &= ~DRIVE_UDMA; 4787 if (ACARD_IS_850(sc)) { 4788 idetime |= ATP850_SETTIME(drive, 4789 acard_act_dma[drvp->DMA_mode], 4790 acard_rec_dma[drvp->DMA_mode]); 4791 } else { 4792 idetime |= ATP860_SETTIME(channel, drive, 4793 acard_act_dma[drvp->DMA_mode], 4794 acard_rec_dma[drvp->DMA_mode]); 4795 } 4796 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4797 } else { 4798 /* PIO only */ 4799 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4800 if (ACARD_IS_850(sc)) { 4801 idetime |= ATP850_SETTIME(drive, 4802 acard_act_pio[drvp->PIO_mode], 4803 acard_rec_pio[drvp->PIO_mode]); 4804 } else { 4805 idetime |= ATP860_SETTIME(channel, drive, 4806 acard_act_pio[drvp->PIO_mode], 4807 acard_rec_pio[drvp->PIO_mode]); 4808 } 4809 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4810 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4811 | ATP8x0_CTRL_EN(channel)); 4812 } 4813 } 4814 4815 if (idedma_ctl != 0) { 4816 /* Add software bits in status register */ 4817 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4818 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4819 } 4820 pciide_print_modes(cp); 4821 4822 if (ACARD_IS_850(sc)) { 4823 pci_conf_write(sc->sc_pc, sc->sc_tag, 4824 ATP850_IDETIME(channel), idetime); 4825 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4826 } else { 4827 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4828 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4829 } 4830 } 4831 4832 int 4833 acard_pci_intr(arg) 4834 void *arg; 4835 { 4836 struct pciide_softc *sc = arg; 4837 struct pciide_channel *cp; 4838 struct channel_softc *wdc_cp; 4839 int rv = 0; 4840 int dmastat, i, crv; 4841 4842 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4843 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4844 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4845 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4846 continue; 4847 cp = &sc->pciide_channels[i]; 4848 wdc_cp = &cp->wdc_channel; 4849 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4850 (void)wdcintr(wdc_cp); 4851 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4852 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4853 continue; 4854 } 4855 crv = wdcintr(wdc_cp); 4856 if (crv == 0) 4857 printf("%s:%d: bogus intr\n", 4858 sc->sc_wdcdev.sc_dev.dv_xname, i); 4859 else if (crv == 1) 4860 rv = 1; 4861 else if (rv == 0) 4862 rv = crv; 4863 } 4864 return rv; 4865 } 4866 4867 static int 4868 sl82c105_bugchk(struct pci_attach_args *pa) 4869 { 4870 4871 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 4872 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 4873 return (0); 4874 4875 if (PCI_REVISION(pa->pa_class) <= 0x05) 4876 return (1); 4877 4878 return (0); 4879 } 4880 4881 void 4882 sl82c105_chip_map(sc, pa) 4883 struct pciide_softc *sc; 4884 struct pci_attach_args *pa; 4885 { 4886 struct pciide_channel *cp; 4887 bus_size_t cmdsize, ctlsize; 4888 pcireg_t interface, idecr; 4889 int channel; 4890 4891 if (pciide_chipen(sc, pa) == 0) 4892 return; 4893 4894 printf("%s: bus-master DMA support present", 4895 sc->sc_wdcdev.sc_dev.dv_xname); 4896 4897 /* 4898 * Check to see if we're part of the Winbond 83c553 Southbridge. 4899 * If so, we need to disable DMA on rev. <= 5 of that chip. 4900 */ 4901 if (pci_find_device(pa, sl82c105_bugchk)) { 4902 printf(" but disabled due to 83c553 rev. <= 0x05"); 4903 sc->sc_dma_ok = 0; 4904 } else 4905 pciide_mapreg_dma(sc, pa); 4906 printf("\n"); 4907 4908 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4909 WDC_CAPABILITY_MODE; 4910 sc->sc_wdcdev.PIO_cap = 4; 4911 if (sc->sc_dma_ok) { 4912 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4913 sc->sc_wdcdev.irqack = pciide_irqack; 4914 sc->sc_wdcdev.DMA_cap = 2; 4915 } 4916 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 4917 4918 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4919 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4920 4921 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 4922 4923 interface = PCI_INTERFACE(pa->pa_class); 4924 4925 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4926 cp = &sc->pciide_channels[channel]; 4927 if (pciide_chansetup(sc, channel, interface) == 0) 4928 continue; 4929 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 4930 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 4931 printf("%s: %s channel ignored (disabled)\n", 4932 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4933 continue; 4934 } 4935 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4936 pciide_pci_intr); 4937 if (cp->hw_ok == 0) 4938 continue; 4939 pciide_map_compat_intr(pa, cp, channel, interface); 4940 if (cp->hw_ok == 0) 4941 continue; 4942 sl82c105_setup_channel(&cp->wdc_channel); 4943 } 4944 } 4945 4946 void 4947 sl82c105_setup_channel(chp) 4948 struct channel_softc *chp; 4949 { 4950 struct ata_drive_datas *drvp; 4951 struct pciide_channel *cp = (struct pciide_channel*)chp; 4952 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4953 int pxdx_reg, drive; 4954 pcireg_t pxdx; 4955 4956 /* Set up DMA if needed. */ 4957 pciide_channel_dma_setup(cp); 4958 4959 for (drive = 0; drive < 2; drive++) { 4960 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 4961 : SYMPH_P1D0CR) + (drive * 4); 4962 4963 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 4964 4965 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 4966 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 4967 4968 drvp = &chp->ch_drive[drive]; 4969 /* If no drive, skip. */ 4970 if ((drvp->drive_flags & DRIVE) == 0) { 4971 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 4972 continue; 4973 } 4974 4975 if (drvp->drive_flags & DRIVE_DMA) { 4976 /* 4977 * Timings will be used for both PIO and DMA, 4978 * so adjust DMA mode if needed. 4979 */ 4980 if (drvp->PIO_mode >= 3) { 4981 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 4982 drvp->DMA_mode = drvp->PIO_mode - 2; 4983 if (drvp->DMA_mode < 1) { 4984 /* 4985 * Can't mix both PIO and DMA. 4986 * Disable DMA. 4987 */ 4988 drvp->drive_flags &= ~DRIVE_DMA; 4989 } 4990 } else { 4991 /* 4992 * Can't mix both PIO and DMA. Disable 4993 * DMA. 4994 */ 4995 drvp->drive_flags &= ~DRIVE_DMA; 4996 } 4997 } 4998 4999 if (drvp->drive_flags & DRIVE_DMA) { 5000 /* Use multi-word DMA. */ 5001 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 5002 PxDx_CMD_ON_SHIFT; 5003 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 5004 } else { 5005 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 5006 PxDx_CMD_ON_SHIFT; 5007 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 5008 } 5009 5010 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 5011 5012 /* ...and set the mode for this drive. */ 5013 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 5014 } 5015 5016 pciide_print_modes(cp); 5017 } 5018 5019 void 5020 serverworks_chip_map(sc, pa) 5021 struct pciide_softc *sc; 5022 struct pci_attach_args *pa; 5023 { 5024 struct pciide_channel *cp; 5025 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 5026 pcitag_t pcib_tag; 5027 int channel; 5028 bus_size_t cmdsize, ctlsize; 5029 5030 if (pciide_chipen(sc, pa) == 0) 5031 return; 5032 5033 printf("%s: bus-master DMA support present", 5034 sc->sc_wdcdev.sc_dev.dv_xname); 5035 pciide_mapreg_dma(sc, pa); 5036 printf("\n"); 5037 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5038 WDC_CAPABILITY_MODE; 5039 5040 if (sc->sc_dma_ok) { 5041 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5042 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5043 sc->sc_wdcdev.irqack = pciide_irqack; 5044 } 5045 sc->sc_wdcdev.PIO_cap = 4; 5046 sc->sc_wdcdev.DMA_cap = 2; 5047 switch (sc->sc_pp->ide_product) { 5048 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 5049 sc->sc_wdcdev.UDMA_cap = 2; 5050 break; 5051 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 5052 if (PCI_REVISION(pa->pa_class) < 0x92) 5053 sc->sc_wdcdev.UDMA_cap = 4; 5054 else 5055 sc->sc_wdcdev.UDMA_cap = 5; 5056 break; 5057 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 5058 sc->sc_wdcdev.UDMA_cap = 5; 5059 break; 5060 } 5061 5062 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 5063 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5064 sc->sc_wdcdev.nchannels = 2; 5065 5066 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5067 cp = &sc->pciide_channels[channel]; 5068 if (pciide_chansetup(sc, channel, interface) == 0) 5069 continue; 5070 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5071 serverworks_pci_intr); 5072 if (cp->hw_ok == 0) 5073 return; 5074 pciide_map_compat_intr(pa, cp, channel, interface); 5075 if (cp->hw_ok == 0) 5076 return; 5077 serverworks_setup_channel(&cp->wdc_channel); 5078 } 5079 5080 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 5081 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 5082 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 5083 } 5084 5085 void 5086 serverworks_setup_channel(chp) 5087 struct channel_softc *chp; 5088 { 5089 struct ata_drive_datas *drvp; 5090 struct pciide_channel *cp = (struct pciide_channel*)chp; 5091 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5092 int channel = chp->channel; 5093 int drive, unit; 5094 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 5095 u_int32_t idedma_ctl; 5096 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 5097 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 5098 5099 /* setup DMA if needed */ 5100 pciide_channel_dma_setup(cp); 5101 5102 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 5103 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 5104 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 5105 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 5106 5107 pio_time &= ~(0xffff << (16 * channel)); 5108 dma_time &= ~(0xffff << (16 * channel)); 5109 pio_mode &= ~(0xff << (8 * channel + 16)); 5110 udma_mode &= ~(0xff << (8 * channel + 16)); 5111 udma_mode &= ~(3 << (2 * channel)); 5112 5113 idedma_ctl = 0; 5114 5115 /* Per drive settings */ 5116 for (drive = 0; drive < 2; drive++) { 5117 drvp = &chp->ch_drive[drive]; 5118 /* If no drive, skip */ 5119 if ((drvp->drive_flags & DRIVE) == 0) 5120 continue; 5121 unit = drive + 2 * channel; 5122 /* add timing values, setup DMA if needed */ 5123 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 5124 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 5125 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 5126 (drvp->drive_flags & DRIVE_UDMA)) { 5127 /* use Ultra/DMA, check for 80-pin cable */ 5128 if (drvp->UDMA_mode > 2 && 5129 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 5130 drvp->UDMA_mode = 2; 5131 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 5132 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 5133 udma_mode |= 1 << unit; 5134 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5135 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 5136 (drvp->drive_flags & DRIVE_DMA)) { 5137 /* use Multiword DMA */ 5138 drvp->drive_flags &= ~DRIVE_UDMA; 5139 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 5140 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5141 } else { 5142 /* PIO only */ 5143 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 5144 } 5145 } 5146 5147 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 5148 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 5149 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 5150 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 5151 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 5152 5153 if (idedma_ctl != 0) { 5154 /* Add software bits in status register */ 5155 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5156 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 5157 } 5158 pciide_print_modes(cp); 5159 } 5160 5161 int 5162 serverworks_pci_intr(arg) 5163 void *arg; 5164 { 5165 struct pciide_softc *sc = arg; 5166 struct pciide_channel *cp; 5167 struct channel_softc *wdc_cp; 5168 int rv = 0; 5169 int dmastat, i, crv; 5170 5171 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5172 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5173 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 5174 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 5175 IDEDMA_CTL_INTR) 5176 continue; 5177 cp = &sc->pciide_channels[i]; 5178 wdc_cp = &cp->wdc_channel; 5179 crv = wdcintr(wdc_cp); 5180 if (crv == 0) { 5181 printf("%s:%d: bogus intr\n", 5182 sc->sc_wdcdev.sc_dev.dv_xname, i); 5183 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5184 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 5185 } else 5186 rv = 1; 5187 } 5188 return rv; 5189 } 5190
Indexes created Thu Oct 02 10:09:58 GMT 2025