pciide.c revision 1.184
1 /* $NetBSD: pciide.c,v 1.184 2003/03/18 01:13:08 thorpej Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.184 2003/03/18 01:13:08 thorpej Exp $"); 80 81 #ifndef WDCDEBUG 82 #define WDCDEBUG 83 #endif 84 85 #define DEBUG_DMA 0x01 86 #define DEBUG_XFERS 0x02 87 #define DEBUG_FUNCS 0x08 88 #define DEBUG_PROBE 0x10 89 #ifdef WDCDEBUG 90 int wdcdebug_pciide_mask = 0; 91 #define WDCDEBUG_PRINT(args, level) \ 92 if (wdcdebug_pciide_mask & (level)) printf args 93 #else 94 #define WDCDEBUG_PRINT(args, level) 95 #endif 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <machine/endian.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/pciide_sl82c105_reg.h> 122 #include <dev/pci/cy82c693var.h> 123 124 #include "opt_pciide.h" 125 126 /* inlines for reading/writing 8-bit PCI registers */ 127 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 128 int)); 129 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 130 int, u_int8_t)); 131 132 static __inline u_int8_t 133 pciide_pci_read(pc, pa, reg) 134 pci_chipset_tag_t pc; 135 pcitag_t pa; 136 int reg; 137 { 138 139 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 140 ((reg & 0x03) * 8) & 0xff); 141 } 142 143 static __inline void 144 pciide_pci_write(pc, pa, reg, val) 145 pci_chipset_tag_t pc; 146 pcitag_t pa; 147 int reg; 148 u_int8_t val; 149 { 150 pcireg_t pcival; 151 152 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 153 pcival &= ~(0xff << ((reg & 0x03) * 8)); 154 pcival |= (val << ((reg & 0x03) * 8)); 155 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 156 } 157 158 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 160 void sata_setup_channel __P((struct channel_softc*)); 161 162 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 163 void piix_setup_channel __P((struct channel_softc*)); 164 void piix3_4_setup_channel __P((struct channel_softc*)); 165 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 166 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 167 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 168 169 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 170 void amd7x6_setup_channel __P((struct channel_softc*)); 171 172 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 173 void apollo_setup_channel __P((struct channel_softc*)); 174 175 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 176 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 177 void cmd0643_9_setup_channel __P((struct channel_softc*)); 178 void cmd_channel_map __P((struct pci_attach_args *, 179 struct pciide_softc *, int)); 180 int cmd_pci_intr __P((void *)); 181 void cmd646_9_irqack __P((struct channel_softc *)); 182 void cmd680_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 183 void cmd680_setup_channel __P((struct channel_softc*)); 184 void cmd680_channel_map __P((struct pci_attach_args *, 185 struct pciide_softc *, int)); 186 187 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 188 void cy693_setup_channel __P((struct channel_softc*)); 189 190 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 191 void sis_setup_channel __P((struct channel_softc*)); 192 void sis96x_setup_channel __P((struct channel_softc*)); 193 static int sis_hostbr_match __P(( struct pci_attach_args *)); 194 static int sis_south_match __P(( struct pci_attach_args *)); 195 196 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 197 void acer_setup_channel __P((struct channel_softc*)); 198 int acer_pci_intr __P((void *)); 199 200 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 201 void pdc202xx_setup_channel __P((struct channel_softc*)); 202 void pdc20268_setup_channel __P((struct channel_softc*)); 203 int pdc202xx_pci_intr __P((void *)); 204 int pdc20265_pci_intr __P((void *)); 205 206 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 207 void opti_setup_channel __P((struct channel_softc*)); 208 209 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 210 void hpt_setup_channel __P((struct channel_softc*)); 211 int hpt_pci_intr __P((void *)); 212 213 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 214 void acard_setup_channel __P((struct channel_softc*)); 215 int acard_pci_intr __P((void *)); 216 217 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 218 void serverworks_setup_channel __P((struct channel_softc*)); 219 int serverworks_pci_intr __P((void *)); 220 221 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 222 void sl82c105_setup_channel __P((struct channel_softc*)); 223 224 void pciide_channel_dma_setup __P((struct pciide_channel *)); 225 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 226 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 227 void pciide_dma_start __P((void*, int, int)); 228 int pciide_dma_finish __P((void*, int, int, int)); 229 void pciide_irqack __P((struct channel_softc *)); 230 void pciide_print_modes __P((struct pciide_channel *)); 231 232 void artisea_chip_map __P((struct pciide_softc*, struct pci_attach_args *)); 233 234 struct pciide_product_desc { 235 u_int32_t ide_product; 236 int ide_flags; 237 const char *ide_name; 238 /* map and setup chip, probe drives */ 239 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 240 }; 241 242 /* Flags for ide_flags */ 243 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 244 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 245 246 /* Default product description for devices not known from this controller */ 247 const struct pciide_product_desc default_product_desc = { 248 0, 249 0, 250 "Generic PCI IDE controller", 251 default_chip_map, 252 }; 253 254 const struct pciide_product_desc pciide_intel_products[] = { 255 { PCI_PRODUCT_INTEL_82092AA, 256 0, 257 "Intel 82092AA IDE controller", 258 default_chip_map, 259 }, 260 { PCI_PRODUCT_INTEL_82371FB_IDE, 261 0, 262 "Intel 82371FB IDE controller (PIIX)", 263 piix_chip_map, 264 }, 265 { PCI_PRODUCT_INTEL_82371SB_IDE, 266 0, 267 "Intel 82371SB IDE Interface (PIIX3)", 268 piix_chip_map, 269 }, 270 { PCI_PRODUCT_INTEL_82371AB_IDE, 271 0, 272 "Intel 82371AB IDE controller (PIIX4)", 273 piix_chip_map, 274 }, 275 { PCI_PRODUCT_INTEL_82440MX_IDE, 276 0, 277 "Intel 82440MX IDE controller", 278 piix_chip_map 279 }, 280 { PCI_PRODUCT_INTEL_82801AA_IDE, 281 0, 282 "Intel 82801AA IDE Controller (ICH)", 283 piix_chip_map, 284 }, 285 { PCI_PRODUCT_INTEL_82801AB_IDE, 286 0, 287 "Intel 82801AB IDE Controller (ICH0)", 288 piix_chip_map, 289 }, 290 { PCI_PRODUCT_INTEL_82801BA_IDE, 291 0, 292 "Intel 82801BA IDE Controller (ICH2)", 293 piix_chip_map, 294 }, 295 { PCI_PRODUCT_INTEL_82801BAM_IDE, 296 0, 297 "Intel 82801BAM IDE Controller (ICH2)", 298 piix_chip_map, 299 }, 300 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 301 0, 302 "Intel 82801CA IDE Controller", 303 piix_chip_map, 304 }, 305 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 306 0, 307 "Intel 82801CA IDE Controller", 308 piix_chip_map, 309 }, 310 { PCI_PRODUCT_INTEL_82801DB_IDE, 311 0, 312 "Intel 82801DB IDE Controller (ICH4)", 313 piix_chip_map, 314 }, 315 { PCI_PRODUCT_INTEL_31244, 316 0, 317 "Intel 31244 Serial ATA Controller", 318 artisea_chip_map, 319 }, 320 { 0, 321 0, 322 NULL, 323 NULL 324 } 325 }; 326 327 const struct pciide_product_desc pciide_amd_products[] = { 328 { PCI_PRODUCT_AMD_PBC756_IDE, 329 0, 330 "Advanced Micro Devices AMD756 IDE Controller", 331 amd7x6_chip_map 332 }, 333 { PCI_PRODUCT_AMD_PBC766_IDE, 334 0, 335 "Advanced Micro Devices AMD766 IDE Controller", 336 amd7x6_chip_map 337 }, 338 { PCI_PRODUCT_AMD_PBC768_IDE, 339 0, 340 "Advanced Micro Devices AMD768 IDE Controller", 341 amd7x6_chip_map 342 }, 343 { PCI_PRODUCT_AMD_PBC8111_IDE, 344 0, 345 "Advanced Micro Devices AMD8111 IDE Controller", 346 amd7x6_chip_map 347 }, 348 { 0, 349 0, 350 NULL, 351 NULL 352 } 353 }; 354 355 const struct pciide_product_desc pciide_nvidia_products[] = { 356 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 357 0, 358 "NVIDIA nForce IDE Controller", 359 amd7x6_chip_map 360 }, 361 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 362 0, 363 "NVIDIA nForce2 IDE Controller", 364 amd7x6_chip_map 365 }, 366 { 0, 367 0, 368 NULL, 369 NULL 370 } 371 }; 372 373 const struct pciide_product_desc pciide_cmd_products[] = { 374 { PCI_PRODUCT_CMDTECH_640, 375 0, 376 "CMD Technology PCI0640", 377 cmd_chip_map 378 }, 379 { PCI_PRODUCT_CMDTECH_643, 380 0, 381 "CMD Technology PCI0643", 382 cmd0643_9_chip_map, 383 }, 384 { PCI_PRODUCT_CMDTECH_646, 385 0, 386 "CMD Technology PCI0646", 387 cmd0643_9_chip_map, 388 }, 389 { PCI_PRODUCT_CMDTECH_648, 390 IDE_PCI_CLASS_OVERRIDE, 391 "CMD Technology PCI0648", 392 cmd0643_9_chip_map, 393 }, 394 { PCI_PRODUCT_CMDTECH_649, 395 IDE_PCI_CLASS_OVERRIDE, 396 "CMD Technology PCI0649", 397 cmd0643_9_chip_map, 398 }, 399 { PCI_PRODUCT_CMDTECH_680, 400 IDE_PCI_CLASS_OVERRIDE, 401 "Silicon Image 0680", 402 cmd680_chip_map, 403 }, 404 { 0, 405 0, 406 NULL, 407 NULL 408 } 409 }; 410 411 const struct pciide_product_desc pciide_via_products[] = { 412 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 413 0, 414 NULL, 415 apollo_chip_map, 416 }, 417 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 418 0, 419 NULL, 420 apollo_chip_map, 421 }, 422 { 0, 423 0, 424 NULL, 425 NULL 426 } 427 }; 428 429 const struct pciide_product_desc pciide_cypress_products[] = { 430 { PCI_PRODUCT_CONTAQ_82C693, 431 IDE_16BIT_IOSPACE, 432 "Cypress 82C693 IDE Controller", 433 cy693_chip_map, 434 }, 435 { 0, 436 0, 437 NULL, 438 NULL 439 } 440 }; 441 442 const struct pciide_product_desc pciide_sis_products[] = { 443 { PCI_PRODUCT_SIS_5597_IDE, 444 0, 445 NULL, 446 sis_chip_map, 447 }, 448 { 0, 449 0, 450 NULL, 451 NULL 452 } 453 }; 454 455 const struct pciide_product_desc pciide_acer_products[] = { 456 { PCI_PRODUCT_ALI_M5229, 457 0, 458 "Acer Labs M5229 UDMA IDE Controller", 459 acer_chip_map, 460 }, 461 { 0, 462 0, 463 NULL, 464 NULL 465 } 466 }; 467 468 const struct pciide_product_desc pciide_promise_products[] = { 469 { PCI_PRODUCT_PROMISE_ULTRA33, 470 IDE_PCI_CLASS_OVERRIDE, 471 "Promise Ultra33/ATA Bus Master IDE Accelerator", 472 pdc202xx_chip_map, 473 }, 474 { PCI_PRODUCT_PROMISE_ULTRA66, 475 IDE_PCI_CLASS_OVERRIDE, 476 "Promise Ultra66/ATA Bus Master IDE Accelerator", 477 pdc202xx_chip_map, 478 }, 479 { PCI_PRODUCT_PROMISE_ULTRA100, 480 IDE_PCI_CLASS_OVERRIDE, 481 "Promise Ultra100/ATA Bus Master IDE Accelerator", 482 pdc202xx_chip_map, 483 }, 484 { PCI_PRODUCT_PROMISE_ULTRA100X, 485 IDE_PCI_CLASS_OVERRIDE, 486 "Promise Ultra100/ATA Bus Master IDE Accelerator", 487 pdc202xx_chip_map, 488 }, 489 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 490 IDE_PCI_CLASS_OVERRIDE, 491 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 492 pdc202xx_chip_map, 493 }, 494 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 495 IDE_PCI_CLASS_OVERRIDE, 496 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 497 pdc202xx_chip_map, 498 }, 499 { PCI_PRODUCT_PROMISE_ULTRA133, 500 IDE_PCI_CLASS_OVERRIDE, 501 "Promise Ultra133/ATA Bus Master IDE Accelerator", 502 pdc202xx_chip_map, 503 }, 504 { PCI_PRODUCT_PROMISE_ULTRA133TX2, 505 IDE_PCI_CLASS_OVERRIDE, 506 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 507 pdc202xx_chip_map, 508 }, 509 { PCI_PRODUCT_PROMISE_MBULTRA133, 510 IDE_PCI_CLASS_OVERRIDE, 511 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 512 pdc202xx_chip_map, 513 }, 514 { PCI_PRODUCT_PROMISE_ULTRA133TX2v2, 515 IDE_PCI_CLASS_OVERRIDE, 516 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 517 pdc202xx_chip_map, 518 }, 519 { PCI_PRODUCT_PROMISE_FASTTRAK133LITE, 520 IDE_PCI_CLASS_OVERRIDE, 521 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 522 pdc202xx_chip_map, 523 }, 524 { PCI_PRODUCT_PROMISE_SATA150TX2PLUS, 525 IDE_PCI_CLASS_OVERRIDE, 526 "Promise Serial ATA/150 TX2plus Bus Master IDE Accelerator", 527 pdc202xx_chip_map, 528 }, 529 { 0, 530 0, 531 NULL, 532 NULL 533 } 534 }; 535 536 const struct pciide_product_desc pciide_opti_products[] = { 537 { PCI_PRODUCT_OPTI_82C621, 538 0, 539 "OPTi 82c621 PCI IDE controller", 540 opti_chip_map, 541 }, 542 { PCI_PRODUCT_OPTI_82C568, 543 0, 544 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 545 opti_chip_map, 546 }, 547 { PCI_PRODUCT_OPTI_82D568, 548 0, 549 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 550 opti_chip_map, 551 }, 552 { 0, 553 0, 554 NULL, 555 NULL 556 } 557 }; 558 559 const struct pciide_product_desc pciide_triones_products[] = { 560 { PCI_PRODUCT_TRIONES_HPT366, 561 IDE_PCI_CLASS_OVERRIDE, 562 NULL, 563 hpt_chip_map, 564 }, 565 { PCI_PRODUCT_TRIONES_HPT372, 566 IDE_PCI_CLASS_OVERRIDE, 567 NULL, 568 hpt_chip_map 569 }, 570 { PCI_PRODUCT_TRIONES_HPT374, 571 IDE_PCI_CLASS_OVERRIDE, 572 NULL, 573 hpt_chip_map 574 }, 575 { 0, 576 0, 577 NULL, 578 NULL 579 } 580 }; 581 582 const struct pciide_product_desc pciide_acard_products[] = { 583 { PCI_PRODUCT_ACARD_ATP850U, 584 IDE_PCI_CLASS_OVERRIDE, 585 "Acard ATP850U Ultra33 IDE Controller", 586 acard_chip_map, 587 }, 588 { PCI_PRODUCT_ACARD_ATP860, 589 IDE_PCI_CLASS_OVERRIDE, 590 "Acard ATP860 Ultra66 IDE Controller", 591 acard_chip_map, 592 }, 593 { PCI_PRODUCT_ACARD_ATP860A, 594 IDE_PCI_CLASS_OVERRIDE, 595 "Acard ATP860-A Ultra66 IDE Controller", 596 acard_chip_map, 597 }, 598 { 0, 599 0, 600 NULL, 601 NULL 602 } 603 }; 604 605 const struct pciide_product_desc pciide_serverworks_products[] = { 606 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 607 0, 608 "ServerWorks OSB4 IDE Controller", 609 serverworks_chip_map, 610 }, 611 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 612 0, 613 "ServerWorks CSB5 IDE Controller", 614 serverworks_chip_map, 615 }, 616 { PCI_PRODUCT_SERVERWORKS_CSB6_IDE, 617 0, 618 "ServerWorks CSB6 RAID/IDE Controller", 619 serverworks_chip_map, 620 }, 621 { 0, 622 0, 623 NULL, 624 } 625 }; 626 627 const struct pciide_product_desc pciide_symphony_products[] = { 628 { PCI_PRODUCT_SYMPHONY_82C105, 629 0, 630 "Symphony Labs 82C105 IDE controller", 631 sl82c105_chip_map, 632 }, 633 { 0, 634 0, 635 NULL, 636 } 637 }; 638 639 const struct pciide_product_desc pciide_winbond_products[] = { 640 { PCI_PRODUCT_WINBOND_W83C553F_1, 641 0, 642 "Winbond W83C553F IDE controller", 643 sl82c105_chip_map, 644 }, 645 { 0, 646 0, 647 NULL, 648 } 649 }; 650 651 struct pciide_vendor_desc { 652 u_int32_t ide_vendor; 653 const struct pciide_product_desc *ide_products; 654 }; 655 656 const struct pciide_vendor_desc pciide_vendors[] = { 657 { PCI_VENDOR_INTEL, pciide_intel_products }, 658 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 659 { PCI_VENDOR_VIATECH, pciide_via_products }, 660 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 661 { PCI_VENDOR_SIS, pciide_sis_products }, 662 { PCI_VENDOR_ALI, pciide_acer_products }, 663 { PCI_VENDOR_PROMISE, pciide_promise_products }, 664 { PCI_VENDOR_AMD, pciide_amd_products }, 665 { PCI_VENDOR_OPTI, pciide_opti_products }, 666 { PCI_VENDOR_TRIONES, pciide_triones_products }, 667 { PCI_VENDOR_ACARD, pciide_acard_products }, 668 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 669 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 670 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 671 { PCI_VENDOR_NVIDIA, pciide_nvidia_products }, 672 { 0, NULL } 673 }; 674 675 /* options passed via the 'flags' config keyword */ 676 #define PCIIDE_OPTIONS_DMA 0x01 677 #define PCIIDE_OPTIONS_NODMA 0x02 678 679 int pciide_match __P((struct device *, struct cfdata *, void *)); 680 void pciide_attach __P((struct device *, struct device *, void *)); 681 682 CFATTACH_DECL(pciide, sizeof(struct pciide_softc), 683 pciide_match, pciide_attach, NULL, NULL); 684 685 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 686 int pciide_mapregs_compat __P(( struct pci_attach_args *, 687 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 688 int pciide_mapregs_native __P((struct pci_attach_args *, 689 struct pciide_channel *, bus_size_t *, bus_size_t *, 690 int (*pci_intr) __P((void *)))); 691 void pciide_mapreg_dma __P((struct pciide_softc *, 692 struct pci_attach_args *)); 693 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 694 void pciide_mapchan __P((struct pci_attach_args *, 695 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 696 int (*pci_intr) __P((void *)))); 697 int pciide_chan_candisable __P((struct pciide_channel *)); 698 void pciide_map_compat_intr __P(( struct pci_attach_args *, 699 struct pciide_channel *, int, int)); 700 int pciide_compat_intr __P((void *)); 701 int pciide_pci_intr __P((void *)); 702 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 703 704 const struct pciide_product_desc * 705 pciide_lookup_product(id) 706 u_int32_t id; 707 { 708 const struct pciide_product_desc *pp; 709 const struct pciide_vendor_desc *vp; 710 711 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 712 if (PCI_VENDOR(id) == vp->ide_vendor) 713 break; 714 715 if ((pp = vp->ide_products) == NULL) 716 return NULL; 717 718 for (; pp->chip_map != NULL; pp++) 719 if (PCI_PRODUCT(id) == pp->ide_product) 720 break; 721 722 if (pp->chip_map == NULL) 723 return NULL; 724 return pp; 725 } 726 727 int 728 pciide_match(parent, match, aux) 729 struct device *parent; 730 struct cfdata *match; 731 void *aux; 732 { 733 struct pci_attach_args *pa = aux; 734 const struct pciide_product_desc *pp; 735 736 /* 737 * Check the ID register to see that it's a PCI IDE controller. 738 * If it is, we assume that we can deal with it; it _should_ 739 * work in a standardized way... 740 */ 741 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 742 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 743 return (1); 744 } 745 746 /* 747 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 748 * controllers. Let see if we can deal with it anyway. 749 */ 750 pp = pciide_lookup_product(pa->pa_id); 751 if (pp != NULL && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 752 return (1); 753 } 754 755 return (0); 756 } 757 758 void 759 pciide_attach(parent, self, aux) 760 struct device *parent, *self; 761 void *aux; 762 { 763 struct pci_attach_args *pa = aux; 764 pci_chipset_tag_t pc = pa->pa_pc; 765 pcitag_t tag = pa->pa_tag; 766 struct pciide_softc *sc = (struct pciide_softc *)self; 767 pcireg_t csr; 768 char devinfo[256]; 769 const char *displaydev; 770 771 sc->sc_pci_vendor = PCI_VENDOR(pa->pa_id); 772 sc->sc_pp = pciide_lookup_product(pa->pa_id); 773 if (sc->sc_pp == NULL) { 774 sc->sc_pp = &default_product_desc; 775 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 776 displaydev = devinfo; 777 } else 778 displaydev = sc->sc_pp->ide_name; 779 780 /* if displaydev == NULL, printf is done in chip-specific map */ 781 if (displaydev) 782 printf(": %s (rev. 0x%02x)\n", displaydev, 783 PCI_REVISION(pa->pa_class)); 784 785 sc->sc_pc = pa->pa_pc; 786 sc->sc_tag = pa->pa_tag; 787 #ifdef WDCDEBUG 788 if (wdcdebug_pciide_mask & DEBUG_PROBE) 789 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 790 #endif 791 sc->sc_pp->chip_map(sc, pa); 792 793 if (sc->sc_dma_ok) { 794 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 795 csr |= PCI_COMMAND_MASTER_ENABLE; 796 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 797 } 798 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 799 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 800 } 801 802 /* tell whether the chip is enabled or not */ 803 int 804 pciide_chipen(sc, pa) 805 struct pciide_softc *sc; 806 struct pci_attach_args *pa; 807 { 808 pcireg_t csr; 809 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 810 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 811 PCI_COMMAND_STATUS_REG); 812 printf("%s: device disabled (at %s)\n", 813 sc->sc_wdcdev.sc_dev.dv_xname, 814 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 815 "device" : "bridge"); 816 return 0; 817 } 818 return 1; 819 } 820 821 int 822 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 823 struct pci_attach_args *pa; 824 struct pciide_channel *cp; 825 int compatchan; 826 bus_size_t *cmdsizep, *ctlsizep; 827 { 828 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 829 struct channel_softc *wdc_cp = &cp->wdc_channel; 830 831 cp->compat = 1; 832 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 833 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 834 835 wdc_cp->cmd_iot = pa->pa_iot; 836 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 837 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 838 printf("%s: couldn't map %s channel cmd regs\n", 839 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 840 return (0); 841 } 842 843 wdc_cp->ctl_iot = pa->pa_iot; 844 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 845 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 846 printf("%s: couldn't map %s channel ctl regs\n", 847 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 848 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 849 PCIIDE_COMPAT_CMD_SIZE); 850 return (0); 851 } 852 853 return (1); 854 } 855 856 int 857 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 858 struct pci_attach_args * pa; 859 struct pciide_channel *cp; 860 bus_size_t *cmdsizep, *ctlsizep; 861 int (*pci_intr) __P((void *)); 862 { 863 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 864 struct channel_softc *wdc_cp = &cp->wdc_channel; 865 const char *intrstr; 866 pci_intr_handle_t intrhandle; 867 868 cp->compat = 0; 869 870 if (sc->sc_pci_ih == NULL) { 871 if (pci_intr_map(pa, &intrhandle) != 0) { 872 printf("%s: couldn't map native-PCI interrupt\n", 873 sc->sc_wdcdev.sc_dev.dv_xname); 874 return 0; 875 } 876 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 877 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 878 intrhandle, IPL_BIO, pci_intr, sc); 879 if (sc->sc_pci_ih != NULL) { 880 printf("%s: using %s for native-PCI interrupt\n", 881 sc->sc_wdcdev.sc_dev.dv_xname, 882 intrstr ? intrstr : "unknown interrupt"); 883 } else { 884 printf("%s: couldn't establish native-PCI interrupt", 885 sc->sc_wdcdev.sc_dev.dv_xname); 886 if (intrstr != NULL) 887 printf(" at %s", intrstr); 888 printf("\n"); 889 return 0; 890 } 891 } 892 cp->ih = sc->sc_pci_ih; 893 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 894 PCI_MAPREG_TYPE_IO, 0, 895 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 896 printf("%s: couldn't map %s channel cmd regs\n", 897 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 898 return 0; 899 } 900 901 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 902 PCI_MAPREG_TYPE_IO, 0, 903 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 904 printf("%s: couldn't map %s channel ctl regs\n", 905 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 906 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 907 return 0; 908 } 909 /* 910 * In native mode, 4 bytes of I/O space are mapped for the control 911 * register, the control register is at offset 2. Pass the generic 912 * code a handle for only one byte at the right offset. 913 */ 914 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 915 &wdc_cp->ctl_ioh) != 0) { 916 printf("%s: unable to subregion %s channel ctl regs\n", 917 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 918 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 919 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 920 return 0; 921 } 922 return (1); 923 } 924 925 void 926 pciide_mapreg_dma(sc, pa) 927 struct pciide_softc *sc; 928 struct pci_attach_args *pa; 929 { 930 pcireg_t maptype; 931 bus_addr_t addr; 932 933 /* 934 * Map DMA registers 935 * 936 * Note that sc_dma_ok is the right variable to test to see if 937 * DMA can be done. If the interface doesn't support DMA, 938 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 939 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 940 * non-zero if the interface supports DMA and the registers 941 * could be mapped. 942 * 943 * XXX Note that despite the fact that the Bus Master IDE specs 944 * XXX say that "The bus master IDE function uses 16 bytes of IO 945 * XXX space," some controllers (at least the United 946 * XXX Microelectronics UM8886BF) place it in memory space. 947 */ 948 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 949 PCIIDE_REG_BUS_MASTER_DMA); 950 951 switch (maptype) { 952 case PCI_MAPREG_TYPE_IO: 953 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 954 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 955 &addr, NULL, NULL) == 0); 956 if (sc->sc_dma_ok == 0) { 957 printf(", but unused (couldn't query registers)"); 958 break; 959 } 960 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 961 && addr >= 0x10000) { 962 sc->sc_dma_ok = 0; 963 printf(", but unused (registers at unsafe address " 964 "%#lx)", (unsigned long)addr); 965 break; 966 } 967 /* FALLTHROUGH */ 968 969 case PCI_MAPREG_MEM_TYPE_32BIT: 970 sc->sc_dma_ok = (pci_mapreg_map(pa, 971 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 972 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 973 sc->sc_dmat = pa->pa_dmat; 974 if (sc->sc_dma_ok == 0) { 975 printf(", but unused (couldn't map registers)"); 976 } else { 977 sc->sc_wdcdev.dma_arg = sc; 978 sc->sc_wdcdev.dma_init = pciide_dma_init; 979 sc->sc_wdcdev.dma_start = pciide_dma_start; 980 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 981 } 982 983 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 984 PCIIDE_OPTIONS_NODMA) { 985 printf(", but unused (forced off by config file)"); 986 sc->sc_dma_ok = 0; 987 } 988 break; 989 990 default: 991 sc->sc_dma_ok = 0; 992 printf(", but unsupported register maptype (0x%x)", maptype); 993 } 994 } 995 996 int 997 pciide_compat_intr(arg) 998 void *arg; 999 { 1000 struct pciide_channel *cp = arg; 1001 1002 #ifdef DIAGNOSTIC 1003 /* should only be called for a compat channel */ 1004 if (cp->compat == 0) 1005 panic("pciide compat intr called for non-compat chan %p", cp); 1006 #endif 1007 return (wdcintr(&cp->wdc_channel)); 1008 } 1009 1010 int 1011 pciide_pci_intr(arg) 1012 void *arg; 1013 { 1014 struct pciide_softc *sc = arg; 1015 struct pciide_channel *cp; 1016 struct channel_softc *wdc_cp; 1017 int i, rv, crv; 1018 1019 rv = 0; 1020 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1021 cp = &sc->pciide_channels[i]; 1022 wdc_cp = &cp->wdc_channel; 1023 1024 /* If a compat channel skip. */ 1025 if (cp->compat) 1026 continue; 1027 /* if this channel not waiting for intr, skip */ 1028 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 1029 continue; 1030 1031 crv = wdcintr(wdc_cp); 1032 if (crv == 0) 1033 ; /* leave rv alone */ 1034 else if (crv == 1) 1035 rv = 1; /* claim the intr */ 1036 else if (rv == 0) /* crv should be -1 in this case */ 1037 rv = crv; /* if we've done no better, take it */ 1038 } 1039 return (rv); 1040 } 1041 1042 void 1043 pciide_channel_dma_setup(cp) 1044 struct pciide_channel *cp; 1045 { 1046 int drive; 1047 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1048 struct ata_drive_datas *drvp; 1049 1050 for (drive = 0; drive < 2; drive++) { 1051 drvp = &cp->wdc_channel.ch_drive[drive]; 1052 /* If no drive, skip */ 1053 if ((drvp->drive_flags & DRIVE) == 0) 1054 continue; 1055 /* setup DMA if needed */ 1056 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1057 (drvp->drive_flags & DRIVE_UDMA) == 0) || 1058 sc->sc_dma_ok == 0) { 1059 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1060 continue; 1061 } 1062 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 1063 != 0) { 1064 /* Abort DMA setup */ 1065 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1066 continue; 1067 } 1068 } 1069 } 1070 1071 int 1072 pciide_dma_table_setup(sc, channel, drive) 1073 struct pciide_softc *sc; 1074 int channel, drive; 1075 { 1076 bus_dma_segment_t seg; 1077 int error, rseg; 1078 const bus_size_t dma_table_size = 1079 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1080 struct pciide_dma_maps *dma_maps = 1081 &sc->pciide_channels[channel].dma_maps[drive]; 1082 1083 /* If table was already allocated, just return */ 1084 if (dma_maps->dma_table) 1085 return 0; 1086 1087 /* Allocate memory for the DMA tables and map it */ 1088 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1089 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1090 BUS_DMA_NOWAIT)) != 0) { 1091 printf("%s:%d: unable to allocate table DMA for " 1092 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1093 channel, drive, error); 1094 return error; 1095 } 1096 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1097 dma_table_size, 1098 (caddr_t *)&dma_maps->dma_table, 1099 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1100 printf("%s:%d: unable to map table DMA for" 1101 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1102 channel, drive, error); 1103 return error; 1104 } 1105 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1106 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1107 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1108 1109 /* Create and load table DMA map for this disk */ 1110 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1111 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1112 &dma_maps->dmamap_table)) != 0) { 1113 printf("%s:%d: unable to create table DMA map for " 1114 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1115 channel, drive, error); 1116 return error; 1117 } 1118 if ((error = bus_dmamap_load(sc->sc_dmat, 1119 dma_maps->dmamap_table, 1120 dma_maps->dma_table, 1121 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1122 printf("%s:%d: unable to load table DMA map for " 1123 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1124 channel, drive, error); 1125 return error; 1126 } 1127 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1128 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1129 DEBUG_PROBE); 1130 /* Create a xfer DMA map for this drive */ 1131 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1132 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1133 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1134 &dma_maps->dmamap_xfer)) != 0) { 1135 printf("%s:%d: unable to create xfer DMA map for " 1136 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1137 channel, drive, error); 1138 return error; 1139 } 1140 return 0; 1141 } 1142 1143 int 1144 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1145 void *v; 1146 int channel, drive; 1147 void *databuf; 1148 size_t datalen; 1149 int flags; 1150 { 1151 struct pciide_softc *sc = v; 1152 int error, seg; 1153 struct pciide_dma_maps *dma_maps = 1154 &sc->pciide_channels[channel].dma_maps[drive]; 1155 1156 error = bus_dmamap_load(sc->sc_dmat, 1157 dma_maps->dmamap_xfer, 1158 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1159 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1160 if (error) { 1161 printf("%s:%d: unable to load xfer DMA map for" 1162 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1163 channel, drive, error); 1164 return error; 1165 } 1166 1167 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1168 dma_maps->dmamap_xfer->dm_mapsize, 1169 (flags & WDC_DMA_READ) ? 1170 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1171 1172 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1173 #ifdef DIAGNOSTIC 1174 /* A segment must not cross a 64k boundary */ 1175 { 1176 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1177 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1178 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1179 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1180 printf("pciide_dma: segment %d physical addr 0x%lx" 1181 " len 0x%lx not properly aligned\n", 1182 seg, phys, len); 1183 panic("pciide_dma: buf align"); 1184 } 1185 } 1186 #endif 1187 dma_maps->dma_table[seg].base_addr = 1188 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1189 dma_maps->dma_table[seg].byte_count = 1190 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1191 IDEDMA_BYTE_COUNT_MASK); 1192 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1193 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1194 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1195 1196 } 1197 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1198 htole32(IDEDMA_BYTE_COUNT_EOT); 1199 1200 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1201 dma_maps->dmamap_table->dm_mapsize, 1202 BUS_DMASYNC_PREWRITE); 1203 1204 /* Maps are ready. Start DMA function */ 1205 #ifdef DIAGNOSTIC 1206 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1207 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1208 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1209 panic("pciide_dma_init: table align"); 1210 } 1211 #endif 1212 1213 /* Clear status bits */ 1214 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1215 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1216 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1217 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1218 /* Write table addr */ 1219 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1220 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1221 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1222 /* set read/write */ 1223 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1224 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1225 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1226 /* remember flags */ 1227 dma_maps->dma_flags = flags; 1228 return 0; 1229 } 1230 1231 void 1232 pciide_dma_start(v, channel, drive) 1233 void *v; 1234 int channel, drive; 1235 { 1236 struct pciide_softc *sc = v; 1237 1238 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1239 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1240 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1241 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1242 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1243 } 1244 1245 int 1246 pciide_dma_finish(v, channel, drive, force) 1247 void *v; 1248 int channel, drive; 1249 int force; 1250 { 1251 struct pciide_softc *sc = v; 1252 u_int8_t status; 1253 int error = 0; 1254 struct pciide_dma_maps *dma_maps = 1255 &sc->pciide_channels[channel].dma_maps[drive]; 1256 1257 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1258 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1259 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1260 DEBUG_XFERS); 1261 1262 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1263 return WDC_DMAST_NOIRQ; 1264 1265 /* stop DMA channel */ 1266 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1267 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1268 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1269 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1270 1271 /* Unload the map of the data buffer */ 1272 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1273 dma_maps->dmamap_xfer->dm_mapsize, 1274 (dma_maps->dma_flags & WDC_DMA_READ) ? 1275 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1276 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1277 1278 if ((status & IDEDMA_CTL_ERR) != 0) { 1279 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1280 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1281 error |= WDC_DMAST_ERR; 1282 } 1283 1284 if ((status & IDEDMA_CTL_INTR) == 0) { 1285 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1286 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1287 drive, status); 1288 error |= WDC_DMAST_NOIRQ; 1289 } 1290 1291 if ((status & IDEDMA_CTL_ACT) != 0) { 1292 /* data underrun, may be a valid condition for ATAPI */ 1293 error |= WDC_DMAST_UNDER; 1294 } 1295 return error; 1296 } 1297 1298 void 1299 pciide_irqack(chp) 1300 struct channel_softc *chp; 1301 { 1302 struct pciide_channel *cp = (struct pciide_channel*)chp; 1303 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1304 1305 /* clear status bits in IDE DMA registers */ 1306 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1307 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1308 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1309 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1310 } 1311 1312 /* some common code used by several chip_map */ 1313 int 1314 pciide_chansetup(sc, channel, interface) 1315 struct pciide_softc *sc; 1316 int channel; 1317 pcireg_t interface; 1318 { 1319 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1320 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1321 cp->name = PCIIDE_CHANNEL_NAME(channel); 1322 cp->wdc_channel.channel = channel; 1323 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1324 cp->wdc_channel.ch_queue = 1325 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1326 if (cp->wdc_channel.ch_queue == NULL) { 1327 printf("%s %s channel: " 1328 "can't allocate memory for command queue", 1329 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1330 return 0; 1331 } 1332 printf("%s: %s channel %s to %s mode\n", 1333 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1334 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1335 "configured" : "wired", 1336 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1337 "native-PCI" : "compatibility"); 1338 return 1; 1339 } 1340 1341 /* some common code used by several chip channel_map */ 1342 void 1343 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1344 struct pci_attach_args *pa; 1345 struct pciide_channel *cp; 1346 pcireg_t interface; 1347 bus_size_t *cmdsizep, *ctlsizep; 1348 int (*pci_intr) __P((void *)); 1349 { 1350 struct channel_softc *wdc_cp = &cp->wdc_channel; 1351 1352 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1353 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1354 pci_intr); 1355 else 1356 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1357 wdc_cp->channel, cmdsizep, ctlsizep); 1358 1359 if (cp->hw_ok == 0) 1360 return; 1361 wdc_cp->data32iot = wdc_cp->cmd_iot; 1362 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1363 wdcattach(wdc_cp); 1364 } 1365 1366 /* 1367 * Generic code to call to know if a channel can be disabled. Return 1 1368 * if channel can be disabled, 0 if not 1369 */ 1370 int 1371 pciide_chan_candisable(cp) 1372 struct pciide_channel *cp; 1373 { 1374 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1375 struct channel_softc *wdc_cp = &cp->wdc_channel; 1376 1377 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1378 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1379 printf("%s: disabling %s channel (no drives)\n", 1380 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1381 cp->hw_ok = 0; 1382 return 1; 1383 } 1384 return 0; 1385 } 1386 1387 /* 1388 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1389 * Set hw_ok=0 on failure 1390 */ 1391 void 1392 pciide_map_compat_intr(pa, cp, compatchan, interface) 1393 struct pci_attach_args *pa; 1394 struct pciide_channel *cp; 1395 int compatchan, interface; 1396 { 1397 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1398 struct channel_softc *wdc_cp = &cp->wdc_channel; 1399 1400 if (cp->hw_ok == 0) 1401 return; 1402 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1403 return; 1404 1405 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1406 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1407 pa, compatchan, pciide_compat_intr, cp); 1408 if (cp->ih == NULL) { 1409 #endif 1410 printf("%s: no compatibility interrupt for use by %s " 1411 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1412 cp->hw_ok = 0; 1413 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1414 } 1415 #endif 1416 } 1417 1418 void 1419 pciide_print_modes(cp) 1420 struct pciide_channel *cp; 1421 { 1422 wdc_print_modes(&cp->wdc_channel); 1423 } 1424 1425 void 1426 default_chip_map(sc, pa) 1427 struct pciide_softc *sc; 1428 struct pci_attach_args *pa; 1429 { 1430 struct pciide_channel *cp; 1431 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1432 pcireg_t csr; 1433 int channel, drive; 1434 struct ata_drive_datas *drvp; 1435 u_int8_t idedma_ctl; 1436 bus_size_t cmdsize, ctlsize; 1437 char *failreason; 1438 1439 if (pciide_chipen(sc, pa) == 0) 1440 return; 1441 1442 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1443 printf("%s: bus-master DMA support present", 1444 sc->sc_wdcdev.sc_dev.dv_xname); 1445 if (sc->sc_pp == &default_product_desc && 1446 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1447 PCIIDE_OPTIONS_DMA) == 0) { 1448 printf(", but unused (no driver support)"); 1449 sc->sc_dma_ok = 0; 1450 } else { 1451 pciide_mapreg_dma(sc, pa); 1452 if (sc->sc_dma_ok != 0) 1453 printf(", used without full driver " 1454 "support"); 1455 } 1456 } else { 1457 printf("%s: hardware does not support DMA", 1458 sc->sc_wdcdev.sc_dev.dv_xname); 1459 sc->sc_dma_ok = 0; 1460 } 1461 printf("\n"); 1462 if (sc->sc_dma_ok) { 1463 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1464 sc->sc_wdcdev.irqack = pciide_irqack; 1465 } 1466 sc->sc_wdcdev.PIO_cap = 0; 1467 sc->sc_wdcdev.DMA_cap = 0; 1468 1469 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1470 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1471 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1472 1473 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1474 cp = &sc->pciide_channels[channel]; 1475 if (pciide_chansetup(sc, channel, interface) == 0) 1476 continue; 1477 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1478 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1479 &ctlsize, pciide_pci_intr); 1480 } else { 1481 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1482 channel, &cmdsize, &ctlsize); 1483 } 1484 if (cp->hw_ok == 0) 1485 continue; 1486 /* 1487 * Check to see if something appears to be there. 1488 */ 1489 failreason = NULL; 1490 if (!wdcprobe(&cp->wdc_channel)) { 1491 failreason = "not responding; disabled or no drives?"; 1492 goto next; 1493 } 1494 /* 1495 * Now, make sure it's actually attributable to this PCI IDE 1496 * channel by trying to access the channel again while the 1497 * PCI IDE controller's I/O space is disabled. (If the 1498 * channel no longer appears to be there, it belongs to 1499 * this controller.) YUCK! 1500 */ 1501 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1502 PCI_COMMAND_STATUS_REG); 1503 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1504 csr & ~PCI_COMMAND_IO_ENABLE); 1505 if (wdcprobe(&cp->wdc_channel)) 1506 failreason = "other hardware responding at addresses"; 1507 pci_conf_write(sc->sc_pc, sc->sc_tag, 1508 PCI_COMMAND_STATUS_REG, csr); 1509 next: 1510 if (failreason) { 1511 printf("%s: %s channel ignored (%s)\n", 1512 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1513 failreason); 1514 cp->hw_ok = 0; 1515 bus_space_unmap(cp->wdc_channel.cmd_iot, 1516 cp->wdc_channel.cmd_ioh, cmdsize); 1517 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1518 bus_space_unmap(cp->wdc_channel.ctl_iot, 1519 cp->ctl_baseioh, ctlsize); 1520 else 1521 bus_space_unmap(cp->wdc_channel.ctl_iot, 1522 cp->wdc_channel.ctl_ioh, ctlsize); 1523 } else { 1524 pciide_map_compat_intr(pa, cp, channel, interface); 1525 } 1526 if (cp->hw_ok) { 1527 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1528 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1529 wdcattach(&cp->wdc_channel); 1530 } 1531 } 1532 1533 if (sc->sc_dma_ok == 0) 1534 return; 1535 1536 /* Allocate DMA maps */ 1537 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1538 idedma_ctl = 0; 1539 cp = &sc->pciide_channels[channel]; 1540 for (drive = 0; drive < 2; drive++) { 1541 drvp = &cp->wdc_channel.ch_drive[drive]; 1542 /* If no drive, skip */ 1543 if ((drvp->drive_flags & DRIVE) == 0) 1544 continue; 1545 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1546 continue; 1547 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1548 /* Abort DMA setup */ 1549 printf("%s:%d:%d: can't allocate DMA maps, " 1550 "using PIO transfers\n", 1551 sc->sc_wdcdev.sc_dev.dv_xname, 1552 channel, drive); 1553 drvp->drive_flags &= ~DRIVE_DMA; 1554 } 1555 printf("%s:%d:%d: using DMA data transfers\n", 1556 sc->sc_wdcdev.sc_dev.dv_xname, 1557 channel, drive); 1558 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1559 } 1560 if (idedma_ctl != 0) { 1561 /* Add software bits in status register */ 1562 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1563 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1564 idedma_ctl); 1565 } 1566 } 1567 } 1568 1569 void 1570 sata_setup_channel(chp) 1571 struct channel_softc *chp; 1572 { 1573 struct ata_drive_datas *drvp; 1574 int drive; 1575 u_int32_t idedma_ctl; 1576 struct pciide_channel *cp = (struct pciide_channel*)chp; 1577 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 1578 1579 /* setup DMA if needed */ 1580 pciide_channel_dma_setup(cp); 1581 1582 idedma_ctl = 0; 1583 1584 for (drive = 0; drive < 2; drive++) { 1585 drvp = &chp->ch_drive[drive]; 1586 /* If no drive, skip */ 1587 if ((drvp->drive_flags & DRIVE) == 0) 1588 continue; 1589 if (drvp->drive_flags & DRIVE_UDMA) { 1590 /* use Ultra/DMA */ 1591 drvp->drive_flags &= ~DRIVE_DMA; 1592 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1593 } else if (drvp->drive_flags & DRIVE_DMA) { 1594 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1595 } 1596 } 1597 1598 /* 1599 * Nothing to do to setup modes; it is meaningless in S-ATA 1600 * (but many S-ATA drives still want to get the SET_FEATURE 1601 * command). 1602 */ 1603 if (idedma_ctl != 0) { 1604 /* Add software bits in status register */ 1605 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1606 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1607 idedma_ctl); 1608 } 1609 pciide_print_modes(cp); 1610 } 1611 1612 void 1613 piix_chip_map(sc, pa) 1614 struct pciide_softc *sc; 1615 struct pci_attach_args *pa; 1616 { 1617 struct pciide_channel *cp; 1618 int channel; 1619 u_int32_t idetim; 1620 bus_size_t cmdsize, ctlsize; 1621 1622 if (pciide_chipen(sc, pa) == 0) 1623 return; 1624 1625 printf("%s: bus-master DMA support present", 1626 sc->sc_wdcdev.sc_dev.dv_xname); 1627 pciide_mapreg_dma(sc, pa); 1628 printf("\n"); 1629 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1630 WDC_CAPABILITY_MODE; 1631 if (sc->sc_dma_ok) { 1632 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1633 sc->sc_wdcdev.irqack = pciide_irqack; 1634 switch(sc->sc_pp->ide_product) { 1635 case PCI_PRODUCT_INTEL_82371AB_IDE: 1636 case PCI_PRODUCT_INTEL_82440MX_IDE: 1637 case PCI_PRODUCT_INTEL_82801AA_IDE: 1638 case PCI_PRODUCT_INTEL_82801AB_IDE: 1639 case PCI_PRODUCT_INTEL_82801BA_IDE: 1640 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1641 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1642 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1643 case PCI_PRODUCT_INTEL_82801DB_IDE: 1644 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1645 } 1646 } 1647 sc->sc_wdcdev.PIO_cap = 4; 1648 sc->sc_wdcdev.DMA_cap = 2; 1649 switch(sc->sc_pp->ide_product) { 1650 case PCI_PRODUCT_INTEL_82801AA_IDE: 1651 sc->sc_wdcdev.UDMA_cap = 4; 1652 break; 1653 case PCI_PRODUCT_INTEL_82801BA_IDE: 1654 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1655 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1656 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1657 case PCI_PRODUCT_INTEL_82801DB_IDE: 1658 sc->sc_wdcdev.UDMA_cap = 5; 1659 break; 1660 default: 1661 sc->sc_wdcdev.UDMA_cap = 2; 1662 } 1663 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1664 sc->sc_wdcdev.set_modes = piix_setup_channel; 1665 else 1666 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1667 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1668 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1669 1670 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1671 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1672 DEBUG_PROBE); 1673 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1674 WDCDEBUG_PRINT((", sidetim=0x%x", 1675 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1676 DEBUG_PROBE); 1677 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1678 WDCDEBUG_PRINT((", udamreg 0x%x", 1679 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1680 DEBUG_PROBE); 1681 } 1682 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1683 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1684 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1685 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1686 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1687 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1688 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1689 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1690 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1691 DEBUG_PROBE); 1692 } 1693 1694 } 1695 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1696 1697 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1698 cp = &sc->pciide_channels[channel]; 1699 /* PIIX is compat-only */ 1700 if (pciide_chansetup(sc, channel, 0) == 0) 1701 continue; 1702 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1703 if ((PIIX_IDETIM_READ(idetim, channel) & 1704 PIIX_IDETIM_IDE) == 0) { 1705 printf("%s: %s channel ignored (disabled)\n", 1706 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1707 continue; 1708 } 1709 /* PIIX are compat-only pciide devices */ 1710 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1711 if (cp->hw_ok == 0) 1712 continue; 1713 if (pciide_chan_candisable(cp)) { 1714 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1715 channel); 1716 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1717 idetim); 1718 } 1719 pciide_map_compat_intr(pa, cp, channel, 0); 1720 if (cp->hw_ok == 0) 1721 continue; 1722 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1723 } 1724 1725 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1726 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1727 DEBUG_PROBE); 1728 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1729 WDCDEBUG_PRINT((", sidetim=0x%x", 1730 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1731 DEBUG_PROBE); 1732 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1733 WDCDEBUG_PRINT((", udamreg 0x%x", 1734 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1735 DEBUG_PROBE); 1736 } 1737 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1738 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1739 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1740 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1741 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1742 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1743 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1744 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1745 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1746 DEBUG_PROBE); 1747 } 1748 } 1749 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1750 } 1751 1752 void 1753 piix_setup_channel(chp) 1754 struct channel_softc *chp; 1755 { 1756 u_int8_t mode[2], drive; 1757 u_int32_t oidetim, idetim, idedma_ctl; 1758 struct pciide_channel *cp = (struct pciide_channel*)chp; 1759 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1760 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1761 1762 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1763 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1764 idedma_ctl = 0; 1765 1766 /* set up new idetim: Enable IDE registers decode */ 1767 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1768 chp->channel); 1769 1770 /* setup DMA */ 1771 pciide_channel_dma_setup(cp); 1772 1773 /* 1774 * Here we have to mess up with drives mode: PIIX can't have 1775 * different timings for master and slave drives. 1776 * We need to find the best combination. 1777 */ 1778 1779 /* If both drives supports DMA, take the lower mode */ 1780 if ((drvp[0].drive_flags & DRIVE_DMA) && 1781 (drvp[1].drive_flags & DRIVE_DMA)) { 1782 mode[0] = mode[1] = 1783 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1784 drvp[0].DMA_mode = mode[0]; 1785 drvp[1].DMA_mode = mode[1]; 1786 goto ok; 1787 } 1788 /* 1789 * If only one drive supports DMA, use its mode, and 1790 * put the other one in PIO mode 0 if mode not compatible 1791 */ 1792 if (drvp[0].drive_flags & DRIVE_DMA) { 1793 mode[0] = drvp[0].DMA_mode; 1794 mode[1] = drvp[1].PIO_mode; 1795 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1796 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1797 mode[1] = drvp[1].PIO_mode = 0; 1798 goto ok; 1799 } 1800 if (drvp[1].drive_flags & DRIVE_DMA) { 1801 mode[1] = drvp[1].DMA_mode; 1802 mode[0] = drvp[0].PIO_mode; 1803 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1804 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1805 mode[0] = drvp[0].PIO_mode = 0; 1806 goto ok; 1807 } 1808 /* 1809 * If both drives are not DMA, takes the lower mode, unless 1810 * one of them is PIO mode < 2 1811 */ 1812 if (drvp[0].PIO_mode < 2) { 1813 mode[0] = drvp[0].PIO_mode = 0; 1814 mode[1] = drvp[1].PIO_mode; 1815 } else if (drvp[1].PIO_mode < 2) { 1816 mode[1] = drvp[1].PIO_mode = 0; 1817 mode[0] = drvp[0].PIO_mode; 1818 } else { 1819 mode[0] = mode[1] = 1820 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1821 drvp[0].PIO_mode = mode[0]; 1822 drvp[1].PIO_mode = mode[1]; 1823 } 1824 ok: /* The modes are setup */ 1825 for (drive = 0; drive < 2; drive++) { 1826 if (drvp[drive].drive_flags & DRIVE_DMA) { 1827 idetim |= piix_setup_idetim_timings( 1828 mode[drive], 1, chp->channel); 1829 goto end; 1830 } 1831 } 1832 /* If we are there, none of the drives are DMA */ 1833 if (mode[0] >= 2) 1834 idetim |= piix_setup_idetim_timings( 1835 mode[0], 0, chp->channel); 1836 else 1837 idetim |= piix_setup_idetim_timings( 1838 mode[1], 0, chp->channel); 1839 end: /* 1840 * timing mode is now set up in the controller. Enable 1841 * it per-drive 1842 */ 1843 for (drive = 0; drive < 2; drive++) { 1844 /* If no drive, skip */ 1845 if ((drvp[drive].drive_flags & DRIVE) == 0) 1846 continue; 1847 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1848 if (drvp[drive].drive_flags & DRIVE_DMA) 1849 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1850 } 1851 if (idedma_ctl != 0) { 1852 /* Add software bits in status register */ 1853 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1854 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1855 idedma_ctl); 1856 } 1857 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1858 pciide_print_modes(cp); 1859 } 1860 1861 void 1862 piix3_4_setup_channel(chp) 1863 struct channel_softc *chp; 1864 { 1865 struct ata_drive_datas *drvp; 1866 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1867 struct pciide_channel *cp = (struct pciide_channel*)chp; 1868 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1869 int drive; 1870 int channel = chp->channel; 1871 1872 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1873 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1874 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1875 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1876 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1877 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1878 PIIX_SIDETIM_RTC_MASK(channel)); 1879 1880 idedma_ctl = 0; 1881 /* If channel disabled, no need to go further */ 1882 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1883 return; 1884 /* set up new idetim: Enable IDE registers decode */ 1885 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1886 1887 /* setup DMA if needed */ 1888 pciide_channel_dma_setup(cp); 1889 1890 for (drive = 0; drive < 2; drive++) { 1891 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1892 PIIX_UDMATIM_SET(0x3, channel, drive)); 1893 drvp = &chp->ch_drive[drive]; 1894 /* If no drive, skip */ 1895 if ((drvp->drive_flags & DRIVE) == 0) 1896 continue; 1897 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1898 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1899 goto pio; 1900 1901 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1902 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1903 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1904 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1905 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1906 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1907 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1908 ideconf |= PIIX_CONFIG_PINGPONG; 1909 } 1910 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1911 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1912 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1913 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1914 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1915 /* setup Ultra/100 */ 1916 if (drvp->UDMA_mode > 2 && 1917 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1918 drvp->UDMA_mode = 2; 1919 if (drvp->UDMA_mode > 4) { 1920 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1921 } else { 1922 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1923 if (drvp->UDMA_mode > 2) { 1924 ideconf |= PIIX_CONFIG_UDMA66(channel, 1925 drive); 1926 } else { 1927 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1928 drive); 1929 } 1930 } 1931 } 1932 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1933 /* setup Ultra/66 */ 1934 if (drvp->UDMA_mode > 2 && 1935 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1936 drvp->UDMA_mode = 2; 1937 if (drvp->UDMA_mode > 2) 1938 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1939 else 1940 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1941 } 1942 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1943 (drvp->drive_flags & DRIVE_UDMA)) { 1944 /* use Ultra/DMA */ 1945 drvp->drive_flags &= ~DRIVE_DMA; 1946 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1947 udmareg |= PIIX_UDMATIM_SET( 1948 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1949 } else { 1950 /* use Multiword DMA */ 1951 drvp->drive_flags &= ~DRIVE_UDMA; 1952 if (drive == 0) { 1953 idetim |= piix_setup_idetim_timings( 1954 drvp->DMA_mode, 1, channel); 1955 } else { 1956 sidetim |= piix_setup_sidetim_timings( 1957 drvp->DMA_mode, 1, channel); 1958 idetim =PIIX_IDETIM_SET(idetim, 1959 PIIX_IDETIM_SITRE, channel); 1960 } 1961 } 1962 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1963 1964 pio: /* use PIO mode */ 1965 idetim |= piix_setup_idetim_drvs(drvp); 1966 if (drive == 0) { 1967 idetim |= piix_setup_idetim_timings( 1968 drvp->PIO_mode, 0, channel); 1969 } else { 1970 sidetim |= piix_setup_sidetim_timings( 1971 drvp->PIO_mode, 0, channel); 1972 idetim =PIIX_IDETIM_SET(idetim, 1973 PIIX_IDETIM_SITRE, channel); 1974 } 1975 } 1976 if (idedma_ctl != 0) { 1977 /* Add software bits in status register */ 1978 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1979 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1980 idedma_ctl); 1981 } 1982 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1983 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1984 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1985 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1986 pciide_print_modes(cp); 1987 } 1988 1989 1990 /* setup ISP and RTC fields, based on mode */ 1991 static u_int32_t 1992 piix_setup_idetim_timings(mode, dma, channel) 1993 u_int8_t mode; 1994 u_int8_t dma; 1995 u_int8_t channel; 1996 { 1997 1998 if (dma) 1999 return PIIX_IDETIM_SET(0, 2000 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 2001 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 2002 channel); 2003 else 2004 return PIIX_IDETIM_SET(0, 2005 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 2006 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 2007 channel); 2008 } 2009 2010 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 2011 static u_int32_t 2012 piix_setup_idetim_drvs(drvp) 2013 struct ata_drive_datas *drvp; 2014 { 2015 u_int32_t ret = 0; 2016 struct channel_softc *chp = drvp->chnl_softc; 2017 u_int8_t channel = chp->channel; 2018 u_int8_t drive = drvp->drive; 2019 2020 /* 2021 * If drive is using UDMA, timings setups are independant 2022 * So just check DMA and PIO here. 2023 */ 2024 if (drvp->drive_flags & DRIVE_DMA) { 2025 /* if mode = DMA mode 0, use compatible timings */ 2026 if ((drvp->drive_flags & DRIVE_DMA) && 2027 drvp->DMA_mode == 0) { 2028 drvp->PIO_mode = 0; 2029 return ret; 2030 } 2031 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2032 /* 2033 * PIO and DMA timings are the same, use fast timings for PIO 2034 * too, else use compat timings. 2035 */ 2036 if ((piix_isp_pio[drvp->PIO_mode] != 2037 piix_isp_dma[drvp->DMA_mode]) || 2038 (piix_rtc_pio[drvp->PIO_mode] != 2039 piix_rtc_dma[drvp->DMA_mode])) 2040 drvp->PIO_mode = 0; 2041 /* if PIO mode <= 2, use compat timings for PIO */ 2042 if (drvp->PIO_mode <= 2) { 2043 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 2044 channel); 2045 return ret; 2046 } 2047 } 2048 2049 /* 2050 * Now setup PIO modes. If mode < 2, use compat timings. 2051 * Else enable fast timings. Enable IORDY and prefetch/post 2052 * if PIO mode >= 3. 2053 */ 2054 2055 if (drvp->PIO_mode < 2) 2056 return ret; 2057 2058 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2059 if (drvp->PIO_mode >= 3) { 2060 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 2061 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 2062 } 2063 return ret; 2064 } 2065 2066 /* setup values in SIDETIM registers, based on mode */ 2067 static u_int32_t 2068 piix_setup_sidetim_timings(mode, dma, channel) 2069 u_int8_t mode; 2070 u_int8_t dma; 2071 u_int8_t channel; 2072 { 2073 if (dma) 2074 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 2075 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 2076 else 2077 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 2078 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 2079 } 2080 2081 void 2082 amd7x6_chip_map(sc, pa) 2083 struct pciide_softc *sc; 2084 struct pci_attach_args *pa; 2085 { 2086 struct pciide_channel *cp; 2087 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2088 int channel; 2089 pcireg_t chanenable; 2090 bus_size_t cmdsize, ctlsize; 2091 2092 if (pciide_chipen(sc, pa) == 0) 2093 return; 2094 printf("%s: bus-master DMA support present", 2095 sc->sc_wdcdev.sc_dev.dv_xname); 2096 pciide_mapreg_dma(sc, pa); 2097 printf("\n"); 2098 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2099 WDC_CAPABILITY_MODE; 2100 if (sc->sc_dma_ok) { 2101 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2102 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2103 sc->sc_wdcdev.irqack = pciide_irqack; 2104 } 2105 sc->sc_wdcdev.PIO_cap = 4; 2106 sc->sc_wdcdev.DMA_cap = 2; 2107 2108 switch (sc->sc_pci_vendor) { 2109 case PCI_VENDOR_AMD: 2110 switch (sc->sc_pp->ide_product) { 2111 case PCI_PRODUCT_AMD_PBC766_IDE: 2112 case PCI_PRODUCT_AMD_PBC768_IDE: 2113 case PCI_PRODUCT_AMD_PBC8111_IDE: 2114 sc->sc_wdcdev.UDMA_cap = 5; 2115 break; 2116 default: 2117 sc->sc_wdcdev.UDMA_cap = 4; 2118 } 2119 sc->sc_amd_regbase = AMD7X6_AMD_REGBASE; 2120 break; 2121 2122 case PCI_VENDOR_NVIDIA: 2123 switch (sc->sc_pp->ide_product) { 2124 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 2125 sc->sc_wdcdev.UDMA_cap = 5; 2126 break; 2127 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 2128 sc->sc_wdcdev.UDMA_cap = 6; 2129 break; 2130 } 2131 sc->sc_amd_regbase = AMD7X6_NVIDIA_REGBASE; 2132 break; 2133 2134 default: 2135 panic("amd7x6_chip_map: unknown vendor"); 2136 } 2137 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 2138 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2139 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2140 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, 2141 AMD7X6_CHANSTATUS_EN(sc)); 2142 2143 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 2144 DEBUG_PROBE); 2145 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2146 cp = &sc->pciide_channels[channel]; 2147 if (pciide_chansetup(sc, channel, interface) == 0) 2148 continue; 2149 2150 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 2151 printf("%s: %s channel ignored (disabled)\n", 2152 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2153 continue; 2154 } 2155 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2156 pciide_pci_intr); 2157 2158 if (pciide_chan_candisable(cp)) 2159 chanenable &= ~AMD7X6_CHAN_EN(channel); 2160 pciide_map_compat_intr(pa, cp, channel, interface); 2161 if (cp->hw_ok == 0) 2162 continue; 2163 2164 amd7x6_setup_channel(&cp->wdc_channel); 2165 } 2166 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN(sc), 2167 chanenable); 2168 return; 2169 } 2170 2171 void 2172 amd7x6_setup_channel(chp) 2173 struct channel_softc *chp; 2174 { 2175 u_int32_t udmatim_reg, datatim_reg; 2176 u_int8_t idedma_ctl; 2177 int mode, drive; 2178 struct ata_drive_datas *drvp; 2179 struct pciide_channel *cp = (struct pciide_channel*)chp; 2180 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2181 #ifndef PCIIDE_AMD756_ENABLEDMA 2182 int rev = PCI_REVISION( 2183 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2184 #endif 2185 2186 idedma_ctl = 0; 2187 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc)); 2188 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc)); 2189 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2190 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2191 2192 /* setup DMA if needed */ 2193 pciide_channel_dma_setup(cp); 2194 2195 for (drive = 0; drive < 2; drive++) { 2196 drvp = &chp->ch_drive[drive]; 2197 /* If no drive, skip */ 2198 if ((drvp->drive_flags & DRIVE) == 0) 2199 continue; 2200 /* add timing values, setup DMA if needed */ 2201 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2202 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2203 mode = drvp->PIO_mode; 2204 goto pio; 2205 } 2206 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2207 (drvp->drive_flags & DRIVE_UDMA)) { 2208 /* use Ultra/DMA */ 2209 drvp->drive_flags &= ~DRIVE_DMA; 2210 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2211 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2212 AMD7X6_UDMA_TIME(chp->channel, drive, 2213 amd7x6_udma_tim[drvp->UDMA_mode]); 2214 /* can use PIO timings, MW DMA unused */ 2215 mode = drvp->PIO_mode; 2216 } else { 2217 /* use Multiword DMA, but only if revision is OK */ 2218 drvp->drive_flags &= ~DRIVE_UDMA; 2219 #ifndef PCIIDE_AMD756_ENABLEDMA 2220 /* 2221 * The workaround doesn't seem to be necessary 2222 * with all drives, so it can be disabled by 2223 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2224 * triggered. 2225 */ 2226 if (sc->sc_pci_vendor == PCI_VENDOR_AMD && 2227 sc->sc_pp->ide_product == 2228 PCI_PRODUCT_AMD_PBC756_IDE && 2229 AMD756_CHIPREV_DISABLEDMA(rev)) { 2230 printf("%s:%d:%d: multi-word DMA disabled due " 2231 "to chip revision\n", 2232 sc->sc_wdcdev.sc_dev.dv_xname, 2233 chp->channel, drive); 2234 mode = drvp->PIO_mode; 2235 drvp->drive_flags &= ~DRIVE_DMA; 2236 goto pio; 2237 } 2238 #endif 2239 /* mode = min(pio, dma+2) */ 2240 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2241 mode = drvp->PIO_mode; 2242 else 2243 mode = drvp->DMA_mode + 2; 2244 } 2245 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2246 2247 pio: /* setup PIO mode */ 2248 if (mode <= 2) { 2249 drvp->DMA_mode = 0; 2250 drvp->PIO_mode = 0; 2251 mode = 0; 2252 } else { 2253 drvp->PIO_mode = mode; 2254 drvp->DMA_mode = mode - 2; 2255 } 2256 datatim_reg |= 2257 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2258 amd7x6_pio_set[mode]) | 2259 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2260 amd7x6_pio_rec[mode]); 2261 } 2262 if (idedma_ctl != 0) { 2263 /* Add software bits in status register */ 2264 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2265 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2266 idedma_ctl); 2267 } 2268 pciide_print_modes(cp); 2269 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc), datatim_reg); 2270 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc), udmatim_reg); 2271 } 2272 2273 void 2274 apollo_chip_map(sc, pa) 2275 struct pciide_softc *sc; 2276 struct pci_attach_args *pa; 2277 { 2278 struct pciide_channel *cp; 2279 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2280 int channel; 2281 u_int32_t ideconf; 2282 bus_size_t cmdsize, ctlsize; 2283 pcitag_t pcib_tag; 2284 pcireg_t pcib_id, pcib_class; 2285 2286 if (pciide_chipen(sc, pa) == 0) 2287 return; 2288 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2289 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2290 /* and read ID and rev of the ISA bridge */ 2291 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2292 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2293 printf(": VIA Technologies "); 2294 switch (PCI_PRODUCT(pcib_id)) { 2295 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2296 printf("VT82C586 (Apollo VP) "); 2297 if(PCI_REVISION(pcib_class) >= 0x02) { 2298 printf("ATA33 controller\n"); 2299 sc->sc_wdcdev.UDMA_cap = 2; 2300 } else { 2301 printf("controller\n"); 2302 sc->sc_wdcdev.UDMA_cap = 0; 2303 } 2304 break; 2305 case PCI_PRODUCT_VIATECH_VT82C596A: 2306 printf("VT82C596A (Apollo Pro) "); 2307 if (PCI_REVISION(pcib_class) >= 0x12) { 2308 printf("ATA66 controller\n"); 2309 sc->sc_wdcdev.UDMA_cap = 4; 2310 } else { 2311 printf("ATA33 controller\n"); 2312 sc->sc_wdcdev.UDMA_cap = 2; 2313 } 2314 break; 2315 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2316 printf("VT82C686A (Apollo KX133) "); 2317 if (PCI_REVISION(pcib_class) >= 0x40) { 2318 printf("ATA100 controller\n"); 2319 sc->sc_wdcdev.UDMA_cap = 5; 2320 } else { 2321 printf("ATA66 controller\n"); 2322 sc->sc_wdcdev.UDMA_cap = 4; 2323 } 2324 break; 2325 case PCI_PRODUCT_VIATECH_VT8231: 2326 printf("VT8231 ATA100 controller\n"); 2327 sc->sc_wdcdev.UDMA_cap = 5; 2328 break; 2329 case PCI_PRODUCT_VIATECH_VT8233: 2330 printf("VT8233 ATA100 controller\n"); 2331 sc->sc_wdcdev.UDMA_cap = 5; 2332 break; 2333 case PCI_PRODUCT_VIATECH_VT8233A: 2334 printf("VT8233A ATA133 controller\n"); 2335 sc->sc_wdcdev.UDMA_cap = 6; 2336 break; 2337 case PCI_PRODUCT_VIATECH_VT8235: 2338 printf("VT8235 ATA133 controller\n"); 2339 sc->sc_wdcdev.UDMA_cap = 6; 2340 break; 2341 default: 2342 printf("unknown ATA controller\n"); 2343 sc->sc_wdcdev.UDMA_cap = 0; 2344 } 2345 2346 printf("%s: bus-master DMA support present", 2347 sc->sc_wdcdev.sc_dev.dv_xname); 2348 pciide_mapreg_dma(sc, pa); 2349 printf("\n"); 2350 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2351 WDC_CAPABILITY_MODE; 2352 if (sc->sc_dma_ok) { 2353 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2354 sc->sc_wdcdev.irqack = pciide_irqack; 2355 if (sc->sc_wdcdev.UDMA_cap > 0) 2356 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2357 } 2358 sc->sc_wdcdev.PIO_cap = 4; 2359 sc->sc_wdcdev.DMA_cap = 2; 2360 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2361 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2362 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2363 2364 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2365 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2366 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2367 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2368 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2369 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2370 DEBUG_PROBE); 2371 2372 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2373 cp = &sc->pciide_channels[channel]; 2374 if (pciide_chansetup(sc, channel, interface) == 0) 2375 continue; 2376 2377 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2378 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2379 printf("%s: %s channel ignored (disabled)\n", 2380 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2381 continue; 2382 } 2383 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2384 pciide_pci_intr); 2385 if (cp->hw_ok == 0) 2386 continue; 2387 if (pciide_chan_candisable(cp)) { 2388 ideconf &= ~APO_IDECONF_EN(channel); 2389 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2390 ideconf); 2391 } 2392 pciide_map_compat_intr(pa, cp, channel, interface); 2393 2394 if (cp->hw_ok == 0) 2395 continue; 2396 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2397 } 2398 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2399 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2400 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2401 } 2402 2403 void 2404 apollo_setup_channel(chp) 2405 struct channel_softc *chp; 2406 { 2407 u_int32_t udmatim_reg, datatim_reg; 2408 u_int8_t idedma_ctl; 2409 int mode, drive; 2410 struct ata_drive_datas *drvp; 2411 struct pciide_channel *cp = (struct pciide_channel*)chp; 2412 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2413 2414 idedma_ctl = 0; 2415 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2416 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2417 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2418 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2419 2420 /* setup DMA if needed */ 2421 pciide_channel_dma_setup(cp); 2422 2423 for (drive = 0; drive < 2; drive++) { 2424 drvp = &chp->ch_drive[drive]; 2425 /* If no drive, skip */ 2426 if ((drvp->drive_flags & DRIVE) == 0) 2427 continue; 2428 /* add timing values, setup DMA if needed */ 2429 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2430 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2431 mode = drvp->PIO_mode; 2432 goto pio; 2433 } 2434 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2435 (drvp->drive_flags & DRIVE_UDMA)) { 2436 /* use Ultra/DMA */ 2437 drvp->drive_flags &= ~DRIVE_DMA; 2438 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2439 APO_UDMA_EN_MTH(chp->channel, drive); 2440 if (sc->sc_wdcdev.UDMA_cap == 6) { 2441 /* 8233a */ 2442 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2443 drive, apollo_udma133_tim[drvp->UDMA_mode]); 2444 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 2445 /* 686b */ 2446 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2447 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2448 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2449 /* 596b or 686a */ 2450 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2451 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2452 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2453 } else { 2454 /* 596a or 586b */ 2455 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2456 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2457 } 2458 /* can use PIO timings, MW DMA unused */ 2459 mode = drvp->PIO_mode; 2460 } else { 2461 /* use Multiword DMA */ 2462 drvp->drive_flags &= ~DRIVE_UDMA; 2463 /* mode = min(pio, dma+2) */ 2464 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2465 mode = drvp->PIO_mode; 2466 else 2467 mode = drvp->DMA_mode + 2; 2468 } 2469 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2470 2471 pio: /* setup PIO mode */ 2472 if (mode <= 2) { 2473 drvp->DMA_mode = 0; 2474 drvp->PIO_mode = 0; 2475 mode = 0; 2476 } else { 2477 drvp->PIO_mode = mode; 2478 drvp->DMA_mode = mode - 2; 2479 } 2480 datatim_reg |= 2481 APO_DATATIM_PULSE(chp->channel, drive, 2482 apollo_pio_set[mode]) | 2483 APO_DATATIM_RECOV(chp->channel, drive, 2484 apollo_pio_rec[mode]); 2485 } 2486 if (idedma_ctl != 0) { 2487 /* Add software bits in status register */ 2488 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2489 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2490 idedma_ctl); 2491 } 2492 pciide_print_modes(cp); 2493 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2494 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2495 } 2496 2497 void 2498 cmd_channel_map(pa, sc, channel) 2499 struct pci_attach_args *pa; 2500 struct pciide_softc *sc; 2501 int channel; 2502 { 2503 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2504 bus_size_t cmdsize, ctlsize; 2505 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2506 int interface, one_channel; 2507 2508 /* 2509 * The 0648/0649 can be told to identify as a RAID controller. 2510 * In this case, we have to fake interface 2511 */ 2512 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2513 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2514 PCIIDE_INTERFACE_SETTABLE(1); 2515 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2516 CMD_CONF_DSA1) 2517 interface |= PCIIDE_INTERFACE_PCI(0) | 2518 PCIIDE_INTERFACE_PCI(1); 2519 } else { 2520 interface = PCI_INTERFACE(pa->pa_class); 2521 } 2522 2523 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2524 cp->name = PCIIDE_CHANNEL_NAME(channel); 2525 cp->wdc_channel.channel = channel; 2526 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2527 2528 /* 2529 * Older CMD64X doesn't have independant channels 2530 */ 2531 switch (sc->sc_pp->ide_product) { 2532 case PCI_PRODUCT_CMDTECH_649: 2533 one_channel = 0; 2534 break; 2535 default: 2536 one_channel = 1; 2537 break; 2538 } 2539 2540 if (channel > 0 && one_channel) { 2541 cp->wdc_channel.ch_queue = 2542 sc->pciide_channels[0].wdc_channel.ch_queue; 2543 } else { 2544 cp->wdc_channel.ch_queue = 2545 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2546 } 2547 if (cp->wdc_channel.ch_queue == NULL) { 2548 printf("%s %s channel: " 2549 "can't allocate memory for command queue", 2550 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2551 return; 2552 } 2553 2554 printf("%s: %s channel %s to %s mode\n", 2555 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2556 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2557 "configured" : "wired", 2558 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2559 "native-PCI" : "compatibility"); 2560 2561 /* 2562 * with a CMD PCI64x, if we get here, the first channel is enabled: 2563 * there's no way to disable the first channel without disabling 2564 * the whole device 2565 */ 2566 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2567 printf("%s: %s channel ignored (disabled)\n", 2568 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2569 return; 2570 } 2571 2572 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2573 if (cp->hw_ok == 0) 2574 return; 2575 if (channel == 1) { 2576 if (pciide_chan_candisable(cp)) { 2577 ctrl &= ~CMD_CTRL_2PORT; 2578 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2579 CMD_CTRL, ctrl); 2580 } 2581 } 2582 pciide_map_compat_intr(pa, cp, channel, interface); 2583 } 2584 2585 int 2586 cmd_pci_intr(arg) 2587 void *arg; 2588 { 2589 struct pciide_softc *sc = arg; 2590 struct pciide_channel *cp; 2591 struct channel_softc *wdc_cp; 2592 int i, rv, crv; 2593 u_int32_t priirq, secirq; 2594 2595 rv = 0; 2596 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2597 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2598 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2599 cp = &sc->pciide_channels[i]; 2600 wdc_cp = &cp->wdc_channel; 2601 /* If a compat channel skip. */ 2602 if (cp->compat) 2603 continue; 2604 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2605 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2606 crv = wdcintr(wdc_cp); 2607 if (crv == 0) 2608 printf("%s:%d: bogus intr\n", 2609 sc->sc_wdcdev.sc_dev.dv_xname, i); 2610 else 2611 rv = 1; 2612 } 2613 } 2614 return rv; 2615 } 2616 2617 void 2618 cmd_chip_map(sc, pa) 2619 struct pciide_softc *sc; 2620 struct pci_attach_args *pa; 2621 { 2622 int channel; 2623 2624 /* 2625 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2626 * and base adresses registers can be disabled at 2627 * hardware level. In this case, the device is wired 2628 * in compat mode and its first channel is always enabled, 2629 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2630 * In fact, it seems that the first channel of the CMD PCI0640 2631 * can't be disabled. 2632 */ 2633 2634 #ifdef PCIIDE_CMD064x_DISABLE 2635 if (pciide_chipen(sc, pa) == 0) 2636 return; 2637 #endif 2638 2639 printf("%s: hardware does not support DMA\n", 2640 sc->sc_wdcdev.sc_dev.dv_xname); 2641 sc->sc_dma_ok = 0; 2642 2643 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2644 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2645 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2646 2647 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2648 cmd_channel_map(pa, sc, channel); 2649 } 2650 } 2651 2652 void 2653 cmd0643_9_chip_map(sc, pa) 2654 struct pciide_softc *sc; 2655 struct pci_attach_args *pa; 2656 { 2657 struct pciide_channel *cp; 2658 int channel; 2659 pcireg_t rev = PCI_REVISION(pa->pa_class); 2660 2661 /* 2662 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2663 * and base adresses registers can be disabled at 2664 * hardware level. In this case, the device is wired 2665 * in compat mode and its first channel is always enabled, 2666 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2667 * In fact, it seems that the first channel of the CMD PCI0640 2668 * can't be disabled. 2669 */ 2670 2671 #ifdef PCIIDE_CMD064x_DISABLE 2672 if (pciide_chipen(sc, pa) == 0) 2673 return; 2674 #endif 2675 printf("%s: bus-master DMA support present", 2676 sc->sc_wdcdev.sc_dev.dv_xname); 2677 pciide_mapreg_dma(sc, pa); 2678 printf("\n"); 2679 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2680 WDC_CAPABILITY_MODE; 2681 if (sc->sc_dma_ok) { 2682 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2683 switch (sc->sc_pp->ide_product) { 2684 case PCI_PRODUCT_CMDTECH_649: 2685 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2686 sc->sc_wdcdev.UDMA_cap = 5; 2687 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2688 break; 2689 case PCI_PRODUCT_CMDTECH_648: 2690 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2691 sc->sc_wdcdev.UDMA_cap = 4; 2692 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2693 break; 2694 case PCI_PRODUCT_CMDTECH_646: 2695 if (rev >= CMD0646U2_REV) { 2696 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2697 sc->sc_wdcdev.UDMA_cap = 2; 2698 } else if (rev >= CMD0646U_REV) { 2699 /* 2700 * Linux's driver claims that the 646U is broken 2701 * with UDMA. Only enable it if we know what we're 2702 * doing 2703 */ 2704 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2705 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2706 sc->sc_wdcdev.UDMA_cap = 2; 2707 #endif 2708 /* explicitly disable UDMA */ 2709 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2710 CMD_UDMATIM(0), 0); 2711 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2712 CMD_UDMATIM(1), 0); 2713 } 2714 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2715 break; 2716 default: 2717 sc->sc_wdcdev.irqack = pciide_irqack; 2718 } 2719 } 2720 2721 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2722 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2723 sc->sc_wdcdev.PIO_cap = 4; 2724 sc->sc_wdcdev.DMA_cap = 2; 2725 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2726 2727 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2728 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2729 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2730 DEBUG_PROBE); 2731 2732 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2733 cp = &sc->pciide_channels[channel]; 2734 cmd_channel_map(pa, sc, channel); 2735 if (cp->hw_ok == 0) 2736 continue; 2737 cmd0643_9_setup_channel(&cp->wdc_channel); 2738 } 2739 /* 2740 * note - this also makes sure we clear the irq disable and reset 2741 * bits 2742 */ 2743 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2744 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2745 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2746 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2747 DEBUG_PROBE); 2748 } 2749 2750 void 2751 cmd0643_9_setup_channel(chp) 2752 struct channel_softc *chp; 2753 { 2754 struct ata_drive_datas *drvp; 2755 u_int8_t tim; 2756 u_int32_t idedma_ctl, udma_reg; 2757 int drive; 2758 struct pciide_channel *cp = (struct pciide_channel*)chp; 2759 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2760 2761 idedma_ctl = 0; 2762 /* setup DMA if needed */ 2763 pciide_channel_dma_setup(cp); 2764 2765 for (drive = 0; drive < 2; drive++) { 2766 drvp = &chp->ch_drive[drive]; 2767 /* If no drive, skip */ 2768 if ((drvp->drive_flags & DRIVE) == 0) 2769 continue; 2770 /* add timing values, setup DMA if needed */ 2771 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2772 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2773 if (drvp->drive_flags & DRIVE_UDMA) { 2774 /* UltraDMA on a 646U2, 0648 or 0649 */ 2775 drvp->drive_flags &= ~DRIVE_DMA; 2776 udma_reg = pciide_pci_read(sc->sc_pc, 2777 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2778 if (drvp->UDMA_mode > 2 && 2779 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2780 CMD_BICSR) & 2781 CMD_BICSR_80(chp->channel)) == 0) 2782 drvp->UDMA_mode = 2; 2783 if (drvp->UDMA_mode > 2) 2784 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2785 else if (sc->sc_wdcdev.UDMA_cap > 2) 2786 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2787 udma_reg |= CMD_UDMATIM_UDMA(drive); 2788 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2789 CMD_UDMATIM_TIM_OFF(drive)); 2790 udma_reg |= 2791 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2792 CMD_UDMATIM_TIM_OFF(drive)); 2793 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2794 CMD_UDMATIM(chp->channel), udma_reg); 2795 } else { 2796 /* 2797 * use Multiword DMA. 2798 * Timings will be used for both PIO and DMA, 2799 * so adjust DMA mode if needed 2800 * if we have a 0646U2/8/9, turn off UDMA 2801 */ 2802 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2803 udma_reg = pciide_pci_read(sc->sc_pc, 2804 sc->sc_tag, 2805 CMD_UDMATIM(chp->channel)); 2806 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2807 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2808 CMD_UDMATIM(chp->channel), 2809 udma_reg); 2810 } 2811 if (drvp->PIO_mode >= 3 && 2812 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2813 drvp->DMA_mode = drvp->PIO_mode - 2; 2814 } 2815 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2816 } 2817 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2818 } 2819 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2820 CMD_DATA_TIM(chp->channel, drive), tim); 2821 } 2822 if (idedma_ctl != 0) { 2823 /* Add software bits in status register */ 2824 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2825 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2826 idedma_ctl); 2827 } 2828 pciide_print_modes(cp); 2829 } 2830 2831 void 2832 cmd646_9_irqack(chp) 2833 struct channel_softc *chp; 2834 { 2835 u_int32_t priirq, secirq; 2836 struct pciide_channel *cp = (struct pciide_channel*)chp; 2837 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2838 2839 if (chp->channel == 0) { 2840 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2841 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2842 } else { 2843 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2844 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2845 } 2846 pciide_irqack(chp); 2847 } 2848 2849 void 2850 cmd680_chip_map(sc, pa) 2851 struct pciide_softc *sc; 2852 struct pci_attach_args *pa; 2853 { 2854 struct pciide_channel *cp; 2855 int channel; 2856 2857 if (pciide_chipen(sc, pa) == 0) 2858 return; 2859 printf("%s: bus-master DMA support present", 2860 sc->sc_wdcdev.sc_dev.dv_xname); 2861 pciide_mapreg_dma(sc, pa); 2862 printf("\n"); 2863 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2864 WDC_CAPABILITY_MODE; 2865 if (sc->sc_dma_ok) { 2866 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2867 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2868 sc->sc_wdcdev.UDMA_cap = 6; 2869 sc->sc_wdcdev.irqack = pciide_irqack; 2870 } 2871 2872 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2873 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2874 sc->sc_wdcdev.PIO_cap = 4; 2875 sc->sc_wdcdev.DMA_cap = 2; 2876 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 2877 2878 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 2879 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 2880 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 2881 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 2882 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2883 cp = &sc->pciide_channels[channel]; 2884 cmd680_channel_map(pa, sc, channel); 2885 if (cp->hw_ok == 0) 2886 continue; 2887 cmd680_setup_channel(&cp->wdc_channel); 2888 } 2889 } 2890 2891 void 2892 cmd680_channel_map(pa, sc, channel) 2893 struct pci_attach_args *pa; 2894 struct pciide_softc *sc; 2895 int channel; 2896 { 2897 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2898 bus_size_t cmdsize, ctlsize; 2899 int interface, i, reg; 2900 static const u_int8_t init_val[] = 2901 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 2902 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 2903 2904 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2905 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2906 PCIIDE_INTERFACE_SETTABLE(1); 2907 interface |= PCIIDE_INTERFACE_PCI(0) | 2908 PCIIDE_INTERFACE_PCI(1); 2909 } else { 2910 interface = PCI_INTERFACE(pa->pa_class); 2911 } 2912 2913 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2914 cp->name = PCIIDE_CHANNEL_NAME(channel); 2915 cp->wdc_channel.channel = channel; 2916 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2917 2918 cp->wdc_channel.ch_queue = 2919 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2920 if (cp->wdc_channel.ch_queue == NULL) { 2921 printf("%s %s channel: " 2922 "can't allocate memory for command queue", 2923 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2924 return; 2925 } 2926 2927 /* XXX */ 2928 reg = 0xa2 + channel * 16; 2929 for (i = 0; i < sizeof(init_val); i++) 2930 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 2931 2932 printf("%s: %s channel %s to %s mode\n", 2933 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2934 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2935 "configured" : "wired", 2936 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2937 "native-PCI" : "compatibility"); 2938 2939 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 2940 if (cp->hw_ok == 0) 2941 return; 2942 pciide_map_compat_intr(pa, cp, channel, interface); 2943 } 2944 2945 void 2946 cmd680_setup_channel(chp) 2947 struct channel_softc *chp; 2948 { 2949 struct ata_drive_datas *drvp; 2950 u_int8_t mode, off, scsc; 2951 u_int16_t val; 2952 u_int32_t idedma_ctl; 2953 int drive; 2954 struct pciide_channel *cp = (struct pciide_channel*)chp; 2955 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2956 pci_chipset_tag_t pc = sc->sc_pc; 2957 pcitag_t pa = sc->sc_tag; 2958 static const u_int8_t udma2_tbl[] = 2959 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 2960 static const u_int8_t udma_tbl[] = 2961 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 2962 static const u_int16_t dma_tbl[] = 2963 { 0x2208, 0x10c2, 0x10c1 }; 2964 static const u_int16_t pio_tbl[] = 2965 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 2966 2967 idedma_ctl = 0; 2968 pciide_channel_dma_setup(cp); 2969 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 2970 2971 for (drive = 0; drive < 2; drive++) { 2972 drvp = &chp->ch_drive[drive]; 2973 /* If no drive, skip */ 2974 if ((drvp->drive_flags & DRIVE) == 0) 2975 continue; 2976 mode &= ~(0x03 << (drive * 4)); 2977 if (drvp->drive_flags & DRIVE_UDMA) { 2978 drvp->drive_flags &= ~DRIVE_DMA; 2979 off = 0xa0 + chp->channel * 16; 2980 if (drvp->UDMA_mode > 2 && 2981 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 2982 drvp->UDMA_mode = 2; 2983 scsc = pciide_pci_read(pc, pa, 0x8a); 2984 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 2985 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 2986 scsc = pciide_pci_read(pc, pa, 0x8a); 2987 if ((scsc & 0x30) == 0) 2988 drvp->UDMA_mode = 5; 2989 } 2990 mode |= 0x03 << (drive * 4); 2991 off = 0xac + chp->channel * 16 + drive * 2; 2992 val = pciide_pci_read(pc, pa, off) & ~0x3f; 2993 if (scsc & 0x30) 2994 val |= udma2_tbl[drvp->UDMA_mode]; 2995 else 2996 val |= udma_tbl[drvp->UDMA_mode]; 2997 pciide_pci_write(pc, pa, off, val); 2998 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2999 } else if (drvp->drive_flags & DRIVE_DMA) { 3000 mode |= 0x02 << (drive * 4); 3001 off = 0xa8 + chp->channel * 16 + drive * 2; 3002 val = dma_tbl[drvp->DMA_mode]; 3003 pciide_pci_write(pc, pa, off, val & 0xff); 3004 pciide_pci_write(pc, pa, off, val >> 8); 3005 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3006 } else { 3007 mode |= 0x01 << (drive * 4); 3008 off = 0xa4 + chp->channel * 16 + drive * 2; 3009 val = pio_tbl[drvp->PIO_mode]; 3010 pciide_pci_write(pc, pa, off, val & 0xff); 3011 pciide_pci_write(pc, pa, off, val >> 8); 3012 } 3013 } 3014 3015 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 3016 if (idedma_ctl != 0) { 3017 /* Add software bits in status register */ 3018 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3019 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3020 idedma_ctl); 3021 } 3022 pciide_print_modes(cp); 3023 } 3024 3025 void 3026 cy693_chip_map(sc, pa) 3027 struct pciide_softc *sc; 3028 struct pci_attach_args *pa; 3029 { 3030 struct pciide_channel *cp; 3031 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3032 bus_size_t cmdsize, ctlsize; 3033 3034 if (pciide_chipen(sc, pa) == 0) 3035 return; 3036 /* 3037 * this chip has 2 PCI IDE functions, one for primary and one for 3038 * secondary. So we need to call pciide_mapregs_compat() with 3039 * the real channel 3040 */ 3041 if (pa->pa_function == 1) { 3042 sc->sc_cy_compatchan = 0; 3043 } else if (pa->pa_function == 2) { 3044 sc->sc_cy_compatchan = 1; 3045 } else { 3046 printf("%s: unexpected PCI function %d\n", 3047 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3048 return; 3049 } 3050 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 3051 printf("%s: bus-master DMA support present", 3052 sc->sc_wdcdev.sc_dev.dv_xname); 3053 pciide_mapreg_dma(sc, pa); 3054 } else { 3055 printf("%s: hardware does not support DMA", 3056 sc->sc_wdcdev.sc_dev.dv_xname); 3057 sc->sc_dma_ok = 0; 3058 } 3059 printf("\n"); 3060 3061 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 3062 if (sc->sc_cy_handle == NULL) { 3063 printf("%s: unable to map hyperCache control registers\n", 3064 sc->sc_wdcdev.sc_dev.dv_xname); 3065 sc->sc_dma_ok = 0; 3066 } 3067 3068 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3069 WDC_CAPABILITY_MODE; 3070 if (sc->sc_dma_ok) { 3071 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3072 sc->sc_wdcdev.irqack = pciide_irqack; 3073 } 3074 sc->sc_wdcdev.PIO_cap = 4; 3075 sc->sc_wdcdev.DMA_cap = 2; 3076 sc->sc_wdcdev.set_modes = cy693_setup_channel; 3077 3078 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3079 sc->sc_wdcdev.nchannels = 1; 3080 3081 /* Only one channel for this chip; if we are here it's enabled */ 3082 cp = &sc->pciide_channels[0]; 3083 sc->wdc_chanarray[0] = &cp->wdc_channel; 3084 cp->name = PCIIDE_CHANNEL_NAME(0); 3085 cp->wdc_channel.channel = 0; 3086 cp->wdc_channel.wdc = &sc->sc_wdcdev; 3087 cp->wdc_channel.ch_queue = 3088 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 3089 if (cp->wdc_channel.ch_queue == NULL) { 3090 printf("%s primary channel: " 3091 "can't allocate memory for command queue", 3092 sc->sc_wdcdev.sc_dev.dv_xname); 3093 return; 3094 } 3095 printf("%s: primary channel %s to ", 3096 sc->sc_wdcdev.sc_dev.dv_xname, 3097 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 3098 "configured" : "wired"); 3099 if (interface & PCIIDE_INTERFACE_PCI(0)) { 3100 printf("native-PCI"); 3101 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 3102 pciide_pci_intr); 3103 } else { 3104 printf("compatibility"); 3105 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 3106 &cmdsize, &ctlsize); 3107 } 3108 printf(" mode\n"); 3109 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3110 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3111 wdcattach(&cp->wdc_channel); 3112 if (pciide_chan_candisable(cp)) { 3113 pci_conf_write(sc->sc_pc, sc->sc_tag, 3114 PCI_COMMAND_STATUS_REG, 0); 3115 } 3116 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 3117 if (cp->hw_ok == 0) 3118 return; 3119 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 3120 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 3121 cy693_setup_channel(&cp->wdc_channel); 3122 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 3123 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 3124 } 3125 3126 void 3127 cy693_setup_channel(chp) 3128 struct channel_softc *chp; 3129 { 3130 struct ata_drive_datas *drvp; 3131 int drive; 3132 u_int32_t cy_cmd_ctrl; 3133 u_int32_t idedma_ctl; 3134 struct pciide_channel *cp = (struct pciide_channel*)chp; 3135 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3136 int dma_mode = -1; 3137 3138 cy_cmd_ctrl = idedma_ctl = 0; 3139 3140 /* setup DMA if needed */ 3141 pciide_channel_dma_setup(cp); 3142 3143 for (drive = 0; drive < 2; drive++) { 3144 drvp = &chp->ch_drive[drive]; 3145 /* If no drive, skip */ 3146 if ((drvp->drive_flags & DRIVE) == 0) 3147 continue; 3148 /* add timing values, setup DMA if needed */ 3149 if (drvp->drive_flags & DRIVE_DMA) { 3150 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3151 /* use Multiword DMA */ 3152 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 3153 dma_mode = drvp->DMA_mode; 3154 } 3155 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3156 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 3157 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3158 CY_CMD_CTRL_IOW_REC_OFF(drive)); 3159 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3160 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 3161 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3162 CY_CMD_CTRL_IOR_REC_OFF(drive)); 3163 } 3164 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 3165 chp->ch_drive[0].DMA_mode = dma_mode; 3166 chp->ch_drive[1].DMA_mode = dma_mode; 3167 3168 if (dma_mode == -1) 3169 dma_mode = 0; 3170 3171 if (sc->sc_cy_handle != NULL) { 3172 /* Note: `multiple' is implied. */ 3173 cy82c693_write(sc->sc_cy_handle, 3174 (sc->sc_cy_compatchan == 0) ? 3175 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 3176 } 3177 3178 pciide_print_modes(cp); 3179 3180 if (idedma_ctl != 0) { 3181 /* Add software bits in status register */ 3182 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3183 IDEDMA_CTL, idedma_ctl); 3184 } 3185 } 3186 3187 static struct sis_hostbr_type { 3188 u_int16_t id; 3189 u_int8_t rev; 3190 u_int8_t udma_mode; 3191 char *name; 3192 u_int8_t type; 3193 #define SIS_TYPE_NOUDMA 0 3194 #define SIS_TYPE_66 1 3195 #define SIS_TYPE_100OLD 2 3196 #define SIS_TYPE_100NEW 3 3197 #define SIS_TYPE_133OLD 4 3198 #define SIS_TYPE_133NEW 5 3199 #define SIS_TYPE_SOUTH 6 3200 } sis_hostbr_type[] = { 3201 /* Most infos here are from sos (at) freebsd.org */ 3202 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 3203 #if 0 3204 /* 3205 * controllers associated to a rev 0x2 530 Host to PCI Bridge 3206 * have problems with UDMA (info provided by Christos) 3207 */ 3208 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 3209 #endif 3210 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 3211 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 3212 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 3213 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 3214 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 3215 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 3216 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 3217 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 3218 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 3219 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 3220 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 3221 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 3222 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 3223 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 3224 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 3225 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 3226 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 3227 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 3228 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 3229 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 3230 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 3231 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 3232 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 3233 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 3234 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 3235 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 3236 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 3237 /* 3238 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 3239 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 3240 */ 3241 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 3242 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 3243 }; 3244 3245 static struct sis_hostbr_type *sis_hostbr_type_match; 3246 3247 static int 3248 sis_hostbr_match(pa) 3249 struct pci_attach_args *pa; 3250 { 3251 int i; 3252 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 3253 return 0; 3254 sis_hostbr_type_match = NULL; 3255 for (i = 0; 3256 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 3257 i++) { 3258 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 3259 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 3260 sis_hostbr_type_match = &sis_hostbr_type[i]; 3261 } 3262 return (sis_hostbr_type_match != NULL); 3263 } 3264 3265 static int sis_south_match(pa) 3266 struct pci_attach_args *pa; 3267 { 3268 return(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 3269 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 3270 PCI_REVISION(pa->pa_class) >= 0x10); 3271 } 3272 3273 void 3274 sis_chip_map(sc, pa) 3275 struct pciide_softc *sc; 3276 struct pci_attach_args *pa; 3277 { 3278 struct pciide_channel *cp; 3279 int channel; 3280 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 3281 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3282 pcireg_t rev = PCI_REVISION(pa->pa_class); 3283 bus_size_t cmdsize, ctlsize; 3284 3285 if (pciide_chipen(sc, pa) == 0) 3286 return; 3287 printf(": Silicon Integrated System "); 3288 pci_find_device(NULL, sis_hostbr_match); 3289 if (sis_hostbr_type_match) { 3290 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 3291 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 3292 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3293 SIS_REG_57) & 0x7f); 3294 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 3295 PCI_ID_REG)) == SIS_PRODUCT_5518) { 3296 printf("96X UDMA%d", 3297 sis_hostbr_type_match->udma_mode); 3298 sc->sis_type = SIS_TYPE_133NEW; 3299 sc->sc_wdcdev.UDMA_cap = 3300 sis_hostbr_type_match->udma_mode; 3301 } else { 3302 if (pci_find_device(NULL, sis_south_match)) { 3303 sc->sis_type = SIS_TYPE_133OLD; 3304 sc->sc_wdcdev.UDMA_cap = 3305 sis_hostbr_type_match->udma_mode; 3306 } else { 3307 sc->sis_type = SIS_TYPE_100NEW; 3308 sc->sc_wdcdev.UDMA_cap = 3309 sis_hostbr_type_match->udma_mode; 3310 } 3311 } 3312 } else { 3313 sc->sis_type = sis_hostbr_type_match->type; 3314 sc->sc_wdcdev.UDMA_cap = 3315 sis_hostbr_type_match->udma_mode; 3316 } 3317 printf(sis_hostbr_type_match->name); 3318 } else { 3319 printf("5597/5598"); 3320 if (rev >= 0xd0) { 3321 sc->sc_wdcdev.UDMA_cap = 2; 3322 sc->sis_type = SIS_TYPE_66; 3323 } else { 3324 sc->sc_wdcdev.UDMA_cap = 0; 3325 sc->sis_type = SIS_TYPE_NOUDMA; 3326 } 3327 } 3328 printf(" IDE controller (rev. 0x%02x)\n", PCI_REVISION(pa->pa_class)); 3329 printf("%s: bus-master DMA support present", 3330 sc->sc_wdcdev.sc_dev.dv_xname); 3331 pciide_mapreg_dma(sc, pa); 3332 printf("\n"); 3333 3334 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3335 WDC_CAPABILITY_MODE; 3336 if (sc->sc_dma_ok) { 3337 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3338 sc->sc_wdcdev.irqack = pciide_irqack; 3339 if (sc->sis_type >= SIS_TYPE_66) 3340 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3341 } 3342 3343 sc->sc_wdcdev.PIO_cap = 4; 3344 sc->sc_wdcdev.DMA_cap = 2; 3345 3346 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3347 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3348 switch(sc->sis_type) { 3349 case SIS_TYPE_NOUDMA: 3350 case SIS_TYPE_66: 3351 case SIS_TYPE_100OLD: 3352 sc->sc_wdcdev.set_modes = sis_setup_channel; 3353 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 3354 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 3355 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 3356 break; 3357 case SIS_TYPE_100NEW: 3358 case SIS_TYPE_133OLD: 3359 sc->sc_wdcdev.set_modes = sis_setup_channel; 3360 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 3361 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 3362 break; 3363 case SIS_TYPE_133NEW: 3364 sc->sc_wdcdev.set_modes = sis96x_setup_channel; 3365 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 3366 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 3367 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 3368 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 3369 break; 3370 } 3371 3372 3373 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3374 cp = &sc->pciide_channels[channel]; 3375 if (pciide_chansetup(sc, channel, interface) == 0) 3376 continue; 3377 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 3378 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 3379 printf("%s: %s channel ignored (disabled)\n", 3380 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3381 continue; 3382 } 3383 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3384 pciide_pci_intr); 3385 if (cp->hw_ok == 0) 3386 continue; 3387 if (pciide_chan_candisable(cp)) { 3388 if (channel == 0) 3389 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 3390 else 3391 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 3392 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 3393 sis_ctr0); 3394 } 3395 pciide_map_compat_intr(pa, cp, channel, interface); 3396 if (cp->hw_ok == 0) 3397 continue; 3398 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 3399 } 3400 } 3401 3402 void 3403 sis96x_setup_channel(chp) 3404 struct channel_softc *chp; 3405 { 3406 struct ata_drive_datas *drvp; 3407 int drive; 3408 u_int32_t sis_tim; 3409 u_int32_t idedma_ctl; 3410 int regtim; 3411 struct pciide_channel *cp = (struct pciide_channel*)chp; 3412 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3413 3414 sis_tim = 0; 3415 idedma_ctl = 0; 3416 /* setup DMA if needed */ 3417 pciide_channel_dma_setup(cp); 3418 3419 for (drive = 0; drive < 2; drive++) { 3420 regtim = SIS_TIM133( 3421 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 3422 chp->channel, drive); 3423 drvp = &chp->ch_drive[drive]; 3424 /* If no drive, skip */ 3425 if ((drvp->drive_flags & DRIVE) == 0) 3426 continue; 3427 /* add timing values, setup DMA if needed */ 3428 if (drvp->drive_flags & DRIVE_UDMA) { 3429 /* use Ultra/DMA */ 3430 drvp->drive_flags &= ~DRIVE_DMA; 3431 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3432 SIS96x_REG_CBL(chp->channel)) & SIS96x_REG_CBL_33) { 3433 if (drvp->UDMA_mode > 2) 3434 drvp->UDMA_mode = 2; 3435 } 3436 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 3437 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3438 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3439 } else if (drvp->drive_flags & DRIVE_DMA) { 3440 /* 3441 * use Multiword DMA 3442 * Timings will be used for both PIO and DMA, 3443 * so adjust DMA mode if needed 3444 */ 3445 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3446 drvp->PIO_mode = drvp->DMA_mode + 2; 3447 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3448 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3449 drvp->PIO_mode - 2 : 0; 3450 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 3451 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3452 } else { 3453 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3454 } 3455 WDCDEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 3456 "channel %d drive %d: 0x%x (reg 0x%x)\n", 3457 chp->channel, drive, sis_tim, regtim), DEBUG_PROBE); 3458 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 3459 } 3460 if (idedma_ctl != 0) { 3461 /* Add software bits in status register */ 3462 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3463 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3464 idedma_ctl); 3465 } 3466 pciide_print_modes(cp); 3467 } 3468 3469 void 3470 sis_setup_channel(chp) 3471 struct channel_softc *chp; 3472 { 3473 struct ata_drive_datas *drvp; 3474 int drive; 3475 u_int32_t sis_tim; 3476 u_int32_t idedma_ctl; 3477 struct pciide_channel *cp = (struct pciide_channel*)chp; 3478 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3479 3480 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 3481 "channel %d 0x%x\n", chp->channel, 3482 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 3483 DEBUG_PROBE); 3484 sis_tim = 0; 3485 idedma_ctl = 0; 3486 /* setup DMA if needed */ 3487 pciide_channel_dma_setup(cp); 3488 3489 for (drive = 0; drive < 2; drive++) { 3490 drvp = &chp->ch_drive[drive]; 3491 /* If no drive, skip */ 3492 if ((drvp->drive_flags & DRIVE) == 0) 3493 continue; 3494 /* add timing values, setup DMA if needed */ 3495 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3496 (drvp->drive_flags & DRIVE_UDMA) == 0) 3497 goto pio; 3498 3499 if (drvp->drive_flags & DRIVE_UDMA) { 3500 /* use Ultra/DMA */ 3501 drvp->drive_flags &= ~DRIVE_DMA; 3502 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3503 SIS_REG_CBL) & SIS_REG_CBL_33(chp->channel)) { 3504 if (drvp->UDMA_mode > 2) 3505 drvp->UDMA_mode = 2; 3506 } 3507 switch (sc->sis_type) { 3508 case SIS_TYPE_66: 3509 case SIS_TYPE_100OLD: 3510 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 3511 SIS_TIM66_UDMA_TIME_OFF(drive); 3512 break; 3513 case SIS_TYPE_100NEW: 3514 sis_tim |= 3515 sis_udma100new_tim[drvp->UDMA_mode] << 3516 SIS_TIM100_UDMA_TIME_OFF(drive); 3517 case SIS_TYPE_133OLD: 3518 sis_tim |= 3519 sis_udma133old_tim[drvp->UDMA_mode] << 3520 SIS_TIM100_UDMA_TIME_OFF(drive); 3521 break; 3522 default: 3523 printf("unknown SiS IDE type %d\n", 3524 sc->sis_type); 3525 } 3526 } else { 3527 /* 3528 * use Multiword DMA 3529 * Timings will be used for both PIO and DMA, 3530 * so adjust DMA mode if needed 3531 */ 3532 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3533 drvp->PIO_mode = drvp->DMA_mode + 2; 3534 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3535 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3536 drvp->PIO_mode - 2 : 0; 3537 if (drvp->DMA_mode == 0) 3538 drvp->PIO_mode = 0; 3539 } 3540 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3541 pio: switch (sc->sis_type) { 3542 case SIS_TYPE_NOUDMA: 3543 case SIS_TYPE_66: 3544 case SIS_TYPE_100OLD: 3545 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3546 SIS_TIM66_ACT_OFF(drive); 3547 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3548 SIS_TIM66_REC_OFF(drive); 3549 break; 3550 case SIS_TYPE_100NEW: 3551 case SIS_TYPE_133OLD: 3552 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3553 SIS_TIM100_ACT_OFF(drive); 3554 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3555 SIS_TIM100_REC_OFF(drive); 3556 break; 3557 default: 3558 printf("unknown SiS IDE type %d\n", 3559 sc->sis_type); 3560 } 3561 } 3562 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 3563 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 3564 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 3565 if (idedma_ctl != 0) { 3566 /* Add software bits in status register */ 3567 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3568 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3569 idedma_ctl); 3570 } 3571 pciide_print_modes(cp); 3572 } 3573 3574 void 3575 acer_chip_map(sc, pa) 3576 struct pciide_softc *sc; 3577 struct pci_attach_args *pa; 3578 { 3579 struct pciide_channel *cp; 3580 int channel; 3581 pcireg_t cr, interface; 3582 bus_size_t cmdsize, ctlsize; 3583 pcireg_t rev = PCI_REVISION(pa->pa_class); 3584 3585 if (pciide_chipen(sc, pa) == 0) 3586 return; 3587 printf("%s: bus-master DMA support present", 3588 sc->sc_wdcdev.sc_dev.dv_xname); 3589 pciide_mapreg_dma(sc, pa); 3590 printf("\n"); 3591 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3592 WDC_CAPABILITY_MODE; 3593 if (sc->sc_dma_ok) { 3594 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3595 if (rev >= 0x20) { 3596 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3597 if (rev >= 0xC4) 3598 sc->sc_wdcdev.UDMA_cap = 5; 3599 else if (rev >= 0xC2) 3600 sc->sc_wdcdev.UDMA_cap = 4; 3601 else 3602 sc->sc_wdcdev.UDMA_cap = 2; 3603 } 3604 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3605 sc->sc_wdcdev.irqack = pciide_irqack; 3606 } 3607 3608 sc->sc_wdcdev.PIO_cap = 4; 3609 sc->sc_wdcdev.DMA_cap = 2; 3610 sc->sc_wdcdev.set_modes = acer_setup_channel; 3611 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3612 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3613 3614 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3615 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3616 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3617 3618 /* Enable "microsoft register bits" R/W. */ 3619 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3620 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3621 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3622 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3623 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3624 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3625 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3626 ~ACER_CHANSTATUSREGS_RO); 3627 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3628 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3629 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3630 /* Don't use cr, re-read the real register content instead */ 3631 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3632 PCI_CLASS_REG)); 3633 3634 /* From linux: enable "Cable Detection" */ 3635 if (rev >= 0xC2) { 3636 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3637 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3638 | ACER_0x4B_CDETECT); 3639 } 3640 3641 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3642 cp = &sc->pciide_channels[channel]; 3643 if (pciide_chansetup(sc, channel, interface) == 0) 3644 continue; 3645 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3646 printf("%s: %s channel ignored (disabled)\n", 3647 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3648 continue; 3649 } 3650 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3651 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3652 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3653 if (cp->hw_ok == 0) 3654 continue; 3655 if (pciide_chan_candisable(cp)) { 3656 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3657 pci_conf_write(sc->sc_pc, sc->sc_tag, 3658 PCI_CLASS_REG, cr); 3659 } 3660 pciide_map_compat_intr(pa, cp, channel, interface); 3661 acer_setup_channel(&cp->wdc_channel); 3662 } 3663 } 3664 3665 void 3666 acer_setup_channel(chp) 3667 struct channel_softc *chp; 3668 { 3669 struct ata_drive_datas *drvp; 3670 int drive; 3671 u_int32_t acer_fifo_udma; 3672 u_int32_t idedma_ctl; 3673 struct pciide_channel *cp = (struct pciide_channel*)chp; 3674 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3675 3676 idedma_ctl = 0; 3677 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3678 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3679 acer_fifo_udma), DEBUG_PROBE); 3680 /* setup DMA if needed */ 3681 pciide_channel_dma_setup(cp); 3682 3683 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3684 DRIVE_UDMA) { /* check 80 pins cable */ 3685 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3686 ACER_0x4A_80PIN(chp->channel)) { 3687 if (chp->ch_drive[0].UDMA_mode > 2) 3688 chp->ch_drive[0].UDMA_mode = 2; 3689 if (chp->ch_drive[1].UDMA_mode > 2) 3690 chp->ch_drive[1].UDMA_mode = 2; 3691 } 3692 } 3693 3694 for (drive = 0; drive < 2; drive++) { 3695 drvp = &chp->ch_drive[drive]; 3696 /* If no drive, skip */ 3697 if ((drvp->drive_flags & DRIVE) == 0) 3698 continue; 3699 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3700 "channel %d drive %d 0x%x\n", chp->channel, drive, 3701 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3702 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3703 /* clear FIFO/DMA mode */ 3704 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3705 ACER_UDMA_EN(chp->channel, drive) | 3706 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3707 3708 /* add timing values, setup DMA if needed */ 3709 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3710 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3711 acer_fifo_udma |= 3712 ACER_FTH_OPL(chp->channel, drive, 0x1); 3713 goto pio; 3714 } 3715 3716 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3717 if (drvp->drive_flags & DRIVE_UDMA) { 3718 /* use Ultra/DMA */ 3719 drvp->drive_flags &= ~DRIVE_DMA; 3720 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3721 acer_fifo_udma |= 3722 ACER_UDMA_TIM(chp->channel, drive, 3723 acer_udma[drvp->UDMA_mode]); 3724 /* XXX disable if one drive < UDMA3 ? */ 3725 if (drvp->UDMA_mode >= 3) { 3726 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3727 ACER_0x4B, 3728 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3729 ACER_0x4B) | ACER_0x4B_UDMA66); 3730 } 3731 } else { 3732 /* 3733 * use Multiword DMA 3734 * Timings will be used for both PIO and DMA, 3735 * so adjust DMA mode if needed 3736 */ 3737 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3738 drvp->PIO_mode = drvp->DMA_mode + 2; 3739 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3740 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3741 drvp->PIO_mode - 2 : 0; 3742 if (drvp->DMA_mode == 0) 3743 drvp->PIO_mode = 0; 3744 } 3745 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3746 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3747 ACER_IDETIM(chp->channel, drive), 3748 acer_pio[drvp->PIO_mode]); 3749 } 3750 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3751 acer_fifo_udma), DEBUG_PROBE); 3752 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3753 if (idedma_ctl != 0) { 3754 /* Add software bits in status register */ 3755 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3756 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3757 idedma_ctl); 3758 } 3759 pciide_print_modes(cp); 3760 } 3761 3762 int 3763 acer_pci_intr(arg) 3764 void *arg; 3765 { 3766 struct pciide_softc *sc = arg; 3767 struct pciide_channel *cp; 3768 struct channel_softc *wdc_cp; 3769 int i, rv, crv; 3770 u_int32_t chids; 3771 3772 rv = 0; 3773 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3774 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3775 cp = &sc->pciide_channels[i]; 3776 wdc_cp = &cp->wdc_channel; 3777 /* If a compat channel skip. */ 3778 if (cp->compat) 3779 continue; 3780 if (chids & ACER_CHIDS_INT(i)) { 3781 crv = wdcintr(wdc_cp); 3782 if (crv == 0) 3783 printf("%s:%d: bogus intr\n", 3784 sc->sc_wdcdev.sc_dev.dv_xname, i); 3785 else 3786 rv = 1; 3787 } 3788 } 3789 return rv; 3790 } 3791 3792 void 3793 hpt_chip_map(sc, pa) 3794 struct pciide_softc *sc; 3795 struct pci_attach_args *pa; 3796 { 3797 struct pciide_channel *cp; 3798 int i, compatchan, revision; 3799 pcireg_t interface; 3800 bus_size_t cmdsize, ctlsize; 3801 3802 if (pciide_chipen(sc, pa) == 0) 3803 return; 3804 revision = PCI_REVISION(pa->pa_class); 3805 printf(": Triones/Highpoint "); 3806 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3807 printf("HPT374 IDE Controller\n"); 3808 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372) 3809 printf("HPT372 IDE Controller\n"); 3810 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 3811 if (revision == HPT372_REV) 3812 printf("HPT372 IDE Controller\n"); 3813 else if (revision == HPT370_REV) 3814 printf("HPT370 IDE Controller\n"); 3815 else if (revision == HPT370A_REV) 3816 printf("HPT370A IDE Controller\n"); 3817 else if (revision == HPT366_REV) 3818 printf("HPT366 IDE Controller\n"); 3819 else 3820 printf("unknown HPT IDE controller rev %d\n", revision); 3821 } else 3822 printf("unknown HPT IDE controller 0x%x\n", 3823 sc->sc_pp->ide_product); 3824 3825 /* 3826 * when the chip is in native mode it identifies itself as a 3827 * 'misc mass storage'. Fake interface in this case. 3828 */ 3829 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3830 interface = PCI_INTERFACE(pa->pa_class); 3831 } else { 3832 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3833 PCIIDE_INTERFACE_PCI(0); 3834 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3835 (revision == HPT370_REV || revision == HPT370A_REV || 3836 revision == HPT372_REV)) || 3837 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3838 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3839 interface |= PCIIDE_INTERFACE_PCI(1); 3840 } 3841 3842 printf("%s: bus-master DMA support present", 3843 sc->sc_wdcdev.sc_dev.dv_xname); 3844 pciide_mapreg_dma(sc, pa); 3845 printf("\n"); 3846 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3847 WDC_CAPABILITY_MODE; 3848 if (sc->sc_dma_ok) { 3849 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3850 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3851 sc->sc_wdcdev.irqack = pciide_irqack; 3852 } 3853 sc->sc_wdcdev.PIO_cap = 4; 3854 sc->sc_wdcdev.DMA_cap = 2; 3855 3856 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3857 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3858 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3859 revision == HPT366_REV) { 3860 sc->sc_wdcdev.UDMA_cap = 4; 3861 /* 3862 * The 366 has 2 PCI IDE functions, one for primary and one 3863 * for secondary. So we need to call pciide_mapregs_compat() 3864 * with the real channel 3865 */ 3866 if (pa->pa_function == 0) { 3867 compatchan = 0; 3868 } else if (pa->pa_function == 1) { 3869 compatchan = 1; 3870 } else { 3871 printf("%s: unexpected PCI function %d\n", 3872 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3873 return; 3874 } 3875 sc->sc_wdcdev.nchannels = 1; 3876 } else { 3877 sc->sc_wdcdev.nchannels = 2; 3878 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 3879 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3880 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3881 revision == HPT372_REV)) 3882 sc->sc_wdcdev.UDMA_cap = 6; 3883 else 3884 sc->sc_wdcdev.UDMA_cap = 5; 3885 } 3886 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3887 cp = &sc->pciide_channels[i]; 3888 if (sc->sc_wdcdev.nchannels > 1) { 3889 compatchan = i; 3890 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3891 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3892 printf("%s: %s channel ignored (disabled)\n", 3893 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3894 continue; 3895 } 3896 } 3897 if (pciide_chansetup(sc, i, interface) == 0) 3898 continue; 3899 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3900 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3901 &ctlsize, hpt_pci_intr); 3902 } else { 3903 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3904 &cmdsize, &ctlsize); 3905 } 3906 if (cp->hw_ok == 0) 3907 return; 3908 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3909 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3910 wdcattach(&cp->wdc_channel); 3911 hpt_setup_channel(&cp->wdc_channel); 3912 } 3913 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3914 (revision == HPT370_REV || revision == HPT370A_REV || 3915 revision == HPT372_REV)) || 3916 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3917 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 3918 /* 3919 * HPT370_REV and highter has a bit to disable interrupts, 3920 * make sure to clear it 3921 */ 3922 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3923 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3924 ~HPT_CSEL_IRQDIS); 3925 } 3926 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 3927 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3928 revision == HPT372_REV ) || 3929 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3930 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3931 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 3932 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 3933 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 3934 return; 3935 } 3936 3937 void 3938 hpt_setup_channel(chp) 3939 struct channel_softc *chp; 3940 { 3941 struct ata_drive_datas *drvp; 3942 int drive; 3943 int cable; 3944 u_int32_t before, after; 3945 u_int32_t idedma_ctl; 3946 struct pciide_channel *cp = (struct pciide_channel*)chp; 3947 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3948 int revision = 3949 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 3950 3951 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3952 3953 /* setup DMA if needed */ 3954 pciide_channel_dma_setup(cp); 3955 3956 idedma_ctl = 0; 3957 3958 /* Per drive settings */ 3959 for (drive = 0; drive < 2; drive++) { 3960 drvp = &chp->ch_drive[drive]; 3961 /* If no drive, skip */ 3962 if ((drvp->drive_flags & DRIVE) == 0) 3963 continue; 3964 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3965 HPT_IDETIM(chp->channel, drive)); 3966 3967 /* add timing values, setup DMA if needed */ 3968 if (drvp->drive_flags & DRIVE_UDMA) { 3969 /* use Ultra/DMA */ 3970 drvp->drive_flags &= ~DRIVE_DMA; 3971 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3972 drvp->UDMA_mode > 2) 3973 drvp->UDMA_mode = 2; 3974 switch (sc->sc_pp->ide_product) { 3975 case PCI_PRODUCT_TRIONES_HPT374: 3976 after = hpt374_udma[drvp->UDMA_mode]; 3977 break; 3978 case PCI_PRODUCT_TRIONES_HPT372: 3979 after = hpt372_udma[drvp->UDMA_mode]; 3980 break; 3981 case PCI_PRODUCT_TRIONES_HPT366: 3982 default: 3983 switch(revision) { 3984 case HPT372_REV: 3985 after = hpt372_udma[drvp->UDMA_mode]; 3986 break; 3987 case HPT370_REV: 3988 case HPT370A_REV: 3989 after = hpt370_udma[drvp->UDMA_mode]; 3990 break; 3991 case HPT366_REV: 3992 default: 3993 after = hpt366_udma[drvp->UDMA_mode]; 3994 break; 3995 } 3996 } 3997 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3998 } else if (drvp->drive_flags & DRIVE_DMA) { 3999 /* 4000 * use Multiword DMA. 4001 * Timings will be used for both PIO and DMA, so adjust 4002 * DMA mode if needed 4003 */ 4004 if (drvp->PIO_mode >= 3 && 4005 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 4006 drvp->DMA_mode = drvp->PIO_mode - 2; 4007 } 4008 switch (sc->sc_pp->ide_product) { 4009 case PCI_PRODUCT_TRIONES_HPT374: 4010 after = hpt374_dma[drvp->DMA_mode]; 4011 break; 4012 case PCI_PRODUCT_TRIONES_HPT372: 4013 after = hpt372_dma[drvp->DMA_mode]; 4014 break; 4015 case PCI_PRODUCT_TRIONES_HPT366: 4016 default: 4017 switch(revision) { 4018 case HPT372_REV: 4019 after = hpt372_dma[drvp->DMA_mode]; 4020 break; 4021 case HPT370_REV: 4022 case HPT370A_REV: 4023 after = hpt370_dma[drvp->DMA_mode]; 4024 break; 4025 case HPT366_REV: 4026 default: 4027 after = hpt366_dma[drvp->DMA_mode]; 4028 break; 4029 } 4030 } 4031 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4032 } else { 4033 /* PIO only */ 4034 switch (sc->sc_pp->ide_product) { 4035 case PCI_PRODUCT_TRIONES_HPT374: 4036 after = hpt374_pio[drvp->PIO_mode]; 4037 break; 4038 case PCI_PRODUCT_TRIONES_HPT372: 4039 after = hpt372_pio[drvp->PIO_mode]; 4040 break; 4041 case PCI_PRODUCT_TRIONES_HPT366: 4042 default: 4043 switch(revision) { 4044 case HPT372_REV: 4045 after = hpt372_pio[drvp->PIO_mode]; 4046 break; 4047 case HPT370_REV: 4048 case HPT370A_REV: 4049 after = hpt370_pio[drvp->PIO_mode]; 4050 break; 4051 case HPT366_REV: 4052 default: 4053 after = hpt366_pio[drvp->PIO_mode]; 4054 break; 4055 } 4056 } 4057 } 4058 pci_conf_write(sc->sc_pc, sc->sc_tag, 4059 HPT_IDETIM(chp->channel, drive), after); 4060 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 4061 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 4062 after, before), DEBUG_PROBE); 4063 } 4064 if (idedma_ctl != 0) { 4065 /* Add software bits in status register */ 4066 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4067 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4068 idedma_ctl); 4069 } 4070 pciide_print_modes(cp); 4071 } 4072 4073 int 4074 hpt_pci_intr(arg) 4075 void *arg; 4076 { 4077 struct pciide_softc *sc = arg; 4078 struct pciide_channel *cp; 4079 struct channel_softc *wdc_cp; 4080 int rv = 0; 4081 int dmastat, i, crv; 4082 4083 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4084 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4085 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4086 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4087 IDEDMA_CTL_INTR) 4088 continue; 4089 cp = &sc->pciide_channels[i]; 4090 wdc_cp = &cp->wdc_channel; 4091 crv = wdcintr(wdc_cp); 4092 if (crv == 0) { 4093 printf("%s:%d: bogus intr\n", 4094 sc->sc_wdcdev.sc_dev.dv_xname, i); 4095 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4096 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4097 } else 4098 rv = 1; 4099 } 4100 return rv; 4101 } 4102 4103 4104 /* Macros to test product */ 4105 #define PDC_IS_262(sc) \ 4106 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 4107 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 4108 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 4109 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4110 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4111 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4112 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4113 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4114 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4115 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4116 #define PDC_IS_265(sc) \ 4117 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 4118 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 4119 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4120 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4121 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4122 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4123 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4124 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4125 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4126 #define PDC_IS_268(sc) \ 4127 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4128 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4129 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4130 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4131 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4132 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4133 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4134 #define PDC_IS_276(sc) \ 4135 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4136 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4137 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4138 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4139 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4140 4141 void 4142 pdc202xx_chip_map(sc, pa) 4143 struct pciide_softc *sc; 4144 struct pci_attach_args *pa; 4145 { 4146 struct pciide_channel *cp; 4147 int channel; 4148 pcireg_t interface, st, mode; 4149 bus_size_t cmdsize, ctlsize; 4150 4151 if (!PDC_IS_268(sc)) { 4152 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4153 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 4154 st), DEBUG_PROBE); 4155 } 4156 if (pciide_chipen(sc, pa) == 0) 4157 return; 4158 4159 /* turn off RAID mode */ 4160 if (!PDC_IS_268(sc)) 4161 st &= ~PDC2xx_STATE_IDERAID; 4162 4163 /* 4164 * can't rely on the PCI_CLASS_REG content if the chip was in raid 4165 * mode. We have to fake interface 4166 */ 4167 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 4168 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 4169 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4170 4171 printf("%s: bus-master DMA support present", 4172 sc->sc_wdcdev.sc_dev.dv_xname); 4173 pciide_mapreg_dma(sc, pa); 4174 printf("\n"); 4175 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4176 WDC_CAPABILITY_MODE; 4177 if (sc->sc_dma_ok) { 4178 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4179 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4180 sc->sc_wdcdev.irqack = pciide_irqack; 4181 } 4182 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 4183 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 4184 sc->sc_wdcdev.cap |= WDC_CAPABILITY_RAID; 4185 sc->sc_wdcdev.PIO_cap = 4; 4186 sc->sc_wdcdev.DMA_cap = 2; 4187 if (PDC_IS_276(sc)) 4188 sc->sc_wdcdev.UDMA_cap = 6; 4189 else if (PDC_IS_265(sc)) 4190 sc->sc_wdcdev.UDMA_cap = 5; 4191 else if (PDC_IS_262(sc)) 4192 sc->sc_wdcdev.UDMA_cap = 4; 4193 else 4194 sc->sc_wdcdev.UDMA_cap = 2; 4195 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 4196 pdc20268_setup_channel : pdc202xx_setup_channel; 4197 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4198 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4199 4200 if (!PDC_IS_268(sc)) { 4201 /* setup failsafe defaults */ 4202 mode = 0; 4203 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 4204 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 4205 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 4206 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 4207 for (channel = 0; 4208 channel < sc->sc_wdcdev.nchannels; 4209 channel++) { 4210 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 4211 "drive 0 initial timings 0x%x, now 0x%x\n", 4212 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 4213 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 4214 DEBUG_PROBE); 4215 pci_conf_write(sc->sc_pc, sc->sc_tag, 4216 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 4217 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 4218 "drive 1 initial timings 0x%x, now 0x%x\n", 4219 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 4220 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 4221 pci_conf_write(sc->sc_pc, sc->sc_tag, 4222 PDC2xx_TIM(channel, 1), mode); 4223 } 4224 4225 mode = PDC2xx_SCR_DMA; 4226 if (PDC_IS_262(sc)) { 4227 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 4228 } else { 4229 /* the BIOS set it up this way */ 4230 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 4231 } 4232 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 4233 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 4234 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 4235 "now 0x%x\n", 4236 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4237 PDC2xx_SCR), 4238 mode), DEBUG_PROBE); 4239 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4240 PDC2xx_SCR, mode); 4241 4242 /* controller initial state register is OK even without BIOS */ 4243 /* Set DMA mode to IDE DMA compatibility */ 4244 mode = 4245 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 4246 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 4247 DEBUG_PROBE); 4248 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 4249 mode | 0x1); 4250 mode = 4251 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 4252 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 4253 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 4254 mode | 0x1); 4255 } 4256 4257 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4258 cp = &sc->pciide_channels[channel]; 4259 if (pciide_chansetup(sc, channel, interface) == 0) 4260 continue; 4261 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 4262 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 4263 printf("%s: %s channel ignored (disabled)\n", 4264 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4265 continue; 4266 } 4267 if (PDC_IS_265(sc)) 4268 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4269 pdc20265_pci_intr); 4270 else 4271 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4272 pdc202xx_pci_intr); 4273 if (cp->hw_ok == 0) 4274 continue; 4275 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 4276 st &= ~(PDC_IS_262(sc) ? 4277 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 4278 pciide_map_compat_intr(pa, cp, channel, interface); 4279 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 4280 } 4281 if (!PDC_IS_268(sc)) { 4282 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 4283 "0x%x\n", st), DEBUG_PROBE); 4284 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 4285 } 4286 return; 4287 } 4288 4289 void 4290 pdc202xx_setup_channel(chp) 4291 struct channel_softc *chp; 4292 { 4293 struct ata_drive_datas *drvp; 4294 int drive; 4295 pcireg_t mode, st; 4296 u_int32_t idedma_ctl, scr, atapi; 4297 struct pciide_channel *cp = (struct pciide_channel*)chp; 4298 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4299 int channel = chp->channel; 4300 4301 /* setup DMA if needed */ 4302 pciide_channel_dma_setup(cp); 4303 4304 idedma_ctl = 0; 4305 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 4306 sc->sc_wdcdev.sc_dev.dv_xname, 4307 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 4308 DEBUG_PROBE); 4309 4310 /* Per channel settings */ 4311 if (PDC_IS_262(sc)) { 4312 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4313 PDC262_U66); 4314 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4315 /* Trim UDMA mode */ 4316 if ((st & PDC262_STATE_80P(channel)) != 0 || 4317 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4318 chp->ch_drive[0].UDMA_mode <= 2) || 4319 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4320 chp->ch_drive[1].UDMA_mode <= 2)) { 4321 if (chp->ch_drive[0].UDMA_mode > 2) 4322 chp->ch_drive[0].UDMA_mode = 2; 4323 if (chp->ch_drive[1].UDMA_mode > 2) 4324 chp->ch_drive[1].UDMA_mode = 2; 4325 } 4326 /* Set U66 if needed */ 4327 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4328 chp->ch_drive[0].UDMA_mode > 2) || 4329 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4330 chp->ch_drive[1].UDMA_mode > 2)) 4331 scr |= PDC262_U66_EN(channel); 4332 else 4333 scr &= ~PDC262_U66_EN(channel); 4334 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4335 PDC262_U66, scr); 4336 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 4337 sc->sc_wdcdev.sc_dev.dv_xname, channel, 4338 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4339 PDC262_ATAPI(channel))), DEBUG_PROBE); 4340 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 4341 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 4342 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4343 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4344 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 4345 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4346 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4347 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 4348 atapi = 0; 4349 else 4350 atapi = PDC262_ATAPI_UDMA; 4351 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4352 PDC262_ATAPI(channel), atapi); 4353 } 4354 } 4355 for (drive = 0; drive < 2; drive++) { 4356 drvp = &chp->ch_drive[drive]; 4357 /* If no drive, skip */ 4358 if ((drvp->drive_flags & DRIVE) == 0) 4359 continue; 4360 mode = 0; 4361 if (drvp->drive_flags & DRIVE_UDMA) { 4362 /* use Ultra/DMA */ 4363 drvp->drive_flags &= ~DRIVE_DMA; 4364 mode = PDC2xx_TIM_SET_MB(mode, 4365 pdc2xx_udma_mb[drvp->UDMA_mode]); 4366 mode = PDC2xx_TIM_SET_MC(mode, 4367 pdc2xx_udma_mc[drvp->UDMA_mode]); 4368 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4369 } else if (drvp->drive_flags & DRIVE_DMA) { 4370 mode = PDC2xx_TIM_SET_MB(mode, 4371 pdc2xx_dma_mb[drvp->DMA_mode]); 4372 mode = PDC2xx_TIM_SET_MC(mode, 4373 pdc2xx_dma_mc[drvp->DMA_mode]); 4374 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4375 } else { 4376 mode = PDC2xx_TIM_SET_MB(mode, 4377 pdc2xx_dma_mb[0]); 4378 mode = PDC2xx_TIM_SET_MC(mode, 4379 pdc2xx_dma_mc[0]); 4380 } 4381 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 4382 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 4383 if (drvp->drive_flags & DRIVE_ATA) 4384 mode |= PDC2xx_TIM_PRE; 4385 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 4386 if (drvp->PIO_mode >= 3) { 4387 mode |= PDC2xx_TIM_IORDY; 4388 if (drive == 0) 4389 mode |= PDC2xx_TIM_IORDYp; 4390 } 4391 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 4392 "timings 0x%x\n", 4393 sc->sc_wdcdev.sc_dev.dv_xname, 4394 chp->channel, drive, mode), DEBUG_PROBE); 4395 pci_conf_write(sc->sc_pc, sc->sc_tag, 4396 PDC2xx_TIM(chp->channel, drive), mode); 4397 } 4398 if (idedma_ctl != 0) { 4399 /* Add software bits in status register */ 4400 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4401 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4402 idedma_ctl); 4403 } 4404 pciide_print_modes(cp); 4405 } 4406 4407 void 4408 pdc20268_setup_channel(chp) 4409 struct channel_softc *chp; 4410 { 4411 struct ata_drive_datas *drvp; 4412 int drive; 4413 u_int32_t idedma_ctl; 4414 struct pciide_channel *cp = (struct pciide_channel*)chp; 4415 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4416 int u100; 4417 4418 /* setup DMA if needed */ 4419 pciide_channel_dma_setup(cp); 4420 4421 idedma_ctl = 0; 4422 4423 /* I don't know what this is for, FreeBSD does it ... */ 4424 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4425 IDEDMA_CMD + 0x1, 0x0b); 4426 4427 /* 4428 * I don't know what this is for; FreeBSD checks this ... this is not 4429 * cable type detect. 4430 */ 4431 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4432 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 4433 4434 for (drive = 0; drive < 2; drive++) { 4435 drvp = &chp->ch_drive[drive]; 4436 /* If no drive, skip */ 4437 if ((drvp->drive_flags & DRIVE) == 0) 4438 continue; 4439 if (drvp->drive_flags & DRIVE_UDMA) { 4440 /* use Ultra/DMA */ 4441 drvp->drive_flags &= ~DRIVE_DMA; 4442 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4443 if (drvp->UDMA_mode > 2 && u100 == 0) 4444 drvp->UDMA_mode = 2; 4445 } else if (drvp->drive_flags & DRIVE_DMA) { 4446 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4447 } 4448 } 4449 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 4450 if (idedma_ctl != 0) { 4451 /* Add software bits in status register */ 4452 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4453 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4454 idedma_ctl); 4455 } 4456 pciide_print_modes(cp); 4457 } 4458 4459 int 4460 pdc202xx_pci_intr(arg) 4461 void *arg; 4462 { 4463 struct pciide_softc *sc = arg; 4464 struct pciide_channel *cp; 4465 struct channel_softc *wdc_cp; 4466 int i, rv, crv; 4467 u_int32_t scr; 4468 4469 rv = 0; 4470 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 4471 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4472 cp = &sc->pciide_channels[i]; 4473 wdc_cp = &cp->wdc_channel; 4474 /* If a compat channel skip. */ 4475 if (cp->compat) 4476 continue; 4477 if (scr & PDC2xx_SCR_INT(i)) { 4478 crv = wdcintr(wdc_cp); 4479 if (crv == 0) 4480 printf("%s:%d: bogus intr (reg 0x%x)\n", 4481 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 4482 else 4483 rv = 1; 4484 } 4485 } 4486 return rv; 4487 } 4488 4489 int 4490 pdc20265_pci_intr(arg) 4491 void *arg; 4492 { 4493 struct pciide_softc *sc = arg; 4494 struct pciide_channel *cp; 4495 struct channel_softc *wdc_cp; 4496 int i, rv, crv; 4497 u_int32_t dmastat; 4498 4499 rv = 0; 4500 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4501 cp = &sc->pciide_channels[i]; 4502 wdc_cp = &cp->wdc_channel; 4503 /* If a compat channel skip. */ 4504 if (cp->compat) 4505 continue; 4506 /* 4507 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 4508 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 4509 * So use it instead (requires 2 reg reads instead of 1, 4510 * but we can't do it another way). 4511 */ 4512 dmastat = bus_space_read_1(sc->sc_dma_iot, 4513 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4514 if((dmastat & IDEDMA_CTL_INTR) == 0) 4515 continue; 4516 crv = wdcintr(wdc_cp); 4517 if (crv == 0) 4518 printf("%s:%d: bogus intr\n", 4519 sc->sc_wdcdev.sc_dev.dv_xname, i); 4520 else 4521 rv = 1; 4522 } 4523 return rv; 4524 } 4525 4526 void 4527 opti_chip_map(sc, pa) 4528 struct pciide_softc *sc; 4529 struct pci_attach_args *pa; 4530 { 4531 struct pciide_channel *cp; 4532 bus_size_t cmdsize, ctlsize; 4533 pcireg_t interface; 4534 u_int8_t init_ctrl; 4535 int channel; 4536 4537 if (pciide_chipen(sc, pa) == 0) 4538 return; 4539 printf("%s: bus-master DMA support present", 4540 sc->sc_wdcdev.sc_dev.dv_xname); 4541 4542 /* 4543 * XXXSCW: 4544 * There seem to be a couple of buggy revisions/implementations 4545 * of the OPTi pciide chipset. This kludge seems to fix one of 4546 * the reported problems (PR/11644) but still fails for the 4547 * other (PR/13151), although the latter may be due to other 4548 * issues too... 4549 */ 4550 if (PCI_REVISION(pa->pa_class) <= 0x12) { 4551 printf(" but disabled due to chip rev. <= 0x12"); 4552 sc->sc_dma_ok = 0; 4553 } else 4554 pciide_mapreg_dma(sc, pa); 4555 4556 printf("\n"); 4557 4558 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4559 WDC_CAPABILITY_MODE; 4560 sc->sc_wdcdev.PIO_cap = 4; 4561 if (sc->sc_dma_ok) { 4562 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4563 sc->sc_wdcdev.irqack = pciide_irqack; 4564 sc->sc_wdcdev.DMA_cap = 2; 4565 } 4566 sc->sc_wdcdev.set_modes = opti_setup_channel; 4567 4568 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4569 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4570 4571 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 4572 OPTI_REG_INIT_CONTROL); 4573 4574 interface = PCI_INTERFACE(pa->pa_class); 4575 4576 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4577 cp = &sc->pciide_channels[channel]; 4578 if (pciide_chansetup(sc, channel, interface) == 0) 4579 continue; 4580 if (channel == 1 && 4581 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 4582 printf("%s: %s channel ignored (disabled)\n", 4583 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4584 continue; 4585 } 4586 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4587 pciide_pci_intr); 4588 if (cp->hw_ok == 0) 4589 continue; 4590 pciide_map_compat_intr(pa, cp, channel, interface); 4591 if (cp->hw_ok == 0) 4592 continue; 4593 opti_setup_channel(&cp->wdc_channel); 4594 } 4595 } 4596 4597 void 4598 opti_setup_channel(chp) 4599 struct channel_softc *chp; 4600 { 4601 struct ata_drive_datas *drvp; 4602 struct pciide_channel *cp = (struct pciide_channel*)chp; 4603 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4604 int drive, spd; 4605 int mode[2]; 4606 u_int8_t rv, mr; 4607 4608 /* 4609 * The `Delay' and `Address Setup Time' fields of the 4610 * Miscellaneous Register are always zero initially. 4611 */ 4612 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 4613 mr &= ~(OPTI_MISC_DELAY_MASK | 4614 OPTI_MISC_ADDR_SETUP_MASK | 4615 OPTI_MISC_INDEX_MASK); 4616 4617 /* Prime the control register before setting timing values */ 4618 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 4619 4620 /* Determine the clockrate of the PCIbus the chip is attached to */ 4621 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 4622 spd &= OPTI_STRAP_PCI_SPEED_MASK; 4623 4624 /* setup DMA if needed */ 4625 pciide_channel_dma_setup(cp); 4626 4627 for (drive = 0; drive < 2; drive++) { 4628 drvp = &chp->ch_drive[drive]; 4629 /* If no drive, skip */ 4630 if ((drvp->drive_flags & DRIVE) == 0) { 4631 mode[drive] = -1; 4632 continue; 4633 } 4634 4635 if ((drvp->drive_flags & DRIVE_DMA)) { 4636 /* 4637 * Timings will be used for both PIO and DMA, 4638 * so adjust DMA mode if needed 4639 */ 4640 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 4641 drvp->PIO_mode = drvp->DMA_mode + 2; 4642 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 4643 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 4644 drvp->PIO_mode - 2 : 0; 4645 if (drvp->DMA_mode == 0) 4646 drvp->PIO_mode = 0; 4647 4648 mode[drive] = drvp->DMA_mode + 5; 4649 } else 4650 mode[drive] = drvp->PIO_mode; 4651 4652 if (drive && mode[0] >= 0 && 4653 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 4654 /* 4655 * Can't have two drives using different values 4656 * for `Address Setup Time'. 4657 * Slow down the faster drive to compensate. 4658 */ 4659 int d = (opti_tim_as[spd][mode[0]] > 4660 opti_tim_as[spd][mode[1]]) ? 0 : 1; 4661 4662 mode[d] = mode[1-d]; 4663 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4664 chp->ch_drive[d].DMA_mode = 0; 4665 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 4666 } 4667 } 4668 4669 for (drive = 0; drive < 2; drive++) { 4670 int m; 4671 if ((m = mode[drive]) < 0) 4672 continue; 4673 4674 /* Set the Address Setup Time and select appropriate index */ 4675 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4676 rv |= OPTI_MISC_INDEX(drive); 4677 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4678 4679 /* Set the pulse width and recovery timing parameters */ 4680 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4681 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4682 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4683 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4684 4685 /* Set the Enhanced Mode register appropriately */ 4686 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4687 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4688 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4689 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4690 } 4691 4692 /* Finally, enable the timings */ 4693 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4694 4695 pciide_print_modes(cp); 4696 } 4697 4698 #define ACARD_IS_850(sc) \ 4699 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4700 4701 void 4702 acard_chip_map(sc, pa) 4703 struct pciide_softc *sc; 4704 struct pci_attach_args *pa; 4705 { 4706 struct pciide_channel *cp; 4707 int i; 4708 pcireg_t interface; 4709 bus_size_t cmdsize, ctlsize; 4710 4711 if (pciide_chipen(sc, pa) == 0) 4712 return; 4713 4714 /* 4715 * when the chip is in native mode it identifies itself as a 4716 * 'misc mass storage'. Fake interface in this case. 4717 */ 4718 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4719 interface = PCI_INTERFACE(pa->pa_class); 4720 } else { 4721 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4722 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4723 } 4724 4725 printf("%s: bus-master DMA support present", 4726 sc->sc_wdcdev.sc_dev.dv_xname); 4727 pciide_mapreg_dma(sc, pa); 4728 printf("\n"); 4729 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4730 WDC_CAPABILITY_MODE; 4731 4732 if (sc->sc_dma_ok) { 4733 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4734 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4735 sc->sc_wdcdev.irqack = pciide_irqack; 4736 } 4737 sc->sc_wdcdev.PIO_cap = 4; 4738 sc->sc_wdcdev.DMA_cap = 2; 4739 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4740 4741 sc->sc_wdcdev.set_modes = acard_setup_channel; 4742 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4743 sc->sc_wdcdev.nchannels = 2; 4744 4745 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4746 cp = &sc->pciide_channels[i]; 4747 if (pciide_chansetup(sc, i, interface) == 0) 4748 continue; 4749 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4750 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4751 &ctlsize, pciide_pci_intr); 4752 } else { 4753 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4754 &cmdsize, &ctlsize); 4755 } 4756 if (cp->hw_ok == 0) 4757 return; 4758 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4759 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4760 wdcattach(&cp->wdc_channel); 4761 acard_setup_channel(&cp->wdc_channel); 4762 } 4763 if (!ACARD_IS_850(sc)) { 4764 u_int32_t reg; 4765 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4766 reg &= ~ATP860_CTRL_INT; 4767 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4768 } 4769 } 4770 4771 void 4772 acard_setup_channel(chp) 4773 struct channel_softc *chp; 4774 { 4775 struct ata_drive_datas *drvp; 4776 struct pciide_channel *cp = (struct pciide_channel*)chp; 4777 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4778 int channel = chp->channel; 4779 int drive; 4780 u_int32_t idetime, udma_mode; 4781 u_int32_t idedma_ctl; 4782 4783 /* setup DMA if needed */ 4784 pciide_channel_dma_setup(cp); 4785 4786 if (ACARD_IS_850(sc)) { 4787 idetime = 0; 4788 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4789 udma_mode &= ~ATP850_UDMA_MASK(channel); 4790 } else { 4791 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4792 idetime &= ~ATP860_SETTIME_MASK(channel); 4793 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4794 udma_mode &= ~ATP860_UDMA_MASK(channel); 4795 4796 /* check 80 pins cable */ 4797 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4798 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4799 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4800 & ATP860_CTRL_80P(chp->channel)) { 4801 if (chp->ch_drive[0].UDMA_mode > 2) 4802 chp->ch_drive[0].UDMA_mode = 2; 4803 if (chp->ch_drive[1].UDMA_mode > 2) 4804 chp->ch_drive[1].UDMA_mode = 2; 4805 } 4806 } 4807 } 4808 4809 idedma_ctl = 0; 4810 4811 /* Per drive settings */ 4812 for (drive = 0; drive < 2; drive++) { 4813 drvp = &chp->ch_drive[drive]; 4814 /* If no drive, skip */ 4815 if ((drvp->drive_flags & DRIVE) == 0) 4816 continue; 4817 /* add timing values, setup DMA if needed */ 4818 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4819 (drvp->drive_flags & DRIVE_UDMA)) { 4820 /* use Ultra/DMA */ 4821 if (ACARD_IS_850(sc)) { 4822 idetime |= ATP850_SETTIME(drive, 4823 acard_act_udma[drvp->UDMA_mode], 4824 acard_rec_udma[drvp->UDMA_mode]); 4825 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4826 acard_udma_conf[drvp->UDMA_mode]); 4827 } else { 4828 idetime |= ATP860_SETTIME(channel, drive, 4829 acard_act_udma[drvp->UDMA_mode], 4830 acard_rec_udma[drvp->UDMA_mode]); 4831 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4832 acard_udma_conf[drvp->UDMA_mode]); 4833 } 4834 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4835 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4836 (drvp->drive_flags & DRIVE_DMA)) { 4837 /* use Multiword DMA */ 4838 drvp->drive_flags &= ~DRIVE_UDMA; 4839 if (ACARD_IS_850(sc)) { 4840 idetime |= ATP850_SETTIME(drive, 4841 acard_act_dma[drvp->DMA_mode], 4842 acard_rec_dma[drvp->DMA_mode]); 4843 } else { 4844 idetime |= ATP860_SETTIME(channel, drive, 4845 acard_act_dma[drvp->DMA_mode], 4846 acard_rec_dma[drvp->DMA_mode]); 4847 } 4848 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4849 } else { 4850 /* PIO only */ 4851 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4852 if (ACARD_IS_850(sc)) { 4853 idetime |= ATP850_SETTIME(drive, 4854 acard_act_pio[drvp->PIO_mode], 4855 acard_rec_pio[drvp->PIO_mode]); 4856 } else { 4857 idetime |= ATP860_SETTIME(channel, drive, 4858 acard_act_pio[drvp->PIO_mode], 4859 acard_rec_pio[drvp->PIO_mode]); 4860 } 4861 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4862 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4863 | ATP8x0_CTRL_EN(channel)); 4864 } 4865 } 4866 4867 if (idedma_ctl != 0) { 4868 /* Add software bits in status register */ 4869 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4870 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4871 } 4872 pciide_print_modes(cp); 4873 4874 if (ACARD_IS_850(sc)) { 4875 pci_conf_write(sc->sc_pc, sc->sc_tag, 4876 ATP850_IDETIME(channel), idetime); 4877 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4878 } else { 4879 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4880 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4881 } 4882 } 4883 4884 int 4885 acard_pci_intr(arg) 4886 void *arg; 4887 { 4888 struct pciide_softc *sc = arg; 4889 struct pciide_channel *cp; 4890 struct channel_softc *wdc_cp; 4891 int rv = 0; 4892 int dmastat, i, crv; 4893 4894 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4895 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4896 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4897 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4898 continue; 4899 cp = &sc->pciide_channels[i]; 4900 wdc_cp = &cp->wdc_channel; 4901 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4902 (void)wdcintr(wdc_cp); 4903 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4904 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4905 continue; 4906 } 4907 crv = wdcintr(wdc_cp); 4908 if (crv == 0) 4909 printf("%s:%d: bogus intr\n", 4910 sc->sc_wdcdev.sc_dev.dv_xname, i); 4911 else if (crv == 1) 4912 rv = 1; 4913 else if (rv == 0) 4914 rv = crv; 4915 } 4916 return rv; 4917 } 4918 4919 static int 4920 sl82c105_bugchk(struct pci_attach_args *pa) 4921 { 4922 4923 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 4924 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 4925 return (0); 4926 4927 if (PCI_REVISION(pa->pa_class) <= 0x05) 4928 return (1); 4929 4930 return (0); 4931 } 4932 4933 void 4934 sl82c105_chip_map(sc, pa) 4935 struct pciide_softc *sc; 4936 struct pci_attach_args *pa; 4937 { 4938 struct pciide_channel *cp; 4939 bus_size_t cmdsize, ctlsize; 4940 pcireg_t interface, idecr; 4941 int channel; 4942 4943 if (pciide_chipen(sc, pa) == 0) 4944 return; 4945 4946 printf("%s: bus-master DMA support present", 4947 sc->sc_wdcdev.sc_dev.dv_xname); 4948 4949 /* 4950 * Check to see if we're part of the Winbond 83c553 Southbridge. 4951 * If so, we need to disable DMA on rev. <= 5 of that chip. 4952 */ 4953 if (pci_find_device(pa, sl82c105_bugchk)) { 4954 printf(" but disabled due to 83c553 rev. <= 0x05"); 4955 sc->sc_dma_ok = 0; 4956 } else 4957 pciide_mapreg_dma(sc, pa); 4958 printf("\n"); 4959 4960 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4961 WDC_CAPABILITY_MODE; 4962 sc->sc_wdcdev.PIO_cap = 4; 4963 if (sc->sc_dma_ok) { 4964 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4965 sc->sc_wdcdev.irqack = pciide_irqack; 4966 sc->sc_wdcdev.DMA_cap = 2; 4967 } 4968 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 4969 4970 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4971 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4972 4973 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 4974 4975 interface = PCI_INTERFACE(pa->pa_class); 4976 4977 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4978 cp = &sc->pciide_channels[channel]; 4979 if (pciide_chansetup(sc, channel, interface) == 0) 4980 continue; 4981 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 4982 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 4983 printf("%s: %s channel ignored (disabled)\n", 4984 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4985 continue; 4986 } 4987 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4988 pciide_pci_intr); 4989 if (cp->hw_ok == 0) 4990 continue; 4991 pciide_map_compat_intr(pa, cp, channel, interface); 4992 if (cp->hw_ok == 0) 4993 continue; 4994 sl82c105_setup_channel(&cp->wdc_channel); 4995 } 4996 } 4997 4998 void 4999 sl82c105_setup_channel(chp) 5000 struct channel_softc *chp; 5001 { 5002 struct ata_drive_datas *drvp; 5003 struct pciide_channel *cp = (struct pciide_channel*)chp; 5004 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5005 int pxdx_reg, drive; 5006 pcireg_t pxdx; 5007 5008 /* Set up DMA if needed. */ 5009 pciide_channel_dma_setup(cp); 5010 5011 for (drive = 0; drive < 2; drive++) { 5012 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 5013 : SYMPH_P1D0CR) + (drive * 4); 5014 5015 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 5016 5017 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 5018 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 5019 5020 drvp = &chp->ch_drive[drive]; 5021 /* If no drive, skip. */ 5022 if ((drvp->drive_flags & DRIVE) == 0) { 5023 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 5024 continue; 5025 } 5026 5027 if (drvp->drive_flags & DRIVE_DMA) { 5028 /* 5029 * Timings will be used for both PIO and DMA, 5030 * so adjust DMA mode if needed. 5031 */ 5032 if (drvp->PIO_mode >= 3) { 5033 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 5034 drvp->DMA_mode = drvp->PIO_mode - 2; 5035 if (drvp->DMA_mode < 1) { 5036 /* 5037 * Can't mix both PIO and DMA. 5038 * Disable DMA. 5039 */ 5040 drvp->drive_flags &= ~DRIVE_DMA; 5041 } 5042 } else { 5043 /* 5044 * Can't mix both PIO and DMA. Disable 5045 * DMA. 5046 */ 5047 drvp->drive_flags &= ~DRIVE_DMA; 5048 } 5049 } 5050 5051 if (drvp->drive_flags & DRIVE_DMA) { 5052 /* Use multi-word DMA. */ 5053 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 5054 PxDx_CMD_ON_SHIFT; 5055 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 5056 } else { 5057 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 5058 PxDx_CMD_ON_SHIFT; 5059 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 5060 } 5061 5062 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 5063 5064 /* ...and set the mode for this drive. */ 5065 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 5066 } 5067 5068 pciide_print_modes(cp); 5069 } 5070 5071 void 5072 serverworks_chip_map(sc, pa) 5073 struct pciide_softc *sc; 5074 struct pci_attach_args *pa; 5075 { 5076 struct pciide_channel *cp; 5077 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 5078 pcitag_t pcib_tag; 5079 int channel; 5080 bus_size_t cmdsize, ctlsize; 5081 5082 if (pciide_chipen(sc, pa) == 0) 5083 return; 5084 5085 printf("%s: bus-master DMA support present", 5086 sc->sc_wdcdev.sc_dev.dv_xname); 5087 pciide_mapreg_dma(sc, pa); 5088 printf("\n"); 5089 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5090 WDC_CAPABILITY_MODE; 5091 5092 if (sc->sc_dma_ok) { 5093 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5094 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5095 sc->sc_wdcdev.irqack = pciide_irqack; 5096 } 5097 sc->sc_wdcdev.PIO_cap = 4; 5098 sc->sc_wdcdev.DMA_cap = 2; 5099 switch (sc->sc_pp->ide_product) { 5100 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 5101 sc->sc_wdcdev.UDMA_cap = 2; 5102 break; 5103 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 5104 if (PCI_REVISION(pa->pa_class) < 0x92) 5105 sc->sc_wdcdev.UDMA_cap = 4; 5106 else 5107 sc->sc_wdcdev.UDMA_cap = 5; 5108 break; 5109 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 5110 sc->sc_wdcdev.UDMA_cap = 5; 5111 break; 5112 } 5113 5114 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 5115 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5116 sc->sc_wdcdev.nchannels = 2; 5117 5118 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5119 cp = &sc->pciide_channels[channel]; 5120 if (pciide_chansetup(sc, channel, interface) == 0) 5121 continue; 5122 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5123 serverworks_pci_intr); 5124 if (cp->hw_ok == 0) 5125 return; 5126 pciide_map_compat_intr(pa, cp, channel, interface); 5127 if (cp->hw_ok == 0) 5128 return; 5129 serverworks_setup_channel(&cp->wdc_channel); 5130 } 5131 5132 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 5133 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 5134 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 5135 } 5136 5137 void 5138 serverworks_setup_channel(chp) 5139 struct channel_softc *chp; 5140 { 5141 struct ata_drive_datas *drvp; 5142 struct pciide_channel *cp = (struct pciide_channel*)chp; 5143 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5144 int channel = chp->channel; 5145 int drive, unit; 5146 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 5147 u_int32_t idedma_ctl; 5148 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 5149 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 5150 5151 /* setup DMA if needed */ 5152 pciide_channel_dma_setup(cp); 5153 5154 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 5155 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 5156 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 5157 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 5158 5159 pio_time &= ~(0xffff << (16 * channel)); 5160 dma_time &= ~(0xffff << (16 * channel)); 5161 pio_mode &= ~(0xff << (8 * channel + 16)); 5162 udma_mode &= ~(0xff << (8 * channel + 16)); 5163 udma_mode &= ~(3 << (2 * channel)); 5164 5165 idedma_ctl = 0; 5166 5167 /* Per drive settings */ 5168 for (drive = 0; drive < 2; drive++) { 5169 drvp = &chp->ch_drive[drive]; 5170 /* If no drive, skip */ 5171 if ((drvp->drive_flags & DRIVE) == 0) 5172 continue; 5173 unit = drive + 2 * channel; 5174 /* add timing values, setup DMA if needed */ 5175 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 5176 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 5177 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 5178 (drvp->drive_flags & DRIVE_UDMA)) { 5179 /* use Ultra/DMA, check for 80-pin cable */ 5180 if (drvp->UDMA_mode > 2 && 5181 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 5182 drvp->UDMA_mode = 2; 5183 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 5184 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 5185 udma_mode |= 1 << unit; 5186 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5187 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 5188 (drvp->drive_flags & DRIVE_DMA)) { 5189 /* use Multiword DMA */ 5190 drvp->drive_flags &= ~DRIVE_UDMA; 5191 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 5192 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5193 } else { 5194 /* PIO only */ 5195 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 5196 } 5197 } 5198 5199 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 5200 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 5201 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 5202 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 5203 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 5204 5205 if (idedma_ctl != 0) { 5206 /* Add software bits in status register */ 5207 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5208 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 5209 } 5210 pciide_print_modes(cp); 5211 } 5212 5213 int 5214 serverworks_pci_intr(arg) 5215 void *arg; 5216 { 5217 struct pciide_softc *sc = arg; 5218 struct pciide_channel *cp; 5219 struct channel_softc *wdc_cp; 5220 int rv = 0; 5221 int dmastat, i, crv; 5222 5223 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5224 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5225 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 5226 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 5227 IDEDMA_CTL_INTR) 5228 continue; 5229 cp = &sc->pciide_channels[i]; 5230 wdc_cp = &cp->wdc_channel; 5231 crv = wdcintr(wdc_cp); 5232 if (crv == 0) { 5233 printf("%s:%d: bogus intr\n", 5234 sc->sc_wdcdev.sc_dev.dv_xname, i); 5235 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5236 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 5237 } else 5238 rv = 1; 5239 } 5240 return rv; 5241 } 5242 5243 void 5244 artisea_chip_map(sc, pa) 5245 struct pciide_softc *sc; 5246 struct pci_attach_args *pa; 5247 { 5248 struct pciide_channel *cp; 5249 bus_size_t cmdsize, ctlsize; 5250 pcireg_t interface; 5251 int channel; 5252 5253 if (pciide_chipen(sc, pa) == 0) 5254 return; 5255 5256 printf("%s: bus-master DMA support resent", 5257 sc->sc_wdcdev.sc_dev.dv_xname); 5258 #ifndef PCIIDE_I31244_ENABLEDMA 5259 if (PCI_REVISION(pa->pa_class) == 0) { 5260 printf(" but disabled due to rev. 0"); 5261 sc->sc_dma_ok = 0; 5262 } else 5263 #endif 5264 pciide_mapreg_dma(sc, pa); 5265 printf("\n"); 5266 5267 /* 5268 * XXX Configure LEDs to show activity. 5269 */ 5270 5271 sc->sc_wdcdev.PIO_cap = 4; 5272 if (sc->sc_dma_ok) { 5273 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5274 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5275 sc->sc_wdcdev.irqack = pciide_irqack; 5276 sc->sc_wdcdev.DMA_cap = 2; 5277 sc->sc_wdcdev.UDMA_cap = 6; 5278 } 5279 sc->sc_wdcdev.set_modes = sata_setup_channel; 5280 5281 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5282 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5283 5284 interface = PCI_INTERFACE(pa->pa_class); 5285 5286 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5287 cp = &sc->pciide_channels[channel]; 5288 if (pciide_chansetup(sc, channel, interface) == 0) 5289 continue; 5290 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5291 pciide_pci_intr); 5292 if (cp->hw_ok == 0) 5293 continue; 5294 pciide_map_compat_intr(pa, cp, channel, interface); 5295 sata_setup_channel(&cp->wdc_channel); 5296 } 5297 } 5298
Indexes created Thu Oct 02 10:09:58 GMT 2025