pciide.c revision 1.186
1 /* $NetBSD: pciide.c,v 1.186 2003/03/19 15:13:57 thorpej Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.186 2003/03/19 15:13:57 thorpej Exp $"); 80 81 #ifndef WDCDEBUG 82 #define WDCDEBUG 83 #endif 84 85 #define DEBUG_DMA 0x01 86 #define DEBUG_XFERS 0x02 87 #define DEBUG_FUNCS 0x08 88 #define DEBUG_PROBE 0x10 89 #ifdef WDCDEBUG 90 int wdcdebug_pciide_mask = 0; 91 #define WDCDEBUG_PRINT(args, level) \ 92 if (wdcdebug_pciide_mask & (level)) printf args 93 #else 94 #define WDCDEBUG_PRINT(args, level) 95 #endif 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <machine/endian.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/pciide_sl82c105_reg.h> 122 #include <dev/pci/pciide_i31244_reg.h> 123 #include <dev/pci/cy82c693var.h> 124 125 #include "opt_pciide.h" 126 127 /* inlines for reading/writing 8-bit PCI registers */ 128 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 129 int)); 130 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 131 int, u_int8_t)); 132 133 static __inline u_int8_t 134 pciide_pci_read(pc, pa, reg) 135 pci_chipset_tag_t pc; 136 pcitag_t pa; 137 int reg; 138 { 139 140 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 141 ((reg & 0x03) * 8) & 0xff); 142 } 143 144 static __inline void 145 pciide_pci_write(pc, pa, reg, val) 146 pci_chipset_tag_t pc; 147 pcitag_t pa; 148 int reg; 149 u_int8_t val; 150 { 151 pcireg_t pcival; 152 153 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 154 pcival &= ~(0xff << ((reg & 0x03) * 8)); 155 pcival |= (val << ((reg & 0x03) * 8)); 156 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 157 } 158 159 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 160 161 void sata_setup_channel __P((struct channel_softc*)); 162 163 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 164 void piix_setup_channel __P((struct channel_softc*)); 165 void piix3_4_setup_channel __P((struct channel_softc*)); 166 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 167 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 168 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 169 170 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void amd7x6_setup_channel __P((struct channel_softc*)); 172 173 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void apollo_setup_channel __P((struct channel_softc*)); 175 176 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 177 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void cmd0643_9_setup_channel __P((struct channel_softc*)); 179 void cmd_channel_map __P((struct pci_attach_args *, 180 struct pciide_softc *, int)); 181 int cmd_pci_intr __P((void *)); 182 void cmd646_9_irqack __P((struct channel_softc *)); 183 void cmd680_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 184 void cmd680_setup_channel __P((struct channel_softc*)); 185 void cmd680_channel_map __P((struct pci_attach_args *, 186 struct pciide_softc *, int)); 187 188 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void cy693_setup_channel __P((struct channel_softc*)); 190 191 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 192 void sis_setup_channel __P((struct channel_softc*)); 193 void sis96x_setup_channel __P((struct channel_softc*)); 194 static int sis_hostbr_match __P(( struct pci_attach_args *)); 195 static int sis_south_match __P(( struct pci_attach_args *)); 196 197 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 198 void acer_setup_channel __P((struct channel_softc*)); 199 int acer_pci_intr __P((void *)); 200 201 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 202 void pdc202xx_setup_channel __P((struct channel_softc*)); 203 void pdc20268_setup_channel __P((struct channel_softc*)); 204 int pdc202xx_pci_intr __P((void *)); 205 int pdc20265_pci_intr __P((void *)); 206 207 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 208 void opti_setup_channel __P((struct channel_softc*)); 209 210 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 211 void hpt_setup_channel __P((struct channel_softc*)); 212 int hpt_pci_intr __P((void *)); 213 214 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 215 void acard_setup_channel __P((struct channel_softc*)); 216 int acard_pci_intr __P((void *)); 217 218 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 219 void serverworks_setup_channel __P((struct channel_softc*)); 220 int serverworks_pci_intr __P((void *)); 221 222 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 223 void sl82c105_setup_channel __P((struct channel_softc*)); 224 225 void pciide_channel_dma_setup __P((struct pciide_channel *)); 226 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 227 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 228 void pciide_dma_start __P((void*, int, int)); 229 int pciide_dma_finish __P((void*, int, int, int)); 230 void pciide_irqack __P((struct channel_softc *)); 231 void pciide_print_modes __P((struct pciide_channel *)); 232 233 void artisea_chip_map __P((struct pciide_softc*, struct pci_attach_args *)); 234 235 struct pciide_product_desc { 236 u_int32_t ide_product; 237 int ide_flags; 238 const char *ide_name; 239 /* map and setup chip, probe drives */ 240 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 241 }; 242 243 /* Flags for ide_flags */ 244 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 245 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 246 247 /* Default product description for devices not known from this controller */ 248 const struct pciide_product_desc default_product_desc = { 249 0, 250 0, 251 "Generic PCI IDE controller", 252 default_chip_map, 253 }; 254 255 const struct pciide_product_desc pciide_intel_products[] = { 256 { PCI_PRODUCT_INTEL_82092AA, 257 0, 258 "Intel 82092AA IDE controller", 259 default_chip_map, 260 }, 261 { PCI_PRODUCT_INTEL_82371FB_IDE, 262 0, 263 "Intel 82371FB IDE controller (PIIX)", 264 piix_chip_map, 265 }, 266 { PCI_PRODUCT_INTEL_82371SB_IDE, 267 0, 268 "Intel 82371SB IDE Interface (PIIX3)", 269 piix_chip_map, 270 }, 271 { PCI_PRODUCT_INTEL_82371AB_IDE, 272 0, 273 "Intel 82371AB IDE controller (PIIX4)", 274 piix_chip_map, 275 }, 276 { PCI_PRODUCT_INTEL_82440MX_IDE, 277 0, 278 "Intel 82440MX IDE controller", 279 piix_chip_map 280 }, 281 { PCI_PRODUCT_INTEL_82801AA_IDE, 282 0, 283 "Intel 82801AA IDE Controller (ICH)", 284 piix_chip_map, 285 }, 286 { PCI_PRODUCT_INTEL_82801AB_IDE, 287 0, 288 "Intel 82801AB IDE Controller (ICH0)", 289 piix_chip_map, 290 }, 291 { PCI_PRODUCT_INTEL_82801BA_IDE, 292 0, 293 "Intel 82801BA IDE Controller (ICH2)", 294 piix_chip_map, 295 }, 296 { PCI_PRODUCT_INTEL_82801BAM_IDE, 297 0, 298 "Intel 82801BAM IDE Controller (ICH2)", 299 piix_chip_map, 300 }, 301 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 302 0, 303 "Intel 82801CA IDE Controller", 304 piix_chip_map, 305 }, 306 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 307 0, 308 "Intel 82801CA IDE Controller", 309 piix_chip_map, 310 }, 311 { PCI_PRODUCT_INTEL_82801DB_IDE, 312 0, 313 "Intel 82801DB IDE Controller (ICH4)", 314 piix_chip_map, 315 }, 316 { PCI_PRODUCT_INTEL_31244, 317 0, 318 "Intel 31244 Serial ATA Controller", 319 artisea_chip_map, 320 }, 321 { 0, 322 0, 323 NULL, 324 NULL 325 } 326 }; 327 328 const struct pciide_product_desc pciide_amd_products[] = { 329 { PCI_PRODUCT_AMD_PBC756_IDE, 330 0, 331 "Advanced Micro Devices AMD756 IDE Controller", 332 amd7x6_chip_map 333 }, 334 { PCI_PRODUCT_AMD_PBC766_IDE, 335 0, 336 "Advanced Micro Devices AMD766 IDE Controller", 337 amd7x6_chip_map 338 }, 339 { PCI_PRODUCT_AMD_PBC768_IDE, 340 0, 341 "Advanced Micro Devices AMD768 IDE Controller", 342 amd7x6_chip_map 343 }, 344 { PCI_PRODUCT_AMD_PBC8111_IDE, 345 0, 346 "Advanced Micro Devices AMD8111 IDE Controller", 347 amd7x6_chip_map 348 }, 349 { 0, 350 0, 351 NULL, 352 NULL 353 } 354 }; 355 356 const struct pciide_product_desc pciide_nvidia_products[] = { 357 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 358 0, 359 "NVIDIA nForce IDE Controller", 360 amd7x6_chip_map 361 }, 362 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 363 0, 364 "NVIDIA nForce2 IDE Controller", 365 amd7x6_chip_map 366 }, 367 { 0, 368 0, 369 NULL, 370 NULL 371 } 372 }; 373 374 const struct pciide_product_desc pciide_cmd_products[] = { 375 { PCI_PRODUCT_CMDTECH_640, 376 0, 377 "CMD Technology PCI0640", 378 cmd_chip_map 379 }, 380 { PCI_PRODUCT_CMDTECH_643, 381 0, 382 "CMD Technology PCI0643", 383 cmd0643_9_chip_map, 384 }, 385 { PCI_PRODUCT_CMDTECH_646, 386 0, 387 "CMD Technology PCI0646", 388 cmd0643_9_chip_map, 389 }, 390 { PCI_PRODUCT_CMDTECH_648, 391 IDE_PCI_CLASS_OVERRIDE, 392 "CMD Technology PCI0648", 393 cmd0643_9_chip_map, 394 }, 395 { PCI_PRODUCT_CMDTECH_649, 396 IDE_PCI_CLASS_OVERRIDE, 397 "CMD Technology PCI0649", 398 cmd0643_9_chip_map, 399 }, 400 { PCI_PRODUCT_CMDTECH_680, 401 IDE_PCI_CLASS_OVERRIDE, 402 "Silicon Image 0680", 403 cmd680_chip_map, 404 }, 405 { 0, 406 0, 407 NULL, 408 NULL 409 } 410 }; 411 412 const struct pciide_product_desc pciide_via_products[] = { 413 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 414 0, 415 NULL, 416 apollo_chip_map, 417 }, 418 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 419 0, 420 NULL, 421 apollo_chip_map, 422 }, 423 { 0, 424 0, 425 NULL, 426 NULL 427 } 428 }; 429 430 const struct pciide_product_desc pciide_cypress_products[] = { 431 { PCI_PRODUCT_CONTAQ_82C693, 432 IDE_16BIT_IOSPACE, 433 "Cypress 82C693 IDE Controller", 434 cy693_chip_map, 435 }, 436 { 0, 437 0, 438 NULL, 439 NULL 440 } 441 }; 442 443 const struct pciide_product_desc pciide_sis_products[] = { 444 { PCI_PRODUCT_SIS_5597_IDE, 445 0, 446 NULL, 447 sis_chip_map, 448 }, 449 { 0, 450 0, 451 NULL, 452 NULL 453 } 454 }; 455 456 const struct pciide_product_desc pciide_acer_products[] = { 457 { PCI_PRODUCT_ALI_M5229, 458 0, 459 "Acer Labs M5229 UDMA IDE Controller", 460 acer_chip_map, 461 }, 462 { 0, 463 0, 464 NULL, 465 NULL 466 } 467 }; 468 469 const struct pciide_product_desc pciide_promise_products[] = { 470 { PCI_PRODUCT_PROMISE_ULTRA33, 471 IDE_PCI_CLASS_OVERRIDE, 472 "Promise Ultra33/ATA Bus Master IDE Accelerator", 473 pdc202xx_chip_map, 474 }, 475 { PCI_PRODUCT_PROMISE_ULTRA66, 476 IDE_PCI_CLASS_OVERRIDE, 477 "Promise Ultra66/ATA Bus Master IDE Accelerator", 478 pdc202xx_chip_map, 479 }, 480 { PCI_PRODUCT_PROMISE_ULTRA100, 481 IDE_PCI_CLASS_OVERRIDE, 482 "Promise Ultra100/ATA Bus Master IDE Accelerator", 483 pdc202xx_chip_map, 484 }, 485 { PCI_PRODUCT_PROMISE_ULTRA100X, 486 IDE_PCI_CLASS_OVERRIDE, 487 "Promise Ultra100/ATA Bus Master IDE Accelerator", 488 pdc202xx_chip_map, 489 }, 490 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 491 IDE_PCI_CLASS_OVERRIDE, 492 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 493 pdc202xx_chip_map, 494 }, 495 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 496 IDE_PCI_CLASS_OVERRIDE, 497 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 498 pdc202xx_chip_map, 499 }, 500 { PCI_PRODUCT_PROMISE_ULTRA133, 501 IDE_PCI_CLASS_OVERRIDE, 502 "Promise Ultra133/ATA Bus Master IDE Accelerator", 503 pdc202xx_chip_map, 504 }, 505 { PCI_PRODUCT_PROMISE_ULTRA133TX2, 506 IDE_PCI_CLASS_OVERRIDE, 507 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 508 pdc202xx_chip_map, 509 }, 510 { PCI_PRODUCT_PROMISE_MBULTRA133, 511 IDE_PCI_CLASS_OVERRIDE, 512 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 513 pdc202xx_chip_map, 514 }, 515 { PCI_PRODUCT_PROMISE_ULTRA133TX2v2, 516 IDE_PCI_CLASS_OVERRIDE, 517 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 518 pdc202xx_chip_map, 519 }, 520 { PCI_PRODUCT_PROMISE_FASTTRAK133LITE, 521 IDE_PCI_CLASS_OVERRIDE, 522 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 523 pdc202xx_chip_map, 524 }, 525 { PCI_PRODUCT_PROMISE_SATA150TX2PLUS, 526 IDE_PCI_CLASS_OVERRIDE, 527 "Promise Serial ATA/150 TX2plus Bus Master IDE Accelerator", 528 pdc202xx_chip_map, 529 }, 530 { 0, 531 0, 532 NULL, 533 NULL 534 } 535 }; 536 537 const struct pciide_product_desc pciide_opti_products[] = { 538 { PCI_PRODUCT_OPTI_82C621, 539 0, 540 "OPTi 82c621 PCI IDE controller", 541 opti_chip_map, 542 }, 543 { PCI_PRODUCT_OPTI_82C568, 544 0, 545 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 546 opti_chip_map, 547 }, 548 { PCI_PRODUCT_OPTI_82D568, 549 0, 550 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 551 opti_chip_map, 552 }, 553 { 0, 554 0, 555 NULL, 556 NULL 557 } 558 }; 559 560 const struct pciide_product_desc pciide_triones_products[] = { 561 { PCI_PRODUCT_TRIONES_HPT366, 562 IDE_PCI_CLASS_OVERRIDE, 563 NULL, 564 hpt_chip_map, 565 }, 566 { PCI_PRODUCT_TRIONES_HPT372, 567 IDE_PCI_CLASS_OVERRIDE, 568 NULL, 569 hpt_chip_map 570 }, 571 { PCI_PRODUCT_TRIONES_HPT374, 572 IDE_PCI_CLASS_OVERRIDE, 573 NULL, 574 hpt_chip_map 575 }, 576 { 0, 577 0, 578 NULL, 579 NULL 580 } 581 }; 582 583 const struct pciide_product_desc pciide_acard_products[] = { 584 { PCI_PRODUCT_ACARD_ATP850U, 585 IDE_PCI_CLASS_OVERRIDE, 586 "Acard ATP850U Ultra33 IDE Controller", 587 acard_chip_map, 588 }, 589 { PCI_PRODUCT_ACARD_ATP860, 590 IDE_PCI_CLASS_OVERRIDE, 591 "Acard ATP860 Ultra66 IDE Controller", 592 acard_chip_map, 593 }, 594 { PCI_PRODUCT_ACARD_ATP860A, 595 IDE_PCI_CLASS_OVERRIDE, 596 "Acard ATP860-A Ultra66 IDE Controller", 597 acard_chip_map, 598 }, 599 { 0, 600 0, 601 NULL, 602 NULL 603 } 604 }; 605 606 const struct pciide_product_desc pciide_serverworks_products[] = { 607 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 608 0, 609 "ServerWorks OSB4 IDE Controller", 610 serverworks_chip_map, 611 }, 612 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 613 0, 614 "ServerWorks CSB5 IDE Controller", 615 serverworks_chip_map, 616 }, 617 { PCI_PRODUCT_SERVERWORKS_CSB6_IDE, 618 0, 619 "ServerWorks CSB6 RAID/IDE Controller", 620 serverworks_chip_map, 621 }, 622 { 0, 623 0, 624 NULL, 625 } 626 }; 627 628 const struct pciide_product_desc pciide_symphony_products[] = { 629 { PCI_PRODUCT_SYMPHONY_82C105, 630 0, 631 "Symphony Labs 82C105 IDE controller", 632 sl82c105_chip_map, 633 }, 634 { 0, 635 0, 636 NULL, 637 } 638 }; 639 640 const struct pciide_product_desc pciide_winbond_products[] = { 641 { PCI_PRODUCT_WINBOND_W83C553F_1, 642 0, 643 "Winbond W83C553F IDE controller", 644 sl82c105_chip_map, 645 }, 646 { 0, 647 0, 648 NULL, 649 } 650 }; 651 652 struct pciide_vendor_desc { 653 u_int32_t ide_vendor; 654 const struct pciide_product_desc *ide_products; 655 }; 656 657 const struct pciide_vendor_desc pciide_vendors[] = { 658 { PCI_VENDOR_INTEL, pciide_intel_products }, 659 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 660 { PCI_VENDOR_VIATECH, pciide_via_products }, 661 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 662 { PCI_VENDOR_SIS, pciide_sis_products }, 663 { PCI_VENDOR_ALI, pciide_acer_products }, 664 { PCI_VENDOR_PROMISE, pciide_promise_products }, 665 { PCI_VENDOR_AMD, pciide_amd_products }, 666 { PCI_VENDOR_OPTI, pciide_opti_products }, 667 { PCI_VENDOR_TRIONES, pciide_triones_products }, 668 { PCI_VENDOR_ACARD, pciide_acard_products }, 669 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 670 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 671 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 672 { PCI_VENDOR_NVIDIA, pciide_nvidia_products }, 673 { 0, NULL } 674 }; 675 676 /* options passed via the 'flags' config keyword */ 677 #define PCIIDE_OPTIONS_DMA 0x01 678 #define PCIIDE_OPTIONS_NODMA 0x02 679 680 int pciide_match __P((struct device *, struct cfdata *, void *)); 681 void pciide_attach __P((struct device *, struct device *, void *)); 682 683 CFATTACH_DECL(pciide, sizeof(struct pciide_softc), 684 pciide_match, pciide_attach, NULL, NULL); 685 686 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 687 int pciide_mapregs_compat __P(( struct pci_attach_args *, 688 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 689 int pciide_mapregs_native __P((struct pci_attach_args *, 690 struct pciide_channel *, bus_size_t *, bus_size_t *, 691 int (*pci_intr) __P((void *)))); 692 void pciide_mapreg_dma __P((struct pciide_softc *, 693 struct pci_attach_args *)); 694 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 695 void pciide_mapchan __P((struct pci_attach_args *, 696 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 697 int (*pci_intr) __P((void *)))); 698 int pciide_chan_candisable __P((struct pciide_channel *)); 699 void pciide_map_compat_intr __P(( struct pci_attach_args *, 700 struct pciide_channel *, int, int)); 701 int pciide_compat_intr __P((void *)); 702 int pciide_pci_intr __P((void *)); 703 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 704 705 const struct pciide_product_desc * 706 pciide_lookup_product(id) 707 u_int32_t id; 708 { 709 const struct pciide_product_desc *pp; 710 const struct pciide_vendor_desc *vp; 711 712 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 713 if (PCI_VENDOR(id) == vp->ide_vendor) 714 break; 715 716 if ((pp = vp->ide_products) == NULL) 717 return NULL; 718 719 for (; pp->chip_map != NULL; pp++) 720 if (PCI_PRODUCT(id) == pp->ide_product) 721 break; 722 723 if (pp->chip_map == NULL) 724 return NULL; 725 return pp; 726 } 727 728 int 729 pciide_match(parent, match, aux) 730 struct device *parent; 731 struct cfdata *match; 732 void *aux; 733 { 734 struct pci_attach_args *pa = aux; 735 const struct pciide_product_desc *pp; 736 737 /* 738 * Check the ID register to see that it's a PCI IDE controller. 739 * If it is, we assume that we can deal with it; it _should_ 740 * work in a standardized way... 741 */ 742 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 743 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 744 return (1); 745 } 746 747 /* 748 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 749 * controllers. Let see if we can deal with it anyway. 750 */ 751 pp = pciide_lookup_product(pa->pa_id); 752 if (pp != NULL && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 753 return (1); 754 } 755 756 return (0); 757 } 758 759 void 760 pciide_attach(parent, self, aux) 761 struct device *parent, *self; 762 void *aux; 763 { 764 struct pci_attach_args *pa = aux; 765 pci_chipset_tag_t pc = pa->pa_pc; 766 pcitag_t tag = pa->pa_tag; 767 struct pciide_softc *sc = (struct pciide_softc *)self; 768 pcireg_t csr; 769 char devinfo[256]; 770 const char *displaydev; 771 772 sc->sc_pci_vendor = PCI_VENDOR(pa->pa_id); 773 sc->sc_pp = pciide_lookup_product(pa->pa_id); 774 if (sc->sc_pp == NULL) { 775 sc->sc_pp = &default_product_desc; 776 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 777 displaydev = devinfo; 778 } else 779 displaydev = sc->sc_pp->ide_name; 780 781 /* if displaydev == NULL, printf is done in chip-specific map */ 782 if (displaydev) 783 printf(": %s (rev. 0x%02x)\n", displaydev, 784 PCI_REVISION(pa->pa_class)); 785 786 sc->sc_pc = pa->pa_pc; 787 sc->sc_tag = pa->pa_tag; 788 #ifdef WDCDEBUG 789 if (wdcdebug_pciide_mask & DEBUG_PROBE) 790 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 791 #endif 792 sc->sc_pp->chip_map(sc, pa); 793 794 if (sc->sc_dma_ok) { 795 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 796 csr |= PCI_COMMAND_MASTER_ENABLE; 797 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 798 } 799 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 800 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 801 } 802 803 /* tell whether the chip is enabled or not */ 804 int 805 pciide_chipen(sc, pa) 806 struct pciide_softc *sc; 807 struct pci_attach_args *pa; 808 { 809 pcireg_t csr; 810 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 811 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 812 PCI_COMMAND_STATUS_REG); 813 printf("%s: device disabled (at %s)\n", 814 sc->sc_wdcdev.sc_dev.dv_xname, 815 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 816 "device" : "bridge"); 817 return 0; 818 } 819 return 1; 820 } 821 822 int 823 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 824 struct pci_attach_args *pa; 825 struct pciide_channel *cp; 826 int compatchan; 827 bus_size_t *cmdsizep, *ctlsizep; 828 { 829 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 830 struct channel_softc *wdc_cp = &cp->wdc_channel; 831 832 cp->compat = 1; 833 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 834 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 835 836 wdc_cp->cmd_iot = pa->pa_iot; 837 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 838 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 839 printf("%s: couldn't map %s channel cmd regs\n", 840 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 841 return (0); 842 } 843 844 wdc_cp->ctl_iot = pa->pa_iot; 845 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 846 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 847 printf("%s: couldn't map %s channel ctl regs\n", 848 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 849 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 850 PCIIDE_COMPAT_CMD_SIZE); 851 return (0); 852 } 853 854 return (1); 855 } 856 857 int 858 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 859 struct pci_attach_args * pa; 860 struct pciide_channel *cp; 861 bus_size_t *cmdsizep, *ctlsizep; 862 int (*pci_intr) __P((void *)); 863 { 864 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 865 struct channel_softc *wdc_cp = &cp->wdc_channel; 866 const char *intrstr; 867 pci_intr_handle_t intrhandle; 868 869 cp->compat = 0; 870 871 if (sc->sc_pci_ih == NULL) { 872 if (pci_intr_map(pa, &intrhandle) != 0) { 873 printf("%s: couldn't map native-PCI interrupt\n", 874 sc->sc_wdcdev.sc_dev.dv_xname); 875 return 0; 876 } 877 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 878 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 879 intrhandle, IPL_BIO, pci_intr, sc); 880 if (sc->sc_pci_ih != NULL) { 881 printf("%s: using %s for native-PCI interrupt\n", 882 sc->sc_wdcdev.sc_dev.dv_xname, 883 intrstr ? intrstr : "unknown interrupt"); 884 } else { 885 printf("%s: couldn't establish native-PCI interrupt", 886 sc->sc_wdcdev.sc_dev.dv_xname); 887 if (intrstr != NULL) 888 printf(" at %s", intrstr); 889 printf("\n"); 890 return 0; 891 } 892 } 893 cp->ih = sc->sc_pci_ih; 894 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 895 PCI_MAPREG_TYPE_IO, 0, 896 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 897 printf("%s: couldn't map %s channel cmd regs\n", 898 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 899 return 0; 900 } 901 902 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 903 PCI_MAPREG_TYPE_IO, 0, 904 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 905 printf("%s: couldn't map %s channel ctl regs\n", 906 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 907 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 908 return 0; 909 } 910 /* 911 * In native mode, 4 bytes of I/O space are mapped for the control 912 * register, the control register is at offset 2. Pass the generic 913 * code a handle for only one byte at the right offset. 914 */ 915 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 916 &wdc_cp->ctl_ioh) != 0) { 917 printf("%s: unable to subregion %s channel ctl regs\n", 918 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 919 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 920 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 921 return 0; 922 } 923 return (1); 924 } 925 926 void 927 pciide_mapreg_dma(sc, pa) 928 struct pciide_softc *sc; 929 struct pci_attach_args *pa; 930 { 931 pcireg_t maptype; 932 bus_addr_t addr; 933 934 /* 935 * Map DMA registers 936 * 937 * Note that sc_dma_ok is the right variable to test to see if 938 * DMA can be done. If the interface doesn't support DMA, 939 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 940 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 941 * non-zero if the interface supports DMA and the registers 942 * could be mapped. 943 * 944 * XXX Note that despite the fact that the Bus Master IDE specs 945 * XXX say that "The bus master IDE function uses 16 bytes of IO 946 * XXX space," some controllers (at least the United 947 * XXX Microelectronics UM8886BF) place it in memory space. 948 */ 949 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 950 PCIIDE_REG_BUS_MASTER_DMA); 951 952 switch (maptype) { 953 case PCI_MAPREG_TYPE_IO: 954 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 955 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 956 &addr, NULL, NULL) == 0); 957 if (sc->sc_dma_ok == 0) { 958 printf(", but unused (couldn't query registers)"); 959 break; 960 } 961 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 962 && addr >= 0x10000) { 963 sc->sc_dma_ok = 0; 964 printf(", but unused (registers at unsafe address " 965 "%#lx)", (unsigned long)addr); 966 break; 967 } 968 /* FALLTHROUGH */ 969 970 case PCI_MAPREG_MEM_TYPE_32BIT: 971 sc->sc_dma_ok = (pci_mapreg_map(pa, 972 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 973 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 974 sc->sc_dmat = pa->pa_dmat; 975 if (sc->sc_dma_ok == 0) { 976 printf(", but unused (couldn't map registers)"); 977 } else { 978 sc->sc_wdcdev.dma_arg = sc; 979 sc->sc_wdcdev.dma_init = pciide_dma_init; 980 sc->sc_wdcdev.dma_start = pciide_dma_start; 981 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 982 } 983 984 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 985 PCIIDE_OPTIONS_NODMA) { 986 printf(", but unused (forced off by config file)"); 987 sc->sc_dma_ok = 0; 988 } 989 break; 990 991 default: 992 sc->sc_dma_ok = 0; 993 printf(", but unsupported register maptype (0x%x)", maptype); 994 } 995 } 996 997 int 998 pciide_compat_intr(arg) 999 void *arg; 1000 { 1001 struct pciide_channel *cp = arg; 1002 1003 #ifdef DIAGNOSTIC 1004 /* should only be called for a compat channel */ 1005 if (cp->compat == 0) 1006 panic("pciide compat intr called for non-compat chan %p", cp); 1007 #endif 1008 return (wdcintr(&cp->wdc_channel)); 1009 } 1010 1011 int 1012 pciide_pci_intr(arg) 1013 void *arg; 1014 { 1015 struct pciide_softc *sc = arg; 1016 struct pciide_channel *cp; 1017 struct channel_softc *wdc_cp; 1018 int i, rv, crv; 1019 1020 rv = 0; 1021 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1022 cp = &sc->pciide_channels[i]; 1023 wdc_cp = &cp->wdc_channel; 1024 1025 /* If a compat channel skip. */ 1026 if (cp->compat) 1027 continue; 1028 /* if this channel not waiting for intr, skip */ 1029 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 1030 continue; 1031 1032 crv = wdcintr(wdc_cp); 1033 if (crv == 0) 1034 ; /* leave rv alone */ 1035 else if (crv == 1) 1036 rv = 1; /* claim the intr */ 1037 else if (rv == 0) /* crv should be -1 in this case */ 1038 rv = crv; /* if we've done no better, take it */ 1039 } 1040 return (rv); 1041 } 1042 1043 void 1044 pciide_channel_dma_setup(cp) 1045 struct pciide_channel *cp; 1046 { 1047 int drive; 1048 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1049 struct ata_drive_datas *drvp; 1050 1051 for (drive = 0; drive < 2; drive++) { 1052 drvp = &cp->wdc_channel.ch_drive[drive]; 1053 /* If no drive, skip */ 1054 if ((drvp->drive_flags & DRIVE) == 0) 1055 continue; 1056 /* setup DMA if needed */ 1057 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1058 (drvp->drive_flags & DRIVE_UDMA) == 0) || 1059 sc->sc_dma_ok == 0) { 1060 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1061 continue; 1062 } 1063 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 1064 != 0) { 1065 /* Abort DMA setup */ 1066 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1067 continue; 1068 } 1069 } 1070 } 1071 1072 int 1073 pciide_dma_table_setup(sc, channel, drive) 1074 struct pciide_softc *sc; 1075 int channel, drive; 1076 { 1077 bus_dma_segment_t seg; 1078 int error, rseg; 1079 const bus_size_t dma_table_size = 1080 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1081 struct pciide_dma_maps *dma_maps = 1082 &sc->pciide_channels[channel].dma_maps[drive]; 1083 1084 /* If table was already allocated, just return */ 1085 if (dma_maps->dma_table) 1086 return 0; 1087 1088 /* Allocate memory for the DMA tables and map it */ 1089 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1090 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1091 BUS_DMA_NOWAIT)) != 0) { 1092 printf("%s:%d: unable to allocate table DMA for " 1093 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1094 channel, drive, error); 1095 return error; 1096 } 1097 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1098 dma_table_size, 1099 (caddr_t *)&dma_maps->dma_table, 1100 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1101 printf("%s:%d: unable to map table DMA for" 1102 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1103 channel, drive, error); 1104 return error; 1105 } 1106 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1107 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1108 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1109 1110 /* Create and load table DMA map for this disk */ 1111 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1112 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1113 &dma_maps->dmamap_table)) != 0) { 1114 printf("%s:%d: unable to create table DMA map for " 1115 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1116 channel, drive, error); 1117 return error; 1118 } 1119 if ((error = bus_dmamap_load(sc->sc_dmat, 1120 dma_maps->dmamap_table, 1121 dma_maps->dma_table, 1122 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1123 printf("%s:%d: unable to load table DMA map for " 1124 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1125 channel, drive, error); 1126 return error; 1127 } 1128 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1129 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1130 DEBUG_PROBE); 1131 /* Create a xfer DMA map for this drive */ 1132 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1133 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1134 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1135 &dma_maps->dmamap_xfer)) != 0) { 1136 printf("%s:%d: unable to create xfer DMA map for " 1137 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1138 channel, drive, error); 1139 return error; 1140 } 1141 return 0; 1142 } 1143 1144 int 1145 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1146 void *v; 1147 int channel, drive; 1148 void *databuf; 1149 size_t datalen; 1150 int flags; 1151 { 1152 struct pciide_softc *sc = v; 1153 int error, seg; 1154 struct pciide_dma_maps *dma_maps = 1155 &sc->pciide_channels[channel].dma_maps[drive]; 1156 1157 error = bus_dmamap_load(sc->sc_dmat, 1158 dma_maps->dmamap_xfer, 1159 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1160 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1161 if (error) { 1162 printf("%s:%d: unable to load xfer DMA map for" 1163 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1164 channel, drive, error); 1165 return error; 1166 } 1167 1168 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1169 dma_maps->dmamap_xfer->dm_mapsize, 1170 (flags & WDC_DMA_READ) ? 1171 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1172 1173 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1174 #ifdef DIAGNOSTIC 1175 /* A segment must not cross a 64k boundary */ 1176 { 1177 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1178 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1179 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1180 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1181 printf("pciide_dma: segment %d physical addr 0x%lx" 1182 " len 0x%lx not properly aligned\n", 1183 seg, phys, len); 1184 panic("pciide_dma: buf align"); 1185 } 1186 } 1187 #endif 1188 dma_maps->dma_table[seg].base_addr = 1189 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1190 dma_maps->dma_table[seg].byte_count = 1191 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1192 IDEDMA_BYTE_COUNT_MASK); 1193 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1194 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1195 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1196 1197 } 1198 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1199 htole32(IDEDMA_BYTE_COUNT_EOT); 1200 1201 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1202 dma_maps->dmamap_table->dm_mapsize, 1203 BUS_DMASYNC_PREWRITE); 1204 1205 /* Maps are ready. Start DMA function */ 1206 #ifdef DIAGNOSTIC 1207 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1208 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1209 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1210 panic("pciide_dma_init: table align"); 1211 } 1212 #endif 1213 1214 /* Clear status bits */ 1215 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1216 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1217 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1218 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1219 /* Write table addr */ 1220 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1221 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1222 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1223 /* set read/write */ 1224 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1225 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1226 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1227 /* remember flags */ 1228 dma_maps->dma_flags = flags; 1229 return 0; 1230 } 1231 1232 void 1233 pciide_dma_start(v, channel, drive) 1234 void *v; 1235 int channel, drive; 1236 { 1237 struct pciide_softc *sc = v; 1238 1239 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1240 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1241 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1242 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1243 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1244 } 1245 1246 int 1247 pciide_dma_finish(v, channel, drive, force) 1248 void *v; 1249 int channel, drive; 1250 int force; 1251 { 1252 struct pciide_softc *sc = v; 1253 u_int8_t status; 1254 int error = 0; 1255 struct pciide_dma_maps *dma_maps = 1256 &sc->pciide_channels[channel].dma_maps[drive]; 1257 1258 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1259 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1260 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1261 DEBUG_XFERS); 1262 1263 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1264 return WDC_DMAST_NOIRQ; 1265 1266 /* stop DMA channel */ 1267 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1268 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1269 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1270 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1271 1272 /* Unload the map of the data buffer */ 1273 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1274 dma_maps->dmamap_xfer->dm_mapsize, 1275 (dma_maps->dma_flags & WDC_DMA_READ) ? 1276 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1277 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1278 1279 if ((status & IDEDMA_CTL_ERR) != 0) { 1280 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1281 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1282 error |= WDC_DMAST_ERR; 1283 } 1284 1285 if ((status & IDEDMA_CTL_INTR) == 0) { 1286 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1287 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1288 drive, status); 1289 error |= WDC_DMAST_NOIRQ; 1290 } 1291 1292 if ((status & IDEDMA_CTL_ACT) != 0) { 1293 /* data underrun, may be a valid condition for ATAPI */ 1294 error |= WDC_DMAST_UNDER; 1295 } 1296 return error; 1297 } 1298 1299 void 1300 pciide_irqack(chp) 1301 struct channel_softc *chp; 1302 { 1303 struct pciide_channel *cp = (struct pciide_channel*)chp; 1304 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1305 1306 /* clear status bits in IDE DMA registers */ 1307 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1308 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1309 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1310 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1311 } 1312 1313 /* some common code used by several chip_map */ 1314 int 1315 pciide_chansetup(sc, channel, interface) 1316 struct pciide_softc *sc; 1317 int channel; 1318 pcireg_t interface; 1319 { 1320 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1321 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1322 cp->name = PCIIDE_CHANNEL_NAME(channel); 1323 cp->wdc_channel.channel = channel; 1324 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1325 cp->wdc_channel.ch_queue = 1326 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1327 if (cp->wdc_channel.ch_queue == NULL) { 1328 printf("%s %s channel: " 1329 "can't allocate memory for command queue", 1330 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1331 return 0; 1332 } 1333 printf("%s: %s channel %s to %s mode\n", 1334 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1335 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1336 "configured" : "wired", 1337 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1338 "native-PCI" : "compatibility"); 1339 return 1; 1340 } 1341 1342 /* some common code used by several chip channel_map */ 1343 void 1344 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1345 struct pci_attach_args *pa; 1346 struct pciide_channel *cp; 1347 pcireg_t interface; 1348 bus_size_t *cmdsizep, *ctlsizep; 1349 int (*pci_intr) __P((void *)); 1350 { 1351 struct channel_softc *wdc_cp = &cp->wdc_channel; 1352 1353 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1354 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1355 pci_intr); 1356 else 1357 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1358 wdc_cp->channel, cmdsizep, ctlsizep); 1359 1360 if (cp->hw_ok == 0) 1361 return; 1362 wdc_cp->data32iot = wdc_cp->cmd_iot; 1363 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1364 wdcattach(wdc_cp); 1365 } 1366 1367 /* 1368 * Generic code to call to know if a channel can be disabled. Return 1 1369 * if channel can be disabled, 0 if not 1370 */ 1371 int 1372 pciide_chan_candisable(cp) 1373 struct pciide_channel *cp; 1374 { 1375 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1376 struct channel_softc *wdc_cp = &cp->wdc_channel; 1377 1378 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1379 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1380 printf("%s: disabling %s channel (no drives)\n", 1381 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1382 cp->hw_ok = 0; 1383 return 1; 1384 } 1385 return 0; 1386 } 1387 1388 /* 1389 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1390 * Set hw_ok=0 on failure 1391 */ 1392 void 1393 pciide_map_compat_intr(pa, cp, compatchan, interface) 1394 struct pci_attach_args *pa; 1395 struct pciide_channel *cp; 1396 int compatchan, interface; 1397 { 1398 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1399 struct channel_softc *wdc_cp = &cp->wdc_channel; 1400 1401 if (cp->hw_ok == 0) 1402 return; 1403 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1404 return; 1405 1406 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1407 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1408 pa, compatchan, pciide_compat_intr, cp); 1409 if (cp->ih == NULL) { 1410 #endif 1411 printf("%s: no compatibility interrupt for use by %s " 1412 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1413 cp->hw_ok = 0; 1414 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1415 } 1416 #endif 1417 } 1418 1419 void 1420 pciide_print_modes(cp) 1421 struct pciide_channel *cp; 1422 { 1423 wdc_print_modes(&cp->wdc_channel); 1424 } 1425 1426 void 1427 default_chip_map(sc, pa) 1428 struct pciide_softc *sc; 1429 struct pci_attach_args *pa; 1430 { 1431 struct pciide_channel *cp; 1432 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1433 pcireg_t csr; 1434 int channel, drive; 1435 struct ata_drive_datas *drvp; 1436 u_int8_t idedma_ctl; 1437 bus_size_t cmdsize, ctlsize; 1438 char *failreason; 1439 1440 if (pciide_chipen(sc, pa) == 0) 1441 return; 1442 1443 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1444 printf("%s: bus-master DMA support present", 1445 sc->sc_wdcdev.sc_dev.dv_xname); 1446 if (sc->sc_pp == &default_product_desc && 1447 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1448 PCIIDE_OPTIONS_DMA) == 0) { 1449 printf(", but unused (no driver support)"); 1450 sc->sc_dma_ok = 0; 1451 } else { 1452 pciide_mapreg_dma(sc, pa); 1453 if (sc->sc_dma_ok != 0) 1454 printf(", used without full driver " 1455 "support"); 1456 } 1457 } else { 1458 printf("%s: hardware does not support DMA", 1459 sc->sc_wdcdev.sc_dev.dv_xname); 1460 sc->sc_dma_ok = 0; 1461 } 1462 printf("\n"); 1463 if (sc->sc_dma_ok) { 1464 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1465 sc->sc_wdcdev.irqack = pciide_irqack; 1466 } 1467 sc->sc_wdcdev.PIO_cap = 0; 1468 sc->sc_wdcdev.DMA_cap = 0; 1469 1470 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1471 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1472 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1473 1474 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1475 cp = &sc->pciide_channels[channel]; 1476 if (pciide_chansetup(sc, channel, interface) == 0) 1477 continue; 1478 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1479 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1480 &ctlsize, pciide_pci_intr); 1481 } else { 1482 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1483 channel, &cmdsize, &ctlsize); 1484 } 1485 if (cp->hw_ok == 0) 1486 continue; 1487 /* 1488 * Check to see if something appears to be there. 1489 */ 1490 failreason = NULL; 1491 if (!wdcprobe(&cp->wdc_channel)) { 1492 failreason = "not responding; disabled or no drives?"; 1493 goto next; 1494 } 1495 /* 1496 * Now, make sure it's actually attributable to this PCI IDE 1497 * channel by trying to access the channel again while the 1498 * PCI IDE controller's I/O space is disabled. (If the 1499 * channel no longer appears to be there, it belongs to 1500 * this controller.) YUCK! 1501 */ 1502 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1503 PCI_COMMAND_STATUS_REG); 1504 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1505 csr & ~PCI_COMMAND_IO_ENABLE); 1506 if (wdcprobe(&cp->wdc_channel)) 1507 failreason = "other hardware responding at addresses"; 1508 pci_conf_write(sc->sc_pc, sc->sc_tag, 1509 PCI_COMMAND_STATUS_REG, csr); 1510 next: 1511 if (failreason) { 1512 printf("%s: %s channel ignored (%s)\n", 1513 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1514 failreason); 1515 cp->hw_ok = 0; 1516 bus_space_unmap(cp->wdc_channel.cmd_iot, 1517 cp->wdc_channel.cmd_ioh, cmdsize); 1518 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1519 bus_space_unmap(cp->wdc_channel.ctl_iot, 1520 cp->ctl_baseioh, ctlsize); 1521 else 1522 bus_space_unmap(cp->wdc_channel.ctl_iot, 1523 cp->wdc_channel.ctl_ioh, ctlsize); 1524 } else { 1525 pciide_map_compat_intr(pa, cp, channel, interface); 1526 } 1527 if (cp->hw_ok) { 1528 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1529 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1530 wdcattach(&cp->wdc_channel); 1531 } 1532 } 1533 1534 if (sc->sc_dma_ok == 0) 1535 return; 1536 1537 /* Allocate DMA maps */ 1538 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1539 idedma_ctl = 0; 1540 cp = &sc->pciide_channels[channel]; 1541 for (drive = 0; drive < 2; drive++) { 1542 drvp = &cp->wdc_channel.ch_drive[drive]; 1543 /* If no drive, skip */ 1544 if ((drvp->drive_flags & DRIVE) == 0) 1545 continue; 1546 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1547 continue; 1548 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1549 /* Abort DMA setup */ 1550 printf("%s:%d:%d: can't allocate DMA maps, " 1551 "using PIO transfers\n", 1552 sc->sc_wdcdev.sc_dev.dv_xname, 1553 channel, drive); 1554 drvp->drive_flags &= ~DRIVE_DMA; 1555 } 1556 printf("%s:%d:%d: using DMA data transfers\n", 1557 sc->sc_wdcdev.sc_dev.dv_xname, 1558 channel, drive); 1559 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1560 } 1561 if (idedma_ctl != 0) { 1562 /* Add software bits in status register */ 1563 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1564 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1565 idedma_ctl); 1566 } 1567 } 1568 } 1569 1570 void 1571 sata_setup_channel(chp) 1572 struct channel_softc *chp; 1573 { 1574 struct ata_drive_datas *drvp; 1575 int drive; 1576 u_int32_t idedma_ctl; 1577 struct pciide_channel *cp = (struct pciide_channel*)chp; 1578 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 1579 1580 /* setup DMA if needed */ 1581 pciide_channel_dma_setup(cp); 1582 1583 idedma_ctl = 0; 1584 1585 for (drive = 0; drive < 2; drive++) { 1586 drvp = &chp->ch_drive[drive]; 1587 /* If no drive, skip */ 1588 if ((drvp->drive_flags & DRIVE) == 0) 1589 continue; 1590 if (drvp->drive_flags & DRIVE_UDMA) { 1591 /* use Ultra/DMA */ 1592 drvp->drive_flags &= ~DRIVE_DMA; 1593 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1594 } else if (drvp->drive_flags & DRIVE_DMA) { 1595 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1596 } 1597 } 1598 1599 /* 1600 * Nothing to do to setup modes; it is meaningless in S-ATA 1601 * (but many S-ATA drives still want to get the SET_FEATURE 1602 * command). 1603 */ 1604 if (idedma_ctl != 0) { 1605 /* Add software bits in status register */ 1606 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1607 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1608 idedma_ctl); 1609 } 1610 pciide_print_modes(cp); 1611 } 1612 1613 void 1614 piix_chip_map(sc, pa) 1615 struct pciide_softc *sc; 1616 struct pci_attach_args *pa; 1617 { 1618 struct pciide_channel *cp; 1619 int channel; 1620 u_int32_t idetim; 1621 bus_size_t cmdsize, ctlsize; 1622 1623 if (pciide_chipen(sc, pa) == 0) 1624 return; 1625 1626 printf("%s: bus-master DMA support present", 1627 sc->sc_wdcdev.sc_dev.dv_xname); 1628 pciide_mapreg_dma(sc, pa); 1629 printf("\n"); 1630 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1631 WDC_CAPABILITY_MODE; 1632 if (sc->sc_dma_ok) { 1633 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1634 sc->sc_wdcdev.irqack = pciide_irqack; 1635 switch(sc->sc_pp->ide_product) { 1636 case PCI_PRODUCT_INTEL_82371AB_IDE: 1637 case PCI_PRODUCT_INTEL_82440MX_IDE: 1638 case PCI_PRODUCT_INTEL_82801AA_IDE: 1639 case PCI_PRODUCT_INTEL_82801AB_IDE: 1640 case PCI_PRODUCT_INTEL_82801BA_IDE: 1641 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1642 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1643 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1644 case PCI_PRODUCT_INTEL_82801DB_IDE: 1645 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1646 } 1647 } 1648 sc->sc_wdcdev.PIO_cap = 4; 1649 sc->sc_wdcdev.DMA_cap = 2; 1650 switch(sc->sc_pp->ide_product) { 1651 case PCI_PRODUCT_INTEL_82801AA_IDE: 1652 sc->sc_wdcdev.UDMA_cap = 4; 1653 break; 1654 case PCI_PRODUCT_INTEL_82801BA_IDE: 1655 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1656 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1657 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1658 case PCI_PRODUCT_INTEL_82801DB_IDE: 1659 sc->sc_wdcdev.UDMA_cap = 5; 1660 break; 1661 default: 1662 sc->sc_wdcdev.UDMA_cap = 2; 1663 } 1664 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1665 sc->sc_wdcdev.set_modes = piix_setup_channel; 1666 else 1667 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1668 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1669 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1670 1671 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1672 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1673 DEBUG_PROBE); 1674 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1675 WDCDEBUG_PRINT((", sidetim=0x%x", 1676 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1677 DEBUG_PROBE); 1678 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1679 WDCDEBUG_PRINT((", udamreg 0x%x", 1680 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1681 DEBUG_PROBE); 1682 } 1683 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1684 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1685 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1686 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1687 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1688 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1689 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1690 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1691 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1692 DEBUG_PROBE); 1693 } 1694 1695 } 1696 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1697 1698 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1699 cp = &sc->pciide_channels[channel]; 1700 /* PIIX is compat-only */ 1701 if (pciide_chansetup(sc, channel, 0) == 0) 1702 continue; 1703 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1704 if ((PIIX_IDETIM_READ(idetim, channel) & 1705 PIIX_IDETIM_IDE) == 0) { 1706 printf("%s: %s channel ignored (disabled)\n", 1707 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1708 continue; 1709 } 1710 /* PIIX are compat-only pciide devices */ 1711 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1712 if (cp->hw_ok == 0) 1713 continue; 1714 if (pciide_chan_candisable(cp)) { 1715 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1716 channel); 1717 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1718 idetim); 1719 } 1720 pciide_map_compat_intr(pa, cp, channel, 0); 1721 if (cp->hw_ok == 0) 1722 continue; 1723 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1724 } 1725 1726 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1727 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1728 DEBUG_PROBE); 1729 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1730 WDCDEBUG_PRINT((", sidetim=0x%x", 1731 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1732 DEBUG_PROBE); 1733 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1734 WDCDEBUG_PRINT((", udamreg 0x%x", 1735 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1736 DEBUG_PROBE); 1737 } 1738 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1739 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1740 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1741 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1742 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1743 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1744 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1745 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1746 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1747 DEBUG_PROBE); 1748 } 1749 } 1750 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1751 } 1752 1753 void 1754 piix_setup_channel(chp) 1755 struct channel_softc *chp; 1756 { 1757 u_int8_t mode[2], drive; 1758 u_int32_t oidetim, idetim, idedma_ctl; 1759 struct pciide_channel *cp = (struct pciide_channel*)chp; 1760 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1761 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1762 1763 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1764 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1765 idedma_ctl = 0; 1766 1767 /* set up new idetim: Enable IDE registers decode */ 1768 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1769 chp->channel); 1770 1771 /* setup DMA */ 1772 pciide_channel_dma_setup(cp); 1773 1774 /* 1775 * Here we have to mess up with drives mode: PIIX can't have 1776 * different timings for master and slave drives. 1777 * We need to find the best combination. 1778 */ 1779 1780 /* If both drives supports DMA, take the lower mode */ 1781 if ((drvp[0].drive_flags & DRIVE_DMA) && 1782 (drvp[1].drive_flags & DRIVE_DMA)) { 1783 mode[0] = mode[1] = 1784 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1785 drvp[0].DMA_mode = mode[0]; 1786 drvp[1].DMA_mode = mode[1]; 1787 goto ok; 1788 } 1789 /* 1790 * If only one drive supports DMA, use its mode, and 1791 * put the other one in PIO mode 0 if mode not compatible 1792 */ 1793 if (drvp[0].drive_flags & DRIVE_DMA) { 1794 mode[0] = drvp[0].DMA_mode; 1795 mode[1] = drvp[1].PIO_mode; 1796 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1797 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1798 mode[1] = drvp[1].PIO_mode = 0; 1799 goto ok; 1800 } 1801 if (drvp[1].drive_flags & DRIVE_DMA) { 1802 mode[1] = drvp[1].DMA_mode; 1803 mode[0] = drvp[0].PIO_mode; 1804 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1805 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1806 mode[0] = drvp[0].PIO_mode = 0; 1807 goto ok; 1808 } 1809 /* 1810 * If both drives are not DMA, takes the lower mode, unless 1811 * one of them is PIO mode < 2 1812 */ 1813 if (drvp[0].PIO_mode < 2) { 1814 mode[0] = drvp[0].PIO_mode = 0; 1815 mode[1] = drvp[1].PIO_mode; 1816 } else if (drvp[1].PIO_mode < 2) { 1817 mode[1] = drvp[1].PIO_mode = 0; 1818 mode[0] = drvp[0].PIO_mode; 1819 } else { 1820 mode[0] = mode[1] = 1821 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1822 drvp[0].PIO_mode = mode[0]; 1823 drvp[1].PIO_mode = mode[1]; 1824 } 1825 ok: /* The modes are setup */ 1826 for (drive = 0; drive < 2; drive++) { 1827 if (drvp[drive].drive_flags & DRIVE_DMA) { 1828 idetim |= piix_setup_idetim_timings( 1829 mode[drive], 1, chp->channel); 1830 goto end; 1831 } 1832 } 1833 /* If we are there, none of the drives are DMA */ 1834 if (mode[0] >= 2) 1835 idetim |= piix_setup_idetim_timings( 1836 mode[0], 0, chp->channel); 1837 else 1838 idetim |= piix_setup_idetim_timings( 1839 mode[1], 0, chp->channel); 1840 end: /* 1841 * timing mode is now set up in the controller. Enable 1842 * it per-drive 1843 */ 1844 for (drive = 0; drive < 2; drive++) { 1845 /* If no drive, skip */ 1846 if ((drvp[drive].drive_flags & DRIVE) == 0) 1847 continue; 1848 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1849 if (drvp[drive].drive_flags & DRIVE_DMA) 1850 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1851 } 1852 if (idedma_ctl != 0) { 1853 /* Add software bits in status register */ 1854 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1855 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1856 idedma_ctl); 1857 } 1858 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1859 pciide_print_modes(cp); 1860 } 1861 1862 void 1863 piix3_4_setup_channel(chp) 1864 struct channel_softc *chp; 1865 { 1866 struct ata_drive_datas *drvp; 1867 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1868 struct pciide_channel *cp = (struct pciide_channel*)chp; 1869 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1870 int drive; 1871 int channel = chp->channel; 1872 1873 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1874 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1875 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1876 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1877 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1878 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1879 PIIX_SIDETIM_RTC_MASK(channel)); 1880 1881 idedma_ctl = 0; 1882 /* If channel disabled, no need to go further */ 1883 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1884 return; 1885 /* set up new idetim: Enable IDE registers decode */ 1886 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1887 1888 /* setup DMA if needed */ 1889 pciide_channel_dma_setup(cp); 1890 1891 for (drive = 0; drive < 2; drive++) { 1892 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1893 PIIX_UDMATIM_SET(0x3, channel, drive)); 1894 drvp = &chp->ch_drive[drive]; 1895 /* If no drive, skip */ 1896 if ((drvp->drive_flags & DRIVE) == 0) 1897 continue; 1898 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1899 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1900 goto pio; 1901 1902 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1903 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1904 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1905 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1906 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1907 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1908 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1909 ideconf |= PIIX_CONFIG_PINGPONG; 1910 } 1911 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1912 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1913 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1914 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1915 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1916 /* setup Ultra/100 */ 1917 if (drvp->UDMA_mode > 2 && 1918 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1919 drvp->UDMA_mode = 2; 1920 if (drvp->UDMA_mode > 4) { 1921 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1922 } else { 1923 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1924 if (drvp->UDMA_mode > 2) { 1925 ideconf |= PIIX_CONFIG_UDMA66(channel, 1926 drive); 1927 } else { 1928 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1929 drive); 1930 } 1931 } 1932 } 1933 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1934 /* setup Ultra/66 */ 1935 if (drvp->UDMA_mode > 2 && 1936 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1937 drvp->UDMA_mode = 2; 1938 if (drvp->UDMA_mode > 2) 1939 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1940 else 1941 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1942 } 1943 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1944 (drvp->drive_flags & DRIVE_UDMA)) { 1945 /* use Ultra/DMA */ 1946 drvp->drive_flags &= ~DRIVE_DMA; 1947 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1948 udmareg |= PIIX_UDMATIM_SET( 1949 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1950 } else { 1951 /* use Multiword DMA */ 1952 drvp->drive_flags &= ~DRIVE_UDMA; 1953 if (drive == 0) { 1954 idetim |= piix_setup_idetim_timings( 1955 drvp->DMA_mode, 1, channel); 1956 } else { 1957 sidetim |= piix_setup_sidetim_timings( 1958 drvp->DMA_mode, 1, channel); 1959 idetim =PIIX_IDETIM_SET(idetim, 1960 PIIX_IDETIM_SITRE, channel); 1961 } 1962 } 1963 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1964 1965 pio: /* use PIO mode */ 1966 idetim |= piix_setup_idetim_drvs(drvp); 1967 if (drive == 0) { 1968 idetim |= piix_setup_idetim_timings( 1969 drvp->PIO_mode, 0, channel); 1970 } else { 1971 sidetim |= piix_setup_sidetim_timings( 1972 drvp->PIO_mode, 0, channel); 1973 idetim =PIIX_IDETIM_SET(idetim, 1974 PIIX_IDETIM_SITRE, channel); 1975 } 1976 } 1977 if (idedma_ctl != 0) { 1978 /* Add software bits in status register */ 1979 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1980 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1981 idedma_ctl); 1982 } 1983 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1984 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1985 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1986 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1987 pciide_print_modes(cp); 1988 } 1989 1990 1991 /* setup ISP and RTC fields, based on mode */ 1992 static u_int32_t 1993 piix_setup_idetim_timings(mode, dma, channel) 1994 u_int8_t mode; 1995 u_int8_t dma; 1996 u_int8_t channel; 1997 { 1998 1999 if (dma) 2000 return PIIX_IDETIM_SET(0, 2001 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 2002 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 2003 channel); 2004 else 2005 return PIIX_IDETIM_SET(0, 2006 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 2007 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 2008 channel); 2009 } 2010 2011 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 2012 static u_int32_t 2013 piix_setup_idetim_drvs(drvp) 2014 struct ata_drive_datas *drvp; 2015 { 2016 u_int32_t ret = 0; 2017 struct channel_softc *chp = drvp->chnl_softc; 2018 u_int8_t channel = chp->channel; 2019 u_int8_t drive = drvp->drive; 2020 2021 /* 2022 * If drive is using UDMA, timings setups are independant 2023 * So just check DMA and PIO here. 2024 */ 2025 if (drvp->drive_flags & DRIVE_DMA) { 2026 /* if mode = DMA mode 0, use compatible timings */ 2027 if ((drvp->drive_flags & DRIVE_DMA) && 2028 drvp->DMA_mode == 0) { 2029 drvp->PIO_mode = 0; 2030 return ret; 2031 } 2032 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2033 /* 2034 * PIO and DMA timings are the same, use fast timings for PIO 2035 * too, else use compat timings. 2036 */ 2037 if ((piix_isp_pio[drvp->PIO_mode] != 2038 piix_isp_dma[drvp->DMA_mode]) || 2039 (piix_rtc_pio[drvp->PIO_mode] != 2040 piix_rtc_dma[drvp->DMA_mode])) 2041 drvp->PIO_mode = 0; 2042 /* if PIO mode <= 2, use compat timings for PIO */ 2043 if (drvp->PIO_mode <= 2) { 2044 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 2045 channel); 2046 return ret; 2047 } 2048 } 2049 2050 /* 2051 * Now setup PIO modes. If mode < 2, use compat timings. 2052 * Else enable fast timings. Enable IORDY and prefetch/post 2053 * if PIO mode >= 3. 2054 */ 2055 2056 if (drvp->PIO_mode < 2) 2057 return ret; 2058 2059 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2060 if (drvp->PIO_mode >= 3) { 2061 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 2062 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 2063 } 2064 return ret; 2065 } 2066 2067 /* setup values in SIDETIM registers, based on mode */ 2068 static u_int32_t 2069 piix_setup_sidetim_timings(mode, dma, channel) 2070 u_int8_t mode; 2071 u_int8_t dma; 2072 u_int8_t channel; 2073 { 2074 if (dma) 2075 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 2076 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 2077 else 2078 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 2079 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 2080 } 2081 2082 void 2083 amd7x6_chip_map(sc, pa) 2084 struct pciide_softc *sc; 2085 struct pci_attach_args *pa; 2086 { 2087 struct pciide_channel *cp; 2088 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2089 int channel; 2090 pcireg_t chanenable; 2091 bus_size_t cmdsize, ctlsize; 2092 2093 if (pciide_chipen(sc, pa) == 0) 2094 return; 2095 printf("%s: bus-master DMA support present", 2096 sc->sc_wdcdev.sc_dev.dv_xname); 2097 pciide_mapreg_dma(sc, pa); 2098 printf("\n"); 2099 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2100 WDC_CAPABILITY_MODE; 2101 if (sc->sc_dma_ok) { 2102 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2103 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2104 sc->sc_wdcdev.irqack = pciide_irqack; 2105 } 2106 sc->sc_wdcdev.PIO_cap = 4; 2107 sc->sc_wdcdev.DMA_cap = 2; 2108 2109 switch (sc->sc_pci_vendor) { 2110 case PCI_VENDOR_AMD: 2111 switch (sc->sc_pp->ide_product) { 2112 case PCI_PRODUCT_AMD_PBC766_IDE: 2113 case PCI_PRODUCT_AMD_PBC768_IDE: 2114 case PCI_PRODUCT_AMD_PBC8111_IDE: 2115 sc->sc_wdcdev.UDMA_cap = 5; 2116 break; 2117 default: 2118 sc->sc_wdcdev.UDMA_cap = 4; 2119 } 2120 sc->sc_amd_regbase = AMD7X6_AMD_REGBASE; 2121 break; 2122 2123 case PCI_VENDOR_NVIDIA: 2124 switch (sc->sc_pp->ide_product) { 2125 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 2126 sc->sc_wdcdev.UDMA_cap = 5; 2127 break; 2128 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 2129 sc->sc_wdcdev.UDMA_cap = 6; 2130 break; 2131 } 2132 sc->sc_amd_regbase = AMD7X6_NVIDIA_REGBASE; 2133 break; 2134 2135 default: 2136 panic("amd7x6_chip_map: unknown vendor"); 2137 } 2138 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 2139 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2140 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2141 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, 2142 AMD7X6_CHANSTATUS_EN(sc)); 2143 2144 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 2145 DEBUG_PROBE); 2146 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2147 cp = &sc->pciide_channels[channel]; 2148 if (pciide_chansetup(sc, channel, interface) == 0) 2149 continue; 2150 2151 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 2152 printf("%s: %s channel ignored (disabled)\n", 2153 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2154 continue; 2155 } 2156 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2157 pciide_pci_intr); 2158 2159 if (pciide_chan_candisable(cp)) 2160 chanenable &= ~AMD7X6_CHAN_EN(channel); 2161 pciide_map_compat_intr(pa, cp, channel, interface); 2162 if (cp->hw_ok == 0) 2163 continue; 2164 2165 amd7x6_setup_channel(&cp->wdc_channel); 2166 } 2167 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN(sc), 2168 chanenable); 2169 return; 2170 } 2171 2172 void 2173 amd7x6_setup_channel(chp) 2174 struct channel_softc *chp; 2175 { 2176 u_int32_t udmatim_reg, datatim_reg; 2177 u_int8_t idedma_ctl; 2178 int mode, drive; 2179 struct ata_drive_datas *drvp; 2180 struct pciide_channel *cp = (struct pciide_channel*)chp; 2181 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2182 #ifndef PCIIDE_AMD756_ENABLEDMA 2183 int rev = PCI_REVISION( 2184 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2185 #endif 2186 2187 idedma_ctl = 0; 2188 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc)); 2189 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc)); 2190 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2191 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2192 2193 /* setup DMA if needed */ 2194 pciide_channel_dma_setup(cp); 2195 2196 for (drive = 0; drive < 2; drive++) { 2197 drvp = &chp->ch_drive[drive]; 2198 /* If no drive, skip */ 2199 if ((drvp->drive_flags & DRIVE) == 0) 2200 continue; 2201 /* add timing values, setup DMA if needed */ 2202 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2203 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2204 mode = drvp->PIO_mode; 2205 goto pio; 2206 } 2207 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2208 (drvp->drive_flags & DRIVE_UDMA)) { 2209 /* use Ultra/DMA */ 2210 drvp->drive_flags &= ~DRIVE_DMA; 2211 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2212 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2213 AMD7X6_UDMA_TIME(chp->channel, drive, 2214 amd7x6_udma_tim[drvp->UDMA_mode]); 2215 /* can use PIO timings, MW DMA unused */ 2216 mode = drvp->PIO_mode; 2217 } else { 2218 /* use Multiword DMA, but only if revision is OK */ 2219 drvp->drive_flags &= ~DRIVE_UDMA; 2220 #ifndef PCIIDE_AMD756_ENABLEDMA 2221 /* 2222 * The workaround doesn't seem to be necessary 2223 * with all drives, so it can be disabled by 2224 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2225 * triggered. 2226 */ 2227 if (sc->sc_pci_vendor == PCI_VENDOR_AMD && 2228 sc->sc_pp->ide_product == 2229 PCI_PRODUCT_AMD_PBC756_IDE && 2230 AMD756_CHIPREV_DISABLEDMA(rev)) { 2231 printf("%s:%d:%d: multi-word DMA disabled due " 2232 "to chip revision\n", 2233 sc->sc_wdcdev.sc_dev.dv_xname, 2234 chp->channel, drive); 2235 mode = drvp->PIO_mode; 2236 drvp->drive_flags &= ~DRIVE_DMA; 2237 goto pio; 2238 } 2239 #endif 2240 /* mode = min(pio, dma+2) */ 2241 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2242 mode = drvp->PIO_mode; 2243 else 2244 mode = drvp->DMA_mode + 2; 2245 } 2246 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2247 2248 pio: /* setup PIO mode */ 2249 if (mode <= 2) { 2250 drvp->DMA_mode = 0; 2251 drvp->PIO_mode = 0; 2252 mode = 0; 2253 } else { 2254 drvp->PIO_mode = mode; 2255 drvp->DMA_mode = mode - 2; 2256 } 2257 datatim_reg |= 2258 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2259 amd7x6_pio_set[mode]) | 2260 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2261 amd7x6_pio_rec[mode]); 2262 } 2263 if (idedma_ctl != 0) { 2264 /* Add software bits in status register */ 2265 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2266 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2267 idedma_ctl); 2268 } 2269 pciide_print_modes(cp); 2270 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc), datatim_reg); 2271 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc), udmatim_reg); 2272 } 2273 2274 void 2275 apollo_chip_map(sc, pa) 2276 struct pciide_softc *sc; 2277 struct pci_attach_args *pa; 2278 { 2279 struct pciide_channel *cp; 2280 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2281 int channel; 2282 u_int32_t ideconf; 2283 bus_size_t cmdsize, ctlsize; 2284 pcitag_t pcib_tag; 2285 pcireg_t pcib_id, pcib_class; 2286 2287 if (pciide_chipen(sc, pa) == 0) 2288 return; 2289 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2290 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2291 /* and read ID and rev of the ISA bridge */ 2292 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2293 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2294 printf(": VIA Technologies "); 2295 switch (PCI_PRODUCT(pcib_id)) { 2296 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2297 printf("VT82C586 (Apollo VP) "); 2298 if(PCI_REVISION(pcib_class) >= 0x02) { 2299 printf("ATA33 controller\n"); 2300 sc->sc_wdcdev.UDMA_cap = 2; 2301 } else { 2302 printf("controller\n"); 2303 sc->sc_wdcdev.UDMA_cap = 0; 2304 } 2305 break; 2306 case PCI_PRODUCT_VIATECH_VT82C596A: 2307 printf("VT82C596A (Apollo Pro) "); 2308 if (PCI_REVISION(pcib_class) >= 0x12) { 2309 printf("ATA66 controller\n"); 2310 sc->sc_wdcdev.UDMA_cap = 4; 2311 } else { 2312 printf("ATA33 controller\n"); 2313 sc->sc_wdcdev.UDMA_cap = 2; 2314 } 2315 break; 2316 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2317 printf("VT82C686A (Apollo KX133) "); 2318 if (PCI_REVISION(pcib_class) >= 0x40) { 2319 printf("ATA100 controller\n"); 2320 sc->sc_wdcdev.UDMA_cap = 5; 2321 } else { 2322 printf("ATA66 controller\n"); 2323 sc->sc_wdcdev.UDMA_cap = 4; 2324 } 2325 break; 2326 case PCI_PRODUCT_VIATECH_VT8231: 2327 printf("VT8231 ATA100 controller\n"); 2328 sc->sc_wdcdev.UDMA_cap = 5; 2329 break; 2330 case PCI_PRODUCT_VIATECH_VT8233: 2331 printf("VT8233 ATA100 controller\n"); 2332 sc->sc_wdcdev.UDMA_cap = 5; 2333 break; 2334 case PCI_PRODUCT_VIATECH_VT8233A: 2335 printf("VT8233A ATA133 controller\n"); 2336 sc->sc_wdcdev.UDMA_cap = 6; 2337 break; 2338 case PCI_PRODUCT_VIATECH_VT8235: 2339 printf("VT8235 ATA133 controller\n"); 2340 sc->sc_wdcdev.UDMA_cap = 6; 2341 break; 2342 default: 2343 printf("unknown ATA controller\n"); 2344 sc->sc_wdcdev.UDMA_cap = 0; 2345 } 2346 2347 printf("%s: bus-master DMA support present", 2348 sc->sc_wdcdev.sc_dev.dv_xname); 2349 pciide_mapreg_dma(sc, pa); 2350 printf("\n"); 2351 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2352 WDC_CAPABILITY_MODE; 2353 if (sc->sc_dma_ok) { 2354 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2355 sc->sc_wdcdev.irqack = pciide_irqack; 2356 if (sc->sc_wdcdev.UDMA_cap > 0) 2357 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2358 } 2359 sc->sc_wdcdev.PIO_cap = 4; 2360 sc->sc_wdcdev.DMA_cap = 2; 2361 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2362 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2363 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2364 2365 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2366 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2367 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2368 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2369 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2370 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2371 DEBUG_PROBE); 2372 2373 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2374 cp = &sc->pciide_channels[channel]; 2375 if (pciide_chansetup(sc, channel, interface) == 0) 2376 continue; 2377 2378 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2379 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2380 printf("%s: %s channel ignored (disabled)\n", 2381 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2382 continue; 2383 } 2384 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2385 pciide_pci_intr); 2386 if (cp->hw_ok == 0) 2387 continue; 2388 if (pciide_chan_candisable(cp)) { 2389 ideconf &= ~APO_IDECONF_EN(channel); 2390 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2391 ideconf); 2392 } 2393 pciide_map_compat_intr(pa, cp, channel, interface); 2394 2395 if (cp->hw_ok == 0) 2396 continue; 2397 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2398 } 2399 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2400 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2401 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2402 } 2403 2404 void 2405 apollo_setup_channel(chp) 2406 struct channel_softc *chp; 2407 { 2408 u_int32_t udmatim_reg, datatim_reg; 2409 u_int8_t idedma_ctl; 2410 int mode, drive; 2411 struct ata_drive_datas *drvp; 2412 struct pciide_channel *cp = (struct pciide_channel*)chp; 2413 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2414 2415 idedma_ctl = 0; 2416 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2417 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2418 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2419 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2420 2421 /* setup DMA if needed */ 2422 pciide_channel_dma_setup(cp); 2423 2424 for (drive = 0; drive < 2; drive++) { 2425 drvp = &chp->ch_drive[drive]; 2426 /* If no drive, skip */ 2427 if ((drvp->drive_flags & DRIVE) == 0) 2428 continue; 2429 /* add timing values, setup DMA if needed */ 2430 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2431 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2432 mode = drvp->PIO_mode; 2433 goto pio; 2434 } 2435 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2436 (drvp->drive_flags & DRIVE_UDMA)) { 2437 /* use Ultra/DMA */ 2438 drvp->drive_flags &= ~DRIVE_DMA; 2439 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2440 APO_UDMA_EN_MTH(chp->channel, drive); 2441 if (sc->sc_wdcdev.UDMA_cap == 6) { 2442 /* 8233a */ 2443 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2444 drive, apollo_udma133_tim[drvp->UDMA_mode]); 2445 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 2446 /* 686b */ 2447 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2448 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2449 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2450 /* 596b or 686a */ 2451 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2452 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2453 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2454 } else { 2455 /* 596a or 586b */ 2456 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2457 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2458 } 2459 /* can use PIO timings, MW DMA unused */ 2460 mode = drvp->PIO_mode; 2461 } else { 2462 /* use Multiword DMA */ 2463 drvp->drive_flags &= ~DRIVE_UDMA; 2464 /* mode = min(pio, dma+2) */ 2465 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2466 mode = drvp->PIO_mode; 2467 else 2468 mode = drvp->DMA_mode + 2; 2469 } 2470 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2471 2472 pio: /* setup PIO mode */ 2473 if (mode <= 2) { 2474 drvp->DMA_mode = 0; 2475 drvp->PIO_mode = 0; 2476 mode = 0; 2477 } else { 2478 drvp->PIO_mode = mode; 2479 drvp->DMA_mode = mode - 2; 2480 } 2481 datatim_reg |= 2482 APO_DATATIM_PULSE(chp->channel, drive, 2483 apollo_pio_set[mode]) | 2484 APO_DATATIM_RECOV(chp->channel, drive, 2485 apollo_pio_rec[mode]); 2486 } 2487 if (idedma_ctl != 0) { 2488 /* Add software bits in status register */ 2489 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2490 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2491 idedma_ctl); 2492 } 2493 pciide_print_modes(cp); 2494 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2495 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2496 } 2497 2498 void 2499 cmd_channel_map(pa, sc, channel) 2500 struct pci_attach_args *pa; 2501 struct pciide_softc *sc; 2502 int channel; 2503 { 2504 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2505 bus_size_t cmdsize, ctlsize; 2506 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2507 int interface, one_channel; 2508 2509 /* 2510 * The 0648/0649 can be told to identify as a RAID controller. 2511 * In this case, we have to fake interface 2512 */ 2513 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2514 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2515 PCIIDE_INTERFACE_SETTABLE(1); 2516 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2517 CMD_CONF_DSA1) 2518 interface |= PCIIDE_INTERFACE_PCI(0) | 2519 PCIIDE_INTERFACE_PCI(1); 2520 } else { 2521 interface = PCI_INTERFACE(pa->pa_class); 2522 } 2523 2524 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2525 cp->name = PCIIDE_CHANNEL_NAME(channel); 2526 cp->wdc_channel.channel = channel; 2527 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2528 2529 /* 2530 * Older CMD64X doesn't have independant channels 2531 */ 2532 switch (sc->sc_pp->ide_product) { 2533 case PCI_PRODUCT_CMDTECH_649: 2534 one_channel = 0; 2535 break; 2536 default: 2537 one_channel = 1; 2538 break; 2539 } 2540 2541 if (channel > 0 && one_channel) { 2542 cp->wdc_channel.ch_queue = 2543 sc->pciide_channels[0].wdc_channel.ch_queue; 2544 } else { 2545 cp->wdc_channel.ch_queue = 2546 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2547 } 2548 if (cp->wdc_channel.ch_queue == NULL) { 2549 printf("%s %s channel: " 2550 "can't allocate memory for command queue", 2551 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2552 return; 2553 } 2554 2555 printf("%s: %s channel %s to %s mode\n", 2556 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2557 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2558 "configured" : "wired", 2559 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2560 "native-PCI" : "compatibility"); 2561 2562 /* 2563 * with a CMD PCI64x, if we get here, the first channel is enabled: 2564 * there's no way to disable the first channel without disabling 2565 * the whole device 2566 */ 2567 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2568 printf("%s: %s channel ignored (disabled)\n", 2569 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2570 return; 2571 } 2572 2573 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2574 if (cp->hw_ok == 0) 2575 return; 2576 if (channel == 1) { 2577 if (pciide_chan_candisable(cp)) { 2578 ctrl &= ~CMD_CTRL_2PORT; 2579 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2580 CMD_CTRL, ctrl); 2581 } 2582 } 2583 pciide_map_compat_intr(pa, cp, channel, interface); 2584 } 2585 2586 int 2587 cmd_pci_intr(arg) 2588 void *arg; 2589 { 2590 struct pciide_softc *sc = arg; 2591 struct pciide_channel *cp; 2592 struct channel_softc *wdc_cp; 2593 int i, rv, crv; 2594 u_int32_t priirq, secirq; 2595 2596 rv = 0; 2597 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2598 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2599 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2600 cp = &sc->pciide_channels[i]; 2601 wdc_cp = &cp->wdc_channel; 2602 /* If a compat channel skip. */ 2603 if (cp->compat) 2604 continue; 2605 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2606 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2607 crv = wdcintr(wdc_cp); 2608 if (crv == 0) 2609 printf("%s:%d: bogus intr\n", 2610 sc->sc_wdcdev.sc_dev.dv_xname, i); 2611 else 2612 rv = 1; 2613 } 2614 } 2615 return rv; 2616 } 2617 2618 void 2619 cmd_chip_map(sc, pa) 2620 struct pciide_softc *sc; 2621 struct pci_attach_args *pa; 2622 { 2623 int channel; 2624 2625 /* 2626 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2627 * and base adresses registers can be disabled at 2628 * hardware level. In this case, the device is wired 2629 * in compat mode and its first channel is always enabled, 2630 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2631 * In fact, it seems that the first channel of the CMD PCI0640 2632 * can't be disabled. 2633 */ 2634 2635 #ifdef PCIIDE_CMD064x_DISABLE 2636 if (pciide_chipen(sc, pa) == 0) 2637 return; 2638 #endif 2639 2640 printf("%s: hardware does not support DMA\n", 2641 sc->sc_wdcdev.sc_dev.dv_xname); 2642 sc->sc_dma_ok = 0; 2643 2644 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2645 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2646 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2647 2648 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2649 cmd_channel_map(pa, sc, channel); 2650 } 2651 } 2652 2653 void 2654 cmd0643_9_chip_map(sc, pa) 2655 struct pciide_softc *sc; 2656 struct pci_attach_args *pa; 2657 { 2658 struct pciide_channel *cp; 2659 int channel; 2660 pcireg_t rev = PCI_REVISION(pa->pa_class); 2661 2662 /* 2663 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2664 * and base adresses registers can be disabled at 2665 * hardware level. In this case, the device is wired 2666 * in compat mode and its first channel is always enabled, 2667 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2668 * In fact, it seems that the first channel of the CMD PCI0640 2669 * can't be disabled. 2670 */ 2671 2672 #ifdef PCIIDE_CMD064x_DISABLE 2673 if (pciide_chipen(sc, pa) == 0) 2674 return; 2675 #endif 2676 printf("%s: bus-master DMA support present", 2677 sc->sc_wdcdev.sc_dev.dv_xname); 2678 pciide_mapreg_dma(sc, pa); 2679 printf("\n"); 2680 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2681 WDC_CAPABILITY_MODE; 2682 if (sc->sc_dma_ok) { 2683 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2684 switch (sc->sc_pp->ide_product) { 2685 case PCI_PRODUCT_CMDTECH_649: 2686 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2687 sc->sc_wdcdev.UDMA_cap = 5; 2688 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2689 break; 2690 case PCI_PRODUCT_CMDTECH_648: 2691 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2692 sc->sc_wdcdev.UDMA_cap = 4; 2693 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2694 break; 2695 case PCI_PRODUCT_CMDTECH_646: 2696 if (rev >= CMD0646U2_REV) { 2697 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2698 sc->sc_wdcdev.UDMA_cap = 2; 2699 } else if (rev >= CMD0646U_REV) { 2700 /* 2701 * Linux's driver claims that the 646U is broken 2702 * with UDMA. Only enable it if we know what we're 2703 * doing 2704 */ 2705 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2706 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2707 sc->sc_wdcdev.UDMA_cap = 2; 2708 #endif 2709 /* explicitly disable UDMA */ 2710 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2711 CMD_UDMATIM(0), 0); 2712 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2713 CMD_UDMATIM(1), 0); 2714 } 2715 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2716 break; 2717 default: 2718 sc->sc_wdcdev.irqack = pciide_irqack; 2719 } 2720 } 2721 2722 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2723 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2724 sc->sc_wdcdev.PIO_cap = 4; 2725 sc->sc_wdcdev.DMA_cap = 2; 2726 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2727 2728 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2729 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2730 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2731 DEBUG_PROBE); 2732 2733 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2734 cp = &sc->pciide_channels[channel]; 2735 cmd_channel_map(pa, sc, channel); 2736 if (cp->hw_ok == 0) 2737 continue; 2738 cmd0643_9_setup_channel(&cp->wdc_channel); 2739 } 2740 /* 2741 * note - this also makes sure we clear the irq disable and reset 2742 * bits 2743 */ 2744 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2745 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2746 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2747 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2748 DEBUG_PROBE); 2749 } 2750 2751 void 2752 cmd0643_9_setup_channel(chp) 2753 struct channel_softc *chp; 2754 { 2755 struct ata_drive_datas *drvp; 2756 u_int8_t tim; 2757 u_int32_t idedma_ctl, udma_reg; 2758 int drive; 2759 struct pciide_channel *cp = (struct pciide_channel*)chp; 2760 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2761 2762 idedma_ctl = 0; 2763 /* setup DMA if needed */ 2764 pciide_channel_dma_setup(cp); 2765 2766 for (drive = 0; drive < 2; drive++) { 2767 drvp = &chp->ch_drive[drive]; 2768 /* If no drive, skip */ 2769 if ((drvp->drive_flags & DRIVE) == 0) 2770 continue; 2771 /* add timing values, setup DMA if needed */ 2772 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2773 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2774 if (drvp->drive_flags & DRIVE_UDMA) { 2775 /* UltraDMA on a 646U2, 0648 or 0649 */ 2776 drvp->drive_flags &= ~DRIVE_DMA; 2777 udma_reg = pciide_pci_read(sc->sc_pc, 2778 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2779 if (drvp->UDMA_mode > 2 && 2780 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2781 CMD_BICSR) & 2782 CMD_BICSR_80(chp->channel)) == 0) 2783 drvp->UDMA_mode = 2; 2784 if (drvp->UDMA_mode > 2) 2785 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2786 else if (sc->sc_wdcdev.UDMA_cap > 2) 2787 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2788 udma_reg |= CMD_UDMATIM_UDMA(drive); 2789 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2790 CMD_UDMATIM_TIM_OFF(drive)); 2791 udma_reg |= 2792 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2793 CMD_UDMATIM_TIM_OFF(drive)); 2794 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2795 CMD_UDMATIM(chp->channel), udma_reg); 2796 } else { 2797 /* 2798 * use Multiword DMA. 2799 * Timings will be used for both PIO and DMA, 2800 * so adjust DMA mode if needed 2801 * if we have a 0646U2/8/9, turn off UDMA 2802 */ 2803 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2804 udma_reg = pciide_pci_read(sc->sc_pc, 2805 sc->sc_tag, 2806 CMD_UDMATIM(chp->channel)); 2807 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2808 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2809 CMD_UDMATIM(chp->channel), 2810 udma_reg); 2811 } 2812 if (drvp->PIO_mode >= 3 && 2813 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2814 drvp->DMA_mode = drvp->PIO_mode - 2; 2815 } 2816 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2817 } 2818 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2819 } 2820 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2821 CMD_DATA_TIM(chp->channel, drive), tim); 2822 } 2823 if (idedma_ctl != 0) { 2824 /* Add software bits in status register */ 2825 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2826 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2827 idedma_ctl); 2828 } 2829 pciide_print_modes(cp); 2830 } 2831 2832 void 2833 cmd646_9_irqack(chp) 2834 struct channel_softc *chp; 2835 { 2836 u_int32_t priirq, secirq; 2837 struct pciide_channel *cp = (struct pciide_channel*)chp; 2838 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2839 2840 if (chp->channel == 0) { 2841 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2842 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2843 } else { 2844 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2845 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2846 } 2847 pciide_irqack(chp); 2848 } 2849 2850 void 2851 cmd680_chip_map(sc, pa) 2852 struct pciide_softc *sc; 2853 struct pci_attach_args *pa; 2854 { 2855 struct pciide_channel *cp; 2856 int channel; 2857 2858 if (pciide_chipen(sc, pa) == 0) 2859 return; 2860 printf("%s: bus-master DMA support present", 2861 sc->sc_wdcdev.sc_dev.dv_xname); 2862 pciide_mapreg_dma(sc, pa); 2863 printf("\n"); 2864 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2865 WDC_CAPABILITY_MODE; 2866 if (sc->sc_dma_ok) { 2867 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2868 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2869 sc->sc_wdcdev.UDMA_cap = 6; 2870 sc->sc_wdcdev.irqack = pciide_irqack; 2871 } 2872 2873 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2874 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2875 sc->sc_wdcdev.PIO_cap = 4; 2876 sc->sc_wdcdev.DMA_cap = 2; 2877 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 2878 2879 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 2880 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 2881 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 2882 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 2883 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2884 cp = &sc->pciide_channels[channel]; 2885 cmd680_channel_map(pa, sc, channel); 2886 if (cp->hw_ok == 0) 2887 continue; 2888 cmd680_setup_channel(&cp->wdc_channel); 2889 } 2890 } 2891 2892 void 2893 cmd680_channel_map(pa, sc, channel) 2894 struct pci_attach_args *pa; 2895 struct pciide_softc *sc; 2896 int channel; 2897 { 2898 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2899 bus_size_t cmdsize, ctlsize; 2900 int interface, i, reg; 2901 static const u_int8_t init_val[] = 2902 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 2903 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 2904 2905 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2906 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2907 PCIIDE_INTERFACE_SETTABLE(1); 2908 interface |= PCIIDE_INTERFACE_PCI(0) | 2909 PCIIDE_INTERFACE_PCI(1); 2910 } else { 2911 interface = PCI_INTERFACE(pa->pa_class); 2912 } 2913 2914 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2915 cp->name = PCIIDE_CHANNEL_NAME(channel); 2916 cp->wdc_channel.channel = channel; 2917 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2918 2919 cp->wdc_channel.ch_queue = 2920 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2921 if (cp->wdc_channel.ch_queue == NULL) { 2922 printf("%s %s channel: " 2923 "can't allocate memory for command queue", 2924 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2925 return; 2926 } 2927 2928 /* XXX */ 2929 reg = 0xa2 + channel * 16; 2930 for (i = 0; i < sizeof(init_val); i++) 2931 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 2932 2933 printf("%s: %s channel %s to %s mode\n", 2934 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2935 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2936 "configured" : "wired", 2937 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2938 "native-PCI" : "compatibility"); 2939 2940 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 2941 if (cp->hw_ok == 0) 2942 return; 2943 pciide_map_compat_intr(pa, cp, channel, interface); 2944 } 2945 2946 void 2947 cmd680_setup_channel(chp) 2948 struct channel_softc *chp; 2949 { 2950 struct ata_drive_datas *drvp; 2951 u_int8_t mode, off, scsc; 2952 u_int16_t val; 2953 u_int32_t idedma_ctl; 2954 int drive; 2955 struct pciide_channel *cp = (struct pciide_channel*)chp; 2956 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2957 pci_chipset_tag_t pc = sc->sc_pc; 2958 pcitag_t pa = sc->sc_tag; 2959 static const u_int8_t udma2_tbl[] = 2960 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 2961 static const u_int8_t udma_tbl[] = 2962 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 2963 static const u_int16_t dma_tbl[] = 2964 { 0x2208, 0x10c2, 0x10c1 }; 2965 static const u_int16_t pio_tbl[] = 2966 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 2967 2968 idedma_ctl = 0; 2969 pciide_channel_dma_setup(cp); 2970 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 2971 2972 for (drive = 0; drive < 2; drive++) { 2973 drvp = &chp->ch_drive[drive]; 2974 /* If no drive, skip */ 2975 if ((drvp->drive_flags & DRIVE) == 0) 2976 continue; 2977 mode &= ~(0x03 << (drive * 4)); 2978 if (drvp->drive_flags & DRIVE_UDMA) { 2979 drvp->drive_flags &= ~DRIVE_DMA; 2980 off = 0xa0 + chp->channel * 16; 2981 if (drvp->UDMA_mode > 2 && 2982 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 2983 drvp->UDMA_mode = 2; 2984 scsc = pciide_pci_read(pc, pa, 0x8a); 2985 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 2986 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 2987 scsc = pciide_pci_read(pc, pa, 0x8a); 2988 if ((scsc & 0x30) == 0) 2989 drvp->UDMA_mode = 5; 2990 } 2991 mode |= 0x03 << (drive * 4); 2992 off = 0xac + chp->channel * 16 + drive * 2; 2993 val = pciide_pci_read(pc, pa, off) & ~0x3f; 2994 if (scsc & 0x30) 2995 val |= udma2_tbl[drvp->UDMA_mode]; 2996 else 2997 val |= udma_tbl[drvp->UDMA_mode]; 2998 pciide_pci_write(pc, pa, off, val); 2999 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3000 } else if (drvp->drive_flags & DRIVE_DMA) { 3001 mode |= 0x02 << (drive * 4); 3002 off = 0xa8 + chp->channel * 16 + drive * 2; 3003 val = dma_tbl[drvp->DMA_mode]; 3004 pciide_pci_write(pc, pa, off, val & 0xff); 3005 pciide_pci_write(pc, pa, off, val >> 8); 3006 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3007 } else { 3008 mode |= 0x01 << (drive * 4); 3009 off = 0xa4 + chp->channel * 16 + drive * 2; 3010 val = pio_tbl[drvp->PIO_mode]; 3011 pciide_pci_write(pc, pa, off, val & 0xff); 3012 pciide_pci_write(pc, pa, off, val >> 8); 3013 } 3014 } 3015 3016 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 3017 if (idedma_ctl != 0) { 3018 /* Add software bits in status register */ 3019 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3020 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3021 idedma_ctl); 3022 } 3023 pciide_print_modes(cp); 3024 } 3025 3026 void 3027 cy693_chip_map(sc, pa) 3028 struct pciide_softc *sc; 3029 struct pci_attach_args *pa; 3030 { 3031 struct pciide_channel *cp; 3032 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3033 bus_size_t cmdsize, ctlsize; 3034 3035 if (pciide_chipen(sc, pa) == 0) 3036 return; 3037 /* 3038 * this chip has 2 PCI IDE functions, one for primary and one for 3039 * secondary. So we need to call pciide_mapregs_compat() with 3040 * the real channel 3041 */ 3042 if (pa->pa_function == 1) { 3043 sc->sc_cy_compatchan = 0; 3044 } else if (pa->pa_function == 2) { 3045 sc->sc_cy_compatchan = 1; 3046 } else { 3047 printf("%s: unexpected PCI function %d\n", 3048 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3049 return; 3050 } 3051 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 3052 printf("%s: bus-master DMA support present", 3053 sc->sc_wdcdev.sc_dev.dv_xname); 3054 pciide_mapreg_dma(sc, pa); 3055 } else { 3056 printf("%s: hardware does not support DMA", 3057 sc->sc_wdcdev.sc_dev.dv_xname); 3058 sc->sc_dma_ok = 0; 3059 } 3060 printf("\n"); 3061 3062 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 3063 if (sc->sc_cy_handle == NULL) { 3064 printf("%s: unable to map hyperCache control registers\n", 3065 sc->sc_wdcdev.sc_dev.dv_xname); 3066 sc->sc_dma_ok = 0; 3067 } 3068 3069 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3070 WDC_CAPABILITY_MODE; 3071 if (sc->sc_dma_ok) { 3072 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3073 sc->sc_wdcdev.irqack = pciide_irqack; 3074 } 3075 sc->sc_wdcdev.PIO_cap = 4; 3076 sc->sc_wdcdev.DMA_cap = 2; 3077 sc->sc_wdcdev.set_modes = cy693_setup_channel; 3078 3079 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3080 sc->sc_wdcdev.nchannels = 1; 3081 3082 /* Only one channel for this chip; if we are here it's enabled */ 3083 cp = &sc->pciide_channels[0]; 3084 sc->wdc_chanarray[0] = &cp->wdc_channel; 3085 cp->name = PCIIDE_CHANNEL_NAME(0); 3086 cp->wdc_channel.channel = 0; 3087 cp->wdc_channel.wdc = &sc->sc_wdcdev; 3088 cp->wdc_channel.ch_queue = 3089 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 3090 if (cp->wdc_channel.ch_queue == NULL) { 3091 printf("%s primary channel: " 3092 "can't allocate memory for command queue", 3093 sc->sc_wdcdev.sc_dev.dv_xname); 3094 return; 3095 } 3096 printf("%s: primary channel %s to ", 3097 sc->sc_wdcdev.sc_dev.dv_xname, 3098 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 3099 "configured" : "wired"); 3100 if (interface & PCIIDE_INTERFACE_PCI(0)) { 3101 printf("native-PCI"); 3102 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 3103 pciide_pci_intr); 3104 } else { 3105 printf("compatibility"); 3106 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 3107 &cmdsize, &ctlsize); 3108 } 3109 printf(" mode\n"); 3110 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3111 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3112 wdcattach(&cp->wdc_channel); 3113 if (pciide_chan_candisable(cp)) { 3114 pci_conf_write(sc->sc_pc, sc->sc_tag, 3115 PCI_COMMAND_STATUS_REG, 0); 3116 } 3117 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 3118 if (cp->hw_ok == 0) 3119 return; 3120 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 3121 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 3122 cy693_setup_channel(&cp->wdc_channel); 3123 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 3124 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 3125 } 3126 3127 void 3128 cy693_setup_channel(chp) 3129 struct channel_softc *chp; 3130 { 3131 struct ata_drive_datas *drvp; 3132 int drive; 3133 u_int32_t cy_cmd_ctrl; 3134 u_int32_t idedma_ctl; 3135 struct pciide_channel *cp = (struct pciide_channel*)chp; 3136 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3137 int dma_mode = -1; 3138 3139 cy_cmd_ctrl = idedma_ctl = 0; 3140 3141 /* setup DMA if needed */ 3142 pciide_channel_dma_setup(cp); 3143 3144 for (drive = 0; drive < 2; drive++) { 3145 drvp = &chp->ch_drive[drive]; 3146 /* If no drive, skip */ 3147 if ((drvp->drive_flags & DRIVE) == 0) 3148 continue; 3149 /* add timing values, setup DMA if needed */ 3150 if (drvp->drive_flags & DRIVE_DMA) { 3151 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3152 /* use Multiword DMA */ 3153 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 3154 dma_mode = drvp->DMA_mode; 3155 } 3156 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3157 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 3158 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3159 CY_CMD_CTRL_IOW_REC_OFF(drive)); 3160 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3161 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 3162 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3163 CY_CMD_CTRL_IOR_REC_OFF(drive)); 3164 } 3165 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 3166 chp->ch_drive[0].DMA_mode = dma_mode; 3167 chp->ch_drive[1].DMA_mode = dma_mode; 3168 3169 if (dma_mode == -1) 3170 dma_mode = 0; 3171 3172 if (sc->sc_cy_handle != NULL) { 3173 /* Note: `multiple' is implied. */ 3174 cy82c693_write(sc->sc_cy_handle, 3175 (sc->sc_cy_compatchan == 0) ? 3176 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 3177 } 3178 3179 pciide_print_modes(cp); 3180 3181 if (idedma_ctl != 0) { 3182 /* Add software bits in status register */ 3183 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3184 IDEDMA_CTL, idedma_ctl); 3185 } 3186 } 3187 3188 static struct sis_hostbr_type { 3189 u_int16_t id; 3190 u_int8_t rev; 3191 u_int8_t udma_mode; 3192 char *name; 3193 u_int8_t type; 3194 #define SIS_TYPE_NOUDMA 0 3195 #define SIS_TYPE_66 1 3196 #define SIS_TYPE_100OLD 2 3197 #define SIS_TYPE_100NEW 3 3198 #define SIS_TYPE_133OLD 4 3199 #define SIS_TYPE_133NEW 5 3200 #define SIS_TYPE_SOUTH 6 3201 } sis_hostbr_type[] = { 3202 /* Most infos here are from sos (at) freebsd.org */ 3203 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 3204 #if 0 3205 /* 3206 * controllers associated to a rev 0x2 530 Host to PCI Bridge 3207 * have problems with UDMA (info provided by Christos) 3208 */ 3209 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 3210 #endif 3211 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 3212 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 3213 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 3214 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 3215 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 3216 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 3217 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 3218 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 3219 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 3220 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 3221 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 3222 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 3223 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 3224 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 3225 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 3226 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 3227 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 3228 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 3229 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 3230 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 3231 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 3232 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 3233 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 3234 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 3235 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 3236 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 3237 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 3238 /* 3239 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 3240 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 3241 */ 3242 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 3243 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 3244 }; 3245 3246 static struct sis_hostbr_type *sis_hostbr_type_match; 3247 3248 static int 3249 sis_hostbr_match(pa) 3250 struct pci_attach_args *pa; 3251 { 3252 int i; 3253 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 3254 return 0; 3255 sis_hostbr_type_match = NULL; 3256 for (i = 0; 3257 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 3258 i++) { 3259 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 3260 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 3261 sis_hostbr_type_match = &sis_hostbr_type[i]; 3262 } 3263 return (sis_hostbr_type_match != NULL); 3264 } 3265 3266 static int sis_south_match(pa) 3267 struct pci_attach_args *pa; 3268 { 3269 return(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 3270 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 3271 PCI_REVISION(pa->pa_class) >= 0x10); 3272 } 3273 3274 void 3275 sis_chip_map(sc, pa) 3276 struct pciide_softc *sc; 3277 struct pci_attach_args *pa; 3278 { 3279 struct pciide_channel *cp; 3280 int channel; 3281 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 3282 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3283 pcireg_t rev = PCI_REVISION(pa->pa_class); 3284 bus_size_t cmdsize, ctlsize; 3285 3286 if (pciide_chipen(sc, pa) == 0) 3287 return; 3288 printf(": Silicon Integrated System "); 3289 pci_find_device(NULL, sis_hostbr_match); 3290 if (sis_hostbr_type_match) { 3291 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 3292 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 3293 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3294 SIS_REG_57) & 0x7f); 3295 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 3296 PCI_ID_REG)) == SIS_PRODUCT_5518) { 3297 printf("96X UDMA%d", 3298 sis_hostbr_type_match->udma_mode); 3299 sc->sis_type = SIS_TYPE_133NEW; 3300 sc->sc_wdcdev.UDMA_cap = 3301 sis_hostbr_type_match->udma_mode; 3302 } else { 3303 if (pci_find_device(NULL, sis_south_match)) { 3304 sc->sis_type = SIS_TYPE_133OLD; 3305 sc->sc_wdcdev.UDMA_cap = 3306 sis_hostbr_type_match->udma_mode; 3307 } else { 3308 sc->sis_type = SIS_TYPE_100NEW; 3309 sc->sc_wdcdev.UDMA_cap = 3310 sis_hostbr_type_match->udma_mode; 3311 } 3312 } 3313 } else { 3314 sc->sis_type = sis_hostbr_type_match->type; 3315 sc->sc_wdcdev.UDMA_cap = 3316 sis_hostbr_type_match->udma_mode; 3317 } 3318 printf(sis_hostbr_type_match->name); 3319 } else { 3320 printf("5597/5598"); 3321 if (rev >= 0xd0) { 3322 sc->sc_wdcdev.UDMA_cap = 2; 3323 sc->sis_type = SIS_TYPE_66; 3324 } else { 3325 sc->sc_wdcdev.UDMA_cap = 0; 3326 sc->sis_type = SIS_TYPE_NOUDMA; 3327 } 3328 } 3329 printf(" IDE controller (rev. 0x%02x)\n", PCI_REVISION(pa->pa_class)); 3330 printf("%s: bus-master DMA support present", 3331 sc->sc_wdcdev.sc_dev.dv_xname); 3332 pciide_mapreg_dma(sc, pa); 3333 printf("\n"); 3334 3335 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3336 WDC_CAPABILITY_MODE; 3337 if (sc->sc_dma_ok) { 3338 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3339 sc->sc_wdcdev.irqack = pciide_irqack; 3340 if (sc->sis_type >= SIS_TYPE_66) 3341 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3342 } 3343 3344 sc->sc_wdcdev.PIO_cap = 4; 3345 sc->sc_wdcdev.DMA_cap = 2; 3346 3347 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3348 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3349 switch(sc->sis_type) { 3350 case SIS_TYPE_NOUDMA: 3351 case SIS_TYPE_66: 3352 case SIS_TYPE_100OLD: 3353 sc->sc_wdcdev.set_modes = sis_setup_channel; 3354 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 3355 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 3356 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 3357 break; 3358 case SIS_TYPE_100NEW: 3359 case SIS_TYPE_133OLD: 3360 sc->sc_wdcdev.set_modes = sis_setup_channel; 3361 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 3362 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 3363 break; 3364 case SIS_TYPE_133NEW: 3365 sc->sc_wdcdev.set_modes = sis96x_setup_channel; 3366 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 3367 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 3368 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 3369 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 3370 break; 3371 } 3372 3373 3374 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3375 cp = &sc->pciide_channels[channel]; 3376 if (pciide_chansetup(sc, channel, interface) == 0) 3377 continue; 3378 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 3379 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 3380 printf("%s: %s channel ignored (disabled)\n", 3381 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3382 continue; 3383 } 3384 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3385 pciide_pci_intr); 3386 if (cp->hw_ok == 0) 3387 continue; 3388 if (pciide_chan_candisable(cp)) { 3389 if (channel == 0) 3390 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 3391 else 3392 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 3393 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 3394 sis_ctr0); 3395 } 3396 pciide_map_compat_intr(pa, cp, channel, interface); 3397 if (cp->hw_ok == 0) 3398 continue; 3399 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 3400 } 3401 } 3402 3403 void 3404 sis96x_setup_channel(chp) 3405 struct channel_softc *chp; 3406 { 3407 struct ata_drive_datas *drvp; 3408 int drive; 3409 u_int32_t sis_tim; 3410 u_int32_t idedma_ctl; 3411 int regtim; 3412 struct pciide_channel *cp = (struct pciide_channel*)chp; 3413 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3414 3415 sis_tim = 0; 3416 idedma_ctl = 0; 3417 /* setup DMA if needed */ 3418 pciide_channel_dma_setup(cp); 3419 3420 for (drive = 0; drive < 2; drive++) { 3421 regtim = SIS_TIM133( 3422 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 3423 chp->channel, drive); 3424 drvp = &chp->ch_drive[drive]; 3425 /* If no drive, skip */ 3426 if ((drvp->drive_flags & DRIVE) == 0) 3427 continue; 3428 /* add timing values, setup DMA if needed */ 3429 if (drvp->drive_flags & DRIVE_UDMA) { 3430 /* use Ultra/DMA */ 3431 drvp->drive_flags &= ~DRIVE_DMA; 3432 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3433 SIS96x_REG_CBL(chp->channel)) & SIS96x_REG_CBL_33) { 3434 if (drvp->UDMA_mode > 2) 3435 drvp->UDMA_mode = 2; 3436 } 3437 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 3438 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3439 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3440 } else if (drvp->drive_flags & DRIVE_DMA) { 3441 /* 3442 * use Multiword DMA 3443 * Timings will be used for both PIO and DMA, 3444 * so adjust DMA mode if needed 3445 */ 3446 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3447 drvp->PIO_mode = drvp->DMA_mode + 2; 3448 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3449 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3450 drvp->PIO_mode - 2 : 0; 3451 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 3452 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3453 } else { 3454 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3455 } 3456 WDCDEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 3457 "channel %d drive %d: 0x%x (reg 0x%x)\n", 3458 chp->channel, drive, sis_tim, regtim), DEBUG_PROBE); 3459 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 3460 } 3461 if (idedma_ctl != 0) { 3462 /* Add software bits in status register */ 3463 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3464 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3465 idedma_ctl); 3466 } 3467 pciide_print_modes(cp); 3468 } 3469 3470 void 3471 sis_setup_channel(chp) 3472 struct channel_softc *chp; 3473 { 3474 struct ata_drive_datas *drvp; 3475 int drive; 3476 u_int32_t sis_tim; 3477 u_int32_t idedma_ctl; 3478 struct pciide_channel *cp = (struct pciide_channel*)chp; 3479 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3480 3481 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 3482 "channel %d 0x%x\n", chp->channel, 3483 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 3484 DEBUG_PROBE); 3485 sis_tim = 0; 3486 idedma_ctl = 0; 3487 /* setup DMA if needed */ 3488 pciide_channel_dma_setup(cp); 3489 3490 for (drive = 0; drive < 2; drive++) { 3491 drvp = &chp->ch_drive[drive]; 3492 /* If no drive, skip */ 3493 if ((drvp->drive_flags & DRIVE) == 0) 3494 continue; 3495 /* add timing values, setup DMA if needed */ 3496 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3497 (drvp->drive_flags & DRIVE_UDMA) == 0) 3498 goto pio; 3499 3500 if (drvp->drive_flags & DRIVE_UDMA) { 3501 /* use Ultra/DMA */ 3502 drvp->drive_flags &= ~DRIVE_DMA; 3503 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3504 SIS_REG_CBL) & SIS_REG_CBL_33(chp->channel)) { 3505 if (drvp->UDMA_mode > 2) 3506 drvp->UDMA_mode = 2; 3507 } 3508 switch (sc->sis_type) { 3509 case SIS_TYPE_66: 3510 case SIS_TYPE_100OLD: 3511 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 3512 SIS_TIM66_UDMA_TIME_OFF(drive); 3513 break; 3514 case SIS_TYPE_100NEW: 3515 sis_tim |= 3516 sis_udma100new_tim[drvp->UDMA_mode] << 3517 SIS_TIM100_UDMA_TIME_OFF(drive); 3518 case SIS_TYPE_133OLD: 3519 sis_tim |= 3520 sis_udma133old_tim[drvp->UDMA_mode] << 3521 SIS_TIM100_UDMA_TIME_OFF(drive); 3522 break; 3523 default: 3524 printf("unknown SiS IDE type %d\n", 3525 sc->sis_type); 3526 } 3527 } else { 3528 /* 3529 * use Multiword DMA 3530 * Timings will be used for both PIO and DMA, 3531 * so adjust DMA mode if needed 3532 */ 3533 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3534 drvp->PIO_mode = drvp->DMA_mode + 2; 3535 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3536 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3537 drvp->PIO_mode - 2 : 0; 3538 if (drvp->DMA_mode == 0) 3539 drvp->PIO_mode = 0; 3540 } 3541 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3542 pio: switch (sc->sis_type) { 3543 case SIS_TYPE_NOUDMA: 3544 case SIS_TYPE_66: 3545 case SIS_TYPE_100OLD: 3546 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3547 SIS_TIM66_ACT_OFF(drive); 3548 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3549 SIS_TIM66_REC_OFF(drive); 3550 break; 3551 case SIS_TYPE_100NEW: 3552 case SIS_TYPE_133OLD: 3553 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3554 SIS_TIM100_ACT_OFF(drive); 3555 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3556 SIS_TIM100_REC_OFF(drive); 3557 break; 3558 default: 3559 printf("unknown SiS IDE type %d\n", 3560 sc->sis_type); 3561 } 3562 } 3563 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 3564 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 3565 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 3566 if (idedma_ctl != 0) { 3567 /* Add software bits in status register */ 3568 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3569 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3570 idedma_ctl); 3571 } 3572 pciide_print_modes(cp); 3573 } 3574 3575 void 3576 acer_chip_map(sc, pa) 3577 struct pciide_softc *sc; 3578 struct pci_attach_args *pa; 3579 { 3580 struct pciide_channel *cp; 3581 int channel; 3582 pcireg_t cr, interface; 3583 bus_size_t cmdsize, ctlsize; 3584 pcireg_t rev = PCI_REVISION(pa->pa_class); 3585 3586 if (pciide_chipen(sc, pa) == 0) 3587 return; 3588 printf("%s: bus-master DMA support present", 3589 sc->sc_wdcdev.sc_dev.dv_xname); 3590 pciide_mapreg_dma(sc, pa); 3591 printf("\n"); 3592 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3593 WDC_CAPABILITY_MODE; 3594 if (sc->sc_dma_ok) { 3595 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3596 if (rev >= 0x20) { 3597 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3598 if (rev >= 0xC4) 3599 sc->sc_wdcdev.UDMA_cap = 5; 3600 else if (rev >= 0xC2) 3601 sc->sc_wdcdev.UDMA_cap = 4; 3602 else 3603 sc->sc_wdcdev.UDMA_cap = 2; 3604 } 3605 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3606 sc->sc_wdcdev.irqack = pciide_irqack; 3607 } 3608 3609 sc->sc_wdcdev.PIO_cap = 4; 3610 sc->sc_wdcdev.DMA_cap = 2; 3611 sc->sc_wdcdev.set_modes = acer_setup_channel; 3612 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3613 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3614 3615 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3616 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3617 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3618 3619 /* Enable "microsoft register bits" R/W. */ 3620 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3621 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3622 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3623 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3624 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3625 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3626 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3627 ~ACER_CHANSTATUSREGS_RO); 3628 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3629 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3630 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3631 /* Don't use cr, re-read the real register content instead */ 3632 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3633 PCI_CLASS_REG)); 3634 3635 /* From linux: enable "Cable Detection" */ 3636 if (rev >= 0xC2) { 3637 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3638 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3639 | ACER_0x4B_CDETECT); 3640 } 3641 3642 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3643 cp = &sc->pciide_channels[channel]; 3644 if (pciide_chansetup(sc, channel, interface) == 0) 3645 continue; 3646 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3647 printf("%s: %s channel ignored (disabled)\n", 3648 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3649 continue; 3650 } 3651 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3652 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3653 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3654 if (cp->hw_ok == 0) 3655 continue; 3656 if (pciide_chan_candisable(cp)) { 3657 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3658 pci_conf_write(sc->sc_pc, sc->sc_tag, 3659 PCI_CLASS_REG, cr); 3660 } 3661 pciide_map_compat_intr(pa, cp, channel, interface); 3662 acer_setup_channel(&cp->wdc_channel); 3663 } 3664 } 3665 3666 void 3667 acer_setup_channel(chp) 3668 struct channel_softc *chp; 3669 { 3670 struct ata_drive_datas *drvp; 3671 int drive; 3672 u_int32_t acer_fifo_udma; 3673 u_int32_t idedma_ctl; 3674 struct pciide_channel *cp = (struct pciide_channel*)chp; 3675 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3676 3677 idedma_ctl = 0; 3678 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3679 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3680 acer_fifo_udma), DEBUG_PROBE); 3681 /* setup DMA if needed */ 3682 pciide_channel_dma_setup(cp); 3683 3684 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3685 DRIVE_UDMA) { /* check 80 pins cable */ 3686 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3687 ACER_0x4A_80PIN(chp->channel)) { 3688 if (chp->ch_drive[0].UDMA_mode > 2) 3689 chp->ch_drive[0].UDMA_mode = 2; 3690 if (chp->ch_drive[1].UDMA_mode > 2) 3691 chp->ch_drive[1].UDMA_mode = 2; 3692 } 3693 } 3694 3695 for (drive = 0; drive < 2; drive++) { 3696 drvp = &chp->ch_drive[drive]; 3697 /* If no drive, skip */ 3698 if ((drvp->drive_flags & DRIVE) == 0) 3699 continue; 3700 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3701 "channel %d drive %d 0x%x\n", chp->channel, drive, 3702 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3703 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3704 /* clear FIFO/DMA mode */ 3705 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3706 ACER_UDMA_EN(chp->channel, drive) | 3707 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3708 3709 /* add timing values, setup DMA if needed */ 3710 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3711 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3712 acer_fifo_udma |= 3713 ACER_FTH_OPL(chp->channel, drive, 0x1); 3714 goto pio; 3715 } 3716 3717 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3718 if (drvp->drive_flags & DRIVE_UDMA) { 3719 /* use Ultra/DMA */ 3720 drvp->drive_flags &= ~DRIVE_DMA; 3721 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3722 acer_fifo_udma |= 3723 ACER_UDMA_TIM(chp->channel, drive, 3724 acer_udma[drvp->UDMA_mode]); 3725 /* XXX disable if one drive < UDMA3 ? */ 3726 if (drvp->UDMA_mode >= 3) { 3727 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3728 ACER_0x4B, 3729 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3730 ACER_0x4B) | ACER_0x4B_UDMA66); 3731 } 3732 } else { 3733 /* 3734 * use Multiword DMA 3735 * Timings will be used for both PIO and DMA, 3736 * so adjust DMA mode if needed 3737 */ 3738 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3739 drvp->PIO_mode = drvp->DMA_mode + 2; 3740 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3741 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3742 drvp->PIO_mode - 2 : 0; 3743 if (drvp->DMA_mode == 0) 3744 drvp->PIO_mode = 0; 3745 } 3746 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3747 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3748 ACER_IDETIM(chp->channel, drive), 3749 acer_pio[drvp->PIO_mode]); 3750 } 3751 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3752 acer_fifo_udma), DEBUG_PROBE); 3753 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3754 if (idedma_ctl != 0) { 3755 /* Add software bits in status register */ 3756 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3757 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3758 idedma_ctl); 3759 } 3760 pciide_print_modes(cp); 3761 } 3762 3763 int 3764 acer_pci_intr(arg) 3765 void *arg; 3766 { 3767 struct pciide_softc *sc = arg; 3768 struct pciide_channel *cp; 3769 struct channel_softc *wdc_cp; 3770 int i, rv, crv; 3771 u_int32_t chids; 3772 3773 rv = 0; 3774 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3775 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3776 cp = &sc->pciide_channels[i]; 3777 wdc_cp = &cp->wdc_channel; 3778 /* If a compat channel skip. */ 3779 if (cp->compat) 3780 continue; 3781 if (chids & ACER_CHIDS_INT(i)) { 3782 crv = wdcintr(wdc_cp); 3783 if (crv == 0) 3784 printf("%s:%d: bogus intr\n", 3785 sc->sc_wdcdev.sc_dev.dv_xname, i); 3786 else 3787 rv = 1; 3788 } 3789 } 3790 return rv; 3791 } 3792 3793 void 3794 hpt_chip_map(sc, pa) 3795 struct pciide_softc *sc; 3796 struct pci_attach_args *pa; 3797 { 3798 struct pciide_channel *cp; 3799 int i, compatchan, revision; 3800 pcireg_t interface; 3801 bus_size_t cmdsize, ctlsize; 3802 3803 if (pciide_chipen(sc, pa) == 0) 3804 return; 3805 revision = PCI_REVISION(pa->pa_class); 3806 printf(": Triones/Highpoint "); 3807 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3808 printf("HPT374 IDE Controller\n"); 3809 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372) 3810 printf("HPT372 IDE Controller\n"); 3811 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 3812 if (revision == HPT372_REV) 3813 printf("HPT372 IDE Controller\n"); 3814 else if (revision == HPT370_REV) 3815 printf("HPT370 IDE Controller\n"); 3816 else if (revision == HPT370A_REV) 3817 printf("HPT370A IDE Controller\n"); 3818 else if (revision == HPT366_REV) 3819 printf("HPT366 IDE Controller\n"); 3820 else 3821 printf("unknown HPT IDE controller rev %d\n", revision); 3822 } else 3823 printf("unknown HPT IDE controller 0x%x\n", 3824 sc->sc_pp->ide_product); 3825 3826 /* 3827 * when the chip is in native mode it identifies itself as a 3828 * 'misc mass storage'. Fake interface in this case. 3829 */ 3830 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3831 interface = PCI_INTERFACE(pa->pa_class); 3832 } else { 3833 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3834 PCIIDE_INTERFACE_PCI(0); 3835 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3836 (revision == HPT370_REV || revision == HPT370A_REV || 3837 revision == HPT372_REV)) || 3838 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3839 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3840 interface |= PCIIDE_INTERFACE_PCI(1); 3841 } 3842 3843 printf("%s: bus-master DMA support present", 3844 sc->sc_wdcdev.sc_dev.dv_xname); 3845 pciide_mapreg_dma(sc, pa); 3846 printf("\n"); 3847 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3848 WDC_CAPABILITY_MODE; 3849 if (sc->sc_dma_ok) { 3850 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3851 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3852 sc->sc_wdcdev.irqack = pciide_irqack; 3853 } 3854 sc->sc_wdcdev.PIO_cap = 4; 3855 sc->sc_wdcdev.DMA_cap = 2; 3856 3857 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3858 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3859 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3860 revision == HPT366_REV) { 3861 sc->sc_wdcdev.UDMA_cap = 4; 3862 /* 3863 * The 366 has 2 PCI IDE functions, one for primary and one 3864 * for secondary. So we need to call pciide_mapregs_compat() 3865 * with the real channel 3866 */ 3867 if (pa->pa_function == 0) { 3868 compatchan = 0; 3869 } else if (pa->pa_function == 1) { 3870 compatchan = 1; 3871 } else { 3872 printf("%s: unexpected PCI function %d\n", 3873 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3874 return; 3875 } 3876 sc->sc_wdcdev.nchannels = 1; 3877 } else { 3878 sc->sc_wdcdev.nchannels = 2; 3879 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 3880 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3881 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3882 revision == HPT372_REV)) 3883 sc->sc_wdcdev.UDMA_cap = 6; 3884 else 3885 sc->sc_wdcdev.UDMA_cap = 5; 3886 } 3887 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3888 cp = &sc->pciide_channels[i]; 3889 if (sc->sc_wdcdev.nchannels > 1) { 3890 compatchan = i; 3891 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3892 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3893 printf("%s: %s channel ignored (disabled)\n", 3894 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3895 continue; 3896 } 3897 } 3898 if (pciide_chansetup(sc, i, interface) == 0) 3899 continue; 3900 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3901 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3902 &ctlsize, hpt_pci_intr); 3903 } else { 3904 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3905 &cmdsize, &ctlsize); 3906 } 3907 if (cp->hw_ok == 0) 3908 return; 3909 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3910 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3911 wdcattach(&cp->wdc_channel); 3912 hpt_setup_channel(&cp->wdc_channel); 3913 } 3914 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3915 (revision == HPT370_REV || revision == HPT370A_REV || 3916 revision == HPT372_REV)) || 3917 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3918 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 3919 /* 3920 * HPT370_REV and highter has a bit to disable interrupts, 3921 * make sure to clear it 3922 */ 3923 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3924 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3925 ~HPT_CSEL_IRQDIS); 3926 } 3927 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 3928 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3929 revision == HPT372_REV ) || 3930 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3931 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3932 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 3933 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 3934 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 3935 return; 3936 } 3937 3938 void 3939 hpt_setup_channel(chp) 3940 struct channel_softc *chp; 3941 { 3942 struct ata_drive_datas *drvp; 3943 int drive; 3944 int cable; 3945 u_int32_t before, after; 3946 u_int32_t idedma_ctl; 3947 struct pciide_channel *cp = (struct pciide_channel*)chp; 3948 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3949 int revision = 3950 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 3951 3952 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3953 3954 /* setup DMA if needed */ 3955 pciide_channel_dma_setup(cp); 3956 3957 idedma_ctl = 0; 3958 3959 /* Per drive settings */ 3960 for (drive = 0; drive < 2; drive++) { 3961 drvp = &chp->ch_drive[drive]; 3962 /* If no drive, skip */ 3963 if ((drvp->drive_flags & DRIVE) == 0) 3964 continue; 3965 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3966 HPT_IDETIM(chp->channel, drive)); 3967 3968 /* add timing values, setup DMA if needed */ 3969 if (drvp->drive_flags & DRIVE_UDMA) { 3970 /* use Ultra/DMA */ 3971 drvp->drive_flags &= ~DRIVE_DMA; 3972 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3973 drvp->UDMA_mode > 2) 3974 drvp->UDMA_mode = 2; 3975 switch (sc->sc_pp->ide_product) { 3976 case PCI_PRODUCT_TRIONES_HPT374: 3977 after = hpt374_udma[drvp->UDMA_mode]; 3978 break; 3979 case PCI_PRODUCT_TRIONES_HPT372: 3980 after = hpt372_udma[drvp->UDMA_mode]; 3981 break; 3982 case PCI_PRODUCT_TRIONES_HPT366: 3983 default: 3984 switch(revision) { 3985 case HPT372_REV: 3986 after = hpt372_udma[drvp->UDMA_mode]; 3987 break; 3988 case HPT370_REV: 3989 case HPT370A_REV: 3990 after = hpt370_udma[drvp->UDMA_mode]; 3991 break; 3992 case HPT366_REV: 3993 default: 3994 after = hpt366_udma[drvp->UDMA_mode]; 3995 break; 3996 } 3997 } 3998 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3999 } else if (drvp->drive_flags & DRIVE_DMA) { 4000 /* 4001 * use Multiword DMA. 4002 * Timings will be used for both PIO and DMA, so adjust 4003 * DMA mode if needed 4004 */ 4005 if (drvp->PIO_mode >= 3 && 4006 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 4007 drvp->DMA_mode = drvp->PIO_mode - 2; 4008 } 4009 switch (sc->sc_pp->ide_product) { 4010 case PCI_PRODUCT_TRIONES_HPT374: 4011 after = hpt374_dma[drvp->DMA_mode]; 4012 break; 4013 case PCI_PRODUCT_TRIONES_HPT372: 4014 after = hpt372_dma[drvp->DMA_mode]; 4015 break; 4016 case PCI_PRODUCT_TRIONES_HPT366: 4017 default: 4018 switch(revision) { 4019 case HPT372_REV: 4020 after = hpt372_dma[drvp->DMA_mode]; 4021 break; 4022 case HPT370_REV: 4023 case HPT370A_REV: 4024 after = hpt370_dma[drvp->DMA_mode]; 4025 break; 4026 case HPT366_REV: 4027 default: 4028 after = hpt366_dma[drvp->DMA_mode]; 4029 break; 4030 } 4031 } 4032 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4033 } else { 4034 /* PIO only */ 4035 switch (sc->sc_pp->ide_product) { 4036 case PCI_PRODUCT_TRIONES_HPT374: 4037 after = hpt374_pio[drvp->PIO_mode]; 4038 break; 4039 case PCI_PRODUCT_TRIONES_HPT372: 4040 after = hpt372_pio[drvp->PIO_mode]; 4041 break; 4042 case PCI_PRODUCT_TRIONES_HPT366: 4043 default: 4044 switch(revision) { 4045 case HPT372_REV: 4046 after = hpt372_pio[drvp->PIO_mode]; 4047 break; 4048 case HPT370_REV: 4049 case HPT370A_REV: 4050 after = hpt370_pio[drvp->PIO_mode]; 4051 break; 4052 case HPT366_REV: 4053 default: 4054 after = hpt366_pio[drvp->PIO_mode]; 4055 break; 4056 } 4057 } 4058 } 4059 pci_conf_write(sc->sc_pc, sc->sc_tag, 4060 HPT_IDETIM(chp->channel, drive), after); 4061 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 4062 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 4063 after, before), DEBUG_PROBE); 4064 } 4065 if (idedma_ctl != 0) { 4066 /* Add software bits in status register */ 4067 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4068 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4069 idedma_ctl); 4070 } 4071 pciide_print_modes(cp); 4072 } 4073 4074 int 4075 hpt_pci_intr(arg) 4076 void *arg; 4077 { 4078 struct pciide_softc *sc = arg; 4079 struct pciide_channel *cp; 4080 struct channel_softc *wdc_cp; 4081 int rv = 0; 4082 int dmastat, i, crv; 4083 4084 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4085 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4086 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4087 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4088 IDEDMA_CTL_INTR) 4089 continue; 4090 cp = &sc->pciide_channels[i]; 4091 wdc_cp = &cp->wdc_channel; 4092 crv = wdcintr(wdc_cp); 4093 if (crv == 0) { 4094 printf("%s:%d: bogus intr\n", 4095 sc->sc_wdcdev.sc_dev.dv_xname, i); 4096 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4097 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4098 } else 4099 rv = 1; 4100 } 4101 return rv; 4102 } 4103 4104 4105 /* Macros to test product */ 4106 #define PDC_IS_262(sc) \ 4107 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 4108 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 4109 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 4110 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4111 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4112 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4113 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4114 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4115 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4116 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4117 #define PDC_IS_265(sc) \ 4118 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 4119 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 4120 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4121 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4122 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4123 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4124 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4125 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4126 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4127 #define PDC_IS_268(sc) \ 4128 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4129 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4130 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4131 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4132 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4133 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4134 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4135 #define PDC_IS_276(sc) \ 4136 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4137 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4138 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4139 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4140 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4141 4142 void 4143 pdc202xx_chip_map(sc, pa) 4144 struct pciide_softc *sc; 4145 struct pci_attach_args *pa; 4146 { 4147 struct pciide_channel *cp; 4148 int channel; 4149 pcireg_t interface, st, mode; 4150 bus_size_t cmdsize, ctlsize; 4151 4152 if (!PDC_IS_268(sc)) { 4153 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4154 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 4155 st), DEBUG_PROBE); 4156 } 4157 if (pciide_chipen(sc, pa) == 0) 4158 return; 4159 4160 /* turn off RAID mode */ 4161 if (!PDC_IS_268(sc)) 4162 st &= ~PDC2xx_STATE_IDERAID; 4163 4164 /* 4165 * can't rely on the PCI_CLASS_REG content if the chip was in raid 4166 * mode. We have to fake interface 4167 */ 4168 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 4169 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 4170 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4171 4172 printf("%s: bus-master DMA support present", 4173 sc->sc_wdcdev.sc_dev.dv_xname); 4174 pciide_mapreg_dma(sc, pa); 4175 printf("\n"); 4176 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4177 WDC_CAPABILITY_MODE; 4178 if (sc->sc_dma_ok) { 4179 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4180 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4181 sc->sc_wdcdev.irqack = pciide_irqack; 4182 } 4183 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 4184 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 4185 sc->sc_wdcdev.cap |= WDC_CAPABILITY_RAID; 4186 sc->sc_wdcdev.PIO_cap = 4; 4187 sc->sc_wdcdev.DMA_cap = 2; 4188 if (PDC_IS_276(sc)) 4189 sc->sc_wdcdev.UDMA_cap = 6; 4190 else if (PDC_IS_265(sc)) 4191 sc->sc_wdcdev.UDMA_cap = 5; 4192 else if (PDC_IS_262(sc)) 4193 sc->sc_wdcdev.UDMA_cap = 4; 4194 else 4195 sc->sc_wdcdev.UDMA_cap = 2; 4196 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 4197 pdc20268_setup_channel : pdc202xx_setup_channel; 4198 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4199 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4200 4201 if (!PDC_IS_268(sc)) { 4202 /* setup failsafe defaults */ 4203 mode = 0; 4204 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 4205 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 4206 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 4207 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 4208 for (channel = 0; 4209 channel < sc->sc_wdcdev.nchannels; 4210 channel++) { 4211 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 4212 "drive 0 initial timings 0x%x, now 0x%x\n", 4213 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 4214 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 4215 DEBUG_PROBE); 4216 pci_conf_write(sc->sc_pc, sc->sc_tag, 4217 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 4218 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 4219 "drive 1 initial timings 0x%x, now 0x%x\n", 4220 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 4221 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 4222 pci_conf_write(sc->sc_pc, sc->sc_tag, 4223 PDC2xx_TIM(channel, 1), mode); 4224 } 4225 4226 mode = PDC2xx_SCR_DMA; 4227 if (PDC_IS_262(sc)) { 4228 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 4229 } else { 4230 /* the BIOS set it up this way */ 4231 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 4232 } 4233 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 4234 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 4235 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 4236 "now 0x%x\n", 4237 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4238 PDC2xx_SCR), 4239 mode), DEBUG_PROBE); 4240 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4241 PDC2xx_SCR, mode); 4242 4243 /* controller initial state register is OK even without BIOS */ 4244 /* Set DMA mode to IDE DMA compatibility */ 4245 mode = 4246 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 4247 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 4248 DEBUG_PROBE); 4249 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 4250 mode | 0x1); 4251 mode = 4252 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 4253 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 4254 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 4255 mode | 0x1); 4256 } 4257 4258 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4259 cp = &sc->pciide_channels[channel]; 4260 if (pciide_chansetup(sc, channel, interface) == 0) 4261 continue; 4262 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 4263 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 4264 printf("%s: %s channel ignored (disabled)\n", 4265 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4266 continue; 4267 } 4268 if (PDC_IS_265(sc)) 4269 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4270 pdc20265_pci_intr); 4271 else 4272 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4273 pdc202xx_pci_intr); 4274 if (cp->hw_ok == 0) 4275 continue; 4276 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 4277 st &= ~(PDC_IS_262(sc) ? 4278 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 4279 pciide_map_compat_intr(pa, cp, channel, interface); 4280 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 4281 } 4282 if (!PDC_IS_268(sc)) { 4283 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 4284 "0x%x\n", st), DEBUG_PROBE); 4285 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 4286 } 4287 return; 4288 } 4289 4290 void 4291 pdc202xx_setup_channel(chp) 4292 struct channel_softc *chp; 4293 { 4294 struct ata_drive_datas *drvp; 4295 int drive; 4296 pcireg_t mode, st; 4297 u_int32_t idedma_ctl, scr, atapi; 4298 struct pciide_channel *cp = (struct pciide_channel*)chp; 4299 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4300 int channel = chp->channel; 4301 4302 /* setup DMA if needed */ 4303 pciide_channel_dma_setup(cp); 4304 4305 idedma_ctl = 0; 4306 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 4307 sc->sc_wdcdev.sc_dev.dv_xname, 4308 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 4309 DEBUG_PROBE); 4310 4311 /* Per channel settings */ 4312 if (PDC_IS_262(sc)) { 4313 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4314 PDC262_U66); 4315 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4316 /* Trim UDMA mode */ 4317 if ((st & PDC262_STATE_80P(channel)) != 0 || 4318 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4319 chp->ch_drive[0].UDMA_mode <= 2) || 4320 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4321 chp->ch_drive[1].UDMA_mode <= 2)) { 4322 if (chp->ch_drive[0].UDMA_mode > 2) 4323 chp->ch_drive[0].UDMA_mode = 2; 4324 if (chp->ch_drive[1].UDMA_mode > 2) 4325 chp->ch_drive[1].UDMA_mode = 2; 4326 } 4327 /* Set U66 if needed */ 4328 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4329 chp->ch_drive[0].UDMA_mode > 2) || 4330 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4331 chp->ch_drive[1].UDMA_mode > 2)) 4332 scr |= PDC262_U66_EN(channel); 4333 else 4334 scr &= ~PDC262_U66_EN(channel); 4335 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4336 PDC262_U66, scr); 4337 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 4338 sc->sc_wdcdev.sc_dev.dv_xname, channel, 4339 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4340 PDC262_ATAPI(channel))), DEBUG_PROBE); 4341 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 4342 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 4343 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4344 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4345 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 4346 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4347 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4348 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 4349 atapi = 0; 4350 else 4351 atapi = PDC262_ATAPI_UDMA; 4352 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4353 PDC262_ATAPI(channel), atapi); 4354 } 4355 } 4356 for (drive = 0; drive < 2; drive++) { 4357 drvp = &chp->ch_drive[drive]; 4358 /* If no drive, skip */ 4359 if ((drvp->drive_flags & DRIVE) == 0) 4360 continue; 4361 mode = 0; 4362 if (drvp->drive_flags & DRIVE_UDMA) { 4363 /* use Ultra/DMA */ 4364 drvp->drive_flags &= ~DRIVE_DMA; 4365 mode = PDC2xx_TIM_SET_MB(mode, 4366 pdc2xx_udma_mb[drvp->UDMA_mode]); 4367 mode = PDC2xx_TIM_SET_MC(mode, 4368 pdc2xx_udma_mc[drvp->UDMA_mode]); 4369 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4370 } else if (drvp->drive_flags & DRIVE_DMA) { 4371 mode = PDC2xx_TIM_SET_MB(mode, 4372 pdc2xx_dma_mb[drvp->DMA_mode]); 4373 mode = PDC2xx_TIM_SET_MC(mode, 4374 pdc2xx_dma_mc[drvp->DMA_mode]); 4375 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4376 } else { 4377 mode = PDC2xx_TIM_SET_MB(mode, 4378 pdc2xx_dma_mb[0]); 4379 mode = PDC2xx_TIM_SET_MC(mode, 4380 pdc2xx_dma_mc[0]); 4381 } 4382 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 4383 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 4384 if (drvp->drive_flags & DRIVE_ATA) 4385 mode |= PDC2xx_TIM_PRE; 4386 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 4387 if (drvp->PIO_mode >= 3) { 4388 mode |= PDC2xx_TIM_IORDY; 4389 if (drive == 0) 4390 mode |= PDC2xx_TIM_IORDYp; 4391 } 4392 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 4393 "timings 0x%x\n", 4394 sc->sc_wdcdev.sc_dev.dv_xname, 4395 chp->channel, drive, mode), DEBUG_PROBE); 4396 pci_conf_write(sc->sc_pc, sc->sc_tag, 4397 PDC2xx_TIM(chp->channel, drive), mode); 4398 } 4399 if (idedma_ctl != 0) { 4400 /* Add software bits in status register */ 4401 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4402 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4403 idedma_ctl); 4404 } 4405 pciide_print_modes(cp); 4406 } 4407 4408 void 4409 pdc20268_setup_channel(chp) 4410 struct channel_softc *chp; 4411 { 4412 struct ata_drive_datas *drvp; 4413 int drive; 4414 u_int32_t idedma_ctl; 4415 struct pciide_channel *cp = (struct pciide_channel*)chp; 4416 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4417 int u100; 4418 4419 /* setup DMA if needed */ 4420 pciide_channel_dma_setup(cp); 4421 4422 idedma_ctl = 0; 4423 4424 /* I don't know what this is for, FreeBSD does it ... */ 4425 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4426 IDEDMA_CMD + 0x1, 0x0b); 4427 4428 /* 4429 * I don't know what this is for; FreeBSD checks this ... this is not 4430 * cable type detect. 4431 */ 4432 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4433 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 4434 4435 for (drive = 0; drive < 2; drive++) { 4436 drvp = &chp->ch_drive[drive]; 4437 /* If no drive, skip */ 4438 if ((drvp->drive_flags & DRIVE) == 0) 4439 continue; 4440 if (drvp->drive_flags & DRIVE_UDMA) { 4441 /* use Ultra/DMA */ 4442 drvp->drive_flags &= ~DRIVE_DMA; 4443 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4444 if (drvp->UDMA_mode > 2 && u100 == 0) 4445 drvp->UDMA_mode = 2; 4446 } else if (drvp->drive_flags & DRIVE_DMA) { 4447 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4448 } 4449 } 4450 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 4451 if (idedma_ctl != 0) { 4452 /* Add software bits in status register */ 4453 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4454 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4455 idedma_ctl); 4456 } 4457 pciide_print_modes(cp); 4458 } 4459 4460 int 4461 pdc202xx_pci_intr(arg) 4462 void *arg; 4463 { 4464 struct pciide_softc *sc = arg; 4465 struct pciide_channel *cp; 4466 struct channel_softc *wdc_cp; 4467 int i, rv, crv; 4468 u_int32_t scr; 4469 4470 rv = 0; 4471 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 4472 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4473 cp = &sc->pciide_channels[i]; 4474 wdc_cp = &cp->wdc_channel; 4475 /* If a compat channel skip. */ 4476 if (cp->compat) 4477 continue; 4478 if (scr & PDC2xx_SCR_INT(i)) { 4479 crv = wdcintr(wdc_cp); 4480 if (crv == 0) 4481 printf("%s:%d: bogus intr (reg 0x%x)\n", 4482 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 4483 else 4484 rv = 1; 4485 } 4486 } 4487 return rv; 4488 } 4489 4490 int 4491 pdc20265_pci_intr(arg) 4492 void *arg; 4493 { 4494 struct pciide_softc *sc = arg; 4495 struct pciide_channel *cp; 4496 struct channel_softc *wdc_cp; 4497 int i, rv, crv; 4498 u_int32_t dmastat; 4499 4500 rv = 0; 4501 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4502 cp = &sc->pciide_channels[i]; 4503 wdc_cp = &cp->wdc_channel; 4504 /* If a compat channel skip. */ 4505 if (cp->compat) 4506 continue; 4507 /* 4508 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 4509 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 4510 * So use it instead (requires 2 reg reads instead of 1, 4511 * but we can't do it another way). 4512 */ 4513 dmastat = bus_space_read_1(sc->sc_dma_iot, 4514 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4515 if((dmastat & IDEDMA_CTL_INTR) == 0) 4516 continue; 4517 crv = wdcintr(wdc_cp); 4518 if (crv == 0) 4519 printf("%s:%d: bogus intr\n", 4520 sc->sc_wdcdev.sc_dev.dv_xname, i); 4521 else 4522 rv = 1; 4523 } 4524 return rv; 4525 } 4526 4527 void 4528 opti_chip_map(sc, pa) 4529 struct pciide_softc *sc; 4530 struct pci_attach_args *pa; 4531 { 4532 struct pciide_channel *cp; 4533 bus_size_t cmdsize, ctlsize; 4534 pcireg_t interface; 4535 u_int8_t init_ctrl; 4536 int channel; 4537 4538 if (pciide_chipen(sc, pa) == 0) 4539 return; 4540 printf("%s: bus-master DMA support present", 4541 sc->sc_wdcdev.sc_dev.dv_xname); 4542 4543 /* 4544 * XXXSCW: 4545 * There seem to be a couple of buggy revisions/implementations 4546 * of the OPTi pciide chipset. This kludge seems to fix one of 4547 * the reported problems (PR/11644) but still fails for the 4548 * other (PR/13151), although the latter may be due to other 4549 * issues too... 4550 */ 4551 if (PCI_REVISION(pa->pa_class) <= 0x12) { 4552 printf(" but disabled due to chip rev. <= 0x12"); 4553 sc->sc_dma_ok = 0; 4554 } else 4555 pciide_mapreg_dma(sc, pa); 4556 4557 printf("\n"); 4558 4559 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4560 WDC_CAPABILITY_MODE; 4561 sc->sc_wdcdev.PIO_cap = 4; 4562 if (sc->sc_dma_ok) { 4563 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4564 sc->sc_wdcdev.irqack = pciide_irqack; 4565 sc->sc_wdcdev.DMA_cap = 2; 4566 } 4567 sc->sc_wdcdev.set_modes = opti_setup_channel; 4568 4569 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4570 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4571 4572 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 4573 OPTI_REG_INIT_CONTROL); 4574 4575 interface = PCI_INTERFACE(pa->pa_class); 4576 4577 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4578 cp = &sc->pciide_channels[channel]; 4579 if (pciide_chansetup(sc, channel, interface) == 0) 4580 continue; 4581 if (channel == 1 && 4582 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 4583 printf("%s: %s channel ignored (disabled)\n", 4584 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4585 continue; 4586 } 4587 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4588 pciide_pci_intr); 4589 if (cp->hw_ok == 0) 4590 continue; 4591 pciide_map_compat_intr(pa, cp, channel, interface); 4592 if (cp->hw_ok == 0) 4593 continue; 4594 opti_setup_channel(&cp->wdc_channel); 4595 } 4596 } 4597 4598 void 4599 opti_setup_channel(chp) 4600 struct channel_softc *chp; 4601 { 4602 struct ata_drive_datas *drvp; 4603 struct pciide_channel *cp = (struct pciide_channel*)chp; 4604 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4605 int drive, spd; 4606 int mode[2]; 4607 u_int8_t rv, mr; 4608 4609 /* 4610 * The `Delay' and `Address Setup Time' fields of the 4611 * Miscellaneous Register are always zero initially. 4612 */ 4613 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 4614 mr &= ~(OPTI_MISC_DELAY_MASK | 4615 OPTI_MISC_ADDR_SETUP_MASK | 4616 OPTI_MISC_INDEX_MASK); 4617 4618 /* Prime the control register before setting timing values */ 4619 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 4620 4621 /* Determine the clockrate of the PCIbus the chip is attached to */ 4622 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 4623 spd &= OPTI_STRAP_PCI_SPEED_MASK; 4624 4625 /* setup DMA if needed */ 4626 pciide_channel_dma_setup(cp); 4627 4628 for (drive = 0; drive < 2; drive++) { 4629 drvp = &chp->ch_drive[drive]; 4630 /* If no drive, skip */ 4631 if ((drvp->drive_flags & DRIVE) == 0) { 4632 mode[drive] = -1; 4633 continue; 4634 } 4635 4636 if ((drvp->drive_flags & DRIVE_DMA)) { 4637 /* 4638 * Timings will be used for both PIO and DMA, 4639 * so adjust DMA mode if needed 4640 */ 4641 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 4642 drvp->PIO_mode = drvp->DMA_mode + 2; 4643 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 4644 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 4645 drvp->PIO_mode - 2 : 0; 4646 if (drvp->DMA_mode == 0) 4647 drvp->PIO_mode = 0; 4648 4649 mode[drive] = drvp->DMA_mode + 5; 4650 } else 4651 mode[drive] = drvp->PIO_mode; 4652 4653 if (drive && mode[0] >= 0 && 4654 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 4655 /* 4656 * Can't have two drives using different values 4657 * for `Address Setup Time'. 4658 * Slow down the faster drive to compensate. 4659 */ 4660 int d = (opti_tim_as[spd][mode[0]] > 4661 opti_tim_as[spd][mode[1]]) ? 0 : 1; 4662 4663 mode[d] = mode[1-d]; 4664 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4665 chp->ch_drive[d].DMA_mode = 0; 4666 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 4667 } 4668 } 4669 4670 for (drive = 0; drive < 2; drive++) { 4671 int m; 4672 if ((m = mode[drive]) < 0) 4673 continue; 4674 4675 /* Set the Address Setup Time and select appropriate index */ 4676 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4677 rv |= OPTI_MISC_INDEX(drive); 4678 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4679 4680 /* Set the pulse width and recovery timing parameters */ 4681 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4682 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4683 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4684 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4685 4686 /* Set the Enhanced Mode register appropriately */ 4687 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4688 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4689 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4690 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4691 } 4692 4693 /* Finally, enable the timings */ 4694 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4695 4696 pciide_print_modes(cp); 4697 } 4698 4699 #define ACARD_IS_850(sc) \ 4700 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4701 4702 void 4703 acard_chip_map(sc, pa) 4704 struct pciide_softc *sc; 4705 struct pci_attach_args *pa; 4706 { 4707 struct pciide_channel *cp; 4708 int i; 4709 pcireg_t interface; 4710 bus_size_t cmdsize, ctlsize; 4711 4712 if (pciide_chipen(sc, pa) == 0) 4713 return; 4714 4715 /* 4716 * when the chip is in native mode it identifies itself as a 4717 * 'misc mass storage'. Fake interface in this case. 4718 */ 4719 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4720 interface = PCI_INTERFACE(pa->pa_class); 4721 } else { 4722 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4723 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4724 } 4725 4726 printf("%s: bus-master DMA support present", 4727 sc->sc_wdcdev.sc_dev.dv_xname); 4728 pciide_mapreg_dma(sc, pa); 4729 printf("\n"); 4730 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4731 WDC_CAPABILITY_MODE; 4732 4733 if (sc->sc_dma_ok) { 4734 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4735 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4736 sc->sc_wdcdev.irqack = pciide_irqack; 4737 } 4738 sc->sc_wdcdev.PIO_cap = 4; 4739 sc->sc_wdcdev.DMA_cap = 2; 4740 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4741 4742 sc->sc_wdcdev.set_modes = acard_setup_channel; 4743 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4744 sc->sc_wdcdev.nchannels = 2; 4745 4746 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4747 cp = &sc->pciide_channels[i]; 4748 if (pciide_chansetup(sc, i, interface) == 0) 4749 continue; 4750 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4751 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4752 &ctlsize, pciide_pci_intr); 4753 } else { 4754 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4755 &cmdsize, &ctlsize); 4756 } 4757 if (cp->hw_ok == 0) 4758 return; 4759 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4760 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4761 wdcattach(&cp->wdc_channel); 4762 acard_setup_channel(&cp->wdc_channel); 4763 } 4764 if (!ACARD_IS_850(sc)) { 4765 u_int32_t reg; 4766 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4767 reg &= ~ATP860_CTRL_INT; 4768 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4769 } 4770 } 4771 4772 void 4773 acard_setup_channel(chp) 4774 struct channel_softc *chp; 4775 { 4776 struct ata_drive_datas *drvp; 4777 struct pciide_channel *cp = (struct pciide_channel*)chp; 4778 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4779 int channel = chp->channel; 4780 int drive; 4781 u_int32_t idetime, udma_mode; 4782 u_int32_t idedma_ctl; 4783 4784 /* setup DMA if needed */ 4785 pciide_channel_dma_setup(cp); 4786 4787 if (ACARD_IS_850(sc)) { 4788 idetime = 0; 4789 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4790 udma_mode &= ~ATP850_UDMA_MASK(channel); 4791 } else { 4792 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4793 idetime &= ~ATP860_SETTIME_MASK(channel); 4794 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4795 udma_mode &= ~ATP860_UDMA_MASK(channel); 4796 4797 /* check 80 pins cable */ 4798 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4799 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4800 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4801 & ATP860_CTRL_80P(chp->channel)) { 4802 if (chp->ch_drive[0].UDMA_mode > 2) 4803 chp->ch_drive[0].UDMA_mode = 2; 4804 if (chp->ch_drive[1].UDMA_mode > 2) 4805 chp->ch_drive[1].UDMA_mode = 2; 4806 } 4807 } 4808 } 4809 4810 idedma_ctl = 0; 4811 4812 /* Per drive settings */ 4813 for (drive = 0; drive < 2; drive++) { 4814 drvp = &chp->ch_drive[drive]; 4815 /* If no drive, skip */ 4816 if ((drvp->drive_flags & DRIVE) == 0) 4817 continue; 4818 /* add timing values, setup DMA if needed */ 4819 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4820 (drvp->drive_flags & DRIVE_UDMA)) { 4821 /* use Ultra/DMA */ 4822 if (ACARD_IS_850(sc)) { 4823 idetime |= ATP850_SETTIME(drive, 4824 acard_act_udma[drvp->UDMA_mode], 4825 acard_rec_udma[drvp->UDMA_mode]); 4826 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4827 acard_udma_conf[drvp->UDMA_mode]); 4828 } else { 4829 idetime |= ATP860_SETTIME(channel, drive, 4830 acard_act_udma[drvp->UDMA_mode], 4831 acard_rec_udma[drvp->UDMA_mode]); 4832 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4833 acard_udma_conf[drvp->UDMA_mode]); 4834 } 4835 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4836 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4837 (drvp->drive_flags & DRIVE_DMA)) { 4838 /* use Multiword DMA */ 4839 drvp->drive_flags &= ~DRIVE_UDMA; 4840 if (ACARD_IS_850(sc)) { 4841 idetime |= ATP850_SETTIME(drive, 4842 acard_act_dma[drvp->DMA_mode], 4843 acard_rec_dma[drvp->DMA_mode]); 4844 } else { 4845 idetime |= ATP860_SETTIME(channel, drive, 4846 acard_act_dma[drvp->DMA_mode], 4847 acard_rec_dma[drvp->DMA_mode]); 4848 } 4849 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4850 } else { 4851 /* PIO only */ 4852 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4853 if (ACARD_IS_850(sc)) { 4854 idetime |= ATP850_SETTIME(drive, 4855 acard_act_pio[drvp->PIO_mode], 4856 acard_rec_pio[drvp->PIO_mode]); 4857 } else { 4858 idetime |= ATP860_SETTIME(channel, drive, 4859 acard_act_pio[drvp->PIO_mode], 4860 acard_rec_pio[drvp->PIO_mode]); 4861 } 4862 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4863 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4864 | ATP8x0_CTRL_EN(channel)); 4865 } 4866 } 4867 4868 if (idedma_ctl != 0) { 4869 /* Add software bits in status register */ 4870 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4871 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4872 } 4873 pciide_print_modes(cp); 4874 4875 if (ACARD_IS_850(sc)) { 4876 pci_conf_write(sc->sc_pc, sc->sc_tag, 4877 ATP850_IDETIME(channel), idetime); 4878 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4879 } else { 4880 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4881 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4882 } 4883 } 4884 4885 int 4886 acard_pci_intr(arg) 4887 void *arg; 4888 { 4889 struct pciide_softc *sc = arg; 4890 struct pciide_channel *cp; 4891 struct channel_softc *wdc_cp; 4892 int rv = 0; 4893 int dmastat, i, crv; 4894 4895 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4896 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4897 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4898 if ((dmastat & IDEDMA_CTL_INTR) == 0) 4899 continue; 4900 cp = &sc->pciide_channels[i]; 4901 wdc_cp = &cp->wdc_channel; 4902 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 4903 (void)wdcintr(wdc_cp); 4904 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4905 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4906 continue; 4907 } 4908 crv = wdcintr(wdc_cp); 4909 if (crv == 0) 4910 printf("%s:%d: bogus intr\n", 4911 sc->sc_wdcdev.sc_dev.dv_xname, i); 4912 else if (crv == 1) 4913 rv = 1; 4914 else if (rv == 0) 4915 rv = crv; 4916 } 4917 return rv; 4918 } 4919 4920 static int 4921 sl82c105_bugchk(struct pci_attach_args *pa) 4922 { 4923 4924 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 4925 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 4926 return (0); 4927 4928 if (PCI_REVISION(pa->pa_class) <= 0x05) 4929 return (1); 4930 4931 return (0); 4932 } 4933 4934 void 4935 sl82c105_chip_map(sc, pa) 4936 struct pciide_softc *sc; 4937 struct pci_attach_args *pa; 4938 { 4939 struct pciide_channel *cp; 4940 bus_size_t cmdsize, ctlsize; 4941 pcireg_t interface, idecr; 4942 int channel; 4943 4944 if (pciide_chipen(sc, pa) == 0) 4945 return; 4946 4947 printf("%s: bus-master DMA support present", 4948 sc->sc_wdcdev.sc_dev.dv_xname); 4949 4950 /* 4951 * Check to see if we're part of the Winbond 83c553 Southbridge. 4952 * If so, we need to disable DMA on rev. <= 5 of that chip. 4953 */ 4954 if (pci_find_device(pa, sl82c105_bugchk)) { 4955 printf(" but disabled due to 83c553 rev. <= 0x05"); 4956 sc->sc_dma_ok = 0; 4957 } else 4958 pciide_mapreg_dma(sc, pa); 4959 printf("\n"); 4960 4961 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4962 WDC_CAPABILITY_MODE; 4963 sc->sc_wdcdev.PIO_cap = 4; 4964 if (sc->sc_dma_ok) { 4965 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4966 sc->sc_wdcdev.irqack = pciide_irqack; 4967 sc->sc_wdcdev.DMA_cap = 2; 4968 } 4969 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 4970 4971 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4972 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4973 4974 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 4975 4976 interface = PCI_INTERFACE(pa->pa_class); 4977 4978 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4979 cp = &sc->pciide_channels[channel]; 4980 if (pciide_chansetup(sc, channel, interface) == 0) 4981 continue; 4982 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 4983 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 4984 printf("%s: %s channel ignored (disabled)\n", 4985 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4986 continue; 4987 } 4988 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4989 pciide_pci_intr); 4990 if (cp->hw_ok == 0) 4991 continue; 4992 pciide_map_compat_intr(pa, cp, channel, interface); 4993 if (cp->hw_ok == 0) 4994 continue; 4995 sl82c105_setup_channel(&cp->wdc_channel); 4996 } 4997 } 4998 4999 void 5000 sl82c105_setup_channel(chp) 5001 struct channel_softc *chp; 5002 { 5003 struct ata_drive_datas *drvp; 5004 struct pciide_channel *cp = (struct pciide_channel*)chp; 5005 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5006 int pxdx_reg, drive; 5007 pcireg_t pxdx; 5008 5009 /* Set up DMA if needed. */ 5010 pciide_channel_dma_setup(cp); 5011 5012 for (drive = 0; drive < 2; drive++) { 5013 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 5014 : SYMPH_P1D0CR) + (drive * 4); 5015 5016 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 5017 5018 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 5019 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 5020 5021 drvp = &chp->ch_drive[drive]; 5022 /* If no drive, skip. */ 5023 if ((drvp->drive_flags & DRIVE) == 0) { 5024 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 5025 continue; 5026 } 5027 5028 if (drvp->drive_flags & DRIVE_DMA) { 5029 /* 5030 * Timings will be used for both PIO and DMA, 5031 * so adjust DMA mode if needed. 5032 */ 5033 if (drvp->PIO_mode >= 3) { 5034 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 5035 drvp->DMA_mode = drvp->PIO_mode - 2; 5036 if (drvp->DMA_mode < 1) { 5037 /* 5038 * Can't mix both PIO and DMA. 5039 * Disable DMA. 5040 */ 5041 drvp->drive_flags &= ~DRIVE_DMA; 5042 } 5043 } else { 5044 /* 5045 * Can't mix both PIO and DMA. Disable 5046 * DMA. 5047 */ 5048 drvp->drive_flags &= ~DRIVE_DMA; 5049 } 5050 } 5051 5052 if (drvp->drive_flags & DRIVE_DMA) { 5053 /* Use multi-word DMA. */ 5054 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 5055 PxDx_CMD_ON_SHIFT; 5056 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 5057 } else { 5058 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 5059 PxDx_CMD_ON_SHIFT; 5060 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 5061 } 5062 5063 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 5064 5065 /* ...and set the mode for this drive. */ 5066 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 5067 } 5068 5069 pciide_print_modes(cp); 5070 } 5071 5072 void 5073 serverworks_chip_map(sc, pa) 5074 struct pciide_softc *sc; 5075 struct pci_attach_args *pa; 5076 { 5077 struct pciide_channel *cp; 5078 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 5079 pcitag_t pcib_tag; 5080 int channel; 5081 bus_size_t cmdsize, ctlsize; 5082 5083 if (pciide_chipen(sc, pa) == 0) 5084 return; 5085 5086 printf("%s: bus-master DMA support present", 5087 sc->sc_wdcdev.sc_dev.dv_xname); 5088 pciide_mapreg_dma(sc, pa); 5089 printf("\n"); 5090 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5091 WDC_CAPABILITY_MODE; 5092 5093 if (sc->sc_dma_ok) { 5094 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5095 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5096 sc->sc_wdcdev.irqack = pciide_irqack; 5097 } 5098 sc->sc_wdcdev.PIO_cap = 4; 5099 sc->sc_wdcdev.DMA_cap = 2; 5100 switch (sc->sc_pp->ide_product) { 5101 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 5102 sc->sc_wdcdev.UDMA_cap = 2; 5103 break; 5104 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 5105 if (PCI_REVISION(pa->pa_class) < 0x92) 5106 sc->sc_wdcdev.UDMA_cap = 4; 5107 else 5108 sc->sc_wdcdev.UDMA_cap = 5; 5109 break; 5110 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 5111 sc->sc_wdcdev.UDMA_cap = 5; 5112 break; 5113 } 5114 5115 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 5116 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5117 sc->sc_wdcdev.nchannels = 2; 5118 5119 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5120 cp = &sc->pciide_channels[channel]; 5121 if (pciide_chansetup(sc, channel, interface) == 0) 5122 continue; 5123 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5124 serverworks_pci_intr); 5125 if (cp->hw_ok == 0) 5126 return; 5127 pciide_map_compat_intr(pa, cp, channel, interface); 5128 if (cp->hw_ok == 0) 5129 return; 5130 serverworks_setup_channel(&cp->wdc_channel); 5131 } 5132 5133 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 5134 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 5135 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 5136 } 5137 5138 void 5139 serverworks_setup_channel(chp) 5140 struct channel_softc *chp; 5141 { 5142 struct ata_drive_datas *drvp; 5143 struct pciide_channel *cp = (struct pciide_channel*)chp; 5144 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5145 int channel = chp->channel; 5146 int drive, unit; 5147 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 5148 u_int32_t idedma_ctl; 5149 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 5150 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 5151 5152 /* setup DMA if needed */ 5153 pciide_channel_dma_setup(cp); 5154 5155 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 5156 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 5157 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 5158 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 5159 5160 pio_time &= ~(0xffff << (16 * channel)); 5161 dma_time &= ~(0xffff << (16 * channel)); 5162 pio_mode &= ~(0xff << (8 * channel + 16)); 5163 udma_mode &= ~(0xff << (8 * channel + 16)); 5164 udma_mode &= ~(3 << (2 * channel)); 5165 5166 idedma_ctl = 0; 5167 5168 /* Per drive settings */ 5169 for (drive = 0; drive < 2; drive++) { 5170 drvp = &chp->ch_drive[drive]; 5171 /* If no drive, skip */ 5172 if ((drvp->drive_flags & DRIVE) == 0) 5173 continue; 5174 unit = drive + 2 * channel; 5175 /* add timing values, setup DMA if needed */ 5176 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 5177 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 5178 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 5179 (drvp->drive_flags & DRIVE_UDMA)) { 5180 /* use Ultra/DMA, check for 80-pin cable */ 5181 if (drvp->UDMA_mode > 2 && 5182 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 5183 drvp->UDMA_mode = 2; 5184 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 5185 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 5186 udma_mode |= 1 << unit; 5187 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5188 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 5189 (drvp->drive_flags & DRIVE_DMA)) { 5190 /* use Multiword DMA */ 5191 drvp->drive_flags &= ~DRIVE_UDMA; 5192 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 5193 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5194 } else { 5195 /* PIO only */ 5196 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 5197 } 5198 } 5199 5200 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 5201 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 5202 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 5203 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 5204 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 5205 5206 if (idedma_ctl != 0) { 5207 /* Add software bits in status register */ 5208 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5209 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 5210 } 5211 pciide_print_modes(cp); 5212 } 5213 5214 int 5215 serverworks_pci_intr(arg) 5216 void *arg; 5217 { 5218 struct pciide_softc *sc = arg; 5219 struct pciide_channel *cp; 5220 struct channel_softc *wdc_cp; 5221 int rv = 0; 5222 int dmastat, i, crv; 5223 5224 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5225 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5226 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 5227 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 5228 IDEDMA_CTL_INTR) 5229 continue; 5230 cp = &sc->pciide_channels[i]; 5231 wdc_cp = &cp->wdc_channel; 5232 crv = wdcintr(wdc_cp); 5233 if (crv == 0) { 5234 printf("%s:%d: bogus intr\n", 5235 sc->sc_wdcdev.sc_dev.dv_xname, i); 5236 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5237 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 5238 } else 5239 rv = 1; 5240 } 5241 return rv; 5242 } 5243 5244 void 5245 artisea_chip_map(sc, pa) 5246 struct pciide_softc *sc; 5247 struct pci_attach_args *pa; 5248 { 5249 struct pciide_channel *cp; 5250 bus_size_t cmdsize, ctlsize; 5251 pcireg_t interface; 5252 int channel; 5253 5254 if (pciide_chipen(sc, pa) == 0) 5255 return; 5256 5257 printf("%s: bus-master DMA support resent", 5258 sc->sc_wdcdev.sc_dev.dv_xname); 5259 #ifndef PCIIDE_I31244_ENABLEDMA 5260 if (PCI_REVISION(pa->pa_class) == 0) { 5261 printf(" but disabled due to rev. 0"); 5262 sc->sc_dma_ok = 0; 5263 } else 5264 #endif 5265 pciide_mapreg_dma(sc, pa); 5266 printf("\n"); 5267 5268 /* 5269 * XXX Configure LEDs to show activity. 5270 */ 5271 5272 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5273 WDC_CAPABILITY_MODE; 5274 sc->sc_wdcdev.PIO_cap = 4; 5275 if (sc->sc_dma_ok) { 5276 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5277 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5278 sc->sc_wdcdev.irqack = pciide_irqack; 5279 sc->sc_wdcdev.DMA_cap = 2; 5280 sc->sc_wdcdev.UDMA_cap = 6; 5281 } 5282 sc->sc_wdcdev.set_modes = sata_setup_channel; 5283 5284 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5285 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5286 5287 interface = PCI_INTERFACE(pa->pa_class); 5288 5289 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5290 cp = &sc->pciide_channels[channel]; 5291 if (pciide_chansetup(sc, channel, interface) == 0) 5292 continue; 5293 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5294 pciide_pci_intr); 5295 if (cp->hw_ok == 0) 5296 continue; 5297 pciide_map_compat_intr(pa, cp, channel, interface); 5298 sata_setup_channel(&cp->wdc_channel); 5299 } 5300 } 5301
Indexes created Thu Oct 02 10:09:58 GMT 2025