pciide.c revision 1.187
1 /* $NetBSD: pciide.c,v 1.187 2003/03/20 04:22:49 thorpej Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.187 2003/03/20 04:22:49 thorpej Exp $"); 80 81 #ifndef WDCDEBUG 82 #define WDCDEBUG 83 #endif 84 85 #define DEBUG_DMA 0x01 86 #define DEBUG_XFERS 0x02 87 #define DEBUG_FUNCS 0x08 88 #define DEBUG_PROBE 0x10 89 #ifdef WDCDEBUG 90 int wdcdebug_pciide_mask = 0; 91 #define WDCDEBUG_PRINT(args, level) \ 92 if (wdcdebug_pciide_mask & (level)) printf args 93 #else 94 #define WDCDEBUG_PRINT(args, level) 95 #endif 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <machine/endian.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/pciide_sl82c105_reg.h> 122 #include <dev/pci/pciide_i31244_reg.h> 123 #include <dev/pci/pciide_sii3112_reg.h> 124 #include <dev/pci/cy82c693var.h> 125 126 #include "opt_pciide.h" 127 128 /* inlines for reading/writing 8-bit PCI registers */ 129 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 130 int)); 131 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 132 int, u_int8_t)); 133 134 static __inline u_int8_t 135 pciide_pci_read(pc, pa, reg) 136 pci_chipset_tag_t pc; 137 pcitag_t pa; 138 int reg; 139 { 140 141 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 142 ((reg & 0x03) * 8) & 0xff); 143 } 144 145 static __inline void 146 pciide_pci_write(pc, pa, reg, val) 147 pci_chipset_tag_t pc; 148 pcitag_t pa; 149 int reg; 150 u_int8_t val; 151 { 152 pcireg_t pcival; 153 154 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 155 pcival &= ~(0xff << ((reg & 0x03) * 8)); 156 pcival |= (val << ((reg & 0x03) * 8)); 157 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 158 } 159 160 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 162 void sata_setup_channel __P((struct channel_softc*)); 163 164 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void piix_setup_channel __P((struct channel_softc*)); 166 void piix3_4_setup_channel __P((struct channel_softc*)); 167 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 168 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 169 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 170 171 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 172 void amd7x6_setup_channel __P((struct channel_softc*)); 173 174 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void apollo_setup_channel __P((struct channel_softc*)); 176 177 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 179 void cmd0643_9_setup_channel __P((struct channel_softc*)); 180 void cmd_channel_map __P((struct pci_attach_args *, 181 struct pciide_softc *, int)); 182 int cmd_pci_intr __P((void *)); 183 void cmd646_9_irqack __P((struct channel_softc *)); 184 void cmd680_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void cmd680_setup_channel __P((struct channel_softc*)); 186 void cmd680_channel_map __P((struct pci_attach_args *, 187 struct pciide_softc *, int)); 188 189 void cmd3112_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 190 void cmd3112_setup_channel __P((struct channel_softc*)); 191 192 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void cy693_setup_channel __P((struct channel_softc*)); 194 195 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 196 void sis_setup_channel __P((struct channel_softc*)); 197 void sis96x_setup_channel __P((struct channel_softc*)); 198 static int sis_hostbr_match __P(( struct pci_attach_args *)); 199 static int sis_south_match __P(( struct pci_attach_args *)); 200 201 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 202 void acer_setup_channel __P((struct channel_softc*)); 203 int acer_pci_intr __P((void *)); 204 205 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 206 void pdc202xx_setup_channel __P((struct channel_softc*)); 207 void pdc20268_setup_channel __P((struct channel_softc*)); 208 int pdc202xx_pci_intr __P((void *)); 209 int pdc20265_pci_intr __P((void *)); 210 211 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 212 void opti_setup_channel __P((struct channel_softc*)); 213 214 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 215 void hpt_setup_channel __P((struct channel_softc*)); 216 int hpt_pci_intr __P((void *)); 217 218 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 219 void acard_setup_channel __P((struct channel_softc*)); 220 int acard_pci_intr __P((void *)); 221 222 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 223 void serverworks_setup_channel __P((struct channel_softc*)); 224 int serverworks_pci_intr __P((void *)); 225 226 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 227 void sl82c105_setup_channel __P((struct channel_softc*)); 228 229 void pciide_channel_dma_setup __P((struct pciide_channel *)); 230 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 231 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 232 void pciide_dma_start __P((void*, int, int)); 233 int pciide_dma_finish __P((void*, int, int, int)); 234 void pciide_irqack __P((struct channel_softc *)); 235 void pciide_print_modes __P((struct pciide_channel *)); 236 237 void artisea_chip_map __P((struct pciide_softc*, struct pci_attach_args *)); 238 239 struct pciide_product_desc { 240 u_int32_t ide_product; 241 int ide_flags; 242 const char *ide_name; 243 /* map and setup chip, probe drives */ 244 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 245 }; 246 247 /* Flags for ide_flags */ 248 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 249 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 250 251 /* Default product description for devices not known from this controller */ 252 const struct pciide_product_desc default_product_desc = { 253 0, 254 0, 255 "Generic PCI IDE controller", 256 default_chip_map, 257 }; 258 259 const struct pciide_product_desc pciide_intel_products[] = { 260 { PCI_PRODUCT_INTEL_82092AA, 261 0, 262 "Intel 82092AA IDE controller", 263 default_chip_map, 264 }, 265 { PCI_PRODUCT_INTEL_82371FB_IDE, 266 0, 267 "Intel 82371FB IDE controller (PIIX)", 268 piix_chip_map, 269 }, 270 { PCI_PRODUCT_INTEL_82371SB_IDE, 271 0, 272 "Intel 82371SB IDE Interface (PIIX3)", 273 piix_chip_map, 274 }, 275 { PCI_PRODUCT_INTEL_82371AB_IDE, 276 0, 277 "Intel 82371AB IDE controller (PIIX4)", 278 piix_chip_map, 279 }, 280 { PCI_PRODUCT_INTEL_82440MX_IDE, 281 0, 282 "Intel 82440MX IDE controller", 283 piix_chip_map 284 }, 285 { PCI_PRODUCT_INTEL_82801AA_IDE, 286 0, 287 "Intel 82801AA IDE Controller (ICH)", 288 piix_chip_map, 289 }, 290 { PCI_PRODUCT_INTEL_82801AB_IDE, 291 0, 292 "Intel 82801AB IDE Controller (ICH0)", 293 piix_chip_map, 294 }, 295 { PCI_PRODUCT_INTEL_82801BA_IDE, 296 0, 297 "Intel 82801BA IDE Controller (ICH2)", 298 piix_chip_map, 299 }, 300 { PCI_PRODUCT_INTEL_82801BAM_IDE, 301 0, 302 "Intel 82801BAM IDE Controller (ICH2)", 303 piix_chip_map, 304 }, 305 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 306 0, 307 "Intel 82801CA IDE Controller", 308 piix_chip_map, 309 }, 310 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 311 0, 312 "Intel 82801CA IDE Controller", 313 piix_chip_map, 314 }, 315 { PCI_PRODUCT_INTEL_82801DB_IDE, 316 0, 317 "Intel 82801DB IDE Controller (ICH4)", 318 piix_chip_map, 319 }, 320 { PCI_PRODUCT_INTEL_31244, 321 0, 322 "Intel 31244 Serial ATA Controller", 323 artisea_chip_map, 324 }, 325 { 0, 326 0, 327 NULL, 328 NULL 329 } 330 }; 331 332 const struct pciide_product_desc pciide_amd_products[] = { 333 { PCI_PRODUCT_AMD_PBC756_IDE, 334 0, 335 "Advanced Micro Devices AMD756 IDE Controller", 336 amd7x6_chip_map 337 }, 338 { PCI_PRODUCT_AMD_PBC766_IDE, 339 0, 340 "Advanced Micro Devices AMD766 IDE Controller", 341 amd7x6_chip_map 342 }, 343 { PCI_PRODUCT_AMD_PBC768_IDE, 344 0, 345 "Advanced Micro Devices AMD768 IDE Controller", 346 amd7x6_chip_map 347 }, 348 { PCI_PRODUCT_AMD_PBC8111_IDE, 349 0, 350 "Advanced Micro Devices AMD8111 IDE Controller", 351 amd7x6_chip_map 352 }, 353 { 0, 354 0, 355 NULL, 356 NULL 357 } 358 }; 359 360 const struct pciide_product_desc pciide_nvidia_products[] = { 361 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 362 0, 363 "NVIDIA nForce IDE Controller", 364 amd7x6_chip_map 365 }, 366 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 367 0, 368 "NVIDIA nForce2 IDE Controller", 369 amd7x6_chip_map 370 }, 371 { 0, 372 0, 373 NULL, 374 NULL 375 } 376 }; 377 378 const struct pciide_product_desc pciide_cmd_products[] = { 379 { PCI_PRODUCT_CMDTECH_640, 380 0, 381 "CMD Technology PCI0640", 382 cmd_chip_map 383 }, 384 { PCI_PRODUCT_CMDTECH_643, 385 0, 386 "CMD Technology PCI0643", 387 cmd0643_9_chip_map, 388 }, 389 { PCI_PRODUCT_CMDTECH_646, 390 0, 391 "CMD Technology PCI0646", 392 cmd0643_9_chip_map, 393 }, 394 { PCI_PRODUCT_CMDTECH_648, 395 IDE_PCI_CLASS_OVERRIDE, 396 "CMD Technology PCI0648", 397 cmd0643_9_chip_map, 398 }, 399 { PCI_PRODUCT_CMDTECH_649, 400 IDE_PCI_CLASS_OVERRIDE, 401 "CMD Technology PCI0649", 402 cmd0643_9_chip_map, 403 }, 404 { PCI_PRODUCT_CMDTECH_680, 405 IDE_PCI_CLASS_OVERRIDE, 406 "Silicon Image 0680", 407 cmd680_chip_map, 408 }, 409 { PCI_PRODUCT_CMDTECH_3112, 410 IDE_PCI_CLASS_OVERRIDE, 411 "Silicon Image SATALink 3112", 412 cmd3112_chip_map, 413 }, 414 { 0, 415 0, 416 NULL, 417 NULL 418 } 419 }; 420 421 const struct pciide_product_desc pciide_via_products[] = { 422 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 423 0, 424 NULL, 425 apollo_chip_map, 426 }, 427 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 428 0, 429 NULL, 430 apollo_chip_map, 431 }, 432 { 0, 433 0, 434 NULL, 435 NULL 436 } 437 }; 438 439 const struct pciide_product_desc pciide_cypress_products[] = { 440 { PCI_PRODUCT_CONTAQ_82C693, 441 IDE_16BIT_IOSPACE, 442 "Cypress 82C693 IDE Controller", 443 cy693_chip_map, 444 }, 445 { 0, 446 0, 447 NULL, 448 NULL 449 } 450 }; 451 452 const struct pciide_product_desc pciide_sis_products[] = { 453 { PCI_PRODUCT_SIS_5597_IDE, 454 0, 455 NULL, 456 sis_chip_map, 457 }, 458 { 0, 459 0, 460 NULL, 461 NULL 462 } 463 }; 464 465 const struct pciide_product_desc pciide_acer_products[] = { 466 { PCI_PRODUCT_ALI_M5229, 467 0, 468 "Acer Labs M5229 UDMA IDE Controller", 469 acer_chip_map, 470 }, 471 { 0, 472 0, 473 NULL, 474 NULL 475 } 476 }; 477 478 const struct pciide_product_desc pciide_promise_products[] = { 479 { PCI_PRODUCT_PROMISE_ULTRA33, 480 IDE_PCI_CLASS_OVERRIDE, 481 "Promise Ultra33/ATA Bus Master IDE Accelerator", 482 pdc202xx_chip_map, 483 }, 484 { PCI_PRODUCT_PROMISE_ULTRA66, 485 IDE_PCI_CLASS_OVERRIDE, 486 "Promise Ultra66/ATA Bus Master IDE Accelerator", 487 pdc202xx_chip_map, 488 }, 489 { PCI_PRODUCT_PROMISE_ULTRA100, 490 IDE_PCI_CLASS_OVERRIDE, 491 "Promise Ultra100/ATA Bus Master IDE Accelerator", 492 pdc202xx_chip_map, 493 }, 494 { PCI_PRODUCT_PROMISE_ULTRA100X, 495 IDE_PCI_CLASS_OVERRIDE, 496 "Promise Ultra100/ATA Bus Master IDE Accelerator", 497 pdc202xx_chip_map, 498 }, 499 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 500 IDE_PCI_CLASS_OVERRIDE, 501 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 502 pdc202xx_chip_map, 503 }, 504 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 505 IDE_PCI_CLASS_OVERRIDE, 506 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 507 pdc202xx_chip_map, 508 }, 509 { PCI_PRODUCT_PROMISE_ULTRA133, 510 IDE_PCI_CLASS_OVERRIDE, 511 "Promise Ultra133/ATA Bus Master IDE Accelerator", 512 pdc202xx_chip_map, 513 }, 514 { PCI_PRODUCT_PROMISE_ULTRA133TX2, 515 IDE_PCI_CLASS_OVERRIDE, 516 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 517 pdc202xx_chip_map, 518 }, 519 { PCI_PRODUCT_PROMISE_MBULTRA133, 520 IDE_PCI_CLASS_OVERRIDE, 521 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 522 pdc202xx_chip_map, 523 }, 524 { PCI_PRODUCT_PROMISE_ULTRA133TX2v2, 525 IDE_PCI_CLASS_OVERRIDE, 526 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 527 pdc202xx_chip_map, 528 }, 529 { PCI_PRODUCT_PROMISE_FASTTRAK133LITE, 530 IDE_PCI_CLASS_OVERRIDE, 531 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 532 pdc202xx_chip_map, 533 }, 534 { PCI_PRODUCT_PROMISE_SATA150TX2PLUS, 535 IDE_PCI_CLASS_OVERRIDE, 536 "Promise Serial ATA/150 TX2plus Bus Master IDE Accelerator", 537 pdc202xx_chip_map, 538 }, 539 { 0, 540 0, 541 NULL, 542 NULL 543 } 544 }; 545 546 const struct pciide_product_desc pciide_opti_products[] = { 547 { PCI_PRODUCT_OPTI_82C621, 548 0, 549 "OPTi 82c621 PCI IDE controller", 550 opti_chip_map, 551 }, 552 { PCI_PRODUCT_OPTI_82C568, 553 0, 554 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 555 opti_chip_map, 556 }, 557 { PCI_PRODUCT_OPTI_82D568, 558 0, 559 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 560 opti_chip_map, 561 }, 562 { 0, 563 0, 564 NULL, 565 NULL 566 } 567 }; 568 569 const struct pciide_product_desc pciide_triones_products[] = { 570 { PCI_PRODUCT_TRIONES_HPT366, 571 IDE_PCI_CLASS_OVERRIDE, 572 NULL, 573 hpt_chip_map, 574 }, 575 { PCI_PRODUCT_TRIONES_HPT372, 576 IDE_PCI_CLASS_OVERRIDE, 577 NULL, 578 hpt_chip_map 579 }, 580 { PCI_PRODUCT_TRIONES_HPT374, 581 IDE_PCI_CLASS_OVERRIDE, 582 NULL, 583 hpt_chip_map 584 }, 585 { 0, 586 0, 587 NULL, 588 NULL 589 } 590 }; 591 592 const struct pciide_product_desc pciide_acard_products[] = { 593 { PCI_PRODUCT_ACARD_ATP850U, 594 IDE_PCI_CLASS_OVERRIDE, 595 "Acard ATP850U Ultra33 IDE Controller", 596 acard_chip_map, 597 }, 598 { PCI_PRODUCT_ACARD_ATP860, 599 IDE_PCI_CLASS_OVERRIDE, 600 "Acard ATP860 Ultra66 IDE Controller", 601 acard_chip_map, 602 }, 603 { PCI_PRODUCT_ACARD_ATP860A, 604 IDE_PCI_CLASS_OVERRIDE, 605 "Acard ATP860-A Ultra66 IDE Controller", 606 acard_chip_map, 607 }, 608 { 0, 609 0, 610 NULL, 611 NULL 612 } 613 }; 614 615 const struct pciide_product_desc pciide_serverworks_products[] = { 616 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 617 0, 618 "ServerWorks OSB4 IDE Controller", 619 serverworks_chip_map, 620 }, 621 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 622 0, 623 "ServerWorks CSB5 IDE Controller", 624 serverworks_chip_map, 625 }, 626 { PCI_PRODUCT_SERVERWORKS_CSB6_IDE, 627 0, 628 "ServerWorks CSB6 RAID/IDE Controller", 629 serverworks_chip_map, 630 }, 631 { 0, 632 0, 633 NULL, 634 } 635 }; 636 637 const struct pciide_product_desc pciide_symphony_products[] = { 638 { PCI_PRODUCT_SYMPHONY_82C105, 639 0, 640 "Symphony Labs 82C105 IDE controller", 641 sl82c105_chip_map, 642 }, 643 { 0, 644 0, 645 NULL, 646 } 647 }; 648 649 const struct pciide_product_desc pciide_winbond_products[] = { 650 { PCI_PRODUCT_WINBOND_W83C553F_1, 651 0, 652 "Winbond W83C553F IDE controller", 653 sl82c105_chip_map, 654 }, 655 { 0, 656 0, 657 NULL, 658 } 659 }; 660 661 struct pciide_vendor_desc { 662 u_int32_t ide_vendor; 663 const struct pciide_product_desc *ide_products; 664 }; 665 666 const struct pciide_vendor_desc pciide_vendors[] = { 667 { PCI_VENDOR_INTEL, pciide_intel_products }, 668 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 669 { PCI_VENDOR_VIATECH, pciide_via_products }, 670 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 671 { PCI_VENDOR_SIS, pciide_sis_products }, 672 { PCI_VENDOR_ALI, pciide_acer_products }, 673 { PCI_VENDOR_PROMISE, pciide_promise_products }, 674 { PCI_VENDOR_AMD, pciide_amd_products }, 675 { PCI_VENDOR_OPTI, pciide_opti_products }, 676 { PCI_VENDOR_TRIONES, pciide_triones_products }, 677 { PCI_VENDOR_ACARD, pciide_acard_products }, 678 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 679 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 680 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 681 { PCI_VENDOR_NVIDIA, pciide_nvidia_products }, 682 { 0, NULL } 683 }; 684 685 /* options passed via the 'flags' config keyword */ 686 #define PCIIDE_OPTIONS_DMA 0x01 687 #define PCIIDE_OPTIONS_NODMA 0x02 688 689 int pciide_match __P((struct device *, struct cfdata *, void *)); 690 void pciide_attach __P((struct device *, struct device *, void *)); 691 692 CFATTACH_DECL(pciide, sizeof(struct pciide_softc), 693 pciide_match, pciide_attach, NULL, NULL); 694 695 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 696 int pciide_mapregs_compat __P(( struct pci_attach_args *, 697 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 698 int pciide_mapregs_native __P((struct pci_attach_args *, 699 struct pciide_channel *, bus_size_t *, bus_size_t *, 700 int (*pci_intr) __P((void *)))); 701 void pciide_mapreg_dma __P((struct pciide_softc *, 702 struct pci_attach_args *)); 703 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 704 void pciide_mapchan __P((struct pci_attach_args *, 705 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 706 int (*pci_intr) __P((void *)))); 707 int pciide_chan_candisable __P((struct pciide_channel *)); 708 void pciide_map_compat_intr __P(( struct pci_attach_args *, 709 struct pciide_channel *, int, int)); 710 int pciide_compat_intr __P((void *)); 711 int pciide_pci_intr __P((void *)); 712 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 713 714 const struct pciide_product_desc * 715 pciide_lookup_product(id) 716 u_int32_t id; 717 { 718 const struct pciide_product_desc *pp; 719 const struct pciide_vendor_desc *vp; 720 721 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 722 if (PCI_VENDOR(id) == vp->ide_vendor) 723 break; 724 725 if ((pp = vp->ide_products) == NULL) 726 return NULL; 727 728 for (; pp->chip_map != NULL; pp++) 729 if (PCI_PRODUCT(id) == pp->ide_product) 730 break; 731 732 if (pp->chip_map == NULL) 733 return NULL; 734 return pp; 735 } 736 737 int 738 pciide_match(parent, match, aux) 739 struct device *parent; 740 struct cfdata *match; 741 void *aux; 742 { 743 struct pci_attach_args *pa = aux; 744 const struct pciide_product_desc *pp; 745 746 /* 747 * Check the ID register to see that it's a PCI IDE controller. 748 * If it is, we assume that we can deal with it; it _should_ 749 * work in a standardized way... 750 */ 751 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 752 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 753 return (1); 754 } 755 756 /* 757 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 758 * controllers. Let see if we can deal with it anyway. 759 */ 760 pp = pciide_lookup_product(pa->pa_id); 761 if (pp != NULL && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 762 return (1); 763 } 764 765 return (0); 766 } 767 768 void 769 pciide_attach(parent, self, aux) 770 struct device *parent, *self; 771 void *aux; 772 { 773 struct pci_attach_args *pa = aux; 774 pci_chipset_tag_t pc = pa->pa_pc; 775 pcitag_t tag = pa->pa_tag; 776 struct pciide_softc *sc = (struct pciide_softc *)self; 777 pcireg_t csr; 778 char devinfo[256]; 779 const char *displaydev; 780 781 sc->sc_pci_vendor = PCI_VENDOR(pa->pa_id); 782 sc->sc_pp = pciide_lookup_product(pa->pa_id); 783 if (sc->sc_pp == NULL) { 784 sc->sc_pp = &default_product_desc; 785 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 786 displaydev = devinfo; 787 } else 788 displaydev = sc->sc_pp->ide_name; 789 790 /* if displaydev == NULL, printf is done in chip-specific map */ 791 if (displaydev) 792 printf(": %s (rev. 0x%02x)\n", displaydev, 793 PCI_REVISION(pa->pa_class)); 794 795 sc->sc_pc = pa->pa_pc; 796 sc->sc_tag = pa->pa_tag; 797 798 /* Set up DMA defaults; these might be adjusted by chip_map. */ 799 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 800 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 801 802 #ifdef WDCDEBUG 803 if (wdcdebug_pciide_mask & DEBUG_PROBE) 804 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 805 #endif 806 sc->sc_pp->chip_map(sc, pa); 807 808 if (sc->sc_dma_ok) { 809 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 810 csr |= PCI_COMMAND_MASTER_ENABLE; 811 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 812 } 813 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 814 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 815 } 816 817 /* tell whether the chip is enabled or not */ 818 int 819 pciide_chipen(sc, pa) 820 struct pciide_softc *sc; 821 struct pci_attach_args *pa; 822 { 823 pcireg_t csr; 824 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 825 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 826 PCI_COMMAND_STATUS_REG); 827 printf("%s: device disabled (at %s)\n", 828 sc->sc_wdcdev.sc_dev.dv_xname, 829 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 830 "device" : "bridge"); 831 return 0; 832 } 833 return 1; 834 } 835 836 int 837 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 838 struct pci_attach_args *pa; 839 struct pciide_channel *cp; 840 int compatchan; 841 bus_size_t *cmdsizep, *ctlsizep; 842 { 843 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 844 struct channel_softc *wdc_cp = &cp->wdc_channel; 845 846 cp->compat = 1; 847 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 848 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 849 850 wdc_cp->cmd_iot = pa->pa_iot; 851 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 852 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 853 printf("%s: couldn't map %s channel cmd regs\n", 854 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 855 return (0); 856 } 857 858 wdc_cp->ctl_iot = pa->pa_iot; 859 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 860 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 861 printf("%s: couldn't map %s channel ctl regs\n", 862 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 863 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 864 PCIIDE_COMPAT_CMD_SIZE); 865 return (0); 866 } 867 868 return (1); 869 } 870 871 int 872 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 873 struct pci_attach_args * pa; 874 struct pciide_channel *cp; 875 bus_size_t *cmdsizep, *ctlsizep; 876 int (*pci_intr) __P((void *)); 877 { 878 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 879 struct channel_softc *wdc_cp = &cp->wdc_channel; 880 const char *intrstr; 881 pci_intr_handle_t intrhandle; 882 883 cp->compat = 0; 884 885 if (sc->sc_pci_ih == NULL) { 886 if (pci_intr_map(pa, &intrhandle) != 0) { 887 printf("%s: couldn't map native-PCI interrupt\n", 888 sc->sc_wdcdev.sc_dev.dv_xname); 889 return 0; 890 } 891 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 892 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 893 intrhandle, IPL_BIO, pci_intr, sc); 894 if (sc->sc_pci_ih != NULL) { 895 printf("%s: using %s for native-PCI interrupt\n", 896 sc->sc_wdcdev.sc_dev.dv_xname, 897 intrstr ? intrstr : "unknown interrupt"); 898 } else { 899 printf("%s: couldn't establish native-PCI interrupt", 900 sc->sc_wdcdev.sc_dev.dv_xname); 901 if (intrstr != NULL) 902 printf(" at %s", intrstr); 903 printf("\n"); 904 return 0; 905 } 906 } 907 cp->ih = sc->sc_pci_ih; 908 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 909 PCI_MAPREG_TYPE_IO, 0, 910 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 911 printf("%s: couldn't map %s channel cmd regs\n", 912 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 913 return 0; 914 } 915 916 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 917 PCI_MAPREG_TYPE_IO, 0, 918 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 919 printf("%s: couldn't map %s channel ctl regs\n", 920 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 921 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 922 return 0; 923 } 924 /* 925 * In native mode, 4 bytes of I/O space are mapped for the control 926 * register, the control register is at offset 2. Pass the generic 927 * code a handle for only one byte at the right offset. 928 */ 929 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 930 &wdc_cp->ctl_ioh) != 0) { 931 printf("%s: unable to subregion %s channel ctl regs\n", 932 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 933 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 934 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 935 return 0; 936 } 937 return (1); 938 } 939 940 void 941 pciide_mapreg_dma(sc, pa) 942 struct pciide_softc *sc; 943 struct pci_attach_args *pa; 944 { 945 pcireg_t maptype; 946 bus_addr_t addr; 947 948 /* 949 * Map DMA registers 950 * 951 * Note that sc_dma_ok is the right variable to test to see if 952 * DMA can be done. If the interface doesn't support DMA, 953 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 954 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 955 * non-zero if the interface supports DMA and the registers 956 * could be mapped. 957 * 958 * XXX Note that despite the fact that the Bus Master IDE specs 959 * XXX say that "The bus master IDE function uses 16 bytes of IO 960 * XXX space," some controllers (at least the United 961 * XXX Microelectronics UM8886BF) place it in memory space. 962 */ 963 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 964 PCIIDE_REG_BUS_MASTER_DMA); 965 966 switch (maptype) { 967 case PCI_MAPREG_TYPE_IO: 968 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 969 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 970 &addr, NULL, NULL) == 0); 971 if (sc->sc_dma_ok == 0) { 972 printf(", but unused (couldn't query registers)"); 973 break; 974 } 975 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 976 && addr >= 0x10000) { 977 sc->sc_dma_ok = 0; 978 printf(", but unused (registers at unsafe address " 979 "%#lx)", (unsigned long)addr); 980 break; 981 } 982 /* FALLTHROUGH */ 983 984 case PCI_MAPREG_MEM_TYPE_32BIT: 985 sc->sc_dma_ok = (pci_mapreg_map(pa, 986 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 987 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 988 sc->sc_dmat = pa->pa_dmat; 989 if (sc->sc_dma_ok == 0) { 990 printf(", but unused (couldn't map registers)"); 991 } else { 992 sc->sc_wdcdev.dma_arg = sc; 993 sc->sc_wdcdev.dma_init = pciide_dma_init; 994 sc->sc_wdcdev.dma_start = pciide_dma_start; 995 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 996 } 997 998 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 999 PCIIDE_OPTIONS_NODMA) { 1000 printf(", but unused (forced off by config file)"); 1001 sc->sc_dma_ok = 0; 1002 } 1003 break; 1004 1005 default: 1006 sc->sc_dma_ok = 0; 1007 printf(", but unsupported register maptype (0x%x)", maptype); 1008 } 1009 } 1010 1011 int 1012 pciide_compat_intr(arg) 1013 void *arg; 1014 { 1015 struct pciide_channel *cp = arg; 1016 1017 #ifdef DIAGNOSTIC 1018 /* should only be called for a compat channel */ 1019 if (cp->compat == 0) 1020 panic("pciide compat intr called for non-compat chan %p", cp); 1021 #endif 1022 return (wdcintr(&cp->wdc_channel)); 1023 } 1024 1025 int 1026 pciide_pci_intr(arg) 1027 void *arg; 1028 { 1029 struct pciide_softc *sc = arg; 1030 struct pciide_channel *cp; 1031 struct channel_softc *wdc_cp; 1032 int i, rv, crv; 1033 1034 rv = 0; 1035 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1036 cp = &sc->pciide_channels[i]; 1037 wdc_cp = &cp->wdc_channel; 1038 1039 /* If a compat channel skip. */ 1040 if (cp->compat) 1041 continue; 1042 /* if this channel not waiting for intr, skip */ 1043 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 1044 continue; 1045 1046 crv = wdcintr(wdc_cp); 1047 if (crv == 0) 1048 ; /* leave rv alone */ 1049 else if (crv == 1) 1050 rv = 1; /* claim the intr */ 1051 else if (rv == 0) /* crv should be -1 in this case */ 1052 rv = crv; /* if we've done no better, take it */ 1053 } 1054 return (rv); 1055 } 1056 1057 void 1058 pciide_channel_dma_setup(cp) 1059 struct pciide_channel *cp; 1060 { 1061 int drive; 1062 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1063 struct ata_drive_datas *drvp; 1064 1065 for (drive = 0; drive < 2; drive++) { 1066 drvp = &cp->wdc_channel.ch_drive[drive]; 1067 /* If no drive, skip */ 1068 if ((drvp->drive_flags & DRIVE) == 0) 1069 continue; 1070 /* setup DMA if needed */ 1071 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1072 (drvp->drive_flags & DRIVE_UDMA) == 0) || 1073 sc->sc_dma_ok == 0) { 1074 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1075 continue; 1076 } 1077 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 1078 != 0) { 1079 /* Abort DMA setup */ 1080 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1081 continue; 1082 } 1083 } 1084 } 1085 1086 int 1087 pciide_dma_table_setup(sc, channel, drive) 1088 struct pciide_softc *sc; 1089 int channel, drive; 1090 { 1091 bus_dma_segment_t seg; 1092 int error, rseg; 1093 const bus_size_t dma_table_size = 1094 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1095 struct pciide_dma_maps *dma_maps = 1096 &sc->pciide_channels[channel].dma_maps[drive]; 1097 1098 /* If table was already allocated, just return */ 1099 if (dma_maps->dma_table) 1100 return 0; 1101 1102 /* Allocate memory for the DMA tables and map it */ 1103 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1104 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1105 BUS_DMA_NOWAIT)) != 0) { 1106 printf("%s:%d: unable to allocate table DMA for " 1107 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1108 channel, drive, error); 1109 return error; 1110 } 1111 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1112 dma_table_size, 1113 (caddr_t *)&dma_maps->dma_table, 1114 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1115 printf("%s:%d: unable to map table DMA for" 1116 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1117 channel, drive, error); 1118 return error; 1119 } 1120 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1121 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1122 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1123 1124 /* Create and load table DMA map for this disk */ 1125 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1126 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1127 &dma_maps->dmamap_table)) != 0) { 1128 printf("%s:%d: unable to create table DMA map for " 1129 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1130 channel, drive, error); 1131 return error; 1132 } 1133 if ((error = bus_dmamap_load(sc->sc_dmat, 1134 dma_maps->dmamap_table, 1135 dma_maps->dma_table, 1136 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1137 printf("%s:%d: unable to load table DMA map for " 1138 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1139 channel, drive, error); 1140 return error; 1141 } 1142 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1143 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1144 DEBUG_PROBE); 1145 /* Create a xfer DMA map for this drive */ 1146 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1147 NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 1148 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1149 &dma_maps->dmamap_xfer)) != 0) { 1150 printf("%s:%d: unable to create xfer DMA map for " 1151 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1152 channel, drive, error); 1153 return error; 1154 } 1155 return 0; 1156 } 1157 1158 int 1159 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1160 void *v; 1161 int channel, drive; 1162 void *databuf; 1163 size_t datalen; 1164 int flags; 1165 { 1166 struct pciide_softc *sc = v; 1167 int error, seg; 1168 struct pciide_dma_maps *dma_maps = 1169 &sc->pciide_channels[channel].dma_maps[drive]; 1170 1171 error = bus_dmamap_load(sc->sc_dmat, 1172 dma_maps->dmamap_xfer, 1173 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1174 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1175 if (error) { 1176 printf("%s:%d: unable to load xfer DMA map for" 1177 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1178 channel, drive, error); 1179 return error; 1180 } 1181 1182 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1183 dma_maps->dmamap_xfer->dm_mapsize, 1184 (flags & WDC_DMA_READ) ? 1185 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1186 1187 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1188 #ifdef DIAGNOSTIC 1189 /* A segment must not cross a 64k boundary */ 1190 { 1191 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1192 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1193 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1194 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1195 printf("pciide_dma: segment %d physical addr 0x%lx" 1196 " len 0x%lx not properly aligned\n", 1197 seg, phys, len); 1198 panic("pciide_dma: buf align"); 1199 } 1200 } 1201 #endif 1202 dma_maps->dma_table[seg].base_addr = 1203 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1204 dma_maps->dma_table[seg].byte_count = 1205 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1206 IDEDMA_BYTE_COUNT_MASK); 1207 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1208 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1209 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1210 1211 } 1212 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1213 htole32(IDEDMA_BYTE_COUNT_EOT); 1214 1215 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1216 dma_maps->dmamap_table->dm_mapsize, 1217 BUS_DMASYNC_PREWRITE); 1218 1219 /* Maps are ready. Start DMA function */ 1220 #ifdef DIAGNOSTIC 1221 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1222 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1223 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1224 panic("pciide_dma_init: table align"); 1225 } 1226 #endif 1227 1228 /* Clear status bits */ 1229 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1230 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1231 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1232 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1233 /* Write table addr */ 1234 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1235 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1236 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1237 /* set read/write */ 1238 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1239 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1240 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1241 /* remember flags */ 1242 dma_maps->dma_flags = flags; 1243 return 0; 1244 } 1245 1246 void 1247 pciide_dma_start(v, channel, drive) 1248 void *v; 1249 int channel, drive; 1250 { 1251 struct pciide_softc *sc = v; 1252 1253 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1254 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1255 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1256 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1257 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1258 } 1259 1260 int 1261 pciide_dma_finish(v, channel, drive, force) 1262 void *v; 1263 int channel, drive; 1264 int force; 1265 { 1266 struct pciide_softc *sc = v; 1267 u_int8_t status; 1268 int error = 0; 1269 struct pciide_dma_maps *dma_maps = 1270 &sc->pciide_channels[channel].dma_maps[drive]; 1271 1272 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1273 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1274 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1275 DEBUG_XFERS); 1276 1277 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1278 return WDC_DMAST_NOIRQ; 1279 1280 /* stop DMA channel */ 1281 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1282 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1283 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1284 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1285 1286 /* Unload the map of the data buffer */ 1287 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1288 dma_maps->dmamap_xfer->dm_mapsize, 1289 (dma_maps->dma_flags & WDC_DMA_READ) ? 1290 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1291 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1292 1293 if ((status & IDEDMA_CTL_ERR) != 0) { 1294 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1295 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1296 error |= WDC_DMAST_ERR; 1297 } 1298 1299 if ((status & IDEDMA_CTL_INTR) == 0) { 1300 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1301 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1302 drive, status); 1303 error |= WDC_DMAST_NOIRQ; 1304 } 1305 1306 if ((status & IDEDMA_CTL_ACT) != 0) { 1307 /* data underrun, may be a valid condition for ATAPI */ 1308 error |= WDC_DMAST_UNDER; 1309 } 1310 return error; 1311 } 1312 1313 void 1314 pciide_irqack(chp) 1315 struct channel_softc *chp; 1316 { 1317 struct pciide_channel *cp = (struct pciide_channel*)chp; 1318 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1319 1320 /* clear status bits in IDE DMA registers */ 1321 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1322 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1323 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1324 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1325 } 1326 1327 /* some common code used by several chip_map */ 1328 int 1329 pciide_chansetup(sc, channel, interface) 1330 struct pciide_softc *sc; 1331 int channel; 1332 pcireg_t interface; 1333 { 1334 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1335 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1336 cp->name = PCIIDE_CHANNEL_NAME(channel); 1337 cp->wdc_channel.channel = channel; 1338 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1339 cp->wdc_channel.ch_queue = 1340 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1341 if (cp->wdc_channel.ch_queue == NULL) { 1342 printf("%s %s channel: " 1343 "can't allocate memory for command queue", 1344 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1345 return 0; 1346 } 1347 printf("%s: %s channel %s to %s mode\n", 1348 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1349 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1350 "configured" : "wired", 1351 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1352 "native-PCI" : "compatibility"); 1353 return 1; 1354 } 1355 1356 /* some common code used by several chip channel_map */ 1357 void 1358 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1359 struct pci_attach_args *pa; 1360 struct pciide_channel *cp; 1361 pcireg_t interface; 1362 bus_size_t *cmdsizep, *ctlsizep; 1363 int (*pci_intr) __P((void *)); 1364 { 1365 struct channel_softc *wdc_cp = &cp->wdc_channel; 1366 1367 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1368 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1369 pci_intr); 1370 else 1371 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1372 wdc_cp->channel, cmdsizep, ctlsizep); 1373 1374 if (cp->hw_ok == 0) 1375 return; 1376 wdc_cp->data32iot = wdc_cp->cmd_iot; 1377 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1378 wdcattach(wdc_cp); 1379 } 1380 1381 /* 1382 * Generic code to call to know if a channel can be disabled. Return 1 1383 * if channel can be disabled, 0 if not 1384 */ 1385 int 1386 pciide_chan_candisable(cp) 1387 struct pciide_channel *cp; 1388 { 1389 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1390 struct channel_softc *wdc_cp = &cp->wdc_channel; 1391 1392 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1393 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1394 printf("%s: disabling %s channel (no drives)\n", 1395 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1396 cp->hw_ok = 0; 1397 return 1; 1398 } 1399 return 0; 1400 } 1401 1402 /* 1403 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1404 * Set hw_ok=0 on failure 1405 */ 1406 void 1407 pciide_map_compat_intr(pa, cp, compatchan, interface) 1408 struct pci_attach_args *pa; 1409 struct pciide_channel *cp; 1410 int compatchan, interface; 1411 { 1412 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1413 struct channel_softc *wdc_cp = &cp->wdc_channel; 1414 1415 if (cp->hw_ok == 0) 1416 return; 1417 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1418 return; 1419 1420 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1421 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1422 pa, compatchan, pciide_compat_intr, cp); 1423 if (cp->ih == NULL) { 1424 #endif 1425 printf("%s: no compatibility interrupt for use by %s " 1426 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1427 cp->hw_ok = 0; 1428 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1429 } 1430 #endif 1431 } 1432 1433 void 1434 pciide_print_modes(cp) 1435 struct pciide_channel *cp; 1436 { 1437 wdc_print_modes(&cp->wdc_channel); 1438 } 1439 1440 void 1441 default_chip_map(sc, pa) 1442 struct pciide_softc *sc; 1443 struct pci_attach_args *pa; 1444 { 1445 struct pciide_channel *cp; 1446 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1447 pcireg_t csr; 1448 int channel, drive; 1449 struct ata_drive_datas *drvp; 1450 u_int8_t idedma_ctl; 1451 bus_size_t cmdsize, ctlsize; 1452 char *failreason; 1453 1454 if (pciide_chipen(sc, pa) == 0) 1455 return; 1456 1457 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1458 printf("%s: bus-master DMA support present", 1459 sc->sc_wdcdev.sc_dev.dv_xname); 1460 if (sc->sc_pp == &default_product_desc && 1461 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1462 PCIIDE_OPTIONS_DMA) == 0) { 1463 printf(", but unused (no driver support)"); 1464 sc->sc_dma_ok = 0; 1465 } else { 1466 pciide_mapreg_dma(sc, pa); 1467 if (sc->sc_dma_ok != 0) 1468 printf(", used without full driver " 1469 "support"); 1470 } 1471 } else { 1472 printf("%s: hardware does not support DMA", 1473 sc->sc_wdcdev.sc_dev.dv_xname); 1474 sc->sc_dma_ok = 0; 1475 } 1476 printf("\n"); 1477 if (sc->sc_dma_ok) { 1478 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1479 sc->sc_wdcdev.irqack = pciide_irqack; 1480 } 1481 sc->sc_wdcdev.PIO_cap = 0; 1482 sc->sc_wdcdev.DMA_cap = 0; 1483 1484 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1485 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1486 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1487 1488 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1489 cp = &sc->pciide_channels[channel]; 1490 if (pciide_chansetup(sc, channel, interface) == 0) 1491 continue; 1492 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1493 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1494 &ctlsize, pciide_pci_intr); 1495 } else { 1496 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1497 channel, &cmdsize, &ctlsize); 1498 } 1499 if (cp->hw_ok == 0) 1500 continue; 1501 /* 1502 * Check to see if something appears to be there. 1503 */ 1504 failreason = NULL; 1505 if (!wdcprobe(&cp->wdc_channel)) { 1506 failreason = "not responding; disabled or no drives?"; 1507 goto next; 1508 } 1509 /* 1510 * Now, make sure it's actually attributable to this PCI IDE 1511 * channel by trying to access the channel again while the 1512 * PCI IDE controller's I/O space is disabled. (If the 1513 * channel no longer appears to be there, it belongs to 1514 * this controller.) YUCK! 1515 */ 1516 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1517 PCI_COMMAND_STATUS_REG); 1518 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1519 csr & ~PCI_COMMAND_IO_ENABLE); 1520 if (wdcprobe(&cp->wdc_channel)) 1521 failreason = "other hardware responding at addresses"; 1522 pci_conf_write(sc->sc_pc, sc->sc_tag, 1523 PCI_COMMAND_STATUS_REG, csr); 1524 next: 1525 if (failreason) { 1526 printf("%s: %s channel ignored (%s)\n", 1527 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1528 failreason); 1529 cp->hw_ok = 0; 1530 bus_space_unmap(cp->wdc_channel.cmd_iot, 1531 cp->wdc_channel.cmd_ioh, cmdsize); 1532 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1533 bus_space_unmap(cp->wdc_channel.ctl_iot, 1534 cp->ctl_baseioh, ctlsize); 1535 else 1536 bus_space_unmap(cp->wdc_channel.ctl_iot, 1537 cp->wdc_channel.ctl_ioh, ctlsize); 1538 } else { 1539 pciide_map_compat_intr(pa, cp, channel, interface); 1540 } 1541 if (cp->hw_ok) { 1542 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1543 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1544 wdcattach(&cp->wdc_channel); 1545 } 1546 } 1547 1548 if (sc->sc_dma_ok == 0) 1549 return; 1550 1551 /* Allocate DMA maps */ 1552 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1553 idedma_ctl = 0; 1554 cp = &sc->pciide_channels[channel]; 1555 for (drive = 0; drive < 2; drive++) { 1556 drvp = &cp->wdc_channel.ch_drive[drive]; 1557 /* If no drive, skip */ 1558 if ((drvp->drive_flags & DRIVE) == 0) 1559 continue; 1560 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1561 continue; 1562 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1563 /* Abort DMA setup */ 1564 printf("%s:%d:%d: can't allocate DMA maps, " 1565 "using PIO transfers\n", 1566 sc->sc_wdcdev.sc_dev.dv_xname, 1567 channel, drive); 1568 drvp->drive_flags &= ~DRIVE_DMA; 1569 } 1570 printf("%s:%d:%d: using DMA data transfers\n", 1571 sc->sc_wdcdev.sc_dev.dv_xname, 1572 channel, drive); 1573 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1574 } 1575 if (idedma_ctl != 0) { 1576 /* Add software bits in status register */ 1577 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1578 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1579 idedma_ctl); 1580 } 1581 } 1582 } 1583 1584 void 1585 sata_setup_channel(chp) 1586 struct channel_softc *chp; 1587 { 1588 struct ata_drive_datas *drvp; 1589 int drive; 1590 u_int32_t idedma_ctl; 1591 struct pciide_channel *cp = (struct pciide_channel*)chp; 1592 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 1593 1594 /* setup DMA if needed */ 1595 pciide_channel_dma_setup(cp); 1596 1597 idedma_ctl = 0; 1598 1599 for (drive = 0; drive < 2; drive++) { 1600 drvp = &chp->ch_drive[drive]; 1601 /* If no drive, skip */ 1602 if ((drvp->drive_flags & DRIVE) == 0) 1603 continue; 1604 if (drvp->drive_flags & DRIVE_UDMA) { 1605 /* use Ultra/DMA */ 1606 drvp->drive_flags &= ~DRIVE_DMA; 1607 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1608 } else if (drvp->drive_flags & DRIVE_DMA) { 1609 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1610 } 1611 } 1612 1613 /* 1614 * Nothing to do to setup modes; it is meaningless in S-ATA 1615 * (but many S-ATA drives still want to get the SET_FEATURE 1616 * command). 1617 */ 1618 if (idedma_ctl != 0) { 1619 /* Add software bits in status register */ 1620 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1621 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1622 idedma_ctl); 1623 } 1624 pciide_print_modes(cp); 1625 } 1626 1627 void 1628 piix_chip_map(sc, pa) 1629 struct pciide_softc *sc; 1630 struct pci_attach_args *pa; 1631 { 1632 struct pciide_channel *cp; 1633 int channel; 1634 u_int32_t idetim; 1635 bus_size_t cmdsize, ctlsize; 1636 1637 if (pciide_chipen(sc, pa) == 0) 1638 return; 1639 1640 printf("%s: bus-master DMA support present", 1641 sc->sc_wdcdev.sc_dev.dv_xname); 1642 pciide_mapreg_dma(sc, pa); 1643 printf("\n"); 1644 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1645 WDC_CAPABILITY_MODE; 1646 if (sc->sc_dma_ok) { 1647 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1648 sc->sc_wdcdev.irqack = pciide_irqack; 1649 switch(sc->sc_pp->ide_product) { 1650 case PCI_PRODUCT_INTEL_82371AB_IDE: 1651 case PCI_PRODUCT_INTEL_82440MX_IDE: 1652 case PCI_PRODUCT_INTEL_82801AA_IDE: 1653 case PCI_PRODUCT_INTEL_82801AB_IDE: 1654 case PCI_PRODUCT_INTEL_82801BA_IDE: 1655 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1656 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1657 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1658 case PCI_PRODUCT_INTEL_82801DB_IDE: 1659 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1660 } 1661 } 1662 sc->sc_wdcdev.PIO_cap = 4; 1663 sc->sc_wdcdev.DMA_cap = 2; 1664 switch(sc->sc_pp->ide_product) { 1665 case PCI_PRODUCT_INTEL_82801AA_IDE: 1666 sc->sc_wdcdev.UDMA_cap = 4; 1667 break; 1668 case PCI_PRODUCT_INTEL_82801BA_IDE: 1669 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1670 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1671 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1672 case PCI_PRODUCT_INTEL_82801DB_IDE: 1673 sc->sc_wdcdev.UDMA_cap = 5; 1674 break; 1675 default: 1676 sc->sc_wdcdev.UDMA_cap = 2; 1677 } 1678 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1679 sc->sc_wdcdev.set_modes = piix_setup_channel; 1680 else 1681 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1682 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1683 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1684 1685 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1686 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1687 DEBUG_PROBE); 1688 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1689 WDCDEBUG_PRINT((", sidetim=0x%x", 1690 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1691 DEBUG_PROBE); 1692 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1693 WDCDEBUG_PRINT((", udamreg 0x%x", 1694 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1695 DEBUG_PROBE); 1696 } 1697 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1698 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1699 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1700 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1701 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1702 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1703 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1704 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1705 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1706 DEBUG_PROBE); 1707 } 1708 1709 } 1710 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1711 1712 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1713 cp = &sc->pciide_channels[channel]; 1714 /* PIIX is compat-only */ 1715 if (pciide_chansetup(sc, channel, 0) == 0) 1716 continue; 1717 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1718 if ((PIIX_IDETIM_READ(idetim, channel) & 1719 PIIX_IDETIM_IDE) == 0) { 1720 printf("%s: %s channel ignored (disabled)\n", 1721 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1722 continue; 1723 } 1724 /* PIIX are compat-only pciide devices */ 1725 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1726 if (cp->hw_ok == 0) 1727 continue; 1728 if (pciide_chan_candisable(cp)) { 1729 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1730 channel); 1731 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1732 idetim); 1733 } 1734 pciide_map_compat_intr(pa, cp, channel, 0); 1735 if (cp->hw_ok == 0) 1736 continue; 1737 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1738 } 1739 1740 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1741 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1742 DEBUG_PROBE); 1743 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1744 WDCDEBUG_PRINT((", sidetim=0x%x", 1745 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1746 DEBUG_PROBE); 1747 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1748 WDCDEBUG_PRINT((", udamreg 0x%x", 1749 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1750 DEBUG_PROBE); 1751 } 1752 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1753 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1754 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1755 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1756 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1757 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1758 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1759 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1760 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1761 DEBUG_PROBE); 1762 } 1763 } 1764 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1765 } 1766 1767 void 1768 piix_setup_channel(chp) 1769 struct channel_softc *chp; 1770 { 1771 u_int8_t mode[2], drive; 1772 u_int32_t oidetim, idetim, idedma_ctl; 1773 struct pciide_channel *cp = (struct pciide_channel*)chp; 1774 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1775 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1776 1777 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1778 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1779 idedma_ctl = 0; 1780 1781 /* set up new idetim: Enable IDE registers decode */ 1782 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1783 chp->channel); 1784 1785 /* setup DMA */ 1786 pciide_channel_dma_setup(cp); 1787 1788 /* 1789 * Here we have to mess up with drives mode: PIIX can't have 1790 * different timings for master and slave drives. 1791 * We need to find the best combination. 1792 */ 1793 1794 /* If both drives supports DMA, take the lower mode */ 1795 if ((drvp[0].drive_flags & DRIVE_DMA) && 1796 (drvp[1].drive_flags & DRIVE_DMA)) { 1797 mode[0] = mode[1] = 1798 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1799 drvp[0].DMA_mode = mode[0]; 1800 drvp[1].DMA_mode = mode[1]; 1801 goto ok; 1802 } 1803 /* 1804 * If only one drive supports DMA, use its mode, and 1805 * put the other one in PIO mode 0 if mode not compatible 1806 */ 1807 if (drvp[0].drive_flags & DRIVE_DMA) { 1808 mode[0] = drvp[0].DMA_mode; 1809 mode[1] = drvp[1].PIO_mode; 1810 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1811 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1812 mode[1] = drvp[1].PIO_mode = 0; 1813 goto ok; 1814 } 1815 if (drvp[1].drive_flags & DRIVE_DMA) { 1816 mode[1] = drvp[1].DMA_mode; 1817 mode[0] = drvp[0].PIO_mode; 1818 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1819 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1820 mode[0] = drvp[0].PIO_mode = 0; 1821 goto ok; 1822 } 1823 /* 1824 * If both drives are not DMA, takes the lower mode, unless 1825 * one of them is PIO mode < 2 1826 */ 1827 if (drvp[0].PIO_mode < 2) { 1828 mode[0] = drvp[0].PIO_mode = 0; 1829 mode[1] = drvp[1].PIO_mode; 1830 } else if (drvp[1].PIO_mode < 2) { 1831 mode[1] = drvp[1].PIO_mode = 0; 1832 mode[0] = drvp[0].PIO_mode; 1833 } else { 1834 mode[0] = mode[1] = 1835 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1836 drvp[0].PIO_mode = mode[0]; 1837 drvp[1].PIO_mode = mode[1]; 1838 } 1839 ok: /* The modes are setup */ 1840 for (drive = 0; drive < 2; drive++) { 1841 if (drvp[drive].drive_flags & DRIVE_DMA) { 1842 idetim |= piix_setup_idetim_timings( 1843 mode[drive], 1, chp->channel); 1844 goto end; 1845 } 1846 } 1847 /* If we are there, none of the drives are DMA */ 1848 if (mode[0] >= 2) 1849 idetim |= piix_setup_idetim_timings( 1850 mode[0], 0, chp->channel); 1851 else 1852 idetim |= piix_setup_idetim_timings( 1853 mode[1], 0, chp->channel); 1854 end: /* 1855 * timing mode is now set up in the controller. Enable 1856 * it per-drive 1857 */ 1858 for (drive = 0; drive < 2; drive++) { 1859 /* If no drive, skip */ 1860 if ((drvp[drive].drive_flags & DRIVE) == 0) 1861 continue; 1862 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1863 if (drvp[drive].drive_flags & DRIVE_DMA) 1864 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1865 } 1866 if (idedma_ctl != 0) { 1867 /* Add software bits in status register */ 1868 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1869 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1870 idedma_ctl); 1871 } 1872 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1873 pciide_print_modes(cp); 1874 } 1875 1876 void 1877 piix3_4_setup_channel(chp) 1878 struct channel_softc *chp; 1879 { 1880 struct ata_drive_datas *drvp; 1881 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1882 struct pciide_channel *cp = (struct pciide_channel*)chp; 1883 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1884 int drive; 1885 int channel = chp->channel; 1886 1887 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1888 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1889 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1890 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1891 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1892 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1893 PIIX_SIDETIM_RTC_MASK(channel)); 1894 1895 idedma_ctl = 0; 1896 /* If channel disabled, no need to go further */ 1897 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1898 return; 1899 /* set up new idetim: Enable IDE registers decode */ 1900 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1901 1902 /* setup DMA if needed */ 1903 pciide_channel_dma_setup(cp); 1904 1905 for (drive = 0; drive < 2; drive++) { 1906 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1907 PIIX_UDMATIM_SET(0x3, channel, drive)); 1908 drvp = &chp->ch_drive[drive]; 1909 /* If no drive, skip */ 1910 if ((drvp->drive_flags & DRIVE) == 0) 1911 continue; 1912 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1913 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1914 goto pio; 1915 1916 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1917 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1918 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1919 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1920 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1921 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1922 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1923 ideconf |= PIIX_CONFIG_PINGPONG; 1924 } 1925 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1926 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1927 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1928 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1929 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE) { 1930 /* setup Ultra/100 */ 1931 if (drvp->UDMA_mode > 2 && 1932 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1933 drvp->UDMA_mode = 2; 1934 if (drvp->UDMA_mode > 4) { 1935 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1936 } else { 1937 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1938 if (drvp->UDMA_mode > 2) { 1939 ideconf |= PIIX_CONFIG_UDMA66(channel, 1940 drive); 1941 } else { 1942 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1943 drive); 1944 } 1945 } 1946 } 1947 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1948 /* setup Ultra/66 */ 1949 if (drvp->UDMA_mode > 2 && 1950 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1951 drvp->UDMA_mode = 2; 1952 if (drvp->UDMA_mode > 2) 1953 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1954 else 1955 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1956 } 1957 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1958 (drvp->drive_flags & DRIVE_UDMA)) { 1959 /* use Ultra/DMA */ 1960 drvp->drive_flags &= ~DRIVE_DMA; 1961 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1962 udmareg |= PIIX_UDMATIM_SET( 1963 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1964 } else { 1965 /* use Multiword DMA */ 1966 drvp->drive_flags &= ~DRIVE_UDMA; 1967 if (drive == 0) { 1968 idetim |= piix_setup_idetim_timings( 1969 drvp->DMA_mode, 1, channel); 1970 } else { 1971 sidetim |= piix_setup_sidetim_timings( 1972 drvp->DMA_mode, 1, channel); 1973 idetim =PIIX_IDETIM_SET(idetim, 1974 PIIX_IDETIM_SITRE, channel); 1975 } 1976 } 1977 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1978 1979 pio: /* use PIO mode */ 1980 idetim |= piix_setup_idetim_drvs(drvp); 1981 if (drive == 0) { 1982 idetim |= piix_setup_idetim_timings( 1983 drvp->PIO_mode, 0, channel); 1984 } else { 1985 sidetim |= piix_setup_sidetim_timings( 1986 drvp->PIO_mode, 0, channel); 1987 idetim =PIIX_IDETIM_SET(idetim, 1988 PIIX_IDETIM_SITRE, channel); 1989 } 1990 } 1991 if (idedma_ctl != 0) { 1992 /* Add software bits in status register */ 1993 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1994 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1995 idedma_ctl); 1996 } 1997 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1998 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1999 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 2000 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 2001 pciide_print_modes(cp); 2002 } 2003 2004 2005 /* setup ISP and RTC fields, based on mode */ 2006 static u_int32_t 2007 piix_setup_idetim_timings(mode, dma, channel) 2008 u_int8_t mode; 2009 u_int8_t dma; 2010 u_int8_t channel; 2011 { 2012 2013 if (dma) 2014 return PIIX_IDETIM_SET(0, 2015 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 2016 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 2017 channel); 2018 else 2019 return PIIX_IDETIM_SET(0, 2020 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 2021 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 2022 channel); 2023 } 2024 2025 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 2026 static u_int32_t 2027 piix_setup_idetim_drvs(drvp) 2028 struct ata_drive_datas *drvp; 2029 { 2030 u_int32_t ret = 0; 2031 struct channel_softc *chp = drvp->chnl_softc; 2032 u_int8_t channel = chp->channel; 2033 u_int8_t drive = drvp->drive; 2034 2035 /* 2036 * If drive is using UDMA, timings setups are independant 2037 * So just check DMA and PIO here. 2038 */ 2039 if (drvp->drive_flags & DRIVE_DMA) { 2040 /* if mode = DMA mode 0, use compatible timings */ 2041 if ((drvp->drive_flags & DRIVE_DMA) && 2042 drvp->DMA_mode == 0) { 2043 drvp->PIO_mode = 0; 2044 return ret; 2045 } 2046 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2047 /* 2048 * PIO and DMA timings are the same, use fast timings for PIO 2049 * too, else use compat timings. 2050 */ 2051 if ((piix_isp_pio[drvp->PIO_mode] != 2052 piix_isp_dma[drvp->DMA_mode]) || 2053 (piix_rtc_pio[drvp->PIO_mode] != 2054 piix_rtc_dma[drvp->DMA_mode])) 2055 drvp->PIO_mode = 0; 2056 /* if PIO mode <= 2, use compat timings for PIO */ 2057 if (drvp->PIO_mode <= 2) { 2058 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 2059 channel); 2060 return ret; 2061 } 2062 } 2063 2064 /* 2065 * Now setup PIO modes. If mode < 2, use compat timings. 2066 * Else enable fast timings. Enable IORDY and prefetch/post 2067 * if PIO mode >= 3. 2068 */ 2069 2070 if (drvp->PIO_mode < 2) 2071 return ret; 2072 2073 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2074 if (drvp->PIO_mode >= 3) { 2075 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 2076 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 2077 } 2078 return ret; 2079 } 2080 2081 /* setup values in SIDETIM registers, based on mode */ 2082 static u_int32_t 2083 piix_setup_sidetim_timings(mode, dma, channel) 2084 u_int8_t mode; 2085 u_int8_t dma; 2086 u_int8_t channel; 2087 { 2088 if (dma) 2089 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 2090 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 2091 else 2092 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 2093 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 2094 } 2095 2096 void 2097 amd7x6_chip_map(sc, pa) 2098 struct pciide_softc *sc; 2099 struct pci_attach_args *pa; 2100 { 2101 struct pciide_channel *cp; 2102 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2103 int channel; 2104 pcireg_t chanenable; 2105 bus_size_t cmdsize, ctlsize; 2106 2107 if (pciide_chipen(sc, pa) == 0) 2108 return; 2109 printf("%s: bus-master DMA support present", 2110 sc->sc_wdcdev.sc_dev.dv_xname); 2111 pciide_mapreg_dma(sc, pa); 2112 printf("\n"); 2113 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2114 WDC_CAPABILITY_MODE; 2115 if (sc->sc_dma_ok) { 2116 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2117 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2118 sc->sc_wdcdev.irqack = pciide_irqack; 2119 } 2120 sc->sc_wdcdev.PIO_cap = 4; 2121 sc->sc_wdcdev.DMA_cap = 2; 2122 2123 switch (sc->sc_pci_vendor) { 2124 case PCI_VENDOR_AMD: 2125 switch (sc->sc_pp->ide_product) { 2126 case PCI_PRODUCT_AMD_PBC766_IDE: 2127 case PCI_PRODUCT_AMD_PBC768_IDE: 2128 case PCI_PRODUCT_AMD_PBC8111_IDE: 2129 sc->sc_wdcdev.UDMA_cap = 5; 2130 break; 2131 default: 2132 sc->sc_wdcdev.UDMA_cap = 4; 2133 } 2134 sc->sc_amd_regbase = AMD7X6_AMD_REGBASE; 2135 break; 2136 2137 case PCI_VENDOR_NVIDIA: 2138 switch (sc->sc_pp->ide_product) { 2139 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 2140 sc->sc_wdcdev.UDMA_cap = 5; 2141 break; 2142 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 2143 sc->sc_wdcdev.UDMA_cap = 6; 2144 break; 2145 } 2146 sc->sc_amd_regbase = AMD7X6_NVIDIA_REGBASE; 2147 break; 2148 2149 default: 2150 panic("amd7x6_chip_map: unknown vendor"); 2151 } 2152 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 2153 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2154 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2155 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, 2156 AMD7X6_CHANSTATUS_EN(sc)); 2157 2158 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 2159 DEBUG_PROBE); 2160 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2161 cp = &sc->pciide_channels[channel]; 2162 if (pciide_chansetup(sc, channel, interface) == 0) 2163 continue; 2164 2165 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 2166 printf("%s: %s channel ignored (disabled)\n", 2167 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2168 continue; 2169 } 2170 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2171 pciide_pci_intr); 2172 2173 if (pciide_chan_candisable(cp)) 2174 chanenable &= ~AMD7X6_CHAN_EN(channel); 2175 pciide_map_compat_intr(pa, cp, channel, interface); 2176 if (cp->hw_ok == 0) 2177 continue; 2178 2179 amd7x6_setup_channel(&cp->wdc_channel); 2180 } 2181 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN(sc), 2182 chanenable); 2183 return; 2184 } 2185 2186 void 2187 amd7x6_setup_channel(chp) 2188 struct channel_softc *chp; 2189 { 2190 u_int32_t udmatim_reg, datatim_reg; 2191 u_int8_t idedma_ctl; 2192 int mode, drive; 2193 struct ata_drive_datas *drvp; 2194 struct pciide_channel *cp = (struct pciide_channel*)chp; 2195 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2196 #ifndef PCIIDE_AMD756_ENABLEDMA 2197 int rev = PCI_REVISION( 2198 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2199 #endif 2200 2201 idedma_ctl = 0; 2202 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc)); 2203 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc)); 2204 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2205 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2206 2207 /* setup DMA if needed */ 2208 pciide_channel_dma_setup(cp); 2209 2210 for (drive = 0; drive < 2; drive++) { 2211 drvp = &chp->ch_drive[drive]; 2212 /* If no drive, skip */ 2213 if ((drvp->drive_flags & DRIVE) == 0) 2214 continue; 2215 /* add timing values, setup DMA if needed */ 2216 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2217 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2218 mode = drvp->PIO_mode; 2219 goto pio; 2220 } 2221 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2222 (drvp->drive_flags & DRIVE_UDMA)) { 2223 /* use Ultra/DMA */ 2224 drvp->drive_flags &= ~DRIVE_DMA; 2225 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2226 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2227 AMD7X6_UDMA_TIME(chp->channel, drive, 2228 amd7x6_udma_tim[drvp->UDMA_mode]); 2229 /* can use PIO timings, MW DMA unused */ 2230 mode = drvp->PIO_mode; 2231 } else { 2232 /* use Multiword DMA, but only if revision is OK */ 2233 drvp->drive_flags &= ~DRIVE_UDMA; 2234 #ifndef PCIIDE_AMD756_ENABLEDMA 2235 /* 2236 * The workaround doesn't seem to be necessary 2237 * with all drives, so it can be disabled by 2238 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2239 * triggered. 2240 */ 2241 if (sc->sc_pci_vendor == PCI_VENDOR_AMD && 2242 sc->sc_pp->ide_product == 2243 PCI_PRODUCT_AMD_PBC756_IDE && 2244 AMD756_CHIPREV_DISABLEDMA(rev)) { 2245 printf("%s:%d:%d: multi-word DMA disabled due " 2246 "to chip revision\n", 2247 sc->sc_wdcdev.sc_dev.dv_xname, 2248 chp->channel, drive); 2249 mode = drvp->PIO_mode; 2250 drvp->drive_flags &= ~DRIVE_DMA; 2251 goto pio; 2252 } 2253 #endif 2254 /* mode = min(pio, dma+2) */ 2255 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2256 mode = drvp->PIO_mode; 2257 else 2258 mode = drvp->DMA_mode + 2; 2259 } 2260 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2261 2262 pio: /* setup PIO mode */ 2263 if (mode <= 2) { 2264 drvp->DMA_mode = 0; 2265 drvp->PIO_mode = 0; 2266 mode = 0; 2267 } else { 2268 drvp->PIO_mode = mode; 2269 drvp->DMA_mode = mode - 2; 2270 } 2271 datatim_reg |= 2272 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2273 amd7x6_pio_set[mode]) | 2274 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2275 amd7x6_pio_rec[mode]); 2276 } 2277 if (idedma_ctl != 0) { 2278 /* Add software bits in status register */ 2279 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2280 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2281 idedma_ctl); 2282 } 2283 pciide_print_modes(cp); 2284 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc), datatim_reg); 2285 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc), udmatim_reg); 2286 } 2287 2288 void 2289 apollo_chip_map(sc, pa) 2290 struct pciide_softc *sc; 2291 struct pci_attach_args *pa; 2292 { 2293 struct pciide_channel *cp; 2294 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2295 int channel; 2296 u_int32_t ideconf; 2297 bus_size_t cmdsize, ctlsize; 2298 pcitag_t pcib_tag; 2299 pcireg_t pcib_id, pcib_class; 2300 2301 if (pciide_chipen(sc, pa) == 0) 2302 return; 2303 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2304 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2305 /* and read ID and rev of the ISA bridge */ 2306 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2307 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2308 printf(": VIA Technologies "); 2309 switch (PCI_PRODUCT(pcib_id)) { 2310 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2311 printf("VT82C586 (Apollo VP) "); 2312 if(PCI_REVISION(pcib_class) >= 0x02) { 2313 printf("ATA33 controller\n"); 2314 sc->sc_wdcdev.UDMA_cap = 2; 2315 } else { 2316 printf("controller\n"); 2317 sc->sc_wdcdev.UDMA_cap = 0; 2318 } 2319 break; 2320 case PCI_PRODUCT_VIATECH_VT82C596A: 2321 printf("VT82C596A (Apollo Pro) "); 2322 if (PCI_REVISION(pcib_class) >= 0x12) { 2323 printf("ATA66 controller\n"); 2324 sc->sc_wdcdev.UDMA_cap = 4; 2325 } else { 2326 printf("ATA33 controller\n"); 2327 sc->sc_wdcdev.UDMA_cap = 2; 2328 } 2329 break; 2330 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2331 printf("VT82C686A (Apollo KX133) "); 2332 if (PCI_REVISION(pcib_class) >= 0x40) { 2333 printf("ATA100 controller\n"); 2334 sc->sc_wdcdev.UDMA_cap = 5; 2335 } else { 2336 printf("ATA66 controller\n"); 2337 sc->sc_wdcdev.UDMA_cap = 4; 2338 } 2339 break; 2340 case PCI_PRODUCT_VIATECH_VT8231: 2341 printf("VT8231 ATA100 controller\n"); 2342 sc->sc_wdcdev.UDMA_cap = 5; 2343 break; 2344 case PCI_PRODUCT_VIATECH_VT8233: 2345 printf("VT8233 ATA100 controller\n"); 2346 sc->sc_wdcdev.UDMA_cap = 5; 2347 break; 2348 case PCI_PRODUCT_VIATECH_VT8233A: 2349 printf("VT8233A ATA133 controller\n"); 2350 sc->sc_wdcdev.UDMA_cap = 6; 2351 break; 2352 case PCI_PRODUCT_VIATECH_VT8235: 2353 printf("VT8235 ATA133 controller\n"); 2354 sc->sc_wdcdev.UDMA_cap = 6; 2355 break; 2356 default: 2357 printf("unknown ATA controller\n"); 2358 sc->sc_wdcdev.UDMA_cap = 0; 2359 } 2360 2361 printf("%s: bus-master DMA support present", 2362 sc->sc_wdcdev.sc_dev.dv_xname); 2363 pciide_mapreg_dma(sc, pa); 2364 printf("\n"); 2365 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2366 WDC_CAPABILITY_MODE; 2367 if (sc->sc_dma_ok) { 2368 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2369 sc->sc_wdcdev.irqack = pciide_irqack; 2370 if (sc->sc_wdcdev.UDMA_cap > 0) 2371 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2372 } 2373 sc->sc_wdcdev.PIO_cap = 4; 2374 sc->sc_wdcdev.DMA_cap = 2; 2375 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2376 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2377 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2378 2379 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2380 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2381 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2382 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2383 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2384 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2385 DEBUG_PROBE); 2386 2387 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2388 cp = &sc->pciide_channels[channel]; 2389 if (pciide_chansetup(sc, channel, interface) == 0) 2390 continue; 2391 2392 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2393 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2394 printf("%s: %s channel ignored (disabled)\n", 2395 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2396 continue; 2397 } 2398 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2399 pciide_pci_intr); 2400 if (cp->hw_ok == 0) 2401 continue; 2402 if (pciide_chan_candisable(cp)) { 2403 ideconf &= ~APO_IDECONF_EN(channel); 2404 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2405 ideconf); 2406 } 2407 pciide_map_compat_intr(pa, cp, channel, interface); 2408 2409 if (cp->hw_ok == 0) 2410 continue; 2411 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2412 } 2413 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2414 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2415 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2416 } 2417 2418 void 2419 apollo_setup_channel(chp) 2420 struct channel_softc *chp; 2421 { 2422 u_int32_t udmatim_reg, datatim_reg; 2423 u_int8_t idedma_ctl; 2424 int mode, drive; 2425 struct ata_drive_datas *drvp; 2426 struct pciide_channel *cp = (struct pciide_channel*)chp; 2427 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2428 2429 idedma_ctl = 0; 2430 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2431 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2432 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2433 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2434 2435 /* setup DMA if needed */ 2436 pciide_channel_dma_setup(cp); 2437 2438 for (drive = 0; drive < 2; drive++) { 2439 drvp = &chp->ch_drive[drive]; 2440 /* If no drive, skip */ 2441 if ((drvp->drive_flags & DRIVE) == 0) 2442 continue; 2443 /* add timing values, setup DMA if needed */ 2444 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2445 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2446 mode = drvp->PIO_mode; 2447 goto pio; 2448 } 2449 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2450 (drvp->drive_flags & DRIVE_UDMA)) { 2451 /* use Ultra/DMA */ 2452 drvp->drive_flags &= ~DRIVE_DMA; 2453 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2454 APO_UDMA_EN_MTH(chp->channel, drive); 2455 if (sc->sc_wdcdev.UDMA_cap == 6) { 2456 /* 8233a */ 2457 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2458 drive, apollo_udma133_tim[drvp->UDMA_mode]); 2459 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 2460 /* 686b */ 2461 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2462 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2463 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2464 /* 596b or 686a */ 2465 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2466 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2467 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2468 } else { 2469 /* 596a or 586b */ 2470 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2471 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2472 } 2473 /* can use PIO timings, MW DMA unused */ 2474 mode = drvp->PIO_mode; 2475 } else { 2476 /* use Multiword DMA */ 2477 drvp->drive_flags &= ~DRIVE_UDMA; 2478 /* mode = min(pio, dma+2) */ 2479 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2480 mode = drvp->PIO_mode; 2481 else 2482 mode = drvp->DMA_mode + 2; 2483 } 2484 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2485 2486 pio: /* setup PIO mode */ 2487 if (mode <= 2) { 2488 drvp->DMA_mode = 0; 2489 drvp->PIO_mode = 0; 2490 mode = 0; 2491 } else { 2492 drvp->PIO_mode = mode; 2493 drvp->DMA_mode = mode - 2; 2494 } 2495 datatim_reg |= 2496 APO_DATATIM_PULSE(chp->channel, drive, 2497 apollo_pio_set[mode]) | 2498 APO_DATATIM_RECOV(chp->channel, drive, 2499 apollo_pio_rec[mode]); 2500 } 2501 if (idedma_ctl != 0) { 2502 /* Add software bits in status register */ 2503 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2504 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2505 idedma_ctl); 2506 } 2507 pciide_print_modes(cp); 2508 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2509 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2510 } 2511 2512 void 2513 cmd_channel_map(pa, sc, channel) 2514 struct pci_attach_args *pa; 2515 struct pciide_softc *sc; 2516 int channel; 2517 { 2518 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2519 bus_size_t cmdsize, ctlsize; 2520 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2521 int interface, one_channel; 2522 2523 /* 2524 * The 0648/0649 can be told to identify as a RAID controller. 2525 * In this case, we have to fake interface 2526 */ 2527 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2528 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2529 PCIIDE_INTERFACE_SETTABLE(1); 2530 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2531 CMD_CONF_DSA1) 2532 interface |= PCIIDE_INTERFACE_PCI(0) | 2533 PCIIDE_INTERFACE_PCI(1); 2534 } else { 2535 interface = PCI_INTERFACE(pa->pa_class); 2536 } 2537 2538 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2539 cp->name = PCIIDE_CHANNEL_NAME(channel); 2540 cp->wdc_channel.channel = channel; 2541 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2542 2543 /* 2544 * Older CMD64X doesn't have independant channels 2545 */ 2546 switch (sc->sc_pp->ide_product) { 2547 case PCI_PRODUCT_CMDTECH_649: 2548 one_channel = 0; 2549 break; 2550 default: 2551 one_channel = 1; 2552 break; 2553 } 2554 2555 if (channel > 0 && one_channel) { 2556 cp->wdc_channel.ch_queue = 2557 sc->pciide_channels[0].wdc_channel.ch_queue; 2558 } else { 2559 cp->wdc_channel.ch_queue = 2560 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2561 } 2562 if (cp->wdc_channel.ch_queue == NULL) { 2563 printf("%s %s channel: " 2564 "can't allocate memory for command queue", 2565 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2566 return; 2567 } 2568 2569 printf("%s: %s channel %s to %s mode\n", 2570 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2571 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2572 "configured" : "wired", 2573 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2574 "native-PCI" : "compatibility"); 2575 2576 /* 2577 * with a CMD PCI64x, if we get here, the first channel is enabled: 2578 * there's no way to disable the first channel without disabling 2579 * the whole device 2580 */ 2581 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2582 printf("%s: %s channel ignored (disabled)\n", 2583 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2584 return; 2585 } 2586 2587 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2588 if (cp->hw_ok == 0) 2589 return; 2590 if (channel == 1) { 2591 if (pciide_chan_candisable(cp)) { 2592 ctrl &= ~CMD_CTRL_2PORT; 2593 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2594 CMD_CTRL, ctrl); 2595 } 2596 } 2597 pciide_map_compat_intr(pa, cp, channel, interface); 2598 } 2599 2600 int 2601 cmd_pci_intr(arg) 2602 void *arg; 2603 { 2604 struct pciide_softc *sc = arg; 2605 struct pciide_channel *cp; 2606 struct channel_softc *wdc_cp; 2607 int i, rv, crv; 2608 u_int32_t priirq, secirq; 2609 2610 rv = 0; 2611 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2612 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2613 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2614 cp = &sc->pciide_channels[i]; 2615 wdc_cp = &cp->wdc_channel; 2616 /* If a compat channel skip. */ 2617 if (cp->compat) 2618 continue; 2619 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2620 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2621 crv = wdcintr(wdc_cp); 2622 if (crv == 0) 2623 printf("%s:%d: bogus intr\n", 2624 sc->sc_wdcdev.sc_dev.dv_xname, i); 2625 else 2626 rv = 1; 2627 } 2628 } 2629 return rv; 2630 } 2631 2632 void 2633 cmd_chip_map(sc, pa) 2634 struct pciide_softc *sc; 2635 struct pci_attach_args *pa; 2636 { 2637 int channel; 2638 2639 /* 2640 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2641 * and base adresses registers can be disabled at 2642 * hardware level. In this case, the device is wired 2643 * in compat mode and its first channel is always enabled, 2644 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2645 * In fact, it seems that the first channel of the CMD PCI0640 2646 * can't be disabled. 2647 */ 2648 2649 #ifdef PCIIDE_CMD064x_DISABLE 2650 if (pciide_chipen(sc, pa) == 0) 2651 return; 2652 #endif 2653 2654 printf("%s: hardware does not support DMA\n", 2655 sc->sc_wdcdev.sc_dev.dv_xname); 2656 sc->sc_dma_ok = 0; 2657 2658 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2659 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2660 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2661 2662 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2663 cmd_channel_map(pa, sc, channel); 2664 } 2665 } 2666 2667 void 2668 cmd0643_9_chip_map(sc, pa) 2669 struct pciide_softc *sc; 2670 struct pci_attach_args *pa; 2671 { 2672 struct pciide_channel *cp; 2673 int channel; 2674 pcireg_t rev = PCI_REVISION(pa->pa_class); 2675 2676 /* 2677 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2678 * and base adresses registers can be disabled at 2679 * hardware level. In this case, the device is wired 2680 * in compat mode and its first channel is always enabled, 2681 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2682 * In fact, it seems that the first channel of the CMD PCI0640 2683 * can't be disabled. 2684 */ 2685 2686 #ifdef PCIIDE_CMD064x_DISABLE 2687 if (pciide_chipen(sc, pa) == 0) 2688 return; 2689 #endif 2690 printf("%s: bus-master DMA support present", 2691 sc->sc_wdcdev.sc_dev.dv_xname); 2692 pciide_mapreg_dma(sc, pa); 2693 printf("\n"); 2694 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2695 WDC_CAPABILITY_MODE; 2696 if (sc->sc_dma_ok) { 2697 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2698 switch (sc->sc_pp->ide_product) { 2699 case PCI_PRODUCT_CMDTECH_649: 2700 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2701 sc->sc_wdcdev.UDMA_cap = 5; 2702 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2703 break; 2704 case PCI_PRODUCT_CMDTECH_648: 2705 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2706 sc->sc_wdcdev.UDMA_cap = 4; 2707 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2708 break; 2709 case PCI_PRODUCT_CMDTECH_646: 2710 if (rev >= CMD0646U2_REV) { 2711 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2712 sc->sc_wdcdev.UDMA_cap = 2; 2713 } else if (rev >= CMD0646U_REV) { 2714 /* 2715 * Linux's driver claims that the 646U is broken 2716 * with UDMA. Only enable it if we know what we're 2717 * doing 2718 */ 2719 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2720 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2721 sc->sc_wdcdev.UDMA_cap = 2; 2722 #endif 2723 /* explicitly disable UDMA */ 2724 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2725 CMD_UDMATIM(0), 0); 2726 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2727 CMD_UDMATIM(1), 0); 2728 } 2729 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2730 break; 2731 default: 2732 sc->sc_wdcdev.irqack = pciide_irqack; 2733 } 2734 } 2735 2736 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2737 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2738 sc->sc_wdcdev.PIO_cap = 4; 2739 sc->sc_wdcdev.DMA_cap = 2; 2740 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2741 2742 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2743 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2744 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2745 DEBUG_PROBE); 2746 2747 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2748 cp = &sc->pciide_channels[channel]; 2749 cmd_channel_map(pa, sc, channel); 2750 if (cp->hw_ok == 0) 2751 continue; 2752 cmd0643_9_setup_channel(&cp->wdc_channel); 2753 } 2754 /* 2755 * note - this also makes sure we clear the irq disable and reset 2756 * bits 2757 */ 2758 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2759 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2760 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2761 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2762 DEBUG_PROBE); 2763 } 2764 2765 void 2766 cmd0643_9_setup_channel(chp) 2767 struct channel_softc *chp; 2768 { 2769 struct ata_drive_datas *drvp; 2770 u_int8_t tim; 2771 u_int32_t idedma_ctl, udma_reg; 2772 int drive; 2773 struct pciide_channel *cp = (struct pciide_channel*)chp; 2774 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2775 2776 idedma_ctl = 0; 2777 /* setup DMA if needed */ 2778 pciide_channel_dma_setup(cp); 2779 2780 for (drive = 0; drive < 2; drive++) { 2781 drvp = &chp->ch_drive[drive]; 2782 /* If no drive, skip */ 2783 if ((drvp->drive_flags & DRIVE) == 0) 2784 continue; 2785 /* add timing values, setup DMA if needed */ 2786 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2787 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2788 if (drvp->drive_flags & DRIVE_UDMA) { 2789 /* UltraDMA on a 646U2, 0648 or 0649 */ 2790 drvp->drive_flags &= ~DRIVE_DMA; 2791 udma_reg = pciide_pci_read(sc->sc_pc, 2792 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2793 if (drvp->UDMA_mode > 2 && 2794 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2795 CMD_BICSR) & 2796 CMD_BICSR_80(chp->channel)) == 0) 2797 drvp->UDMA_mode = 2; 2798 if (drvp->UDMA_mode > 2) 2799 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2800 else if (sc->sc_wdcdev.UDMA_cap > 2) 2801 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2802 udma_reg |= CMD_UDMATIM_UDMA(drive); 2803 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2804 CMD_UDMATIM_TIM_OFF(drive)); 2805 udma_reg |= 2806 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2807 CMD_UDMATIM_TIM_OFF(drive)); 2808 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2809 CMD_UDMATIM(chp->channel), udma_reg); 2810 } else { 2811 /* 2812 * use Multiword DMA. 2813 * Timings will be used for both PIO and DMA, 2814 * so adjust DMA mode if needed 2815 * if we have a 0646U2/8/9, turn off UDMA 2816 */ 2817 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2818 udma_reg = pciide_pci_read(sc->sc_pc, 2819 sc->sc_tag, 2820 CMD_UDMATIM(chp->channel)); 2821 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2822 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2823 CMD_UDMATIM(chp->channel), 2824 udma_reg); 2825 } 2826 if (drvp->PIO_mode >= 3 && 2827 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2828 drvp->DMA_mode = drvp->PIO_mode - 2; 2829 } 2830 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2831 } 2832 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2833 } 2834 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2835 CMD_DATA_TIM(chp->channel, drive), tim); 2836 } 2837 if (idedma_ctl != 0) { 2838 /* Add software bits in status register */ 2839 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2840 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2841 idedma_ctl); 2842 } 2843 pciide_print_modes(cp); 2844 } 2845 2846 void 2847 cmd646_9_irqack(chp) 2848 struct channel_softc *chp; 2849 { 2850 u_int32_t priirq, secirq; 2851 struct pciide_channel *cp = (struct pciide_channel*)chp; 2852 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2853 2854 if (chp->channel == 0) { 2855 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2856 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2857 } else { 2858 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2859 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2860 } 2861 pciide_irqack(chp); 2862 } 2863 2864 void 2865 cmd680_chip_map(sc, pa) 2866 struct pciide_softc *sc; 2867 struct pci_attach_args *pa; 2868 { 2869 struct pciide_channel *cp; 2870 int channel; 2871 2872 if (pciide_chipen(sc, pa) == 0) 2873 return; 2874 printf("%s: bus-master DMA support present", 2875 sc->sc_wdcdev.sc_dev.dv_xname); 2876 pciide_mapreg_dma(sc, pa); 2877 printf("\n"); 2878 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2879 WDC_CAPABILITY_MODE; 2880 if (sc->sc_dma_ok) { 2881 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2882 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2883 sc->sc_wdcdev.UDMA_cap = 6; 2884 sc->sc_wdcdev.irqack = pciide_irqack; 2885 } 2886 2887 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2888 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2889 sc->sc_wdcdev.PIO_cap = 4; 2890 sc->sc_wdcdev.DMA_cap = 2; 2891 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 2892 2893 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 2894 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 2895 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 2896 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 2897 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2898 cp = &sc->pciide_channels[channel]; 2899 cmd680_channel_map(pa, sc, channel); 2900 if (cp->hw_ok == 0) 2901 continue; 2902 cmd680_setup_channel(&cp->wdc_channel); 2903 } 2904 } 2905 2906 void 2907 cmd680_channel_map(pa, sc, channel) 2908 struct pci_attach_args *pa; 2909 struct pciide_softc *sc; 2910 int channel; 2911 { 2912 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2913 bus_size_t cmdsize, ctlsize; 2914 int interface, i, reg; 2915 static const u_int8_t init_val[] = 2916 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 2917 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 2918 2919 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2920 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2921 PCIIDE_INTERFACE_SETTABLE(1); 2922 interface |= PCIIDE_INTERFACE_PCI(0) | 2923 PCIIDE_INTERFACE_PCI(1); 2924 } else { 2925 interface = PCI_INTERFACE(pa->pa_class); 2926 } 2927 2928 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2929 cp->name = PCIIDE_CHANNEL_NAME(channel); 2930 cp->wdc_channel.channel = channel; 2931 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2932 2933 cp->wdc_channel.ch_queue = 2934 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2935 if (cp->wdc_channel.ch_queue == NULL) { 2936 printf("%s %s channel: " 2937 "can't allocate memory for command queue", 2938 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2939 return; 2940 } 2941 2942 /* XXX */ 2943 reg = 0xa2 + channel * 16; 2944 for (i = 0; i < sizeof(init_val); i++) 2945 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 2946 2947 printf("%s: %s channel %s to %s mode\n", 2948 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2949 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2950 "configured" : "wired", 2951 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2952 "native-PCI" : "compatibility"); 2953 2954 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 2955 if (cp->hw_ok == 0) 2956 return; 2957 pciide_map_compat_intr(pa, cp, channel, interface); 2958 } 2959 2960 void 2961 cmd680_setup_channel(chp) 2962 struct channel_softc *chp; 2963 { 2964 struct ata_drive_datas *drvp; 2965 u_int8_t mode, off, scsc; 2966 u_int16_t val; 2967 u_int32_t idedma_ctl; 2968 int drive; 2969 struct pciide_channel *cp = (struct pciide_channel*)chp; 2970 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2971 pci_chipset_tag_t pc = sc->sc_pc; 2972 pcitag_t pa = sc->sc_tag; 2973 static const u_int8_t udma2_tbl[] = 2974 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 2975 static const u_int8_t udma_tbl[] = 2976 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 2977 static const u_int16_t dma_tbl[] = 2978 { 0x2208, 0x10c2, 0x10c1 }; 2979 static const u_int16_t pio_tbl[] = 2980 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 2981 2982 idedma_ctl = 0; 2983 pciide_channel_dma_setup(cp); 2984 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 2985 2986 for (drive = 0; drive < 2; drive++) { 2987 drvp = &chp->ch_drive[drive]; 2988 /* If no drive, skip */ 2989 if ((drvp->drive_flags & DRIVE) == 0) 2990 continue; 2991 mode &= ~(0x03 << (drive * 4)); 2992 if (drvp->drive_flags & DRIVE_UDMA) { 2993 drvp->drive_flags &= ~DRIVE_DMA; 2994 off = 0xa0 + chp->channel * 16; 2995 if (drvp->UDMA_mode > 2 && 2996 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 2997 drvp->UDMA_mode = 2; 2998 scsc = pciide_pci_read(pc, pa, 0x8a); 2999 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 3000 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 3001 scsc = pciide_pci_read(pc, pa, 0x8a); 3002 if ((scsc & 0x30) == 0) 3003 drvp->UDMA_mode = 5; 3004 } 3005 mode |= 0x03 << (drive * 4); 3006 off = 0xac + chp->channel * 16 + drive * 2; 3007 val = pciide_pci_read(pc, pa, off) & ~0x3f; 3008 if (scsc & 0x30) 3009 val |= udma2_tbl[drvp->UDMA_mode]; 3010 else 3011 val |= udma_tbl[drvp->UDMA_mode]; 3012 pciide_pci_write(pc, pa, off, val); 3013 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3014 } else if (drvp->drive_flags & DRIVE_DMA) { 3015 mode |= 0x02 << (drive * 4); 3016 off = 0xa8 + chp->channel * 16 + drive * 2; 3017 val = dma_tbl[drvp->DMA_mode]; 3018 pciide_pci_write(pc, pa, off, val & 0xff); 3019 pciide_pci_write(pc, pa, off, val >> 8); 3020 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3021 } else { 3022 mode |= 0x01 << (drive * 4); 3023 off = 0xa4 + chp->channel * 16 + drive * 2; 3024 val = pio_tbl[drvp->PIO_mode]; 3025 pciide_pci_write(pc, pa, off, val & 0xff); 3026 pciide_pci_write(pc, pa, off, val >> 8); 3027 } 3028 } 3029 3030 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 3031 if (idedma_ctl != 0) { 3032 /* Add software bits in status register */ 3033 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3034 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3035 idedma_ctl); 3036 } 3037 pciide_print_modes(cp); 3038 } 3039 3040 void 3041 cmd3112_chip_map(sc, pa) 3042 struct pciide_softc *sc; 3043 struct pci_attach_args *pa; 3044 { 3045 struct pciide_channel *cp; 3046 bus_size_t cmdsize, ctlsize; 3047 pcireg_t interface; 3048 int channel; 3049 3050 if (pciide_chipen(sc, pa) == 0) 3051 return; 3052 3053 printf("%s: bus-master DMA support present", 3054 sc->sc_wdcdev.sc_dev.dv_xname); 3055 pciide_mapreg_dma(sc, pa); 3056 printf("\n"); 3057 3058 /* 3059 * Rev. <= 0x01 of the 3112 have a bug that can cause data 3060 * corruption if DMA transfers cross an 8K boundary. This is 3061 * apparently hard to tickle, but we'll go ahead and play it 3062 * safe. 3063 */ 3064 if (PCI_REVISION(pa->pa_class) <= 0x01) { 3065 sc->sc_dma_maxsegsz = 8192; 3066 sc->sc_dma_boundary = 8192; 3067 } 3068 3069 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3070 WDC_CAPABILITY_MODE; 3071 sc->sc_wdcdev.PIO_cap = 4; 3072 if (sc->sc_dma_ok) { 3073 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3074 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3075 sc->sc_wdcdev.irqack = pciide_irqack; 3076 sc->sc_wdcdev.DMA_cap = 2; 3077 sc->sc_wdcdev.UDMA_cap = 6; 3078 } 3079 sc->sc_wdcdev.set_modes = cmd3112_setup_channel; 3080 3081 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3082 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3083 3084 /* 3085 * The 3112 can be told to identify as a RAID controller. 3086 * In this case, we have to fake interface 3087 */ 3088 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3089 interface = PCI_INTERFACE(pa->pa_class); 3090 } else { 3091 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3092 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3093 } 3094 3095 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3096 cp = &sc->pciide_channels[channel]; 3097 if (pciide_chansetup(sc, channel, interface) == 0) 3098 continue; 3099 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3100 pciide_pci_intr); 3101 if (cp->hw_ok == 0) 3102 continue; 3103 pciide_map_compat_intr(pa, cp, channel, interface); 3104 cmd3112_setup_channel(&cp->wdc_channel); 3105 } 3106 } 3107 3108 void 3109 cmd3112_setup_channel(chp) 3110 struct channel_softc *chp; 3111 { 3112 struct ata_drive_datas *drvp; 3113 int drive; 3114 u_int32_t idedma_ctl, dtm; 3115 struct pciide_channel *cp = (struct pciide_channel*)chp; 3116 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 3117 3118 /* setup DMA if needed */ 3119 pciide_channel_dma_setup(cp); 3120 3121 idedma_ctl = 0; 3122 dtm = 0; 3123 3124 for (drive = 0; drive < 2; drive++) { 3125 drvp = &chp->ch_drive[drive]; 3126 /* If no drive, skip */ 3127 if ((drvp->drive_flags & DRIVE) == 0) 3128 continue; 3129 if (drvp->drive_flags & DRIVE_UDMA) { 3130 /* use Ultra/DMA */ 3131 drvp->drive_flags &= ~DRIVE_DMA; 3132 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3133 dtm |= DTM_IDEx_DMA; 3134 } else if (drvp->drive_flags & DRIVE_DMA) { 3135 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3136 dtm |= DTM_IDEx_DMA; 3137 } else { 3138 dtm |= DTM_IDEx_PIO; 3139 } 3140 } 3141 3142 /* 3143 * Nothing to do to setup modes; it is meaningless in S-ATA 3144 * (but many S-ATA drives still want to get the SET_FEATURE 3145 * command). 3146 */ 3147 if (idedma_ctl != 0) { 3148 /* Add software bits in status register */ 3149 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3150 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3151 idedma_ctl); 3152 } 3153 pci_conf_write(sc->sc_pc, sc->sc_tag, 3154 chp->channel == 0 ? SII3112_DTM_IDE0 : SII3112_DTM_IDE1, dtm); 3155 pciide_print_modes(cp); 3156 } 3157 3158 void 3159 cy693_chip_map(sc, pa) 3160 struct pciide_softc *sc; 3161 struct pci_attach_args *pa; 3162 { 3163 struct pciide_channel *cp; 3164 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3165 bus_size_t cmdsize, ctlsize; 3166 3167 if (pciide_chipen(sc, pa) == 0) 3168 return; 3169 /* 3170 * this chip has 2 PCI IDE functions, one for primary and one for 3171 * secondary. So we need to call pciide_mapregs_compat() with 3172 * the real channel 3173 */ 3174 if (pa->pa_function == 1) { 3175 sc->sc_cy_compatchan = 0; 3176 } else if (pa->pa_function == 2) { 3177 sc->sc_cy_compatchan = 1; 3178 } else { 3179 printf("%s: unexpected PCI function %d\n", 3180 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3181 return; 3182 } 3183 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 3184 printf("%s: bus-master DMA support present", 3185 sc->sc_wdcdev.sc_dev.dv_xname); 3186 pciide_mapreg_dma(sc, pa); 3187 } else { 3188 printf("%s: hardware does not support DMA", 3189 sc->sc_wdcdev.sc_dev.dv_xname); 3190 sc->sc_dma_ok = 0; 3191 } 3192 printf("\n"); 3193 3194 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 3195 if (sc->sc_cy_handle == NULL) { 3196 printf("%s: unable to map hyperCache control registers\n", 3197 sc->sc_wdcdev.sc_dev.dv_xname); 3198 sc->sc_dma_ok = 0; 3199 } 3200 3201 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3202 WDC_CAPABILITY_MODE; 3203 if (sc->sc_dma_ok) { 3204 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3205 sc->sc_wdcdev.irqack = pciide_irqack; 3206 } 3207 sc->sc_wdcdev.PIO_cap = 4; 3208 sc->sc_wdcdev.DMA_cap = 2; 3209 sc->sc_wdcdev.set_modes = cy693_setup_channel; 3210 3211 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3212 sc->sc_wdcdev.nchannels = 1; 3213 3214 /* Only one channel for this chip; if we are here it's enabled */ 3215 cp = &sc->pciide_channels[0]; 3216 sc->wdc_chanarray[0] = &cp->wdc_channel; 3217 cp->name = PCIIDE_CHANNEL_NAME(0); 3218 cp->wdc_channel.channel = 0; 3219 cp->wdc_channel.wdc = &sc->sc_wdcdev; 3220 cp->wdc_channel.ch_queue = 3221 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 3222 if (cp->wdc_channel.ch_queue == NULL) { 3223 printf("%s primary channel: " 3224 "can't allocate memory for command queue", 3225 sc->sc_wdcdev.sc_dev.dv_xname); 3226 return; 3227 } 3228 printf("%s: primary channel %s to ", 3229 sc->sc_wdcdev.sc_dev.dv_xname, 3230 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 3231 "configured" : "wired"); 3232 if (interface & PCIIDE_INTERFACE_PCI(0)) { 3233 printf("native-PCI"); 3234 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 3235 pciide_pci_intr); 3236 } else { 3237 printf("compatibility"); 3238 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 3239 &cmdsize, &ctlsize); 3240 } 3241 printf(" mode\n"); 3242 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3243 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3244 wdcattach(&cp->wdc_channel); 3245 if (pciide_chan_candisable(cp)) { 3246 pci_conf_write(sc->sc_pc, sc->sc_tag, 3247 PCI_COMMAND_STATUS_REG, 0); 3248 } 3249 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 3250 if (cp->hw_ok == 0) 3251 return; 3252 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 3253 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 3254 cy693_setup_channel(&cp->wdc_channel); 3255 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 3256 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 3257 } 3258 3259 void 3260 cy693_setup_channel(chp) 3261 struct channel_softc *chp; 3262 { 3263 struct ata_drive_datas *drvp; 3264 int drive; 3265 u_int32_t cy_cmd_ctrl; 3266 u_int32_t idedma_ctl; 3267 struct pciide_channel *cp = (struct pciide_channel*)chp; 3268 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3269 int dma_mode = -1; 3270 3271 cy_cmd_ctrl = idedma_ctl = 0; 3272 3273 /* setup DMA if needed */ 3274 pciide_channel_dma_setup(cp); 3275 3276 for (drive = 0; drive < 2; drive++) { 3277 drvp = &chp->ch_drive[drive]; 3278 /* If no drive, skip */ 3279 if ((drvp->drive_flags & DRIVE) == 0) 3280 continue; 3281 /* add timing values, setup DMA if needed */ 3282 if (drvp->drive_flags & DRIVE_DMA) { 3283 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3284 /* use Multiword DMA */ 3285 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 3286 dma_mode = drvp->DMA_mode; 3287 } 3288 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3289 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 3290 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3291 CY_CMD_CTRL_IOW_REC_OFF(drive)); 3292 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3293 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 3294 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3295 CY_CMD_CTRL_IOR_REC_OFF(drive)); 3296 } 3297 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 3298 chp->ch_drive[0].DMA_mode = dma_mode; 3299 chp->ch_drive[1].DMA_mode = dma_mode; 3300 3301 if (dma_mode == -1) 3302 dma_mode = 0; 3303 3304 if (sc->sc_cy_handle != NULL) { 3305 /* Note: `multiple' is implied. */ 3306 cy82c693_write(sc->sc_cy_handle, 3307 (sc->sc_cy_compatchan == 0) ? 3308 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 3309 } 3310 3311 pciide_print_modes(cp); 3312 3313 if (idedma_ctl != 0) { 3314 /* Add software bits in status register */ 3315 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3316 IDEDMA_CTL, idedma_ctl); 3317 } 3318 } 3319 3320 static struct sis_hostbr_type { 3321 u_int16_t id; 3322 u_int8_t rev; 3323 u_int8_t udma_mode; 3324 char *name; 3325 u_int8_t type; 3326 #define SIS_TYPE_NOUDMA 0 3327 #define SIS_TYPE_66 1 3328 #define SIS_TYPE_100OLD 2 3329 #define SIS_TYPE_100NEW 3 3330 #define SIS_TYPE_133OLD 4 3331 #define SIS_TYPE_133NEW 5 3332 #define SIS_TYPE_SOUTH 6 3333 } sis_hostbr_type[] = { 3334 /* Most infos here are from sos (at) freebsd.org */ 3335 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 3336 #if 0 3337 /* 3338 * controllers associated to a rev 0x2 530 Host to PCI Bridge 3339 * have problems with UDMA (info provided by Christos) 3340 */ 3341 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 3342 #endif 3343 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 3344 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 3345 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 3346 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 3347 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 3348 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 3349 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 3350 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 3351 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 3352 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 3353 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 3354 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 3355 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 3356 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 3357 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 3358 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 3359 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 3360 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 3361 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 3362 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 3363 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 3364 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 3365 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 3366 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 3367 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 3368 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 3369 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 3370 /* 3371 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 3372 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 3373 */ 3374 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 3375 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 3376 }; 3377 3378 static struct sis_hostbr_type *sis_hostbr_type_match; 3379 3380 static int 3381 sis_hostbr_match(pa) 3382 struct pci_attach_args *pa; 3383 { 3384 int i; 3385 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 3386 return 0; 3387 sis_hostbr_type_match = NULL; 3388 for (i = 0; 3389 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 3390 i++) { 3391 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 3392 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 3393 sis_hostbr_type_match = &sis_hostbr_type[i]; 3394 } 3395 return (sis_hostbr_type_match != NULL); 3396 } 3397 3398 static int sis_south_match(pa) 3399 struct pci_attach_args *pa; 3400 { 3401 return(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 3402 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 3403 PCI_REVISION(pa->pa_class) >= 0x10); 3404 } 3405 3406 void 3407 sis_chip_map(sc, pa) 3408 struct pciide_softc *sc; 3409 struct pci_attach_args *pa; 3410 { 3411 struct pciide_channel *cp; 3412 int channel; 3413 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 3414 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3415 pcireg_t rev = PCI_REVISION(pa->pa_class); 3416 bus_size_t cmdsize, ctlsize; 3417 3418 if (pciide_chipen(sc, pa) == 0) 3419 return; 3420 printf(": Silicon Integrated System "); 3421 pci_find_device(NULL, sis_hostbr_match); 3422 if (sis_hostbr_type_match) { 3423 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 3424 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 3425 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3426 SIS_REG_57) & 0x7f); 3427 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 3428 PCI_ID_REG)) == SIS_PRODUCT_5518) { 3429 printf("96X UDMA%d", 3430 sis_hostbr_type_match->udma_mode); 3431 sc->sis_type = SIS_TYPE_133NEW; 3432 sc->sc_wdcdev.UDMA_cap = 3433 sis_hostbr_type_match->udma_mode; 3434 } else { 3435 if (pci_find_device(NULL, sis_south_match)) { 3436 sc->sis_type = SIS_TYPE_133OLD; 3437 sc->sc_wdcdev.UDMA_cap = 3438 sis_hostbr_type_match->udma_mode; 3439 } else { 3440 sc->sis_type = SIS_TYPE_100NEW; 3441 sc->sc_wdcdev.UDMA_cap = 3442 sis_hostbr_type_match->udma_mode; 3443 } 3444 } 3445 } else { 3446 sc->sis_type = sis_hostbr_type_match->type; 3447 sc->sc_wdcdev.UDMA_cap = 3448 sis_hostbr_type_match->udma_mode; 3449 } 3450 printf(sis_hostbr_type_match->name); 3451 } else { 3452 printf("5597/5598"); 3453 if (rev >= 0xd0) { 3454 sc->sc_wdcdev.UDMA_cap = 2; 3455 sc->sis_type = SIS_TYPE_66; 3456 } else { 3457 sc->sc_wdcdev.UDMA_cap = 0; 3458 sc->sis_type = SIS_TYPE_NOUDMA; 3459 } 3460 } 3461 printf(" IDE controller (rev. 0x%02x)\n", PCI_REVISION(pa->pa_class)); 3462 printf("%s: bus-master DMA support present", 3463 sc->sc_wdcdev.sc_dev.dv_xname); 3464 pciide_mapreg_dma(sc, pa); 3465 printf("\n"); 3466 3467 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3468 WDC_CAPABILITY_MODE; 3469 if (sc->sc_dma_ok) { 3470 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3471 sc->sc_wdcdev.irqack = pciide_irqack; 3472 if (sc->sis_type >= SIS_TYPE_66) 3473 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3474 } 3475 3476 sc->sc_wdcdev.PIO_cap = 4; 3477 sc->sc_wdcdev.DMA_cap = 2; 3478 3479 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3480 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3481 switch(sc->sis_type) { 3482 case SIS_TYPE_NOUDMA: 3483 case SIS_TYPE_66: 3484 case SIS_TYPE_100OLD: 3485 sc->sc_wdcdev.set_modes = sis_setup_channel; 3486 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 3487 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 3488 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 3489 break; 3490 case SIS_TYPE_100NEW: 3491 case SIS_TYPE_133OLD: 3492 sc->sc_wdcdev.set_modes = sis_setup_channel; 3493 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 3494 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 3495 break; 3496 case SIS_TYPE_133NEW: 3497 sc->sc_wdcdev.set_modes = sis96x_setup_channel; 3498 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 3499 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 3500 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 3501 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 3502 break; 3503 } 3504 3505 3506 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3507 cp = &sc->pciide_channels[channel]; 3508 if (pciide_chansetup(sc, channel, interface) == 0) 3509 continue; 3510 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 3511 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 3512 printf("%s: %s channel ignored (disabled)\n", 3513 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3514 continue; 3515 } 3516 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3517 pciide_pci_intr); 3518 if (cp->hw_ok == 0) 3519 continue; 3520 if (pciide_chan_candisable(cp)) { 3521 if (channel == 0) 3522 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 3523 else 3524 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 3525 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 3526 sis_ctr0); 3527 } 3528 pciide_map_compat_intr(pa, cp, channel, interface); 3529 if (cp->hw_ok == 0) 3530 continue; 3531 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 3532 } 3533 } 3534 3535 void 3536 sis96x_setup_channel(chp) 3537 struct channel_softc *chp; 3538 { 3539 struct ata_drive_datas *drvp; 3540 int drive; 3541 u_int32_t sis_tim; 3542 u_int32_t idedma_ctl; 3543 int regtim; 3544 struct pciide_channel *cp = (struct pciide_channel*)chp; 3545 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3546 3547 sis_tim = 0; 3548 idedma_ctl = 0; 3549 /* setup DMA if needed */ 3550 pciide_channel_dma_setup(cp); 3551 3552 for (drive = 0; drive < 2; drive++) { 3553 regtim = SIS_TIM133( 3554 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 3555 chp->channel, drive); 3556 drvp = &chp->ch_drive[drive]; 3557 /* If no drive, skip */ 3558 if ((drvp->drive_flags & DRIVE) == 0) 3559 continue; 3560 /* add timing values, setup DMA if needed */ 3561 if (drvp->drive_flags & DRIVE_UDMA) { 3562 /* use Ultra/DMA */ 3563 drvp->drive_flags &= ~DRIVE_DMA; 3564 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3565 SIS96x_REG_CBL(chp->channel)) & SIS96x_REG_CBL_33) { 3566 if (drvp->UDMA_mode > 2) 3567 drvp->UDMA_mode = 2; 3568 } 3569 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 3570 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3571 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3572 } else if (drvp->drive_flags & DRIVE_DMA) { 3573 /* 3574 * use Multiword DMA 3575 * Timings will be used for both PIO and DMA, 3576 * so adjust DMA mode if needed 3577 */ 3578 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3579 drvp->PIO_mode = drvp->DMA_mode + 2; 3580 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3581 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3582 drvp->PIO_mode - 2 : 0; 3583 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 3584 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3585 } else { 3586 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3587 } 3588 WDCDEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 3589 "channel %d drive %d: 0x%x (reg 0x%x)\n", 3590 chp->channel, drive, sis_tim, regtim), DEBUG_PROBE); 3591 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 3592 } 3593 if (idedma_ctl != 0) { 3594 /* Add software bits in status register */ 3595 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3596 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3597 idedma_ctl); 3598 } 3599 pciide_print_modes(cp); 3600 } 3601 3602 void 3603 sis_setup_channel(chp) 3604 struct channel_softc *chp; 3605 { 3606 struct ata_drive_datas *drvp; 3607 int drive; 3608 u_int32_t sis_tim; 3609 u_int32_t idedma_ctl; 3610 struct pciide_channel *cp = (struct pciide_channel*)chp; 3611 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3612 3613 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 3614 "channel %d 0x%x\n", chp->channel, 3615 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 3616 DEBUG_PROBE); 3617 sis_tim = 0; 3618 idedma_ctl = 0; 3619 /* setup DMA if needed */ 3620 pciide_channel_dma_setup(cp); 3621 3622 for (drive = 0; drive < 2; drive++) { 3623 drvp = &chp->ch_drive[drive]; 3624 /* If no drive, skip */ 3625 if ((drvp->drive_flags & DRIVE) == 0) 3626 continue; 3627 /* add timing values, setup DMA if needed */ 3628 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3629 (drvp->drive_flags & DRIVE_UDMA) == 0) 3630 goto pio; 3631 3632 if (drvp->drive_flags & DRIVE_UDMA) { 3633 /* use Ultra/DMA */ 3634 drvp->drive_flags &= ~DRIVE_DMA; 3635 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3636 SIS_REG_CBL) & SIS_REG_CBL_33(chp->channel)) { 3637 if (drvp->UDMA_mode > 2) 3638 drvp->UDMA_mode = 2; 3639 } 3640 switch (sc->sis_type) { 3641 case SIS_TYPE_66: 3642 case SIS_TYPE_100OLD: 3643 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 3644 SIS_TIM66_UDMA_TIME_OFF(drive); 3645 break; 3646 case SIS_TYPE_100NEW: 3647 sis_tim |= 3648 sis_udma100new_tim[drvp->UDMA_mode] << 3649 SIS_TIM100_UDMA_TIME_OFF(drive); 3650 case SIS_TYPE_133OLD: 3651 sis_tim |= 3652 sis_udma133old_tim[drvp->UDMA_mode] << 3653 SIS_TIM100_UDMA_TIME_OFF(drive); 3654 break; 3655 default: 3656 printf("unknown SiS IDE type %d\n", 3657 sc->sis_type); 3658 } 3659 } else { 3660 /* 3661 * use Multiword DMA 3662 * Timings will be used for both PIO and DMA, 3663 * so adjust DMA mode if needed 3664 */ 3665 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3666 drvp->PIO_mode = drvp->DMA_mode + 2; 3667 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3668 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3669 drvp->PIO_mode - 2 : 0; 3670 if (drvp->DMA_mode == 0) 3671 drvp->PIO_mode = 0; 3672 } 3673 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3674 pio: switch (sc->sis_type) { 3675 case SIS_TYPE_NOUDMA: 3676 case SIS_TYPE_66: 3677 case SIS_TYPE_100OLD: 3678 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3679 SIS_TIM66_ACT_OFF(drive); 3680 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3681 SIS_TIM66_REC_OFF(drive); 3682 break; 3683 case SIS_TYPE_100NEW: 3684 case SIS_TYPE_133OLD: 3685 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3686 SIS_TIM100_ACT_OFF(drive); 3687 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3688 SIS_TIM100_REC_OFF(drive); 3689 break; 3690 default: 3691 printf("unknown SiS IDE type %d\n", 3692 sc->sis_type); 3693 } 3694 } 3695 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 3696 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 3697 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 3698 if (idedma_ctl != 0) { 3699 /* Add software bits in status register */ 3700 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3701 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3702 idedma_ctl); 3703 } 3704 pciide_print_modes(cp); 3705 } 3706 3707 void 3708 acer_chip_map(sc, pa) 3709 struct pciide_softc *sc; 3710 struct pci_attach_args *pa; 3711 { 3712 struct pciide_channel *cp; 3713 int channel; 3714 pcireg_t cr, interface; 3715 bus_size_t cmdsize, ctlsize; 3716 pcireg_t rev = PCI_REVISION(pa->pa_class); 3717 3718 if (pciide_chipen(sc, pa) == 0) 3719 return; 3720 printf("%s: bus-master DMA support present", 3721 sc->sc_wdcdev.sc_dev.dv_xname); 3722 pciide_mapreg_dma(sc, pa); 3723 printf("\n"); 3724 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3725 WDC_CAPABILITY_MODE; 3726 if (sc->sc_dma_ok) { 3727 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3728 if (rev >= 0x20) { 3729 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3730 if (rev >= 0xC4) 3731 sc->sc_wdcdev.UDMA_cap = 5; 3732 else if (rev >= 0xC2) 3733 sc->sc_wdcdev.UDMA_cap = 4; 3734 else 3735 sc->sc_wdcdev.UDMA_cap = 2; 3736 } 3737 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3738 sc->sc_wdcdev.irqack = pciide_irqack; 3739 } 3740 3741 sc->sc_wdcdev.PIO_cap = 4; 3742 sc->sc_wdcdev.DMA_cap = 2; 3743 sc->sc_wdcdev.set_modes = acer_setup_channel; 3744 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3745 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3746 3747 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3748 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3749 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3750 3751 /* Enable "microsoft register bits" R/W. */ 3752 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3753 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3754 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3755 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3756 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3757 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3758 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3759 ~ACER_CHANSTATUSREGS_RO); 3760 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3761 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3762 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3763 /* Don't use cr, re-read the real register content instead */ 3764 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3765 PCI_CLASS_REG)); 3766 3767 /* From linux: enable "Cable Detection" */ 3768 if (rev >= 0xC2) { 3769 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3770 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3771 | ACER_0x4B_CDETECT); 3772 } 3773 3774 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3775 cp = &sc->pciide_channels[channel]; 3776 if (pciide_chansetup(sc, channel, interface) == 0) 3777 continue; 3778 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3779 printf("%s: %s channel ignored (disabled)\n", 3780 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3781 continue; 3782 } 3783 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3784 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3785 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3786 if (cp->hw_ok == 0) 3787 continue; 3788 if (pciide_chan_candisable(cp)) { 3789 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3790 pci_conf_write(sc->sc_pc, sc->sc_tag, 3791 PCI_CLASS_REG, cr); 3792 } 3793 pciide_map_compat_intr(pa, cp, channel, interface); 3794 acer_setup_channel(&cp->wdc_channel); 3795 } 3796 } 3797 3798 void 3799 acer_setup_channel(chp) 3800 struct channel_softc *chp; 3801 { 3802 struct ata_drive_datas *drvp; 3803 int drive; 3804 u_int32_t acer_fifo_udma; 3805 u_int32_t idedma_ctl; 3806 struct pciide_channel *cp = (struct pciide_channel*)chp; 3807 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3808 3809 idedma_ctl = 0; 3810 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3811 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3812 acer_fifo_udma), DEBUG_PROBE); 3813 /* setup DMA if needed */ 3814 pciide_channel_dma_setup(cp); 3815 3816 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3817 DRIVE_UDMA) { /* check 80 pins cable */ 3818 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3819 ACER_0x4A_80PIN(chp->channel)) { 3820 if (chp->ch_drive[0].UDMA_mode > 2) 3821 chp->ch_drive[0].UDMA_mode = 2; 3822 if (chp->ch_drive[1].UDMA_mode > 2) 3823 chp->ch_drive[1].UDMA_mode = 2; 3824 } 3825 } 3826 3827 for (drive = 0; drive < 2; drive++) { 3828 drvp = &chp->ch_drive[drive]; 3829 /* If no drive, skip */ 3830 if ((drvp->drive_flags & DRIVE) == 0) 3831 continue; 3832 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3833 "channel %d drive %d 0x%x\n", chp->channel, drive, 3834 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3835 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3836 /* clear FIFO/DMA mode */ 3837 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3838 ACER_UDMA_EN(chp->channel, drive) | 3839 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3840 3841 /* add timing values, setup DMA if needed */ 3842 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3843 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3844 acer_fifo_udma |= 3845 ACER_FTH_OPL(chp->channel, drive, 0x1); 3846 goto pio; 3847 } 3848 3849 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3850 if (drvp->drive_flags & DRIVE_UDMA) { 3851 /* use Ultra/DMA */ 3852 drvp->drive_flags &= ~DRIVE_DMA; 3853 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3854 acer_fifo_udma |= 3855 ACER_UDMA_TIM(chp->channel, drive, 3856 acer_udma[drvp->UDMA_mode]); 3857 /* XXX disable if one drive < UDMA3 ? */ 3858 if (drvp->UDMA_mode >= 3) { 3859 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3860 ACER_0x4B, 3861 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3862 ACER_0x4B) | ACER_0x4B_UDMA66); 3863 } 3864 } else { 3865 /* 3866 * use Multiword DMA 3867 * Timings will be used for both PIO and DMA, 3868 * so adjust DMA mode if needed 3869 */ 3870 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3871 drvp->PIO_mode = drvp->DMA_mode + 2; 3872 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3873 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3874 drvp->PIO_mode - 2 : 0; 3875 if (drvp->DMA_mode == 0) 3876 drvp->PIO_mode = 0; 3877 } 3878 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3879 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3880 ACER_IDETIM(chp->channel, drive), 3881 acer_pio[drvp->PIO_mode]); 3882 } 3883 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3884 acer_fifo_udma), DEBUG_PROBE); 3885 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3886 if (idedma_ctl != 0) { 3887 /* Add software bits in status register */ 3888 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3889 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3890 idedma_ctl); 3891 } 3892 pciide_print_modes(cp); 3893 } 3894 3895 int 3896 acer_pci_intr(arg) 3897 void *arg; 3898 { 3899 struct pciide_softc *sc = arg; 3900 struct pciide_channel *cp; 3901 struct channel_softc *wdc_cp; 3902 int i, rv, crv; 3903 u_int32_t chids; 3904 3905 rv = 0; 3906 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3907 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3908 cp = &sc->pciide_channels[i]; 3909 wdc_cp = &cp->wdc_channel; 3910 /* If a compat channel skip. */ 3911 if (cp->compat) 3912 continue; 3913 if (chids & ACER_CHIDS_INT(i)) { 3914 crv = wdcintr(wdc_cp); 3915 if (crv == 0) 3916 printf("%s:%d: bogus intr\n", 3917 sc->sc_wdcdev.sc_dev.dv_xname, i); 3918 else 3919 rv = 1; 3920 } 3921 } 3922 return rv; 3923 } 3924 3925 void 3926 hpt_chip_map(sc, pa) 3927 struct pciide_softc *sc; 3928 struct pci_attach_args *pa; 3929 { 3930 struct pciide_channel *cp; 3931 int i, compatchan, revision; 3932 pcireg_t interface; 3933 bus_size_t cmdsize, ctlsize; 3934 3935 if (pciide_chipen(sc, pa) == 0) 3936 return; 3937 revision = PCI_REVISION(pa->pa_class); 3938 printf(": Triones/Highpoint "); 3939 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3940 printf("HPT374 IDE Controller\n"); 3941 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372) 3942 printf("HPT372 IDE Controller\n"); 3943 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 3944 if (revision == HPT372_REV) 3945 printf("HPT372 IDE Controller\n"); 3946 else if (revision == HPT370_REV) 3947 printf("HPT370 IDE Controller\n"); 3948 else if (revision == HPT370A_REV) 3949 printf("HPT370A IDE Controller\n"); 3950 else if (revision == HPT366_REV) 3951 printf("HPT366 IDE Controller\n"); 3952 else 3953 printf("unknown HPT IDE controller rev %d\n", revision); 3954 } else 3955 printf("unknown HPT IDE controller 0x%x\n", 3956 sc->sc_pp->ide_product); 3957 3958 /* 3959 * when the chip is in native mode it identifies itself as a 3960 * 'misc mass storage'. Fake interface in this case. 3961 */ 3962 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3963 interface = PCI_INTERFACE(pa->pa_class); 3964 } else { 3965 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3966 PCIIDE_INTERFACE_PCI(0); 3967 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3968 (revision == HPT370_REV || revision == HPT370A_REV || 3969 revision == HPT372_REV)) || 3970 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3971 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3972 interface |= PCIIDE_INTERFACE_PCI(1); 3973 } 3974 3975 printf("%s: bus-master DMA support present", 3976 sc->sc_wdcdev.sc_dev.dv_xname); 3977 pciide_mapreg_dma(sc, pa); 3978 printf("\n"); 3979 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3980 WDC_CAPABILITY_MODE; 3981 if (sc->sc_dma_ok) { 3982 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3983 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3984 sc->sc_wdcdev.irqack = pciide_irqack; 3985 } 3986 sc->sc_wdcdev.PIO_cap = 4; 3987 sc->sc_wdcdev.DMA_cap = 2; 3988 3989 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3990 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3991 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3992 revision == HPT366_REV) { 3993 sc->sc_wdcdev.UDMA_cap = 4; 3994 /* 3995 * The 366 has 2 PCI IDE functions, one for primary and one 3996 * for secondary. So we need to call pciide_mapregs_compat() 3997 * with the real channel 3998 */ 3999 if (pa->pa_function == 0) { 4000 compatchan = 0; 4001 } else if (pa->pa_function == 1) { 4002 compatchan = 1; 4003 } else { 4004 printf("%s: unexpected PCI function %d\n", 4005 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 4006 return; 4007 } 4008 sc->sc_wdcdev.nchannels = 1; 4009 } else { 4010 sc->sc_wdcdev.nchannels = 2; 4011 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 4012 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 4013 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 4014 revision == HPT372_REV)) 4015 sc->sc_wdcdev.UDMA_cap = 6; 4016 else 4017 sc->sc_wdcdev.UDMA_cap = 5; 4018 } 4019 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4020 cp = &sc->pciide_channels[i]; 4021 if (sc->sc_wdcdev.nchannels > 1) { 4022 compatchan = i; 4023 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 4024 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 4025 printf("%s: %s channel ignored (disabled)\n", 4026 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4027 continue; 4028 } 4029 } 4030 if (pciide_chansetup(sc, i, interface) == 0) 4031 continue; 4032 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4033 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4034 &ctlsize, hpt_pci_intr); 4035 } else { 4036 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 4037 &cmdsize, &ctlsize); 4038 } 4039 if (cp->hw_ok == 0) 4040 return; 4041 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4042 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4043 wdcattach(&cp->wdc_channel); 4044 hpt_setup_channel(&cp->wdc_channel); 4045 } 4046 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 4047 (revision == HPT370_REV || revision == HPT370A_REV || 4048 revision == HPT372_REV)) || 4049 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 4050 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 4051 /* 4052 * HPT370_REV and highter has a bit to disable interrupts, 4053 * make sure to clear it 4054 */ 4055 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 4056 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 4057 ~HPT_CSEL_IRQDIS); 4058 } 4059 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 4060 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 4061 revision == HPT372_REV ) || 4062 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 4063 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 4064 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 4065 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 4066 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 4067 return; 4068 } 4069 4070 void 4071 hpt_setup_channel(chp) 4072 struct channel_softc *chp; 4073 { 4074 struct ata_drive_datas *drvp; 4075 int drive; 4076 int cable; 4077 u_int32_t before, after; 4078 u_int32_t idedma_ctl; 4079 struct pciide_channel *cp = (struct pciide_channel*)chp; 4080 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4081 int revision = 4082 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 4083 4084 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 4085 4086 /* setup DMA if needed */ 4087 pciide_channel_dma_setup(cp); 4088 4089 idedma_ctl = 0; 4090 4091 /* Per drive settings */ 4092 for (drive = 0; drive < 2; drive++) { 4093 drvp = &chp->ch_drive[drive]; 4094 /* If no drive, skip */ 4095 if ((drvp->drive_flags & DRIVE) == 0) 4096 continue; 4097 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 4098 HPT_IDETIM(chp->channel, drive)); 4099 4100 /* add timing values, setup DMA if needed */ 4101 if (drvp->drive_flags & DRIVE_UDMA) { 4102 /* use Ultra/DMA */ 4103 drvp->drive_flags &= ~DRIVE_DMA; 4104 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 4105 drvp->UDMA_mode > 2) 4106 drvp->UDMA_mode = 2; 4107 switch (sc->sc_pp->ide_product) { 4108 case PCI_PRODUCT_TRIONES_HPT374: 4109 after = hpt374_udma[drvp->UDMA_mode]; 4110 break; 4111 case PCI_PRODUCT_TRIONES_HPT372: 4112 after = hpt372_udma[drvp->UDMA_mode]; 4113 break; 4114 case PCI_PRODUCT_TRIONES_HPT366: 4115 default: 4116 switch(revision) { 4117 case HPT372_REV: 4118 after = hpt372_udma[drvp->UDMA_mode]; 4119 break; 4120 case HPT370_REV: 4121 case HPT370A_REV: 4122 after = hpt370_udma[drvp->UDMA_mode]; 4123 break; 4124 case HPT366_REV: 4125 default: 4126 after = hpt366_udma[drvp->UDMA_mode]; 4127 break; 4128 } 4129 } 4130 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4131 } else if (drvp->drive_flags & DRIVE_DMA) { 4132 /* 4133 * use Multiword DMA. 4134 * Timings will be used for both PIO and DMA, so adjust 4135 * DMA mode if needed 4136 */ 4137 if (drvp->PIO_mode >= 3 && 4138 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 4139 drvp->DMA_mode = drvp->PIO_mode - 2; 4140 } 4141 switch (sc->sc_pp->ide_product) { 4142 case PCI_PRODUCT_TRIONES_HPT374: 4143 after = hpt374_dma[drvp->DMA_mode]; 4144 break; 4145 case PCI_PRODUCT_TRIONES_HPT372: 4146 after = hpt372_dma[drvp->DMA_mode]; 4147 break; 4148 case PCI_PRODUCT_TRIONES_HPT366: 4149 default: 4150 switch(revision) { 4151 case HPT372_REV: 4152 after = hpt372_dma[drvp->DMA_mode]; 4153 break; 4154 case HPT370_REV: 4155 case HPT370A_REV: 4156 after = hpt370_dma[drvp->DMA_mode]; 4157 break; 4158 case HPT366_REV: 4159 default: 4160 after = hpt366_dma[drvp->DMA_mode]; 4161 break; 4162 } 4163 } 4164 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4165 } else { 4166 /* PIO only */ 4167 switch (sc->sc_pp->ide_product) { 4168 case PCI_PRODUCT_TRIONES_HPT374: 4169 after = hpt374_pio[drvp->PIO_mode]; 4170 break; 4171 case PCI_PRODUCT_TRIONES_HPT372: 4172 after = hpt372_pio[drvp->PIO_mode]; 4173 break; 4174 case PCI_PRODUCT_TRIONES_HPT366: 4175 default: 4176 switch(revision) { 4177 case HPT372_REV: 4178 after = hpt372_pio[drvp->PIO_mode]; 4179 break; 4180 case HPT370_REV: 4181 case HPT370A_REV: 4182 after = hpt370_pio[drvp->PIO_mode]; 4183 break; 4184 case HPT366_REV: 4185 default: 4186 after = hpt366_pio[drvp->PIO_mode]; 4187 break; 4188 } 4189 } 4190 } 4191 pci_conf_write(sc->sc_pc, sc->sc_tag, 4192 HPT_IDETIM(chp->channel, drive), after); 4193 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 4194 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 4195 after, before), DEBUG_PROBE); 4196 } 4197 if (idedma_ctl != 0) { 4198 /* Add software bits in status register */ 4199 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4200 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4201 idedma_ctl); 4202 } 4203 pciide_print_modes(cp); 4204 } 4205 4206 int 4207 hpt_pci_intr(arg) 4208 void *arg; 4209 { 4210 struct pciide_softc *sc = arg; 4211 struct pciide_channel *cp; 4212 struct channel_softc *wdc_cp; 4213 int rv = 0; 4214 int dmastat, i, crv; 4215 4216 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4217 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4218 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4219 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4220 IDEDMA_CTL_INTR) 4221 continue; 4222 cp = &sc->pciide_channels[i]; 4223 wdc_cp = &cp->wdc_channel; 4224 crv = wdcintr(wdc_cp); 4225 if (crv == 0) { 4226 printf("%s:%d: bogus intr\n", 4227 sc->sc_wdcdev.sc_dev.dv_xname, i); 4228 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4229 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4230 } else 4231 rv = 1; 4232 } 4233 return rv; 4234 } 4235 4236 4237 /* Macros to test product */ 4238 #define PDC_IS_262(sc) \ 4239 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 4240 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 4241 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 4242 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4243 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4244 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4245 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4246 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4247 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4248 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4249 #define PDC_IS_265(sc) \ 4250 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 4251 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 4252 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4253 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4254 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4255 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4256 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4257 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4258 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4259 #define PDC_IS_268(sc) \ 4260 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4261 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4262 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4263 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4264 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4265 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4266 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4267 #define PDC_IS_276(sc) \ 4268 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4269 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4270 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4271 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4272 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4273 4274 void 4275 pdc202xx_chip_map(sc, pa) 4276 struct pciide_softc *sc; 4277 struct pci_attach_args *pa; 4278 { 4279 struct pciide_channel *cp; 4280 int channel; 4281 pcireg_t interface, st, mode; 4282 bus_size_t cmdsize, ctlsize; 4283 4284 if (!PDC_IS_268(sc)) { 4285 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4286 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 4287 st), DEBUG_PROBE); 4288 } 4289 if (pciide_chipen(sc, pa) == 0) 4290 return; 4291 4292 /* turn off RAID mode */ 4293 if (!PDC_IS_268(sc)) 4294 st &= ~PDC2xx_STATE_IDERAID; 4295 4296 /* 4297 * can't rely on the PCI_CLASS_REG content if the chip was in raid 4298 * mode. We have to fake interface 4299 */ 4300 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 4301 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 4302 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4303 4304 printf("%s: bus-master DMA support present", 4305 sc->sc_wdcdev.sc_dev.dv_xname); 4306 pciide_mapreg_dma(sc, pa); 4307 printf("\n"); 4308 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4309 WDC_CAPABILITY_MODE; 4310 if (sc->sc_dma_ok) { 4311 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4312 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4313 sc->sc_wdcdev.irqack = pciide_irqack; 4314 } 4315 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 4316 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 4317 sc->sc_wdcdev.cap |= WDC_CAPABILITY_RAID; 4318 sc->sc_wdcdev.PIO_cap = 4; 4319 sc->sc_wdcdev.DMA_cap = 2; 4320 if (PDC_IS_276(sc)) 4321 sc->sc_wdcdev.UDMA_cap = 6; 4322 else if (PDC_IS_265(sc)) 4323 sc->sc_wdcdev.UDMA_cap = 5; 4324 else if (PDC_IS_262(sc)) 4325 sc->sc_wdcdev.UDMA_cap = 4; 4326 else 4327 sc->sc_wdcdev.UDMA_cap = 2; 4328 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 4329 pdc20268_setup_channel : pdc202xx_setup_channel; 4330 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4331 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4332 4333 if (!PDC_IS_268(sc)) { 4334 /* setup failsafe defaults */ 4335 mode = 0; 4336 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 4337 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 4338 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 4339 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 4340 for (channel = 0; 4341 channel < sc->sc_wdcdev.nchannels; 4342 channel++) { 4343 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 4344 "drive 0 initial timings 0x%x, now 0x%x\n", 4345 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 4346 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 4347 DEBUG_PROBE); 4348 pci_conf_write(sc->sc_pc, sc->sc_tag, 4349 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 4350 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 4351 "drive 1 initial timings 0x%x, now 0x%x\n", 4352 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 4353 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 4354 pci_conf_write(sc->sc_pc, sc->sc_tag, 4355 PDC2xx_TIM(channel, 1), mode); 4356 } 4357 4358 mode = PDC2xx_SCR_DMA; 4359 if (PDC_IS_262(sc)) { 4360 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 4361 } else { 4362 /* the BIOS set it up this way */ 4363 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 4364 } 4365 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 4366 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 4367 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 4368 "now 0x%x\n", 4369 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4370 PDC2xx_SCR), 4371 mode), DEBUG_PROBE); 4372 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4373 PDC2xx_SCR, mode); 4374 4375 /* controller initial state register is OK even without BIOS */ 4376 /* Set DMA mode to IDE DMA compatibility */ 4377 mode = 4378 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 4379 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 4380 DEBUG_PROBE); 4381 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 4382 mode | 0x1); 4383 mode = 4384 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 4385 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 4386 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 4387 mode | 0x1); 4388 } 4389 4390 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4391 cp = &sc->pciide_channels[channel]; 4392 if (pciide_chansetup(sc, channel, interface) == 0) 4393 continue; 4394 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 4395 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 4396 printf("%s: %s channel ignored (disabled)\n", 4397 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4398 continue; 4399 } 4400 if (PDC_IS_265(sc)) 4401 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4402 pdc20265_pci_intr); 4403 else 4404 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4405 pdc202xx_pci_intr); 4406 if (cp->hw_ok == 0) 4407 continue; 4408 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 4409 st &= ~(PDC_IS_262(sc) ? 4410 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 4411 pciide_map_compat_intr(pa, cp, channel, interface); 4412 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 4413 } 4414 if (!PDC_IS_268(sc)) { 4415 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 4416 "0x%x\n", st), DEBUG_PROBE); 4417 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 4418 } 4419 return; 4420 } 4421 4422 void 4423 pdc202xx_setup_channel(chp) 4424 struct channel_softc *chp; 4425 { 4426 struct ata_drive_datas *drvp; 4427 int drive; 4428 pcireg_t mode, st; 4429 u_int32_t idedma_ctl, scr, atapi; 4430 struct pciide_channel *cp = (struct pciide_channel*)chp; 4431 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4432 int channel = chp->channel; 4433 4434 /* setup DMA if needed */ 4435 pciide_channel_dma_setup(cp); 4436 4437 idedma_ctl = 0; 4438 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 4439 sc->sc_wdcdev.sc_dev.dv_xname, 4440 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 4441 DEBUG_PROBE); 4442 4443 /* Per channel settings */ 4444 if (PDC_IS_262(sc)) { 4445 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4446 PDC262_U66); 4447 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4448 /* Trim UDMA mode */ 4449 if ((st & PDC262_STATE_80P(channel)) != 0 || 4450 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4451 chp->ch_drive[0].UDMA_mode <= 2) || 4452 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4453 chp->ch_drive[1].UDMA_mode <= 2)) { 4454 if (chp->ch_drive[0].UDMA_mode > 2) 4455 chp->ch_drive[0].UDMA_mode = 2; 4456 if (chp->ch_drive[1].UDMA_mode > 2) 4457 chp->ch_drive[1].UDMA_mode = 2; 4458 } 4459 /* Set U66 if needed */ 4460 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4461 chp->ch_drive[0].UDMA_mode > 2) || 4462 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4463 chp->ch_drive[1].UDMA_mode > 2)) 4464 scr |= PDC262_U66_EN(channel); 4465 else 4466 scr &= ~PDC262_U66_EN(channel); 4467 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4468 PDC262_U66, scr); 4469 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 4470 sc->sc_wdcdev.sc_dev.dv_xname, channel, 4471 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4472 PDC262_ATAPI(channel))), DEBUG_PROBE); 4473 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 4474 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 4475 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4476 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4477 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 4478 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4479 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4480 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 4481 atapi = 0; 4482 else 4483 atapi = PDC262_ATAPI_UDMA; 4484 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4485 PDC262_ATAPI(channel), atapi); 4486 } 4487 } 4488 for (drive = 0; drive < 2; drive++) { 4489 drvp = &chp->ch_drive[drive]; 4490 /* If no drive, skip */ 4491 if ((drvp->drive_flags & DRIVE) == 0) 4492 continue; 4493 mode = 0; 4494 if (drvp->drive_flags & DRIVE_UDMA) { 4495 /* use Ultra/DMA */ 4496 drvp->drive_flags &= ~DRIVE_DMA; 4497 mode = PDC2xx_TIM_SET_MB(mode, 4498 pdc2xx_udma_mb[drvp->UDMA_mode]); 4499 mode = PDC2xx_TIM_SET_MC(mode, 4500 pdc2xx_udma_mc[drvp->UDMA_mode]); 4501 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4502 } else if (drvp->drive_flags & DRIVE_DMA) { 4503 mode = PDC2xx_TIM_SET_MB(mode, 4504 pdc2xx_dma_mb[drvp->DMA_mode]); 4505 mode = PDC2xx_TIM_SET_MC(mode, 4506 pdc2xx_dma_mc[drvp->DMA_mode]); 4507 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4508 } else { 4509 mode = PDC2xx_TIM_SET_MB(mode, 4510 pdc2xx_dma_mb[0]); 4511 mode = PDC2xx_TIM_SET_MC(mode, 4512 pdc2xx_dma_mc[0]); 4513 } 4514 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 4515 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 4516 if (drvp->drive_flags & DRIVE_ATA) 4517 mode |= PDC2xx_TIM_PRE; 4518 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 4519 if (drvp->PIO_mode >= 3) { 4520 mode |= PDC2xx_TIM_IORDY; 4521 if (drive == 0) 4522 mode |= PDC2xx_TIM_IORDYp; 4523 } 4524 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 4525 "timings 0x%x\n", 4526 sc->sc_wdcdev.sc_dev.dv_xname, 4527 chp->channel, drive, mode), DEBUG_PROBE); 4528 pci_conf_write(sc->sc_pc, sc->sc_tag, 4529 PDC2xx_TIM(chp->channel, drive), mode); 4530 } 4531 if (idedma_ctl != 0) { 4532 /* Add software bits in status register */ 4533 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4534 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4535 idedma_ctl); 4536 } 4537 pciide_print_modes(cp); 4538 } 4539 4540 void 4541 pdc20268_setup_channel(chp) 4542 struct channel_softc *chp; 4543 { 4544 struct ata_drive_datas *drvp; 4545 int drive; 4546 u_int32_t idedma_ctl; 4547 struct pciide_channel *cp = (struct pciide_channel*)chp; 4548 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4549 int u100; 4550 4551 /* setup DMA if needed */ 4552 pciide_channel_dma_setup(cp); 4553 4554 idedma_ctl = 0; 4555 4556 /* I don't know what this is for, FreeBSD does it ... */ 4557 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4558 IDEDMA_CMD + 0x1, 0x0b); 4559 4560 /* 4561 * I don't know what this is for; FreeBSD checks this ... this is not 4562 * cable type detect. 4563 */ 4564 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4565 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 4566 4567 for (drive = 0; drive < 2; drive++) { 4568 drvp = &chp->ch_drive[drive]; 4569 /* If no drive, skip */ 4570 if ((drvp->drive_flags & DRIVE) == 0) 4571 continue; 4572 if (drvp->drive_flags & DRIVE_UDMA) { 4573 /* use Ultra/DMA */ 4574 drvp->drive_flags &= ~DRIVE_DMA; 4575 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4576 if (drvp->UDMA_mode > 2 && u100 == 0) 4577 drvp->UDMA_mode = 2; 4578 } else if (drvp->drive_flags & DRIVE_DMA) { 4579 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4580 } 4581 } 4582 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 4583 if (idedma_ctl != 0) { 4584 /* Add software bits in status register */ 4585 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4586 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4587 idedma_ctl); 4588 } 4589 pciide_print_modes(cp); 4590 } 4591 4592 int 4593 pdc202xx_pci_intr(arg) 4594 void *arg; 4595 { 4596 struct pciide_softc *sc = arg; 4597 struct pciide_channel *cp; 4598 struct channel_softc *wdc_cp; 4599 int i, rv, crv; 4600 u_int32_t scr; 4601 4602 rv = 0; 4603 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 4604 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4605 cp = &sc->pciide_channels[i]; 4606 wdc_cp = &cp->wdc_channel; 4607 /* If a compat channel skip. */ 4608 if (cp->compat) 4609 continue; 4610 if (scr & PDC2xx_SCR_INT(i)) { 4611 crv = wdcintr(wdc_cp); 4612 if (crv == 0) 4613 printf("%s:%d: bogus intr (reg 0x%x)\n", 4614 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 4615 else 4616 rv = 1; 4617 } 4618 } 4619 return rv; 4620 } 4621 4622 int 4623 pdc20265_pci_intr(arg) 4624 void *arg; 4625 { 4626 struct pciide_softc *sc = arg; 4627 struct pciide_channel *cp; 4628 struct channel_softc *wdc_cp; 4629 int i, rv, crv; 4630 u_int32_t dmastat; 4631 4632 rv = 0; 4633 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4634 cp = &sc->pciide_channels[i]; 4635 wdc_cp = &cp->wdc_channel; 4636 /* If a compat channel skip. */ 4637 if (cp->compat) 4638 continue; 4639 /* 4640 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 4641 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 4642 * So use it instead (requires 2 reg reads instead of 1, 4643 * but we can't do it another way). 4644 */ 4645 dmastat = bus_space_read_1(sc->sc_dma_iot, 4646 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4647 if((dmastat & IDEDMA_CTL_INTR) == 0) 4648 continue; 4649 crv = wdcintr(wdc_cp); 4650 if (crv == 0) 4651 printf("%s:%d: bogus intr\n", 4652 sc->sc_wdcdev.sc_dev.dv_xname, i); 4653 else 4654 rv = 1; 4655 } 4656 return rv; 4657 } 4658 4659 void 4660 opti_chip_map(sc, pa) 4661 struct pciide_softc *sc; 4662 struct pci_attach_args *pa; 4663 { 4664 struct pciide_channel *cp; 4665 bus_size_t cmdsize, ctlsize; 4666 pcireg_t interface; 4667 u_int8_t init_ctrl; 4668 int channel; 4669 4670 if (pciide_chipen(sc, pa) == 0) 4671 return; 4672 printf("%s: bus-master DMA support present", 4673 sc->sc_wdcdev.sc_dev.dv_xname); 4674 4675 /* 4676 * XXXSCW: 4677 * There seem to be a couple of buggy revisions/implementations 4678 * of the OPTi pciide chipset. This kludge seems to fix one of 4679 * the reported problems (PR/11644) but still fails for the 4680 * other (PR/13151), although the latter may be due to other 4681 * issues too... 4682 */ 4683 if (PCI_REVISION(pa->pa_class) <= 0x12) { 4684 printf(" but disabled due to chip rev. <= 0x12"); 4685 sc->sc_dma_ok = 0; 4686 } else 4687 pciide_mapreg_dma(sc, pa); 4688 4689 printf("\n"); 4690 4691 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4692 WDC_CAPABILITY_MODE; 4693 sc->sc_wdcdev.PIO_cap = 4; 4694 if (sc->sc_dma_ok) { 4695 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4696 sc->sc_wdcdev.irqack = pciide_irqack; 4697 sc->sc_wdcdev.DMA_cap = 2; 4698 } 4699 sc->sc_wdcdev.set_modes = opti_setup_channel; 4700 4701 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4702 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4703 4704 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 4705 OPTI_REG_INIT_CONTROL); 4706 4707 interface = PCI_INTERFACE(pa->pa_class); 4708 4709 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4710 cp = &sc->pciide_channels[channel]; 4711 if (pciide_chansetup(sc, channel, interface) == 0) 4712 continue; 4713 if (channel == 1 && 4714 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 4715 printf("%s: %s channel ignored (disabled)\n", 4716 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4717 continue; 4718 } 4719 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4720 pciide_pci_intr); 4721 if (cp->hw_ok == 0) 4722 continue; 4723 pciide_map_compat_intr(pa, cp, channel, interface); 4724 if (cp->hw_ok == 0) 4725 continue; 4726 opti_setup_channel(&cp->wdc_channel); 4727 } 4728 } 4729 4730 void 4731 opti_setup_channel(chp) 4732 struct channel_softc *chp; 4733 { 4734 struct ata_drive_datas *drvp; 4735 struct pciide_channel *cp = (struct pciide_channel*)chp; 4736 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4737 int drive, spd; 4738 int mode[2]; 4739 u_int8_t rv, mr; 4740 4741 /* 4742 * The `Delay' and `Address Setup Time' fields of the 4743 * Miscellaneous Register are always zero initially. 4744 */ 4745 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 4746 mr &= ~(OPTI_MISC_DELAY_MASK | 4747 OPTI_MISC_ADDR_SETUP_MASK | 4748 OPTI_MISC_INDEX_MASK); 4749 4750 /* Prime the control register before setting timing values */ 4751 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 4752 4753 /* Determine the clockrate of the PCIbus the chip is attached to */ 4754 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 4755 spd &= OPTI_STRAP_PCI_SPEED_MASK; 4756 4757 /* setup DMA if needed */ 4758 pciide_channel_dma_setup(cp); 4759 4760 for (drive = 0; drive < 2; drive++) { 4761 drvp = &chp->ch_drive[drive]; 4762 /* If no drive, skip */ 4763 if ((drvp->drive_flags & DRIVE) == 0) { 4764 mode[drive] = -1; 4765 continue; 4766 } 4767 4768 if ((drvp->drive_flags & DRIVE_DMA)) { 4769 /* 4770 * Timings will be used for both PIO and DMA, 4771 * so adjust DMA mode if needed 4772 */ 4773 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 4774 drvp->PIO_mode = drvp->DMA_mode + 2; 4775 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 4776 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 4777 drvp->PIO_mode - 2 : 0; 4778 if (drvp->DMA_mode == 0) 4779 drvp->PIO_mode = 0; 4780 4781 mode[drive] = drvp->DMA_mode + 5; 4782 } else 4783 mode[drive] = drvp->PIO_mode; 4784 4785 if (drive && mode[0] >= 0 && 4786 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 4787 /* 4788 * Can't have two drives using different values 4789 * for `Address Setup Time'. 4790 * Slow down the faster drive to compensate. 4791 */ 4792 int d = (opti_tim_as[spd][mode[0]] > 4793 opti_tim_as[spd][mode[1]]) ? 0 : 1; 4794 4795 mode[d] = mode[1-d]; 4796 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4797 chp->ch_drive[d].DMA_mode = 0; 4798 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 4799 } 4800 } 4801 4802 for (drive = 0; drive < 2; drive++) { 4803 int m; 4804 if ((m = mode[drive]) < 0) 4805 continue; 4806 4807 /* Set the Address Setup Time and select appropriate index */ 4808 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4809 rv |= OPTI_MISC_INDEX(drive); 4810 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4811 4812 /* Set the pulse width and recovery timing parameters */ 4813 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4814 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4815 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4816 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4817 4818 /* Set the Enhanced Mode register appropriately */ 4819 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4820 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4821 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4822 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4823 } 4824 4825 /* Finally, enable the timings */ 4826 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4827 4828 pciide_print_modes(cp); 4829 } 4830 4831 #define ACARD_IS_850(sc) \ 4832 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4833 4834 void 4835 acard_chip_map(sc, pa) 4836 struct pciide_softc *sc; 4837 struct pci_attach_args *pa; 4838 { 4839 struct pciide_channel *cp; 4840 int i; 4841 pcireg_t interface; 4842 bus_size_t cmdsize, ctlsize; 4843 4844 if (pciide_chipen(sc, pa) == 0) 4845 return; 4846 4847 /* 4848 * when the chip is in native mode it identifies itself as a 4849 * 'misc mass storage'. Fake interface in this case. 4850 */ 4851 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4852 interface = PCI_INTERFACE(pa->pa_class); 4853 } else { 4854 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4855 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4856 } 4857 4858 printf("%s: bus-master DMA support present", 4859 sc->sc_wdcdev.sc_dev.dv_xname); 4860 pciide_mapreg_dma(sc, pa); 4861 printf("\n"); 4862 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4863 WDC_CAPABILITY_MODE; 4864 4865 if (sc->sc_dma_ok) { 4866 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4867 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4868 sc->sc_wdcdev.irqack = pciide_irqack; 4869 } 4870 sc->sc_wdcdev.PIO_cap = 4; 4871 sc->sc_wdcdev.DMA_cap = 2; 4872 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4873 4874 sc->sc_wdcdev.set_modes = acard_setup_channel; 4875 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4876 sc->sc_wdcdev.nchannels = 2; 4877 4878 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4879 cp = &sc->pciide_channels[i]; 4880 if (pciide_chansetup(sc, i, interface) == 0) 4881 continue; 4882 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4883 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4884 &ctlsize, pciide_pci_intr); 4885 } else { 4886 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4887 &cmdsize, &ctlsize); 4888 } 4889 if (cp->hw_ok == 0) 4890 return; 4891 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4892 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4893 wdcattach(&cp->wdc_channel); 4894 acard_setup_channel(&cp->wdc_channel); 4895 } 4896 if (!ACARD_IS_850(sc)) { 4897 u_int32_t reg; 4898 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4899 reg &= ~ATP860_CTRL_INT; 4900 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4901 } 4902 } 4903 4904 void 4905 acard_setup_channel(chp) 4906 struct channel_softc *chp; 4907 { 4908 struct ata_drive_datas *drvp; 4909 struct pciide_channel *cp = (struct pciide_channel*)chp; 4910 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4911 int channel = chp->channel; 4912 int drive; 4913 u_int32_t idetime, udma_mode; 4914 u_int32_t idedma_ctl; 4915 4916 /* setup DMA if needed */ 4917 pciide_channel_dma_setup(cp); 4918 4919 if (ACARD_IS_850(sc)) { 4920 idetime = 0; 4921 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4922 udma_mode &= ~ATP850_UDMA_MASK(channel); 4923 } else { 4924 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4925 idetime &= ~ATP860_SETTIME_MASK(channel); 4926 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4927 udma_mode &= ~ATP860_UDMA_MASK(channel); 4928 4929 /* check 80 pins cable */ 4930 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4931 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4932 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4933 & ATP860_CTRL_80P(chp->channel)) { 4934 if (chp->ch_drive[0].UDMA_mode > 2) 4935 chp->ch_drive[0].UDMA_mode = 2; 4936 if (chp->ch_drive[1].UDMA_mode > 2) 4937 chp->ch_drive[1].UDMA_mode = 2; 4938 } 4939 } 4940 } 4941 4942 idedma_ctl = 0; 4943 4944 /* Per drive settings */ 4945 for (drive = 0; drive < 2; drive++) { 4946 drvp = &chp->ch_drive[drive]; 4947 /* If no drive, skip */ 4948 if ((drvp->drive_flags & DRIVE) == 0) 4949 continue; 4950 /* add timing values, setup DMA if needed */ 4951 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4952 (drvp->drive_flags & DRIVE_UDMA)) { 4953 /* use Ultra/DMA */ 4954 if (ACARD_IS_850(sc)) { 4955 idetime |= ATP850_SETTIME(drive, 4956 acard_act_udma[drvp->UDMA_mode], 4957 acard_rec_udma[drvp->UDMA_mode]); 4958 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4959 acard_udma_conf[drvp->UDMA_mode]); 4960 } else { 4961 idetime |= ATP860_SETTIME(channel, drive, 4962 acard_act_udma[drvp->UDMA_mode], 4963 acard_rec_udma[drvp->UDMA_mode]); 4964 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4965 acard_udma_conf[drvp->UDMA_mode]); 4966 } 4967 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4968 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4969 (drvp->drive_flags & DRIVE_DMA)) { 4970 /* use Multiword DMA */ 4971 drvp->drive_flags &= ~DRIVE_UDMA; 4972 if (ACARD_IS_850(sc)) { 4973 idetime |= ATP850_SETTIME(drive, 4974 acard_act_dma[drvp->DMA_mode], 4975 acard_rec_dma[drvp->DMA_mode]); 4976 } else { 4977 idetime |= ATP860_SETTIME(channel, drive, 4978 acard_act_dma[drvp->DMA_mode], 4979 acard_rec_dma[drvp->DMA_mode]); 4980 } 4981 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4982 } else { 4983 /* PIO only */ 4984 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4985 if (ACARD_IS_850(sc)) { 4986 idetime |= ATP850_SETTIME(drive, 4987 acard_act_pio[drvp->PIO_mode], 4988 acard_rec_pio[drvp->PIO_mode]); 4989 } else { 4990 idetime |= ATP860_SETTIME(channel, drive, 4991 acard_act_pio[drvp->PIO_mode], 4992 acard_rec_pio[drvp->PIO_mode]); 4993 } 4994 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4995 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4996 | ATP8x0_CTRL_EN(channel)); 4997 } 4998 } 4999 5000 if (idedma_ctl != 0) { 5001 /* Add software bits in status register */ 5002 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5003 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 5004 } 5005 pciide_print_modes(cp); 5006 5007 if (ACARD_IS_850(sc)) { 5008 pci_conf_write(sc->sc_pc, sc->sc_tag, 5009 ATP850_IDETIME(channel), idetime); 5010 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 5011 } else { 5012 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 5013 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 5014 } 5015 } 5016 5017 int 5018 acard_pci_intr(arg) 5019 void *arg; 5020 { 5021 struct pciide_softc *sc = arg; 5022 struct pciide_channel *cp; 5023 struct channel_softc *wdc_cp; 5024 int rv = 0; 5025 int dmastat, i, crv; 5026 5027 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5028 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5029 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 5030 if ((dmastat & IDEDMA_CTL_INTR) == 0) 5031 continue; 5032 cp = &sc->pciide_channels[i]; 5033 wdc_cp = &cp->wdc_channel; 5034 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 5035 (void)wdcintr(wdc_cp); 5036 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5037 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 5038 continue; 5039 } 5040 crv = wdcintr(wdc_cp); 5041 if (crv == 0) 5042 printf("%s:%d: bogus intr\n", 5043 sc->sc_wdcdev.sc_dev.dv_xname, i); 5044 else if (crv == 1) 5045 rv = 1; 5046 else if (rv == 0) 5047 rv = crv; 5048 } 5049 return rv; 5050 } 5051 5052 static int 5053 sl82c105_bugchk(struct pci_attach_args *pa) 5054 { 5055 5056 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 5057 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 5058 return (0); 5059 5060 if (PCI_REVISION(pa->pa_class) <= 0x05) 5061 return (1); 5062 5063 return (0); 5064 } 5065 5066 void 5067 sl82c105_chip_map(sc, pa) 5068 struct pciide_softc *sc; 5069 struct pci_attach_args *pa; 5070 { 5071 struct pciide_channel *cp; 5072 bus_size_t cmdsize, ctlsize; 5073 pcireg_t interface, idecr; 5074 int channel; 5075 5076 if (pciide_chipen(sc, pa) == 0) 5077 return; 5078 5079 printf("%s: bus-master DMA support present", 5080 sc->sc_wdcdev.sc_dev.dv_xname); 5081 5082 /* 5083 * Check to see if we're part of the Winbond 83c553 Southbridge. 5084 * If so, we need to disable DMA on rev. <= 5 of that chip. 5085 */ 5086 if (pci_find_device(pa, sl82c105_bugchk)) { 5087 printf(" but disabled due to 83c553 rev. <= 0x05"); 5088 sc->sc_dma_ok = 0; 5089 } else 5090 pciide_mapreg_dma(sc, pa); 5091 printf("\n"); 5092 5093 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 5094 WDC_CAPABILITY_MODE; 5095 sc->sc_wdcdev.PIO_cap = 4; 5096 if (sc->sc_dma_ok) { 5097 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 5098 sc->sc_wdcdev.irqack = pciide_irqack; 5099 sc->sc_wdcdev.DMA_cap = 2; 5100 } 5101 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 5102 5103 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5104 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5105 5106 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 5107 5108 interface = PCI_INTERFACE(pa->pa_class); 5109 5110 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5111 cp = &sc->pciide_channels[channel]; 5112 if (pciide_chansetup(sc, channel, interface) == 0) 5113 continue; 5114 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 5115 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 5116 printf("%s: %s channel ignored (disabled)\n", 5117 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 5118 continue; 5119 } 5120 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5121 pciide_pci_intr); 5122 if (cp->hw_ok == 0) 5123 continue; 5124 pciide_map_compat_intr(pa, cp, channel, interface); 5125 if (cp->hw_ok == 0) 5126 continue; 5127 sl82c105_setup_channel(&cp->wdc_channel); 5128 } 5129 } 5130 5131 void 5132 sl82c105_setup_channel(chp) 5133 struct channel_softc *chp; 5134 { 5135 struct ata_drive_datas *drvp; 5136 struct pciide_channel *cp = (struct pciide_channel*)chp; 5137 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5138 int pxdx_reg, drive; 5139 pcireg_t pxdx; 5140 5141 /* Set up DMA if needed. */ 5142 pciide_channel_dma_setup(cp); 5143 5144 for (drive = 0; drive < 2; drive++) { 5145 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 5146 : SYMPH_P1D0CR) + (drive * 4); 5147 5148 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 5149 5150 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 5151 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 5152 5153 drvp = &chp->ch_drive[drive]; 5154 /* If no drive, skip. */ 5155 if ((drvp->drive_flags & DRIVE) == 0) { 5156 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 5157 continue; 5158 } 5159 5160 if (drvp->drive_flags & DRIVE_DMA) { 5161 /* 5162 * Timings will be used for both PIO and DMA, 5163 * so adjust DMA mode if needed. 5164 */ 5165 if (drvp->PIO_mode >= 3) { 5166 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 5167 drvp->DMA_mode = drvp->PIO_mode - 2; 5168 if (drvp->DMA_mode < 1) { 5169 /* 5170 * Can't mix both PIO and DMA. 5171 * Disable DMA. 5172 */ 5173 drvp->drive_flags &= ~DRIVE_DMA; 5174 } 5175 } else { 5176 /* 5177 * Can't mix both PIO and DMA. Disable 5178 * DMA. 5179 */ 5180 drvp->drive_flags &= ~DRIVE_DMA; 5181 } 5182 } 5183 5184 if (drvp->drive_flags & DRIVE_DMA) { 5185 /* Use multi-word DMA. */ 5186 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 5187 PxDx_CMD_ON_SHIFT; 5188 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 5189 } else { 5190 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 5191 PxDx_CMD_ON_SHIFT; 5192 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 5193 } 5194 5195 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 5196 5197 /* ...and set the mode for this drive. */ 5198 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 5199 } 5200 5201 pciide_print_modes(cp); 5202 } 5203 5204 void 5205 serverworks_chip_map(sc, pa) 5206 struct pciide_softc *sc; 5207 struct pci_attach_args *pa; 5208 { 5209 struct pciide_channel *cp; 5210 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 5211 pcitag_t pcib_tag; 5212 int channel; 5213 bus_size_t cmdsize, ctlsize; 5214 5215 if (pciide_chipen(sc, pa) == 0) 5216 return; 5217 5218 printf("%s: bus-master DMA support present", 5219 sc->sc_wdcdev.sc_dev.dv_xname); 5220 pciide_mapreg_dma(sc, pa); 5221 printf("\n"); 5222 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5223 WDC_CAPABILITY_MODE; 5224 5225 if (sc->sc_dma_ok) { 5226 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5227 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5228 sc->sc_wdcdev.irqack = pciide_irqack; 5229 } 5230 sc->sc_wdcdev.PIO_cap = 4; 5231 sc->sc_wdcdev.DMA_cap = 2; 5232 switch (sc->sc_pp->ide_product) { 5233 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 5234 sc->sc_wdcdev.UDMA_cap = 2; 5235 break; 5236 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 5237 if (PCI_REVISION(pa->pa_class) < 0x92) 5238 sc->sc_wdcdev.UDMA_cap = 4; 5239 else 5240 sc->sc_wdcdev.UDMA_cap = 5; 5241 break; 5242 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 5243 sc->sc_wdcdev.UDMA_cap = 5; 5244 break; 5245 } 5246 5247 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 5248 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5249 sc->sc_wdcdev.nchannels = 2; 5250 5251 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5252 cp = &sc->pciide_channels[channel]; 5253 if (pciide_chansetup(sc, channel, interface) == 0) 5254 continue; 5255 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5256 serverworks_pci_intr); 5257 if (cp->hw_ok == 0) 5258 return; 5259 pciide_map_compat_intr(pa, cp, channel, interface); 5260 if (cp->hw_ok == 0) 5261 return; 5262 serverworks_setup_channel(&cp->wdc_channel); 5263 } 5264 5265 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 5266 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 5267 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 5268 } 5269 5270 void 5271 serverworks_setup_channel(chp) 5272 struct channel_softc *chp; 5273 { 5274 struct ata_drive_datas *drvp; 5275 struct pciide_channel *cp = (struct pciide_channel*)chp; 5276 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5277 int channel = chp->channel; 5278 int drive, unit; 5279 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 5280 u_int32_t idedma_ctl; 5281 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 5282 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 5283 5284 /* setup DMA if needed */ 5285 pciide_channel_dma_setup(cp); 5286 5287 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 5288 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 5289 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 5290 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 5291 5292 pio_time &= ~(0xffff << (16 * channel)); 5293 dma_time &= ~(0xffff << (16 * channel)); 5294 pio_mode &= ~(0xff << (8 * channel + 16)); 5295 udma_mode &= ~(0xff << (8 * channel + 16)); 5296 udma_mode &= ~(3 << (2 * channel)); 5297 5298 idedma_ctl = 0; 5299 5300 /* Per drive settings */ 5301 for (drive = 0; drive < 2; drive++) { 5302 drvp = &chp->ch_drive[drive]; 5303 /* If no drive, skip */ 5304 if ((drvp->drive_flags & DRIVE) == 0) 5305 continue; 5306 unit = drive + 2 * channel; 5307 /* add timing values, setup DMA if needed */ 5308 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 5309 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 5310 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 5311 (drvp->drive_flags & DRIVE_UDMA)) { 5312 /* use Ultra/DMA, check for 80-pin cable */ 5313 if (drvp->UDMA_mode > 2 && 5314 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 5315 drvp->UDMA_mode = 2; 5316 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 5317 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 5318 udma_mode |= 1 << unit; 5319 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5320 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 5321 (drvp->drive_flags & DRIVE_DMA)) { 5322 /* use Multiword DMA */ 5323 drvp->drive_flags &= ~DRIVE_UDMA; 5324 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 5325 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5326 } else { 5327 /* PIO only */ 5328 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 5329 } 5330 } 5331 5332 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 5333 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 5334 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 5335 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 5336 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 5337 5338 if (idedma_ctl != 0) { 5339 /* Add software bits in status register */ 5340 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5341 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 5342 } 5343 pciide_print_modes(cp); 5344 } 5345 5346 int 5347 serverworks_pci_intr(arg) 5348 void *arg; 5349 { 5350 struct pciide_softc *sc = arg; 5351 struct pciide_channel *cp; 5352 struct channel_softc *wdc_cp; 5353 int rv = 0; 5354 int dmastat, i, crv; 5355 5356 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5357 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5358 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 5359 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 5360 IDEDMA_CTL_INTR) 5361 continue; 5362 cp = &sc->pciide_channels[i]; 5363 wdc_cp = &cp->wdc_channel; 5364 crv = wdcintr(wdc_cp); 5365 if (crv == 0) { 5366 printf("%s:%d: bogus intr\n", 5367 sc->sc_wdcdev.sc_dev.dv_xname, i); 5368 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5369 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 5370 } else 5371 rv = 1; 5372 } 5373 return rv; 5374 } 5375 5376 void 5377 artisea_chip_map(sc, pa) 5378 struct pciide_softc *sc; 5379 struct pci_attach_args *pa; 5380 { 5381 struct pciide_channel *cp; 5382 bus_size_t cmdsize, ctlsize; 5383 pcireg_t interface; 5384 int channel; 5385 5386 if (pciide_chipen(sc, pa) == 0) 5387 return; 5388 5389 printf("%s: bus-master DMA support resent", 5390 sc->sc_wdcdev.sc_dev.dv_xname); 5391 #ifndef PCIIDE_I31244_ENABLEDMA 5392 if (PCI_REVISION(pa->pa_class) == 0) { 5393 printf(" but disabled due to rev. 0"); 5394 sc->sc_dma_ok = 0; 5395 } else 5396 #endif 5397 pciide_mapreg_dma(sc, pa); 5398 printf("\n"); 5399 5400 /* 5401 * XXX Configure LEDs to show activity. 5402 */ 5403 5404 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5405 WDC_CAPABILITY_MODE; 5406 sc->sc_wdcdev.PIO_cap = 4; 5407 if (sc->sc_dma_ok) { 5408 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5409 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5410 sc->sc_wdcdev.irqack = pciide_irqack; 5411 sc->sc_wdcdev.DMA_cap = 2; 5412 sc->sc_wdcdev.UDMA_cap = 6; 5413 } 5414 sc->sc_wdcdev.set_modes = sata_setup_channel; 5415 5416 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5417 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5418 5419 interface = PCI_INTERFACE(pa->pa_class); 5420 5421 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5422 cp = &sc->pciide_channels[channel]; 5423 if (pciide_chansetup(sc, channel, interface) == 0) 5424 continue; 5425 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5426 pciide_pci_intr); 5427 if (cp->hw_ok == 0) 5428 continue; 5429 pciide_map_compat_intr(pa, cp, channel, interface); 5430 sata_setup_channel(&cp->wdc_channel); 5431 } 5432 } 5433
Indexes created Thu Oct 02 10:09:58 GMT 2025