pciide.c revision 1.190
1 /* $NetBSD: pciide.c,v 1.190 2003/04/19 23:37:26 christos Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.190 2003/04/19 23:37:26 christos Exp $"); 80 81 #ifndef WDCDEBUG 82 #define WDCDEBUG 83 #endif 84 85 #define DEBUG_DMA 0x01 86 #define DEBUG_XFERS 0x02 87 #define DEBUG_FUNCS 0x08 88 #define DEBUG_PROBE 0x10 89 #ifdef WDCDEBUG 90 int wdcdebug_pciide_mask = 0; 91 #define WDCDEBUG_PRINT(args, level) \ 92 if (wdcdebug_pciide_mask & (level)) printf args 93 #else 94 #define WDCDEBUG_PRINT(args, level) 95 #endif 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <machine/endian.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/pciide_sl82c105_reg.h> 122 #include <dev/pci/pciide_i31244_reg.h> 123 #include <dev/pci/pciide_sii3112_reg.h> 124 #include <dev/pci/cy82c693var.h> 125 126 #include "opt_pciide.h" 127 128 static const char dmaerrfmt[] = 129 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 130 131 /* inlines for reading/writing 8-bit PCI registers */ 132 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 133 int)); 134 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 135 int, u_int8_t)); 136 137 static __inline u_int8_t 138 pciide_pci_read(pc, pa, reg) 139 pci_chipset_tag_t pc; 140 pcitag_t pa; 141 int reg; 142 { 143 144 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 145 ((reg & 0x03) * 8) & 0xff); 146 } 147 148 static __inline void 149 pciide_pci_write(pc, pa, reg, val) 150 pci_chipset_tag_t pc; 151 pcitag_t pa; 152 int reg; 153 u_int8_t val; 154 { 155 pcireg_t pcival; 156 157 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 158 pcival &= ~(0xff << ((reg & 0x03) * 8)); 159 pcival |= (val << ((reg & 0x03) * 8)); 160 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 161 } 162 163 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 164 165 void sata_setup_channel __P((struct channel_softc*)); 166 167 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void piix_setup_channel __P((struct channel_softc*)); 169 void piix3_4_setup_channel __P((struct channel_softc*)); 170 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 171 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 172 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 173 174 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void amd7x6_setup_channel __P((struct channel_softc*)); 176 177 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void apollo_setup_channel __P((struct channel_softc*)); 179 180 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void cmd0643_9_setup_channel __P((struct channel_softc*)); 183 void cmd_channel_map __P((struct pci_attach_args *, 184 struct pciide_softc *, int)); 185 int cmd_pci_intr __P((void *)); 186 void cmd646_9_irqack __P((struct channel_softc *)); 187 void cmd680_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 188 void cmd680_setup_channel __P((struct channel_softc*)); 189 void cmd680_channel_map __P((struct pci_attach_args *, 190 struct pciide_softc *, int)); 191 192 void cmd3112_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void cmd3112_setup_channel __P((struct channel_softc*)); 194 195 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 196 void cy693_setup_channel __P((struct channel_softc*)); 197 198 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 199 void sis_setup_channel __P((struct channel_softc*)); 200 void sis96x_setup_channel __P((struct channel_softc*)); 201 static int sis_hostbr_match __P(( struct pci_attach_args *)); 202 static int sis_south_match __P(( struct pci_attach_args *)); 203 204 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 205 void acer_setup_channel __P((struct channel_softc*)); 206 int acer_pci_intr __P((void *)); 207 208 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 209 void pdc202xx_setup_channel __P((struct channel_softc*)); 210 void pdc20268_setup_channel __P((struct channel_softc*)); 211 int pdc202xx_pci_intr __P((void *)); 212 int pdc20265_pci_intr __P((void *)); 213 214 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 215 void opti_setup_channel __P((struct channel_softc*)); 216 217 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 218 void hpt_setup_channel __P((struct channel_softc*)); 219 int hpt_pci_intr __P((void *)); 220 221 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 222 void acard_setup_channel __P((struct channel_softc*)); 223 int acard_pci_intr __P((void *)); 224 225 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 226 void serverworks_setup_channel __P((struct channel_softc*)); 227 int serverworks_pci_intr __P((void *)); 228 229 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 230 void sl82c105_setup_channel __P((struct channel_softc*)); 231 232 void pciide_channel_dma_setup __P((struct pciide_channel *)); 233 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 234 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 235 void pciide_dma_start __P((void*, int, int)); 236 int pciide_dma_finish __P((void*, int, int, int)); 237 void pciide_irqack __P((struct channel_softc *)); 238 void pciide_print_modes __P((struct pciide_channel *)); 239 240 void artisea_chip_map __P((struct pciide_softc*, struct pci_attach_args *)); 241 242 struct pciide_product_desc { 243 u_int32_t ide_product; 244 int ide_flags; 245 const char *ide_name; 246 /* map and setup chip, probe drives */ 247 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 248 }; 249 250 /* Flags for ide_flags */ 251 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 252 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 253 254 /* Default product description for devices not known from this controller */ 255 const struct pciide_product_desc default_product_desc = { 256 0, 257 0, 258 "Generic PCI IDE controller", 259 default_chip_map, 260 }; 261 262 const struct pciide_product_desc pciide_intel_products[] = { 263 { PCI_PRODUCT_INTEL_82092AA, 264 0, 265 "Intel 82092AA IDE controller", 266 default_chip_map, 267 }, 268 { PCI_PRODUCT_INTEL_82371FB_IDE, 269 0, 270 "Intel 82371FB IDE controller (PIIX)", 271 piix_chip_map, 272 }, 273 { PCI_PRODUCT_INTEL_82371SB_IDE, 274 0, 275 "Intel 82371SB IDE Interface (PIIX3)", 276 piix_chip_map, 277 }, 278 { PCI_PRODUCT_INTEL_82371AB_IDE, 279 0, 280 "Intel 82371AB IDE controller (PIIX4)", 281 piix_chip_map, 282 }, 283 { PCI_PRODUCT_INTEL_82440MX_IDE, 284 0, 285 "Intel 82440MX IDE controller", 286 piix_chip_map 287 }, 288 { PCI_PRODUCT_INTEL_82801AA_IDE, 289 0, 290 "Intel 82801AA IDE Controller (ICH)", 291 piix_chip_map, 292 }, 293 { PCI_PRODUCT_INTEL_82801AB_IDE, 294 0, 295 "Intel 82801AB IDE Controller (ICH0)", 296 piix_chip_map, 297 }, 298 { PCI_PRODUCT_INTEL_82801BA_IDE, 299 0, 300 "Intel 82801BA IDE Controller (ICH2)", 301 piix_chip_map, 302 }, 303 { PCI_PRODUCT_INTEL_82801BAM_IDE, 304 0, 305 "Intel 82801BAM IDE Controller (ICH2-M)", 306 piix_chip_map, 307 }, 308 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 309 0, 310 "Intel 82801CA IDE Controller (ICH3)", 311 piix_chip_map, 312 }, 313 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 314 0, 315 "Intel 82801CA IDE Controller (ICH3)", 316 piix_chip_map, 317 }, 318 { PCI_PRODUCT_INTEL_82801DB_IDE, 319 0, 320 "Intel 82801DB IDE Controller (ICH4)", 321 piix_chip_map, 322 }, 323 { PCI_PRODUCT_INTEL_82801DBM_IDE, 324 0, 325 "Intel 82801DBM IDE Controller (ICH4-M)", 326 piix_chip_map, 327 }, 328 { PCI_PRODUCT_INTEL_31244, 329 0, 330 "Intel 31244 Serial ATA Controller", 331 artisea_chip_map, 332 }, 333 { 0, 334 0, 335 NULL, 336 NULL 337 } 338 }; 339 340 const struct pciide_product_desc pciide_amd_products[] = { 341 { PCI_PRODUCT_AMD_PBC756_IDE, 342 0, 343 "Advanced Micro Devices AMD756 IDE Controller", 344 amd7x6_chip_map 345 }, 346 { PCI_PRODUCT_AMD_PBC766_IDE, 347 0, 348 "Advanced Micro Devices AMD766 IDE Controller", 349 amd7x6_chip_map 350 }, 351 { PCI_PRODUCT_AMD_PBC768_IDE, 352 0, 353 "Advanced Micro Devices AMD768 IDE Controller", 354 amd7x6_chip_map 355 }, 356 { PCI_PRODUCT_AMD_PBC8111_IDE, 357 0, 358 "Advanced Micro Devices AMD8111 IDE Controller", 359 amd7x6_chip_map 360 }, 361 { 0, 362 0, 363 NULL, 364 NULL 365 } 366 }; 367 368 const struct pciide_product_desc pciide_nvidia_products[] = { 369 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 370 0, 371 "NVIDIA nForce IDE Controller", 372 amd7x6_chip_map 373 }, 374 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 375 0, 376 "NVIDIA nForce2 IDE Controller", 377 amd7x6_chip_map 378 }, 379 { 0, 380 0, 381 NULL, 382 NULL 383 } 384 }; 385 386 const struct pciide_product_desc pciide_cmd_products[] = { 387 { PCI_PRODUCT_CMDTECH_640, 388 0, 389 "CMD Technology PCI0640", 390 cmd_chip_map 391 }, 392 { PCI_PRODUCT_CMDTECH_643, 393 0, 394 "CMD Technology PCI0643", 395 cmd0643_9_chip_map, 396 }, 397 { PCI_PRODUCT_CMDTECH_646, 398 0, 399 "CMD Technology PCI0646", 400 cmd0643_9_chip_map, 401 }, 402 { PCI_PRODUCT_CMDTECH_648, 403 IDE_PCI_CLASS_OVERRIDE, 404 "CMD Technology PCI0648", 405 cmd0643_9_chip_map, 406 }, 407 { PCI_PRODUCT_CMDTECH_649, 408 IDE_PCI_CLASS_OVERRIDE, 409 "CMD Technology PCI0649", 410 cmd0643_9_chip_map, 411 }, 412 { PCI_PRODUCT_CMDTECH_680, 413 IDE_PCI_CLASS_OVERRIDE, 414 "Silicon Image 0680", 415 cmd680_chip_map, 416 }, 417 { PCI_PRODUCT_CMDTECH_3112, 418 IDE_PCI_CLASS_OVERRIDE, 419 "Silicon Image SATALink 3112", 420 cmd3112_chip_map, 421 }, 422 { 0, 423 0, 424 NULL, 425 NULL 426 } 427 }; 428 429 const struct pciide_product_desc pciide_via_products[] = { 430 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 431 0, 432 NULL, 433 apollo_chip_map, 434 }, 435 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 436 0, 437 NULL, 438 apollo_chip_map, 439 }, 440 { 0, 441 0, 442 NULL, 443 NULL 444 } 445 }; 446 447 const struct pciide_product_desc pciide_cypress_products[] = { 448 { PCI_PRODUCT_CONTAQ_82C693, 449 IDE_16BIT_IOSPACE, 450 "Cypress 82C693 IDE Controller", 451 cy693_chip_map, 452 }, 453 { 0, 454 0, 455 NULL, 456 NULL 457 } 458 }; 459 460 const struct pciide_product_desc pciide_sis_products[] = { 461 { PCI_PRODUCT_SIS_5597_IDE, 462 0, 463 NULL, 464 sis_chip_map, 465 }, 466 { 0, 467 0, 468 NULL, 469 NULL 470 } 471 }; 472 473 const struct pciide_product_desc pciide_acer_products[] = { 474 { PCI_PRODUCT_ALI_M5229, 475 0, 476 "Acer Labs M5229 UDMA IDE Controller", 477 acer_chip_map, 478 }, 479 { 0, 480 0, 481 NULL, 482 NULL 483 } 484 }; 485 486 const struct pciide_product_desc pciide_promise_products[] = { 487 { PCI_PRODUCT_PROMISE_ULTRA33, 488 IDE_PCI_CLASS_OVERRIDE, 489 "Promise Ultra33/ATA Bus Master IDE Accelerator", 490 pdc202xx_chip_map, 491 }, 492 { PCI_PRODUCT_PROMISE_ULTRA66, 493 IDE_PCI_CLASS_OVERRIDE, 494 "Promise Ultra66/ATA Bus Master IDE Accelerator", 495 pdc202xx_chip_map, 496 }, 497 { PCI_PRODUCT_PROMISE_ULTRA100, 498 IDE_PCI_CLASS_OVERRIDE, 499 "Promise Ultra100/ATA Bus Master IDE Accelerator", 500 pdc202xx_chip_map, 501 }, 502 { PCI_PRODUCT_PROMISE_ULTRA100X, 503 IDE_PCI_CLASS_OVERRIDE, 504 "Promise Ultra100/ATA Bus Master IDE Accelerator", 505 pdc202xx_chip_map, 506 }, 507 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 508 IDE_PCI_CLASS_OVERRIDE, 509 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 510 pdc202xx_chip_map, 511 }, 512 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 513 IDE_PCI_CLASS_OVERRIDE, 514 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 515 pdc202xx_chip_map, 516 }, 517 { PCI_PRODUCT_PROMISE_ULTRA133, 518 IDE_PCI_CLASS_OVERRIDE, 519 "Promise Ultra133/ATA Bus Master IDE Accelerator", 520 pdc202xx_chip_map, 521 }, 522 { PCI_PRODUCT_PROMISE_ULTRA133TX2, 523 IDE_PCI_CLASS_OVERRIDE, 524 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 525 pdc202xx_chip_map, 526 }, 527 { PCI_PRODUCT_PROMISE_MBULTRA133, 528 IDE_PCI_CLASS_OVERRIDE, 529 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 530 pdc202xx_chip_map, 531 }, 532 { PCI_PRODUCT_PROMISE_ULTRA133TX2v2, 533 IDE_PCI_CLASS_OVERRIDE, 534 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 535 pdc202xx_chip_map, 536 }, 537 { PCI_PRODUCT_PROMISE_FASTTRAK133LITE, 538 IDE_PCI_CLASS_OVERRIDE, 539 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 540 pdc202xx_chip_map, 541 }, 542 { PCI_PRODUCT_PROMISE_SATA150TX2PLUS, 543 IDE_PCI_CLASS_OVERRIDE, 544 "Promise Serial ATA/150 TX2plus Bus Master IDE Accelerator", 545 pdc202xx_chip_map, 546 }, 547 { 0, 548 0, 549 NULL, 550 NULL 551 } 552 }; 553 554 const struct pciide_product_desc pciide_opti_products[] = { 555 { PCI_PRODUCT_OPTI_82C621, 556 0, 557 "OPTi 82c621 PCI IDE controller", 558 opti_chip_map, 559 }, 560 { PCI_PRODUCT_OPTI_82C568, 561 0, 562 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 563 opti_chip_map, 564 }, 565 { PCI_PRODUCT_OPTI_82D568, 566 0, 567 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 568 opti_chip_map, 569 }, 570 { 0, 571 0, 572 NULL, 573 NULL 574 } 575 }; 576 577 const struct pciide_product_desc pciide_triones_products[] = { 578 { PCI_PRODUCT_TRIONES_HPT366, 579 IDE_PCI_CLASS_OVERRIDE, 580 NULL, 581 hpt_chip_map, 582 }, 583 { PCI_PRODUCT_TRIONES_HPT372, 584 IDE_PCI_CLASS_OVERRIDE, 585 NULL, 586 hpt_chip_map 587 }, 588 { PCI_PRODUCT_TRIONES_HPT374, 589 IDE_PCI_CLASS_OVERRIDE, 590 NULL, 591 hpt_chip_map 592 }, 593 { 0, 594 0, 595 NULL, 596 NULL 597 } 598 }; 599 600 const struct pciide_product_desc pciide_acard_products[] = { 601 { PCI_PRODUCT_ACARD_ATP850U, 602 IDE_PCI_CLASS_OVERRIDE, 603 "Acard ATP850U Ultra33 IDE Controller", 604 acard_chip_map, 605 }, 606 { PCI_PRODUCT_ACARD_ATP860, 607 IDE_PCI_CLASS_OVERRIDE, 608 "Acard ATP860 Ultra66 IDE Controller", 609 acard_chip_map, 610 }, 611 { PCI_PRODUCT_ACARD_ATP860A, 612 IDE_PCI_CLASS_OVERRIDE, 613 "Acard ATP860-A Ultra66 IDE Controller", 614 acard_chip_map, 615 }, 616 { 0, 617 0, 618 NULL, 619 NULL 620 } 621 }; 622 623 const struct pciide_product_desc pciide_serverworks_products[] = { 624 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 625 0, 626 "ServerWorks OSB4 IDE Controller", 627 serverworks_chip_map, 628 }, 629 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 630 0, 631 "ServerWorks CSB5 IDE Controller", 632 serverworks_chip_map, 633 }, 634 { PCI_PRODUCT_SERVERWORKS_CSB6_IDE, 635 0, 636 "ServerWorks CSB6 RAID/IDE Controller", 637 serverworks_chip_map, 638 }, 639 { 0, 640 0, 641 NULL, 642 } 643 }; 644 645 const struct pciide_product_desc pciide_symphony_products[] = { 646 { PCI_PRODUCT_SYMPHONY_82C105, 647 0, 648 "Symphony Labs 82C105 IDE controller", 649 sl82c105_chip_map, 650 }, 651 { 0, 652 0, 653 NULL, 654 } 655 }; 656 657 const struct pciide_product_desc pciide_winbond_products[] = { 658 { PCI_PRODUCT_WINBOND_W83C553F_1, 659 0, 660 "Winbond W83C553F IDE controller", 661 sl82c105_chip_map, 662 }, 663 { 0, 664 0, 665 NULL, 666 } 667 }; 668 669 struct pciide_vendor_desc { 670 u_int32_t ide_vendor; 671 const struct pciide_product_desc *ide_products; 672 }; 673 674 const struct pciide_vendor_desc pciide_vendors[] = { 675 { PCI_VENDOR_INTEL, pciide_intel_products }, 676 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 677 { PCI_VENDOR_VIATECH, pciide_via_products }, 678 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 679 { PCI_VENDOR_SIS, pciide_sis_products }, 680 { PCI_VENDOR_ALI, pciide_acer_products }, 681 { PCI_VENDOR_PROMISE, pciide_promise_products }, 682 { PCI_VENDOR_AMD, pciide_amd_products }, 683 { PCI_VENDOR_OPTI, pciide_opti_products }, 684 { PCI_VENDOR_TRIONES, pciide_triones_products }, 685 { PCI_VENDOR_ACARD, pciide_acard_products }, 686 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 687 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 688 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 689 { PCI_VENDOR_NVIDIA, pciide_nvidia_products }, 690 { 0, NULL } 691 }; 692 693 /* options passed via the 'flags' config keyword */ 694 #define PCIIDE_OPTIONS_DMA 0x01 695 #define PCIIDE_OPTIONS_NODMA 0x02 696 697 int pciide_match __P((struct device *, struct cfdata *, void *)); 698 void pciide_attach __P((struct device *, struct device *, void *)); 699 700 CFATTACH_DECL(pciide, sizeof(struct pciide_softc), 701 pciide_match, pciide_attach, NULL, NULL); 702 703 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 704 int pciide_mapregs_compat __P(( struct pci_attach_args *, 705 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 706 int pciide_mapregs_native __P((struct pci_attach_args *, 707 struct pciide_channel *, bus_size_t *, bus_size_t *, 708 int (*pci_intr) __P((void *)))); 709 void pciide_mapreg_dma __P((struct pciide_softc *, 710 struct pci_attach_args *)); 711 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 712 void pciide_mapchan __P((struct pci_attach_args *, 713 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 714 int (*pci_intr) __P((void *)))); 715 int pciide_chan_candisable __P((struct pciide_channel *)); 716 void pciide_map_compat_intr __P(( struct pci_attach_args *, 717 struct pciide_channel *, int, int)); 718 int pciide_compat_intr __P((void *)); 719 int pciide_pci_intr __P((void *)); 720 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 721 722 const struct pciide_product_desc * 723 pciide_lookup_product(id) 724 u_int32_t id; 725 { 726 const struct pciide_product_desc *pp; 727 const struct pciide_vendor_desc *vp; 728 729 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 730 if (PCI_VENDOR(id) == vp->ide_vendor) 731 break; 732 733 if ((pp = vp->ide_products) == NULL) 734 return NULL; 735 736 for (; pp->chip_map != NULL; pp++) 737 if (PCI_PRODUCT(id) == pp->ide_product) 738 break; 739 740 if (pp->chip_map == NULL) 741 return NULL; 742 return pp; 743 } 744 745 int 746 pciide_match(parent, match, aux) 747 struct device *parent; 748 struct cfdata *match; 749 void *aux; 750 { 751 struct pci_attach_args *pa = aux; 752 const struct pciide_product_desc *pp; 753 754 /* 755 * Check the ID register to see that it's a PCI IDE controller. 756 * If it is, we assume that we can deal with it; it _should_ 757 * work in a standardized way... 758 */ 759 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 760 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 761 return (1); 762 } 763 764 /* 765 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 766 * controllers. Let see if we can deal with it anyway. 767 */ 768 pp = pciide_lookup_product(pa->pa_id); 769 if (pp != NULL && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 770 return (1); 771 } 772 773 return (0); 774 } 775 776 void 777 pciide_attach(parent, self, aux) 778 struct device *parent, *self; 779 void *aux; 780 { 781 struct pci_attach_args *pa = aux; 782 pci_chipset_tag_t pc = pa->pa_pc; 783 pcitag_t tag = pa->pa_tag; 784 struct pciide_softc *sc = (struct pciide_softc *)self; 785 pcireg_t csr; 786 char devinfo[256]; 787 const char *displaydev; 788 789 sc->sc_pci_vendor = PCI_VENDOR(pa->pa_id); 790 sc->sc_pp = pciide_lookup_product(pa->pa_id); 791 if (sc->sc_pp == NULL) { 792 sc->sc_pp = &default_product_desc; 793 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 794 displaydev = devinfo; 795 } else 796 displaydev = sc->sc_pp->ide_name; 797 798 /* if displaydev == NULL, printf is done in chip-specific map */ 799 if (displaydev) 800 printf(": %s (rev. 0x%02x)\n", displaydev, 801 PCI_REVISION(pa->pa_class)); 802 803 sc->sc_pc = pa->pa_pc; 804 sc->sc_tag = pa->pa_tag; 805 806 /* Set up DMA defaults; these might be adjusted by chip_map. */ 807 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 808 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 809 810 #ifdef WDCDEBUG 811 if (wdcdebug_pciide_mask & DEBUG_PROBE) 812 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 813 #endif 814 sc->sc_pp->chip_map(sc, pa); 815 816 if (sc->sc_dma_ok) { 817 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 818 csr |= PCI_COMMAND_MASTER_ENABLE; 819 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 820 } 821 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 822 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 823 } 824 825 /* tell whether the chip is enabled or not */ 826 int 827 pciide_chipen(sc, pa) 828 struct pciide_softc *sc; 829 struct pci_attach_args *pa; 830 { 831 pcireg_t csr; 832 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 833 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 834 PCI_COMMAND_STATUS_REG); 835 printf("%s: device disabled (at %s)\n", 836 sc->sc_wdcdev.sc_dev.dv_xname, 837 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 838 "device" : "bridge"); 839 return 0; 840 } 841 return 1; 842 } 843 844 int 845 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 846 struct pci_attach_args *pa; 847 struct pciide_channel *cp; 848 int compatchan; 849 bus_size_t *cmdsizep, *ctlsizep; 850 { 851 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 852 struct channel_softc *wdc_cp = &cp->wdc_channel; 853 854 cp->compat = 1; 855 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 856 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 857 858 wdc_cp->cmd_iot = pa->pa_iot; 859 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 860 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 861 printf("%s: couldn't map %s channel cmd regs\n", 862 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 863 return (0); 864 } 865 866 wdc_cp->ctl_iot = pa->pa_iot; 867 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 868 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 869 printf("%s: couldn't map %s channel ctl regs\n", 870 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 871 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 872 PCIIDE_COMPAT_CMD_SIZE); 873 return (0); 874 } 875 876 return (1); 877 } 878 879 int 880 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 881 struct pci_attach_args * pa; 882 struct pciide_channel *cp; 883 bus_size_t *cmdsizep, *ctlsizep; 884 int (*pci_intr) __P((void *)); 885 { 886 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 887 struct channel_softc *wdc_cp = &cp->wdc_channel; 888 const char *intrstr; 889 pci_intr_handle_t intrhandle; 890 891 cp->compat = 0; 892 893 if (sc->sc_pci_ih == NULL) { 894 if (pci_intr_map(pa, &intrhandle) != 0) { 895 printf("%s: couldn't map native-PCI interrupt\n", 896 sc->sc_wdcdev.sc_dev.dv_xname); 897 return 0; 898 } 899 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 900 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 901 intrhandle, IPL_BIO, pci_intr, sc); 902 if (sc->sc_pci_ih != NULL) { 903 printf("%s: using %s for native-PCI interrupt\n", 904 sc->sc_wdcdev.sc_dev.dv_xname, 905 intrstr ? intrstr : "unknown interrupt"); 906 } else { 907 printf("%s: couldn't establish native-PCI interrupt", 908 sc->sc_wdcdev.sc_dev.dv_xname); 909 if (intrstr != NULL) 910 printf(" at %s", intrstr); 911 printf("\n"); 912 return 0; 913 } 914 } 915 cp->ih = sc->sc_pci_ih; 916 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 917 PCI_MAPREG_TYPE_IO, 0, 918 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 919 printf("%s: couldn't map %s channel cmd regs\n", 920 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 921 return 0; 922 } 923 924 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 925 PCI_MAPREG_TYPE_IO, 0, 926 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 927 printf("%s: couldn't map %s channel ctl regs\n", 928 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 929 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 930 return 0; 931 } 932 /* 933 * In native mode, 4 bytes of I/O space are mapped for the control 934 * register, the control register is at offset 2. Pass the generic 935 * code a handle for only one byte at the right offset. 936 */ 937 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 938 &wdc_cp->ctl_ioh) != 0) { 939 printf("%s: unable to subregion %s channel ctl regs\n", 940 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 941 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 942 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 943 return 0; 944 } 945 return (1); 946 } 947 948 void 949 pciide_mapreg_dma(sc, pa) 950 struct pciide_softc *sc; 951 struct pci_attach_args *pa; 952 { 953 pcireg_t maptype; 954 bus_addr_t addr; 955 956 /* 957 * Map DMA registers 958 * 959 * Note that sc_dma_ok is the right variable to test to see if 960 * DMA can be done. If the interface doesn't support DMA, 961 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 962 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 963 * non-zero if the interface supports DMA and the registers 964 * could be mapped. 965 * 966 * XXX Note that despite the fact that the Bus Master IDE specs 967 * XXX say that "The bus master IDE function uses 16 bytes of IO 968 * XXX space," some controllers (at least the United 969 * XXX Microelectronics UM8886BF) place it in memory space. 970 */ 971 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 972 PCIIDE_REG_BUS_MASTER_DMA); 973 974 switch (maptype) { 975 case PCI_MAPREG_TYPE_IO: 976 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 977 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 978 &addr, NULL, NULL) == 0); 979 if (sc->sc_dma_ok == 0) { 980 printf(", but unused (couldn't query registers)"); 981 break; 982 } 983 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 984 && addr >= 0x10000) { 985 sc->sc_dma_ok = 0; 986 printf(", but unused (registers at unsafe address " 987 "%#lx)", (unsigned long)addr); 988 break; 989 } 990 /* FALLTHROUGH */ 991 992 case PCI_MAPREG_MEM_TYPE_32BIT: 993 sc->sc_dma_ok = (pci_mapreg_map(pa, 994 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 995 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 996 sc->sc_dmat = pa->pa_dmat; 997 if (sc->sc_dma_ok == 0) { 998 printf(", but unused (couldn't map registers)"); 999 } else { 1000 sc->sc_wdcdev.dma_arg = sc; 1001 sc->sc_wdcdev.dma_init = pciide_dma_init; 1002 sc->sc_wdcdev.dma_start = pciide_dma_start; 1003 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 1004 } 1005 1006 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1007 PCIIDE_OPTIONS_NODMA) { 1008 printf(", but unused (forced off by config file)"); 1009 sc->sc_dma_ok = 0; 1010 } 1011 break; 1012 1013 default: 1014 sc->sc_dma_ok = 0; 1015 printf(", but unsupported register maptype (0x%x)", maptype); 1016 } 1017 } 1018 1019 int 1020 pciide_compat_intr(arg) 1021 void *arg; 1022 { 1023 struct pciide_channel *cp = arg; 1024 1025 #ifdef DIAGNOSTIC 1026 /* should only be called for a compat channel */ 1027 if (cp->compat == 0) 1028 panic("pciide compat intr called for non-compat chan %p", cp); 1029 #endif 1030 return (wdcintr(&cp->wdc_channel)); 1031 } 1032 1033 int 1034 pciide_pci_intr(arg) 1035 void *arg; 1036 { 1037 struct pciide_softc *sc = arg; 1038 struct pciide_channel *cp; 1039 struct channel_softc *wdc_cp; 1040 int i, rv, crv; 1041 1042 rv = 0; 1043 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1044 cp = &sc->pciide_channels[i]; 1045 wdc_cp = &cp->wdc_channel; 1046 1047 /* If a compat channel skip. */ 1048 if (cp->compat) 1049 continue; 1050 /* if this channel not waiting for intr, skip */ 1051 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 1052 continue; 1053 1054 crv = wdcintr(wdc_cp); 1055 if (crv == 0) 1056 ; /* leave rv alone */ 1057 else if (crv == 1) 1058 rv = 1; /* claim the intr */ 1059 else if (rv == 0) /* crv should be -1 in this case */ 1060 rv = crv; /* if we've done no better, take it */ 1061 } 1062 return (rv); 1063 } 1064 1065 void 1066 pciide_channel_dma_setup(cp) 1067 struct pciide_channel *cp; 1068 { 1069 int drive; 1070 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1071 struct ata_drive_datas *drvp; 1072 1073 for (drive = 0; drive < 2; drive++) { 1074 drvp = &cp->wdc_channel.ch_drive[drive]; 1075 /* If no drive, skip */ 1076 if ((drvp->drive_flags & DRIVE) == 0) 1077 continue; 1078 /* setup DMA if needed */ 1079 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1080 (drvp->drive_flags & DRIVE_UDMA) == 0) || 1081 sc->sc_dma_ok == 0) { 1082 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1083 continue; 1084 } 1085 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 1086 != 0) { 1087 /* Abort DMA setup */ 1088 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1089 continue; 1090 } 1091 } 1092 } 1093 1094 int 1095 pciide_dma_table_setup(sc, channel, drive) 1096 struct pciide_softc *sc; 1097 int channel, drive; 1098 { 1099 bus_dma_segment_t seg; 1100 int error, rseg; 1101 const bus_size_t dma_table_size = 1102 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1103 struct pciide_dma_maps *dma_maps = 1104 &sc->pciide_channels[channel].dma_maps[drive]; 1105 1106 /* If table was already allocated, just return */ 1107 if (dma_maps->dma_table) 1108 return 0; 1109 1110 /* Allocate memory for the DMA tables and map it */ 1111 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1112 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1113 BUS_DMA_NOWAIT)) != 0) { 1114 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1115 "allocate", drive, error); 1116 return error; 1117 } 1118 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1119 dma_table_size, 1120 (caddr_t *)&dma_maps->dma_table, 1121 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1122 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1123 "map", drive, error); 1124 return error; 1125 } 1126 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1127 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1128 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1129 /* Create and load table DMA map for this disk */ 1130 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1131 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1132 &dma_maps->dmamap_table)) != 0) { 1133 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1134 "create", drive, error); 1135 return error; 1136 } 1137 if ((error = bus_dmamap_load(sc->sc_dmat, 1138 dma_maps->dmamap_table, 1139 dma_maps->dma_table, 1140 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1141 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1142 "load", drive, error); 1143 return error; 1144 } 1145 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1146 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1147 DEBUG_PROBE); 1148 /* Create a xfer DMA map for this drive */ 1149 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1150 NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 1151 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1152 &dma_maps->dmamap_xfer)) != 0) { 1153 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1154 "create xfer", drive, error); 1155 return error; 1156 } 1157 return 0; 1158 } 1159 1160 int 1161 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1162 void *v; 1163 int channel, drive; 1164 void *databuf; 1165 size_t datalen; 1166 int flags; 1167 { 1168 struct pciide_softc *sc = v; 1169 int error, seg; 1170 struct pciide_dma_maps *dma_maps = 1171 &sc->pciide_channels[channel].dma_maps[drive]; 1172 1173 error = bus_dmamap_load(sc->sc_dmat, 1174 dma_maps->dmamap_xfer, 1175 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1176 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1177 if (error) { 1178 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1179 "load xfer", drive, error); 1180 return error; 1181 } 1182 1183 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1184 dma_maps->dmamap_xfer->dm_mapsize, 1185 (flags & WDC_DMA_READ) ? 1186 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1187 1188 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1189 #ifdef DIAGNOSTIC 1190 /* A segment must not cross a 64k boundary */ 1191 { 1192 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1193 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1194 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1195 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1196 printf("pciide_dma: segment %d physical addr 0x%lx" 1197 " len 0x%lx not properly aligned\n", 1198 seg, phys, len); 1199 panic("pciide_dma: buf align"); 1200 } 1201 } 1202 #endif 1203 dma_maps->dma_table[seg].base_addr = 1204 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1205 dma_maps->dma_table[seg].byte_count = 1206 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1207 IDEDMA_BYTE_COUNT_MASK); 1208 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1209 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1210 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1211 1212 } 1213 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1214 htole32(IDEDMA_BYTE_COUNT_EOT); 1215 1216 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1217 dma_maps->dmamap_table->dm_mapsize, 1218 BUS_DMASYNC_PREWRITE); 1219 1220 /* Maps are ready. Start DMA function */ 1221 #ifdef DIAGNOSTIC 1222 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1223 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1224 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1225 panic("pciide_dma_init: table align"); 1226 } 1227 #endif 1228 1229 /* Clear status bits */ 1230 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1231 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1232 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1233 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1234 /* Write table addr */ 1235 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1236 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1237 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1238 /* set read/write */ 1239 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1240 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1241 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1242 /* remember flags */ 1243 dma_maps->dma_flags = flags; 1244 return 0; 1245 } 1246 1247 void 1248 pciide_dma_start(v, channel, drive) 1249 void *v; 1250 int channel, drive; 1251 { 1252 struct pciide_softc *sc = v; 1253 1254 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1255 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1256 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1257 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1258 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1259 } 1260 1261 int 1262 pciide_dma_finish(v, channel, drive, force) 1263 void *v; 1264 int channel, drive; 1265 int force; 1266 { 1267 struct pciide_softc *sc = v; 1268 u_int8_t status; 1269 int error = 0; 1270 struct pciide_dma_maps *dma_maps = 1271 &sc->pciide_channels[channel].dma_maps[drive]; 1272 1273 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1274 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1275 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1276 DEBUG_XFERS); 1277 1278 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1279 return WDC_DMAST_NOIRQ; 1280 1281 /* stop DMA channel */ 1282 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1283 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1284 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1285 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1286 1287 /* Unload the map of the data buffer */ 1288 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1289 dma_maps->dmamap_xfer->dm_mapsize, 1290 (dma_maps->dma_flags & WDC_DMA_READ) ? 1291 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1292 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1293 1294 if ((status & IDEDMA_CTL_ERR) != 0) { 1295 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1296 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1297 error |= WDC_DMAST_ERR; 1298 } 1299 1300 if ((status & IDEDMA_CTL_INTR) == 0) { 1301 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1302 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1303 drive, status); 1304 error |= WDC_DMAST_NOIRQ; 1305 } 1306 1307 if ((status & IDEDMA_CTL_ACT) != 0) { 1308 /* data underrun, may be a valid condition for ATAPI */ 1309 error |= WDC_DMAST_UNDER; 1310 } 1311 return error; 1312 } 1313 1314 void 1315 pciide_irqack(chp) 1316 struct channel_softc *chp; 1317 { 1318 struct pciide_channel *cp = (struct pciide_channel*)chp; 1319 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1320 1321 /* clear status bits in IDE DMA registers */ 1322 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1323 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1324 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1325 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1326 } 1327 1328 /* some common code used by several chip_map */ 1329 int 1330 pciide_chansetup(sc, channel, interface) 1331 struct pciide_softc *sc; 1332 int channel; 1333 pcireg_t interface; 1334 { 1335 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1336 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1337 cp->name = PCIIDE_CHANNEL_NAME(channel); 1338 cp->wdc_channel.channel = channel; 1339 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1340 cp->wdc_channel.ch_queue = 1341 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1342 if (cp->wdc_channel.ch_queue == NULL) { 1343 printf("%s %s channel: " 1344 "can't allocate memory for command queue", 1345 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1346 return 0; 1347 } 1348 printf("%s: %s channel %s to %s mode\n", 1349 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1350 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1351 "configured" : "wired", 1352 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1353 "native-PCI" : "compatibility"); 1354 return 1; 1355 } 1356 1357 /* some common code used by several chip channel_map */ 1358 void 1359 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1360 struct pci_attach_args *pa; 1361 struct pciide_channel *cp; 1362 pcireg_t interface; 1363 bus_size_t *cmdsizep, *ctlsizep; 1364 int (*pci_intr) __P((void *)); 1365 { 1366 struct channel_softc *wdc_cp = &cp->wdc_channel; 1367 1368 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1369 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1370 pci_intr); 1371 else 1372 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1373 wdc_cp->channel, cmdsizep, ctlsizep); 1374 1375 if (cp->hw_ok == 0) 1376 return; 1377 wdc_cp->data32iot = wdc_cp->cmd_iot; 1378 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1379 wdcattach(wdc_cp); 1380 } 1381 1382 /* 1383 * Generic code to call to know if a channel can be disabled. Return 1 1384 * if channel can be disabled, 0 if not 1385 */ 1386 int 1387 pciide_chan_candisable(cp) 1388 struct pciide_channel *cp; 1389 { 1390 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1391 struct channel_softc *wdc_cp = &cp->wdc_channel; 1392 1393 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1394 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1395 printf("%s: disabling %s channel (no drives)\n", 1396 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1397 cp->hw_ok = 0; 1398 return 1; 1399 } 1400 return 0; 1401 } 1402 1403 /* 1404 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1405 * Set hw_ok=0 on failure 1406 */ 1407 void 1408 pciide_map_compat_intr(pa, cp, compatchan, interface) 1409 struct pci_attach_args *pa; 1410 struct pciide_channel *cp; 1411 int compatchan, interface; 1412 { 1413 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1414 struct channel_softc *wdc_cp = &cp->wdc_channel; 1415 1416 if (cp->hw_ok == 0) 1417 return; 1418 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1419 return; 1420 1421 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1422 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1423 pa, compatchan, pciide_compat_intr, cp); 1424 if (cp->ih == NULL) { 1425 #endif 1426 printf("%s: no compatibility interrupt for use by %s " 1427 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1428 cp->hw_ok = 0; 1429 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1430 } 1431 #endif 1432 } 1433 1434 void 1435 pciide_print_modes(cp) 1436 struct pciide_channel *cp; 1437 { 1438 wdc_print_modes(&cp->wdc_channel); 1439 } 1440 1441 void 1442 default_chip_map(sc, pa) 1443 struct pciide_softc *sc; 1444 struct pci_attach_args *pa; 1445 { 1446 struct pciide_channel *cp; 1447 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1448 pcireg_t csr; 1449 int channel, drive; 1450 struct ata_drive_datas *drvp; 1451 u_int8_t idedma_ctl; 1452 bus_size_t cmdsize, ctlsize; 1453 char *failreason; 1454 1455 if (pciide_chipen(sc, pa) == 0) 1456 return; 1457 1458 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1459 printf("%s: bus-master DMA support present", 1460 sc->sc_wdcdev.sc_dev.dv_xname); 1461 if (sc->sc_pp == &default_product_desc && 1462 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1463 PCIIDE_OPTIONS_DMA) == 0) { 1464 printf(", but unused (no driver support)"); 1465 sc->sc_dma_ok = 0; 1466 } else { 1467 pciide_mapreg_dma(sc, pa); 1468 if (sc->sc_dma_ok != 0) 1469 printf(", used without full driver " 1470 "support"); 1471 } 1472 } else { 1473 printf("%s: hardware does not support DMA", 1474 sc->sc_wdcdev.sc_dev.dv_xname); 1475 sc->sc_dma_ok = 0; 1476 } 1477 printf("\n"); 1478 if (sc->sc_dma_ok) { 1479 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1480 sc->sc_wdcdev.irqack = pciide_irqack; 1481 } 1482 sc->sc_wdcdev.PIO_cap = 0; 1483 sc->sc_wdcdev.DMA_cap = 0; 1484 1485 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1486 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1487 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1488 1489 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1490 cp = &sc->pciide_channels[channel]; 1491 if (pciide_chansetup(sc, channel, interface) == 0) 1492 continue; 1493 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1494 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1495 &ctlsize, pciide_pci_intr); 1496 } else { 1497 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1498 channel, &cmdsize, &ctlsize); 1499 } 1500 if (cp->hw_ok == 0) 1501 continue; 1502 /* 1503 * Check to see if something appears to be there. 1504 */ 1505 failreason = NULL; 1506 if (!wdcprobe(&cp->wdc_channel)) { 1507 failreason = "not responding; disabled or no drives?"; 1508 goto next; 1509 } 1510 /* 1511 * Now, make sure it's actually attributable to this PCI IDE 1512 * channel by trying to access the channel again while the 1513 * PCI IDE controller's I/O space is disabled. (If the 1514 * channel no longer appears to be there, it belongs to 1515 * this controller.) YUCK! 1516 */ 1517 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1518 PCI_COMMAND_STATUS_REG); 1519 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1520 csr & ~PCI_COMMAND_IO_ENABLE); 1521 if (wdcprobe(&cp->wdc_channel)) 1522 failreason = "other hardware responding at addresses"; 1523 pci_conf_write(sc->sc_pc, sc->sc_tag, 1524 PCI_COMMAND_STATUS_REG, csr); 1525 next: 1526 if (failreason) { 1527 printf("%s: %s channel ignored (%s)\n", 1528 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1529 failreason); 1530 cp->hw_ok = 0; 1531 bus_space_unmap(cp->wdc_channel.cmd_iot, 1532 cp->wdc_channel.cmd_ioh, cmdsize); 1533 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1534 bus_space_unmap(cp->wdc_channel.ctl_iot, 1535 cp->ctl_baseioh, ctlsize); 1536 else 1537 bus_space_unmap(cp->wdc_channel.ctl_iot, 1538 cp->wdc_channel.ctl_ioh, ctlsize); 1539 } else { 1540 pciide_map_compat_intr(pa, cp, channel, interface); 1541 } 1542 if (cp->hw_ok) { 1543 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1544 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1545 wdcattach(&cp->wdc_channel); 1546 } 1547 } 1548 1549 if (sc->sc_dma_ok == 0) 1550 return; 1551 1552 /* Allocate DMA maps */ 1553 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1554 idedma_ctl = 0; 1555 cp = &sc->pciide_channels[channel]; 1556 for (drive = 0; drive < 2; drive++) { 1557 drvp = &cp->wdc_channel.ch_drive[drive]; 1558 /* If no drive, skip */ 1559 if ((drvp->drive_flags & DRIVE) == 0) 1560 continue; 1561 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1562 continue; 1563 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1564 /* Abort DMA setup */ 1565 printf("%s:%d:%d: can't allocate DMA maps, " 1566 "using PIO transfers\n", 1567 sc->sc_wdcdev.sc_dev.dv_xname, 1568 channel, drive); 1569 drvp->drive_flags &= ~DRIVE_DMA; 1570 } 1571 printf("%s:%d:%d: using DMA data transfers\n", 1572 sc->sc_wdcdev.sc_dev.dv_xname, 1573 channel, drive); 1574 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1575 } 1576 if (idedma_ctl != 0) { 1577 /* Add software bits in status register */ 1578 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1579 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1580 idedma_ctl); 1581 } 1582 } 1583 } 1584 1585 void 1586 sata_setup_channel(chp) 1587 struct channel_softc *chp; 1588 { 1589 struct ata_drive_datas *drvp; 1590 int drive; 1591 u_int32_t idedma_ctl; 1592 struct pciide_channel *cp = (struct pciide_channel*)chp; 1593 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 1594 1595 /* setup DMA if needed */ 1596 pciide_channel_dma_setup(cp); 1597 1598 idedma_ctl = 0; 1599 1600 for (drive = 0; drive < 2; drive++) { 1601 drvp = &chp->ch_drive[drive]; 1602 /* If no drive, skip */ 1603 if ((drvp->drive_flags & DRIVE) == 0) 1604 continue; 1605 if (drvp->drive_flags & DRIVE_UDMA) { 1606 /* use Ultra/DMA */ 1607 drvp->drive_flags &= ~DRIVE_DMA; 1608 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1609 } else if (drvp->drive_flags & DRIVE_DMA) { 1610 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1611 } 1612 } 1613 1614 /* 1615 * Nothing to do to setup modes; it is meaningless in S-ATA 1616 * (but many S-ATA drives still want to get the SET_FEATURE 1617 * command). 1618 */ 1619 if (idedma_ctl != 0) { 1620 /* Add software bits in status register */ 1621 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1622 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1623 idedma_ctl); 1624 } 1625 pciide_print_modes(cp); 1626 } 1627 1628 void 1629 piix_chip_map(sc, pa) 1630 struct pciide_softc *sc; 1631 struct pci_attach_args *pa; 1632 { 1633 struct pciide_channel *cp; 1634 int channel; 1635 u_int32_t idetim; 1636 bus_size_t cmdsize, ctlsize; 1637 1638 if (pciide_chipen(sc, pa) == 0) 1639 return; 1640 1641 printf("%s: bus-master DMA support present", 1642 sc->sc_wdcdev.sc_dev.dv_xname); 1643 pciide_mapreg_dma(sc, pa); 1644 printf("\n"); 1645 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1646 WDC_CAPABILITY_MODE; 1647 if (sc->sc_dma_ok) { 1648 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1649 sc->sc_wdcdev.irqack = pciide_irqack; 1650 switch(sc->sc_pp->ide_product) { 1651 case PCI_PRODUCT_INTEL_82371AB_IDE: 1652 case PCI_PRODUCT_INTEL_82440MX_IDE: 1653 case PCI_PRODUCT_INTEL_82801AA_IDE: 1654 case PCI_PRODUCT_INTEL_82801AB_IDE: 1655 case PCI_PRODUCT_INTEL_82801BA_IDE: 1656 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1657 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1658 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1659 case PCI_PRODUCT_INTEL_82801DB_IDE: 1660 case PCI_PRODUCT_INTEL_82801DBM_IDE: 1661 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1662 } 1663 } 1664 sc->sc_wdcdev.PIO_cap = 4; 1665 sc->sc_wdcdev.DMA_cap = 2; 1666 switch(sc->sc_pp->ide_product) { 1667 case PCI_PRODUCT_INTEL_82801AA_IDE: 1668 sc->sc_wdcdev.UDMA_cap = 4; 1669 break; 1670 case PCI_PRODUCT_INTEL_82801BA_IDE: 1671 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1672 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1673 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1674 case PCI_PRODUCT_INTEL_82801DB_IDE: 1675 case PCI_PRODUCT_INTEL_82801DBM_IDE: 1676 sc->sc_wdcdev.UDMA_cap = 5; 1677 break; 1678 default: 1679 sc->sc_wdcdev.UDMA_cap = 2; 1680 } 1681 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1682 sc->sc_wdcdev.set_modes = piix_setup_channel; 1683 else 1684 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1685 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1686 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1687 1688 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1689 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1690 DEBUG_PROBE); 1691 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1692 WDCDEBUG_PRINT((", sidetim=0x%x", 1693 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1694 DEBUG_PROBE); 1695 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1696 WDCDEBUG_PRINT((", udamreg 0x%x", 1697 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1698 DEBUG_PROBE); 1699 } 1700 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1701 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1702 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1703 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1704 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1705 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1706 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 1707 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE) { 1708 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1709 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1710 DEBUG_PROBE); 1711 } 1712 1713 } 1714 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1715 1716 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1717 cp = &sc->pciide_channels[channel]; 1718 /* PIIX is compat-only */ 1719 if (pciide_chansetup(sc, channel, 0) == 0) 1720 continue; 1721 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1722 if ((PIIX_IDETIM_READ(idetim, channel) & 1723 PIIX_IDETIM_IDE) == 0) { 1724 printf("%s: %s channel ignored (disabled)\n", 1725 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1726 continue; 1727 } 1728 /* PIIX are compat-only pciide devices */ 1729 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1730 if (cp->hw_ok == 0) 1731 continue; 1732 if (pciide_chan_candisable(cp)) { 1733 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1734 channel); 1735 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1736 idetim); 1737 } 1738 pciide_map_compat_intr(pa, cp, channel, 0); 1739 if (cp->hw_ok == 0) 1740 continue; 1741 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1742 } 1743 1744 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1745 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1746 DEBUG_PROBE); 1747 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1748 WDCDEBUG_PRINT((", sidetim=0x%x", 1749 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1750 DEBUG_PROBE); 1751 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1752 WDCDEBUG_PRINT((", udamreg 0x%x", 1753 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1754 DEBUG_PROBE); 1755 } 1756 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1757 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1758 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1759 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1760 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1761 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1762 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 1763 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE) { 1764 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1765 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1766 DEBUG_PROBE); 1767 } 1768 } 1769 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1770 } 1771 1772 void 1773 piix_setup_channel(chp) 1774 struct channel_softc *chp; 1775 { 1776 u_int8_t mode[2], drive; 1777 u_int32_t oidetim, idetim, idedma_ctl; 1778 struct pciide_channel *cp = (struct pciide_channel*)chp; 1779 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1780 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1781 1782 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1783 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1784 idedma_ctl = 0; 1785 1786 /* set up new idetim: Enable IDE registers decode */ 1787 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1788 chp->channel); 1789 1790 /* setup DMA */ 1791 pciide_channel_dma_setup(cp); 1792 1793 /* 1794 * Here we have to mess up with drives mode: PIIX can't have 1795 * different timings for master and slave drives. 1796 * We need to find the best combination. 1797 */ 1798 1799 /* If both drives supports DMA, take the lower mode */ 1800 if ((drvp[0].drive_flags & DRIVE_DMA) && 1801 (drvp[1].drive_flags & DRIVE_DMA)) { 1802 mode[0] = mode[1] = 1803 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1804 drvp[0].DMA_mode = mode[0]; 1805 drvp[1].DMA_mode = mode[1]; 1806 goto ok; 1807 } 1808 /* 1809 * If only one drive supports DMA, use its mode, and 1810 * put the other one in PIO mode 0 if mode not compatible 1811 */ 1812 if (drvp[0].drive_flags & DRIVE_DMA) { 1813 mode[0] = drvp[0].DMA_mode; 1814 mode[1] = drvp[1].PIO_mode; 1815 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1816 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1817 mode[1] = drvp[1].PIO_mode = 0; 1818 goto ok; 1819 } 1820 if (drvp[1].drive_flags & DRIVE_DMA) { 1821 mode[1] = drvp[1].DMA_mode; 1822 mode[0] = drvp[0].PIO_mode; 1823 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1824 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1825 mode[0] = drvp[0].PIO_mode = 0; 1826 goto ok; 1827 } 1828 /* 1829 * If both drives are not DMA, takes the lower mode, unless 1830 * one of them is PIO mode < 2 1831 */ 1832 if (drvp[0].PIO_mode < 2) { 1833 mode[0] = drvp[0].PIO_mode = 0; 1834 mode[1] = drvp[1].PIO_mode; 1835 } else if (drvp[1].PIO_mode < 2) { 1836 mode[1] = drvp[1].PIO_mode = 0; 1837 mode[0] = drvp[0].PIO_mode; 1838 } else { 1839 mode[0] = mode[1] = 1840 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1841 drvp[0].PIO_mode = mode[0]; 1842 drvp[1].PIO_mode = mode[1]; 1843 } 1844 ok: /* The modes are setup */ 1845 for (drive = 0; drive < 2; drive++) { 1846 if (drvp[drive].drive_flags & DRIVE_DMA) { 1847 idetim |= piix_setup_idetim_timings( 1848 mode[drive], 1, chp->channel); 1849 goto end; 1850 } 1851 } 1852 /* If we are there, none of the drives are DMA */ 1853 if (mode[0] >= 2) 1854 idetim |= piix_setup_idetim_timings( 1855 mode[0], 0, chp->channel); 1856 else 1857 idetim |= piix_setup_idetim_timings( 1858 mode[1], 0, chp->channel); 1859 end: /* 1860 * timing mode is now set up in the controller. Enable 1861 * it per-drive 1862 */ 1863 for (drive = 0; drive < 2; drive++) { 1864 /* If no drive, skip */ 1865 if ((drvp[drive].drive_flags & DRIVE) == 0) 1866 continue; 1867 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1868 if (drvp[drive].drive_flags & DRIVE_DMA) 1869 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1870 } 1871 if (idedma_ctl != 0) { 1872 /* Add software bits in status register */ 1873 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1874 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1875 idedma_ctl); 1876 } 1877 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1878 pciide_print_modes(cp); 1879 } 1880 1881 void 1882 piix3_4_setup_channel(chp) 1883 struct channel_softc *chp; 1884 { 1885 struct ata_drive_datas *drvp; 1886 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1887 struct pciide_channel *cp = (struct pciide_channel*)chp; 1888 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1889 int drive; 1890 int channel = chp->channel; 1891 1892 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1893 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1894 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1895 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1896 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1897 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1898 PIIX_SIDETIM_RTC_MASK(channel)); 1899 1900 idedma_ctl = 0; 1901 /* If channel disabled, no need to go further */ 1902 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1903 return; 1904 /* set up new idetim: Enable IDE registers decode */ 1905 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1906 1907 /* setup DMA if needed */ 1908 pciide_channel_dma_setup(cp); 1909 1910 for (drive = 0; drive < 2; drive++) { 1911 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1912 PIIX_UDMATIM_SET(0x3, channel, drive)); 1913 drvp = &chp->ch_drive[drive]; 1914 /* If no drive, skip */ 1915 if ((drvp->drive_flags & DRIVE) == 0) 1916 continue; 1917 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1918 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1919 goto pio; 1920 1921 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1922 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1923 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1924 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1925 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1926 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1927 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 1928 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE) { 1929 ideconf |= PIIX_CONFIG_PINGPONG; 1930 } 1931 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1932 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1933 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1934 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1935 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 1936 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE) { 1937 /* setup Ultra/100 */ 1938 if (drvp->UDMA_mode > 2 && 1939 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1940 drvp->UDMA_mode = 2; 1941 if (drvp->UDMA_mode > 4) { 1942 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1943 } else { 1944 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1945 if (drvp->UDMA_mode > 2) { 1946 ideconf |= PIIX_CONFIG_UDMA66(channel, 1947 drive); 1948 } else { 1949 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1950 drive); 1951 } 1952 } 1953 } 1954 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1955 /* setup Ultra/66 */ 1956 if (drvp->UDMA_mode > 2 && 1957 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1958 drvp->UDMA_mode = 2; 1959 if (drvp->UDMA_mode > 2) 1960 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1961 else 1962 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1963 } 1964 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1965 (drvp->drive_flags & DRIVE_UDMA)) { 1966 /* use Ultra/DMA */ 1967 drvp->drive_flags &= ~DRIVE_DMA; 1968 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1969 udmareg |= PIIX_UDMATIM_SET( 1970 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1971 } else { 1972 /* use Multiword DMA */ 1973 drvp->drive_flags &= ~DRIVE_UDMA; 1974 if (drive == 0) { 1975 idetim |= piix_setup_idetim_timings( 1976 drvp->DMA_mode, 1, channel); 1977 } else { 1978 sidetim |= piix_setup_sidetim_timings( 1979 drvp->DMA_mode, 1, channel); 1980 idetim =PIIX_IDETIM_SET(idetim, 1981 PIIX_IDETIM_SITRE, channel); 1982 } 1983 } 1984 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1985 1986 pio: /* use PIO mode */ 1987 idetim |= piix_setup_idetim_drvs(drvp); 1988 if (drive == 0) { 1989 idetim |= piix_setup_idetim_timings( 1990 drvp->PIO_mode, 0, channel); 1991 } else { 1992 sidetim |= piix_setup_sidetim_timings( 1993 drvp->PIO_mode, 0, channel); 1994 idetim =PIIX_IDETIM_SET(idetim, 1995 PIIX_IDETIM_SITRE, channel); 1996 } 1997 } 1998 if (idedma_ctl != 0) { 1999 /* Add software bits in status register */ 2000 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2001 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 2002 idedma_ctl); 2003 } 2004 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 2005 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 2006 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 2007 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 2008 pciide_print_modes(cp); 2009 } 2010 2011 2012 /* setup ISP and RTC fields, based on mode */ 2013 static u_int32_t 2014 piix_setup_idetim_timings(mode, dma, channel) 2015 u_int8_t mode; 2016 u_int8_t dma; 2017 u_int8_t channel; 2018 { 2019 2020 if (dma) 2021 return PIIX_IDETIM_SET(0, 2022 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 2023 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 2024 channel); 2025 else 2026 return PIIX_IDETIM_SET(0, 2027 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 2028 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 2029 channel); 2030 } 2031 2032 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 2033 static u_int32_t 2034 piix_setup_idetim_drvs(drvp) 2035 struct ata_drive_datas *drvp; 2036 { 2037 u_int32_t ret = 0; 2038 struct channel_softc *chp = drvp->chnl_softc; 2039 u_int8_t channel = chp->channel; 2040 u_int8_t drive = drvp->drive; 2041 2042 /* 2043 * If drive is using UDMA, timings setups are independant 2044 * So just check DMA and PIO here. 2045 */ 2046 if (drvp->drive_flags & DRIVE_DMA) { 2047 /* if mode = DMA mode 0, use compatible timings */ 2048 if ((drvp->drive_flags & DRIVE_DMA) && 2049 drvp->DMA_mode == 0) { 2050 drvp->PIO_mode = 0; 2051 return ret; 2052 } 2053 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2054 /* 2055 * PIO and DMA timings are the same, use fast timings for PIO 2056 * too, else use compat timings. 2057 */ 2058 if ((piix_isp_pio[drvp->PIO_mode] != 2059 piix_isp_dma[drvp->DMA_mode]) || 2060 (piix_rtc_pio[drvp->PIO_mode] != 2061 piix_rtc_dma[drvp->DMA_mode])) 2062 drvp->PIO_mode = 0; 2063 /* if PIO mode <= 2, use compat timings for PIO */ 2064 if (drvp->PIO_mode <= 2) { 2065 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 2066 channel); 2067 return ret; 2068 } 2069 } 2070 2071 /* 2072 * Now setup PIO modes. If mode < 2, use compat timings. 2073 * Else enable fast timings. Enable IORDY and prefetch/post 2074 * if PIO mode >= 3. 2075 */ 2076 2077 if (drvp->PIO_mode < 2) 2078 return ret; 2079 2080 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2081 if (drvp->PIO_mode >= 3) { 2082 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 2083 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 2084 } 2085 return ret; 2086 } 2087 2088 /* setup values in SIDETIM registers, based on mode */ 2089 static u_int32_t 2090 piix_setup_sidetim_timings(mode, dma, channel) 2091 u_int8_t mode; 2092 u_int8_t dma; 2093 u_int8_t channel; 2094 { 2095 if (dma) 2096 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 2097 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 2098 else 2099 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 2100 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 2101 } 2102 2103 void 2104 amd7x6_chip_map(sc, pa) 2105 struct pciide_softc *sc; 2106 struct pci_attach_args *pa; 2107 { 2108 struct pciide_channel *cp; 2109 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2110 int channel; 2111 pcireg_t chanenable; 2112 bus_size_t cmdsize, ctlsize; 2113 2114 if (pciide_chipen(sc, pa) == 0) 2115 return; 2116 printf("%s: bus-master DMA support present", 2117 sc->sc_wdcdev.sc_dev.dv_xname); 2118 pciide_mapreg_dma(sc, pa); 2119 printf("\n"); 2120 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2121 WDC_CAPABILITY_MODE; 2122 if (sc->sc_dma_ok) { 2123 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2124 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2125 sc->sc_wdcdev.irqack = pciide_irqack; 2126 } 2127 sc->sc_wdcdev.PIO_cap = 4; 2128 sc->sc_wdcdev.DMA_cap = 2; 2129 2130 switch (sc->sc_pci_vendor) { 2131 case PCI_VENDOR_AMD: 2132 switch (sc->sc_pp->ide_product) { 2133 case PCI_PRODUCT_AMD_PBC766_IDE: 2134 case PCI_PRODUCT_AMD_PBC768_IDE: 2135 case PCI_PRODUCT_AMD_PBC8111_IDE: 2136 sc->sc_wdcdev.UDMA_cap = 5; 2137 break; 2138 default: 2139 sc->sc_wdcdev.UDMA_cap = 4; 2140 } 2141 sc->sc_amd_regbase = AMD7X6_AMD_REGBASE; 2142 break; 2143 2144 case PCI_VENDOR_NVIDIA: 2145 switch (sc->sc_pp->ide_product) { 2146 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 2147 sc->sc_wdcdev.UDMA_cap = 5; 2148 break; 2149 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 2150 sc->sc_wdcdev.UDMA_cap = 6; 2151 break; 2152 } 2153 sc->sc_amd_regbase = AMD7X6_NVIDIA_REGBASE; 2154 break; 2155 2156 default: 2157 panic("amd7x6_chip_map: unknown vendor"); 2158 } 2159 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 2160 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2161 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2162 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, 2163 AMD7X6_CHANSTATUS_EN(sc)); 2164 2165 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 2166 DEBUG_PROBE); 2167 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2168 cp = &sc->pciide_channels[channel]; 2169 if (pciide_chansetup(sc, channel, interface) == 0) 2170 continue; 2171 2172 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 2173 printf("%s: %s channel ignored (disabled)\n", 2174 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2175 continue; 2176 } 2177 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2178 pciide_pci_intr); 2179 2180 if (pciide_chan_candisable(cp)) 2181 chanenable &= ~AMD7X6_CHAN_EN(channel); 2182 pciide_map_compat_intr(pa, cp, channel, interface); 2183 if (cp->hw_ok == 0) 2184 continue; 2185 2186 amd7x6_setup_channel(&cp->wdc_channel); 2187 } 2188 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN(sc), 2189 chanenable); 2190 return; 2191 } 2192 2193 void 2194 amd7x6_setup_channel(chp) 2195 struct channel_softc *chp; 2196 { 2197 u_int32_t udmatim_reg, datatim_reg; 2198 u_int8_t idedma_ctl; 2199 int mode, drive; 2200 struct ata_drive_datas *drvp; 2201 struct pciide_channel *cp = (struct pciide_channel*)chp; 2202 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2203 #ifndef PCIIDE_AMD756_ENABLEDMA 2204 int rev = PCI_REVISION( 2205 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2206 #endif 2207 2208 idedma_ctl = 0; 2209 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc)); 2210 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc)); 2211 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2212 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2213 2214 /* setup DMA if needed */ 2215 pciide_channel_dma_setup(cp); 2216 2217 for (drive = 0; drive < 2; drive++) { 2218 drvp = &chp->ch_drive[drive]; 2219 /* If no drive, skip */ 2220 if ((drvp->drive_flags & DRIVE) == 0) 2221 continue; 2222 /* add timing values, setup DMA if needed */ 2223 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2224 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2225 mode = drvp->PIO_mode; 2226 goto pio; 2227 } 2228 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2229 (drvp->drive_flags & DRIVE_UDMA)) { 2230 /* use Ultra/DMA */ 2231 drvp->drive_flags &= ~DRIVE_DMA; 2232 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2233 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2234 AMD7X6_UDMA_TIME(chp->channel, drive, 2235 amd7x6_udma_tim[drvp->UDMA_mode]); 2236 /* can use PIO timings, MW DMA unused */ 2237 mode = drvp->PIO_mode; 2238 } else { 2239 /* use Multiword DMA, but only if revision is OK */ 2240 drvp->drive_flags &= ~DRIVE_UDMA; 2241 #ifndef PCIIDE_AMD756_ENABLEDMA 2242 /* 2243 * The workaround doesn't seem to be necessary 2244 * with all drives, so it can be disabled by 2245 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2246 * triggered. 2247 */ 2248 if (sc->sc_pci_vendor == PCI_VENDOR_AMD && 2249 sc->sc_pp->ide_product == 2250 PCI_PRODUCT_AMD_PBC756_IDE && 2251 AMD756_CHIPREV_DISABLEDMA(rev)) { 2252 printf("%s:%d:%d: multi-word DMA disabled due " 2253 "to chip revision\n", 2254 sc->sc_wdcdev.sc_dev.dv_xname, 2255 chp->channel, drive); 2256 mode = drvp->PIO_mode; 2257 drvp->drive_flags &= ~DRIVE_DMA; 2258 goto pio; 2259 } 2260 #endif 2261 /* mode = min(pio, dma+2) */ 2262 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2263 mode = drvp->PIO_mode; 2264 else 2265 mode = drvp->DMA_mode + 2; 2266 } 2267 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2268 2269 pio: /* setup PIO mode */ 2270 if (mode <= 2) { 2271 drvp->DMA_mode = 0; 2272 drvp->PIO_mode = 0; 2273 mode = 0; 2274 } else { 2275 drvp->PIO_mode = mode; 2276 drvp->DMA_mode = mode - 2; 2277 } 2278 datatim_reg |= 2279 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2280 amd7x6_pio_set[mode]) | 2281 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2282 amd7x6_pio_rec[mode]); 2283 } 2284 if (idedma_ctl != 0) { 2285 /* Add software bits in status register */ 2286 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2287 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2288 idedma_ctl); 2289 } 2290 pciide_print_modes(cp); 2291 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc), datatim_reg); 2292 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc), udmatim_reg); 2293 } 2294 2295 void 2296 apollo_chip_map(sc, pa) 2297 struct pciide_softc *sc; 2298 struct pci_attach_args *pa; 2299 { 2300 struct pciide_channel *cp; 2301 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2302 int channel; 2303 u_int32_t ideconf; 2304 bus_size_t cmdsize, ctlsize; 2305 pcitag_t pcib_tag; 2306 pcireg_t pcib_id, pcib_class; 2307 2308 if (pciide_chipen(sc, pa) == 0) 2309 return; 2310 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2311 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2312 /* and read ID and rev of the ISA bridge */ 2313 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2314 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2315 printf(": VIA Technologies "); 2316 switch (PCI_PRODUCT(pcib_id)) { 2317 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2318 printf("VT82C586 (Apollo VP) "); 2319 if(PCI_REVISION(pcib_class) >= 0x02) { 2320 printf("ATA33 controller\n"); 2321 sc->sc_wdcdev.UDMA_cap = 2; 2322 } else { 2323 printf("controller\n"); 2324 sc->sc_wdcdev.UDMA_cap = 0; 2325 } 2326 break; 2327 case PCI_PRODUCT_VIATECH_VT82C596A: 2328 printf("VT82C596A (Apollo Pro) "); 2329 if (PCI_REVISION(pcib_class) >= 0x12) { 2330 printf("ATA66 controller\n"); 2331 sc->sc_wdcdev.UDMA_cap = 4; 2332 } else { 2333 printf("ATA33 controller\n"); 2334 sc->sc_wdcdev.UDMA_cap = 2; 2335 } 2336 break; 2337 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2338 printf("VT82C686A (Apollo KX133) "); 2339 if (PCI_REVISION(pcib_class) >= 0x40) { 2340 printf("ATA100 controller\n"); 2341 sc->sc_wdcdev.UDMA_cap = 5; 2342 } else { 2343 printf("ATA66 controller\n"); 2344 sc->sc_wdcdev.UDMA_cap = 4; 2345 } 2346 break; 2347 case PCI_PRODUCT_VIATECH_VT8231: 2348 printf("VT8231 ATA100 controller\n"); 2349 sc->sc_wdcdev.UDMA_cap = 5; 2350 break; 2351 case PCI_PRODUCT_VIATECH_VT8233: 2352 printf("VT8233 ATA100 controller\n"); 2353 sc->sc_wdcdev.UDMA_cap = 5; 2354 break; 2355 case PCI_PRODUCT_VIATECH_VT8233A: 2356 printf("VT8233A ATA133 controller\n"); 2357 sc->sc_wdcdev.UDMA_cap = 6; 2358 break; 2359 case PCI_PRODUCT_VIATECH_VT8235: 2360 printf("VT8235 ATA133 controller\n"); 2361 sc->sc_wdcdev.UDMA_cap = 6; 2362 break; 2363 default: 2364 printf("unknown ATA controller\n"); 2365 sc->sc_wdcdev.UDMA_cap = 0; 2366 } 2367 2368 printf("%s: bus-master DMA support present", 2369 sc->sc_wdcdev.sc_dev.dv_xname); 2370 pciide_mapreg_dma(sc, pa); 2371 printf("\n"); 2372 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2373 WDC_CAPABILITY_MODE; 2374 if (sc->sc_dma_ok) { 2375 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2376 sc->sc_wdcdev.irqack = pciide_irqack; 2377 if (sc->sc_wdcdev.UDMA_cap > 0) 2378 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2379 } 2380 sc->sc_wdcdev.PIO_cap = 4; 2381 sc->sc_wdcdev.DMA_cap = 2; 2382 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2383 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2384 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2385 2386 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2387 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2388 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2389 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2390 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2391 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2392 DEBUG_PROBE); 2393 2394 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2395 cp = &sc->pciide_channels[channel]; 2396 if (pciide_chansetup(sc, channel, interface) == 0) 2397 continue; 2398 2399 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2400 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2401 printf("%s: %s channel ignored (disabled)\n", 2402 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2403 continue; 2404 } 2405 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2406 pciide_pci_intr); 2407 if (cp->hw_ok == 0) 2408 continue; 2409 if (pciide_chan_candisable(cp)) { 2410 ideconf &= ~APO_IDECONF_EN(channel); 2411 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2412 ideconf); 2413 } 2414 pciide_map_compat_intr(pa, cp, channel, interface); 2415 2416 if (cp->hw_ok == 0) 2417 continue; 2418 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2419 } 2420 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2421 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2422 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2423 } 2424 2425 void 2426 apollo_setup_channel(chp) 2427 struct channel_softc *chp; 2428 { 2429 u_int32_t udmatim_reg, datatim_reg; 2430 u_int8_t idedma_ctl; 2431 int mode, drive; 2432 struct ata_drive_datas *drvp; 2433 struct pciide_channel *cp = (struct pciide_channel*)chp; 2434 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2435 2436 idedma_ctl = 0; 2437 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2438 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2439 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2440 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2441 2442 /* setup DMA if needed */ 2443 pciide_channel_dma_setup(cp); 2444 2445 for (drive = 0; drive < 2; drive++) { 2446 drvp = &chp->ch_drive[drive]; 2447 /* If no drive, skip */ 2448 if ((drvp->drive_flags & DRIVE) == 0) 2449 continue; 2450 /* add timing values, setup DMA if needed */ 2451 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2452 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2453 mode = drvp->PIO_mode; 2454 goto pio; 2455 } 2456 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2457 (drvp->drive_flags & DRIVE_UDMA)) { 2458 /* use Ultra/DMA */ 2459 drvp->drive_flags &= ~DRIVE_DMA; 2460 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2461 APO_UDMA_EN_MTH(chp->channel, drive); 2462 if (sc->sc_wdcdev.UDMA_cap == 6) { 2463 /* 8233a */ 2464 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2465 drive, apollo_udma133_tim[drvp->UDMA_mode]); 2466 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 2467 /* 686b */ 2468 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2469 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2470 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2471 /* 596b or 686a */ 2472 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2473 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2474 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2475 } else { 2476 /* 596a or 586b */ 2477 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2478 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2479 } 2480 /* can use PIO timings, MW DMA unused */ 2481 mode = drvp->PIO_mode; 2482 } else { 2483 /* use Multiword DMA */ 2484 drvp->drive_flags &= ~DRIVE_UDMA; 2485 /* mode = min(pio, dma+2) */ 2486 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2487 mode = drvp->PIO_mode; 2488 else 2489 mode = drvp->DMA_mode + 2; 2490 } 2491 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2492 2493 pio: /* setup PIO mode */ 2494 if (mode <= 2) { 2495 drvp->DMA_mode = 0; 2496 drvp->PIO_mode = 0; 2497 mode = 0; 2498 } else { 2499 drvp->PIO_mode = mode; 2500 drvp->DMA_mode = mode - 2; 2501 } 2502 datatim_reg |= 2503 APO_DATATIM_PULSE(chp->channel, drive, 2504 apollo_pio_set[mode]) | 2505 APO_DATATIM_RECOV(chp->channel, drive, 2506 apollo_pio_rec[mode]); 2507 } 2508 if (idedma_ctl != 0) { 2509 /* Add software bits in status register */ 2510 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2511 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2512 idedma_ctl); 2513 } 2514 pciide_print_modes(cp); 2515 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2516 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2517 } 2518 2519 void 2520 cmd_channel_map(pa, sc, channel) 2521 struct pci_attach_args *pa; 2522 struct pciide_softc *sc; 2523 int channel; 2524 { 2525 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2526 bus_size_t cmdsize, ctlsize; 2527 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2528 int interface, one_channel; 2529 2530 /* 2531 * The 0648/0649 can be told to identify as a RAID controller. 2532 * In this case, we have to fake interface 2533 */ 2534 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2535 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2536 PCIIDE_INTERFACE_SETTABLE(1); 2537 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2538 CMD_CONF_DSA1) 2539 interface |= PCIIDE_INTERFACE_PCI(0) | 2540 PCIIDE_INTERFACE_PCI(1); 2541 } else { 2542 interface = PCI_INTERFACE(pa->pa_class); 2543 } 2544 2545 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2546 cp->name = PCIIDE_CHANNEL_NAME(channel); 2547 cp->wdc_channel.channel = channel; 2548 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2549 2550 /* 2551 * Older CMD64X doesn't have independant channels 2552 */ 2553 switch (sc->sc_pp->ide_product) { 2554 case PCI_PRODUCT_CMDTECH_649: 2555 one_channel = 0; 2556 break; 2557 default: 2558 one_channel = 1; 2559 break; 2560 } 2561 2562 if (channel > 0 && one_channel) { 2563 cp->wdc_channel.ch_queue = 2564 sc->pciide_channels[0].wdc_channel.ch_queue; 2565 } else { 2566 cp->wdc_channel.ch_queue = 2567 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2568 } 2569 if (cp->wdc_channel.ch_queue == NULL) { 2570 printf("%s %s channel: " 2571 "can't allocate memory for command queue", 2572 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2573 return; 2574 } 2575 2576 printf("%s: %s channel %s to %s mode\n", 2577 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2578 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2579 "configured" : "wired", 2580 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2581 "native-PCI" : "compatibility"); 2582 2583 /* 2584 * with a CMD PCI64x, if we get here, the first channel is enabled: 2585 * there's no way to disable the first channel without disabling 2586 * the whole device 2587 */ 2588 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2589 printf("%s: %s channel ignored (disabled)\n", 2590 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2591 return; 2592 } 2593 2594 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2595 if (cp->hw_ok == 0) 2596 return; 2597 if (channel == 1) { 2598 if (pciide_chan_candisable(cp)) { 2599 ctrl &= ~CMD_CTRL_2PORT; 2600 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2601 CMD_CTRL, ctrl); 2602 } 2603 } 2604 pciide_map_compat_intr(pa, cp, channel, interface); 2605 } 2606 2607 int 2608 cmd_pci_intr(arg) 2609 void *arg; 2610 { 2611 struct pciide_softc *sc = arg; 2612 struct pciide_channel *cp; 2613 struct channel_softc *wdc_cp; 2614 int i, rv, crv; 2615 u_int32_t priirq, secirq; 2616 2617 rv = 0; 2618 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2619 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2620 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2621 cp = &sc->pciide_channels[i]; 2622 wdc_cp = &cp->wdc_channel; 2623 /* If a compat channel skip. */ 2624 if (cp->compat) 2625 continue; 2626 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2627 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2628 crv = wdcintr(wdc_cp); 2629 if (crv == 0) 2630 printf("%s:%d: bogus intr\n", 2631 sc->sc_wdcdev.sc_dev.dv_xname, i); 2632 else 2633 rv = 1; 2634 } 2635 } 2636 return rv; 2637 } 2638 2639 void 2640 cmd_chip_map(sc, pa) 2641 struct pciide_softc *sc; 2642 struct pci_attach_args *pa; 2643 { 2644 int channel; 2645 2646 /* 2647 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2648 * and base adresses registers can be disabled at 2649 * hardware level. In this case, the device is wired 2650 * in compat mode and its first channel is always enabled, 2651 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2652 * In fact, it seems that the first channel of the CMD PCI0640 2653 * can't be disabled. 2654 */ 2655 2656 #ifdef PCIIDE_CMD064x_DISABLE 2657 if (pciide_chipen(sc, pa) == 0) 2658 return; 2659 #endif 2660 2661 printf("%s: hardware does not support DMA\n", 2662 sc->sc_wdcdev.sc_dev.dv_xname); 2663 sc->sc_dma_ok = 0; 2664 2665 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2666 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2667 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2668 2669 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2670 cmd_channel_map(pa, sc, channel); 2671 } 2672 } 2673 2674 void 2675 cmd0643_9_chip_map(sc, pa) 2676 struct pciide_softc *sc; 2677 struct pci_attach_args *pa; 2678 { 2679 struct pciide_channel *cp; 2680 int channel; 2681 pcireg_t rev = PCI_REVISION(pa->pa_class); 2682 2683 /* 2684 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2685 * and base adresses registers can be disabled at 2686 * hardware level. In this case, the device is wired 2687 * in compat mode and its first channel is always enabled, 2688 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2689 * In fact, it seems that the first channel of the CMD PCI0640 2690 * can't be disabled. 2691 */ 2692 2693 #ifdef PCIIDE_CMD064x_DISABLE 2694 if (pciide_chipen(sc, pa) == 0) 2695 return; 2696 #endif 2697 printf("%s: bus-master DMA support present", 2698 sc->sc_wdcdev.sc_dev.dv_xname); 2699 pciide_mapreg_dma(sc, pa); 2700 printf("\n"); 2701 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2702 WDC_CAPABILITY_MODE; 2703 if (sc->sc_dma_ok) { 2704 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2705 switch (sc->sc_pp->ide_product) { 2706 case PCI_PRODUCT_CMDTECH_649: 2707 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2708 sc->sc_wdcdev.UDMA_cap = 5; 2709 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2710 break; 2711 case PCI_PRODUCT_CMDTECH_648: 2712 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2713 sc->sc_wdcdev.UDMA_cap = 4; 2714 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2715 break; 2716 case PCI_PRODUCT_CMDTECH_646: 2717 if (rev >= CMD0646U2_REV) { 2718 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2719 sc->sc_wdcdev.UDMA_cap = 2; 2720 } else if (rev >= CMD0646U_REV) { 2721 /* 2722 * Linux's driver claims that the 646U is broken 2723 * with UDMA. Only enable it if we know what we're 2724 * doing 2725 */ 2726 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2727 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2728 sc->sc_wdcdev.UDMA_cap = 2; 2729 #endif 2730 /* explicitly disable UDMA */ 2731 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2732 CMD_UDMATIM(0), 0); 2733 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2734 CMD_UDMATIM(1), 0); 2735 } 2736 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2737 break; 2738 default: 2739 sc->sc_wdcdev.irqack = pciide_irqack; 2740 } 2741 } 2742 2743 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2744 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2745 sc->sc_wdcdev.PIO_cap = 4; 2746 sc->sc_wdcdev.DMA_cap = 2; 2747 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2748 2749 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2750 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2751 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2752 DEBUG_PROBE); 2753 2754 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2755 cp = &sc->pciide_channels[channel]; 2756 cmd_channel_map(pa, sc, channel); 2757 if (cp->hw_ok == 0) 2758 continue; 2759 cmd0643_9_setup_channel(&cp->wdc_channel); 2760 } 2761 /* 2762 * note - this also makes sure we clear the irq disable and reset 2763 * bits 2764 */ 2765 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2766 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2767 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2768 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2769 DEBUG_PROBE); 2770 } 2771 2772 void 2773 cmd0643_9_setup_channel(chp) 2774 struct channel_softc *chp; 2775 { 2776 struct ata_drive_datas *drvp; 2777 u_int8_t tim; 2778 u_int32_t idedma_ctl, udma_reg; 2779 int drive; 2780 struct pciide_channel *cp = (struct pciide_channel*)chp; 2781 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2782 2783 idedma_ctl = 0; 2784 /* setup DMA if needed */ 2785 pciide_channel_dma_setup(cp); 2786 2787 for (drive = 0; drive < 2; drive++) { 2788 drvp = &chp->ch_drive[drive]; 2789 /* If no drive, skip */ 2790 if ((drvp->drive_flags & DRIVE) == 0) 2791 continue; 2792 /* add timing values, setup DMA if needed */ 2793 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2794 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2795 if (drvp->drive_flags & DRIVE_UDMA) { 2796 /* UltraDMA on a 646U2, 0648 or 0649 */ 2797 drvp->drive_flags &= ~DRIVE_DMA; 2798 udma_reg = pciide_pci_read(sc->sc_pc, 2799 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2800 if (drvp->UDMA_mode > 2 && 2801 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2802 CMD_BICSR) & 2803 CMD_BICSR_80(chp->channel)) == 0) 2804 drvp->UDMA_mode = 2; 2805 if (drvp->UDMA_mode > 2) 2806 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2807 else if (sc->sc_wdcdev.UDMA_cap > 2) 2808 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2809 udma_reg |= CMD_UDMATIM_UDMA(drive); 2810 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2811 CMD_UDMATIM_TIM_OFF(drive)); 2812 udma_reg |= 2813 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2814 CMD_UDMATIM_TIM_OFF(drive)); 2815 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2816 CMD_UDMATIM(chp->channel), udma_reg); 2817 } else { 2818 /* 2819 * use Multiword DMA. 2820 * Timings will be used for both PIO and DMA, 2821 * so adjust DMA mode if needed 2822 * if we have a 0646U2/8/9, turn off UDMA 2823 */ 2824 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2825 udma_reg = pciide_pci_read(sc->sc_pc, 2826 sc->sc_tag, 2827 CMD_UDMATIM(chp->channel)); 2828 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2829 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2830 CMD_UDMATIM(chp->channel), 2831 udma_reg); 2832 } 2833 if (drvp->PIO_mode >= 3 && 2834 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2835 drvp->DMA_mode = drvp->PIO_mode - 2; 2836 } 2837 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2838 } 2839 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2840 } 2841 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2842 CMD_DATA_TIM(chp->channel, drive), tim); 2843 } 2844 if (idedma_ctl != 0) { 2845 /* Add software bits in status register */ 2846 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2847 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2848 idedma_ctl); 2849 } 2850 pciide_print_modes(cp); 2851 } 2852 2853 void 2854 cmd646_9_irqack(chp) 2855 struct channel_softc *chp; 2856 { 2857 u_int32_t priirq, secirq; 2858 struct pciide_channel *cp = (struct pciide_channel*)chp; 2859 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2860 2861 if (chp->channel == 0) { 2862 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2863 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2864 } else { 2865 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2866 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2867 } 2868 pciide_irqack(chp); 2869 } 2870 2871 void 2872 cmd680_chip_map(sc, pa) 2873 struct pciide_softc *sc; 2874 struct pci_attach_args *pa; 2875 { 2876 struct pciide_channel *cp; 2877 int channel; 2878 2879 if (pciide_chipen(sc, pa) == 0) 2880 return; 2881 printf("%s: bus-master DMA support present", 2882 sc->sc_wdcdev.sc_dev.dv_xname); 2883 pciide_mapreg_dma(sc, pa); 2884 printf("\n"); 2885 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2886 WDC_CAPABILITY_MODE; 2887 if (sc->sc_dma_ok) { 2888 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2889 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2890 sc->sc_wdcdev.UDMA_cap = 6; 2891 sc->sc_wdcdev.irqack = pciide_irqack; 2892 } 2893 2894 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2895 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2896 sc->sc_wdcdev.PIO_cap = 4; 2897 sc->sc_wdcdev.DMA_cap = 2; 2898 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 2899 2900 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 2901 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 2902 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 2903 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 2904 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2905 cp = &sc->pciide_channels[channel]; 2906 cmd680_channel_map(pa, sc, channel); 2907 if (cp->hw_ok == 0) 2908 continue; 2909 cmd680_setup_channel(&cp->wdc_channel); 2910 } 2911 } 2912 2913 void 2914 cmd680_channel_map(pa, sc, channel) 2915 struct pci_attach_args *pa; 2916 struct pciide_softc *sc; 2917 int channel; 2918 { 2919 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2920 bus_size_t cmdsize, ctlsize; 2921 int interface, i, reg; 2922 static const u_int8_t init_val[] = 2923 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 2924 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 2925 2926 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2927 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2928 PCIIDE_INTERFACE_SETTABLE(1); 2929 interface |= PCIIDE_INTERFACE_PCI(0) | 2930 PCIIDE_INTERFACE_PCI(1); 2931 } else { 2932 interface = PCI_INTERFACE(pa->pa_class); 2933 } 2934 2935 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2936 cp->name = PCIIDE_CHANNEL_NAME(channel); 2937 cp->wdc_channel.channel = channel; 2938 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2939 2940 cp->wdc_channel.ch_queue = 2941 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2942 if (cp->wdc_channel.ch_queue == NULL) { 2943 printf("%s %s channel: " 2944 "can't allocate memory for command queue", 2945 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2946 return; 2947 } 2948 2949 /* XXX */ 2950 reg = 0xa2 + channel * 16; 2951 for (i = 0; i < sizeof(init_val); i++) 2952 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 2953 2954 printf("%s: %s channel %s to %s mode\n", 2955 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2956 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2957 "configured" : "wired", 2958 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2959 "native-PCI" : "compatibility"); 2960 2961 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 2962 if (cp->hw_ok == 0) 2963 return; 2964 pciide_map_compat_intr(pa, cp, channel, interface); 2965 } 2966 2967 void 2968 cmd680_setup_channel(chp) 2969 struct channel_softc *chp; 2970 { 2971 struct ata_drive_datas *drvp; 2972 u_int8_t mode, off, scsc; 2973 u_int16_t val; 2974 u_int32_t idedma_ctl; 2975 int drive; 2976 struct pciide_channel *cp = (struct pciide_channel*)chp; 2977 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2978 pci_chipset_tag_t pc = sc->sc_pc; 2979 pcitag_t pa = sc->sc_tag; 2980 static const u_int8_t udma2_tbl[] = 2981 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 2982 static const u_int8_t udma_tbl[] = 2983 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 2984 static const u_int16_t dma_tbl[] = 2985 { 0x2208, 0x10c2, 0x10c1 }; 2986 static const u_int16_t pio_tbl[] = 2987 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 2988 2989 idedma_ctl = 0; 2990 pciide_channel_dma_setup(cp); 2991 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 2992 2993 for (drive = 0; drive < 2; drive++) { 2994 drvp = &chp->ch_drive[drive]; 2995 /* If no drive, skip */ 2996 if ((drvp->drive_flags & DRIVE) == 0) 2997 continue; 2998 mode &= ~(0x03 << (drive * 4)); 2999 if (drvp->drive_flags & DRIVE_UDMA) { 3000 drvp->drive_flags &= ~DRIVE_DMA; 3001 off = 0xa0 + chp->channel * 16; 3002 if (drvp->UDMA_mode > 2 && 3003 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 3004 drvp->UDMA_mode = 2; 3005 scsc = pciide_pci_read(pc, pa, 0x8a); 3006 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 3007 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 3008 scsc = pciide_pci_read(pc, pa, 0x8a); 3009 if ((scsc & 0x30) == 0) 3010 drvp->UDMA_mode = 5; 3011 } 3012 mode |= 0x03 << (drive * 4); 3013 off = 0xac + chp->channel * 16 + drive * 2; 3014 val = pciide_pci_read(pc, pa, off) & ~0x3f; 3015 if (scsc & 0x30) 3016 val |= udma2_tbl[drvp->UDMA_mode]; 3017 else 3018 val |= udma_tbl[drvp->UDMA_mode]; 3019 pciide_pci_write(pc, pa, off, val); 3020 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3021 } else if (drvp->drive_flags & DRIVE_DMA) { 3022 mode |= 0x02 << (drive * 4); 3023 off = 0xa8 + chp->channel * 16 + drive * 2; 3024 val = dma_tbl[drvp->DMA_mode]; 3025 pciide_pci_write(pc, pa, off, val & 0xff); 3026 pciide_pci_write(pc, pa, off, val >> 8); 3027 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3028 } else { 3029 mode |= 0x01 << (drive * 4); 3030 off = 0xa4 + chp->channel * 16 + drive * 2; 3031 val = pio_tbl[drvp->PIO_mode]; 3032 pciide_pci_write(pc, pa, off, val & 0xff); 3033 pciide_pci_write(pc, pa, off, val >> 8); 3034 } 3035 } 3036 3037 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 3038 if (idedma_ctl != 0) { 3039 /* Add software bits in status register */ 3040 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3041 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3042 idedma_ctl); 3043 } 3044 pciide_print_modes(cp); 3045 } 3046 3047 void 3048 cmd3112_chip_map(sc, pa) 3049 struct pciide_softc *sc; 3050 struct pci_attach_args *pa; 3051 { 3052 struct pciide_channel *cp; 3053 bus_size_t cmdsize, ctlsize; 3054 pcireg_t interface; 3055 int channel; 3056 3057 if (pciide_chipen(sc, pa) == 0) 3058 return; 3059 3060 printf("%s: bus-master DMA support present", 3061 sc->sc_wdcdev.sc_dev.dv_xname); 3062 pciide_mapreg_dma(sc, pa); 3063 printf("\n"); 3064 3065 /* 3066 * Rev. <= 0x01 of the 3112 have a bug that can cause data 3067 * corruption if DMA transfers cross an 8K boundary. This is 3068 * apparently hard to tickle, but we'll go ahead and play it 3069 * safe. 3070 */ 3071 if (PCI_REVISION(pa->pa_class) <= 0x01) { 3072 sc->sc_dma_maxsegsz = 8192; 3073 sc->sc_dma_boundary = 8192; 3074 } 3075 3076 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3077 WDC_CAPABILITY_MODE; 3078 sc->sc_wdcdev.PIO_cap = 4; 3079 if (sc->sc_dma_ok) { 3080 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3081 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3082 sc->sc_wdcdev.irqack = pciide_irqack; 3083 sc->sc_wdcdev.DMA_cap = 2; 3084 sc->sc_wdcdev.UDMA_cap = 6; 3085 } 3086 sc->sc_wdcdev.set_modes = cmd3112_setup_channel; 3087 3088 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3089 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3090 3091 /* 3092 * The 3112 can be told to identify as a RAID controller. 3093 * In this case, we have to fake interface 3094 */ 3095 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3096 interface = PCI_INTERFACE(pa->pa_class); 3097 } else { 3098 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3099 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3100 } 3101 3102 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3103 cp = &sc->pciide_channels[channel]; 3104 if (pciide_chansetup(sc, channel, interface) == 0) 3105 continue; 3106 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3107 pciide_pci_intr); 3108 if (cp->hw_ok == 0) 3109 continue; 3110 pciide_map_compat_intr(pa, cp, channel, interface); 3111 cmd3112_setup_channel(&cp->wdc_channel); 3112 } 3113 } 3114 3115 void 3116 cmd3112_setup_channel(chp) 3117 struct channel_softc *chp; 3118 { 3119 struct ata_drive_datas *drvp; 3120 int drive; 3121 u_int32_t idedma_ctl, dtm; 3122 struct pciide_channel *cp = (struct pciide_channel*)chp; 3123 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 3124 3125 /* setup DMA if needed */ 3126 pciide_channel_dma_setup(cp); 3127 3128 idedma_ctl = 0; 3129 dtm = 0; 3130 3131 for (drive = 0; drive < 2; drive++) { 3132 drvp = &chp->ch_drive[drive]; 3133 /* If no drive, skip */ 3134 if ((drvp->drive_flags & DRIVE) == 0) 3135 continue; 3136 if (drvp->drive_flags & DRIVE_UDMA) { 3137 /* use Ultra/DMA */ 3138 drvp->drive_flags &= ~DRIVE_DMA; 3139 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3140 dtm |= DTM_IDEx_DMA; 3141 } else if (drvp->drive_flags & DRIVE_DMA) { 3142 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3143 dtm |= DTM_IDEx_DMA; 3144 } else { 3145 dtm |= DTM_IDEx_PIO; 3146 } 3147 } 3148 3149 /* 3150 * Nothing to do to setup modes; it is meaningless in S-ATA 3151 * (but many S-ATA drives still want to get the SET_FEATURE 3152 * command). 3153 */ 3154 if (idedma_ctl != 0) { 3155 /* Add software bits in status register */ 3156 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3157 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3158 idedma_ctl); 3159 } 3160 pci_conf_write(sc->sc_pc, sc->sc_tag, 3161 chp->channel == 0 ? SII3112_DTM_IDE0 : SII3112_DTM_IDE1, dtm); 3162 pciide_print_modes(cp); 3163 } 3164 3165 void 3166 cy693_chip_map(sc, pa) 3167 struct pciide_softc *sc; 3168 struct pci_attach_args *pa; 3169 { 3170 struct pciide_channel *cp; 3171 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3172 bus_size_t cmdsize, ctlsize; 3173 3174 if (pciide_chipen(sc, pa) == 0) 3175 return; 3176 /* 3177 * this chip has 2 PCI IDE functions, one for primary and one for 3178 * secondary. So we need to call pciide_mapregs_compat() with 3179 * the real channel 3180 */ 3181 if (pa->pa_function == 1) { 3182 sc->sc_cy_compatchan = 0; 3183 } else if (pa->pa_function == 2) { 3184 sc->sc_cy_compatchan = 1; 3185 } else { 3186 printf("%s: unexpected PCI function %d\n", 3187 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3188 return; 3189 } 3190 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 3191 printf("%s: bus-master DMA support present", 3192 sc->sc_wdcdev.sc_dev.dv_xname); 3193 pciide_mapreg_dma(sc, pa); 3194 } else { 3195 printf("%s: hardware does not support DMA", 3196 sc->sc_wdcdev.sc_dev.dv_xname); 3197 sc->sc_dma_ok = 0; 3198 } 3199 printf("\n"); 3200 3201 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 3202 if (sc->sc_cy_handle == NULL) { 3203 printf("%s: unable to map hyperCache control registers\n", 3204 sc->sc_wdcdev.sc_dev.dv_xname); 3205 sc->sc_dma_ok = 0; 3206 } 3207 3208 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3209 WDC_CAPABILITY_MODE; 3210 if (sc->sc_dma_ok) { 3211 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3212 sc->sc_wdcdev.irqack = pciide_irqack; 3213 } 3214 sc->sc_wdcdev.PIO_cap = 4; 3215 sc->sc_wdcdev.DMA_cap = 2; 3216 sc->sc_wdcdev.set_modes = cy693_setup_channel; 3217 3218 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3219 sc->sc_wdcdev.nchannels = 1; 3220 3221 /* Only one channel for this chip; if we are here it's enabled */ 3222 cp = &sc->pciide_channels[0]; 3223 sc->wdc_chanarray[0] = &cp->wdc_channel; 3224 cp->name = PCIIDE_CHANNEL_NAME(0); 3225 cp->wdc_channel.channel = 0; 3226 cp->wdc_channel.wdc = &sc->sc_wdcdev; 3227 cp->wdc_channel.ch_queue = 3228 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 3229 if (cp->wdc_channel.ch_queue == NULL) { 3230 printf("%s primary channel: " 3231 "can't allocate memory for command queue", 3232 sc->sc_wdcdev.sc_dev.dv_xname); 3233 return; 3234 } 3235 printf("%s: primary channel %s to ", 3236 sc->sc_wdcdev.sc_dev.dv_xname, 3237 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 3238 "configured" : "wired"); 3239 if (interface & PCIIDE_INTERFACE_PCI(0)) { 3240 printf("native-PCI"); 3241 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 3242 pciide_pci_intr); 3243 } else { 3244 printf("compatibility"); 3245 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 3246 &cmdsize, &ctlsize); 3247 } 3248 printf(" mode\n"); 3249 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3250 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3251 wdcattach(&cp->wdc_channel); 3252 if (pciide_chan_candisable(cp)) { 3253 pci_conf_write(sc->sc_pc, sc->sc_tag, 3254 PCI_COMMAND_STATUS_REG, 0); 3255 } 3256 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 3257 if (cp->hw_ok == 0) 3258 return; 3259 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 3260 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 3261 cy693_setup_channel(&cp->wdc_channel); 3262 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 3263 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 3264 } 3265 3266 void 3267 cy693_setup_channel(chp) 3268 struct channel_softc *chp; 3269 { 3270 struct ata_drive_datas *drvp; 3271 int drive; 3272 u_int32_t cy_cmd_ctrl; 3273 u_int32_t idedma_ctl; 3274 struct pciide_channel *cp = (struct pciide_channel*)chp; 3275 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3276 int dma_mode = -1; 3277 3278 cy_cmd_ctrl = idedma_ctl = 0; 3279 3280 /* setup DMA if needed */ 3281 pciide_channel_dma_setup(cp); 3282 3283 for (drive = 0; drive < 2; drive++) { 3284 drvp = &chp->ch_drive[drive]; 3285 /* If no drive, skip */ 3286 if ((drvp->drive_flags & DRIVE) == 0) 3287 continue; 3288 /* add timing values, setup DMA if needed */ 3289 if (drvp->drive_flags & DRIVE_DMA) { 3290 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3291 /* use Multiword DMA */ 3292 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 3293 dma_mode = drvp->DMA_mode; 3294 } 3295 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3296 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 3297 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3298 CY_CMD_CTRL_IOW_REC_OFF(drive)); 3299 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3300 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 3301 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3302 CY_CMD_CTRL_IOR_REC_OFF(drive)); 3303 } 3304 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 3305 chp->ch_drive[0].DMA_mode = dma_mode; 3306 chp->ch_drive[1].DMA_mode = dma_mode; 3307 3308 if (dma_mode == -1) 3309 dma_mode = 0; 3310 3311 if (sc->sc_cy_handle != NULL) { 3312 /* Note: `multiple' is implied. */ 3313 cy82c693_write(sc->sc_cy_handle, 3314 (sc->sc_cy_compatchan == 0) ? 3315 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 3316 } 3317 3318 pciide_print_modes(cp); 3319 3320 if (idedma_ctl != 0) { 3321 /* Add software bits in status register */ 3322 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3323 IDEDMA_CTL, idedma_ctl); 3324 } 3325 } 3326 3327 static struct sis_hostbr_type { 3328 u_int16_t id; 3329 u_int8_t rev; 3330 u_int8_t udma_mode; 3331 char *name; 3332 u_int8_t type; 3333 #define SIS_TYPE_NOUDMA 0 3334 #define SIS_TYPE_66 1 3335 #define SIS_TYPE_100OLD 2 3336 #define SIS_TYPE_100NEW 3 3337 #define SIS_TYPE_133OLD 4 3338 #define SIS_TYPE_133NEW 5 3339 #define SIS_TYPE_SOUTH 6 3340 } sis_hostbr_type[] = { 3341 /* Most infos here are from sos (at) freebsd.org */ 3342 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 3343 #if 0 3344 /* 3345 * controllers associated to a rev 0x2 530 Host to PCI Bridge 3346 * have problems with UDMA (info provided by Christos) 3347 */ 3348 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 3349 #endif 3350 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 3351 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 3352 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 3353 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 3354 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 3355 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 3356 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 3357 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 3358 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 3359 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 3360 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 3361 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 3362 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 3363 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 3364 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 3365 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 3366 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 3367 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 3368 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 3369 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 3370 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 3371 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 3372 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 3373 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 3374 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 3375 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 3376 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 3377 /* 3378 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 3379 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 3380 */ 3381 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 3382 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 3383 }; 3384 3385 static struct sis_hostbr_type *sis_hostbr_type_match; 3386 3387 static int 3388 sis_hostbr_match(pa) 3389 struct pci_attach_args *pa; 3390 { 3391 int i; 3392 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 3393 return 0; 3394 sis_hostbr_type_match = NULL; 3395 for (i = 0; 3396 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 3397 i++) { 3398 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 3399 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 3400 sis_hostbr_type_match = &sis_hostbr_type[i]; 3401 } 3402 return (sis_hostbr_type_match != NULL); 3403 } 3404 3405 static int sis_south_match(pa) 3406 struct pci_attach_args *pa; 3407 { 3408 return(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 3409 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 3410 PCI_REVISION(pa->pa_class) >= 0x10); 3411 } 3412 3413 void 3414 sis_chip_map(sc, pa) 3415 struct pciide_softc *sc; 3416 struct pci_attach_args *pa; 3417 { 3418 struct pciide_channel *cp; 3419 int channel; 3420 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 3421 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3422 pcireg_t rev = PCI_REVISION(pa->pa_class); 3423 bus_size_t cmdsize, ctlsize; 3424 3425 if (pciide_chipen(sc, pa) == 0) 3426 return; 3427 printf(": Silicon Integrated System "); 3428 pci_find_device(NULL, sis_hostbr_match); 3429 if (sis_hostbr_type_match) { 3430 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 3431 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 3432 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3433 SIS_REG_57) & 0x7f); 3434 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 3435 PCI_ID_REG)) == SIS_PRODUCT_5518) { 3436 printf("96X UDMA%d", 3437 sis_hostbr_type_match->udma_mode); 3438 sc->sis_type = SIS_TYPE_133NEW; 3439 sc->sc_wdcdev.UDMA_cap = 3440 sis_hostbr_type_match->udma_mode; 3441 } else { 3442 if (pci_find_device(NULL, sis_south_match)) { 3443 sc->sis_type = SIS_TYPE_133OLD; 3444 sc->sc_wdcdev.UDMA_cap = 3445 sis_hostbr_type_match->udma_mode; 3446 } else { 3447 sc->sis_type = SIS_TYPE_100NEW; 3448 sc->sc_wdcdev.UDMA_cap = 3449 sis_hostbr_type_match->udma_mode; 3450 } 3451 } 3452 } else { 3453 sc->sis_type = sis_hostbr_type_match->type; 3454 sc->sc_wdcdev.UDMA_cap = 3455 sis_hostbr_type_match->udma_mode; 3456 } 3457 printf(sis_hostbr_type_match->name); 3458 } else { 3459 printf("5597/5598"); 3460 if (rev >= 0xd0) { 3461 sc->sc_wdcdev.UDMA_cap = 2; 3462 sc->sis_type = SIS_TYPE_66; 3463 } else { 3464 sc->sc_wdcdev.UDMA_cap = 0; 3465 sc->sis_type = SIS_TYPE_NOUDMA; 3466 } 3467 } 3468 printf(" IDE controller (rev. 0x%02x)\n", PCI_REVISION(pa->pa_class)); 3469 printf("%s: bus-master DMA support present", 3470 sc->sc_wdcdev.sc_dev.dv_xname); 3471 pciide_mapreg_dma(sc, pa); 3472 printf("\n"); 3473 3474 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3475 WDC_CAPABILITY_MODE; 3476 if (sc->sc_dma_ok) { 3477 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3478 sc->sc_wdcdev.irqack = pciide_irqack; 3479 if (sc->sis_type >= SIS_TYPE_66) 3480 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3481 } 3482 3483 sc->sc_wdcdev.PIO_cap = 4; 3484 sc->sc_wdcdev.DMA_cap = 2; 3485 3486 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3487 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3488 switch(sc->sis_type) { 3489 case SIS_TYPE_NOUDMA: 3490 case SIS_TYPE_66: 3491 case SIS_TYPE_100OLD: 3492 sc->sc_wdcdev.set_modes = sis_setup_channel; 3493 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 3494 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 3495 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 3496 break; 3497 case SIS_TYPE_100NEW: 3498 case SIS_TYPE_133OLD: 3499 sc->sc_wdcdev.set_modes = sis_setup_channel; 3500 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 3501 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 3502 break; 3503 case SIS_TYPE_133NEW: 3504 sc->sc_wdcdev.set_modes = sis96x_setup_channel; 3505 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 3506 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 3507 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 3508 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 3509 break; 3510 } 3511 3512 3513 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3514 cp = &sc->pciide_channels[channel]; 3515 if (pciide_chansetup(sc, channel, interface) == 0) 3516 continue; 3517 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 3518 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 3519 printf("%s: %s channel ignored (disabled)\n", 3520 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3521 continue; 3522 } 3523 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3524 pciide_pci_intr); 3525 if (cp->hw_ok == 0) 3526 continue; 3527 if (pciide_chan_candisable(cp)) { 3528 if (channel == 0) 3529 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 3530 else 3531 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 3532 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 3533 sis_ctr0); 3534 } 3535 pciide_map_compat_intr(pa, cp, channel, interface); 3536 if (cp->hw_ok == 0) 3537 continue; 3538 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 3539 } 3540 } 3541 3542 void 3543 sis96x_setup_channel(chp) 3544 struct channel_softc *chp; 3545 { 3546 struct ata_drive_datas *drvp; 3547 int drive; 3548 u_int32_t sis_tim; 3549 u_int32_t idedma_ctl; 3550 int regtim; 3551 struct pciide_channel *cp = (struct pciide_channel*)chp; 3552 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3553 3554 sis_tim = 0; 3555 idedma_ctl = 0; 3556 /* setup DMA if needed */ 3557 pciide_channel_dma_setup(cp); 3558 3559 for (drive = 0; drive < 2; drive++) { 3560 regtim = SIS_TIM133( 3561 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 3562 chp->channel, drive); 3563 drvp = &chp->ch_drive[drive]; 3564 /* If no drive, skip */ 3565 if ((drvp->drive_flags & DRIVE) == 0) 3566 continue; 3567 /* add timing values, setup DMA if needed */ 3568 if (drvp->drive_flags & DRIVE_UDMA) { 3569 /* use Ultra/DMA */ 3570 drvp->drive_flags &= ~DRIVE_DMA; 3571 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3572 SIS96x_REG_CBL(chp->channel)) & SIS96x_REG_CBL_33) { 3573 if (drvp->UDMA_mode > 2) 3574 drvp->UDMA_mode = 2; 3575 } 3576 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 3577 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3578 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3579 } else if (drvp->drive_flags & DRIVE_DMA) { 3580 /* 3581 * use Multiword DMA 3582 * Timings will be used for both PIO and DMA, 3583 * so adjust DMA mode if needed 3584 */ 3585 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3586 drvp->PIO_mode = drvp->DMA_mode + 2; 3587 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3588 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3589 drvp->PIO_mode - 2 : 0; 3590 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 3591 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3592 } else { 3593 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3594 } 3595 WDCDEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 3596 "channel %d drive %d: 0x%x (reg 0x%x)\n", 3597 chp->channel, drive, sis_tim, regtim), DEBUG_PROBE); 3598 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 3599 } 3600 if (idedma_ctl != 0) { 3601 /* Add software bits in status register */ 3602 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3603 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3604 idedma_ctl); 3605 } 3606 pciide_print_modes(cp); 3607 } 3608 3609 void 3610 sis_setup_channel(chp) 3611 struct channel_softc *chp; 3612 { 3613 struct ata_drive_datas *drvp; 3614 int drive; 3615 u_int32_t sis_tim; 3616 u_int32_t idedma_ctl; 3617 struct pciide_channel *cp = (struct pciide_channel*)chp; 3618 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3619 3620 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 3621 "channel %d 0x%x\n", chp->channel, 3622 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 3623 DEBUG_PROBE); 3624 sis_tim = 0; 3625 idedma_ctl = 0; 3626 /* setup DMA if needed */ 3627 pciide_channel_dma_setup(cp); 3628 3629 for (drive = 0; drive < 2; drive++) { 3630 drvp = &chp->ch_drive[drive]; 3631 /* If no drive, skip */ 3632 if ((drvp->drive_flags & DRIVE) == 0) 3633 continue; 3634 /* add timing values, setup DMA if needed */ 3635 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3636 (drvp->drive_flags & DRIVE_UDMA) == 0) 3637 goto pio; 3638 3639 if (drvp->drive_flags & DRIVE_UDMA) { 3640 /* use Ultra/DMA */ 3641 drvp->drive_flags &= ~DRIVE_DMA; 3642 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3643 SIS_REG_CBL) & SIS_REG_CBL_33(chp->channel)) { 3644 if (drvp->UDMA_mode > 2) 3645 drvp->UDMA_mode = 2; 3646 } 3647 switch (sc->sis_type) { 3648 case SIS_TYPE_66: 3649 case SIS_TYPE_100OLD: 3650 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 3651 SIS_TIM66_UDMA_TIME_OFF(drive); 3652 break; 3653 case SIS_TYPE_100NEW: 3654 sis_tim |= 3655 sis_udma100new_tim[drvp->UDMA_mode] << 3656 SIS_TIM100_UDMA_TIME_OFF(drive); 3657 case SIS_TYPE_133OLD: 3658 sis_tim |= 3659 sis_udma133old_tim[drvp->UDMA_mode] << 3660 SIS_TIM100_UDMA_TIME_OFF(drive); 3661 break; 3662 default: 3663 printf("unknown SiS IDE type %d\n", 3664 sc->sis_type); 3665 } 3666 } else { 3667 /* 3668 * use Multiword DMA 3669 * Timings will be used for both PIO and DMA, 3670 * so adjust DMA mode if needed 3671 */ 3672 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3673 drvp->PIO_mode = drvp->DMA_mode + 2; 3674 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3675 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3676 drvp->PIO_mode - 2 : 0; 3677 if (drvp->DMA_mode == 0) 3678 drvp->PIO_mode = 0; 3679 } 3680 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3681 pio: switch (sc->sis_type) { 3682 case SIS_TYPE_NOUDMA: 3683 case SIS_TYPE_66: 3684 case SIS_TYPE_100OLD: 3685 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3686 SIS_TIM66_ACT_OFF(drive); 3687 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3688 SIS_TIM66_REC_OFF(drive); 3689 break; 3690 case SIS_TYPE_100NEW: 3691 case SIS_TYPE_133OLD: 3692 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3693 SIS_TIM100_ACT_OFF(drive); 3694 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3695 SIS_TIM100_REC_OFF(drive); 3696 break; 3697 default: 3698 printf("unknown SiS IDE type %d\n", 3699 sc->sis_type); 3700 } 3701 } 3702 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 3703 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 3704 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 3705 if (idedma_ctl != 0) { 3706 /* Add software bits in status register */ 3707 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3708 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3709 idedma_ctl); 3710 } 3711 pciide_print_modes(cp); 3712 } 3713 3714 void 3715 acer_chip_map(sc, pa) 3716 struct pciide_softc *sc; 3717 struct pci_attach_args *pa; 3718 { 3719 struct pciide_channel *cp; 3720 int channel; 3721 pcireg_t cr, interface; 3722 bus_size_t cmdsize, ctlsize; 3723 pcireg_t rev = PCI_REVISION(pa->pa_class); 3724 3725 if (pciide_chipen(sc, pa) == 0) 3726 return; 3727 printf("%s: bus-master DMA support present", 3728 sc->sc_wdcdev.sc_dev.dv_xname); 3729 pciide_mapreg_dma(sc, pa); 3730 printf("\n"); 3731 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3732 WDC_CAPABILITY_MODE; 3733 if (sc->sc_dma_ok) { 3734 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3735 if (rev >= 0x20) { 3736 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3737 if (rev >= 0xC4) 3738 sc->sc_wdcdev.UDMA_cap = 5; 3739 else if (rev >= 0xC2) 3740 sc->sc_wdcdev.UDMA_cap = 4; 3741 else 3742 sc->sc_wdcdev.UDMA_cap = 2; 3743 } 3744 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3745 sc->sc_wdcdev.irqack = pciide_irqack; 3746 } 3747 3748 sc->sc_wdcdev.PIO_cap = 4; 3749 sc->sc_wdcdev.DMA_cap = 2; 3750 sc->sc_wdcdev.set_modes = acer_setup_channel; 3751 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3752 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3753 3754 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3755 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3756 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3757 3758 /* Enable "microsoft register bits" R/W. */ 3759 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3760 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3761 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3762 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3763 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3764 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3765 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3766 ~ACER_CHANSTATUSREGS_RO); 3767 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3768 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3769 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3770 /* Don't use cr, re-read the real register content instead */ 3771 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3772 PCI_CLASS_REG)); 3773 3774 /* From linux: enable "Cable Detection" */ 3775 if (rev >= 0xC2) { 3776 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3777 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3778 | ACER_0x4B_CDETECT); 3779 } 3780 3781 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3782 cp = &sc->pciide_channels[channel]; 3783 if (pciide_chansetup(sc, channel, interface) == 0) 3784 continue; 3785 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3786 printf("%s: %s channel ignored (disabled)\n", 3787 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3788 continue; 3789 } 3790 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3791 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3792 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3793 if (cp->hw_ok == 0) 3794 continue; 3795 if (pciide_chan_candisable(cp)) { 3796 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 3797 pci_conf_write(sc->sc_pc, sc->sc_tag, 3798 PCI_CLASS_REG, cr); 3799 } 3800 pciide_map_compat_intr(pa, cp, channel, interface); 3801 acer_setup_channel(&cp->wdc_channel); 3802 } 3803 } 3804 3805 void 3806 acer_setup_channel(chp) 3807 struct channel_softc *chp; 3808 { 3809 struct ata_drive_datas *drvp; 3810 int drive; 3811 u_int32_t acer_fifo_udma; 3812 u_int32_t idedma_ctl; 3813 struct pciide_channel *cp = (struct pciide_channel*)chp; 3814 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3815 3816 idedma_ctl = 0; 3817 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3818 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3819 acer_fifo_udma), DEBUG_PROBE); 3820 /* setup DMA if needed */ 3821 pciide_channel_dma_setup(cp); 3822 3823 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3824 DRIVE_UDMA) { /* check 80 pins cable */ 3825 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3826 ACER_0x4A_80PIN(chp->channel)) { 3827 if (chp->ch_drive[0].UDMA_mode > 2) 3828 chp->ch_drive[0].UDMA_mode = 2; 3829 if (chp->ch_drive[1].UDMA_mode > 2) 3830 chp->ch_drive[1].UDMA_mode = 2; 3831 } 3832 } 3833 3834 for (drive = 0; drive < 2; drive++) { 3835 drvp = &chp->ch_drive[drive]; 3836 /* If no drive, skip */ 3837 if ((drvp->drive_flags & DRIVE) == 0) 3838 continue; 3839 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3840 "channel %d drive %d 0x%x\n", chp->channel, drive, 3841 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3842 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3843 /* clear FIFO/DMA mode */ 3844 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3845 ACER_UDMA_EN(chp->channel, drive) | 3846 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3847 3848 /* add timing values, setup DMA if needed */ 3849 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3850 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3851 acer_fifo_udma |= 3852 ACER_FTH_OPL(chp->channel, drive, 0x1); 3853 goto pio; 3854 } 3855 3856 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3857 if (drvp->drive_flags & DRIVE_UDMA) { 3858 /* use Ultra/DMA */ 3859 drvp->drive_flags &= ~DRIVE_DMA; 3860 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3861 acer_fifo_udma |= 3862 ACER_UDMA_TIM(chp->channel, drive, 3863 acer_udma[drvp->UDMA_mode]); 3864 /* XXX disable if one drive < UDMA3 ? */ 3865 if (drvp->UDMA_mode >= 3) { 3866 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3867 ACER_0x4B, 3868 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3869 ACER_0x4B) | ACER_0x4B_UDMA66); 3870 } 3871 } else { 3872 /* 3873 * use Multiword DMA 3874 * Timings will be used for both PIO and DMA, 3875 * so adjust DMA mode if needed 3876 */ 3877 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3878 drvp->PIO_mode = drvp->DMA_mode + 2; 3879 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3880 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3881 drvp->PIO_mode - 2 : 0; 3882 if (drvp->DMA_mode == 0) 3883 drvp->PIO_mode = 0; 3884 } 3885 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3886 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3887 ACER_IDETIM(chp->channel, drive), 3888 acer_pio[drvp->PIO_mode]); 3889 } 3890 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3891 acer_fifo_udma), DEBUG_PROBE); 3892 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3893 if (idedma_ctl != 0) { 3894 /* Add software bits in status register */ 3895 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3896 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3897 idedma_ctl); 3898 } 3899 pciide_print_modes(cp); 3900 } 3901 3902 int 3903 acer_pci_intr(arg) 3904 void *arg; 3905 { 3906 struct pciide_softc *sc = arg; 3907 struct pciide_channel *cp; 3908 struct channel_softc *wdc_cp; 3909 int i, rv, crv; 3910 u_int32_t chids; 3911 3912 rv = 0; 3913 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3914 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3915 cp = &sc->pciide_channels[i]; 3916 wdc_cp = &cp->wdc_channel; 3917 /* If a compat channel skip. */ 3918 if (cp->compat) 3919 continue; 3920 if (chids & ACER_CHIDS_INT(i)) { 3921 crv = wdcintr(wdc_cp); 3922 if (crv == 0) 3923 printf("%s:%d: bogus intr\n", 3924 sc->sc_wdcdev.sc_dev.dv_xname, i); 3925 else 3926 rv = 1; 3927 } 3928 } 3929 return rv; 3930 } 3931 3932 void 3933 hpt_chip_map(sc, pa) 3934 struct pciide_softc *sc; 3935 struct pci_attach_args *pa; 3936 { 3937 struct pciide_channel *cp; 3938 int i, compatchan, revision; 3939 pcireg_t interface; 3940 bus_size_t cmdsize, ctlsize; 3941 3942 if (pciide_chipen(sc, pa) == 0) 3943 return; 3944 revision = PCI_REVISION(pa->pa_class); 3945 printf(": Triones/Highpoint "); 3946 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3947 printf("HPT374 IDE Controller\n"); 3948 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372) 3949 printf("HPT372 IDE Controller\n"); 3950 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 3951 if (revision == HPT372_REV) 3952 printf("HPT372 IDE Controller\n"); 3953 else if (revision == HPT370_REV) 3954 printf("HPT370 IDE Controller\n"); 3955 else if (revision == HPT370A_REV) 3956 printf("HPT370A IDE Controller\n"); 3957 else if (revision == HPT366_REV) 3958 printf("HPT366 IDE Controller\n"); 3959 else 3960 printf("unknown HPT IDE controller rev %d\n", revision); 3961 } else 3962 printf("unknown HPT IDE controller 0x%x\n", 3963 sc->sc_pp->ide_product); 3964 3965 /* 3966 * when the chip is in native mode it identifies itself as a 3967 * 'misc mass storage'. Fake interface in this case. 3968 */ 3969 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3970 interface = PCI_INTERFACE(pa->pa_class); 3971 } else { 3972 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3973 PCIIDE_INTERFACE_PCI(0); 3974 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3975 (revision == HPT370_REV || revision == HPT370A_REV || 3976 revision == HPT372_REV)) || 3977 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3978 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3979 interface |= PCIIDE_INTERFACE_PCI(1); 3980 } 3981 3982 printf("%s: bus-master DMA support present", 3983 sc->sc_wdcdev.sc_dev.dv_xname); 3984 pciide_mapreg_dma(sc, pa); 3985 printf("\n"); 3986 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3987 WDC_CAPABILITY_MODE; 3988 if (sc->sc_dma_ok) { 3989 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3990 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3991 sc->sc_wdcdev.irqack = pciide_irqack; 3992 } 3993 sc->sc_wdcdev.PIO_cap = 4; 3994 sc->sc_wdcdev.DMA_cap = 2; 3995 3996 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3997 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3998 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3999 revision == HPT366_REV) { 4000 sc->sc_wdcdev.UDMA_cap = 4; 4001 /* 4002 * The 366 has 2 PCI IDE functions, one for primary and one 4003 * for secondary. So we need to call pciide_mapregs_compat() 4004 * with the real channel 4005 */ 4006 if (pa->pa_function == 0) { 4007 compatchan = 0; 4008 } else if (pa->pa_function == 1) { 4009 compatchan = 1; 4010 } else { 4011 printf("%s: unexpected PCI function %d\n", 4012 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 4013 return; 4014 } 4015 sc->sc_wdcdev.nchannels = 1; 4016 } else { 4017 sc->sc_wdcdev.nchannels = 2; 4018 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 4019 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 4020 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 4021 revision == HPT372_REV)) 4022 sc->sc_wdcdev.UDMA_cap = 6; 4023 else 4024 sc->sc_wdcdev.UDMA_cap = 5; 4025 } 4026 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4027 cp = &sc->pciide_channels[i]; 4028 if (sc->sc_wdcdev.nchannels > 1) { 4029 compatchan = i; 4030 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 4031 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 4032 printf("%s: %s channel ignored (disabled)\n", 4033 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4034 continue; 4035 } 4036 } 4037 if (pciide_chansetup(sc, i, interface) == 0) 4038 continue; 4039 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4040 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4041 &ctlsize, hpt_pci_intr); 4042 } else { 4043 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 4044 &cmdsize, &ctlsize); 4045 } 4046 if (cp->hw_ok == 0) 4047 return; 4048 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4049 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4050 wdcattach(&cp->wdc_channel); 4051 hpt_setup_channel(&cp->wdc_channel); 4052 } 4053 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 4054 (revision == HPT370_REV || revision == HPT370A_REV || 4055 revision == HPT372_REV)) || 4056 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 4057 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 4058 /* 4059 * HPT370_REV and highter has a bit to disable interrupts, 4060 * make sure to clear it 4061 */ 4062 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 4063 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 4064 ~HPT_CSEL_IRQDIS); 4065 } 4066 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 4067 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 4068 revision == HPT372_REV ) || 4069 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 4070 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 4071 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 4072 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 4073 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 4074 return; 4075 } 4076 4077 void 4078 hpt_setup_channel(chp) 4079 struct channel_softc *chp; 4080 { 4081 struct ata_drive_datas *drvp; 4082 int drive; 4083 int cable; 4084 u_int32_t before, after; 4085 u_int32_t idedma_ctl; 4086 struct pciide_channel *cp = (struct pciide_channel*)chp; 4087 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4088 int revision = 4089 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 4090 4091 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 4092 4093 /* setup DMA if needed */ 4094 pciide_channel_dma_setup(cp); 4095 4096 idedma_ctl = 0; 4097 4098 /* Per drive settings */ 4099 for (drive = 0; drive < 2; drive++) { 4100 drvp = &chp->ch_drive[drive]; 4101 /* If no drive, skip */ 4102 if ((drvp->drive_flags & DRIVE) == 0) 4103 continue; 4104 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 4105 HPT_IDETIM(chp->channel, drive)); 4106 4107 /* add timing values, setup DMA if needed */ 4108 if (drvp->drive_flags & DRIVE_UDMA) { 4109 /* use Ultra/DMA */ 4110 drvp->drive_flags &= ~DRIVE_DMA; 4111 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 4112 drvp->UDMA_mode > 2) 4113 drvp->UDMA_mode = 2; 4114 switch (sc->sc_pp->ide_product) { 4115 case PCI_PRODUCT_TRIONES_HPT374: 4116 after = hpt374_udma[drvp->UDMA_mode]; 4117 break; 4118 case PCI_PRODUCT_TRIONES_HPT372: 4119 after = hpt372_udma[drvp->UDMA_mode]; 4120 break; 4121 case PCI_PRODUCT_TRIONES_HPT366: 4122 default: 4123 switch(revision) { 4124 case HPT372_REV: 4125 after = hpt372_udma[drvp->UDMA_mode]; 4126 break; 4127 case HPT370_REV: 4128 case HPT370A_REV: 4129 after = hpt370_udma[drvp->UDMA_mode]; 4130 break; 4131 case HPT366_REV: 4132 default: 4133 after = hpt366_udma[drvp->UDMA_mode]; 4134 break; 4135 } 4136 } 4137 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4138 } else if (drvp->drive_flags & DRIVE_DMA) { 4139 /* 4140 * use Multiword DMA. 4141 * Timings will be used for both PIO and DMA, so adjust 4142 * DMA mode if needed 4143 */ 4144 if (drvp->PIO_mode >= 3 && 4145 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 4146 drvp->DMA_mode = drvp->PIO_mode - 2; 4147 } 4148 switch (sc->sc_pp->ide_product) { 4149 case PCI_PRODUCT_TRIONES_HPT374: 4150 after = hpt374_dma[drvp->DMA_mode]; 4151 break; 4152 case PCI_PRODUCT_TRIONES_HPT372: 4153 after = hpt372_dma[drvp->DMA_mode]; 4154 break; 4155 case PCI_PRODUCT_TRIONES_HPT366: 4156 default: 4157 switch(revision) { 4158 case HPT372_REV: 4159 after = hpt372_dma[drvp->DMA_mode]; 4160 break; 4161 case HPT370_REV: 4162 case HPT370A_REV: 4163 after = hpt370_dma[drvp->DMA_mode]; 4164 break; 4165 case HPT366_REV: 4166 default: 4167 after = hpt366_dma[drvp->DMA_mode]; 4168 break; 4169 } 4170 } 4171 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4172 } else { 4173 /* PIO only */ 4174 switch (sc->sc_pp->ide_product) { 4175 case PCI_PRODUCT_TRIONES_HPT374: 4176 after = hpt374_pio[drvp->PIO_mode]; 4177 break; 4178 case PCI_PRODUCT_TRIONES_HPT372: 4179 after = hpt372_pio[drvp->PIO_mode]; 4180 break; 4181 case PCI_PRODUCT_TRIONES_HPT366: 4182 default: 4183 switch(revision) { 4184 case HPT372_REV: 4185 after = hpt372_pio[drvp->PIO_mode]; 4186 break; 4187 case HPT370_REV: 4188 case HPT370A_REV: 4189 after = hpt370_pio[drvp->PIO_mode]; 4190 break; 4191 case HPT366_REV: 4192 default: 4193 after = hpt366_pio[drvp->PIO_mode]; 4194 break; 4195 } 4196 } 4197 } 4198 pci_conf_write(sc->sc_pc, sc->sc_tag, 4199 HPT_IDETIM(chp->channel, drive), after); 4200 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 4201 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 4202 after, before), DEBUG_PROBE); 4203 } 4204 if (idedma_ctl != 0) { 4205 /* Add software bits in status register */ 4206 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4207 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4208 idedma_ctl); 4209 } 4210 pciide_print_modes(cp); 4211 } 4212 4213 int 4214 hpt_pci_intr(arg) 4215 void *arg; 4216 { 4217 struct pciide_softc *sc = arg; 4218 struct pciide_channel *cp; 4219 struct channel_softc *wdc_cp; 4220 int rv = 0; 4221 int dmastat, i, crv; 4222 4223 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4224 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4225 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4226 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4227 IDEDMA_CTL_INTR) 4228 continue; 4229 cp = &sc->pciide_channels[i]; 4230 wdc_cp = &cp->wdc_channel; 4231 crv = wdcintr(wdc_cp); 4232 if (crv == 0) { 4233 printf("%s:%d: bogus intr\n", 4234 sc->sc_wdcdev.sc_dev.dv_xname, i); 4235 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4236 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4237 } else 4238 rv = 1; 4239 } 4240 return rv; 4241 } 4242 4243 4244 /* Macros to test product */ 4245 #define PDC_IS_262(sc) \ 4246 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 4247 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 4248 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 4249 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4250 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4251 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4252 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4253 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4254 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4255 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4256 #define PDC_IS_265(sc) \ 4257 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 4258 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 4259 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4260 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4261 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4262 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4263 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4264 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4265 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4266 #define PDC_IS_268(sc) \ 4267 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4268 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4269 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4270 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4271 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4272 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4273 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4274 #define PDC_IS_276(sc) \ 4275 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4276 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4277 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4278 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4279 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4280 4281 void 4282 pdc202xx_chip_map(sc, pa) 4283 struct pciide_softc *sc; 4284 struct pci_attach_args *pa; 4285 { 4286 struct pciide_channel *cp; 4287 int channel; 4288 pcireg_t interface, st, mode; 4289 bus_size_t cmdsize, ctlsize; 4290 4291 if (!PDC_IS_268(sc)) { 4292 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4293 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 4294 st), DEBUG_PROBE); 4295 } 4296 if (pciide_chipen(sc, pa) == 0) 4297 return; 4298 4299 /* turn off RAID mode */ 4300 if (!PDC_IS_268(sc)) 4301 st &= ~PDC2xx_STATE_IDERAID; 4302 4303 /* 4304 * can't rely on the PCI_CLASS_REG content if the chip was in raid 4305 * mode. We have to fake interface 4306 */ 4307 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 4308 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 4309 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4310 4311 printf("%s: bus-master DMA support present", 4312 sc->sc_wdcdev.sc_dev.dv_xname); 4313 pciide_mapreg_dma(sc, pa); 4314 printf("\n"); 4315 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4316 WDC_CAPABILITY_MODE; 4317 if (sc->sc_dma_ok) { 4318 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4319 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4320 sc->sc_wdcdev.irqack = pciide_irqack; 4321 } 4322 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 4323 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 4324 sc->sc_wdcdev.cap |= WDC_CAPABILITY_RAID; 4325 sc->sc_wdcdev.PIO_cap = 4; 4326 sc->sc_wdcdev.DMA_cap = 2; 4327 if (PDC_IS_276(sc)) 4328 sc->sc_wdcdev.UDMA_cap = 6; 4329 else if (PDC_IS_265(sc)) 4330 sc->sc_wdcdev.UDMA_cap = 5; 4331 else if (PDC_IS_262(sc)) 4332 sc->sc_wdcdev.UDMA_cap = 4; 4333 else 4334 sc->sc_wdcdev.UDMA_cap = 2; 4335 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 4336 pdc20268_setup_channel : pdc202xx_setup_channel; 4337 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4338 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4339 4340 if (!PDC_IS_268(sc)) { 4341 /* setup failsafe defaults */ 4342 mode = 0; 4343 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 4344 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 4345 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 4346 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 4347 for (channel = 0; 4348 channel < sc->sc_wdcdev.nchannels; 4349 channel++) { 4350 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 4351 "drive 0 initial timings 0x%x, now 0x%x\n", 4352 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 4353 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 4354 DEBUG_PROBE); 4355 pci_conf_write(sc->sc_pc, sc->sc_tag, 4356 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 4357 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 4358 "drive 1 initial timings 0x%x, now 0x%x\n", 4359 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 4360 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 4361 pci_conf_write(sc->sc_pc, sc->sc_tag, 4362 PDC2xx_TIM(channel, 1), mode); 4363 } 4364 4365 mode = PDC2xx_SCR_DMA; 4366 if (PDC_IS_262(sc)) { 4367 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 4368 } else { 4369 /* the BIOS set it up this way */ 4370 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 4371 } 4372 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 4373 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 4374 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 4375 "now 0x%x\n", 4376 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4377 PDC2xx_SCR), 4378 mode), DEBUG_PROBE); 4379 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4380 PDC2xx_SCR, mode); 4381 4382 /* controller initial state register is OK even without BIOS */ 4383 /* Set DMA mode to IDE DMA compatibility */ 4384 mode = 4385 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 4386 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 4387 DEBUG_PROBE); 4388 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 4389 mode | 0x1); 4390 mode = 4391 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 4392 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 4393 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 4394 mode | 0x1); 4395 } 4396 4397 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4398 cp = &sc->pciide_channels[channel]; 4399 if (pciide_chansetup(sc, channel, interface) == 0) 4400 continue; 4401 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 4402 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 4403 printf("%s: %s channel ignored (disabled)\n", 4404 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4405 continue; 4406 } 4407 if (PDC_IS_265(sc)) 4408 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4409 pdc20265_pci_intr); 4410 else 4411 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4412 pdc202xx_pci_intr); 4413 if (cp->hw_ok == 0) 4414 continue; 4415 if (!PDC_IS_268(sc) && pciide_chan_candisable(cp)) 4416 st &= ~(PDC_IS_262(sc) ? 4417 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 4418 pciide_map_compat_intr(pa, cp, channel, interface); 4419 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 4420 } 4421 if (!PDC_IS_268(sc)) { 4422 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 4423 "0x%x\n", st), DEBUG_PROBE); 4424 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 4425 } 4426 return; 4427 } 4428 4429 void 4430 pdc202xx_setup_channel(chp) 4431 struct channel_softc *chp; 4432 { 4433 struct ata_drive_datas *drvp; 4434 int drive; 4435 pcireg_t mode, st; 4436 u_int32_t idedma_ctl, scr, atapi; 4437 struct pciide_channel *cp = (struct pciide_channel*)chp; 4438 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4439 int channel = chp->channel; 4440 4441 /* setup DMA if needed */ 4442 pciide_channel_dma_setup(cp); 4443 4444 idedma_ctl = 0; 4445 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 4446 sc->sc_wdcdev.sc_dev.dv_xname, 4447 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 4448 DEBUG_PROBE); 4449 4450 /* Per channel settings */ 4451 if (PDC_IS_262(sc)) { 4452 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4453 PDC262_U66); 4454 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4455 /* Trim UDMA mode */ 4456 if ((st & PDC262_STATE_80P(channel)) != 0 || 4457 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4458 chp->ch_drive[0].UDMA_mode <= 2) || 4459 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4460 chp->ch_drive[1].UDMA_mode <= 2)) { 4461 if (chp->ch_drive[0].UDMA_mode > 2) 4462 chp->ch_drive[0].UDMA_mode = 2; 4463 if (chp->ch_drive[1].UDMA_mode > 2) 4464 chp->ch_drive[1].UDMA_mode = 2; 4465 } 4466 /* Set U66 if needed */ 4467 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4468 chp->ch_drive[0].UDMA_mode > 2) || 4469 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4470 chp->ch_drive[1].UDMA_mode > 2)) 4471 scr |= PDC262_U66_EN(channel); 4472 else 4473 scr &= ~PDC262_U66_EN(channel); 4474 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4475 PDC262_U66, scr); 4476 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 4477 sc->sc_wdcdev.sc_dev.dv_xname, channel, 4478 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4479 PDC262_ATAPI(channel))), DEBUG_PROBE); 4480 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 4481 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 4482 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4483 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4484 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 4485 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4486 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4487 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 4488 atapi = 0; 4489 else 4490 atapi = PDC262_ATAPI_UDMA; 4491 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4492 PDC262_ATAPI(channel), atapi); 4493 } 4494 } 4495 for (drive = 0; drive < 2; drive++) { 4496 drvp = &chp->ch_drive[drive]; 4497 /* If no drive, skip */ 4498 if ((drvp->drive_flags & DRIVE) == 0) 4499 continue; 4500 mode = 0; 4501 if (drvp->drive_flags & DRIVE_UDMA) { 4502 /* use Ultra/DMA */ 4503 drvp->drive_flags &= ~DRIVE_DMA; 4504 mode = PDC2xx_TIM_SET_MB(mode, 4505 pdc2xx_udma_mb[drvp->UDMA_mode]); 4506 mode = PDC2xx_TIM_SET_MC(mode, 4507 pdc2xx_udma_mc[drvp->UDMA_mode]); 4508 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4509 } else if (drvp->drive_flags & DRIVE_DMA) { 4510 mode = PDC2xx_TIM_SET_MB(mode, 4511 pdc2xx_dma_mb[drvp->DMA_mode]); 4512 mode = PDC2xx_TIM_SET_MC(mode, 4513 pdc2xx_dma_mc[drvp->DMA_mode]); 4514 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4515 } else { 4516 mode = PDC2xx_TIM_SET_MB(mode, 4517 pdc2xx_dma_mb[0]); 4518 mode = PDC2xx_TIM_SET_MC(mode, 4519 pdc2xx_dma_mc[0]); 4520 } 4521 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 4522 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 4523 if (drvp->drive_flags & DRIVE_ATA) 4524 mode |= PDC2xx_TIM_PRE; 4525 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 4526 if (drvp->PIO_mode >= 3) { 4527 mode |= PDC2xx_TIM_IORDY; 4528 if (drive == 0) 4529 mode |= PDC2xx_TIM_IORDYp; 4530 } 4531 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 4532 "timings 0x%x\n", 4533 sc->sc_wdcdev.sc_dev.dv_xname, 4534 chp->channel, drive, mode), DEBUG_PROBE); 4535 pci_conf_write(sc->sc_pc, sc->sc_tag, 4536 PDC2xx_TIM(chp->channel, drive), mode); 4537 } 4538 if (idedma_ctl != 0) { 4539 /* Add software bits in status register */ 4540 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4541 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4542 idedma_ctl); 4543 } 4544 pciide_print_modes(cp); 4545 } 4546 4547 void 4548 pdc20268_setup_channel(chp) 4549 struct channel_softc *chp; 4550 { 4551 struct ata_drive_datas *drvp; 4552 int drive; 4553 u_int32_t idedma_ctl; 4554 struct pciide_channel *cp = (struct pciide_channel*)chp; 4555 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4556 int u100; 4557 4558 /* setup DMA if needed */ 4559 pciide_channel_dma_setup(cp); 4560 4561 idedma_ctl = 0; 4562 4563 /* I don't know what this is for, FreeBSD does it ... */ 4564 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4565 IDEDMA_CMD + 0x1, 0x0b); 4566 4567 /* 4568 * I don't know what this is for; FreeBSD checks this ... this is not 4569 * cable type detect. 4570 */ 4571 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4572 IDEDMA_CMD + 0x3) & 0x04) ? 0 : 1; 4573 4574 for (drive = 0; drive < 2; drive++) { 4575 drvp = &chp->ch_drive[drive]; 4576 /* If no drive, skip */ 4577 if ((drvp->drive_flags & DRIVE) == 0) 4578 continue; 4579 if (drvp->drive_flags & DRIVE_UDMA) { 4580 /* use Ultra/DMA */ 4581 drvp->drive_flags &= ~DRIVE_DMA; 4582 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4583 if (drvp->UDMA_mode > 2 && u100 == 0) 4584 drvp->UDMA_mode = 2; 4585 } else if (drvp->drive_flags & DRIVE_DMA) { 4586 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4587 } 4588 } 4589 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 4590 if (idedma_ctl != 0) { 4591 /* Add software bits in status register */ 4592 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4593 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4594 idedma_ctl); 4595 } 4596 pciide_print_modes(cp); 4597 } 4598 4599 int 4600 pdc202xx_pci_intr(arg) 4601 void *arg; 4602 { 4603 struct pciide_softc *sc = arg; 4604 struct pciide_channel *cp; 4605 struct channel_softc *wdc_cp; 4606 int i, rv, crv; 4607 u_int32_t scr; 4608 4609 rv = 0; 4610 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 4611 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4612 cp = &sc->pciide_channels[i]; 4613 wdc_cp = &cp->wdc_channel; 4614 /* If a compat channel skip. */ 4615 if (cp->compat) 4616 continue; 4617 if (scr & PDC2xx_SCR_INT(i)) { 4618 crv = wdcintr(wdc_cp); 4619 if (crv == 0) 4620 printf("%s:%d: bogus intr (reg 0x%x)\n", 4621 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 4622 else 4623 rv = 1; 4624 } 4625 } 4626 return rv; 4627 } 4628 4629 int 4630 pdc20265_pci_intr(arg) 4631 void *arg; 4632 { 4633 struct pciide_softc *sc = arg; 4634 struct pciide_channel *cp; 4635 struct channel_softc *wdc_cp; 4636 int i, rv, crv; 4637 u_int32_t dmastat; 4638 4639 rv = 0; 4640 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4641 cp = &sc->pciide_channels[i]; 4642 wdc_cp = &cp->wdc_channel; 4643 /* If a compat channel skip. */ 4644 if (cp->compat) 4645 continue; 4646 /* 4647 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 4648 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 4649 * So use it instead (requires 2 reg reads instead of 1, 4650 * but we can't do it another way). 4651 */ 4652 dmastat = bus_space_read_1(sc->sc_dma_iot, 4653 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4654 if((dmastat & IDEDMA_CTL_INTR) == 0) 4655 continue; 4656 crv = wdcintr(wdc_cp); 4657 if (crv == 0) 4658 printf("%s:%d: bogus intr\n", 4659 sc->sc_wdcdev.sc_dev.dv_xname, i); 4660 else 4661 rv = 1; 4662 } 4663 return rv; 4664 } 4665 4666 void 4667 opti_chip_map(sc, pa) 4668 struct pciide_softc *sc; 4669 struct pci_attach_args *pa; 4670 { 4671 struct pciide_channel *cp; 4672 bus_size_t cmdsize, ctlsize; 4673 pcireg_t interface; 4674 u_int8_t init_ctrl; 4675 int channel; 4676 4677 if (pciide_chipen(sc, pa) == 0) 4678 return; 4679 printf("%s: bus-master DMA support present", 4680 sc->sc_wdcdev.sc_dev.dv_xname); 4681 4682 /* 4683 * XXXSCW: 4684 * There seem to be a couple of buggy revisions/implementations 4685 * of the OPTi pciide chipset. This kludge seems to fix one of 4686 * the reported problems (PR/11644) but still fails for the 4687 * other (PR/13151), although the latter may be due to other 4688 * issues too... 4689 */ 4690 if (PCI_REVISION(pa->pa_class) <= 0x12) { 4691 printf(" but disabled due to chip rev. <= 0x12"); 4692 sc->sc_dma_ok = 0; 4693 } else 4694 pciide_mapreg_dma(sc, pa); 4695 4696 printf("\n"); 4697 4698 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4699 WDC_CAPABILITY_MODE; 4700 sc->sc_wdcdev.PIO_cap = 4; 4701 if (sc->sc_dma_ok) { 4702 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4703 sc->sc_wdcdev.irqack = pciide_irqack; 4704 sc->sc_wdcdev.DMA_cap = 2; 4705 } 4706 sc->sc_wdcdev.set_modes = opti_setup_channel; 4707 4708 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4709 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4710 4711 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 4712 OPTI_REG_INIT_CONTROL); 4713 4714 interface = PCI_INTERFACE(pa->pa_class); 4715 4716 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4717 cp = &sc->pciide_channels[channel]; 4718 if (pciide_chansetup(sc, channel, interface) == 0) 4719 continue; 4720 if (channel == 1 && 4721 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 4722 printf("%s: %s channel ignored (disabled)\n", 4723 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4724 continue; 4725 } 4726 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4727 pciide_pci_intr); 4728 if (cp->hw_ok == 0) 4729 continue; 4730 pciide_map_compat_intr(pa, cp, channel, interface); 4731 if (cp->hw_ok == 0) 4732 continue; 4733 opti_setup_channel(&cp->wdc_channel); 4734 } 4735 } 4736 4737 void 4738 opti_setup_channel(chp) 4739 struct channel_softc *chp; 4740 { 4741 struct ata_drive_datas *drvp; 4742 struct pciide_channel *cp = (struct pciide_channel*)chp; 4743 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4744 int drive, spd; 4745 int mode[2]; 4746 u_int8_t rv, mr; 4747 4748 /* 4749 * The `Delay' and `Address Setup Time' fields of the 4750 * Miscellaneous Register are always zero initially. 4751 */ 4752 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 4753 mr &= ~(OPTI_MISC_DELAY_MASK | 4754 OPTI_MISC_ADDR_SETUP_MASK | 4755 OPTI_MISC_INDEX_MASK); 4756 4757 /* Prime the control register before setting timing values */ 4758 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 4759 4760 /* Determine the clockrate of the PCIbus the chip is attached to */ 4761 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 4762 spd &= OPTI_STRAP_PCI_SPEED_MASK; 4763 4764 /* setup DMA if needed */ 4765 pciide_channel_dma_setup(cp); 4766 4767 for (drive = 0; drive < 2; drive++) { 4768 drvp = &chp->ch_drive[drive]; 4769 /* If no drive, skip */ 4770 if ((drvp->drive_flags & DRIVE) == 0) { 4771 mode[drive] = -1; 4772 continue; 4773 } 4774 4775 if ((drvp->drive_flags & DRIVE_DMA)) { 4776 /* 4777 * Timings will be used for both PIO and DMA, 4778 * so adjust DMA mode if needed 4779 */ 4780 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 4781 drvp->PIO_mode = drvp->DMA_mode + 2; 4782 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 4783 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 4784 drvp->PIO_mode - 2 : 0; 4785 if (drvp->DMA_mode == 0) 4786 drvp->PIO_mode = 0; 4787 4788 mode[drive] = drvp->DMA_mode + 5; 4789 } else 4790 mode[drive] = drvp->PIO_mode; 4791 4792 if (drive && mode[0] >= 0 && 4793 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 4794 /* 4795 * Can't have two drives using different values 4796 * for `Address Setup Time'. 4797 * Slow down the faster drive to compensate. 4798 */ 4799 int d = (opti_tim_as[spd][mode[0]] > 4800 opti_tim_as[spd][mode[1]]) ? 0 : 1; 4801 4802 mode[d] = mode[1-d]; 4803 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4804 chp->ch_drive[d].DMA_mode = 0; 4805 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 4806 } 4807 } 4808 4809 for (drive = 0; drive < 2; drive++) { 4810 int m; 4811 if ((m = mode[drive]) < 0) 4812 continue; 4813 4814 /* Set the Address Setup Time and select appropriate index */ 4815 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4816 rv |= OPTI_MISC_INDEX(drive); 4817 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4818 4819 /* Set the pulse width and recovery timing parameters */ 4820 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4821 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4822 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4823 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4824 4825 /* Set the Enhanced Mode register appropriately */ 4826 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4827 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4828 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4829 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4830 } 4831 4832 /* Finally, enable the timings */ 4833 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4834 4835 pciide_print_modes(cp); 4836 } 4837 4838 #define ACARD_IS_850(sc) \ 4839 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4840 4841 void 4842 acard_chip_map(sc, pa) 4843 struct pciide_softc *sc; 4844 struct pci_attach_args *pa; 4845 { 4846 struct pciide_channel *cp; 4847 int i; 4848 pcireg_t interface; 4849 bus_size_t cmdsize, ctlsize; 4850 4851 if (pciide_chipen(sc, pa) == 0) 4852 return; 4853 4854 /* 4855 * when the chip is in native mode it identifies itself as a 4856 * 'misc mass storage'. Fake interface in this case. 4857 */ 4858 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4859 interface = PCI_INTERFACE(pa->pa_class); 4860 } else { 4861 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4862 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4863 } 4864 4865 printf("%s: bus-master DMA support present", 4866 sc->sc_wdcdev.sc_dev.dv_xname); 4867 pciide_mapreg_dma(sc, pa); 4868 printf("\n"); 4869 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4870 WDC_CAPABILITY_MODE; 4871 4872 if (sc->sc_dma_ok) { 4873 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4874 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4875 sc->sc_wdcdev.irqack = pciide_irqack; 4876 } 4877 sc->sc_wdcdev.PIO_cap = 4; 4878 sc->sc_wdcdev.DMA_cap = 2; 4879 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4880 4881 sc->sc_wdcdev.set_modes = acard_setup_channel; 4882 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4883 sc->sc_wdcdev.nchannels = 2; 4884 4885 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4886 cp = &sc->pciide_channels[i]; 4887 if (pciide_chansetup(sc, i, interface) == 0) 4888 continue; 4889 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4890 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 4891 &ctlsize, pciide_pci_intr); 4892 } else { 4893 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 4894 &cmdsize, &ctlsize); 4895 } 4896 if (cp->hw_ok == 0) 4897 return; 4898 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 4899 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 4900 wdcattach(&cp->wdc_channel); 4901 acard_setup_channel(&cp->wdc_channel); 4902 } 4903 if (!ACARD_IS_850(sc)) { 4904 u_int32_t reg; 4905 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4906 reg &= ~ATP860_CTRL_INT; 4907 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4908 } 4909 } 4910 4911 void 4912 acard_setup_channel(chp) 4913 struct channel_softc *chp; 4914 { 4915 struct ata_drive_datas *drvp; 4916 struct pciide_channel *cp = (struct pciide_channel*)chp; 4917 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4918 int channel = chp->channel; 4919 int drive; 4920 u_int32_t idetime, udma_mode; 4921 u_int32_t idedma_ctl; 4922 4923 /* setup DMA if needed */ 4924 pciide_channel_dma_setup(cp); 4925 4926 if (ACARD_IS_850(sc)) { 4927 idetime = 0; 4928 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4929 udma_mode &= ~ATP850_UDMA_MASK(channel); 4930 } else { 4931 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4932 idetime &= ~ATP860_SETTIME_MASK(channel); 4933 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4934 udma_mode &= ~ATP860_UDMA_MASK(channel); 4935 4936 /* check 80 pins cable */ 4937 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4938 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4939 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4940 & ATP860_CTRL_80P(chp->channel)) { 4941 if (chp->ch_drive[0].UDMA_mode > 2) 4942 chp->ch_drive[0].UDMA_mode = 2; 4943 if (chp->ch_drive[1].UDMA_mode > 2) 4944 chp->ch_drive[1].UDMA_mode = 2; 4945 } 4946 } 4947 } 4948 4949 idedma_ctl = 0; 4950 4951 /* Per drive settings */ 4952 for (drive = 0; drive < 2; drive++) { 4953 drvp = &chp->ch_drive[drive]; 4954 /* If no drive, skip */ 4955 if ((drvp->drive_flags & DRIVE) == 0) 4956 continue; 4957 /* add timing values, setup DMA if needed */ 4958 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4959 (drvp->drive_flags & DRIVE_UDMA)) { 4960 /* use Ultra/DMA */ 4961 if (ACARD_IS_850(sc)) { 4962 idetime |= ATP850_SETTIME(drive, 4963 acard_act_udma[drvp->UDMA_mode], 4964 acard_rec_udma[drvp->UDMA_mode]); 4965 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4966 acard_udma_conf[drvp->UDMA_mode]); 4967 } else { 4968 idetime |= ATP860_SETTIME(channel, drive, 4969 acard_act_udma[drvp->UDMA_mode], 4970 acard_rec_udma[drvp->UDMA_mode]); 4971 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4972 acard_udma_conf[drvp->UDMA_mode]); 4973 } 4974 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4975 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4976 (drvp->drive_flags & DRIVE_DMA)) { 4977 /* use Multiword DMA */ 4978 drvp->drive_flags &= ~DRIVE_UDMA; 4979 if (ACARD_IS_850(sc)) { 4980 idetime |= ATP850_SETTIME(drive, 4981 acard_act_dma[drvp->DMA_mode], 4982 acard_rec_dma[drvp->DMA_mode]); 4983 } else { 4984 idetime |= ATP860_SETTIME(channel, drive, 4985 acard_act_dma[drvp->DMA_mode], 4986 acard_rec_dma[drvp->DMA_mode]); 4987 } 4988 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4989 } else { 4990 /* PIO only */ 4991 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4992 if (ACARD_IS_850(sc)) { 4993 idetime |= ATP850_SETTIME(drive, 4994 acard_act_pio[drvp->PIO_mode], 4995 acard_rec_pio[drvp->PIO_mode]); 4996 } else { 4997 idetime |= ATP860_SETTIME(channel, drive, 4998 acard_act_pio[drvp->PIO_mode], 4999 acard_rec_pio[drvp->PIO_mode]); 5000 } 5001 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 5002 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 5003 | ATP8x0_CTRL_EN(channel)); 5004 } 5005 } 5006 5007 if (idedma_ctl != 0) { 5008 /* Add software bits in status register */ 5009 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5010 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 5011 } 5012 pciide_print_modes(cp); 5013 5014 if (ACARD_IS_850(sc)) { 5015 pci_conf_write(sc->sc_pc, sc->sc_tag, 5016 ATP850_IDETIME(channel), idetime); 5017 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 5018 } else { 5019 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 5020 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 5021 } 5022 } 5023 5024 int 5025 acard_pci_intr(arg) 5026 void *arg; 5027 { 5028 struct pciide_softc *sc = arg; 5029 struct pciide_channel *cp; 5030 struct channel_softc *wdc_cp; 5031 int rv = 0; 5032 int dmastat, i, crv; 5033 5034 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5035 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5036 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 5037 if ((dmastat & IDEDMA_CTL_INTR) == 0) 5038 continue; 5039 cp = &sc->pciide_channels[i]; 5040 wdc_cp = &cp->wdc_channel; 5041 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 5042 (void)wdcintr(wdc_cp); 5043 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5044 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 5045 continue; 5046 } 5047 crv = wdcintr(wdc_cp); 5048 if (crv == 0) 5049 printf("%s:%d: bogus intr\n", 5050 sc->sc_wdcdev.sc_dev.dv_xname, i); 5051 else if (crv == 1) 5052 rv = 1; 5053 else if (rv == 0) 5054 rv = crv; 5055 } 5056 return rv; 5057 } 5058 5059 static int 5060 sl82c105_bugchk(struct pci_attach_args *pa) 5061 { 5062 5063 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 5064 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 5065 return (0); 5066 5067 if (PCI_REVISION(pa->pa_class) <= 0x05) 5068 return (1); 5069 5070 return (0); 5071 } 5072 5073 void 5074 sl82c105_chip_map(sc, pa) 5075 struct pciide_softc *sc; 5076 struct pci_attach_args *pa; 5077 { 5078 struct pciide_channel *cp; 5079 bus_size_t cmdsize, ctlsize; 5080 pcireg_t interface, idecr; 5081 int channel; 5082 5083 if (pciide_chipen(sc, pa) == 0) 5084 return; 5085 5086 printf("%s: bus-master DMA support present", 5087 sc->sc_wdcdev.sc_dev.dv_xname); 5088 5089 /* 5090 * Check to see if we're part of the Winbond 83c553 Southbridge. 5091 * If so, we need to disable DMA on rev. <= 5 of that chip. 5092 */ 5093 if (pci_find_device(pa, sl82c105_bugchk)) { 5094 printf(" but disabled due to 83c553 rev. <= 0x05"); 5095 sc->sc_dma_ok = 0; 5096 } else 5097 pciide_mapreg_dma(sc, pa); 5098 printf("\n"); 5099 5100 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 5101 WDC_CAPABILITY_MODE; 5102 sc->sc_wdcdev.PIO_cap = 4; 5103 if (sc->sc_dma_ok) { 5104 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 5105 sc->sc_wdcdev.irqack = pciide_irqack; 5106 sc->sc_wdcdev.DMA_cap = 2; 5107 } 5108 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 5109 5110 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5111 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5112 5113 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 5114 5115 interface = PCI_INTERFACE(pa->pa_class); 5116 5117 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5118 cp = &sc->pciide_channels[channel]; 5119 if (pciide_chansetup(sc, channel, interface) == 0) 5120 continue; 5121 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 5122 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 5123 printf("%s: %s channel ignored (disabled)\n", 5124 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 5125 continue; 5126 } 5127 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5128 pciide_pci_intr); 5129 if (cp->hw_ok == 0) 5130 continue; 5131 pciide_map_compat_intr(pa, cp, channel, interface); 5132 if (cp->hw_ok == 0) 5133 continue; 5134 sl82c105_setup_channel(&cp->wdc_channel); 5135 } 5136 } 5137 5138 void 5139 sl82c105_setup_channel(chp) 5140 struct channel_softc *chp; 5141 { 5142 struct ata_drive_datas *drvp; 5143 struct pciide_channel *cp = (struct pciide_channel*)chp; 5144 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5145 int pxdx_reg, drive; 5146 pcireg_t pxdx; 5147 5148 /* Set up DMA if needed. */ 5149 pciide_channel_dma_setup(cp); 5150 5151 for (drive = 0; drive < 2; drive++) { 5152 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 5153 : SYMPH_P1D0CR) + (drive * 4); 5154 5155 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 5156 5157 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 5158 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 5159 5160 drvp = &chp->ch_drive[drive]; 5161 /* If no drive, skip. */ 5162 if ((drvp->drive_flags & DRIVE) == 0) { 5163 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 5164 continue; 5165 } 5166 5167 if (drvp->drive_flags & DRIVE_DMA) { 5168 /* 5169 * Timings will be used for both PIO and DMA, 5170 * so adjust DMA mode if needed. 5171 */ 5172 if (drvp->PIO_mode >= 3) { 5173 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 5174 drvp->DMA_mode = drvp->PIO_mode - 2; 5175 if (drvp->DMA_mode < 1) { 5176 /* 5177 * Can't mix both PIO and DMA. 5178 * Disable DMA. 5179 */ 5180 drvp->drive_flags &= ~DRIVE_DMA; 5181 } 5182 } else { 5183 /* 5184 * Can't mix both PIO and DMA. Disable 5185 * DMA. 5186 */ 5187 drvp->drive_flags &= ~DRIVE_DMA; 5188 } 5189 } 5190 5191 if (drvp->drive_flags & DRIVE_DMA) { 5192 /* Use multi-word DMA. */ 5193 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 5194 PxDx_CMD_ON_SHIFT; 5195 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 5196 } else { 5197 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 5198 PxDx_CMD_ON_SHIFT; 5199 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 5200 } 5201 5202 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 5203 5204 /* ...and set the mode for this drive. */ 5205 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 5206 } 5207 5208 pciide_print_modes(cp); 5209 } 5210 5211 void 5212 serverworks_chip_map(sc, pa) 5213 struct pciide_softc *sc; 5214 struct pci_attach_args *pa; 5215 { 5216 struct pciide_channel *cp; 5217 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 5218 pcitag_t pcib_tag; 5219 int channel; 5220 bus_size_t cmdsize, ctlsize; 5221 5222 if (pciide_chipen(sc, pa) == 0) 5223 return; 5224 5225 printf("%s: bus-master DMA support present", 5226 sc->sc_wdcdev.sc_dev.dv_xname); 5227 pciide_mapreg_dma(sc, pa); 5228 printf("\n"); 5229 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5230 WDC_CAPABILITY_MODE; 5231 5232 if (sc->sc_dma_ok) { 5233 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5234 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5235 sc->sc_wdcdev.irqack = pciide_irqack; 5236 } 5237 sc->sc_wdcdev.PIO_cap = 4; 5238 sc->sc_wdcdev.DMA_cap = 2; 5239 switch (sc->sc_pp->ide_product) { 5240 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 5241 sc->sc_wdcdev.UDMA_cap = 2; 5242 break; 5243 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 5244 if (PCI_REVISION(pa->pa_class) < 0x92) 5245 sc->sc_wdcdev.UDMA_cap = 4; 5246 else 5247 sc->sc_wdcdev.UDMA_cap = 5; 5248 break; 5249 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 5250 sc->sc_wdcdev.UDMA_cap = 5; 5251 break; 5252 } 5253 5254 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 5255 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5256 sc->sc_wdcdev.nchannels = 2; 5257 5258 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5259 cp = &sc->pciide_channels[channel]; 5260 if (pciide_chansetup(sc, channel, interface) == 0) 5261 continue; 5262 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5263 serverworks_pci_intr); 5264 if (cp->hw_ok == 0) 5265 return; 5266 pciide_map_compat_intr(pa, cp, channel, interface); 5267 if (cp->hw_ok == 0) 5268 return; 5269 serverworks_setup_channel(&cp->wdc_channel); 5270 } 5271 5272 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 5273 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 5274 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 5275 } 5276 5277 void 5278 serverworks_setup_channel(chp) 5279 struct channel_softc *chp; 5280 { 5281 struct ata_drive_datas *drvp; 5282 struct pciide_channel *cp = (struct pciide_channel*)chp; 5283 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5284 int channel = chp->channel; 5285 int drive, unit; 5286 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 5287 u_int32_t idedma_ctl; 5288 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 5289 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 5290 5291 /* setup DMA if needed */ 5292 pciide_channel_dma_setup(cp); 5293 5294 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 5295 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 5296 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 5297 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 5298 5299 pio_time &= ~(0xffff << (16 * channel)); 5300 dma_time &= ~(0xffff << (16 * channel)); 5301 pio_mode &= ~(0xff << (8 * channel + 16)); 5302 udma_mode &= ~(0xff << (8 * channel + 16)); 5303 udma_mode &= ~(3 << (2 * channel)); 5304 5305 idedma_ctl = 0; 5306 5307 /* Per drive settings */ 5308 for (drive = 0; drive < 2; drive++) { 5309 drvp = &chp->ch_drive[drive]; 5310 /* If no drive, skip */ 5311 if ((drvp->drive_flags & DRIVE) == 0) 5312 continue; 5313 unit = drive + 2 * channel; 5314 /* add timing values, setup DMA if needed */ 5315 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 5316 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 5317 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 5318 (drvp->drive_flags & DRIVE_UDMA)) { 5319 /* use Ultra/DMA, check for 80-pin cable */ 5320 if (drvp->UDMA_mode > 2 && 5321 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 5322 drvp->UDMA_mode = 2; 5323 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 5324 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 5325 udma_mode |= 1 << unit; 5326 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5327 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 5328 (drvp->drive_flags & DRIVE_DMA)) { 5329 /* use Multiword DMA */ 5330 drvp->drive_flags &= ~DRIVE_UDMA; 5331 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 5332 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5333 } else { 5334 /* PIO only */ 5335 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 5336 } 5337 } 5338 5339 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 5340 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 5341 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 5342 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 5343 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 5344 5345 if (idedma_ctl != 0) { 5346 /* Add software bits in status register */ 5347 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5348 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 5349 } 5350 pciide_print_modes(cp); 5351 } 5352 5353 int 5354 serverworks_pci_intr(arg) 5355 void *arg; 5356 { 5357 struct pciide_softc *sc = arg; 5358 struct pciide_channel *cp; 5359 struct channel_softc *wdc_cp; 5360 int rv = 0; 5361 int dmastat, i, crv; 5362 5363 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5364 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5365 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 5366 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 5367 IDEDMA_CTL_INTR) 5368 continue; 5369 cp = &sc->pciide_channels[i]; 5370 wdc_cp = &cp->wdc_channel; 5371 crv = wdcintr(wdc_cp); 5372 if (crv == 0) { 5373 printf("%s:%d: bogus intr\n", 5374 sc->sc_wdcdev.sc_dev.dv_xname, i); 5375 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5376 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 5377 } else 5378 rv = 1; 5379 } 5380 return rv; 5381 } 5382 5383 void 5384 artisea_chip_map(sc, pa) 5385 struct pciide_softc *sc; 5386 struct pci_attach_args *pa; 5387 { 5388 struct pciide_channel *cp; 5389 bus_size_t cmdsize, ctlsize; 5390 pcireg_t interface; 5391 int channel; 5392 5393 if (pciide_chipen(sc, pa) == 0) 5394 return; 5395 5396 printf("%s: bus-master DMA support resent", 5397 sc->sc_wdcdev.sc_dev.dv_xname); 5398 #ifndef PCIIDE_I31244_ENABLEDMA 5399 if (PCI_REVISION(pa->pa_class) == 0) { 5400 printf(" but disabled due to rev. 0"); 5401 sc->sc_dma_ok = 0; 5402 } else 5403 #endif 5404 pciide_mapreg_dma(sc, pa); 5405 printf("\n"); 5406 5407 /* 5408 * XXX Configure LEDs to show activity. 5409 */ 5410 5411 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5412 WDC_CAPABILITY_MODE; 5413 sc->sc_wdcdev.PIO_cap = 4; 5414 if (sc->sc_dma_ok) { 5415 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5416 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5417 sc->sc_wdcdev.irqack = pciide_irqack; 5418 sc->sc_wdcdev.DMA_cap = 2; 5419 sc->sc_wdcdev.UDMA_cap = 6; 5420 } 5421 sc->sc_wdcdev.set_modes = sata_setup_channel; 5422 5423 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5424 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5425 5426 interface = PCI_INTERFACE(pa->pa_class); 5427 5428 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5429 cp = &sc->pciide_channels[channel]; 5430 if (pciide_chansetup(sc, channel, interface) == 0) 5431 continue; 5432 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5433 pciide_pci_intr); 5434 if (cp->hw_ok == 0) 5435 continue; 5436 pciide_map_compat_intr(pa, cp, channel, interface); 5437 sata_setup_channel(&cp->wdc_channel); 5438 } 5439 } 5440
Indexes created Thu Oct 02 10:09:58 GMT 2025