pciide.c revision 1.200
1 /* $NetBSD: pciide.c,v 1.200 2003/09/19 21:36:05 mycroft Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.200 2003/09/19 21:36:05 mycroft Exp $"); 80 81 #ifndef WDCDEBUG 82 #define WDCDEBUG 83 #endif 84 85 #define DEBUG_DMA 0x01 86 #define DEBUG_XFERS 0x02 87 #define DEBUG_FUNCS 0x08 88 #define DEBUG_PROBE 0x10 89 #ifdef WDCDEBUG 90 int wdcdebug_pciide_mask = 0; 91 #define WDCDEBUG_PRINT(args, level) \ 92 if (wdcdebug_pciide_mask & (level)) printf args 93 #else 94 #define WDCDEBUG_PRINT(args, level) 95 #endif 96 #include <sys/param.h> 97 #include <sys/systm.h> 98 #include <sys/device.h> 99 #include <sys/malloc.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <machine/endian.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/pciide_sl82c105_reg.h> 122 #include <dev/pci/pciide_i31244_reg.h> 123 #include <dev/pci/pciide_sii3112_reg.h> 124 #include <dev/pci/cy82c693var.h> 125 126 #include "opt_pciide.h" 127 128 static const char dmaerrfmt[] = 129 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 130 131 /* inlines for reading/writing 8-bit PCI registers */ 132 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 133 int)); 134 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 135 int, u_int8_t)); 136 137 static __inline u_int8_t 138 pciide_pci_read(pc, pa, reg) 139 pci_chipset_tag_t pc; 140 pcitag_t pa; 141 int reg; 142 { 143 144 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 145 ((reg & 0x03) * 8) & 0xff); 146 } 147 148 static __inline void 149 pciide_pci_write(pc, pa, reg, val) 150 pci_chipset_tag_t pc; 151 pcitag_t pa; 152 int reg; 153 u_int8_t val; 154 { 155 pcireg_t pcival; 156 157 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 158 pcival &= ~(0xff << ((reg & 0x03) * 8)); 159 pcival |= (val << ((reg & 0x03) * 8)); 160 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 161 } 162 163 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 164 165 void sata_setup_channel __P((struct channel_softc*)); 166 167 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void piix_setup_channel __P((struct channel_softc*)); 169 void piix3_4_setup_channel __P((struct channel_softc*)); 170 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 171 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 172 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 173 174 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void amd7x6_setup_channel __P((struct channel_softc*)); 176 177 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void apollo_sata_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 179 void apollo_setup_channel __P((struct channel_softc*)); 180 181 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 183 void cmd0643_9_setup_channel __P((struct channel_softc*)); 184 void cmd_channel_map __P((struct pci_attach_args *, 185 struct pciide_softc *, int)); 186 int cmd_pci_intr __P((void *)); 187 void cmd646_9_irqack __P((struct channel_softc *)); 188 void cmd680_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 189 void cmd680_setup_channel __P((struct channel_softc*)); 190 void cmd680_channel_map __P((struct pci_attach_args *, 191 struct pciide_softc *, int)); 192 193 void cmd3112_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 194 void cmd3112_setup_channel __P((struct channel_softc*)); 195 196 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 197 void cy693_setup_channel __P((struct channel_softc*)); 198 199 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 200 void sis_setup_channel __P((struct channel_softc*)); 201 void sis96x_setup_channel __P((struct channel_softc*)); 202 static int sis_hostbr_match __P(( struct pci_attach_args *)); 203 static int sis_south_match __P(( struct pci_attach_args *)); 204 205 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 206 void acer_setup_channel __P((struct channel_softc*)); 207 int acer_pci_intr __P((void *)); 208 209 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 210 void pdc202xx_setup_channel __P((struct channel_softc*)); 211 void pdc20268_setup_channel __P((struct channel_softc*)); 212 int pdc202xx_pci_intr __P((void *)); 213 int pdc20265_pci_intr __P((void *)); 214 static void pdc20262_dma_start __P((void*, int, int)); 215 static int pdc20262_dma_finish __P((void*, int, int, int)); 216 217 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 218 void opti_setup_channel __P((struct channel_softc*)); 219 220 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 221 void hpt_setup_channel __P((struct channel_softc*)); 222 int hpt_pci_intr __P((void *)); 223 224 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 225 void acard_setup_channel __P((struct channel_softc*)); 226 int acard_pci_intr __P((void *)); 227 228 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 229 void serverworks_setup_channel __P((struct channel_softc*)); 230 int serverworks_pci_intr __P((void *)); 231 232 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 233 void sl82c105_setup_channel __P((struct channel_softc*)); 234 235 void pciide_channel_dma_setup __P((struct pciide_channel *)); 236 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 237 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 238 void pciide_dma_start __P((void*, int, int)); 239 int pciide_dma_finish __P((void*, int, int, int)); 240 void pciide_irqack __P((struct channel_softc *)); 241 242 void artisea_chip_map __P((struct pciide_softc*, struct pci_attach_args *)); 243 244 struct pciide_product_desc { 245 u_int32_t ide_product; 246 int ide_flags; 247 const char *ide_name; 248 /* map and setup chip, probe drives */ 249 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 250 }; 251 252 /* Flags for ide_flags */ 253 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 254 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 255 256 /* Default product description for devices not known from this controller */ 257 const struct pciide_product_desc default_product_desc = { 258 0, 259 0, 260 "Generic PCI IDE controller", 261 default_chip_map, 262 }; 263 264 const struct pciide_product_desc pciide_intel_products[] = { 265 { PCI_PRODUCT_INTEL_82092AA, 266 0, 267 "Intel 82092AA IDE controller", 268 default_chip_map, 269 }, 270 { PCI_PRODUCT_INTEL_82371FB_IDE, 271 0, 272 "Intel 82371FB IDE controller (PIIX)", 273 piix_chip_map, 274 }, 275 { PCI_PRODUCT_INTEL_82371SB_IDE, 276 0, 277 "Intel 82371SB IDE Interface (PIIX3)", 278 piix_chip_map, 279 }, 280 { PCI_PRODUCT_INTEL_82371AB_IDE, 281 0, 282 "Intel 82371AB IDE controller (PIIX4)", 283 piix_chip_map, 284 }, 285 { PCI_PRODUCT_INTEL_82440MX_IDE, 286 0, 287 "Intel 82440MX IDE controller", 288 piix_chip_map 289 }, 290 { PCI_PRODUCT_INTEL_82801AA_IDE, 291 0, 292 "Intel 82801AA IDE Controller (ICH)", 293 piix_chip_map, 294 }, 295 { PCI_PRODUCT_INTEL_82801AB_IDE, 296 0, 297 "Intel 82801AB IDE Controller (ICH0)", 298 piix_chip_map, 299 }, 300 { PCI_PRODUCT_INTEL_82801BA_IDE, 301 0, 302 "Intel 82801BA IDE Controller (ICH2)", 303 piix_chip_map, 304 }, 305 { PCI_PRODUCT_INTEL_82801BAM_IDE, 306 0, 307 "Intel 82801BAM IDE Controller (ICH2-M)", 308 piix_chip_map, 309 }, 310 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 311 0, 312 "Intel 82801CA IDE Controller (ICH3)", 313 piix_chip_map, 314 }, 315 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 316 0, 317 "Intel 82801CA IDE Controller (ICH3)", 318 piix_chip_map, 319 }, 320 { PCI_PRODUCT_INTEL_82801DB_IDE, 321 0, 322 "Intel 82801DB IDE Controller (ICH4)", 323 piix_chip_map, 324 }, 325 { PCI_PRODUCT_INTEL_82801DBM_IDE, 326 0, 327 "Intel 82801DBM IDE Controller (ICH4-M)", 328 piix_chip_map, 329 }, 330 { PCI_PRODUCT_INTEL_82801EB_IDE, 331 0, 332 "Intel 82801EB IDE Controller (ICH5)", 333 piix_chip_map, 334 }, 335 { PCI_PRODUCT_INTEL_31244, 336 0, 337 "Intel 31244 Serial ATA Controller", 338 artisea_chip_map, 339 }, 340 { PCI_PRODUCT_INTEL_82801EB_SATA, 341 0, 342 "Intel 82801EB Serial ATA Controller", 343 artisea_chip_map, 344 }, 345 { 0, 346 0, 347 NULL, 348 NULL 349 } 350 }; 351 352 const struct pciide_product_desc pciide_amd_products[] = { 353 { PCI_PRODUCT_AMD_PBC756_IDE, 354 0, 355 "Advanced Micro Devices AMD756 IDE Controller", 356 amd7x6_chip_map 357 }, 358 { PCI_PRODUCT_AMD_PBC766_IDE, 359 0, 360 "Advanced Micro Devices AMD766 IDE Controller", 361 amd7x6_chip_map 362 }, 363 { PCI_PRODUCT_AMD_PBC768_IDE, 364 0, 365 "Advanced Micro Devices AMD768 IDE Controller", 366 amd7x6_chip_map 367 }, 368 { PCI_PRODUCT_AMD_PBC8111_IDE, 369 0, 370 "Advanced Micro Devices AMD8111 IDE Controller", 371 amd7x6_chip_map 372 }, 373 { 0, 374 0, 375 NULL, 376 NULL 377 } 378 }; 379 380 const struct pciide_product_desc pciide_nvidia_products[] = { 381 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 382 0, 383 "NVIDIA nForce IDE Controller", 384 amd7x6_chip_map 385 }, 386 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 387 0, 388 "NVIDIA nForce2 IDE Controller", 389 amd7x6_chip_map 390 }, 391 { 0, 392 0, 393 NULL, 394 NULL 395 } 396 }; 397 398 const struct pciide_product_desc pciide_cmd_products[] = { 399 { PCI_PRODUCT_CMDTECH_640, 400 0, 401 "CMD Technology PCI0640", 402 cmd_chip_map 403 }, 404 { PCI_PRODUCT_CMDTECH_643, 405 0, 406 "CMD Technology PCI0643", 407 cmd0643_9_chip_map, 408 }, 409 { PCI_PRODUCT_CMDTECH_646, 410 0, 411 "CMD Technology PCI0646", 412 cmd0643_9_chip_map, 413 }, 414 { PCI_PRODUCT_CMDTECH_648, 415 IDE_PCI_CLASS_OVERRIDE, 416 "CMD Technology PCI0648", 417 cmd0643_9_chip_map, 418 }, 419 { PCI_PRODUCT_CMDTECH_649, 420 IDE_PCI_CLASS_OVERRIDE, 421 "CMD Technology PCI0649", 422 cmd0643_9_chip_map, 423 }, 424 { PCI_PRODUCT_CMDTECH_680, 425 IDE_PCI_CLASS_OVERRIDE, 426 "Silicon Image 0680", 427 cmd680_chip_map, 428 }, 429 { PCI_PRODUCT_CMDTECH_3112, 430 IDE_PCI_CLASS_OVERRIDE, 431 "Silicon Image SATALink 3112", 432 cmd3112_chip_map, 433 }, 434 { 0, 435 0, 436 NULL, 437 NULL 438 } 439 }; 440 441 const struct pciide_product_desc pciide_via_products[] = { 442 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 443 0, 444 NULL, 445 apollo_chip_map, 446 }, 447 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 448 0, 449 NULL, 450 apollo_chip_map, 451 }, 452 { PCI_PRODUCT_VIATECH_VT8237_SATA, 453 IDE_PCI_CLASS_OVERRIDE, 454 "VIA Technologies VT8237 SATA Controller", 455 apollo_sata_chip_map, 456 }, 457 { 0, 458 0, 459 NULL, 460 NULL 461 } 462 }; 463 464 const struct pciide_product_desc pciide_cypress_products[] = { 465 { PCI_PRODUCT_CONTAQ_82C693, 466 IDE_16BIT_IOSPACE, 467 "Cypress 82C693 IDE Controller", 468 cy693_chip_map, 469 }, 470 { 0, 471 0, 472 NULL, 473 NULL 474 } 475 }; 476 477 const struct pciide_product_desc pciide_sis_products[] = { 478 { PCI_PRODUCT_SIS_5597_IDE, 479 0, 480 NULL, 481 sis_chip_map, 482 }, 483 { 0, 484 0, 485 NULL, 486 NULL 487 } 488 }; 489 490 const struct pciide_product_desc pciide_acer_products[] = { 491 { PCI_PRODUCT_ALI_M5229, 492 0, 493 "Acer Labs M5229 UDMA IDE Controller", 494 acer_chip_map, 495 }, 496 { 0, 497 0, 498 NULL, 499 NULL 500 } 501 }; 502 503 const struct pciide_product_desc pciide_promise_products[] = { 504 { PCI_PRODUCT_PROMISE_ULTRA33, 505 IDE_PCI_CLASS_OVERRIDE, 506 "Promise Ultra33/ATA Bus Master IDE Accelerator", 507 pdc202xx_chip_map, 508 }, 509 { PCI_PRODUCT_PROMISE_ULTRA66, 510 IDE_PCI_CLASS_OVERRIDE, 511 "Promise Ultra66/ATA Bus Master IDE Accelerator", 512 pdc202xx_chip_map, 513 }, 514 { PCI_PRODUCT_PROMISE_ULTRA100, 515 IDE_PCI_CLASS_OVERRIDE, 516 "Promise Ultra100/ATA Bus Master IDE Accelerator", 517 pdc202xx_chip_map, 518 }, 519 { PCI_PRODUCT_PROMISE_ULTRA100X, 520 IDE_PCI_CLASS_OVERRIDE, 521 "Promise Ultra100/ATA Bus Master IDE Accelerator", 522 pdc202xx_chip_map, 523 }, 524 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 525 IDE_PCI_CLASS_OVERRIDE, 526 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 527 pdc202xx_chip_map, 528 }, 529 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 530 IDE_PCI_CLASS_OVERRIDE, 531 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 532 pdc202xx_chip_map, 533 }, 534 { PCI_PRODUCT_PROMISE_ULTRA133, 535 IDE_PCI_CLASS_OVERRIDE, 536 "Promise Ultra133/ATA Bus Master IDE Accelerator", 537 pdc202xx_chip_map, 538 }, 539 { PCI_PRODUCT_PROMISE_ULTRA133TX2, 540 IDE_PCI_CLASS_OVERRIDE, 541 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 542 pdc202xx_chip_map, 543 }, 544 { PCI_PRODUCT_PROMISE_MBULTRA133, 545 IDE_PCI_CLASS_OVERRIDE, 546 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 547 pdc202xx_chip_map, 548 }, 549 { PCI_PRODUCT_PROMISE_ULTRA133TX2v2, 550 IDE_PCI_CLASS_OVERRIDE, 551 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 552 pdc202xx_chip_map, 553 }, 554 { PCI_PRODUCT_PROMISE_FASTTRAK133LITE, 555 IDE_PCI_CLASS_OVERRIDE, 556 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 557 pdc202xx_chip_map, 558 }, 559 { PCI_PRODUCT_PROMISE_SATA150TX2PLUS, 560 IDE_PCI_CLASS_OVERRIDE, 561 "Promise Serial ATA/150 TX2plus Bus Master IDE Accelerator", 562 pdc202xx_chip_map, 563 }, 564 { 0, 565 0, 566 NULL, 567 NULL 568 } 569 }; 570 571 const struct pciide_product_desc pciide_opti_products[] = { 572 { PCI_PRODUCT_OPTI_82C621, 573 0, 574 "OPTi 82c621 PCI IDE controller", 575 opti_chip_map, 576 }, 577 { PCI_PRODUCT_OPTI_82C568, 578 0, 579 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 580 opti_chip_map, 581 }, 582 { PCI_PRODUCT_OPTI_82D568, 583 0, 584 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 585 opti_chip_map, 586 }, 587 { 0, 588 0, 589 NULL, 590 NULL 591 } 592 }; 593 594 const struct pciide_product_desc pciide_triones_products[] = { 595 { PCI_PRODUCT_TRIONES_HPT366, 596 IDE_PCI_CLASS_OVERRIDE, 597 NULL, 598 hpt_chip_map, 599 }, 600 { PCI_PRODUCT_TRIONES_HPT372, 601 IDE_PCI_CLASS_OVERRIDE, 602 NULL, 603 hpt_chip_map 604 }, 605 { PCI_PRODUCT_TRIONES_HPT374, 606 IDE_PCI_CLASS_OVERRIDE, 607 NULL, 608 hpt_chip_map 609 }, 610 { 0, 611 0, 612 NULL, 613 NULL 614 } 615 }; 616 617 const struct pciide_product_desc pciide_acard_products[] = { 618 { PCI_PRODUCT_ACARD_ATP850U, 619 IDE_PCI_CLASS_OVERRIDE, 620 "Acard ATP850U Ultra33 IDE Controller", 621 acard_chip_map, 622 }, 623 { PCI_PRODUCT_ACARD_ATP860, 624 IDE_PCI_CLASS_OVERRIDE, 625 "Acard ATP860 Ultra66 IDE Controller", 626 acard_chip_map, 627 }, 628 { PCI_PRODUCT_ACARD_ATP860A, 629 IDE_PCI_CLASS_OVERRIDE, 630 "Acard ATP860-A Ultra66 IDE Controller", 631 acard_chip_map, 632 }, 633 { 0, 634 0, 635 NULL, 636 NULL 637 } 638 }; 639 640 const struct pciide_product_desc pciide_serverworks_products[] = { 641 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 642 0, 643 "ServerWorks OSB4 IDE Controller", 644 serverworks_chip_map, 645 }, 646 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 647 0, 648 "ServerWorks CSB5 IDE Controller", 649 serverworks_chip_map, 650 }, 651 { PCI_PRODUCT_SERVERWORKS_CSB6_IDE, 652 0, 653 "ServerWorks CSB6 RAID/IDE Controller", 654 serverworks_chip_map, 655 }, 656 { 0, 657 0, 658 NULL, 659 } 660 }; 661 662 const struct pciide_product_desc pciide_symphony_products[] = { 663 { PCI_PRODUCT_SYMPHONY_82C105, 664 0, 665 "Symphony Labs 82C105 IDE controller", 666 sl82c105_chip_map, 667 }, 668 { 0, 669 0, 670 NULL, 671 } 672 }; 673 674 const struct pciide_product_desc pciide_winbond_products[] = { 675 { PCI_PRODUCT_WINBOND_W83C553F_1, 676 0, 677 "Winbond W83C553F IDE controller", 678 sl82c105_chip_map, 679 }, 680 { 0, 681 0, 682 NULL, 683 } 684 }; 685 686 struct pciide_vendor_desc { 687 u_int32_t ide_vendor; 688 const struct pciide_product_desc *ide_products; 689 }; 690 691 const struct pciide_vendor_desc pciide_vendors[] = { 692 { PCI_VENDOR_INTEL, pciide_intel_products }, 693 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 694 { PCI_VENDOR_VIATECH, pciide_via_products }, 695 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 696 { PCI_VENDOR_SIS, pciide_sis_products }, 697 { PCI_VENDOR_ALI, pciide_acer_products }, 698 { PCI_VENDOR_PROMISE, pciide_promise_products }, 699 { PCI_VENDOR_AMD, pciide_amd_products }, 700 { PCI_VENDOR_OPTI, pciide_opti_products }, 701 { PCI_VENDOR_TRIONES, pciide_triones_products }, 702 { PCI_VENDOR_ACARD, pciide_acard_products }, 703 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 704 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 705 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 706 { PCI_VENDOR_NVIDIA, pciide_nvidia_products }, 707 { 0, NULL } 708 }; 709 710 /* options passed via the 'flags' config keyword */ 711 #define PCIIDE_OPTIONS_DMA 0x01 712 #define PCIIDE_OPTIONS_NODMA 0x02 713 714 int pciide_match __P((struct device *, struct cfdata *, void *)); 715 void pciide_attach __P((struct device *, struct device *, void *)); 716 717 CFATTACH_DECL(pciide, sizeof(struct pciide_softc), 718 pciide_match, pciide_attach, NULL, NULL); 719 720 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 721 int pciide_mapregs_compat __P(( struct pci_attach_args *, 722 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 723 int pciide_mapregs_native __P((struct pci_attach_args *, 724 struct pciide_channel *, bus_size_t *, bus_size_t *, 725 int (*pci_intr) __P((void *)))); 726 void pciide_mapreg_dma __P((struct pciide_softc *, 727 struct pci_attach_args *)); 728 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 729 void pciide_mapchan __P((struct pci_attach_args *, 730 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 731 int (*pci_intr) __P((void *)))); 732 void pciide_map_compat_intr __P(( struct pci_attach_args *, 733 struct pciide_channel *, int)); 734 int pciide_compat_intr __P((void *)); 735 int pciide_pci_intr __P((void *)); 736 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 737 738 const struct pciide_product_desc * 739 pciide_lookup_product(id) 740 u_int32_t id; 741 { 742 const struct pciide_product_desc *pp; 743 const struct pciide_vendor_desc *vp; 744 745 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 746 if (PCI_VENDOR(id) == vp->ide_vendor) 747 break; 748 749 if ((pp = vp->ide_products) == NULL) 750 return NULL; 751 752 for (; pp->chip_map != NULL; pp++) 753 if (PCI_PRODUCT(id) == pp->ide_product) 754 break; 755 756 if (pp->chip_map == NULL) 757 return NULL; 758 return pp; 759 } 760 761 int 762 pciide_match(parent, match, aux) 763 struct device *parent; 764 struct cfdata *match; 765 void *aux; 766 { 767 struct pci_attach_args *pa = aux; 768 const struct pciide_product_desc *pp; 769 770 /* 771 * Check the ID register to see that it's a PCI IDE controller. 772 * If it is, we assume that we can deal with it; it _should_ 773 * work in a standardized way... 774 */ 775 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 776 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 777 return (1); 778 } 779 780 /* 781 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 782 * controllers. Let see if we can deal with it anyway. 783 */ 784 pp = pciide_lookup_product(pa->pa_id); 785 if (pp != NULL && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 786 return (1); 787 } 788 789 return (0); 790 } 791 792 void 793 pciide_attach(parent, self, aux) 794 struct device *parent, *self; 795 void *aux; 796 { 797 struct pci_attach_args *pa = aux; 798 pci_chipset_tag_t pc = pa->pa_pc; 799 pcitag_t tag = pa->pa_tag; 800 struct pciide_softc *sc = (struct pciide_softc *)self; 801 pcireg_t csr; 802 char devinfo[256]; 803 const char *displaydev; 804 805 aprint_naive(": disk controller\n"); 806 807 sc->sc_pci_vendor = PCI_VENDOR(pa->pa_id); 808 sc->sc_pp = pciide_lookup_product(pa->pa_id); 809 if (sc->sc_pp == NULL) { 810 sc->sc_pp = &default_product_desc; 811 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 812 displaydev = devinfo; 813 } else 814 displaydev = sc->sc_pp->ide_name; 815 816 /* if displaydev == NULL, printf is done in chip-specific map */ 817 if (displaydev) 818 aprint_normal(": %s (rev. 0x%02x)\n", displaydev, 819 PCI_REVISION(pa->pa_class)); 820 821 sc->sc_pc = pa->pa_pc; 822 sc->sc_tag = pa->pa_tag; 823 824 /* Set up DMA defaults; these might be adjusted by chip_map. */ 825 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 826 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 827 828 #ifdef WDCDEBUG 829 if (wdcdebug_pciide_mask & DEBUG_PROBE) 830 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 831 #endif 832 sc->sc_pp->chip_map(sc, pa); 833 834 if (sc->sc_dma_ok) { 835 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 836 csr |= PCI_COMMAND_MASTER_ENABLE; 837 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 838 } 839 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 840 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 841 842 config_interrupts(self, wdcattach); 843 } 844 845 /* tell whether the chip is enabled or not */ 846 int 847 pciide_chipen(sc, pa) 848 struct pciide_softc *sc; 849 struct pci_attach_args *pa; 850 { 851 pcireg_t csr; 852 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 853 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 854 PCI_COMMAND_STATUS_REG); 855 aprint_normal("%s: device disabled (at %s)\n", 856 sc->sc_wdcdev.sc_dev.dv_xname, 857 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 858 "device" : "bridge"); 859 return 0; 860 } 861 return 1; 862 } 863 864 int 865 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 866 struct pci_attach_args *pa; 867 struct pciide_channel *cp; 868 int compatchan; 869 bus_size_t *cmdsizep, *ctlsizep; 870 { 871 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 872 struct channel_softc *wdc_cp = &cp->wdc_channel; 873 874 cp->compat = 1; 875 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 876 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 877 878 wdc_cp->cmd_iot = pa->pa_iot; 879 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 880 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 881 aprint_error("%s: couldn't map %s channel cmd regs\n", 882 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 883 goto bad; 884 } 885 886 wdc_cp->ctl_iot = pa->pa_iot; 887 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 888 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 889 aprint_error("%s: couldn't map %s channel ctl regs\n", 890 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 891 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 892 PCIIDE_COMPAT_CMD_SIZE); 893 goto bad; 894 } 895 896 wdc_cp->data32iot = wdc_cp->cmd_iot; 897 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 898 pciide_map_compat_intr(pa, cp, compatchan); 899 return (1); 900 901 bad: 902 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 903 return (0); 904 } 905 906 int 907 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 908 struct pci_attach_args * pa; 909 struct pciide_channel *cp; 910 bus_size_t *cmdsizep, *ctlsizep; 911 int (*pci_intr) __P((void *)); 912 { 913 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 914 struct channel_softc *wdc_cp = &cp->wdc_channel; 915 const char *intrstr; 916 pci_intr_handle_t intrhandle; 917 918 cp->compat = 0; 919 920 if (sc->sc_pci_ih == NULL) { 921 if (pci_intr_map(pa, &intrhandle) != 0) { 922 aprint_error("%s: couldn't map native-PCI interrupt\n", 923 sc->sc_wdcdev.sc_dev.dv_xname); 924 goto bad; 925 } 926 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 927 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 928 intrhandle, IPL_BIO, pci_intr, sc); 929 if (sc->sc_pci_ih != NULL) { 930 aprint_normal("%s: using %s for native-PCI interrupt\n", 931 sc->sc_wdcdev.sc_dev.dv_xname, 932 intrstr ? intrstr : "unknown interrupt"); 933 } else { 934 aprint_error( 935 "%s: couldn't establish native-PCI interrupt", 936 sc->sc_wdcdev.sc_dev.dv_xname); 937 if (intrstr != NULL) 938 aprint_normal(" at %s", intrstr); 939 aprint_normal("\n"); 940 goto bad; 941 } 942 } 943 cp->ih = sc->sc_pci_ih; 944 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 945 PCI_MAPREG_TYPE_IO, 0, 946 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 947 aprint_error("%s: couldn't map %s channel cmd regs\n", 948 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 949 goto bad; 950 } 951 952 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 953 PCI_MAPREG_TYPE_IO, 0, 954 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 955 aprint_error("%s: couldn't map %s channel ctl regs\n", 956 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 957 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 958 goto bad; 959 } 960 /* 961 * In native mode, 4 bytes of I/O space are mapped for the control 962 * register, the control register is at offset 2. Pass the generic 963 * code a handle for only one byte at the right offset. 964 */ 965 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 966 &wdc_cp->ctl_ioh) != 0) { 967 aprint_error("%s: unable to subregion %s channel ctl regs\n", 968 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 969 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 970 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 971 goto bad; 972 } 973 974 wdc_cp->data32iot = wdc_cp->cmd_iot; 975 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 976 return (1); 977 978 bad: 979 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 980 return (0); 981 } 982 983 void 984 pciide_mapreg_dma(sc, pa) 985 struct pciide_softc *sc; 986 struct pci_attach_args *pa; 987 { 988 pcireg_t maptype; 989 bus_addr_t addr; 990 991 /* 992 * Map DMA registers 993 * 994 * Note that sc_dma_ok is the right variable to test to see if 995 * DMA can be done. If the interface doesn't support DMA, 996 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 997 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 998 * non-zero if the interface supports DMA and the registers 999 * could be mapped. 1000 * 1001 * XXX Note that despite the fact that the Bus Master IDE specs 1002 * XXX say that "The bus master IDE function uses 16 bytes of IO 1003 * XXX space," some controllers (at least the United 1004 * XXX Microelectronics UM8886BF) place it in memory space. 1005 */ 1006 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 1007 PCIIDE_REG_BUS_MASTER_DMA); 1008 1009 switch (maptype) { 1010 case PCI_MAPREG_TYPE_IO: 1011 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 1012 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 1013 &addr, NULL, NULL) == 0); 1014 if (sc->sc_dma_ok == 0) { 1015 aprint_normal( 1016 ", but unused (couldn't query registers)"); 1017 break; 1018 } 1019 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 1020 && addr >= 0x10000) { 1021 sc->sc_dma_ok = 0; 1022 aprint_normal( 1023 ", but unused (registers at unsafe address " 1024 "%#lx)", (unsigned long)addr); 1025 break; 1026 } 1027 /* FALLTHROUGH */ 1028 1029 case PCI_MAPREG_MEM_TYPE_32BIT: 1030 sc->sc_dma_ok = (pci_mapreg_map(pa, 1031 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 1032 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 1033 sc->sc_dmat = pa->pa_dmat; 1034 if (sc->sc_dma_ok == 0) { 1035 aprint_normal(", but unused (couldn't map registers)"); 1036 } else { 1037 sc->sc_wdcdev.dma_arg = sc; 1038 sc->sc_wdcdev.dma_init = pciide_dma_init; 1039 sc->sc_wdcdev.dma_start = pciide_dma_start; 1040 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 1041 } 1042 1043 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1044 PCIIDE_OPTIONS_NODMA) { 1045 aprint_normal( 1046 ", but unused (forced off by config file)"); 1047 sc->sc_dma_ok = 0; 1048 } 1049 break; 1050 1051 default: 1052 sc->sc_dma_ok = 0; 1053 aprint_normal( 1054 ", but unsupported register maptype (0x%x)", maptype); 1055 } 1056 } 1057 1058 int 1059 pciide_compat_intr(arg) 1060 void *arg; 1061 { 1062 struct pciide_channel *cp = arg; 1063 1064 #ifdef DIAGNOSTIC 1065 /* should only be called for a compat channel */ 1066 if (cp->compat == 0) 1067 panic("pciide compat intr called for non-compat chan %p", cp); 1068 #endif 1069 return (wdcintr(&cp->wdc_channel)); 1070 } 1071 1072 int 1073 pciide_pci_intr(arg) 1074 void *arg; 1075 { 1076 struct pciide_softc *sc = arg; 1077 struct pciide_channel *cp; 1078 struct channel_softc *wdc_cp; 1079 int i, rv, crv; 1080 1081 rv = 0; 1082 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1083 cp = &sc->pciide_channels[i]; 1084 wdc_cp = &cp->wdc_channel; 1085 1086 /* If a compat channel skip. */ 1087 if (cp->compat) 1088 continue; 1089 /* if this channel not waiting for intr, skip */ 1090 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 1091 continue; 1092 1093 crv = wdcintr(wdc_cp); 1094 if (crv == 0) 1095 ; /* leave rv alone */ 1096 else if (crv == 1) 1097 rv = 1; /* claim the intr */ 1098 else if (rv == 0) /* crv should be -1 in this case */ 1099 rv = crv; /* if we've done no better, take it */ 1100 } 1101 return (rv); 1102 } 1103 1104 void 1105 pciide_channel_dma_setup(cp) 1106 struct pciide_channel *cp; 1107 { 1108 int drive; 1109 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1110 struct ata_drive_datas *drvp; 1111 1112 for (drive = 0; drive < 2; drive++) { 1113 drvp = &cp->wdc_channel.ch_drive[drive]; 1114 /* If no drive, skip */ 1115 if ((drvp->drive_flags & DRIVE) == 0) 1116 continue; 1117 /* setup DMA if needed */ 1118 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1119 (drvp->drive_flags & DRIVE_UDMA) == 0) || 1120 sc->sc_dma_ok == 0) { 1121 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1122 continue; 1123 } 1124 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 1125 != 0) { 1126 /* Abort DMA setup */ 1127 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1128 continue; 1129 } 1130 } 1131 } 1132 1133 int 1134 pciide_dma_table_setup(sc, channel, drive) 1135 struct pciide_softc *sc; 1136 int channel, drive; 1137 { 1138 bus_dma_segment_t seg; 1139 int error, rseg; 1140 const bus_size_t dma_table_size = 1141 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1142 struct pciide_dma_maps *dma_maps = 1143 &sc->pciide_channels[channel].dma_maps[drive]; 1144 1145 /* If table was already allocated, just return */ 1146 if (dma_maps->dma_table) 1147 return 0; 1148 1149 /* Allocate memory for the DMA tables and map it */ 1150 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1151 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1152 BUS_DMA_NOWAIT)) != 0) { 1153 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1154 "allocate", drive, error); 1155 return error; 1156 } 1157 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1158 dma_table_size, 1159 (caddr_t *)&dma_maps->dma_table, 1160 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1161 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1162 "map", drive, error); 1163 return error; 1164 } 1165 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1166 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1167 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1168 /* Create and load table DMA map for this disk */ 1169 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1170 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1171 &dma_maps->dmamap_table)) != 0) { 1172 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1173 "create", drive, error); 1174 return error; 1175 } 1176 if ((error = bus_dmamap_load(sc->sc_dmat, 1177 dma_maps->dmamap_table, 1178 dma_maps->dma_table, 1179 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1180 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1181 "load", drive, error); 1182 return error; 1183 } 1184 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1185 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1186 DEBUG_PROBE); 1187 /* Create a xfer DMA map for this drive */ 1188 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1189 NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 1190 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1191 &dma_maps->dmamap_xfer)) != 0) { 1192 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1193 "create xfer", drive, error); 1194 return error; 1195 } 1196 return 0; 1197 } 1198 1199 int 1200 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1201 void *v; 1202 int channel, drive; 1203 void *databuf; 1204 size_t datalen; 1205 int flags; 1206 { 1207 struct pciide_softc *sc = v; 1208 int error, seg; 1209 struct pciide_dma_maps *dma_maps = 1210 &sc->pciide_channels[channel].dma_maps[drive]; 1211 1212 error = bus_dmamap_load(sc->sc_dmat, 1213 dma_maps->dmamap_xfer, 1214 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1215 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1216 if (error) { 1217 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1218 "load xfer", drive, error); 1219 return error; 1220 } 1221 1222 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1223 dma_maps->dmamap_xfer->dm_mapsize, 1224 (flags & WDC_DMA_READ) ? 1225 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1226 1227 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1228 #ifdef DIAGNOSTIC 1229 /* A segment must not cross a 64k boundary */ 1230 { 1231 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1232 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1233 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1234 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1235 printf("pciide_dma: segment %d physical addr 0x%lx" 1236 " len 0x%lx not properly aligned\n", 1237 seg, phys, len); 1238 panic("pciide_dma: buf align"); 1239 } 1240 } 1241 #endif 1242 dma_maps->dma_table[seg].base_addr = 1243 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1244 dma_maps->dma_table[seg].byte_count = 1245 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1246 IDEDMA_BYTE_COUNT_MASK); 1247 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1248 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1249 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1250 1251 } 1252 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1253 htole32(IDEDMA_BYTE_COUNT_EOT); 1254 1255 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1256 dma_maps->dmamap_table->dm_mapsize, 1257 BUS_DMASYNC_PREWRITE); 1258 1259 /* Maps are ready. Start DMA function */ 1260 #ifdef DIAGNOSTIC 1261 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1262 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1263 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1264 panic("pciide_dma_init: table align"); 1265 } 1266 #endif 1267 1268 /* Clear status bits */ 1269 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1270 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1271 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1272 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1273 /* Write table addr */ 1274 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1275 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1276 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1277 /* set read/write */ 1278 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1279 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1280 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1281 /* remember flags */ 1282 dma_maps->dma_flags = flags; 1283 return 0; 1284 } 1285 1286 void 1287 pciide_dma_start(v, channel, drive) 1288 void *v; 1289 int channel, drive; 1290 { 1291 struct pciide_softc *sc = v; 1292 1293 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1294 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1295 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1296 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1297 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1298 } 1299 1300 int 1301 pciide_dma_finish(v, channel, drive, force) 1302 void *v; 1303 int channel, drive; 1304 int force; 1305 { 1306 struct pciide_softc *sc = v; 1307 u_int8_t status; 1308 int error = 0; 1309 struct pciide_dma_maps *dma_maps = 1310 &sc->pciide_channels[channel].dma_maps[drive]; 1311 1312 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1313 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1314 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1315 DEBUG_XFERS); 1316 1317 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1318 return WDC_DMAST_NOIRQ; 1319 1320 /* stop DMA channel */ 1321 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1322 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1323 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1324 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1325 1326 /* Unload the map of the data buffer */ 1327 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1328 dma_maps->dmamap_xfer->dm_mapsize, 1329 (dma_maps->dma_flags & WDC_DMA_READ) ? 1330 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1331 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1332 1333 if ((status & IDEDMA_CTL_ERR) != 0) { 1334 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1335 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1336 error |= WDC_DMAST_ERR; 1337 } 1338 1339 if ((status & IDEDMA_CTL_INTR) == 0) { 1340 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1341 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1342 drive, status); 1343 error |= WDC_DMAST_NOIRQ; 1344 } 1345 1346 if ((status & IDEDMA_CTL_ACT) != 0) { 1347 /* data underrun, may be a valid condition for ATAPI */ 1348 error |= WDC_DMAST_UNDER; 1349 } 1350 return error; 1351 } 1352 1353 void 1354 pciide_irqack(chp) 1355 struct channel_softc *chp; 1356 { 1357 struct pciide_channel *cp = (struct pciide_channel*)chp; 1358 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1359 1360 /* clear status bits in IDE DMA registers */ 1361 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1362 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1363 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1364 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1365 } 1366 1367 /* some common code used by several chip_map */ 1368 int 1369 pciide_chansetup(sc, channel, interface) 1370 struct pciide_softc *sc; 1371 int channel; 1372 pcireg_t interface; 1373 { 1374 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1375 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1376 cp->name = PCIIDE_CHANNEL_NAME(channel); 1377 cp->wdc_channel.channel = channel; 1378 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1379 cp->wdc_channel.ch_queue = 1380 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1381 if (cp->wdc_channel.ch_queue == NULL) { 1382 aprint_error("%s %s channel: " 1383 "can't allocate memory for command queue", 1384 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1385 return 0; 1386 } 1387 aprint_normal("%s: %s channel %s to %s mode\n", 1388 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1389 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1390 "configured" : "wired", 1391 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1392 "native-PCI" : "compatibility"); 1393 return 1; 1394 } 1395 1396 /* some common code used by several chip channel_map */ 1397 void 1398 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1399 struct pci_attach_args *pa; 1400 struct pciide_channel *cp; 1401 pcireg_t interface; 1402 bus_size_t *cmdsizep, *ctlsizep; 1403 int (*pci_intr) __P((void *)); 1404 { 1405 struct channel_softc *wdc_cp = &cp->wdc_channel; 1406 1407 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1408 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr); 1409 else 1410 pciide_mapregs_compat(pa, cp, wdc_cp->channel, cmdsizep, 1411 ctlsizep); 1412 } 1413 1414 /* 1415 * generic code to map the compat intr. 1416 */ 1417 void 1418 pciide_map_compat_intr(pa, cp, compatchan) 1419 struct pci_attach_args *pa; 1420 struct pciide_channel *cp; 1421 int compatchan; 1422 { 1423 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1424 1425 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1426 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1427 pa, compatchan, pciide_compat_intr, cp); 1428 if (cp->ih == NULL) { 1429 #endif 1430 aprint_error("%s: no compatibility interrupt for use by %s " 1431 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1432 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 1433 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1434 } 1435 #endif 1436 } 1437 1438 void 1439 default_chip_map(sc, pa) 1440 struct pciide_softc *sc; 1441 struct pci_attach_args *pa; 1442 { 1443 struct pciide_channel *cp; 1444 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1445 pcireg_t csr; 1446 int channel, drive; 1447 struct ata_drive_datas *drvp; 1448 u_int8_t idedma_ctl; 1449 bus_size_t cmdsize, ctlsize; 1450 char *failreason; 1451 1452 if (pciide_chipen(sc, pa) == 0) 1453 return; 1454 1455 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1456 aprint_normal("%s: bus-master DMA support present", 1457 sc->sc_wdcdev.sc_dev.dv_xname); 1458 if (sc->sc_pp == &default_product_desc && 1459 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1460 PCIIDE_OPTIONS_DMA) == 0) { 1461 aprint_normal(", but unused (no driver support)"); 1462 sc->sc_dma_ok = 0; 1463 } else { 1464 pciide_mapreg_dma(sc, pa); 1465 if (sc->sc_dma_ok != 0) 1466 aprint_normal(", used without full driver " 1467 "support"); 1468 } 1469 } else { 1470 aprint_normal("%s: hardware does not support DMA", 1471 sc->sc_wdcdev.sc_dev.dv_xname); 1472 sc->sc_dma_ok = 0; 1473 } 1474 aprint_normal("\n"); 1475 if (sc->sc_dma_ok) { 1476 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1477 sc->sc_wdcdev.irqack = pciide_irqack; 1478 } 1479 sc->sc_wdcdev.PIO_cap = 0; 1480 sc->sc_wdcdev.DMA_cap = 0; 1481 1482 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1483 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1484 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1485 1486 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1487 cp = &sc->pciide_channels[channel]; 1488 if (pciide_chansetup(sc, channel, interface) == 0) 1489 continue; 1490 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1491 pciide_pci_intr); 1492 if (cp->wdc_channel.ch_flags & WDCF_DISABLED) 1493 continue; 1494 /* 1495 * Check to see if something appears to be there. 1496 */ 1497 failreason = NULL; 1498 if (!wdcprobe(&cp->wdc_channel)) { 1499 failreason = "not responding; disabled or no drives?"; 1500 goto next; 1501 } 1502 /* 1503 * Now, make sure it's actually attributable to this PCI IDE 1504 * channel by trying to access the channel again while the 1505 * PCI IDE controller's I/O space is disabled. (If the 1506 * channel no longer appears to be there, it belongs to 1507 * this controller.) YUCK! 1508 */ 1509 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1510 PCI_COMMAND_STATUS_REG); 1511 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1512 csr & ~PCI_COMMAND_IO_ENABLE); 1513 if (wdcprobe(&cp->wdc_channel)) 1514 failreason = "other hardware responding at addresses"; 1515 pci_conf_write(sc->sc_pc, sc->sc_tag, 1516 PCI_COMMAND_STATUS_REG, csr); 1517 next: 1518 if (failreason) { 1519 aprint_error("%s: %s channel ignored (%s)\n", 1520 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1521 failreason); 1522 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 1523 } 1524 } 1525 1526 if (sc->sc_dma_ok == 0) 1527 return; 1528 1529 /* Allocate DMA maps */ 1530 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1531 idedma_ctl = 0; 1532 cp = &sc->pciide_channels[channel]; 1533 for (drive = 0; drive < 2; drive++) { 1534 drvp = &cp->wdc_channel.ch_drive[drive]; 1535 /* If no drive, skip */ 1536 if ((drvp->drive_flags & DRIVE) == 0) 1537 continue; 1538 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1539 continue; 1540 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1541 /* Abort DMA setup */ 1542 aprint_error( 1543 "%s:%d:%d: can't allocate DMA maps, " 1544 "using PIO transfers\n", 1545 sc->sc_wdcdev.sc_dev.dv_xname, 1546 channel, drive); 1547 drvp->drive_flags &= ~DRIVE_DMA; 1548 } 1549 aprint_normal("%s:%d:%d: using DMA data transfers\n", 1550 sc->sc_wdcdev.sc_dev.dv_xname, 1551 channel, drive); 1552 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1553 } 1554 if (idedma_ctl != 0) { 1555 /* Add software bits in status register */ 1556 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1557 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1558 idedma_ctl); 1559 } 1560 } 1561 } 1562 1563 void 1564 sata_setup_channel(chp) 1565 struct channel_softc *chp; 1566 { 1567 struct ata_drive_datas *drvp; 1568 int drive; 1569 u_int32_t idedma_ctl; 1570 struct pciide_channel *cp = (struct pciide_channel*)chp; 1571 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 1572 1573 /* setup DMA if needed */ 1574 pciide_channel_dma_setup(cp); 1575 1576 idedma_ctl = 0; 1577 1578 for (drive = 0; drive < 2; drive++) { 1579 drvp = &chp->ch_drive[drive]; 1580 /* If no drive, skip */ 1581 if ((drvp->drive_flags & DRIVE) == 0) 1582 continue; 1583 if (drvp->drive_flags & DRIVE_UDMA) { 1584 /* use Ultra/DMA */ 1585 drvp->drive_flags &= ~DRIVE_DMA; 1586 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1587 } else if (drvp->drive_flags & DRIVE_DMA) { 1588 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1589 } 1590 } 1591 1592 /* 1593 * Nothing to do to setup modes; it is meaningless in S-ATA 1594 * (but many S-ATA drives still want to get the SET_FEATURE 1595 * command). 1596 */ 1597 if (idedma_ctl != 0) { 1598 /* Add software bits in status register */ 1599 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1600 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1601 idedma_ctl); 1602 } 1603 } 1604 1605 void 1606 piix_chip_map(sc, pa) 1607 struct pciide_softc *sc; 1608 struct pci_attach_args *pa; 1609 { 1610 struct pciide_channel *cp; 1611 int channel; 1612 u_int32_t idetim; 1613 bus_size_t cmdsize, ctlsize; 1614 1615 if (pciide_chipen(sc, pa) == 0) 1616 return; 1617 1618 aprint_normal("%s: bus-master DMA support present", 1619 sc->sc_wdcdev.sc_dev.dv_xname); 1620 pciide_mapreg_dma(sc, pa); 1621 aprint_normal("\n"); 1622 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1623 WDC_CAPABILITY_MODE; 1624 if (sc->sc_dma_ok) { 1625 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1626 sc->sc_wdcdev.irqack = pciide_irqack; 1627 switch(sc->sc_pp->ide_product) { 1628 case PCI_PRODUCT_INTEL_82371AB_IDE: 1629 case PCI_PRODUCT_INTEL_82440MX_IDE: 1630 case PCI_PRODUCT_INTEL_82801AA_IDE: 1631 case PCI_PRODUCT_INTEL_82801AB_IDE: 1632 case PCI_PRODUCT_INTEL_82801BA_IDE: 1633 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1634 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1635 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1636 case PCI_PRODUCT_INTEL_82801DB_IDE: 1637 case PCI_PRODUCT_INTEL_82801DBM_IDE: 1638 case PCI_PRODUCT_INTEL_82801EB_IDE: 1639 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1640 } 1641 } 1642 sc->sc_wdcdev.PIO_cap = 4; 1643 sc->sc_wdcdev.DMA_cap = 2; 1644 switch(sc->sc_pp->ide_product) { 1645 case PCI_PRODUCT_INTEL_82801AA_IDE: 1646 sc->sc_wdcdev.UDMA_cap = 4; 1647 break; 1648 case PCI_PRODUCT_INTEL_82801BA_IDE: 1649 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1650 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1651 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1652 case PCI_PRODUCT_INTEL_82801DB_IDE: 1653 case PCI_PRODUCT_INTEL_82801DBM_IDE: 1654 case PCI_PRODUCT_INTEL_82801EB_IDE: 1655 sc->sc_wdcdev.UDMA_cap = 5; 1656 break; 1657 default: 1658 sc->sc_wdcdev.UDMA_cap = 2; 1659 } 1660 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1661 sc->sc_wdcdev.set_modes = piix_setup_channel; 1662 else 1663 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1664 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1665 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1666 1667 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1668 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1669 DEBUG_PROBE); 1670 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1671 WDCDEBUG_PRINT((", sidetim=0x%x", 1672 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1673 DEBUG_PROBE); 1674 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1675 WDCDEBUG_PRINT((", udamreg 0x%x", 1676 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1677 DEBUG_PROBE); 1678 } 1679 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1680 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1681 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1682 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1683 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1684 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1685 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 1686 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 1687 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ) { 1688 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1689 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1690 DEBUG_PROBE); 1691 } 1692 1693 } 1694 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1695 1696 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1697 cp = &sc->pciide_channels[channel]; 1698 /* PIIX is compat-only */ 1699 if (pciide_chansetup(sc, channel, 0) == 0) 1700 continue; 1701 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1702 if ((PIIX_IDETIM_READ(idetim, channel) & 1703 PIIX_IDETIM_IDE) == 0) { 1704 #if 1 1705 aprint_normal("%s: %s channel ignored (disabled)\n", 1706 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1707 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 1708 continue; 1709 #else 1710 pcireg_t interface; 1711 1712 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1713 channel); 1714 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1715 idetim); 1716 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1717 sc->sc_tag, PCI_CLASS_REG)); 1718 aprint_normal("channel %d idetim=%08x interface=%02x\n", 1719 channel, idetim, interface); 1720 #endif 1721 } 1722 /* PIIX are compat-only pciide devices */ 1723 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1724 } 1725 1726 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1727 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1728 DEBUG_PROBE); 1729 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1730 WDCDEBUG_PRINT((", sidetim=0x%x", 1731 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1732 DEBUG_PROBE); 1733 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1734 WDCDEBUG_PRINT((", udamreg 0x%x", 1735 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1736 DEBUG_PROBE); 1737 } 1738 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1739 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1740 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1741 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1742 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1743 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1744 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 1745 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE) { 1746 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1747 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1748 DEBUG_PROBE); 1749 } 1750 } 1751 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1752 } 1753 1754 void 1755 piix_setup_channel(chp) 1756 struct channel_softc *chp; 1757 { 1758 u_int8_t mode[2], drive; 1759 u_int32_t oidetim, idetim, idedma_ctl; 1760 struct pciide_channel *cp = (struct pciide_channel*)chp; 1761 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1762 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1763 1764 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1765 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1766 idedma_ctl = 0; 1767 1768 /* set up new idetim: Enable IDE registers decode */ 1769 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1770 chp->channel); 1771 1772 /* setup DMA */ 1773 pciide_channel_dma_setup(cp); 1774 1775 /* 1776 * Here we have to mess up with drives mode: PIIX can't have 1777 * different timings for master and slave drives. 1778 * We need to find the best combination. 1779 */ 1780 1781 /* If both drives supports DMA, take the lower mode */ 1782 if ((drvp[0].drive_flags & DRIVE_DMA) && 1783 (drvp[1].drive_flags & DRIVE_DMA)) { 1784 mode[0] = mode[1] = 1785 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1786 drvp[0].DMA_mode = mode[0]; 1787 drvp[1].DMA_mode = mode[1]; 1788 goto ok; 1789 } 1790 /* 1791 * If only one drive supports DMA, use its mode, and 1792 * put the other one in PIO mode 0 if mode not compatible 1793 */ 1794 if (drvp[0].drive_flags & DRIVE_DMA) { 1795 mode[0] = drvp[0].DMA_mode; 1796 mode[1] = drvp[1].PIO_mode; 1797 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1798 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1799 mode[1] = drvp[1].PIO_mode = 0; 1800 goto ok; 1801 } 1802 if (drvp[1].drive_flags & DRIVE_DMA) { 1803 mode[1] = drvp[1].DMA_mode; 1804 mode[0] = drvp[0].PIO_mode; 1805 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1806 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1807 mode[0] = drvp[0].PIO_mode = 0; 1808 goto ok; 1809 } 1810 /* 1811 * If both drives are not DMA, takes the lower mode, unless 1812 * one of them is PIO mode < 2 1813 */ 1814 if (drvp[0].PIO_mode < 2) { 1815 mode[0] = drvp[0].PIO_mode = 0; 1816 mode[1] = drvp[1].PIO_mode; 1817 } else if (drvp[1].PIO_mode < 2) { 1818 mode[1] = drvp[1].PIO_mode = 0; 1819 mode[0] = drvp[0].PIO_mode; 1820 } else { 1821 mode[0] = mode[1] = 1822 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1823 drvp[0].PIO_mode = mode[0]; 1824 drvp[1].PIO_mode = mode[1]; 1825 } 1826 ok: /* The modes are setup */ 1827 for (drive = 0; drive < 2; drive++) { 1828 if (drvp[drive].drive_flags & DRIVE_DMA) { 1829 idetim |= piix_setup_idetim_timings( 1830 mode[drive], 1, chp->channel); 1831 goto end; 1832 } 1833 } 1834 /* If we are there, none of the drives are DMA */ 1835 if (mode[0] >= 2) 1836 idetim |= piix_setup_idetim_timings( 1837 mode[0], 0, chp->channel); 1838 else 1839 idetim |= piix_setup_idetim_timings( 1840 mode[1], 0, chp->channel); 1841 end: /* 1842 * timing mode is now set up in the controller. Enable 1843 * it per-drive 1844 */ 1845 for (drive = 0; drive < 2; drive++) { 1846 /* If no drive, skip */ 1847 if ((drvp[drive].drive_flags & DRIVE) == 0) 1848 continue; 1849 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1850 if (drvp[drive].drive_flags & DRIVE_DMA) 1851 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1852 } 1853 if (idedma_ctl != 0) { 1854 /* Add software bits in status register */ 1855 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1856 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1857 idedma_ctl); 1858 } 1859 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1860 } 1861 1862 void 1863 piix3_4_setup_channel(chp) 1864 struct channel_softc *chp; 1865 { 1866 struct ata_drive_datas *drvp; 1867 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1868 struct pciide_channel *cp = (struct pciide_channel*)chp; 1869 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1870 int drive; 1871 int channel = chp->channel; 1872 1873 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1874 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1875 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1876 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1877 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1878 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1879 PIIX_SIDETIM_RTC_MASK(channel)); 1880 idedma_ctl = 0; 1881 1882 /* set up new idetim: Enable IDE registers decode */ 1883 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1884 1885 /* setup DMA if needed */ 1886 pciide_channel_dma_setup(cp); 1887 1888 for (drive = 0; drive < 2; drive++) { 1889 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1890 PIIX_UDMATIM_SET(0x3, channel, drive)); 1891 drvp = &chp->ch_drive[drive]; 1892 /* If no drive, skip */ 1893 if ((drvp->drive_flags & DRIVE) == 0) 1894 continue; 1895 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1896 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1897 goto pio; 1898 1899 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1900 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1901 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1902 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1903 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1904 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1905 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 1906 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 1907 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE) { 1908 ideconf |= PIIX_CONFIG_PINGPONG; 1909 } 1910 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1911 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1912 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1913 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1914 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 1915 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 1916 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE) { 1917 /* setup Ultra/100 */ 1918 if (drvp->UDMA_mode > 2 && 1919 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1920 drvp->UDMA_mode = 2; 1921 if (drvp->UDMA_mode > 4) { 1922 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1923 } else { 1924 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1925 if (drvp->UDMA_mode > 2) { 1926 ideconf |= PIIX_CONFIG_UDMA66(channel, 1927 drive); 1928 } else { 1929 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1930 drive); 1931 } 1932 } 1933 } 1934 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1935 /* setup Ultra/66 */ 1936 if (drvp->UDMA_mode > 2 && 1937 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1938 drvp->UDMA_mode = 2; 1939 if (drvp->UDMA_mode > 2) 1940 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1941 else 1942 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1943 } 1944 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1945 (drvp->drive_flags & DRIVE_UDMA)) { 1946 /* use Ultra/DMA */ 1947 drvp->drive_flags &= ~DRIVE_DMA; 1948 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1949 udmareg |= PIIX_UDMATIM_SET( 1950 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1951 } else { 1952 /* use Multiword DMA */ 1953 drvp->drive_flags &= ~DRIVE_UDMA; 1954 if (drive == 0) { 1955 idetim |= piix_setup_idetim_timings( 1956 drvp->DMA_mode, 1, channel); 1957 } else { 1958 sidetim |= piix_setup_sidetim_timings( 1959 drvp->DMA_mode, 1, channel); 1960 idetim =PIIX_IDETIM_SET(idetim, 1961 PIIX_IDETIM_SITRE, channel); 1962 } 1963 } 1964 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1965 1966 pio: /* use PIO mode */ 1967 idetim |= piix_setup_idetim_drvs(drvp); 1968 if (drive == 0) { 1969 idetim |= piix_setup_idetim_timings( 1970 drvp->PIO_mode, 0, channel); 1971 } else { 1972 sidetim |= piix_setup_sidetim_timings( 1973 drvp->PIO_mode, 0, channel); 1974 idetim =PIIX_IDETIM_SET(idetim, 1975 PIIX_IDETIM_SITRE, channel); 1976 } 1977 } 1978 if (idedma_ctl != 0) { 1979 /* Add software bits in status register */ 1980 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1981 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1982 idedma_ctl); 1983 } 1984 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1985 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1986 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1987 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1988 } 1989 1990 1991 /* setup ISP and RTC fields, based on mode */ 1992 static u_int32_t 1993 piix_setup_idetim_timings(mode, dma, channel) 1994 u_int8_t mode; 1995 u_int8_t dma; 1996 u_int8_t channel; 1997 { 1998 1999 if (dma) 2000 return PIIX_IDETIM_SET(0, 2001 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 2002 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 2003 channel); 2004 else 2005 return PIIX_IDETIM_SET(0, 2006 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 2007 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 2008 channel); 2009 } 2010 2011 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 2012 static u_int32_t 2013 piix_setup_idetim_drvs(drvp) 2014 struct ata_drive_datas *drvp; 2015 { 2016 u_int32_t ret = 0; 2017 struct channel_softc *chp = drvp->chnl_softc; 2018 u_int8_t channel = chp->channel; 2019 u_int8_t drive = drvp->drive; 2020 2021 /* 2022 * If drive is using UDMA, timings setups are independant 2023 * So just check DMA and PIO here. 2024 */ 2025 if (drvp->drive_flags & DRIVE_DMA) { 2026 /* if mode = DMA mode 0, use compatible timings */ 2027 if ((drvp->drive_flags & DRIVE_DMA) && 2028 drvp->DMA_mode == 0) { 2029 drvp->PIO_mode = 0; 2030 return ret; 2031 } 2032 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2033 /* 2034 * PIO and DMA timings are the same, use fast timings for PIO 2035 * too, else use compat timings. 2036 */ 2037 if ((piix_isp_pio[drvp->PIO_mode] != 2038 piix_isp_dma[drvp->DMA_mode]) || 2039 (piix_rtc_pio[drvp->PIO_mode] != 2040 piix_rtc_dma[drvp->DMA_mode])) 2041 drvp->PIO_mode = 0; 2042 /* if PIO mode <= 2, use compat timings for PIO */ 2043 if (drvp->PIO_mode <= 2) { 2044 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 2045 channel); 2046 return ret; 2047 } 2048 } 2049 2050 /* 2051 * Now setup PIO modes. If mode < 2, use compat timings. 2052 * Else enable fast timings. Enable IORDY and prefetch/post 2053 * if PIO mode >= 3. 2054 */ 2055 2056 if (drvp->PIO_mode < 2) 2057 return ret; 2058 2059 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2060 if (drvp->PIO_mode >= 3) { 2061 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 2062 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 2063 } 2064 return ret; 2065 } 2066 2067 /* setup values in SIDETIM registers, based on mode */ 2068 static u_int32_t 2069 piix_setup_sidetim_timings(mode, dma, channel) 2070 u_int8_t mode; 2071 u_int8_t dma; 2072 u_int8_t channel; 2073 { 2074 if (dma) 2075 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 2076 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 2077 else 2078 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 2079 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 2080 } 2081 2082 void 2083 amd7x6_chip_map(sc, pa) 2084 struct pciide_softc *sc; 2085 struct pci_attach_args *pa; 2086 { 2087 struct pciide_channel *cp; 2088 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2089 int channel; 2090 pcireg_t chanenable; 2091 bus_size_t cmdsize, ctlsize; 2092 2093 if (pciide_chipen(sc, pa) == 0) 2094 return; 2095 aprint_normal("%s: bus-master DMA support present", 2096 sc->sc_wdcdev.sc_dev.dv_xname); 2097 pciide_mapreg_dma(sc, pa); 2098 aprint_normal("\n"); 2099 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2100 WDC_CAPABILITY_MODE; 2101 if (sc->sc_dma_ok) { 2102 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2103 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2104 sc->sc_wdcdev.irqack = pciide_irqack; 2105 } 2106 sc->sc_wdcdev.PIO_cap = 4; 2107 sc->sc_wdcdev.DMA_cap = 2; 2108 2109 switch (sc->sc_pci_vendor) { 2110 case PCI_VENDOR_AMD: 2111 switch (sc->sc_pp->ide_product) { 2112 case PCI_PRODUCT_AMD_PBC766_IDE: 2113 case PCI_PRODUCT_AMD_PBC768_IDE: 2114 case PCI_PRODUCT_AMD_PBC8111_IDE: 2115 sc->sc_wdcdev.UDMA_cap = 5; 2116 break; 2117 default: 2118 sc->sc_wdcdev.UDMA_cap = 4; 2119 } 2120 sc->sc_amd_regbase = AMD7X6_AMD_REGBASE; 2121 break; 2122 2123 case PCI_VENDOR_NVIDIA: 2124 switch (sc->sc_pp->ide_product) { 2125 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 2126 sc->sc_wdcdev.UDMA_cap = 5; 2127 break; 2128 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 2129 sc->sc_wdcdev.UDMA_cap = 6; 2130 break; 2131 } 2132 sc->sc_amd_regbase = AMD7X6_NVIDIA_REGBASE; 2133 break; 2134 2135 default: 2136 panic("amd7x6_chip_map: unknown vendor"); 2137 } 2138 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 2139 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2140 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2141 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, 2142 AMD7X6_CHANSTATUS_EN(sc)); 2143 2144 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 2145 DEBUG_PROBE); 2146 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2147 cp = &sc->pciide_channels[channel]; 2148 if (pciide_chansetup(sc, channel, interface) == 0) 2149 continue; 2150 2151 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 2152 aprint_normal("%s: %s channel ignored (disabled)\n", 2153 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2154 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 2155 continue; 2156 } 2157 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2158 pciide_pci_intr); 2159 } 2160 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN(sc), 2161 chanenable); 2162 return; 2163 } 2164 2165 void 2166 amd7x6_setup_channel(chp) 2167 struct channel_softc *chp; 2168 { 2169 u_int32_t udmatim_reg, datatim_reg; 2170 u_int8_t idedma_ctl; 2171 int mode, drive; 2172 struct ata_drive_datas *drvp; 2173 struct pciide_channel *cp = (struct pciide_channel*)chp; 2174 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2175 #ifndef PCIIDE_AMD756_ENABLEDMA 2176 int rev = PCI_REVISION( 2177 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2178 #endif 2179 2180 idedma_ctl = 0; 2181 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc)); 2182 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc)); 2183 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2184 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2185 2186 /* setup DMA if needed */ 2187 pciide_channel_dma_setup(cp); 2188 2189 for (drive = 0; drive < 2; drive++) { 2190 drvp = &chp->ch_drive[drive]; 2191 /* If no drive, skip */ 2192 if ((drvp->drive_flags & DRIVE) == 0) 2193 continue; 2194 /* add timing values, setup DMA if needed */ 2195 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2196 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2197 mode = drvp->PIO_mode; 2198 goto pio; 2199 } 2200 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2201 (drvp->drive_flags & DRIVE_UDMA)) { 2202 /* use Ultra/DMA */ 2203 drvp->drive_flags &= ~DRIVE_DMA; 2204 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2205 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2206 AMD7X6_UDMA_TIME(chp->channel, drive, 2207 amd7x6_udma_tim[drvp->UDMA_mode]); 2208 /* can use PIO timings, MW DMA unused */ 2209 mode = drvp->PIO_mode; 2210 } else { 2211 /* use Multiword DMA, but only if revision is OK */ 2212 drvp->drive_flags &= ~DRIVE_UDMA; 2213 #ifndef PCIIDE_AMD756_ENABLEDMA 2214 /* 2215 * The workaround doesn't seem to be necessary 2216 * with all drives, so it can be disabled by 2217 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2218 * triggered. 2219 */ 2220 if (sc->sc_pci_vendor == PCI_VENDOR_AMD && 2221 sc->sc_pp->ide_product == 2222 PCI_PRODUCT_AMD_PBC756_IDE && 2223 AMD756_CHIPREV_DISABLEDMA(rev)) { 2224 aprint_normal( 2225 "%s:%d:%d: multi-word DMA disabled due " 2226 "to chip revision\n", 2227 sc->sc_wdcdev.sc_dev.dv_xname, 2228 chp->channel, drive); 2229 mode = drvp->PIO_mode; 2230 drvp->drive_flags &= ~DRIVE_DMA; 2231 goto pio; 2232 } 2233 #endif 2234 /* mode = min(pio, dma+2) */ 2235 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2236 mode = drvp->PIO_mode; 2237 else 2238 mode = drvp->DMA_mode + 2; 2239 } 2240 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2241 2242 pio: /* setup PIO mode */ 2243 if (mode <= 2) { 2244 drvp->DMA_mode = 0; 2245 drvp->PIO_mode = 0; 2246 mode = 0; 2247 } else { 2248 drvp->PIO_mode = mode; 2249 drvp->DMA_mode = mode - 2; 2250 } 2251 datatim_reg |= 2252 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2253 amd7x6_pio_set[mode]) | 2254 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2255 amd7x6_pio_rec[mode]); 2256 } 2257 if (idedma_ctl != 0) { 2258 /* Add software bits in status register */ 2259 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2260 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2261 idedma_ctl); 2262 } 2263 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc), datatim_reg); 2264 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc), udmatim_reg); 2265 } 2266 2267 void 2268 apollo_chip_map(sc, pa) 2269 struct pciide_softc *sc; 2270 struct pci_attach_args *pa; 2271 { 2272 struct pciide_channel *cp; 2273 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2274 int channel; 2275 u_int32_t ideconf; 2276 bus_size_t cmdsize, ctlsize; 2277 pcitag_t pcib_tag; 2278 pcireg_t pcib_id, pcib_class; 2279 2280 if (pciide_chipen(sc, pa) == 0) 2281 return; 2282 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2283 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2284 /* and read ID and rev of the ISA bridge */ 2285 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2286 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2287 aprint_normal(": VIA Technologies "); 2288 switch (PCI_PRODUCT(pcib_id)) { 2289 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2290 aprint_normal("VT82C586 (Apollo VP) "); 2291 if(PCI_REVISION(pcib_class) >= 0x02) { 2292 aprint_normal("ATA33 controller\n"); 2293 sc->sc_wdcdev.UDMA_cap = 2; 2294 } else { 2295 aprint_normal("controller\n"); 2296 sc->sc_wdcdev.UDMA_cap = 0; 2297 } 2298 break; 2299 case PCI_PRODUCT_VIATECH_VT82C596A: 2300 aprint_normal("VT82C596A (Apollo Pro) "); 2301 if (PCI_REVISION(pcib_class) >= 0x12) { 2302 aprint_normal("ATA66 controller\n"); 2303 sc->sc_wdcdev.UDMA_cap = 4; 2304 } else { 2305 aprint_normal("ATA33 controller\n"); 2306 sc->sc_wdcdev.UDMA_cap = 2; 2307 } 2308 break; 2309 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2310 aprint_normal("VT82C686A (Apollo KX133) "); 2311 if (PCI_REVISION(pcib_class) >= 0x40) { 2312 aprint_normal("ATA100 controller\n"); 2313 sc->sc_wdcdev.UDMA_cap = 5; 2314 } else { 2315 aprint_normal("ATA66 controller\n"); 2316 sc->sc_wdcdev.UDMA_cap = 4; 2317 } 2318 break; 2319 case PCI_PRODUCT_VIATECH_VT8231: 2320 aprint_normal("VT8231 ATA100 controller\n"); 2321 sc->sc_wdcdev.UDMA_cap = 5; 2322 break; 2323 case PCI_PRODUCT_VIATECH_VT8233: 2324 aprint_normal("VT8233 ATA100 controller\n"); 2325 sc->sc_wdcdev.UDMA_cap = 5; 2326 break; 2327 case PCI_PRODUCT_VIATECH_VT8233A: 2328 aprint_normal("VT8233A ATA133 controller\n"); 2329 sc->sc_wdcdev.UDMA_cap = 6; 2330 break; 2331 case PCI_PRODUCT_VIATECH_VT8235: 2332 aprint_normal("VT8235 ATA133 controller\n"); 2333 sc->sc_wdcdev.UDMA_cap = 6; 2334 break; 2335 case PCI_PRODUCT_VIATECH_VT8237_SATA: 2336 aprint_normal("VT8237 ATA133 controller\n"); 2337 sc->sc_wdcdev.UDMA_cap = 6; 2338 break; 2339 default: 2340 aprint_normal("unknown ATA controller\n"); 2341 sc->sc_wdcdev.UDMA_cap = 0; 2342 } 2343 2344 aprint_normal("%s: bus-master DMA support present", 2345 sc->sc_wdcdev.sc_dev.dv_xname); 2346 pciide_mapreg_dma(sc, pa); 2347 aprint_normal("\n"); 2348 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2349 WDC_CAPABILITY_MODE; 2350 if (sc->sc_dma_ok) { 2351 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2352 sc->sc_wdcdev.irqack = pciide_irqack; 2353 if (sc->sc_wdcdev.UDMA_cap > 0) 2354 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2355 } 2356 sc->sc_wdcdev.PIO_cap = 4; 2357 sc->sc_wdcdev.DMA_cap = 2; 2358 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2359 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2360 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2361 2362 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2363 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2364 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2365 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2366 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2367 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2368 DEBUG_PROBE); 2369 2370 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2371 cp = &sc->pciide_channels[channel]; 2372 if (pciide_chansetup(sc, channel, interface) == 0) 2373 continue; 2374 2375 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2376 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2377 aprint_normal("%s: %s channel ignored (disabled)\n", 2378 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2379 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 2380 continue; 2381 } 2382 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2383 pciide_pci_intr); 2384 } 2385 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2386 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2387 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2388 } 2389 2390 void 2391 apollo_setup_channel(chp) 2392 struct channel_softc *chp; 2393 { 2394 u_int32_t udmatim_reg, datatim_reg; 2395 u_int8_t idedma_ctl; 2396 int mode, drive; 2397 struct ata_drive_datas *drvp; 2398 struct pciide_channel *cp = (struct pciide_channel*)chp; 2399 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2400 2401 idedma_ctl = 0; 2402 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2403 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2404 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2405 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2406 2407 /* setup DMA if needed */ 2408 pciide_channel_dma_setup(cp); 2409 2410 for (drive = 0; drive < 2; drive++) { 2411 drvp = &chp->ch_drive[drive]; 2412 /* If no drive, skip */ 2413 if ((drvp->drive_flags & DRIVE) == 0) 2414 continue; 2415 /* add timing values, setup DMA if needed */ 2416 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2417 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2418 mode = drvp->PIO_mode; 2419 goto pio; 2420 } 2421 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2422 (drvp->drive_flags & DRIVE_UDMA)) { 2423 /* use Ultra/DMA */ 2424 drvp->drive_flags &= ~DRIVE_DMA; 2425 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2426 APO_UDMA_EN_MTH(chp->channel, drive); 2427 if (sc->sc_wdcdev.UDMA_cap == 6) { 2428 /* 8233a */ 2429 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2430 drive, apollo_udma133_tim[drvp->UDMA_mode]); 2431 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 2432 /* 686b */ 2433 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2434 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2435 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2436 /* 596b or 686a */ 2437 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2438 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2439 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2440 } else { 2441 /* 596a or 586b */ 2442 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2443 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2444 } 2445 /* can use PIO timings, MW DMA unused */ 2446 mode = drvp->PIO_mode; 2447 } else { 2448 /* use Multiword DMA */ 2449 drvp->drive_flags &= ~DRIVE_UDMA; 2450 /* mode = min(pio, dma+2) */ 2451 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2452 mode = drvp->PIO_mode; 2453 else 2454 mode = drvp->DMA_mode + 2; 2455 } 2456 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2457 2458 pio: /* setup PIO mode */ 2459 if (mode <= 2) { 2460 drvp->DMA_mode = 0; 2461 drvp->PIO_mode = 0; 2462 mode = 0; 2463 } else { 2464 drvp->PIO_mode = mode; 2465 drvp->DMA_mode = mode - 2; 2466 } 2467 datatim_reg |= 2468 APO_DATATIM_PULSE(chp->channel, drive, 2469 apollo_pio_set[mode]) | 2470 APO_DATATIM_RECOV(chp->channel, drive, 2471 apollo_pio_rec[mode]); 2472 } 2473 if (idedma_ctl != 0) { 2474 /* Add software bits in status register */ 2475 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2476 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2477 idedma_ctl); 2478 } 2479 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2480 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2481 } 2482 2483 void 2484 apollo_sata_chip_map(sc, pa) 2485 struct pciide_softc *sc; 2486 struct pci_attach_args *pa; 2487 { 2488 struct pciide_channel *cp; 2489 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2490 int channel; 2491 bus_size_t cmdsize, ctlsize; 2492 2493 if (pciide_chipen(sc, pa) == 0) 2494 return; 2495 2496 if ( interface == 0 ) { 2497 WDCDEBUG_PRINT(("apollo_sata_chip_map interface == 0\n"), 2498 DEBUG_PROBE); 2499 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2500 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2501 } 2502 2503 aprint_normal("%s: bus-master DMA support present", 2504 sc->sc_wdcdev.sc_dev.dv_xname); 2505 pciide_mapreg_dma(sc, pa); 2506 aprint_normal("\n"); 2507 2508 if (sc->sc_dma_ok) { 2509 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2510 sc->sc_wdcdev.irqack = pciide_irqack; 2511 } 2512 sc->sc_wdcdev.PIO_cap = 4; 2513 sc->sc_wdcdev.DMA_cap = 2; 2514 sc->sc_wdcdev.UDMA_cap = 6; 2515 2516 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2517 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2518 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2519 WDC_CAPABILITY_MODE; 2520 sc->sc_wdcdev.set_modes = sata_setup_channel; 2521 2522 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2523 cp = &sc->pciide_channels[channel]; 2524 if (pciide_chansetup(sc, channel, interface) == 0) 2525 continue; 2526 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2527 pciide_pci_intr); 2528 } 2529 } 2530 2531 void 2532 cmd_channel_map(pa, sc, channel) 2533 struct pci_attach_args *pa; 2534 struct pciide_softc *sc; 2535 int channel; 2536 { 2537 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2538 bus_size_t cmdsize, ctlsize; 2539 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2540 int interface, one_channel; 2541 2542 /* 2543 * The 0648/0649 can be told to identify as a RAID controller. 2544 * In this case, we have to fake interface 2545 */ 2546 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2547 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2548 PCIIDE_INTERFACE_SETTABLE(1); 2549 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2550 CMD_CONF_DSA1) 2551 interface |= PCIIDE_INTERFACE_PCI(0) | 2552 PCIIDE_INTERFACE_PCI(1); 2553 } else { 2554 interface = PCI_INTERFACE(pa->pa_class); 2555 } 2556 2557 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2558 cp->name = PCIIDE_CHANNEL_NAME(channel); 2559 cp->wdc_channel.channel = channel; 2560 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2561 2562 /* 2563 * Older CMD64X doesn't have independant channels 2564 */ 2565 switch (sc->sc_pp->ide_product) { 2566 case PCI_PRODUCT_CMDTECH_649: 2567 one_channel = 0; 2568 break; 2569 default: 2570 one_channel = 1; 2571 break; 2572 } 2573 2574 if (channel > 0 && one_channel) { 2575 cp->wdc_channel.ch_queue = 2576 sc->pciide_channels[0].wdc_channel.ch_queue; 2577 } else { 2578 cp->wdc_channel.ch_queue = 2579 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2580 } 2581 if (cp->wdc_channel.ch_queue == NULL) { 2582 aprint_error("%s %s channel: " 2583 "can't allocate memory for command queue", 2584 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2585 return; 2586 } 2587 2588 aprint_normal("%s: %s channel %s to %s mode\n", 2589 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2590 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2591 "configured" : "wired", 2592 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2593 "native-PCI" : "compatibility"); 2594 2595 /* 2596 * with a CMD PCI64x, if we get here, the first channel is enabled: 2597 * there's no way to disable the first channel without disabling 2598 * the whole device 2599 */ 2600 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2601 aprint_normal("%s: %s channel ignored (disabled)\n", 2602 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2603 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 2604 return; 2605 } 2606 2607 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2608 } 2609 2610 int 2611 cmd_pci_intr(arg) 2612 void *arg; 2613 { 2614 struct pciide_softc *sc = arg; 2615 struct pciide_channel *cp; 2616 struct channel_softc *wdc_cp; 2617 int i, rv, crv; 2618 u_int32_t priirq, secirq; 2619 2620 rv = 0; 2621 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2622 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2623 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2624 cp = &sc->pciide_channels[i]; 2625 wdc_cp = &cp->wdc_channel; 2626 /* If a compat channel skip. */ 2627 if (cp->compat) 2628 continue; 2629 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2630 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2631 crv = wdcintr(wdc_cp); 2632 if (crv == 0) 2633 printf("%s:%d: bogus intr\n", 2634 sc->sc_wdcdev.sc_dev.dv_xname, i); 2635 else 2636 rv = 1; 2637 } 2638 } 2639 return rv; 2640 } 2641 2642 void 2643 cmd_chip_map(sc, pa) 2644 struct pciide_softc *sc; 2645 struct pci_attach_args *pa; 2646 { 2647 int channel; 2648 2649 /* 2650 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2651 * and base adresses registers can be disabled at 2652 * hardware level. In this case, the device is wired 2653 * in compat mode and its first channel is always enabled, 2654 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2655 * In fact, it seems that the first channel of the CMD PCI0640 2656 * can't be disabled. 2657 */ 2658 2659 #ifdef PCIIDE_CMD064x_DISABLE 2660 if (pciide_chipen(sc, pa) == 0) 2661 return; 2662 #endif 2663 2664 aprint_normal("%s: hardware does not support DMA\n", 2665 sc->sc_wdcdev.sc_dev.dv_xname); 2666 sc->sc_dma_ok = 0; 2667 2668 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2669 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2670 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2671 2672 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2673 cmd_channel_map(pa, sc, channel); 2674 } 2675 } 2676 2677 void 2678 cmd0643_9_chip_map(sc, pa) 2679 struct pciide_softc *sc; 2680 struct pci_attach_args *pa; 2681 { 2682 struct pciide_channel *cp; 2683 int channel; 2684 pcireg_t rev = PCI_REVISION(pa->pa_class); 2685 2686 /* 2687 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2688 * and base adresses registers can be disabled at 2689 * hardware level. In this case, the device is wired 2690 * in compat mode and its first channel is always enabled, 2691 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2692 * In fact, it seems that the first channel of the CMD PCI0640 2693 * can't be disabled. 2694 */ 2695 2696 #ifdef PCIIDE_CMD064x_DISABLE 2697 if (pciide_chipen(sc, pa) == 0) 2698 return; 2699 #endif 2700 aprint_normal("%s: bus-master DMA support present", 2701 sc->sc_wdcdev.sc_dev.dv_xname); 2702 pciide_mapreg_dma(sc, pa); 2703 aprint_normal("\n"); 2704 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2705 WDC_CAPABILITY_MODE; 2706 if (sc->sc_dma_ok) { 2707 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2708 switch (sc->sc_pp->ide_product) { 2709 case PCI_PRODUCT_CMDTECH_649: 2710 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2711 sc->sc_wdcdev.UDMA_cap = 5; 2712 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2713 break; 2714 case PCI_PRODUCT_CMDTECH_648: 2715 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2716 sc->sc_wdcdev.UDMA_cap = 4; 2717 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2718 break; 2719 case PCI_PRODUCT_CMDTECH_646: 2720 if (rev >= CMD0646U2_REV) { 2721 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2722 sc->sc_wdcdev.UDMA_cap = 2; 2723 } else if (rev >= CMD0646U_REV) { 2724 /* 2725 * Linux's driver claims that the 646U is broken 2726 * with UDMA. Only enable it if we know what we're 2727 * doing 2728 */ 2729 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2730 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2731 sc->sc_wdcdev.UDMA_cap = 2; 2732 #endif 2733 /* explicitly disable UDMA */ 2734 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2735 CMD_UDMATIM(0), 0); 2736 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2737 CMD_UDMATIM(1), 0); 2738 } 2739 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2740 break; 2741 default: 2742 sc->sc_wdcdev.irqack = pciide_irqack; 2743 } 2744 } 2745 2746 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2747 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2748 sc->sc_wdcdev.PIO_cap = 4; 2749 sc->sc_wdcdev.DMA_cap = 2; 2750 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2751 2752 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2753 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2754 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2755 DEBUG_PROBE); 2756 2757 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2758 cp = &sc->pciide_channels[channel]; 2759 cmd_channel_map(pa, sc, channel); 2760 } 2761 /* 2762 * note - this also makes sure we clear the irq disable and reset 2763 * bits 2764 */ 2765 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2766 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2767 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2768 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2769 DEBUG_PROBE); 2770 } 2771 2772 void 2773 cmd0643_9_setup_channel(chp) 2774 struct channel_softc *chp; 2775 { 2776 struct ata_drive_datas *drvp; 2777 u_int8_t tim; 2778 u_int32_t idedma_ctl, udma_reg; 2779 int drive; 2780 struct pciide_channel *cp = (struct pciide_channel*)chp; 2781 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2782 2783 idedma_ctl = 0; 2784 /* setup DMA if needed */ 2785 pciide_channel_dma_setup(cp); 2786 2787 for (drive = 0; drive < 2; drive++) { 2788 drvp = &chp->ch_drive[drive]; 2789 /* If no drive, skip */ 2790 if ((drvp->drive_flags & DRIVE) == 0) 2791 continue; 2792 /* add timing values, setup DMA if needed */ 2793 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2794 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2795 if (drvp->drive_flags & DRIVE_UDMA) { 2796 /* UltraDMA on a 646U2, 0648 or 0649 */ 2797 drvp->drive_flags &= ~DRIVE_DMA; 2798 udma_reg = pciide_pci_read(sc->sc_pc, 2799 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2800 if (drvp->UDMA_mode > 2 && 2801 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2802 CMD_BICSR) & 2803 CMD_BICSR_80(chp->channel)) == 0) 2804 drvp->UDMA_mode = 2; 2805 if (drvp->UDMA_mode > 2) 2806 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2807 else if (sc->sc_wdcdev.UDMA_cap > 2) 2808 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2809 udma_reg |= CMD_UDMATIM_UDMA(drive); 2810 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2811 CMD_UDMATIM_TIM_OFF(drive)); 2812 udma_reg |= 2813 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2814 CMD_UDMATIM_TIM_OFF(drive)); 2815 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2816 CMD_UDMATIM(chp->channel), udma_reg); 2817 } else { 2818 /* 2819 * use Multiword DMA. 2820 * Timings will be used for both PIO and DMA, 2821 * so adjust DMA mode if needed 2822 * if we have a 0646U2/8/9, turn off UDMA 2823 */ 2824 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2825 udma_reg = pciide_pci_read(sc->sc_pc, 2826 sc->sc_tag, 2827 CMD_UDMATIM(chp->channel)); 2828 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2829 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2830 CMD_UDMATIM(chp->channel), 2831 udma_reg); 2832 } 2833 if (drvp->PIO_mode >= 3 && 2834 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2835 drvp->DMA_mode = drvp->PIO_mode - 2; 2836 } 2837 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2838 } 2839 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2840 } 2841 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2842 CMD_DATA_TIM(chp->channel, drive), tim); 2843 } 2844 if (idedma_ctl != 0) { 2845 /* Add software bits in status register */ 2846 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2847 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2848 idedma_ctl); 2849 } 2850 } 2851 2852 void 2853 cmd646_9_irqack(chp) 2854 struct channel_softc *chp; 2855 { 2856 u_int32_t priirq, secirq; 2857 struct pciide_channel *cp = (struct pciide_channel*)chp; 2858 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2859 2860 if (chp->channel == 0) { 2861 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2862 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2863 } else { 2864 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2865 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2866 } 2867 pciide_irqack(chp); 2868 } 2869 2870 void 2871 cmd680_chip_map(sc, pa) 2872 struct pciide_softc *sc; 2873 struct pci_attach_args *pa; 2874 { 2875 struct pciide_channel *cp; 2876 int channel; 2877 2878 if (pciide_chipen(sc, pa) == 0) 2879 return; 2880 aprint_normal("%s: bus-master DMA support present", 2881 sc->sc_wdcdev.sc_dev.dv_xname); 2882 pciide_mapreg_dma(sc, pa); 2883 aprint_normal("\n"); 2884 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2885 WDC_CAPABILITY_MODE; 2886 if (sc->sc_dma_ok) { 2887 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2888 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2889 sc->sc_wdcdev.UDMA_cap = 6; 2890 sc->sc_wdcdev.irqack = pciide_irqack; 2891 } 2892 2893 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2894 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2895 sc->sc_wdcdev.PIO_cap = 4; 2896 sc->sc_wdcdev.DMA_cap = 2; 2897 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 2898 2899 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 2900 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 2901 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 2902 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 2903 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2904 cp = &sc->pciide_channels[channel]; 2905 cmd680_channel_map(pa, sc, channel); 2906 } 2907 } 2908 2909 void 2910 cmd680_channel_map(pa, sc, channel) 2911 struct pci_attach_args *pa; 2912 struct pciide_softc *sc; 2913 int channel; 2914 { 2915 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2916 bus_size_t cmdsize, ctlsize; 2917 int interface, i, reg; 2918 static const u_int8_t init_val[] = 2919 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 2920 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 2921 2922 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2923 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2924 PCIIDE_INTERFACE_SETTABLE(1); 2925 interface |= PCIIDE_INTERFACE_PCI(0) | 2926 PCIIDE_INTERFACE_PCI(1); 2927 } else { 2928 interface = PCI_INTERFACE(pa->pa_class); 2929 } 2930 2931 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2932 cp->name = PCIIDE_CHANNEL_NAME(channel); 2933 cp->wdc_channel.channel = channel; 2934 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2935 2936 cp->wdc_channel.ch_queue = 2937 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2938 if (cp->wdc_channel.ch_queue == NULL) { 2939 aprint_error("%s %s channel: " 2940 "can't allocate memory for command queue", 2941 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2942 return; 2943 } 2944 2945 /* XXX */ 2946 reg = 0xa2 + channel * 16; 2947 for (i = 0; i < sizeof(init_val); i++) 2948 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 2949 2950 aprint_normal("%s: %s channel %s to %s mode\n", 2951 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2952 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2953 "configured" : "wired", 2954 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2955 "native-PCI" : "compatibility"); 2956 2957 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 2958 } 2959 2960 void 2961 cmd680_setup_channel(chp) 2962 struct channel_softc *chp; 2963 { 2964 struct ata_drive_datas *drvp; 2965 u_int8_t mode, off, scsc; 2966 u_int16_t val; 2967 u_int32_t idedma_ctl; 2968 int drive; 2969 struct pciide_channel *cp = (struct pciide_channel*)chp; 2970 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2971 pci_chipset_tag_t pc = sc->sc_pc; 2972 pcitag_t pa = sc->sc_tag; 2973 static const u_int8_t udma2_tbl[] = 2974 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 2975 static const u_int8_t udma_tbl[] = 2976 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 2977 static const u_int16_t dma_tbl[] = 2978 { 0x2208, 0x10c2, 0x10c1 }; 2979 static const u_int16_t pio_tbl[] = 2980 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 2981 2982 idedma_ctl = 0; 2983 pciide_channel_dma_setup(cp); 2984 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 2985 2986 for (drive = 0; drive < 2; drive++) { 2987 drvp = &chp->ch_drive[drive]; 2988 /* If no drive, skip */ 2989 if ((drvp->drive_flags & DRIVE) == 0) 2990 continue; 2991 mode &= ~(0x03 << (drive * 4)); 2992 if (drvp->drive_flags & DRIVE_UDMA) { 2993 drvp->drive_flags &= ~DRIVE_DMA; 2994 off = 0xa0 + chp->channel * 16; 2995 if (drvp->UDMA_mode > 2 && 2996 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 2997 drvp->UDMA_mode = 2; 2998 scsc = pciide_pci_read(pc, pa, 0x8a); 2999 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 3000 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 3001 scsc = pciide_pci_read(pc, pa, 0x8a); 3002 if ((scsc & 0x30) == 0) 3003 drvp->UDMA_mode = 5; 3004 } 3005 mode |= 0x03 << (drive * 4); 3006 off = 0xac + chp->channel * 16 + drive * 2; 3007 val = pciide_pci_read(pc, pa, off) & ~0x3f; 3008 if (scsc & 0x30) 3009 val |= udma2_tbl[drvp->UDMA_mode]; 3010 else 3011 val |= udma_tbl[drvp->UDMA_mode]; 3012 pciide_pci_write(pc, pa, off, val); 3013 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3014 } else if (drvp->drive_flags & DRIVE_DMA) { 3015 mode |= 0x02 << (drive * 4); 3016 off = 0xa8 + chp->channel * 16 + drive * 2; 3017 val = dma_tbl[drvp->DMA_mode]; 3018 pciide_pci_write(pc, pa, off, val & 0xff); 3019 pciide_pci_write(pc, pa, off, val >> 8); 3020 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3021 } else { 3022 mode |= 0x01 << (drive * 4); 3023 off = 0xa4 + chp->channel * 16 + drive * 2; 3024 val = pio_tbl[drvp->PIO_mode]; 3025 pciide_pci_write(pc, pa, off, val & 0xff); 3026 pciide_pci_write(pc, pa, off, val >> 8); 3027 } 3028 } 3029 3030 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 3031 if (idedma_ctl != 0) { 3032 /* Add software bits in status register */ 3033 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3034 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3035 idedma_ctl); 3036 } 3037 } 3038 3039 void 3040 cmd3112_chip_map(sc, pa) 3041 struct pciide_softc *sc; 3042 struct pci_attach_args *pa; 3043 { 3044 struct pciide_channel *cp; 3045 bus_size_t cmdsize, ctlsize; 3046 pcireg_t interface; 3047 int channel; 3048 3049 if (pciide_chipen(sc, pa) == 0) 3050 return; 3051 3052 aprint_normal("%s: bus-master DMA support present", 3053 sc->sc_wdcdev.sc_dev.dv_xname); 3054 pciide_mapreg_dma(sc, pa); 3055 aprint_normal("\n"); 3056 3057 /* 3058 * Rev. <= 0x01 of the 3112 have a bug that can cause data 3059 * corruption if DMA transfers cross an 8K boundary. This is 3060 * apparently hard to tickle, but we'll go ahead and play it 3061 * safe. 3062 */ 3063 if (PCI_REVISION(pa->pa_class) <= 0x01) { 3064 sc->sc_dma_maxsegsz = 8192; 3065 sc->sc_dma_boundary = 8192; 3066 } 3067 3068 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3069 WDC_CAPABILITY_MODE; 3070 sc->sc_wdcdev.PIO_cap = 4; 3071 if (sc->sc_dma_ok) { 3072 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3073 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3074 sc->sc_wdcdev.irqack = pciide_irqack; 3075 sc->sc_wdcdev.DMA_cap = 2; 3076 sc->sc_wdcdev.UDMA_cap = 6; 3077 } 3078 sc->sc_wdcdev.set_modes = cmd3112_setup_channel; 3079 3080 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3081 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3082 3083 /* 3084 * The 3112 can be told to identify as a RAID controller. 3085 * In this case, we have to fake interface 3086 */ 3087 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3088 interface = PCI_INTERFACE(pa->pa_class); 3089 } else { 3090 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3091 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3092 } 3093 3094 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3095 cp = &sc->pciide_channels[channel]; 3096 if (pciide_chansetup(sc, channel, interface) == 0) 3097 continue; 3098 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3099 pciide_pci_intr); 3100 } 3101 } 3102 3103 void 3104 cmd3112_setup_channel(chp) 3105 struct channel_softc *chp; 3106 { 3107 struct ata_drive_datas *drvp; 3108 int drive; 3109 u_int32_t idedma_ctl, dtm; 3110 struct pciide_channel *cp = (struct pciide_channel*)chp; 3111 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 3112 3113 /* setup DMA if needed */ 3114 pciide_channel_dma_setup(cp); 3115 3116 idedma_ctl = 0; 3117 dtm = 0; 3118 3119 for (drive = 0; drive < 2; drive++) { 3120 drvp = &chp->ch_drive[drive]; 3121 /* If no drive, skip */ 3122 if ((drvp->drive_flags & DRIVE) == 0) 3123 continue; 3124 if (drvp->drive_flags & DRIVE_UDMA) { 3125 /* use Ultra/DMA */ 3126 drvp->drive_flags &= ~DRIVE_DMA; 3127 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3128 dtm |= DTM_IDEx_DMA; 3129 } else if (drvp->drive_flags & DRIVE_DMA) { 3130 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3131 dtm |= DTM_IDEx_DMA; 3132 } else { 3133 dtm |= DTM_IDEx_PIO; 3134 } 3135 } 3136 3137 /* 3138 * Nothing to do to setup modes; it is meaningless in S-ATA 3139 * (but many S-ATA drives still want to get the SET_FEATURE 3140 * command). 3141 */ 3142 if (idedma_ctl != 0) { 3143 /* Add software bits in status register */ 3144 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3145 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3146 idedma_ctl); 3147 } 3148 pci_conf_write(sc->sc_pc, sc->sc_tag, 3149 chp->channel == 0 ? SII3112_DTM_IDE0 : SII3112_DTM_IDE1, dtm); 3150 } 3151 3152 void 3153 cy693_chip_map(sc, pa) 3154 struct pciide_softc *sc; 3155 struct pci_attach_args *pa; 3156 { 3157 struct pciide_channel *cp; 3158 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3159 bus_size_t cmdsize, ctlsize; 3160 3161 if (pciide_chipen(sc, pa) == 0) 3162 return; 3163 /* 3164 * this chip has 2 PCI IDE functions, one for primary and one for 3165 * secondary. So we need to call pciide_mapregs_compat() with 3166 * the real channel 3167 */ 3168 if (pa->pa_function == 1) { 3169 sc->sc_cy_compatchan = 0; 3170 } else if (pa->pa_function == 2) { 3171 sc->sc_cy_compatchan = 1; 3172 } else { 3173 aprint_error("%s: unexpected PCI function %d\n", 3174 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3175 return; 3176 } 3177 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 3178 aprint_normal("%s: bus-master DMA support present", 3179 sc->sc_wdcdev.sc_dev.dv_xname); 3180 pciide_mapreg_dma(sc, pa); 3181 } else { 3182 aprint_normal("%s: hardware does not support DMA", 3183 sc->sc_wdcdev.sc_dev.dv_xname); 3184 sc->sc_dma_ok = 0; 3185 } 3186 aprint_normal("\n"); 3187 3188 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 3189 if (sc->sc_cy_handle == NULL) { 3190 aprint_error("%s: unable to map hyperCache control registers\n", 3191 sc->sc_wdcdev.sc_dev.dv_xname); 3192 sc->sc_dma_ok = 0; 3193 } 3194 3195 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3196 WDC_CAPABILITY_MODE; 3197 if (sc->sc_dma_ok) { 3198 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3199 sc->sc_wdcdev.irqack = pciide_irqack; 3200 } 3201 sc->sc_wdcdev.PIO_cap = 4; 3202 sc->sc_wdcdev.DMA_cap = 2; 3203 sc->sc_wdcdev.set_modes = cy693_setup_channel; 3204 3205 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3206 sc->sc_wdcdev.nchannels = 1; 3207 3208 /* Only one channel for this chip; if we are here it's enabled */ 3209 cp = &sc->pciide_channels[0]; 3210 sc->wdc_chanarray[0] = &cp->wdc_channel; 3211 cp->name = PCIIDE_CHANNEL_NAME(0); 3212 cp->wdc_channel.channel = 0; 3213 cp->wdc_channel.wdc = &sc->sc_wdcdev; 3214 cp->wdc_channel.ch_queue = 3215 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 3216 if (cp->wdc_channel.ch_queue == NULL) { 3217 aprint_error("%s primary channel: " 3218 "can't allocate memory for command queue", 3219 sc->sc_wdcdev.sc_dev.dv_xname); 3220 return; 3221 } 3222 aprint_normal("%s: primary channel %s to ", 3223 sc->sc_wdcdev.sc_dev.dv_xname, 3224 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 3225 "configured" : "wired"); 3226 if (interface & PCIIDE_INTERFACE_PCI(0)) { 3227 aprint_normal("native-PCI mode\n"); 3228 pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 3229 pciide_pci_intr); 3230 } else { 3231 aprint_normal("compatibility mode\n"); 3232 pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, &cmdsize, 3233 &ctlsize); 3234 } 3235 } 3236 3237 void 3238 cy693_setup_channel(chp) 3239 struct channel_softc *chp; 3240 { 3241 struct ata_drive_datas *drvp; 3242 int drive; 3243 u_int32_t cy_cmd_ctrl; 3244 u_int32_t idedma_ctl; 3245 struct pciide_channel *cp = (struct pciide_channel*)chp; 3246 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3247 int dma_mode = -1; 3248 3249 cy_cmd_ctrl = idedma_ctl = 0; 3250 3251 /* setup DMA if needed */ 3252 pciide_channel_dma_setup(cp); 3253 3254 for (drive = 0; drive < 2; drive++) { 3255 drvp = &chp->ch_drive[drive]; 3256 /* If no drive, skip */ 3257 if ((drvp->drive_flags & DRIVE) == 0) 3258 continue; 3259 /* add timing values, setup DMA if needed */ 3260 if (drvp->drive_flags & DRIVE_DMA) { 3261 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3262 /* use Multiword DMA */ 3263 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 3264 dma_mode = drvp->DMA_mode; 3265 } 3266 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3267 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 3268 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3269 CY_CMD_CTRL_IOW_REC_OFF(drive)); 3270 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3271 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 3272 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3273 CY_CMD_CTRL_IOR_REC_OFF(drive)); 3274 } 3275 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 3276 chp->ch_drive[0].DMA_mode = dma_mode; 3277 chp->ch_drive[1].DMA_mode = dma_mode; 3278 3279 if (dma_mode == -1) 3280 dma_mode = 0; 3281 3282 if (sc->sc_cy_handle != NULL) { 3283 /* Note: `multiple' is implied. */ 3284 cy82c693_write(sc->sc_cy_handle, 3285 (sc->sc_cy_compatchan == 0) ? 3286 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 3287 } 3288 3289 if (idedma_ctl != 0) { 3290 /* Add software bits in status register */ 3291 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3292 IDEDMA_CTL, idedma_ctl); 3293 } 3294 } 3295 3296 static struct sis_hostbr_type { 3297 u_int16_t id; 3298 u_int8_t rev; 3299 u_int8_t udma_mode; 3300 char *name; 3301 u_int8_t type; 3302 #define SIS_TYPE_NOUDMA 0 3303 #define SIS_TYPE_66 1 3304 #define SIS_TYPE_100OLD 2 3305 #define SIS_TYPE_100NEW 3 3306 #define SIS_TYPE_133OLD 4 3307 #define SIS_TYPE_133NEW 5 3308 #define SIS_TYPE_SOUTH 6 3309 } sis_hostbr_type[] = { 3310 /* Most infos here are from sos (at) freebsd.org */ 3311 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 3312 #if 0 3313 /* 3314 * controllers associated to a rev 0x2 530 Host to PCI Bridge 3315 * have problems with UDMA (info provided by Christos) 3316 */ 3317 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 3318 #endif 3319 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 3320 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 3321 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 3322 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 3323 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 3324 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 3325 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 3326 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 3327 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 3328 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 3329 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 3330 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 3331 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 3332 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 3333 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 3334 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 3335 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 3336 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 3337 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 3338 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 3339 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 3340 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 3341 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 3342 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 3343 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 3344 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 3345 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 3346 /* 3347 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 3348 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 3349 */ 3350 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 3351 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 3352 }; 3353 3354 static struct sis_hostbr_type *sis_hostbr_type_match; 3355 3356 static int 3357 sis_hostbr_match(pa) 3358 struct pci_attach_args *pa; 3359 { 3360 int i; 3361 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 3362 return 0; 3363 sis_hostbr_type_match = NULL; 3364 for (i = 0; 3365 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 3366 i++) { 3367 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 3368 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 3369 sis_hostbr_type_match = &sis_hostbr_type[i]; 3370 } 3371 return (sis_hostbr_type_match != NULL); 3372 } 3373 3374 static int sis_south_match(pa) 3375 struct pci_attach_args *pa; 3376 { 3377 return(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 3378 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 3379 PCI_REVISION(pa->pa_class) >= 0x10); 3380 } 3381 3382 void 3383 sis_chip_map(sc, pa) 3384 struct pciide_softc *sc; 3385 struct pci_attach_args *pa; 3386 { 3387 struct pciide_channel *cp; 3388 int channel; 3389 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 3390 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3391 pcireg_t rev = PCI_REVISION(pa->pa_class); 3392 bus_size_t cmdsize, ctlsize; 3393 3394 if (pciide_chipen(sc, pa) == 0) 3395 return; 3396 aprint_normal(": Silicon Integrated System "); 3397 pci_find_device(NULL, sis_hostbr_match); 3398 if (sis_hostbr_type_match) { 3399 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 3400 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 3401 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3402 SIS_REG_57) & 0x7f); 3403 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 3404 PCI_ID_REG)) == SIS_PRODUCT_5518) { 3405 aprint_normal("96X UDMA%d", 3406 sis_hostbr_type_match->udma_mode); 3407 sc->sis_type = SIS_TYPE_133NEW; 3408 sc->sc_wdcdev.UDMA_cap = 3409 sis_hostbr_type_match->udma_mode; 3410 } else { 3411 if (pci_find_device(NULL, sis_south_match)) { 3412 sc->sis_type = SIS_TYPE_133OLD; 3413 sc->sc_wdcdev.UDMA_cap = 3414 sis_hostbr_type_match->udma_mode; 3415 } else { 3416 sc->sis_type = SIS_TYPE_100NEW; 3417 sc->sc_wdcdev.UDMA_cap = 3418 sis_hostbr_type_match->udma_mode; 3419 } 3420 } 3421 } else { 3422 sc->sis_type = sis_hostbr_type_match->type; 3423 sc->sc_wdcdev.UDMA_cap = 3424 sis_hostbr_type_match->udma_mode; 3425 } 3426 aprint_normal(sis_hostbr_type_match->name); 3427 } else { 3428 aprint_normal("5597/5598"); 3429 if (rev >= 0xd0) { 3430 sc->sc_wdcdev.UDMA_cap = 2; 3431 sc->sis_type = SIS_TYPE_66; 3432 } else { 3433 sc->sc_wdcdev.UDMA_cap = 0; 3434 sc->sis_type = SIS_TYPE_NOUDMA; 3435 } 3436 } 3437 aprint_normal(" IDE controller (rev. 0x%02x)\n", 3438 PCI_REVISION(pa->pa_class)); 3439 aprint_normal("%s: bus-master DMA support present", 3440 sc->sc_wdcdev.sc_dev.dv_xname); 3441 pciide_mapreg_dma(sc, pa); 3442 aprint_normal("\n"); 3443 3444 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3445 WDC_CAPABILITY_MODE; 3446 if (sc->sc_dma_ok) { 3447 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3448 sc->sc_wdcdev.irqack = pciide_irqack; 3449 if (sc->sis_type >= SIS_TYPE_66) 3450 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3451 } 3452 3453 sc->sc_wdcdev.PIO_cap = 4; 3454 sc->sc_wdcdev.DMA_cap = 2; 3455 3456 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3457 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3458 switch(sc->sis_type) { 3459 case SIS_TYPE_NOUDMA: 3460 case SIS_TYPE_66: 3461 case SIS_TYPE_100OLD: 3462 sc->sc_wdcdev.set_modes = sis_setup_channel; 3463 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 3464 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 3465 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 3466 break; 3467 case SIS_TYPE_100NEW: 3468 case SIS_TYPE_133OLD: 3469 sc->sc_wdcdev.set_modes = sis_setup_channel; 3470 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 3471 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 3472 break; 3473 case SIS_TYPE_133NEW: 3474 sc->sc_wdcdev.set_modes = sis96x_setup_channel; 3475 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 3476 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 3477 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 3478 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 3479 break; 3480 } 3481 3482 3483 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3484 cp = &sc->pciide_channels[channel]; 3485 if (pciide_chansetup(sc, channel, interface) == 0) 3486 continue; 3487 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 3488 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 3489 aprint_normal("%s: %s channel ignored (disabled)\n", 3490 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3491 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 3492 continue; 3493 } 3494 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3495 pciide_pci_intr); 3496 } 3497 } 3498 3499 void 3500 sis96x_setup_channel(chp) 3501 struct channel_softc *chp; 3502 { 3503 struct ata_drive_datas *drvp; 3504 int drive; 3505 u_int32_t sis_tim; 3506 u_int32_t idedma_ctl; 3507 int regtim; 3508 struct pciide_channel *cp = (struct pciide_channel*)chp; 3509 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3510 3511 sis_tim = 0; 3512 idedma_ctl = 0; 3513 /* setup DMA if needed */ 3514 pciide_channel_dma_setup(cp); 3515 3516 for (drive = 0; drive < 2; drive++) { 3517 regtim = SIS_TIM133( 3518 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 3519 chp->channel, drive); 3520 drvp = &chp->ch_drive[drive]; 3521 /* If no drive, skip */ 3522 if ((drvp->drive_flags & DRIVE) == 0) 3523 continue; 3524 /* add timing values, setup DMA if needed */ 3525 if (drvp->drive_flags & DRIVE_UDMA) { 3526 /* use Ultra/DMA */ 3527 drvp->drive_flags &= ~DRIVE_DMA; 3528 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3529 SIS96x_REG_CBL(chp->channel)) & SIS96x_REG_CBL_33) { 3530 if (drvp->UDMA_mode > 2) 3531 drvp->UDMA_mode = 2; 3532 } 3533 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 3534 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3535 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3536 } else if (drvp->drive_flags & DRIVE_DMA) { 3537 /* 3538 * use Multiword DMA 3539 * Timings will be used for both PIO and DMA, 3540 * so adjust DMA mode if needed 3541 */ 3542 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3543 drvp->PIO_mode = drvp->DMA_mode + 2; 3544 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3545 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3546 drvp->PIO_mode - 2 : 0; 3547 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 3548 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3549 } else { 3550 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3551 } 3552 WDCDEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 3553 "channel %d drive %d: 0x%x (reg 0x%x)\n", 3554 chp->channel, drive, sis_tim, regtim), DEBUG_PROBE); 3555 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 3556 } 3557 if (idedma_ctl != 0) { 3558 /* Add software bits in status register */ 3559 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3560 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3561 idedma_ctl); 3562 } 3563 } 3564 3565 void 3566 sis_setup_channel(chp) 3567 struct channel_softc *chp; 3568 { 3569 struct ata_drive_datas *drvp; 3570 int drive; 3571 u_int32_t sis_tim; 3572 u_int32_t idedma_ctl; 3573 struct pciide_channel *cp = (struct pciide_channel*)chp; 3574 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3575 3576 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 3577 "channel %d 0x%x\n", chp->channel, 3578 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 3579 DEBUG_PROBE); 3580 sis_tim = 0; 3581 idedma_ctl = 0; 3582 /* setup DMA if needed */ 3583 pciide_channel_dma_setup(cp); 3584 3585 for (drive = 0; drive < 2; drive++) { 3586 drvp = &chp->ch_drive[drive]; 3587 /* If no drive, skip */ 3588 if ((drvp->drive_flags & DRIVE) == 0) 3589 continue; 3590 /* add timing values, setup DMA if needed */ 3591 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3592 (drvp->drive_flags & DRIVE_UDMA) == 0) 3593 goto pio; 3594 3595 if (drvp->drive_flags & DRIVE_UDMA) { 3596 /* use Ultra/DMA */ 3597 drvp->drive_flags &= ~DRIVE_DMA; 3598 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3599 SIS_REG_CBL) & SIS_REG_CBL_33(chp->channel)) { 3600 if (drvp->UDMA_mode > 2) 3601 drvp->UDMA_mode = 2; 3602 } 3603 switch (sc->sis_type) { 3604 case SIS_TYPE_66: 3605 case SIS_TYPE_100OLD: 3606 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 3607 SIS_TIM66_UDMA_TIME_OFF(drive); 3608 break; 3609 case SIS_TYPE_100NEW: 3610 sis_tim |= 3611 sis_udma100new_tim[drvp->UDMA_mode] << 3612 SIS_TIM100_UDMA_TIME_OFF(drive); 3613 case SIS_TYPE_133OLD: 3614 sis_tim |= 3615 sis_udma133old_tim[drvp->UDMA_mode] << 3616 SIS_TIM100_UDMA_TIME_OFF(drive); 3617 break; 3618 default: 3619 aprint_error("unknown SiS IDE type %d\n", 3620 sc->sis_type); 3621 } 3622 } else { 3623 /* 3624 * use Multiword DMA 3625 * Timings will be used for both PIO and DMA, 3626 * so adjust DMA mode if needed 3627 */ 3628 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3629 drvp->PIO_mode = drvp->DMA_mode + 2; 3630 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3631 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3632 drvp->PIO_mode - 2 : 0; 3633 if (drvp->DMA_mode == 0) 3634 drvp->PIO_mode = 0; 3635 } 3636 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3637 pio: switch (sc->sis_type) { 3638 case SIS_TYPE_NOUDMA: 3639 case SIS_TYPE_66: 3640 case SIS_TYPE_100OLD: 3641 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3642 SIS_TIM66_ACT_OFF(drive); 3643 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3644 SIS_TIM66_REC_OFF(drive); 3645 break; 3646 case SIS_TYPE_100NEW: 3647 case SIS_TYPE_133OLD: 3648 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3649 SIS_TIM100_ACT_OFF(drive); 3650 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3651 SIS_TIM100_REC_OFF(drive); 3652 break; 3653 default: 3654 aprint_error("unknown SiS IDE type %d\n", 3655 sc->sis_type); 3656 } 3657 } 3658 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 3659 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 3660 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 3661 if (idedma_ctl != 0) { 3662 /* Add software bits in status register */ 3663 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3664 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3665 idedma_ctl); 3666 } 3667 } 3668 3669 void 3670 acer_chip_map(sc, pa) 3671 struct pciide_softc *sc; 3672 struct pci_attach_args *pa; 3673 { 3674 struct pciide_channel *cp; 3675 int channel; 3676 pcireg_t cr, interface; 3677 bus_size_t cmdsize, ctlsize; 3678 pcireg_t rev = PCI_REVISION(pa->pa_class); 3679 3680 if (pciide_chipen(sc, pa) == 0) 3681 return; 3682 aprint_normal("%s: bus-master DMA support present", 3683 sc->sc_wdcdev.sc_dev.dv_xname); 3684 pciide_mapreg_dma(sc, pa); 3685 aprint_normal("\n"); 3686 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3687 WDC_CAPABILITY_MODE; 3688 if (sc->sc_dma_ok) { 3689 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3690 if (rev >= 0x20) { 3691 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3692 if (rev >= 0xC4) 3693 sc->sc_wdcdev.UDMA_cap = 5; 3694 else if (rev >= 0xC2) 3695 sc->sc_wdcdev.UDMA_cap = 4; 3696 else 3697 sc->sc_wdcdev.UDMA_cap = 2; 3698 } 3699 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3700 sc->sc_wdcdev.irqack = pciide_irqack; 3701 } 3702 3703 sc->sc_wdcdev.PIO_cap = 4; 3704 sc->sc_wdcdev.DMA_cap = 2; 3705 sc->sc_wdcdev.set_modes = acer_setup_channel; 3706 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3707 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3708 3709 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3710 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3711 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3712 3713 /* Enable "microsoft register bits" R/W. */ 3714 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3715 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3716 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3717 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3718 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3719 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3720 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3721 ~ACER_CHANSTATUSREGS_RO); 3722 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3723 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3724 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3725 /* Don't use cr, re-read the real register content instead */ 3726 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3727 PCI_CLASS_REG)); 3728 3729 /* From linux: enable "Cable Detection" */ 3730 if (rev >= 0xC2) { 3731 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3732 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3733 | ACER_0x4B_CDETECT); 3734 } 3735 3736 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3737 cp = &sc->pciide_channels[channel]; 3738 if (pciide_chansetup(sc, channel, interface) == 0) 3739 continue; 3740 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3741 aprint_normal("%s: %s channel ignored (disabled)\n", 3742 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3743 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 3744 continue; 3745 } 3746 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3747 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3748 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3749 } 3750 } 3751 3752 void 3753 acer_setup_channel(chp) 3754 struct channel_softc *chp; 3755 { 3756 struct ata_drive_datas *drvp; 3757 int drive; 3758 u_int32_t acer_fifo_udma; 3759 u_int32_t idedma_ctl; 3760 struct pciide_channel *cp = (struct pciide_channel*)chp; 3761 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3762 3763 idedma_ctl = 0; 3764 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3765 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3766 acer_fifo_udma), DEBUG_PROBE); 3767 /* setup DMA if needed */ 3768 pciide_channel_dma_setup(cp); 3769 3770 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3771 DRIVE_UDMA) { /* check 80 pins cable */ 3772 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3773 ACER_0x4A_80PIN(chp->channel)) { 3774 if (chp->ch_drive[0].UDMA_mode > 2) 3775 chp->ch_drive[0].UDMA_mode = 2; 3776 if (chp->ch_drive[1].UDMA_mode > 2) 3777 chp->ch_drive[1].UDMA_mode = 2; 3778 } 3779 } 3780 3781 for (drive = 0; drive < 2; drive++) { 3782 drvp = &chp->ch_drive[drive]; 3783 /* If no drive, skip */ 3784 if ((drvp->drive_flags & DRIVE) == 0) 3785 continue; 3786 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3787 "channel %d drive %d 0x%x\n", chp->channel, drive, 3788 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3789 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3790 /* clear FIFO/DMA mode */ 3791 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3792 ACER_UDMA_EN(chp->channel, drive) | 3793 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3794 3795 /* add timing values, setup DMA if needed */ 3796 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3797 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3798 acer_fifo_udma |= 3799 ACER_FTH_OPL(chp->channel, drive, 0x1); 3800 goto pio; 3801 } 3802 3803 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3804 if (drvp->drive_flags & DRIVE_UDMA) { 3805 /* use Ultra/DMA */ 3806 drvp->drive_flags &= ~DRIVE_DMA; 3807 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3808 acer_fifo_udma |= 3809 ACER_UDMA_TIM(chp->channel, drive, 3810 acer_udma[drvp->UDMA_mode]); 3811 /* XXX disable if one drive < UDMA3 ? */ 3812 if (drvp->UDMA_mode >= 3) { 3813 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3814 ACER_0x4B, 3815 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3816 ACER_0x4B) | ACER_0x4B_UDMA66); 3817 } 3818 } else { 3819 /* 3820 * use Multiword DMA 3821 * Timings will be used for both PIO and DMA, 3822 * so adjust DMA mode if needed 3823 */ 3824 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3825 drvp->PIO_mode = drvp->DMA_mode + 2; 3826 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3827 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3828 drvp->PIO_mode - 2 : 0; 3829 if (drvp->DMA_mode == 0) 3830 drvp->PIO_mode = 0; 3831 } 3832 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3833 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3834 ACER_IDETIM(chp->channel, drive), 3835 acer_pio[drvp->PIO_mode]); 3836 } 3837 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3838 acer_fifo_udma), DEBUG_PROBE); 3839 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3840 if (idedma_ctl != 0) { 3841 /* Add software bits in status register */ 3842 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3843 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3844 idedma_ctl); 3845 } 3846 } 3847 3848 int 3849 acer_pci_intr(arg) 3850 void *arg; 3851 { 3852 struct pciide_softc *sc = arg; 3853 struct pciide_channel *cp; 3854 struct channel_softc *wdc_cp; 3855 int i, rv, crv; 3856 u_int32_t chids; 3857 3858 rv = 0; 3859 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3860 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3861 cp = &sc->pciide_channels[i]; 3862 wdc_cp = &cp->wdc_channel; 3863 /* If a compat channel skip. */ 3864 if (cp->compat) 3865 continue; 3866 if (chids & ACER_CHIDS_INT(i)) { 3867 crv = wdcintr(wdc_cp); 3868 if (crv == 0) 3869 printf("%s:%d: bogus intr\n", 3870 sc->sc_wdcdev.sc_dev.dv_xname, i); 3871 else 3872 rv = 1; 3873 } 3874 } 3875 return rv; 3876 } 3877 3878 void 3879 hpt_chip_map(sc, pa) 3880 struct pciide_softc *sc; 3881 struct pci_attach_args *pa; 3882 { 3883 struct pciide_channel *cp; 3884 int i, compatchan, revision; 3885 pcireg_t interface; 3886 bus_size_t cmdsize, ctlsize; 3887 3888 if (pciide_chipen(sc, pa) == 0) 3889 return; 3890 revision = PCI_REVISION(pa->pa_class); 3891 aprint_normal(": Triones/Highpoint "); 3892 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3893 aprint_normal("HPT374 IDE Controller\n"); 3894 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372) 3895 aprint_normal("HPT372 IDE Controller\n"); 3896 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 3897 if (revision == HPT372_REV) 3898 aprint_normal("HPT372 IDE Controller\n"); 3899 else if (revision == HPT370_REV) 3900 aprint_normal("HPT370 IDE Controller\n"); 3901 else if (revision == HPT370A_REV) 3902 aprint_normal("HPT370A IDE Controller\n"); 3903 else if (revision == HPT366_REV) 3904 aprint_normal("HPT366 IDE Controller\n"); 3905 else 3906 aprint_normal("unknown HPT IDE controller rev %d\n", 3907 revision); 3908 } else 3909 aprint_normal("unknown HPT IDE controller 0x%x\n", 3910 sc->sc_pp->ide_product); 3911 3912 /* 3913 * when the chip is in native mode it identifies itself as a 3914 * 'misc mass storage'. Fake interface in this case. 3915 */ 3916 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3917 interface = PCI_INTERFACE(pa->pa_class); 3918 } else { 3919 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3920 PCIIDE_INTERFACE_PCI(0); 3921 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3922 (revision == HPT370_REV || revision == HPT370A_REV || 3923 revision == HPT372_REV)) || 3924 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3925 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3926 interface |= PCIIDE_INTERFACE_PCI(1); 3927 } 3928 3929 aprint_normal("%s: bus-master DMA support present", 3930 sc->sc_wdcdev.sc_dev.dv_xname); 3931 pciide_mapreg_dma(sc, pa); 3932 aprint_normal("\n"); 3933 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3934 WDC_CAPABILITY_MODE; 3935 if (sc->sc_dma_ok) { 3936 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3937 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3938 sc->sc_wdcdev.irqack = pciide_irqack; 3939 } 3940 sc->sc_wdcdev.PIO_cap = 4; 3941 sc->sc_wdcdev.DMA_cap = 2; 3942 3943 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3944 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3945 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3946 revision == HPT366_REV) { 3947 sc->sc_wdcdev.UDMA_cap = 4; 3948 /* 3949 * The 366 has 2 PCI IDE functions, one for primary and one 3950 * for secondary. So we need to call pciide_mapregs_compat() 3951 * with the real channel 3952 */ 3953 if (pa->pa_function == 0) { 3954 compatchan = 0; 3955 } else if (pa->pa_function == 1) { 3956 compatchan = 1; 3957 } else { 3958 aprint_error("%s: unexpected PCI function %d\n", 3959 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3960 return; 3961 } 3962 sc->sc_wdcdev.nchannels = 1; 3963 } else { 3964 sc->sc_wdcdev.nchannels = 2; 3965 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 3966 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3967 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3968 revision == HPT372_REV)) 3969 sc->sc_wdcdev.UDMA_cap = 6; 3970 else 3971 sc->sc_wdcdev.UDMA_cap = 5; 3972 } 3973 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3974 cp = &sc->pciide_channels[i]; 3975 if (sc->sc_wdcdev.nchannels > 1) { 3976 compatchan = i; 3977 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3978 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3979 aprint_normal( 3980 "%s: %s channel ignored (disabled)\n", 3981 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3982 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 3983 continue; 3984 } 3985 } 3986 if (pciide_chansetup(sc, i, interface) == 0) 3987 continue; 3988 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3989 hpt_pci_intr); 3990 } 3991 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3992 (revision == HPT370_REV || revision == HPT370A_REV || 3993 revision == HPT372_REV)) || 3994 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3995 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 3996 /* 3997 * HPT370_REV and highter has a bit to disable interrupts, 3998 * make sure to clear it 3999 */ 4000 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 4001 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 4002 ~HPT_CSEL_IRQDIS); 4003 } 4004 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 4005 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 4006 revision == HPT372_REV ) || 4007 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 4008 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 4009 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 4010 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 4011 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 4012 return; 4013 } 4014 4015 void 4016 hpt_setup_channel(chp) 4017 struct channel_softc *chp; 4018 { 4019 struct ata_drive_datas *drvp; 4020 int drive; 4021 int cable; 4022 u_int32_t before, after; 4023 u_int32_t idedma_ctl; 4024 struct pciide_channel *cp = (struct pciide_channel*)chp; 4025 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4026 int revision = 4027 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 4028 4029 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 4030 4031 /* setup DMA if needed */ 4032 pciide_channel_dma_setup(cp); 4033 4034 idedma_ctl = 0; 4035 4036 /* Per drive settings */ 4037 for (drive = 0; drive < 2; drive++) { 4038 drvp = &chp->ch_drive[drive]; 4039 /* If no drive, skip */ 4040 if ((drvp->drive_flags & DRIVE) == 0) 4041 continue; 4042 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 4043 HPT_IDETIM(chp->channel, drive)); 4044 4045 /* add timing values, setup DMA if needed */ 4046 if (drvp->drive_flags & DRIVE_UDMA) { 4047 /* use Ultra/DMA */ 4048 drvp->drive_flags &= ~DRIVE_DMA; 4049 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 4050 drvp->UDMA_mode > 2) 4051 drvp->UDMA_mode = 2; 4052 switch (sc->sc_pp->ide_product) { 4053 case PCI_PRODUCT_TRIONES_HPT374: 4054 after = hpt374_udma[drvp->UDMA_mode]; 4055 break; 4056 case PCI_PRODUCT_TRIONES_HPT372: 4057 after = hpt372_udma[drvp->UDMA_mode]; 4058 break; 4059 case PCI_PRODUCT_TRIONES_HPT366: 4060 default: 4061 switch(revision) { 4062 case HPT372_REV: 4063 after = hpt372_udma[drvp->UDMA_mode]; 4064 break; 4065 case HPT370_REV: 4066 case HPT370A_REV: 4067 after = hpt370_udma[drvp->UDMA_mode]; 4068 break; 4069 case HPT366_REV: 4070 default: 4071 after = hpt366_udma[drvp->UDMA_mode]; 4072 break; 4073 } 4074 } 4075 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4076 } else if (drvp->drive_flags & DRIVE_DMA) { 4077 /* 4078 * use Multiword DMA. 4079 * Timings will be used for both PIO and DMA, so adjust 4080 * DMA mode if needed 4081 */ 4082 if (drvp->PIO_mode >= 3 && 4083 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 4084 drvp->DMA_mode = drvp->PIO_mode - 2; 4085 } 4086 switch (sc->sc_pp->ide_product) { 4087 case PCI_PRODUCT_TRIONES_HPT374: 4088 after = hpt374_dma[drvp->DMA_mode]; 4089 break; 4090 case PCI_PRODUCT_TRIONES_HPT372: 4091 after = hpt372_dma[drvp->DMA_mode]; 4092 break; 4093 case PCI_PRODUCT_TRIONES_HPT366: 4094 default: 4095 switch(revision) { 4096 case HPT372_REV: 4097 after = hpt372_dma[drvp->DMA_mode]; 4098 break; 4099 case HPT370_REV: 4100 case HPT370A_REV: 4101 after = hpt370_dma[drvp->DMA_mode]; 4102 break; 4103 case HPT366_REV: 4104 default: 4105 after = hpt366_dma[drvp->DMA_mode]; 4106 break; 4107 } 4108 } 4109 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4110 } else { 4111 /* PIO only */ 4112 switch (sc->sc_pp->ide_product) { 4113 case PCI_PRODUCT_TRIONES_HPT374: 4114 after = hpt374_pio[drvp->PIO_mode]; 4115 break; 4116 case PCI_PRODUCT_TRIONES_HPT372: 4117 after = hpt372_pio[drvp->PIO_mode]; 4118 break; 4119 case PCI_PRODUCT_TRIONES_HPT366: 4120 default: 4121 switch(revision) { 4122 case HPT372_REV: 4123 after = hpt372_pio[drvp->PIO_mode]; 4124 break; 4125 case HPT370_REV: 4126 case HPT370A_REV: 4127 after = hpt370_pio[drvp->PIO_mode]; 4128 break; 4129 case HPT366_REV: 4130 default: 4131 after = hpt366_pio[drvp->PIO_mode]; 4132 break; 4133 } 4134 } 4135 } 4136 pci_conf_write(sc->sc_pc, sc->sc_tag, 4137 HPT_IDETIM(chp->channel, drive), after); 4138 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 4139 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 4140 after, before), DEBUG_PROBE); 4141 } 4142 if (idedma_ctl != 0) { 4143 /* Add software bits in status register */ 4144 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4145 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4146 idedma_ctl); 4147 } 4148 } 4149 4150 int 4151 hpt_pci_intr(arg) 4152 void *arg; 4153 { 4154 struct pciide_softc *sc = arg; 4155 struct pciide_channel *cp; 4156 struct channel_softc *wdc_cp; 4157 int rv = 0; 4158 int dmastat, i, crv; 4159 4160 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4161 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4162 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4163 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4164 IDEDMA_CTL_INTR) 4165 continue; 4166 cp = &sc->pciide_channels[i]; 4167 wdc_cp = &cp->wdc_channel; 4168 crv = wdcintr(wdc_cp); 4169 if (crv == 0) { 4170 printf("%s:%d: bogus intr\n", 4171 sc->sc_wdcdev.sc_dev.dv_xname, i); 4172 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4173 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4174 } else 4175 rv = 1; 4176 } 4177 return rv; 4178 } 4179 4180 4181 /* Macros to test product */ 4182 #define PDC_IS_262(sc) \ 4183 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 4184 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 4185 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 4186 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4187 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4188 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4189 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4190 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4191 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4192 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4193 #define PDC_IS_265(sc) \ 4194 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 4195 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 4196 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4197 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4198 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4199 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4200 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4201 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4202 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4203 #define PDC_IS_268(sc) \ 4204 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4205 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4206 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4207 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4208 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4209 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4210 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4211 #define PDC_IS_276(sc) \ 4212 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4213 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4214 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4215 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4216 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4217 4218 void 4219 pdc202xx_chip_map(sc, pa) 4220 struct pciide_softc *sc; 4221 struct pci_attach_args *pa; 4222 { 4223 struct pciide_channel *cp; 4224 int channel; 4225 pcireg_t interface, st, mode; 4226 bus_size_t cmdsize, ctlsize; 4227 4228 if (!PDC_IS_268(sc)) { 4229 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4230 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 4231 st), DEBUG_PROBE); 4232 } 4233 if (pciide_chipen(sc, pa) == 0) 4234 return; 4235 4236 /* turn off RAID mode */ 4237 if (!PDC_IS_268(sc)) 4238 st &= ~PDC2xx_STATE_IDERAID; 4239 4240 /* 4241 * can't rely on the PCI_CLASS_REG content if the chip was in raid 4242 * mode. We have to fake interface 4243 */ 4244 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 4245 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 4246 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4247 4248 aprint_normal("%s: bus-master DMA support present", 4249 sc->sc_wdcdev.sc_dev.dv_xname); 4250 pciide_mapreg_dma(sc, pa); 4251 aprint_normal("\n"); 4252 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4253 WDC_CAPABILITY_MODE; 4254 if (sc->sc_dma_ok) { 4255 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4256 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4257 sc->sc_wdcdev.irqack = pciide_irqack; 4258 } 4259 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 4260 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 4261 sc->sc_wdcdev.cap |= WDC_CAPABILITY_RAID; 4262 sc->sc_wdcdev.PIO_cap = 4; 4263 sc->sc_wdcdev.DMA_cap = 2; 4264 if (PDC_IS_276(sc)) 4265 sc->sc_wdcdev.UDMA_cap = 6; 4266 else if (PDC_IS_265(sc)) 4267 sc->sc_wdcdev.UDMA_cap = 5; 4268 else if (PDC_IS_262(sc)) 4269 sc->sc_wdcdev.UDMA_cap = 4; 4270 else 4271 sc->sc_wdcdev.UDMA_cap = 2; 4272 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 4273 pdc20268_setup_channel : pdc202xx_setup_channel; 4274 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4275 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4276 4277 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || 4278 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || 4279 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) { 4280 sc->sc_wdcdev.dma_start = pdc20262_dma_start; 4281 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish; 4282 } 4283 4284 if (!PDC_IS_268(sc)) { 4285 /* setup failsafe defaults */ 4286 mode = 0; 4287 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 4288 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 4289 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 4290 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 4291 for (channel = 0; 4292 channel < sc->sc_wdcdev.nchannels; 4293 channel++) { 4294 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 4295 "drive 0 initial timings 0x%x, now 0x%x\n", 4296 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 4297 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 4298 DEBUG_PROBE); 4299 pci_conf_write(sc->sc_pc, sc->sc_tag, 4300 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 4301 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 4302 "drive 1 initial timings 0x%x, now 0x%x\n", 4303 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 4304 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 4305 pci_conf_write(sc->sc_pc, sc->sc_tag, 4306 PDC2xx_TIM(channel, 1), mode); 4307 } 4308 4309 mode = PDC2xx_SCR_DMA; 4310 if (PDC_IS_265(sc)) { 4311 mode = PDC2xx_SCR_SET_GEN(mode, PDC265_SCR_GEN_LAT); 4312 } else if (PDC_IS_262(sc)) { 4313 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 4314 } else { 4315 /* the BIOS set it up this way */ 4316 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 4317 } 4318 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 4319 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 4320 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 4321 "now 0x%x\n", 4322 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4323 PDC2xx_SCR), 4324 mode), DEBUG_PROBE); 4325 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4326 PDC2xx_SCR, mode); 4327 4328 /* controller initial state register is OK even without BIOS */ 4329 /* Set DMA mode to IDE DMA compatibility */ 4330 mode = 4331 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 4332 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 4333 DEBUG_PROBE); 4334 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 4335 mode | 0x1); 4336 mode = 4337 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 4338 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 4339 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 4340 mode | 0x1); 4341 } 4342 4343 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4344 cp = &sc->pciide_channels[channel]; 4345 if (pciide_chansetup(sc, channel, interface) == 0) 4346 continue; 4347 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 4348 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 4349 aprint_normal("%s: %s channel ignored (disabled)\n", 4350 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4351 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 4352 continue; 4353 } 4354 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4355 PDC_IS_265(sc) ? pdc20265_pci_intr : pdc202xx_pci_intr); 4356 } 4357 if (!PDC_IS_268(sc)) { 4358 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 4359 "0x%x\n", st), DEBUG_PROBE); 4360 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 4361 } 4362 return; 4363 } 4364 4365 void 4366 pdc202xx_setup_channel(chp) 4367 struct channel_softc *chp; 4368 { 4369 struct ata_drive_datas *drvp; 4370 int drive; 4371 pcireg_t mode, st; 4372 u_int32_t idedma_ctl, scr, atapi; 4373 struct pciide_channel *cp = (struct pciide_channel*)chp; 4374 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4375 int channel = chp->channel; 4376 4377 /* setup DMA if needed */ 4378 pciide_channel_dma_setup(cp); 4379 4380 idedma_ctl = 0; 4381 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 4382 sc->sc_wdcdev.sc_dev.dv_xname, 4383 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 4384 DEBUG_PROBE); 4385 4386 /* Per channel settings */ 4387 if (PDC_IS_262(sc)) { 4388 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4389 PDC262_U66); 4390 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4391 /* Trim UDMA mode */ 4392 if ((st & PDC262_STATE_80P(channel)) != 0 || 4393 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4394 chp->ch_drive[0].UDMA_mode <= 2) || 4395 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4396 chp->ch_drive[1].UDMA_mode <= 2)) { 4397 if (chp->ch_drive[0].UDMA_mode > 2) 4398 chp->ch_drive[0].UDMA_mode = 2; 4399 if (chp->ch_drive[1].UDMA_mode > 2) 4400 chp->ch_drive[1].UDMA_mode = 2; 4401 } 4402 /* Set U66 if needed */ 4403 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4404 chp->ch_drive[0].UDMA_mode > 2) || 4405 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4406 chp->ch_drive[1].UDMA_mode > 2)) 4407 scr |= PDC262_U66_EN(channel); 4408 else 4409 scr &= ~PDC262_U66_EN(channel); 4410 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4411 PDC262_U66, scr); 4412 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 4413 sc->sc_wdcdev.sc_dev.dv_xname, channel, 4414 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4415 PDC262_ATAPI(channel))), DEBUG_PROBE); 4416 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 4417 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 4418 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4419 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4420 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 4421 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4422 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4423 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 4424 atapi = 0; 4425 else 4426 atapi = PDC262_ATAPI_UDMA; 4427 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4428 PDC262_ATAPI(channel), atapi); 4429 } 4430 } 4431 for (drive = 0; drive < 2; drive++) { 4432 drvp = &chp->ch_drive[drive]; 4433 /* If no drive, skip */ 4434 if ((drvp->drive_flags & DRIVE) == 0) 4435 continue; 4436 mode = 0; 4437 if (drvp->drive_flags & DRIVE_UDMA) { 4438 /* use Ultra/DMA */ 4439 drvp->drive_flags &= ~DRIVE_DMA; 4440 mode = PDC2xx_TIM_SET_MB(mode, 4441 pdc2xx_udma_mb[drvp->UDMA_mode]); 4442 mode = PDC2xx_TIM_SET_MC(mode, 4443 pdc2xx_udma_mc[drvp->UDMA_mode]); 4444 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4445 } else if (drvp->drive_flags & DRIVE_DMA) { 4446 mode = PDC2xx_TIM_SET_MB(mode, 4447 pdc2xx_dma_mb[drvp->DMA_mode]); 4448 mode = PDC2xx_TIM_SET_MC(mode, 4449 pdc2xx_dma_mc[drvp->DMA_mode]); 4450 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4451 } else { 4452 mode = PDC2xx_TIM_SET_MB(mode, 4453 pdc2xx_dma_mb[0]); 4454 mode = PDC2xx_TIM_SET_MC(mode, 4455 pdc2xx_dma_mc[0]); 4456 } 4457 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 4458 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 4459 if (drvp->drive_flags & DRIVE_ATA) 4460 mode |= PDC2xx_TIM_PRE; 4461 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 4462 if (drvp->PIO_mode >= 3) { 4463 mode |= PDC2xx_TIM_IORDY; 4464 if (drive == 0) 4465 mode |= PDC2xx_TIM_IORDYp; 4466 } 4467 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 4468 "timings 0x%x\n", 4469 sc->sc_wdcdev.sc_dev.dv_xname, 4470 chp->channel, drive, mode), DEBUG_PROBE); 4471 pci_conf_write(sc->sc_pc, sc->sc_tag, 4472 PDC2xx_TIM(chp->channel, drive), mode); 4473 } 4474 if (idedma_ctl != 0) { 4475 /* Add software bits in status register */ 4476 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4477 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4478 idedma_ctl); 4479 } 4480 } 4481 4482 void 4483 pdc20268_setup_channel(chp) 4484 struct channel_softc *chp; 4485 { 4486 struct ata_drive_datas *drvp; 4487 int drive; 4488 u_int32_t idedma_ctl; 4489 struct pciide_channel *cp = (struct pciide_channel*)chp; 4490 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4491 int u100; 4492 4493 /* setup DMA if needed */ 4494 pciide_channel_dma_setup(cp); 4495 4496 idedma_ctl = 0; 4497 4498 /* I don't know what this is for, FreeBSD does it ... */ 4499 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4500 IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * chp->channel, 0x0b); 4501 4502 /* 4503 * cable type detect, from FreeBSD 4504 */ 4505 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4506 IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * chp->channel) & 0x04) ? 4507 0 : 1; 4508 4509 for (drive = 0; drive < 2; drive++) { 4510 drvp = &chp->ch_drive[drive]; 4511 /* If no drive, skip */ 4512 if ((drvp->drive_flags & DRIVE) == 0) 4513 continue; 4514 if (drvp->drive_flags & DRIVE_UDMA) { 4515 /* use Ultra/DMA */ 4516 drvp->drive_flags &= ~DRIVE_DMA; 4517 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4518 if (drvp->UDMA_mode > 2 && u100 == 0) 4519 drvp->UDMA_mode = 2; 4520 } else if (drvp->drive_flags & DRIVE_DMA) { 4521 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4522 } 4523 } 4524 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 4525 if (idedma_ctl != 0) { 4526 /* Add software bits in status register */ 4527 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4528 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4529 idedma_ctl); 4530 } 4531 } 4532 4533 int 4534 pdc202xx_pci_intr(arg) 4535 void *arg; 4536 { 4537 struct pciide_softc *sc = arg; 4538 struct pciide_channel *cp; 4539 struct channel_softc *wdc_cp; 4540 int i, rv, crv; 4541 u_int32_t scr; 4542 4543 rv = 0; 4544 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 4545 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4546 cp = &sc->pciide_channels[i]; 4547 wdc_cp = &cp->wdc_channel; 4548 /* If a compat channel skip. */ 4549 if (cp->compat) 4550 continue; 4551 if (scr & PDC2xx_SCR_INT(i)) { 4552 crv = wdcintr(wdc_cp); 4553 if (crv == 0) 4554 printf("%s:%d: bogus intr (reg 0x%x)\n", 4555 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 4556 else 4557 rv = 1; 4558 } 4559 } 4560 return rv; 4561 } 4562 4563 int 4564 pdc20265_pci_intr(arg) 4565 void *arg; 4566 { 4567 struct pciide_softc *sc = arg; 4568 struct pciide_channel *cp; 4569 struct channel_softc *wdc_cp; 4570 int i, rv, crv; 4571 u_int32_t dmastat; 4572 4573 rv = 0; 4574 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4575 cp = &sc->pciide_channels[i]; 4576 wdc_cp = &cp->wdc_channel; 4577 /* If a compat channel skip. */ 4578 if (cp->compat) 4579 continue; 4580 /* 4581 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 4582 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 4583 * So use it instead (requires 2 reg reads instead of 1, 4584 * but we can't do it another way). 4585 */ 4586 dmastat = bus_space_read_1(sc->sc_dma_iot, 4587 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4588 if((dmastat & IDEDMA_CTL_INTR) == 0) 4589 continue; 4590 crv = wdcintr(wdc_cp); 4591 if (crv == 0) 4592 printf("%s:%d: bogus intr\n", 4593 sc->sc_wdcdev.sc_dev.dv_xname, i); 4594 else 4595 rv = 1; 4596 } 4597 return rv; 4598 } 4599 4600 static void 4601 pdc20262_dma_start(v, channel, drive) 4602 void *v; 4603 int channel, drive; 4604 { 4605 struct pciide_softc *sc = v; 4606 struct pciide_dma_maps *dma_maps = 4607 &sc->pciide_channels[channel].dma_maps[drive]; 4608 int atapi; 4609 4610 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 4611 atapi = (dma_maps->dma_flags & WDC_DMA_READ) ? 4612 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE; 4613 atapi |= dma_maps->dmamap_xfer->dm_mapsize >> 1; 4614 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4615 PDC262_ATAPI(channel), atapi); 4616 } 4617 4618 pciide_dma_start(v, channel, drive); 4619 } 4620 4621 int 4622 pdc20262_dma_finish(v, channel, drive, force) 4623 void *v; 4624 int channel, drive; 4625 int force; 4626 { 4627 struct pciide_softc *sc = v; 4628 struct pciide_dma_maps *dma_maps = 4629 &sc->pciide_channels[channel].dma_maps[drive]; 4630 struct channel_softc *chp; 4631 int atapi, error; 4632 4633 error = pciide_dma_finish(v, channel, drive, force); 4634 4635 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 4636 chp = sc->wdc_chanarray[channel]; 4637 atapi = 0; 4638 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 4639 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 4640 if ((!(chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4641 (chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 4642 !(chp->ch_drive[1].drive_flags & DRIVE_DMA)) && 4643 (!(chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 4644 (chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4645 !(chp->ch_drive[0].drive_flags & DRIVE_DMA))) 4646 atapi = PDC262_ATAPI_UDMA; 4647 } 4648 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4649 PDC262_ATAPI(channel), atapi); 4650 } 4651 4652 return error; 4653 } 4654 4655 void 4656 opti_chip_map(sc, pa) 4657 struct pciide_softc *sc; 4658 struct pci_attach_args *pa; 4659 { 4660 struct pciide_channel *cp; 4661 bus_size_t cmdsize, ctlsize; 4662 pcireg_t interface; 4663 u_int8_t init_ctrl; 4664 int channel; 4665 4666 if (pciide_chipen(sc, pa) == 0) 4667 return; 4668 aprint_normal("%s: bus-master DMA support present", 4669 sc->sc_wdcdev.sc_dev.dv_xname); 4670 4671 /* 4672 * XXXSCW: 4673 * There seem to be a couple of buggy revisions/implementations 4674 * of the OPTi pciide chipset. This kludge seems to fix one of 4675 * the reported problems (PR/11644) but still fails for the 4676 * other (PR/13151), although the latter may be due to other 4677 * issues too... 4678 */ 4679 if (PCI_REVISION(pa->pa_class) <= 0x12) { 4680 aprint_normal(" but disabled due to chip rev. <= 0x12"); 4681 sc->sc_dma_ok = 0; 4682 } else 4683 pciide_mapreg_dma(sc, pa); 4684 4685 aprint_normal("\n"); 4686 4687 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4688 WDC_CAPABILITY_MODE; 4689 sc->sc_wdcdev.PIO_cap = 4; 4690 if (sc->sc_dma_ok) { 4691 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4692 sc->sc_wdcdev.irqack = pciide_irqack; 4693 sc->sc_wdcdev.DMA_cap = 2; 4694 } 4695 sc->sc_wdcdev.set_modes = opti_setup_channel; 4696 4697 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4698 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4699 4700 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 4701 OPTI_REG_INIT_CONTROL); 4702 4703 interface = PCI_INTERFACE(pa->pa_class); 4704 4705 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4706 cp = &sc->pciide_channels[channel]; 4707 if (pciide_chansetup(sc, channel, interface) == 0) 4708 continue; 4709 if (channel == 1 && 4710 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 4711 aprint_normal("%s: %s channel ignored (disabled)\n", 4712 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4713 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 4714 continue; 4715 } 4716 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4717 pciide_pci_intr); 4718 } 4719 } 4720 4721 void 4722 opti_setup_channel(chp) 4723 struct channel_softc *chp; 4724 { 4725 struct ata_drive_datas *drvp; 4726 struct pciide_channel *cp = (struct pciide_channel*)chp; 4727 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4728 int drive, spd; 4729 int mode[2]; 4730 u_int8_t rv, mr; 4731 4732 /* 4733 * The `Delay' and `Address Setup Time' fields of the 4734 * Miscellaneous Register are always zero initially. 4735 */ 4736 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 4737 mr &= ~(OPTI_MISC_DELAY_MASK | 4738 OPTI_MISC_ADDR_SETUP_MASK | 4739 OPTI_MISC_INDEX_MASK); 4740 4741 /* Prime the control register before setting timing values */ 4742 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 4743 4744 /* Determine the clockrate of the PCIbus the chip is attached to */ 4745 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 4746 spd &= OPTI_STRAP_PCI_SPEED_MASK; 4747 4748 /* setup DMA if needed */ 4749 pciide_channel_dma_setup(cp); 4750 4751 for (drive = 0; drive < 2; drive++) { 4752 drvp = &chp->ch_drive[drive]; 4753 /* If no drive, skip */ 4754 if ((drvp->drive_flags & DRIVE) == 0) { 4755 mode[drive] = -1; 4756 continue; 4757 } 4758 4759 if ((drvp->drive_flags & DRIVE_DMA)) { 4760 /* 4761 * Timings will be used for both PIO and DMA, 4762 * so adjust DMA mode if needed 4763 */ 4764 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 4765 drvp->PIO_mode = drvp->DMA_mode + 2; 4766 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 4767 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 4768 drvp->PIO_mode - 2 : 0; 4769 if (drvp->DMA_mode == 0) 4770 drvp->PIO_mode = 0; 4771 4772 mode[drive] = drvp->DMA_mode + 5; 4773 } else 4774 mode[drive] = drvp->PIO_mode; 4775 4776 if (drive && mode[0] >= 0 && 4777 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 4778 /* 4779 * Can't have two drives using different values 4780 * for `Address Setup Time'. 4781 * Slow down the faster drive to compensate. 4782 */ 4783 int d = (opti_tim_as[spd][mode[0]] > 4784 opti_tim_as[spd][mode[1]]) ? 0 : 1; 4785 4786 mode[d] = mode[1-d]; 4787 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4788 chp->ch_drive[d].DMA_mode = 0; 4789 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 4790 } 4791 } 4792 4793 for (drive = 0; drive < 2; drive++) { 4794 int m; 4795 if ((m = mode[drive]) < 0) 4796 continue; 4797 4798 /* Set the Address Setup Time and select appropriate index */ 4799 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4800 rv |= OPTI_MISC_INDEX(drive); 4801 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4802 4803 /* Set the pulse width and recovery timing parameters */ 4804 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4805 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4806 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4807 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4808 4809 /* Set the Enhanced Mode register appropriately */ 4810 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4811 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4812 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4813 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4814 } 4815 4816 /* Finally, enable the timings */ 4817 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4818 } 4819 4820 #define ACARD_IS_850(sc) \ 4821 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4822 4823 void 4824 acard_chip_map(sc, pa) 4825 struct pciide_softc *sc; 4826 struct pci_attach_args *pa; 4827 { 4828 struct pciide_channel *cp; 4829 int i; 4830 pcireg_t interface; 4831 bus_size_t cmdsize, ctlsize; 4832 4833 if (pciide_chipen(sc, pa) == 0) 4834 return; 4835 4836 /* 4837 * when the chip is in native mode it identifies itself as a 4838 * 'misc mass storage'. Fake interface in this case. 4839 */ 4840 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4841 interface = PCI_INTERFACE(pa->pa_class); 4842 } else { 4843 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4844 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4845 } 4846 4847 aprint_normal("%s: bus-master DMA support present", 4848 sc->sc_wdcdev.sc_dev.dv_xname); 4849 pciide_mapreg_dma(sc, pa); 4850 aprint_normal("\n"); 4851 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4852 WDC_CAPABILITY_MODE; 4853 4854 if (sc->sc_dma_ok) { 4855 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4856 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4857 sc->sc_wdcdev.irqack = pciide_irqack; 4858 } 4859 sc->sc_wdcdev.PIO_cap = 4; 4860 sc->sc_wdcdev.DMA_cap = 2; 4861 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4862 4863 sc->sc_wdcdev.set_modes = acard_setup_channel; 4864 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4865 sc->sc_wdcdev.nchannels = 2; 4866 4867 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4868 cp = &sc->pciide_channels[i]; 4869 if (pciide_chansetup(sc, i, interface) == 0) 4870 continue; 4871 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4872 pciide_pci_intr); 4873 } 4874 if (!ACARD_IS_850(sc)) { 4875 u_int32_t reg; 4876 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4877 reg &= ~ATP860_CTRL_INT; 4878 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4879 } 4880 } 4881 4882 void 4883 acard_setup_channel(chp) 4884 struct channel_softc *chp; 4885 { 4886 struct ata_drive_datas *drvp; 4887 struct pciide_channel *cp = (struct pciide_channel*)chp; 4888 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4889 int channel = chp->channel; 4890 int drive; 4891 u_int32_t idetime, udma_mode; 4892 u_int32_t idedma_ctl; 4893 4894 /* setup DMA if needed */ 4895 pciide_channel_dma_setup(cp); 4896 4897 if (ACARD_IS_850(sc)) { 4898 idetime = 0; 4899 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4900 udma_mode &= ~ATP850_UDMA_MASK(channel); 4901 } else { 4902 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4903 idetime &= ~ATP860_SETTIME_MASK(channel); 4904 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4905 udma_mode &= ~ATP860_UDMA_MASK(channel); 4906 4907 /* check 80 pins cable */ 4908 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4909 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4910 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4911 & ATP860_CTRL_80P(chp->channel)) { 4912 if (chp->ch_drive[0].UDMA_mode > 2) 4913 chp->ch_drive[0].UDMA_mode = 2; 4914 if (chp->ch_drive[1].UDMA_mode > 2) 4915 chp->ch_drive[1].UDMA_mode = 2; 4916 } 4917 } 4918 } 4919 4920 idedma_ctl = 0; 4921 4922 /* Per drive settings */ 4923 for (drive = 0; drive < 2; drive++) { 4924 drvp = &chp->ch_drive[drive]; 4925 /* If no drive, skip */ 4926 if ((drvp->drive_flags & DRIVE) == 0) 4927 continue; 4928 /* add timing values, setup DMA if needed */ 4929 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4930 (drvp->drive_flags & DRIVE_UDMA)) { 4931 /* use Ultra/DMA */ 4932 if (ACARD_IS_850(sc)) { 4933 idetime |= ATP850_SETTIME(drive, 4934 acard_act_udma[drvp->UDMA_mode], 4935 acard_rec_udma[drvp->UDMA_mode]); 4936 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4937 acard_udma_conf[drvp->UDMA_mode]); 4938 } else { 4939 idetime |= ATP860_SETTIME(channel, drive, 4940 acard_act_udma[drvp->UDMA_mode], 4941 acard_rec_udma[drvp->UDMA_mode]); 4942 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4943 acard_udma_conf[drvp->UDMA_mode]); 4944 } 4945 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4946 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4947 (drvp->drive_flags & DRIVE_DMA)) { 4948 /* use Multiword DMA */ 4949 drvp->drive_flags &= ~DRIVE_UDMA; 4950 if (ACARD_IS_850(sc)) { 4951 idetime |= ATP850_SETTIME(drive, 4952 acard_act_dma[drvp->DMA_mode], 4953 acard_rec_dma[drvp->DMA_mode]); 4954 } else { 4955 idetime |= ATP860_SETTIME(channel, drive, 4956 acard_act_dma[drvp->DMA_mode], 4957 acard_rec_dma[drvp->DMA_mode]); 4958 } 4959 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4960 } else { 4961 /* PIO only */ 4962 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4963 if (ACARD_IS_850(sc)) { 4964 idetime |= ATP850_SETTIME(drive, 4965 acard_act_pio[drvp->PIO_mode], 4966 acard_rec_pio[drvp->PIO_mode]); 4967 } else { 4968 idetime |= ATP860_SETTIME(channel, drive, 4969 acard_act_pio[drvp->PIO_mode], 4970 acard_rec_pio[drvp->PIO_mode]); 4971 } 4972 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4973 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4974 | ATP8x0_CTRL_EN(channel)); 4975 } 4976 } 4977 4978 if (idedma_ctl != 0) { 4979 /* Add software bits in status register */ 4980 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4981 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 4982 } 4983 4984 if (ACARD_IS_850(sc)) { 4985 pci_conf_write(sc->sc_pc, sc->sc_tag, 4986 ATP850_IDETIME(channel), idetime); 4987 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 4988 } else { 4989 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 4990 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 4991 } 4992 } 4993 4994 int 4995 acard_pci_intr(arg) 4996 void *arg; 4997 { 4998 struct pciide_softc *sc = arg; 4999 struct pciide_channel *cp; 5000 struct channel_softc *wdc_cp; 5001 int rv = 0; 5002 int dmastat, i, crv; 5003 5004 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5005 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5006 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 5007 if ((dmastat & IDEDMA_CTL_INTR) == 0) 5008 continue; 5009 cp = &sc->pciide_channels[i]; 5010 wdc_cp = &cp->wdc_channel; 5011 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 5012 (void)wdcintr(wdc_cp); 5013 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5014 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 5015 continue; 5016 } 5017 crv = wdcintr(wdc_cp); 5018 if (crv == 0) 5019 printf("%s:%d: bogus intr\n", 5020 sc->sc_wdcdev.sc_dev.dv_xname, i); 5021 else if (crv == 1) 5022 rv = 1; 5023 else if (rv == 0) 5024 rv = crv; 5025 } 5026 return rv; 5027 } 5028 5029 static int 5030 sl82c105_bugchk(struct pci_attach_args *pa) 5031 { 5032 5033 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 5034 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 5035 return (0); 5036 5037 if (PCI_REVISION(pa->pa_class) <= 0x05) 5038 return (1); 5039 5040 return (0); 5041 } 5042 5043 void 5044 sl82c105_chip_map(sc, pa) 5045 struct pciide_softc *sc; 5046 struct pci_attach_args *pa; 5047 { 5048 struct pciide_channel *cp; 5049 bus_size_t cmdsize, ctlsize; 5050 pcireg_t interface, idecr; 5051 int channel; 5052 5053 if (pciide_chipen(sc, pa) == 0) 5054 return; 5055 5056 aprint_normal("%s: bus-master DMA support present", 5057 sc->sc_wdcdev.sc_dev.dv_xname); 5058 5059 /* 5060 * Check to see if we're part of the Winbond 83c553 Southbridge. 5061 * If so, we need to disable DMA on rev. <= 5 of that chip. 5062 */ 5063 if (pci_find_device(pa, sl82c105_bugchk)) { 5064 aprint_normal(" but disabled due to 83c553 rev. <= 0x05"); 5065 sc->sc_dma_ok = 0; 5066 } else 5067 pciide_mapreg_dma(sc, pa); 5068 aprint_normal("\n"); 5069 5070 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 5071 WDC_CAPABILITY_MODE; 5072 sc->sc_wdcdev.PIO_cap = 4; 5073 if (sc->sc_dma_ok) { 5074 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 5075 sc->sc_wdcdev.irqack = pciide_irqack; 5076 sc->sc_wdcdev.DMA_cap = 2; 5077 } 5078 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 5079 5080 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5081 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5082 5083 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 5084 5085 interface = PCI_INTERFACE(pa->pa_class); 5086 5087 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5088 cp = &sc->pciide_channels[channel]; 5089 if (pciide_chansetup(sc, channel, interface) == 0) 5090 continue; 5091 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 5092 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 5093 aprint_normal("%s: %s channel ignored (disabled)\n", 5094 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 5095 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 5096 continue; 5097 } 5098 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5099 pciide_pci_intr); 5100 } 5101 } 5102 5103 void 5104 sl82c105_setup_channel(chp) 5105 struct channel_softc *chp; 5106 { 5107 struct ata_drive_datas *drvp; 5108 struct pciide_channel *cp = (struct pciide_channel*)chp; 5109 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5110 int pxdx_reg, drive; 5111 pcireg_t pxdx; 5112 5113 /* Set up DMA if needed. */ 5114 pciide_channel_dma_setup(cp); 5115 5116 for (drive = 0; drive < 2; drive++) { 5117 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 5118 : SYMPH_P1D0CR) + (drive * 4); 5119 5120 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 5121 5122 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 5123 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 5124 5125 drvp = &chp->ch_drive[drive]; 5126 /* If no drive, skip. */ 5127 if ((drvp->drive_flags & DRIVE) == 0) { 5128 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 5129 continue; 5130 } 5131 5132 if (drvp->drive_flags & DRIVE_DMA) { 5133 /* 5134 * Timings will be used for both PIO and DMA, 5135 * so adjust DMA mode if needed. 5136 */ 5137 if (drvp->PIO_mode >= 3) { 5138 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 5139 drvp->DMA_mode = drvp->PIO_mode - 2; 5140 if (drvp->DMA_mode < 1) { 5141 /* 5142 * Can't mix both PIO and DMA. 5143 * Disable DMA. 5144 */ 5145 drvp->drive_flags &= ~DRIVE_DMA; 5146 } 5147 } else { 5148 /* 5149 * Can't mix both PIO and DMA. Disable 5150 * DMA. 5151 */ 5152 drvp->drive_flags &= ~DRIVE_DMA; 5153 } 5154 } 5155 5156 if (drvp->drive_flags & DRIVE_DMA) { 5157 /* Use multi-word DMA. */ 5158 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 5159 PxDx_CMD_ON_SHIFT; 5160 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 5161 } else { 5162 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 5163 PxDx_CMD_ON_SHIFT; 5164 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 5165 } 5166 5167 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 5168 5169 /* ...and set the mode for this drive. */ 5170 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 5171 } 5172 } 5173 5174 void 5175 serverworks_chip_map(sc, pa) 5176 struct pciide_softc *sc; 5177 struct pci_attach_args *pa; 5178 { 5179 struct pciide_channel *cp; 5180 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 5181 pcitag_t pcib_tag; 5182 int channel; 5183 bus_size_t cmdsize, ctlsize; 5184 5185 if (pciide_chipen(sc, pa) == 0) 5186 return; 5187 5188 aprint_normal("%s: bus-master DMA support present", 5189 sc->sc_wdcdev.sc_dev.dv_xname); 5190 pciide_mapreg_dma(sc, pa); 5191 aprint_normal("\n"); 5192 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5193 WDC_CAPABILITY_MODE; 5194 5195 if (sc->sc_dma_ok) { 5196 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5197 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5198 sc->sc_wdcdev.irqack = pciide_irqack; 5199 } 5200 sc->sc_wdcdev.PIO_cap = 4; 5201 sc->sc_wdcdev.DMA_cap = 2; 5202 switch (sc->sc_pp->ide_product) { 5203 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 5204 sc->sc_wdcdev.UDMA_cap = 2; 5205 break; 5206 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 5207 if (PCI_REVISION(pa->pa_class) < 0x92) 5208 sc->sc_wdcdev.UDMA_cap = 4; 5209 else 5210 sc->sc_wdcdev.UDMA_cap = 5; 5211 break; 5212 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 5213 sc->sc_wdcdev.UDMA_cap = 5; 5214 break; 5215 } 5216 5217 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 5218 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5219 sc->sc_wdcdev.nchannels = 2; 5220 5221 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5222 cp = &sc->pciide_channels[channel]; 5223 if (pciide_chansetup(sc, channel, interface) == 0) 5224 continue; 5225 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5226 serverworks_pci_intr); 5227 } 5228 5229 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 5230 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 5231 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 5232 } 5233 5234 void 5235 serverworks_setup_channel(chp) 5236 struct channel_softc *chp; 5237 { 5238 struct ata_drive_datas *drvp; 5239 struct pciide_channel *cp = (struct pciide_channel*)chp; 5240 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5241 int channel = chp->channel; 5242 int drive, unit; 5243 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 5244 u_int32_t idedma_ctl; 5245 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 5246 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 5247 5248 /* setup DMA if needed */ 5249 pciide_channel_dma_setup(cp); 5250 5251 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 5252 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 5253 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 5254 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 5255 5256 pio_time &= ~(0xffff << (16 * channel)); 5257 dma_time &= ~(0xffff << (16 * channel)); 5258 pio_mode &= ~(0xff << (8 * channel + 16)); 5259 udma_mode &= ~(0xff << (8 * channel + 16)); 5260 udma_mode &= ~(3 << (2 * channel)); 5261 5262 idedma_ctl = 0; 5263 5264 /* Per drive settings */ 5265 for (drive = 0; drive < 2; drive++) { 5266 drvp = &chp->ch_drive[drive]; 5267 /* If no drive, skip */ 5268 if ((drvp->drive_flags & DRIVE) == 0) 5269 continue; 5270 unit = drive + 2 * channel; 5271 /* add timing values, setup DMA if needed */ 5272 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 5273 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 5274 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 5275 (drvp->drive_flags & DRIVE_UDMA)) { 5276 /* use Ultra/DMA, check for 80-pin cable */ 5277 if (drvp->UDMA_mode > 2 && 5278 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 5279 drvp->UDMA_mode = 2; 5280 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 5281 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 5282 udma_mode |= 1 << unit; 5283 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5284 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 5285 (drvp->drive_flags & DRIVE_DMA)) { 5286 /* use Multiword DMA */ 5287 drvp->drive_flags &= ~DRIVE_UDMA; 5288 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 5289 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5290 } else { 5291 /* PIO only */ 5292 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 5293 } 5294 } 5295 5296 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 5297 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 5298 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 5299 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 5300 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 5301 5302 if (idedma_ctl != 0) { 5303 /* Add software bits in status register */ 5304 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5305 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 5306 } 5307 } 5308 5309 int 5310 serverworks_pci_intr(arg) 5311 void *arg; 5312 { 5313 struct pciide_softc *sc = arg; 5314 struct pciide_channel *cp; 5315 struct channel_softc *wdc_cp; 5316 int rv = 0; 5317 int dmastat, i, crv; 5318 5319 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5320 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5321 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 5322 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 5323 IDEDMA_CTL_INTR) 5324 continue; 5325 cp = &sc->pciide_channels[i]; 5326 wdc_cp = &cp->wdc_channel; 5327 crv = wdcintr(wdc_cp); 5328 if (crv == 0) { 5329 printf("%s:%d: bogus intr\n", 5330 sc->sc_wdcdev.sc_dev.dv_xname, i); 5331 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5332 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 5333 } else 5334 rv = 1; 5335 } 5336 return rv; 5337 } 5338 5339 void 5340 artisea_chip_map(sc, pa) 5341 struct pciide_softc *sc; 5342 struct pci_attach_args *pa; 5343 { 5344 struct pciide_channel *cp; 5345 bus_size_t cmdsize, ctlsize; 5346 pcireg_t interface; 5347 int channel; 5348 5349 if (pciide_chipen(sc, pa) == 0) 5350 return; 5351 5352 aprint_normal("%s: bus-master DMA support present", 5353 sc->sc_wdcdev.sc_dev.dv_xname); 5354 #ifndef PCIIDE_I31244_ENABLEDMA 5355 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 && 5356 PCI_REVISION(pa->pa_class) == 0) { 5357 aprint_normal(" but disabled due to rev. 0"); 5358 sc->sc_dma_ok = 0; 5359 } else 5360 #endif 5361 pciide_mapreg_dma(sc, pa); 5362 aprint_normal("\n"); 5363 5364 /* 5365 * XXX Configure LEDs to show activity. 5366 */ 5367 5368 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5369 WDC_CAPABILITY_MODE; 5370 sc->sc_wdcdev.PIO_cap = 4; 5371 if (sc->sc_dma_ok) { 5372 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5373 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5374 sc->sc_wdcdev.irqack = pciide_irqack; 5375 sc->sc_wdcdev.DMA_cap = 2; 5376 sc->sc_wdcdev.UDMA_cap = 6; 5377 } 5378 sc->sc_wdcdev.set_modes = sata_setup_channel; 5379 5380 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5381 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5382 5383 interface = PCI_INTERFACE(pa->pa_class); 5384 5385 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5386 cp = &sc->pciide_channels[channel]; 5387 if (pciide_chansetup(sc, channel, interface) == 0) 5388 continue; 5389 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5390 pciide_pci_intr); 5391 } 5392 } 5393
Indexes created Thu Oct 02 10:09:58 GMT 2025