pciide.c revision 1.207
1 /* $NetBSD: pciide.c,v 1.207 2003/10/05 17:48:49 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 35 /* 36 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by Christopher G. Demetriou 49 * for the NetBSD Project. 50 * 4. The name of the author may not be used to endorse or promote products 51 * derived from this software without specific prior written permission 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 54 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 55 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 56 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 57 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 58 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 62 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * PCI IDE controller driver. 67 * 68 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 69 * sys/dev/pci/ppb.c, revision 1.16). 70 * 71 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 72 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 73 * 5/16/94" from the PCI SIG. 74 * 75 */ 76 77 #include <sys/cdefs.h> 78 __KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.207 2003/10/05 17:48:49 bouyer Exp $"); 79 80 #ifndef WDCDEBUG 81 #define WDCDEBUG 82 #endif 83 84 #define DEBUG_DMA 0x01 85 #define DEBUG_XFERS 0x02 86 #define DEBUG_FUNCS 0x08 87 #define DEBUG_PROBE 0x10 88 #ifdef WDCDEBUG 89 int wdcdebug_pciide_mask = 0; 90 #define WDCDEBUG_PRINT(args, level) \ 91 if (wdcdebug_pciide_mask & (level)) printf args 92 #else 93 #define WDCDEBUG_PRINT(args, level) 94 #endif 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/device.h> 98 #include <sys/malloc.h> 99 100 #include <uvm/uvm_extern.h> 101 102 #include <machine/endian.h> 103 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcivar.h> 106 #include <dev/pci/pcidevs.h> 107 #include <dev/pci/pciidereg.h> 108 #include <dev/pci/pciidevar.h> 109 #include <dev/pci/pciide_piix_reg.h> 110 #include <dev/pci/pciide_amd_reg.h> 111 #include <dev/pci/pciide_apollo_reg.h> 112 #include <dev/pci/pciide_cmd_reg.h> 113 #include <dev/pci/pciide_cy693_reg.h> 114 #include <dev/pci/pciide_sis_reg.h> 115 #include <dev/pci/pciide_acer_reg.h> 116 #include <dev/pci/pciide_pdc202xx_reg.h> 117 #include <dev/pci/pciide_opti_reg.h> 118 #include <dev/pci/pciide_hpt_reg.h> 119 #include <dev/pci/pciide_acard_reg.h> 120 #include <dev/pci/pciide_sl82c105_reg.h> 121 #include <dev/pci/pciide_i31244_reg.h> 122 #include <dev/pci/pciide_sii3112_reg.h> 123 #include <dev/pci/cy82c693var.h> 124 125 #include "opt_pciide.h" 126 127 static const char dmaerrfmt[] = 128 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 129 130 /* inlines for reading/writing 8-bit PCI registers */ 131 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 132 int)); 133 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 134 int, u_int8_t)); 135 136 static __inline u_int8_t 137 pciide_pci_read(pc, pa, reg) 138 pci_chipset_tag_t pc; 139 pcitag_t pa; 140 int reg; 141 { 142 143 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 144 ((reg & 0x03) * 8) & 0xff); 145 } 146 147 static __inline void 148 pciide_pci_write(pc, pa, reg, val) 149 pci_chipset_tag_t pc; 150 pcitag_t pa; 151 int reg; 152 u_int8_t val; 153 { 154 pcireg_t pcival; 155 156 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 157 pcival &= ~(0xff << ((reg & 0x03) * 8)); 158 pcival |= (val << ((reg & 0x03) * 8)); 159 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 160 } 161 162 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 163 164 void sata_setup_channel __P((struct channel_softc*)); 165 166 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 167 void piix_setup_channel __P((struct channel_softc*)); 168 void piix3_4_setup_channel __P((struct channel_softc*)); 169 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 170 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 171 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 172 173 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void amd7x6_setup_channel __P((struct channel_softc*)); 175 176 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 177 void apollo_sata_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void apollo_setup_channel __P((struct channel_softc*)); 179 180 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void cmd0643_9_setup_channel __P((struct channel_softc*)); 183 void cmd_channel_map __P((struct pci_attach_args *, 184 struct pciide_softc *, int)); 185 int cmd_pci_intr __P((void *)); 186 void cmd646_9_irqack __P((struct channel_softc *)); 187 void cmd680_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 188 void cmd680_setup_channel __P((struct channel_softc*)); 189 void cmd680_channel_map __P((struct pci_attach_args *, 190 struct pciide_softc *, int)); 191 192 void cmd3112_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void cmd3112_setup_channel __P((struct channel_softc*)); 194 195 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 196 void cy693_setup_channel __P((struct channel_softc*)); 197 198 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 199 void sis_setup_channel __P((struct channel_softc*)); 200 void sis96x_setup_channel __P((struct channel_softc*)); 201 static int sis_hostbr_match __P(( struct pci_attach_args *)); 202 static int sis_south_match __P(( struct pci_attach_args *)); 203 204 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 205 void acer_setup_channel __P((struct channel_softc*)); 206 int acer_pci_intr __P((void *)); 207 208 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 209 void pdc202xx_setup_channel __P((struct channel_softc*)); 210 void pdc20268_setup_channel __P((struct channel_softc*)); 211 int pdc202xx_pci_intr __P((void *)); 212 int pdc20265_pci_intr __P((void *)); 213 static void pdc20262_dma_start __P((void*, int, int)); 214 static int pdc20262_dma_finish __P((void*, int, int, int)); 215 216 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 217 void opti_setup_channel __P((struct channel_softc*)); 218 219 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 220 void hpt_setup_channel __P((struct channel_softc*)); 221 int hpt_pci_intr __P((void *)); 222 223 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 224 void acard_setup_channel __P((struct channel_softc*)); 225 int acard_pci_intr __P((void *)); 226 227 void serverworks_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 228 void serverworks_setup_channel __P((struct channel_softc*)); 229 int serverworks_pci_intr __P((void *)); 230 231 void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 232 void sl82c105_setup_channel __P((struct channel_softc*)); 233 234 void pciide_channel_dma_setup __P((struct pciide_channel *)); 235 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 236 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 237 void pciide_dma_start __P((void*, int, int)); 238 int pciide_dma_finish __P((void*, int, int, int)); 239 void pciide_irqack __P((struct channel_softc *)); 240 241 void artisea_chip_map __P((struct pciide_softc*, struct pci_attach_args *)); 242 243 struct pciide_product_desc { 244 u_int32_t ide_product; 245 int ide_flags; 246 const char *ide_name; 247 /* map and setup chip, probe drives */ 248 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 249 }; 250 251 /* Flags for ide_flags */ 252 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 253 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 254 255 /* Default product description for devices not known from this controller */ 256 const struct pciide_product_desc default_product_desc = { 257 0, 258 0, 259 "Generic PCI IDE controller", 260 default_chip_map, 261 }; 262 263 const struct pciide_product_desc pciide_intel_products[] = { 264 { PCI_PRODUCT_INTEL_82092AA, 265 0, 266 "Intel 82092AA IDE controller", 267 default_chip_map, 268 }, 269 { PCI_PRODUCT_INTEL_82371FB_IDE, 270 0, 271 "Intel 82371FB IDE controller (PIIX)", 272 piix_chip_map, 273 }, 274 { PCI_PRODUCT_INTEL_82371SB_IDE, 275 0, 276 "Intel 82371SB IDE Interface (PIIX3)", 277 piix_chip_map, 278 }, 279 { PCI_PRODUCT_INTEL_82371AB_IDE, 280 0, 281 "Intel 82371AB IDE controller (PIIX4)", 282 piix_chip_map, 283 }, 284 { PCI_PRODUCT_INTEL_82440MX_IDE, 285 0, 286 "Intel 82440MX IDE controller", 287 piix_chip_map 288 }, 289 { PCI_PRODUCT_INTEL_82801AA_IDE, 290 0, 291 "Intel 82801AA IDE Controller (ICH)", 292 piix_chip_map, 293 }, 294 { PCI_PRODUCT_INTEL_82801AB_IDE, 295 0, 296 "Intel 82801AB IDE Controller (ICH0)", 297 piix_chip_map, 298 }, 299 { PCI_PRODUCT_INTEL_82801BA_IDE, 300 0, 301 "Intel 82801BA IDE Controller (ICH2)", 302 piix_chip_map, 303 }, 304 { PCI_PRODUCT_INTEL_82801BAM_IDE, 305 0, 306 "Intel 82801BAM IDE Controller (ICH2-M)", 307 piix_chip_map, 308 }, 309 { PCI_PRODUCT_INTEL_82801CA_IDE_1, 310 0, 311 "Intel 82801CA IDE Controller (ICH3)", 312 piix_chip_map, 313 }, 314 { PCI_PRODUCT_INTEL_82801CA_IDE_2, 315 0, 316 "Intel 82801CA IDE Controller (ICH3)", 317 piix_chip_map, 318 }, 319 { PCI_PRODUCT_INTEL_82801DB_IDE, 320 0, 321 "Intel 82801DB IDE Controller (ICH4)", 322 piix_chip_map, 323 }, 324 { PCI_PRODUCT_INTEL_82801DBM_IDE, 325 0, 326 "Intel 82801DBM IDE Controller (ICH4-M)", 327 piix_chip_map, 328 }, 329 { PCI_PRODUCT_INTEL_82801EB_IDE, 330 0, 331 "Intel 82801EB IDE Controller (ICH5)", 332 piix_chip_map, 333 }, 334 { PCI_PRODUCT_INTEL_31244, 335 0, 336 "Intel 31244 Serial ATA Controller", 337 artisea_chip_map, 338 }, 339 { PCI_PRODUCT_INTEL_82801EB_SATA, 340 0, 341 "Intel 82801EB Serial ATA Controller", 342 artisea_chip_map, 343 }, 344 { 0, 345 0, 346 NULL, 347 NULL 348 } 349 }; 350 351 const struct pciide_product_desc pciide_amd_products[] = { 352 { PCI_PRODUCT_AMD_PBC756_IDE, 353 0, 354 "Advanced Micro Devices AMD756 IDE Controller", 355 amd7x6_chip_map 356 }, 357 { PCI_PRODUCT_AMD_PBC766_IDE, 358 0, 359 "Advanced Micro Devices AMD766 IDE Controller", 360 amd7x6_chip_map 361 }, 362 { PCI_PRODUCT_AMD_PBC768_IDE, 363 0, 364 "Advanced Micro Devices AMD768 IDE Controller", 365 amd7x6_chip_map 366 }, 367 { PCI_PRODUCT_AMD_PBC8111_IDE, 368 0, 369 "Advanced Micro Devices AMD8111 IDE Controller", 370 amd7x6_chip_map 371 }, 372 { 0, 373 0, 374 NULL, 375 NULL 376 } 377 }; 378 379 const struct pciide_product_desc pciide_nvidia_products[] = { 380 { PCI_PRODUCT_NVIDIA_NFORCE_ATA100, 381 0, 382 "NVIDIA nForce IDE Controller", 383 amd7x6_chip_map 384 }, 385 { PCI_PRODUCT_NVIDIA_NFORCE2_ATA133, 386 0, 387 "NVIDIA nForce2 IDE Controller", 388 amd7x6_chip_map 389 }, 390 { 0, 391 0, 392 NULL, 393 NULL 394 } 395 }; 396 397 const struct pciide_product_desc pciide_cmd_products[] = { 398 { PCI_PRODUCT_CMDTECH_640, 399 0, 400 "CMD Technology PCI0640", 401 cmd_chip_map 402 }, 403 { PCI_PRODUCT_CMDTECH_643, 404 0, 405 "CMD Technology PCI0643", 406 cmd0643_9_chip_map, 407 }, 408 { PCI_PRODUCT_CMDTECH_646, 409 0, 410 "CMD Technology PCI0646", 411 cmd0643_9_chip_map, 412 }, 413 { PCI_PRODUCT_CMDTECH_648, 414 IDE_PCI_CLASS_OVERRIDE, 415 "CMD Technology PCI0648", 416 cmd0643_9_chip_map, 417 }, 418 { PCI_PRODUCT_CMDTECH_649, 419 IDE_PCI_CLASS_OVERRIDE, 420 "CMD Technology PCI0649", 421 cmd0643_9_chip_map, 422 }, 423 { PCI_PRODUCT_CMDTECH_680, 424 IDE_PCI_CLASS_OVERRIDE, 425 "Silicon Image 0680", 426 cmd680_chip_map, 427 }, 428 { PCI_PRODUCT_CMDTECH_3112, 429 IDE_PCI_CLASS_OVERRIDE, 430 "Silicon Image SATALink 3112", 431 cmd3112_chip_map, 432 }, 433 { 0, 434 0, 435 NULL, 436 NULL 437 } 438 }; 439 440 const struct pciide_product_desc pciide_via_products[] = { 441 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 442 0, 443 NULL, 444 apollo_chip_map, 445 }, 446 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 447 0, 448 NULL, 449 apollo_chip_map, 450 }, 451 { PCI_PRODUCT_VIATECH_VT8237_SATA, 452 IDE_PCI_CLASS_OVERRIDE, 453 "VIA Technologies VT8237 SATA Controller", 454 apollo_sata_chip_map, 455 }, 456 { 0, 457 0, 458 NULL, 459 NULL 460 } 461 }; 462 463 const struct pciide_product_desc pciide_cypress_products[] = { 464 { PCI_PRODUCT_CONTAQ_82C693, 465 IDE_16BIT_IOSPACE, 466 "Cypress 82C693 IDE Controller", 467 cy693_chip_map, 468 }, 469 { 0, 470 0, 471 NULL, 472 NULL 473 } 474 }; 475 476 const struct pciide_product_desc pciide_sis_products[] = { 477 { PCI_PRODUCT_SIS_5597_IDE, 478 0, 479 NULL, 480 sis_chip_map, 481 }, 482 { 0, 483 0, 484 NULL, 485 NULL 486 } 487 }; 488 489 const struct pciide_product_desc pciide_acer_products[] = { 490 { PCI_PRODUCT_ALI_M5229, 491 0, 492 "Acer Labs M5229 UDMA IDE Controller", 493 acer_chip_map, 494 }, 495 { 0, 496 0, 497 NULL, 498 NULL 499 } 500 }; 501 502 const struct pciide_product_desc pciide_promise_products[] = { 503 { PCI_PRODUCT_PROMISE_ULTRA33, 504 IDE_PCI_CLASS_OVERRIDE, 505 "Promise Ultra33/ATA Bus Master IDE Accelerator", 506 pdc202xx_chip_map, 507 }, 508 { PCI_PRODUCT_PROMISE_ULTRA66, 509 IDE_PCI_CLASS_OVERRIDE, 510 "Promise Ultra66/ATA Bus Master IDE Accelerator", 511 pdc202xx_chip_map, 512 }, 513 { PCI_PRODUCT_PROMISE_ULTRA100, 514 IDE_PCI_CLASS_OVERRIDE, 515 "Promise Ultra100/ATA Bus Master IDE Accelerator", 516 pdc202xx_chip_map, 517 }, 518 { PCI_PRODUCT_PROMISE_ULTRA100X, 519 IDE_PCI_CLASS_OVERRIDE, 520 "Promise Ultra100/ATA Bus Master IDE Accelerator", 521 pdc202xx_chip_map, 522 }, 523 { PCI_PRODUCT_PROMISE_ULTRA100TX2, 524 IDE_PCI_CLASS_OVERRIDE, 525 "Promise Ultra100TX2/ATA Bus Master IDE Accelerator", 526 pdc202xx_chip_map, 527 }, 528 { PCI_PRODUCT_PROMISE_ULTRA100TX2v2, 529 IDE_PCI_CLASS_OVERRIDE, 530 "Promise Ultra100TX2v2/ATA Bus Master IDE Accelerator", 531 pdc202xx_chip_map, 532 }, 533 { PCI_PRODUCT_PROMISE_ULTRA133, 534 IDE_PCI_CLASS_OVERRIDE, 535 "Promise Ultra133/ATA Bus Master IDE Accelerator", 536 pdc202xx_chip_map, 537 }, 538 { PCI_PRODUCT_PROMISE_ULTRA133TX2, 539 IDE_PCI_CLASS_OVERRIDE, 540 "Promise Ultra133TX2/ATA Bus Master IDE Accelerator", 541 pdc202xx_chip_map, 542 }, 543 { PCI_PRODUCT_PROMISE_MBULTRA133, 544 IDE_PCI_CLASS_OVERRIDE, 545 "Promise Ultra133/ATA Bus Master IDE Accelerator (MB)", 546 pdc202xx_chip_map, 547 }, 548 { PCI_PRODUCT_PROMISE_ULTRA133TX2v2, 549 IDE_PCI_CLASS_OVERRIDE, 550 "Promise Ultra133TX2v2/ATA Bus Master IDE Accelerator", 551 pdc202xx_chip_map, 552 }, 553 { PCI_PRODUCT_PROMISE_FASTTRAK133LITE, 554 IDE_PCI_CLASS_OVERRIDE, 555 "Promise Fasttrak133 Lite Bus Master IDE Accelerator", 556 pdc202xx_chip_map, 557 }, 558 { PCI_PRODUCT_PROMISE_SATA150TX2PLUS, 559 IDE_PCI_CLASS_OVERRIDE, 560 "Promise Serial ATA/150 TX2plus Bus Master IDE Accelerator", 561 pdc202xx_chip_map, 562 }, 563 { 0, 564 0, 565 NULL, 566 NULL 567 } 568 }; 569 570 const struct pciide_product_desc pciide_opti_products[] = { 571 { PCI_PRODUCT_OPTI_82C621, 572 0, 573 "OPTi 82c621 PCI IDE controller", 574 opti_chip_map, 575 }, 576 { PCI_PRODUCT_OPTI_82C568, 577 0, 578 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 579 opti_chip_map, 580 }, 581 { PCI_PRODUCT_OPTI_82D568, 582 0, 583 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 584 opti_chip_map, 585 }, 586 { 0, 587 0, 588 NULL, 589 NULL 590 } 591 }; 592 593 const struct pciide_product_desc pciide_triones_products[] = { 594 { PCI_PRODUCT_TRIONES_HPT366, 595 IDE_PCI_CLASS_OVERRIDE, 596 NULL, 597 hpt_chip_map, 598 }, 599 { PCI_PRODUCT_TRIONES_HPT372, 600 IDE_PCI_CLASS_OVERRIDE, 601 NULL, 602 hpt_chip_map 603 }, 604 { PCI_PRODUCT_TRIONES_HPT374, 605 IDE_PCI_CLASS_OVERRIDE, 606 NULL, 607 hpt_chip_map 608 }, 609 { 0, 610 0, 611 NULL, 612 NULL 613 } 614 }; 615 616 const struct pciide_product_desc pciide_acard_products[] = { 617 { PCI_PRODUCT_ACARD_ATP850U, 618 IDE_PCI_CLASS_OVERRIDE, 619 "Acard ATP850U Ultra33 IDE Controller", 620 acard_chip_map, 621 }, 622 { PCI_PRODUCT_ACARD_ATP860, 623 IDE_PCI_CLASS_OVERRIDE, 624 "Acard ATP860 Ultra66 IDE Controller", 625 acard_chip_map, 626 }, 627 { PCI_PRODUCT_ACARD_ATP860A, 628 IDE_PCI_CLASS_OVERRIDE, 629 "Acard ATP860-A Ultra66 IDE Controller", 630 acard_chip_map, 631 }, 632 { 0, 633 0, 634 NULL, 635 NULL 636 } 637 }; 638 639 const struct pciide_product_desc pciide_serverworks_products[] = { 640 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 641 0, 642 "ServerWorks OSB4 IDE Controller", 643 serverworks_chip_map, 644 }, 645 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 646 0, 647 "ServerWorks CSB5 IDE Controller", 648 serverworks_chip_map, 649 }, 650 { PCI_PRODUCT_SERVERWORKS_CSB6_IDE, 651 0, 652 "ServerWorks CSB6 RAID/IDE Controller", 653 serverworks_chip_map, 654 }, 655 { 0, 656 0, 657 NULL, 658 } 659 }; 660 661 const struct pciide_product_desc pciide_symphony_products[] = { 662 { PCI_PRODUCT_SYMPHONY_82C105, 663 0, 664 "Symphony Labs 82C105 IDE controller", 665 sl82c105_chip_map, 666 }, 667 { 0, 668 0, 669 NULL, 670 } 671 }; 672 673 const struct pciide_product_desc pciide_winbond_products[] = { 674 { PCI_PRODUCT_WINBOND_W83C553F_1, 675 0, 676 "Winbond W83C553F IDE controller", 677 sl82c105_chip_map, 678 }, 679 { 0, 680 0, 681 NULL, 682 } 683 }; 684 685 struct pciide_vendor_desc { 686 u_int32_t ide_vendor; 687 const struct pciide_product_desc *ide_products; 688 }; 689 690 const struct pciide_vendor_desc pciide_vendors[] = { 691 { PCI_VENDOR_INTEL, pciide_intel_products }, 692 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 693 { PCI_VENDOR_VIATECH, pciide_via_products }, 694 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 695 { PCI_VENDOR_SIS, pciide_sis_products }, 696 { PCI_VENDOR_ALI, pciide_acer_products }, 697 { PCI_VENDOR_PROMISE, pciide_promise_products }, 698 { PCI_VENDOR_AMD, pciide_amd_products }, 699 { PCI_VENDOR_OPTI, pciide_opti_products }, 700 { PCI_VENDOR_TRIONES, pciide_triones_products }, 701 { PCI_VENDOR_ACARD, pciide_acard_products }, 702 { PCI_VENDOR_SERVERWORKS, pciide_serverworks_products }, 703 { PCI_VENDOR_SYMPHONY, pciide_symphony_products }, 704 { PCI_VENDOR_WINBOND, pciide_winbond_products }, 705 { PCI_VENDOR_NVIDIA, pciide_nvidia_products }, 706 { 0, NULL } 707 }; 708 709 /* options passed via the 'flags' config keyword */ 710 #define PCIIDE_OPTIONS_DMA 0x01 711 #define PCIIDE_OPTIONS_NODMA 0x02 712 713 int pciide_match __P((struct device *, struct cfdata *, void *)); 714 void pciide_attach __P((struct device *, struct device *, void *)); 715 716 CFATTACH_DECL(pciide, sizeof(struct pciide_softc), 717 pciide_match, pciide_attach, NULL, NULL); 718 719 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 720 void pciide_mapregs_compat __P(( struct pci_attach_args *, 721 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 722 void pciide_mapregs_native __P((struct pci_attach_args *, 723 struct pciide_channel *, bus_size_t *, bus_size_t *, 724 int (*pci_intr) __P((void *)))); 725 void pciide_mapreg_dma __P((struct pciide_softc *, 726 struct pci_attach_args *)); 727 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 728 void pciide_mapchan __P((struct pci_attach_args *, 729 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 730 int (*pci_intr) __P((void *)))); 731 void pciide_map_compat_intr __P(( struct pci_attach_args *, 732 struct pciide_channel *, int)); 733 int pciide_compat_intr __P((void *)); 734 int pciide_pci_intr __P((void *)); 735 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 736 737 const struct pciide_product_desc * 738 pciide_lookup_product(id) 739 u_int32_t id; 740 { 741 const struct pciide_product_desc *pp; 742 const struct pciide_vendor_desc *vp; 743 744 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 745 if (PCI_VENDOR(id) == vp->ide_vendor) 746 break; 747 748 if ((pp = vp->ide_products) == NULL) 749 return NULL; 750 751 for (; pp->chip_map != NULL; pp++) 752 if (PCI_PRODUCT(id) == pp->ide_product) 753 break; 754 755 if (pp->chip_map == NULL) 756 return NULL; 757 return pp; 758 } 759 760 int 761 pciide_match(parent, match, aux) 762 struct device *parent; 763 struct cfdata *match; 764 void *aux; 765 { 766 struct pci_attach_args *pa = aux; 767 const struct pciide_product_desc *pp; 768 769 /* 770 * Check the ID register to see that it's a PCI IDE controller. 771 * If it is, we assume that we can deal with it; it _should_ 772 * work in a standardized way... 773 */ 774 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 775 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 776 return (1); 777 } 778 779 /* 780 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 781 * controllers. Let see if we can deal with it anyway. 782 */ 783 pp = pciide_lookup_product(pa->pa_id); 784 if (pp != NULL && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 785 return (1); 786 } 787 788 return (0); 789 } 790 791 void 792 pciide_attach(parent, self, aux) 793 struct device *parent, *self; 794 void *aux; 795 { 796 struct pci_attach_args *pa = aux; 797 pci_chipset_tag_t pc = pa->pa_pc; 798 pcitag_t tag = pa->pa_tag; 799 struct pciide_softc *sc = (struct pciide_softc *)self; 800 pcireg_t csr; 801 char devinfo[256]; 802 const char *displaydev; 803 804 aprint_naive(": disk controller\n"); 805 aprint_normal("\n"); 806 807 sc->sc_pci_vendor = PCI_VENDOR(pa->pa_id); 808 sc->sc_pp = pciide_lookup_product(pa->pa_id); 809 if (sc->sc_pp == NULL) { 810 sc->sc_pp = &default_product_desc; 811 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 812 displaydev = devinfo; 813 } else 814 displaydev = sc->sc_pp->ide_name; 815 816 /* if displaydev == NULL, printf is done in chip-specific map */ 817 if (displaydev) 818 aprint_normal("%s: %s (rev. 0x%02x)\n", 819 sc->sc_wdcdev.sc_dev.dv_xname, displaydev, 820 PCI_REVISION(pa->pa_class)); 821 822 sc->sc_pc = pa->pa_pc; 823 sc->sc_tag = pa->pa_tag; 824 825 /* Set up DMA defaults; these might be adjusted by chip_map. */ 826 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 827 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 828 829 #ifdef WDCDEBUG 830 if (wdcdebug_pciide_mask & DEBUG_PROBE) 831 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 832 #endif 833 sc->sc_pp->chip_map(sc, pa); 834 835 if (sc->sc_dma_ok) { 836 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 837 csr |= PCI_COMMAND_MASTER_ENABLE; 838 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 839 } 840 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 841 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 842 843 wdcattach(&sc->sc_wdcdev); 844 } 845 846 /* tell whether the chip is enabled or not */ 847 int 848 pciide_chipen(sc, pa) 849 struct pciide_softc *sc; 850 struct pci_attach_args *pa; 851 { 852 pcireg_t csr; 853 854 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 855 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 856 PCI_COMMAND_STATUS_REG); 857 aprint_normal("%s: device disabled (at %s)\n", 858 sc->sc_wdcdev.sc_dev.dv_xname, 859 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 860 "device" : "bridge"); 861 return 0; 862 } 863 return 1; 864 } 865 866 void 867 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 868 struct pci_attach_args *pa; 869 struct pciide_channel *cp; 870 int compatchan; 871 bus_size_t *cmdsizep, *ctlsizep; 872 { 873 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 874 struct channel_softc *wdc_cp = &cp->wdc_channel; 875 876 cp->compat = 1; 877 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 878 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 879 880 wdc_cp->cmd_iot = pa->pa_iot; 881 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 882 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 883 aprint_error("%s: couldn't map %s channel cmd regs\n", 884 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 885 goto bad; 886 } 887 888 wdc_cp->ctl_iot = pa->pa_iot; 889 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 890 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 891 aprint_error("%s: couldn't map %s channel ctl regs\n", 892 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 893 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 894 PCIIDE_COMPAT_CMD_SIZE); 895 goto bad; 896 } 897 898 wdc_cp->data32iot = wdc_cp->cmd_iot; 899 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 900 pciide_map_compat_intr(pa, cp, compatchan); 901 return; 902 903 bad: 904 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 905 return; 906 } 907 908 void 909 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 910 struct pci_attach_args * pa; 911 struct pciide_channel *cp; 912 bus_size_t *cmdsizep, *ctlsizep; 913 int (*pci_intr) __P((void *)); 914 { 915 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 916 struct channel_softc *wdc_cp = &cp->wdc_channel; 917 const char *intrstr; 918 pci_intr_handle_t intrhandle; 919 920 cp->compat = 0; 921 922 if (sc->sc_pci_ih == NULL) { 923 if (pci_intr_map(pa, &intrhandle) != 0) { 924 aprint_error("%s: couldn't map native-PCI interrupt\n", 925 sc->sc_wdcdev.sc_dev.dv_xname); 926 goto bad; 927 } 928 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 929 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 930 intrhandle, IPL_BIO, pci_intr, sc); 931 if (sc->sc_pci_ih != NULL) { 932 aprint_normal("%s: using %s for native-PCI interrupt\n", 933 sc->sc_wdcdev.sc_dev.dv_xname, 934 intrstr ? intrstr : "unknown interrupt"); 935 } else { 936 aprint_error( 937 "%s: couldn't establish native-PCI interrupt", 938 sc->sc_wdcdev.sc_dev.dv_xname); 939 if (intrstr != NULL) 940 aprint_normal(" at %s", intrstr); 941 aprint_normal("\n"); 942 goto bad; 943 } 944 } 945 cp->ih = sc->sc_pci_ih; 946 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 947 PCI_MAPREG_TYPE_IO, 0, 948 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 949 aprint_error("%s: couldn't map %s channel cmd regs\n", 950 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 951 goto bad; 952 } 953 954 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 955 PCI_MAPREG_TYPE_IO, 0, 956 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 957 aprint_error("%s: couldn't map %s channel ctl regs\n", 958 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 959 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 960 goto bad; 961 } 962 /* 963 * In native mode, 4 bytes of I/O space are mapped for the control 964 * register, the control register is at offset 2. Pass the generic 965 * code a handle for only one byte at the right offset. 966 */ 967 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 968 &wdc_cp->ctl_ioh) != 0) { 969 aprint_error("%s: unable to subregion %s channel ctl regs\n", 970 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 971 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 972 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 973 goto bad; 974 } 975 976 wdc_cp->data32iot = wdc_cp->cmd_iot; 977 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 978 return; 979 980 bad: 981 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 982 return; 983 } 984 985 void 986 pciide_mapreg_dma(sc, pa) 987 struct pciide_softc *sc; 988 struct pci_attach_args *pa; 989 { 990 pcireg_t maptype; 991 bus_addr_t addr; 992 993 /* 994 * Map DMA registers 995 * 996 * Note that sc_dma_ok is the right variable to test to see if 997 * DMA can be done. If the interface doesn't support DMA, 998 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 999 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 1000 * non-zero if the interface supports DMA and the registers 1001 * could be mapped. 1002 * 1003 * XXX Note that despite the fact that the Bus Master IDE specs 1004 * XXX say that "The bus master IDE function uses 16 bytes of IO 1005 * XXX space," some controllers (at least the United 1006 * XXX Microelectronics UM8886BF) place it in memory space. 1007 */ 1008 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 1009 PCIIDE_REG_BUS_MASTER_DMA); 1010 1011 switch (maptype) { 1012 case PCI_MAPREG_TYPE_IO: 1013 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 1014 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 1015 &addr, NULL, NULL) == 0); 1016 if (sc->sc_dma_ok == 0) { 1017 aprint_normal( 1018 ", but unused (couldn't query registers)"); 1019 break; 1020 } 1021 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 1022 && addr >= 0x10000) { 1023 sc->sc_dma_ok = 0; 1024 aprint_normal( 1025 ", but unused (registers at unsafe address " 1026 "%#lx)", (unsigned long)addr); 1027 break; 1028 } 1029 /* FALLTHROUGH */ 1030 1031 case PCI_MAPREG_MEM_TYPE_32BIT: 1032 sc->sc_dma_ok = (pci_mapreg_map(pa, 1033 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 1034 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 1035 sc->sc_dmat = pa->pa_dmat; 1036 if (sc->sc_dma_ok == 0) { 1037 aprint_normal(", but unused (couldn't map registers)"); 1038 } else { 1039 sc->sc_wdcdev.dma_arg = sc; 1040 sc->sc_wdcdev.dma_init = pciide_dma_init; 1041 sc->sc_wdcdev.dma_start = pciide_dma_start; 1042 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 1043 } 1044 1045 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1046 PCIIDE_OPTIONS_NODMA) { 1047 aprint_normal( 1048 ", but unused (forced off by config file)"); 1049 sc->sc_dma_ok = 0; 1050 } 1051 break; 1052 1053 default: 1054 sc->sc_dma_ok = 0; 1055 aprint_normal( 1056 ", but unsupported register maptype (0x%x)", maptype); 1057 } 1058 } 1059 1060 int 1061 pciide_compat_intr(arg) 1062 void *arg; 1063 { 1064 struct pciide_channel *cp = arg; 1065 1066 #ifdef DIAGNOSTIC 1067 /* should only be called for a compat channel */ 1068 if (cp->compat == 0) 1069 panic("pciide compat intr called for non-compat chan %p", cp); 1070 #endif 1071 return (wdcintr(&cp->wdc_channel)); 1072 } 1073 1074 int 1075 pciide_pci_intr(arg) 1076 void *arg; 1077 { 1078 struct pciide_softc *sc = arg; 1079 struct pciide_channel *cp; 1080 struct channel_softc *wdc_cp; 1081 int i, rv, crv; 1082 1083 rv = 0; 1084 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1085 cp = &sc->pciide_channels[i]; 1086 wdc_cp = &cp->wdc_channel; 1087 1088 /* If a compat channel skip. */ 1089 if (cp->compat) 1090 continue; 1091 /* if this channel not waiting for intr, skip */ 1092 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 1093 continue; 1094 1095 crv = wdcintr(wdc_cp); 1096 if (crv == 0) 1097 ; /* leave rv alone */ 1098 else if (crv == 1) 1099 rv = 1; /* claim the intr */ 1100 else if (rv == 0) /* crv should be -1 in this case */ 1101 rv = crv; /* if we've done no better, take it */ 1102 } 1103 return (rv); 1104 } 1105 1106 void 1107 pciide_channel_dma_setup(cp) 1108 struct pciide_channel *cp; 1109 { 1110 int drive; 1111 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1112 struct ata_drive_datas *drvp; 1113 1114 for (drive = 0; drive < 2; drive++) { 1115 drvp = &cp->wdc_channel.ch_drive[drive]; 1116 /* If no drive, skip */ 1117 if ((drvp->drive_flags & DRIVE) == 0) 1118 continue; 1119 /* setup DMA if needed */ 1120 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1121 (drvp->drive_flags & DRIVE_UDMA) == 0) || 1122 sc->sc_dma_ok == 0) { 1123 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1124 continue; 1125 } 1126 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 1127 != 0) { 1128 /* Abort DMA setup */ 1129 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1130 continue; 1131 } 1132 } 1133 } 1134 1135 int 1136 pciide_dma_table_setup(sc, channel, drive) 1137 struct pciide_softc *sc; 1138 int channel, drive; 1139 { 1140 bus_dma_segment_t seg; 1141 int error, rseg; 1142 const bus_size_t dma_table_size = 1143 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1144 struct pciide_dma_maps *dma_maps = 1145 &sc->pciide_channels[channel].dma_maps[drive]; 1146 1147 /* If table was already allocated, just return */ 1148 if (dma_maps->dma_table) 1149 return 0; 1150 1151 /* Allocate memory for the DMA tables and map it */ 1152 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1153 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1154 BUS_DMA_NOWAIT)) != 0) { 1155 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1156 "allocate", drive, error); 1157 return error; 1158 } 1159 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1160 dma_table_size, 1161 (caddr_t *)&dma_maps->dma_table, 1162 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1163 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1164 "map", drive, error); 1165 return error; 1166 } 1167 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 1168 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 1169 (unsigned long)seg.ds_addr), DEBUG_PROBE); 1170 /* Create and load table DMA map for this disk */ 1171 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1172 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1173 &dma_maps->dmamap_table)) != 0) { 1174 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1175 "create", drive, error); 1176 return error; 1177 } 1178 if ((error = bus_dmamap_load(sc->sc_dmat, 1179 dma_maps->dmamap_table, 1180 dma_maps->dma_table, 1181 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1182 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1183 "load", drive, error); 1184 return error; 1185 } 1186 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1187 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 1188 DEBUG_PROBE); 1189 /* Create a xfer DMA map for this drive */ 1190 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1191 NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 1192 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1193 &dma_maps->dmamap_xfer)) != 0) { 1194 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1195 "create xfer", drive, error); 1196 return error; 1197 } 1198 return 0; 1199 } 1200 1201 int 1202 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 1203 void *v; 1204 int channel, drive; 1205 void *databuf; 1206 size_t datalen; 1207 int flags; 1208 { 1209 struct pciide_softc *sc = v; 1210 int error, seg; 1211 struct pciide_dma_maps *dma_maps = 1212 &sc->pciide_channels[channel].dma_maps[drive]; 1213 1214 error = bus_dmamap_load(sc->sc_dmat, 1215 dma_maps->dmamap_xfer, 1216 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 1217 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 1218 if (error) { 1219 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 1220 "load xfer", drive, error); 1221 return error; 1222 } 1223 1224 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1225 dma_maps->dmamap_xfer->dm_mapsize, 1226 (flags & WDC_DMA_READ) ? 1227 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1228 1229 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1230 #ifdef DIAGNOSTIC 1231 /* A segment must not cross a 64k boundary */ 1232 { 1233 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1234 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1235 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1236 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1237 printf("pciide_dma: segment %d physical addr 0x%lx" 1238 " len 0x%lx not properly aligned\n", 1239 seg, phys, len); 1240 panic("pciide_dma: buf align"); 1241 } 1242 } 1243 #endif 1244 dma_maps->dma_table[seg].base_addr = 1245 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 1246 dma_maps->dma_table[seg].byte_count = 1247 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1248 IDEDMA_BYTE_COUNT_MASK); 1249 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1250 seg, le32toh(dma_maps->dma_table[seg].byte_count), 1251 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 1252 1253 } 1254 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1255 htole32(IDEDMA_BYTE_COUNT_EOT); 1256 1257 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1258 dma_maps->dmamap_table->dm_mapsize, 1259 BUS_DMASYNC_PREWRITE); 1260 1261 /* Maps are ready. Start DMA function */ 1262 #ifdef DIAGNOSTIC 1263 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1264 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1265 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 1266 panic("pciide_dma_init: table align"); 1267 } 1268 #endif 1269 1270 /* Clear status bits */ 1271 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1272 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1273 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1274 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1275 /* Write table addr */ 1276 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1277 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1278 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1279 /* set read/write */ 1280 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1281 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1282 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1283 /* remember flags */ 1284 dma_maps->dma_flags = flags; 1285 return 0; 1286 } 1287 1288 void 1289 pciide_dma_start(v, channel, drive) 1290 void *v; 1291 int channel, drive; 1292 { 1293 struct pciide_softc *sc = v; 1294 1295 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1296 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1297 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1298 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1299 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1300 } 1301 1302 int 1303 pciide_dma_finish(v, channel, drive, force) 1304 void *v; 1305 int channel, drive; 1306 int force; 1307 { 1308 struct pciide_softc *sc = v; 1309 u_int8_t status; 1310 int error = 0; 1311 struct pciide_dma_maps *dma_maps = 1312 &sc->pciide_channels[channel].dma_maps[drive]; 1313 1314 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1315 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1316 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1317 DEBUG_XFERS); 1318 1319 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1320 return WDC_DMAST_NOIRQ; 1321 1322 /* stop DMA channel */ 1323 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1324 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1325 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1326 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1327 1328 /* Unload the map of the data buffer */ 1329 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1330 dma_maps->dmamap_xfer->dm_mapsize, 1331 (dma_maps->dma_flags & WDC_DMA_READ) ? 1332 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1333 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1334 1335 if ((status & IDEDMA_CTL_ERR) != 0) { 1336 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1337 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1338 error |= WDC_DMAST_ERR; 1339 } 1340 1341 if ((status & IDEDMA_CTL_INTR) == 0) { 1342 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1343 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1344 drive, status); 1345 error |= WDC_DMAST_NOIRQ; 1346 } 1347 1348 if ((status & IDEDMA_CTL_ACT) != 0) { 1349 /* data underrun, may be a valid condition for ATAPI */ 1350 error |= WDC_DMAST_UNDER; 1351 } 1352 return error; 1353 } 1354 1355 void 1356 pciide_irqack(chp) 1357 struct channel_softc *chp; 1358 { 1359 struct pciide_channel *cp = (struct pciide_channel*)chp; 1360 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1361 1362 /* clear status bits in IDE DMA registers */ 1363 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1364 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1365 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1366 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1367 } 1368 1369 /* some common code used by several chip_map */ 1370 int 1371 pciide_chansetup(sc, channel, interface) 1372 struct pciide_softc *sc; 1373 int channel; 1374 pcireg_t interface; 1375 { 1376 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1377 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1378 cp->name = PCIIDE_CHANNEL_NAME(channel); 1379 cp->wdc_channel.channel = channel; 1380 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1381 cp->wdc_channel.ch_queue = 1382 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1383 if (cp->wdc_channel.ch_queue == NULL) { 1384 aprint_error("%s %s channel: " 1385 "can't allocate memory for command queue", 1386 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1387 return 0; 1388 } 1389 aprint_normal("%s: %s channel %s to %s mode\n", 1390 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1391 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1392 "configured" : "wired", 1393 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1394 "native-PCI" : "compatibility"); 1395 return 1; 1396 } 1397 1398 /* some common code used by several chip channel_map */ 1399 void 1400 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1401 struct pci_attach_args *pa; 1402 struct pciide_channel *cp; 1403 pcireg_t interface; 1404 bus_size_t *cmdsizep, *ctlsizep; 1405 int (*pci_intr) __P((void *)); 1406 { 1407 struct channel_softc *wdc_cp = &cp->wdc_channel; 1408 1409 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1410 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr); 1411 else 1412 pciide_mapregs_compat(pa, cp, wdc_cp->channel, cmdsizep, 1413 ctlsizep); 1414 } 1415 1416 /* 1417 * generic code to map the compat intr. 1418 */ 1419 void 1420 pciide_map_compat_intr(pa, cp, compatchan) 1421 struct pci_attach_args *pa; 1422 struct pciide_channel *cp; 1423 int compatchan; 1424 { 1425 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1426 1427 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1428 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1429 pa, compatchan, pciide_compat_intr, cp); 1430 if (cp->ih == NULL) { 1431 #endif 1432 aprint_error("%s: no compatibility interrupt for use by %s " 1433 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1434 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 1435 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 1436 } 1437 #endif 1438 } 1439 1440 void 1441 default_chip_map(sc, pa) 1442 struct pciide_softc *sc; 1443 struct pci_attach_args *pa; 1444 { 1445 struct pciide_channel *cp; 1446 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1447 pcireg_t csr; 1448 int channel, drive; 1449 struct ata_drive_datas *drvp; 1450 u_int8_t idedma_ctl; 1451 bus_size_t cmdsize, ctlsize; 1452 char *failreason; 1453 1454 if (pciide_chipen(sc, pa) == 0) 1455 return; 1456 1457 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1458 aprint_normal("%s: bus-master DMA support present", 1459 sc->sc_wdcdev.sc_dev.dv_xname); 1460 if (sc->sc_pp == &default_product_desc && 1461 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1462 PCIIDE_OPTIONS_DMA) == 0) { 1463 aprint_normal(", but unused (no driver support)"); 1464 sc->sc_dma_ok = 0; 1465 } else { 1466 pciide_mapreg_dma(sc, pa); 1467 if (sc->sc_dma_ok != 0) 1468 aprint_normal(", used without full driver " 1469 "support"); 1470 } 1471 } else { 1472 aprint_normal("%s: hardware does not support DMA", 1473 sc->sc_wdcdev.sc_dev.dv_xname); 1474 sc->sc_dma_ok = 0; 1475 } 1476 aprint_normal("\n"); 1477 if (sc->sc_dma_ok) { 1478 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1479 sc->sc_wdcdev.irqack = pciide_irqack; 1480 } 1481 sc->sc_wdcdev.PIO_cap = 0; 1482 sc->sc_wdcdev.DMA_cap = 0; 1483 1484 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1485 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1486 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1487 1488 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1489 cp = &sc->pciide_channels[channel]; 1490 if (pciide_chansetup(sc, channel, interface) == 0) 1491 continue; 1492 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1493 pciide_pci_intr); 1494 if (cp->wdc_channel.ch_flags & WDCF_DISABLED) 1495 continue; 1496 /* 1497 * Check to see if something appears to be there. 1498 */ 1499 failreason = NULL; 1500 if (!wdcprobe(&cp->wdc_channel)) { 1501 failreason = "not responding; disabled or no drives?"; 1502 goto next; 1503 } 1504 /* 1505 * Now, make sure it's actually attributable to this PCI IDE 1506 * channel by trying to access the channel again while the 1507 * PCI IDE controller's I/O space is disabled. (If the 1508 * channel no longer appears to be there, it belongs to 1509 * this controller.) YUCK! 1510 */ 1511 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1512 PCI_COMMAND_STATUS_REG); 1513 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1514 csr & ~PCI_COMMAND_IO_ENABLE); 1515 if (wdcprobe(&cp->wdc_channel)) 1516 failreason = "other hardware responding at addresses"; 1517 pci_conf_write(sc->sc_pc, sc->sc_tag, 1518 PCI_COMMAND_STATUS_REG, csr); 1519 next: 1520 if (failreason) { 1521 aprint_error("%s: %s channel ignored (%s)\n", 1522 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1523 failreason); 1524 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 1525 } 1526 } 1527 1528 if (sc->sc_dma_ok == 0) 1529 return; 1530 1531 /* Allocate DMA maps */ 1532 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1533 idedma_ctl = 0; 1534 cp = &sc->pciide_channels[channel]; 1535 for (drive = 0; drive < 2; drive++) { 1536 drvp = &cp->wdc_channel.ch_drive[drive]; 1537 /* If no drive, skip */ 1538 if ((drvp->drive_flags & DRIVE) == 0) 1539 continue; 1540 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1541 continue; 1542 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1543 /* Abort DMA setup */ 1544 aprint_error( 1545 "%s:%d:%d: can't allocate DMA maps, " 1546 "using PIO transfers\n", 1547 sc->sc_wdcdev.sc_dev.dv_xname, 1548 channel, drive); 1549 drvp->drive_flags &= ~DRIVE_DMA; 1550 } 1551 aprint_normal("%s:%d:%d: using DMA data transfers\n", 1552 sc->sc_wdcdev.sc_dev.dv_xname, 1553 channel, drive); 1554 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1555 } 1556 if (idedma_ctl != 0) { 1557 /* Add software bits in status register */ 1558 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1559 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1560 idedma_ctl); 1561 } 1562 } 1563 } 1564 1565 void 1566 sata_setup_channel(chp) 1567 struct channel_softc *chp; 1568 { 1569 struct ata_drive_datas *drvp; 1570 int drive; 1571 u_int32_t idedma_ctl; 1572 struct pciide_channel *cp = (struct pciide_channel*)chp; 1573 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 1574 1575 /* setup DMA if needed */ 1576 pciide_channel_dma_setup(cp); 1577 1578 idedma_ctl = 0; 1579 1580 for (drive = 0; drive < 2; drive++) { 1581 drvp = &chp->ch_drive[drive]; 1582 /* If no drive, skip */ 1583 if ((drvp->drive_flags & DRIVE) == 0) 1584 continue; 1585 if (drvp->drive_flags & DRIVE_UDMA) { 1586 /* use Ultra/DMA */ 1587 drvp->drive_flags &= ~DRIVE_DMA; 1588 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1589 } else if (drvp->drive_flags & DRIVE_DMA) { 1590 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1591 } 1592 } 1593 1594 /* 1595 * Nothing to do to setup modes; it is meaningless in S-ATA 1596 * (but many S-ATA drives still want to get the SET_FEATURE 1597 * command). 1598 */ 1599 if (idedma_ctl != 0) { 1600 /* Add software bits in status register */ 1601 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1602 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1603 idedma_ctl); 1604 } 1605 } 1606 1607 void 1608 piix_chip_map(sc, pa) 1609 struct pciide_softc *sc; 1610 struct pci_attach_args *pa; 1611 { 1612 struct pciide_channel *cp; 1613 int channel; 1614 u_int32_t idetim; 1615 bus_size_t cmdsize, ctlsize; 1616 1617 if (pciide_chipen(sc, pa) == 0) 1618 return; 1619 1620 aprint_normal("%s: bus-master DMA support present", 1621 sc->sc_wdcdev.sc_dev.dv_xname); 1622 pciide_mapreg_dma(sc, pa); 1623 aprint_normal("\n"); 1624 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1625 WDC_CAPABILITY_MODE; 1626 if (sc->sc_dma_ok) { 1627 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1628 sc->sc_wdcdev.irqack = pciide_irqack; 1629 switch(sc->sc_pp->ide_product) { 1630 case PCI_PRODUCT_INTEL_82371AB_IDE: 1631 case PCI_PRODUCT_INTEL_82440MX_IDE: 1632 case PCI_PRODUCT_INTEL_82801AA_IDE: 1633 case PCI_PRODUCT_INTEL_82801AB_IDE: 1634 case PCI_PRODUCT_INTEL_82801BA_IDE: 1635 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1636 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1637 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1638 case PCI_PRODUCT_INTEL_82801DB_IDE: 1639 case PCI_PRODUCT_INTEL_82801DBM_IDE: 1640 case PCI_PRODUCT_INTEL_82801EB_IDE: 1641 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1642 } 1643 } 1644 sc->sc_wdcdev.PIO_cap = 4; 1645 sc->sc_wdcdev.DMA_cap = 2; 1646 switch(sc->sc_pp->ide_product) { 1647 case PCI_PRODUCT_INTEL_82801AA_IDE: 1648 sc->sc_wdcdev.UDMA_cap = 4; 1649 break; 1650 case PCI_PRODUCT_INTEL_82801BA_IDE: 1651 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1652 case PCI_PRODUCT_INTEL_82801CA_IDE_1: 1653 case PCI_PRODUCT_INTEL_82801CA_IDE_2: 1654 case PCI_PRODUCT_INTEL_82801DB_IDE: 1655 case PCI_PRODUCT_INTEL_82801DBM_IDE: 1656 case PCI_PRODUCT_INTEL_82801EB_IDE: 1657 sc->sc_wdcdev.UDMA_cap = 5; 1658 break; 1659 default: 1660 sc->sc_wdcdev.UDMA_cap = 2; 1661 } 1662 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1663 sc->sc_wdcdev.set_modes = piix_setup_channel; 1664 else 1665 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1666 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1667 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1668 1669 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1670 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1671 DEBUG_PROBE); 1672 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1673 WDCDEBUG_PRINT((", sidetim=0x%x", 1674 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1675 DEBUG_PROBE); 1676 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1677 WDCDEBUG_PRINT((", udamreg 0x%x", 1678 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1679 DEBUG_PROBE); 1680 } 1681 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1682 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1683 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1684 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1685 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1686 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1687 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 1688 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 1689 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE ) { 1690 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1691 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1692 DEBUG_PROBE); 1693 } 1694 1695 } 1696 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1697 1698 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1699 cp = &sc->pciide_channels[channel]; 1700 /* PIIX is compat-only */ 1701 if (pciide_chansetup(sc, channel, 0) == 0) 1702 continue; 1703 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1704 if ((PIIX_IDETIM_READ(idetim, channel) & 1705 PIIX_IDETIM_IDE) == 0) { 1706 #if 1 1707 aprint_normal("%s: %s channel ignored (disabled)\n", 1708 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1709 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 1710 continue; 1711 #else 1712 pcireg_t interface; 1713 1714 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1715 channel); 1716 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1717 idetim); 1718 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1719 sc->sc_tag, PCI_CLASS_REG)); 1720 aprint_normal("channel %d idetim=%08x interface=%02x\n", 1721 channel, idetim, interface); 1722 #endif 1723 } 1724 /* PIIX are compat-only pciide devices */ 1725 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1726 } 1727 1728 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1729 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1730 DEBUG_PROBE); 1731 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1732 WDCDEBUG_PRINT((", sidetim=0x%x", 1733 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1734 DEBUG_PROBE); 1735 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1736 WDCDEBUG_PRINT((", udamreg 0x%x", 1737 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1738 DEBUG_PROBE); 1739 } 1740 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1741 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1742 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1743 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1744 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1745 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1746 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 1747 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE) { 1748 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1749 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1750 DEBUG_PROBE); 1751 } 1752 } 1753 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1754 } 1755 1756 void 1757 piix_setup_channel(chp) 1758 struct channel_softc *chp; 1759 { 1760 u_int8_t mode[2], drive; 1761 u_int32_t oidetim, idetim, idedma_ctl; 1762 struct pciide_channel *cp = (struct pciide_channel*)chp; 1763 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1764 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1765 1766 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1767 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1768 idedma_ctl = 0; 1769 1770 /* set up new idetim: Enable IDE registers decode */ 1771 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1772 chp->channel); 1773 1774 /* setup DMA */ 1775 pciide_channel_dma_setup(cp); 1776 1777 /* 1778 * Here we have to mess up with drives mode: PIIX can't have 1779 * different timings for master and slave drives. 1780 * We need to find the best combination. 1781 */ 1782 1783 /* If both drives supports DMA, take the lower mode */ 1784 if ((drvp[0].drive_flags & DRIVE_DMA) && 1785 (drvp[1].drive_flags & DRIVE_DMA)) { 1786 mode[0] = mode[1] = 1787 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1788 drvp[0].DMA_mode = mode[0]; 1789 drvp[1].DMA_mode = mode[1]; 1790 goto ok; 1791 } 1792 /* 1793 * If only one drive supports DMA, use its mode, and 1794 * put the other one in PIO mode 0 if mode not compatible 1795 */ 1796 if (drvp[0].drive_flags & DRIVE_DMA) { 1797 mode[0] = drvp[0].DMA_mode; 1798 mode[1] = drvp[1].PIO_mode; 1799 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1800 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1801 mode[1] = drvp[1].PIO_mode = 0; 1802 goto ok; 1803 } 1804 if (drvp[1].drive_flags & DRIVE_DMA) { 1805 mode[1] = drvp[1].DMA_mode; 1806 mode[0] = drvp[0].PIO_mode; 1807 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1808 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1809 mode[0] = drvp[0].PIO_mode = 0; 1810 goto ok; 1811 } 1812 /* 1813 * If both drives are not DMA, takes the lower mode, unless 1814 * one of them is PIO mode < 2 1815 */ 1816 if (drvp[0].PIO_mode < 2) { 1817 mode[0] = drvp[0].PIO_mode = 0; 1818 mode[1] = drvp[1].PIO_mode; 1819 } else if (drvp[1].PIO_mode < 2) { 1820 mode[1] = drvp[1].PIO_mode = 0; 1821 mode[0] = drvp[0].PIO_mode; 1822 } else { 1823 mode[0] = mode[1] = 1824 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1825 drvp[0].PIO_mode = mode[0]; 1826 drvp[1].PIO_mode = mode[1]; 1827 } 1828 ok: /* The modes are setup */ 1829 for (drive = 0; drive < 2; drive++) { 1830 if (drvp[drive].drive_flags & DRIVE_DMA) { 1831 idetim |= piix_setup_idetim_timings( 1832 mode[drive], 1, chp->channel); 1833 goto end; 1834 } 1835 } 1836 /* If we are there, none of the drives are DMA */ 1837 if (mode[0] >= 2) 1838 idetim |= piix_setup_idetim_timings( 1839 mode[0], 0, chp->channel); 1840 else 1841 idetim |= piix_setup_idetim_timings( 1842 mode[1], 0, chp->channel); 1843 end: /* 1844 * timing mode is now set up in the controller. Enable 1845 * it per-drive 1846 */ 1847 for (drive = 0; drive < 2; drive++) { 1848 /* If no drive, skip */ 1849 if ((drvp[drive].drive_flags & DRIVE) == 0) 1850 continue; 1851 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1852 if (drvp[drive].drive_flags & DRIVE_DMA) 1853 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1854 } 1855 if (idedma_ctl != 0) { 1856 /* Add software bits in status register */ 1857 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1858 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1859 idedma_ctl); 1860 } 1861 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1862 } 1863 1864 void 1865 piix3_4_setup_channel(chp) 1866 struct channel_softc *chp; 1867 { 1868 struct ata_drive_datas *drvp; 1869 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1870 struct pciide_channel *cp = (struct pciide_channel*)chp; 1871 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1872 int drive; 1873 int channel = chp->channel; 1874 1875 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1876 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1877 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1878 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1879 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1880 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1881 PIIX_SIDETIM_RTC_MASK(channel)); 1882 idedma_ctl = 0; 1883 1884 /* set up new idetim: Enable IDE registers decode */ 1885 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1886 1887 /* setup DMA if needed */ 1888 pciide_channel_dma_setup(cp); 1889 1890 for (drive = 0; drive < 2; drive++) { 1891 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1892 PIIX_UDMATIM_SET(0x3, channel, drive)); 1893 drvp = &chp->ch_drive[drive]; 1894 /* If no drive, skip */ 1895 if ((drvp->drive_flags & DRIVE) == 0) 1896 continue; 1897 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1898 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1899 goto pio; 1900 1901 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1902 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1903 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1904 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1905 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1906 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1907 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 1908 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 1909 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE) { 1910 ideconf |= PIIX_CONFIG_PINGPONG; 1911 } 1912 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1913 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE || 1914 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_1 || 1915 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801CA_IDE_2 || 1916 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DB_IDE || 1917 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801DBM_IDE || 1918 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801EB_IDE) { 1919 /* setup Ultra/100 */ 1920 if (drvp->UDMA_mode > 2 && 1921 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1922 drvp->UDMA_mode = 2; 1923 if (drvp->UDMA_mode > 4) { 1924 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1925 } else { 1926 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1927 if (drvp->UDMA_mode > 2) { 1928 ideconf |= PIIX_CONFIG_UDMA66(channel, 1929 drive); 1930 } else { 1931 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1932 drive); 1933 } 1934 } 1935 } 1936 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1937 /* setup Ultra/66 */ 1938 if (drvp->UDMA_mode > 2 && 1939 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1940 drvp->UDMA_mode = 2; 1941 if (drvp->UDMA_mode > 2) 1942 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1943 else 1944 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1945 } 1946 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1947 (drvp->drive_flags & DRIVE_UDMA)) { 1948 /* use Ultra/DMA */ 1949 drvp->drive_flags &= ~DRIVE_DMA; 1950 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1951 udmareg |= PIIX_UDMATIM_SET( 1952 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1953 } else { 1954 /* use Multiword DMA */ 1955 drvp->drive_flags &= ~DRIVE_UDMA; 1956 if (drive == 0) { 1957 idetim |= piix_setup_idetim_timings( 1958 drvp->DMA_mode, 1, channel); 1959 } else { 1960 sidetim |= piix_setup_sidetim_timings( 1961 drvp->DMA_mode, 1, channel); 1962 idetim =PIIX_IDETIM_SET(idetim, 1963 PIIX_IDETIM_SITRE, channel); 1964 } 1965 } 1966 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1967 1968 pio: /* use PIO mode */ 1969 idetim |= piix_setup_idetim_drvs(drvp); 1970 if (drive == 0) { 1971 idetim |= piix_setup_idetim_timings( 1972 drvp->PIO_mode, 0, channel); 1973 } else { 1974 sidetim |= piix_setup_sidetim_timings( 1975 drvp->PIO_mode, 0, channel); 1976 idetim =PIIX_IDETIM_SET(idetim, 1977 PIIX_IDETIM_SITRE, channel); 1978 } 1979 } 1980 if (idedma_ctl != 0) { 1981 /* Add software bits in status register */ 1982 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1983 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1984 idedma_ctl); 1985 } 1986 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1987 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1988 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1989 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1990 } 1991 1992 1993 /* setup ISP and RTC fields, based on mode */ 1994 static u_int32_t 1995 piix_setup_idetim_timings(mode, dma, channel) 1996 u_int8_t mode; 1997 u_int8_t dma; 1998 u_int8_t channel; 1999 { 2000 2001 if (dma) 2002 return PIIX_IDETIM_SET(0, 2003 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 2004 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 2005 channel); 2006 else 2007 return PIIX_IDETIM_SET(0, 2008 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 2009 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 2010 channel); 2011 } 2012 2013 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 2014 static u_int32_t 2015 piix_setup_idetim_drvs(drvp) 2016 struct ata_drive_datas *drvp; 2017 { 2018 u_int32_t ret = 0; 2019 struct channel_softc *chp = drvp->chnl_softc; 2020 u_int8_t channel = chp->channel; 2021 u_int8_t drive = drvp->drive; 2022 2023 /* 2024 * If drive is using UDMA, timings setups are independant 2025 * So just check DMA and PIO here. 2026 */ 2027 if (drvp->drive_flags & DRIVE_DMA) { 2028 /* if mode = DMA mode 0, use compatible timings */ 2029 if ((drvp->drive_flags & DRIVE_DMA) && 2030 drvp->DMA_mode == 0) { 2031 drvp->PIO_mode = 0; 2032 return ret; 2033 } 2034 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2035 /* 2036 * PIO and DMA timings are the same, use fast timings for PIO 2037 * too, else use compat timings. 2038 */ 2039 if ((piix_isp_pio[drvp->PIO_mode] != 2040 piix_isp_dma[drvp->DMA_mode]) || 2041 (piix_rtc_pio[drvp->PIO_mode] != 2042 piix_rtc_dma[drvp->DMA_mode])) 2043 drvp->PIO_mode = 0; 2044 /* if PIO mode <= 2, use compat timings for PIO */ 2045 if (drvp->PIO_mode <= 2) { 2046 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 2047 channel); 2048 return ret; 2049 } 2050 } 2051 2052 /* 2053 * Now setup PIO modes. If mode < 2, use compat timings. 2054 * Else enable fast timings. Enable IORDY and prefetch/post 2055 * if PIO mode >= 3. 2056 */ 2057 2058 if (drvp->PIO_mode < 2) 2059 return ret; 2060 2061 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 2062 if (drvp->PIO_mode >= 3) { 2063 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 2064 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 2065 } 2066 return ret; 2067 } 2068 2069 /* setup values in SIDETIM registers, based on mode */ 2070 static u_int32_t 2071 piix_setup_sidetim_timings(mode, dma, channel) 2072 u_int8_t mode; 2073 u_int8_t dma; 2074 u_int8_t channel; 2075 { 2076 if (dma) 2077 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 2078 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 2079 else 2080 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 2081 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 2082 } 2083 2084 void 2085 amd7x6_chip_map(sc, pa) 2086 struct pciide_softc *sc; 2087 struct pci_attach_args *pa; 2088 { 2089 struct pciide_channel *cp; 2090 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2091 int channel; 2092 pcireg_t chanenable; 2093 bus_size_t cmdsize, ctlsize; 2094 2095 if (pciide_chipen(sc, pa) == 0) 2096 return; 2097 2098 aprint_normal("%s: bus-master DMA support present", 2099 sc->sc_wdcdev.sc_dev.dv_xname); 2100 pciide_mapreg_dma(sc, pa); 2101 aprint_normal("\n"); 2102 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2103 WDC_CAPABILITY_MODE; 2104 if (sc->sc_dma_ok) { 2105 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2106 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2107 sc->sc_wdcdev.irqack = pciide_irqack; 2108 } 2109 sc->sc_wdcdev.PIO_cap = 4; 2110 sc->sc_wdcdev.DMA_cap = 2; 2111 2112 switch (sc->sc_pci_vendor) { 2113 case PCI_VENDOR_AMD: 2114 switch (sc->sc_pp->ide_product) { 2115 case PCI_PRODUCT_AMD_PBC766_IDE: 2116 case PCI_PRODUCT_AMD_PBC768_IDE: 2117 case PCI_PRODUCT_AMD_PBC8111_IDE: 2118 sc->sc_wdcdev.UDMA_cap = 5; 2119 break; 2120 default: 2121 sc->sc_wdcdev.UDMA_cap = 4; 2122 } 2123 sc->sc_amd_regbase = AMD7X6_AMD_REGBASE; 2124 break; 2125 2126 case PCI_VENDOR_NVIDIA: 2127 switch (sc->sc_pp->ide_product) { 2128 case PCI_PRODUCT_NVIDIA_NFORCE_ATA100: 2129 sc->sc_wdcdev.UDMA_cap = 5; 2130 break; 2131 case PCI_PRODUCT_NVIDIA_NFORCE2_ATA133: 2132 sc->sc_wdcdev.UDMA_cap = 6; 2133 break; 2134 } 2135 sc->sc_amd_regbase = AMD7X6_NVIDIA_REGBASE; 2136 break; 2137 2138 default: 2139 panic("amd7x6_chip_map: unknown vendor"); 2140 } 2141 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 2142 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2143 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2144 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, 2145 AMD7X6_CHANSTATUS_EN(sc)); 2146 2147 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 2148 DEBUG_PROBE); 2149 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2150 cp = &sc->pciide_channels[channel]; 2151 if (pciide_chansetup(sc, channel, interface) == 0) 2152 continue; 2153 2154 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 2155 aprint_normal("%s: %s channel ignored (disabled)\n", 2156 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2157 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 2158 continue; 2159 } 2160 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2161 pciide_pci_intr); 2162 } 2163 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN(sc), 2164 chanenable); 2165 return; 2166 } 2167 2168 void 2169 amd7x6_setup_channel(chp) 2170 struct channel_softc *chp; 2171 { 2172 u_int32_t udmatim_reg, datatim_reg; 2173 u_int8_t idedma_ctl; 2174 int mode, drive; 2175 struct ata_drive_datas *drvp; 2176 struct pciide_channel *cp = (struct pciide_channel*)chp; 2177 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2178 #ifndef PCIIDE_AMD756_ENABLEDMA 2179 int rev = PCI_REVISION( 2180 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2181 #endif 2182 2183 idedma_ctl = 0; 2184 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc)); 2185 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc)); 2186 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 2187 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 2188 2189 /* setup DMA if needed */ 2190 pciide_channel_dma_setup(cp); 2191 2192 for (drive = 0; drive < 2; drive++) { 2193 drvp = &chp->ch_drive[drive]; 2194 /* If no drive, skip */ 2195 if ((drvp->drive_flags & DRIVE) == 0) 2196 continue; 2197 /* add timing values, setup DMA if needed */ 2198 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2199 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2200 mode = drvp->PIO_mode; 2201 goto pio; 2202 } 2203 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2204 (drvp->drive_flags & DRIVE_UDMA)) { 2205 /* use Ultra/DMA */ 2206 drvp->drive_flags &= ~DRIVE_DMA; 2207 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 2208 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 2209 AMD7X6_UDMA_TIME(chp->channel, drive, 2210 amd7x6_udma_tim[drvp->UDMA_mode]); 2211 /* can use PIO timings, MW DMA unused */ 2212 mode = drvp->PIO_mode; 2213 } else { 2214 /* use Multiword DMA, but only if revision is OK */ 2215 drvp->drive_flags &= ~DRIVE_UDMA; 2216 #ifndef PCIIDE_AMD756_ENABLEDMA 2217 /* 2218 * The workaround doesn't seem to be necessary 2219 * with all drives, so it can be disabled by 2220 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 2221 * triggered. 2222 */ 2223 if (sc->sc_pci_vendor == PCI_VENDOR_AMD && 2224 sc->sc_pp->ide_product == 2225 PCI_PRODUCT_AMD_PBC756_IDE && 2226 AMD756_CHIPREV_DISABLEDMA(rev)) { 2227 aprint_normal( 2228 "%s:%d:%d: multi-word DMA disabled due " 2229 "to chip revision\n", 2230 sc->sc_wdcdev.sc_dev.dv_xname, 2231 chp->channel, drive); 2232 mode = drvp->PIO_mode; 2233 drvp->drive_flags &= ~DRIVE_DMA; 2234 goto pio; 2235 } 2236 #endif 2237 /* mode = min(pio, dma+2) */ 2238 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2239 mode = drvp->PIO_mode; 2240 else 2241 mode = drvp->DMA_mode + 2; 2242 } 2243 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2244 2245 pio: /* setup PIO mode */ 2246 if (mode <= 2) { 2247 drvp->DMA_mode = 0; 2248 drvp->PIO_mode = 0; 2249 mode = 0; 2250 } else { 2251 drvp->PIO_mode = mode; 2252 drvp->DMA_mode = mode - 2; 2253 } 2254 datatim_reg |= 2255 AMD7X6_DATATIM_PULSE(chp->channel, drive, 2256 amd7x6_pio_set[mode]) | 2257 AMD7X6_DATATIM_RECOV(chp->channel, drive, 2258 amd7x6_pio_rec[mode]); 2259 } 2260 if (idedma_ctl != 0) { 2261 /* Add software bits in status register */ 2262 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2263 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2264 idedma_ctl); 2265 } 2266 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM(sc), datatim_reg); 2267 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA(sc), udmatim_reg); 2268 } 2269 2270 void 2271 apollo_chip_map(sc, pa) 2272 struct pciide_softc *sc; 2273 struct pci_attach_args *pa; 2274 { 2275 struct pciide_channel *cp; 2276 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2277 int channel; 2278 u_int32_t ideconf; 2279 bus_size_t cmdsize, ctlsize; 2280 pcitag_t pcib_tag; 2281 pcireg_t pcib_id, pcib_class; 2282 2283 if (pciide_chipen(sc, pa) == 0) 2284 return; 2285 2286 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2287 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2288 /* and read ID and rev of the ISA bridge */ 2289 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2290 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2291 aprint_normal("%s: VIA Technologies ", sc->sc_wdcdev.sc_dev.dv_xname); 2292 switch (PCI_PRODUCT(pcib_id)) { 2293 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2294 aprint_normal("VT82C586 (Apollo VP) "); 2295 if(PCI_REVISION(pcib_class) >= 0x02) { 2296 aprint_normal("ATA33 controller\n"); 2297 sc->sc_wdcdev.UDMA_cap = 2; 2298 } else { 2299 aprint_normal("controller\n"); 2300 sc->sc_wdcdev.UDMA_cap = 0; 2301 } 2302 break; 2303 case PCI_PRODUCT_VIATECH_VT82C596A: 2304 aprint_normal("VT82C596A (Apollo Pro) "); 2305 if (PCI_REVISION(pcib_class) >= 0x12) { 2306 aprint_normal("ATA66 controller\n"); 2307 sc->sc_wdcdev.UDMA_cap = 4; 2308 } else { 2309 aprint_normal("ATA33 controller\n"); 2310 sc->sc_wdcdev.UDMA_cap = 2; 2311 } 2312 break; 2313 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2314 aprint_normal("VT82C686A (Apollo KX133) "); 2315 if (PCI_REVISION(pcib_class) >= 0x40) { 2316 aprint_normal("ATA100 controller\n"); 2317 sc->sc_wdcdev.UDMA_cap = 5; 2318 } else { 2319 aprint_normal("ATA66 controller\n"); 2320 sc->sc_wdcdev.UDMA_cap = 4; 2321 } 2322 break; 2323 case PCI_PRODUCT_VIATECH_VT8231: 2324 aprint_normal("VT8231 ATA100 controller\n"); 2325 sc->sc_wdcdev.UDMA_cap = 5; 2326 break; 2327 case PCI_PRODUCT_VIATECH_VT8233: 2328 aprint_normal("VT8233 ATA100 controller\n"); 2329 sc->sc_wdcdev.UDMA_cap = 5; 2330 break; 2331 case PCI_PRODUCT_VIATECH_VT8233A: 2332 aprint_normal("VT8233A ATA133 controller\n"); 2333 sc->sc_wdcdev.UDMA_cap = 6; 2334 break; 2335 case PCI_PRODUCT_VIATECH_VT8235: 2336 aprint_normal("VT8235 ATA133 controller\n"); 2337 sc->sc_wdcdev.UDMA_cap = 6; 2338 break; 2339 case PCI_PRODUCT_VIATECH_VT8237_SATA: 2340 aprint_normal("VT8237 ATA133 controller\n"); 2341 sc->sc_wdcdev.UDMA_cap = 6; 2342 break; 2343 default: 2344 aprint_normal("unknown ATA controller\n"); 2345 sc->sc_wdcdev.UDMA_cap = 0; 2346 } 2347 2348 aprint_normal("%s: bus-master DMA support present", 2349 sc->sc_wdcdev.sc_dev.dv_xname); 2350 pciide_mapreg_dma(sc, pa); 2351 aprint_normal("\n"); 2352 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2353 WDC_CAPABILITY_MODE; 2354 if (sc->sc_dma_ok) { 2355 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2356 sc->sc_wdcdev.irqack = pciide_irqack; 2357 if (sc->sc_wdcdev.UDMA_cap > 0) 2358 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2359 } 2360 sc->sc_wdcdev.PIO_cap = 4; 2361 sc->sc_wdcdev.DMA_cap = 2; 2362 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2363 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2364 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2365 2366 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2367 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2368 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2369 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2370 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2371 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2372 DEBUG_PROBE); 2373 2374 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2375 cp = &sc->pciide_channels[channel]; 2376 if (pciide_chansetup(sc, channel, interface) == 0) 2377 continue; 2378 2379 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2380 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2381 aprint_normal("%s: %s channel ignored (disabled)\n", 2382 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2383 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 2384 continue; 2385 } 2386 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2387 pciide_pci_intr); 2388 } 2389 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2390 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2391 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2392 } 2393 2394 void 2395 apollo_setup_channel(chp) 2396 struct channel_softc *chp; 2397 { 2398 u_int32_t udmatim_reg, datatim_reg; 2399 u_int8_t idedma_ctl; 2400 int mode, drive; 2401 struct ata_drive_datas *drvp; 2402 struct pciide_channel *cp = (struct pciide_channel*)chp; 2403 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2404 2405 idedma_ctl = 0; 2406 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2407 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2408 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2409 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2410 2411 /* setup DMA if needed */ 2412 pciide_channel_dma_setup(cp); 2413 2414 for (drive = 0; drive < 2; drive++) { 2415 drvp = &chp->ch_drive[drive]; 2416 /* If no drive, skip */ 2417 if ((drvp->drive_flags & DRIVE) == 0) 2418 continue; 2419 /* add timing values, setup DMA if needed */ 2420 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2421 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2422 mode = drvp->PIO_mode; 2423 goto pio; 2424 } 2425 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2426 (drvp->drive_flags & DRIVE_UDMA)) { 2427 /* use Ultra/DMA */ 2428 drvp->drive_flags &= ~DRIVE_DMA; 2429 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2430 APO_UDMA_EN_MTH(chp->channel, drive); 2431 if (sc->sc_wdcdev.UDMA_cap == 6) { 2432 /* 8233a */ 2433 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2434 drive, apollo_udma133_tim[drvp->UDMA_mode]); 2435 } else if (sc->sc_wdcdev.UDMA_cap == 5) { 2436 /* 686b */ 2437 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2438 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2439 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2440 /* 596b or 686a */ 2441 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2442 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2443 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2444 } else { 2445 /* 596a or 586b */ 2446 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2447 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2448 } 2449 /* can use PIO timings, MW DMA unused */ 2450 mode = drvp->PIO_mode; 2451 } else { 2452 /* use Multiword DMA */ 2453 drvp->drive_flags &= ~DRIVE_UDMA; 2454 /* mode = min(pio, dma+2) */ 2455 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2456 mode = drvp->PIO_mode; 2457 else 2458 mode = drvp->DMA_mode + 2; 2459 } 2460 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2461 2462 pio: /* setup PIO mode */ 2463 if (mode <= 2) { 2464 drvp->DMA_mode = 0; 2465 drvp->PIO_mode = 0; 2466 mode = 0; 2467 } else { 2468 drvp->PIO_mode = mode; 2469 drvp->DMA_mode = mode - 2; 2470 } 2471 datatim_reg |= 2472 APO_DATATIM_PULSE(chp->channel, drive, 2473 apollo_pio_set[mode]) | 2474 APO_DATATIM_RECOV(chp->channel, drive, 2475 apollo_pio_rec[mode]); 2476 } 2477 if (idedma_ctl != 0) { 2478 /* Add software bits in status register */ 2479 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2480 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2481 idedma_ctl); 2482 } 2483 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2484 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2485 } 2486 2487 void 2488 apollo_sata_chip_map(sc, pa) 2489 struct pciide_softc *sc; 2490 struct pci_attach_args *pa; 2491 { 2492 struct pciide_channel *cp; 2493 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2494 int channel; 2495 bus_size_t cmdsize, ctlsize; 2496 2497 if (pciide_chipen(sc, pa) == 0) 2498 return; 2499 2500 if ( interface == 0 ) { 2501 WDCDEBUG_PRINT(("apollo_sata_chip_map interface == 0\n"), 2502 DEBUG_PROBE); 2503 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2504 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2505 } 2506 2507 aprint_normal("%s: bus-master DMA support present", 2508 sc->sc_wdcdev.sc_dev.dv_xname); 2509 pciide_mapreg_dma(sc, pa); 2510 aprint_normal("\n"); 2511 2512 if (sc->sc_dma_ok) { 2513 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2514 sc->sc_wdcdev.irqack = pciide_irqack; 2515 } 2516 sc->sc_wdcdev.PIO_cap = 4; 2517 sc->sc_wdcdev.DMA_cap = 2; 2518 sc->sc_wdcdev.UDMA_cap = 6; 2519 2520 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2521 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2522 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2523 WDC_CAPABILITY_MODE; 2524 sc->sc_wdcdev.set_modes = sata_setup_channel; 2525 2526 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2527 cp = &sc->pciide_channels[channel]; 2528 if (pciide_chansetup(sc, channel, interface) == 0) 2529 continue; 2530 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2531 pciide_pci_intr); 2532 } 2533 } 2534 2535 void 2536 cmd_channel_map(pa, sc, channel) 2537 struct pci_attach_args *pa; 2538 struct pciide_softc *sc; 2539 int channel; 2540 { 2541 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2542 bus_size_t cmdsize, ctlsize; 2543 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2544 int interface, one_channel; 2545 2546 /* 2547 * The 0648/0649 can be told to identify as a RAID controller. 2548 * In this case, we have to fake interface 2549 */ 2550 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2551 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2552 PCIIDE_INTERFACE_SETTABLE(1); 2553 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2554 CMD_CONF_DSA1) 2555 interface |= PCIIDE_INTERFACE_PCI(0) | 2556 PCIIDE_INTERFACE_PCI(1); 2557 } else { 2558 interface = PCI_INTERFACE(pa->pa_class); 2559 } 2560 2561 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2562 cp->name = PCIIDE_CHANNEL_NAME(channel); 2563 cp->wdc_channel.channel = channel; 2564 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2565 2566 /* 2567 * Older CMD64X doesn't have independant channels 2568 */ 2569 switch (sc->sc_pp->ide_product) { 2570 case PCI_PRODUCT_CMDTECH_649: 2571 one_channel = 0; 2572 break; 2573 default: 2574 one_channel = 1; 2575 break; 2576 } 2577 2578 if (channel > 0 && one_channel) { 2579 cp->wdc_channel.ch_queue = 2580 sc->pciide_channels[0].wdc_channel.ch_queue; 2581 } else { 2582 cp->wdc_channel.ch_queue = 2583 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2584 } 2585 if (cp->wdc_channel.ch_queue == NULL) { 2586 aprint_error("%s %s channel: " 2587 "can't allocate memory for command queue", 2588 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2589 return; 2590 } 2591 2592 aprint_normal("%s: %s channel %s to %s mode\n", 2593 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2594 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2595 "configured" : "wired", 2596 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2597 "native-PCI" : "compatibility"); 2598 2599 /* 2600 * with a CMD PCI64x, if we get here, the first channel is enabled: 2601 * there's no way to disable the first channel without disabling 2602 * the whole device 2603 */ 2604 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2605 aprint_normal("%s: %s channel ignored (disabled)\n", 2606 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2607 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 2608 return; 2609 } 2610 2611 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2612 } 2613 2614 int 2615 cmd_pci_intr(arg) 2616 void *arg; 2617 { 2618 struct pciide_softc *sc = arg; 2619 struct pciide_channel *cp; 2620 struct channel_softc *wdc_cp; 2621 int i, rv, crv; 2622 u_int32_t priirq, secirq; 2623 2624 rv = 0; 2625 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2626 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2627 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2628 cp = &sc->pciide_channels[i]; 2629 wdc_cp = &cp->wdc_channel; 2630 /* If a compat channel skip. */ 2631 if (cp->compat) 2632 continue; 2633 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2634 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2635 crv = wdcintr(wdc_cp); 2636 if (crv == 0) 2637 printf("%s:%d: bogus intr\n", 2638 sc->sc_wdcdev.sc_dev.dv_xname, i); 2639 else 2640 rv = 1; 2641 } 2642 } 2643 return rv; 2644 } 2645 2646 void 2647 cmd_chip_map(sc, pa) 2648 struct pciide_softc *sc; 2649 struct pci_attach_args *pa; 2650 { 2651 int channel; 2652 2653 /* 2654 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2655 * and base adresses registers can be disabled at 2656 * hardware level. In this case, the device is wired 2657 * in compat mode and its first channel is always enabled, 2658 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2659 * In fact, it seems that the first channel of the CMD PCI0640 2660 * can't be disabled. 2661 */ 2662 2663 #ifdef PCIIDE_CMD064x_DISABLE 2664 if (pciide_chipen(sc, pa) == 0) 2665 return; 2666 #endif 2667 2668 aprint_normal("%s: hardware does not support DMA\n", 2669 sc->sc_wdcdev.sc_dev.dv_xname); 2670 sc->sc_dma_ok = 0; 2671 2672 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2673 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2674 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2675 2676 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2677 cmd_channel_map(pa, sc, channel); 2678 } 2679 } 2680 2681 void 2682 cmd0643_9_chip_map(sc, pa) 2683 struct pciide_softc *sc; 2684 struct pci_attach_args *pa; 2685 { 2686 struct pciide_channel *cp; 2687 int channel; 2688 pcireg_t rev = PCI_REVISION(pa->pa_class); 2689 2690 /* 2691 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2692 * and base adresses registers can be disabled at 2693 * hardware level. In this case, the device is wired 2694 * in compat mode and its first channel is always enabled, 2695 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2696 * In fact, it seems that the first channel of the CMD PCI0640 2697 * can't be disabled. 2698 */ 2699 2700 #ifdef PCIIDE_CMD064x_DISABLE 2701 if (pciide_chipen(sc, pa) == 0) 2702 return; 2703 #endif 2704 2705 aprint_normal("%s: bus-master DMA support present", 2706 sc->sc_wdcdev.sc_dev.dv_xname); 2707 pciide_mapreg_dma(sc, pa); 2708 aprint_normal("\n"); 2709 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2710 WDC_CAPABILITY_MODE; 2711 if (sc->sc_dma_ok) { 2712 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2713 switch (sc->sc_pp->ide_product) { 2714 case PCI_PRODUCT_CMDTECH_649: 2715 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2716 sc->sc_wdcdev.UDMA_cap = 5; 2717 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2718 break; 2719 case PCI_PRODUCT_CMDTECH_648: 2720 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2721 sc->sc_wdcdev.UDMA_cap = 4; 2722 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2723 break; 2724 case PCI_PRODUCT_CMDTECH_646: 2725 if (rev >= CMD0646U2_REV) { 2726 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2727 sc->sc_wdcdev.UDMA_cap = 2; 2728 } else if (rev >= CMD0646U_REV) { 2729 /* 2730 * Linux's driver claims that the 646U is broken 2731 * with UDMA. Only enable it if we know what we're 2732 * doing 2733 */ 2734 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2735 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2736 sc->sc_wdcdev.UDMA_cap = 2; 2737 #endif 2738 /* explicitly disable UDMA */ 2739 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2740 CMD_UDMATIM(0), 0); 2741 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2742 CMD_UDMATIM(1), 0); 2743 } 2744 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2745 break; 2746 default: 2747 sc->sc_wdcdev.irqack = pciide_irqack; 2748 } 2749 } 2750 2751 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2752 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2753 sc->sc_wdcdev.PIO_cap = 4; 2754 sc->sc_wdcdev.DMA_cap = 2; 2755 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2756 2757 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2758 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2759 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2760 DEBUG_PROBE); 2761 2762 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2763 cp = &sc->pciide_channels[channel]; 2764 cmd_channel_map(pa, sc, channel); 2765 } 2766 /* 2767 * note - this also makes sure we clear the irq disable and reset 2768 * bits 2769 */ 2770 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2771 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2772 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2773 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2774 DEBUG_PROBE); 2775 } 2776 2777 void 2778 cmd0643_9_setup_channel(chp) 2779 struct channel_softc *chp; 2780 { 2781 struct ata_drive_datas *drvp; 2782 u_int8_t tim; 2783 u_int32_t idedma_ctl, udma_reg; 2784 int drive; 2785 struct pciide_channel *cp = (struct pciide_channel*)chp; 2786 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2787 2788 idedma_ctl = 0; 2789 /* setup DMA if needed */ 2790 pciide_channel_dma_setup(cp); 2791 2792 for (drive = 0; drive < 2; drive++) { 2793 drvp = &chp->ch_drive[drive]; 2794 /* If no drive, skip */ 2795 if ((drvp->drive_flags & DRIVE) == 0) 2796 continue; 2797 /* add timing values, setup DMA if needed */ 2798 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2799 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2800 if (drvp->drive_flags & DRIVE_UDMA) { 2801 /* UltraDMA on a 646U2, 0648 or 0649 */ 2802 drvp->drive_flags &= ~DRIVE_DMA; 2803 udma_reg = pciide_pci_read(sc->sc_pc, 2804 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2805 if (drvp->UDMA_mode > 2 && 2806 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2807 CMD_BICSR) & 2808 CMD_BICSR_80(chp->channel)) == 0) 2809 drvp->UDMA_mode = 2; 2810 if (drvp->UDMA_mode > 2) 2811 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2812 else if (sc->sc_wdcdev.UDMA_cap > 2) 2813 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2814 udma_reg |= CMD_UDMATIM_UDMA(drive); 2815 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2816 CMD_UDMATIM_TIM_OFF(drive)); 2817 udma_reg |= 2818 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2819 CMD_UDMATIM_TIM_OFF(drive)); 2820 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2821 CMD_UDMATIM(chp->channel), udma_reg); 2822 } else { 2823 /* 2824 * use Multiword DMA. 2825 * Timings will be used for both PIO and DMA, 2826 * so adjust DMA mode if needed 2827 * if we have a 0646U2/8/9, turn off UDMA 2828 */ 2829 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2830 udma_reg = pciide_pci_read(sc->sc_pc, 2831 sc->sc_tag, 2832 CMD_UDMATIM(chp->channel)); 2833 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2834 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2835 CMD_UDMATIM(chp->channel), 2836 udma_reg); 2837 } 2838 if (drvp->PIO_mode >= 3 && 2839 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2840 drvp->DMA_mode = drvp->PIO_mode - 2; 2841 } 2842 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2843 } 2844 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2845 } 2846 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2847 CMD_DATA_TIM(chp->channel, drive), tim); 2848 } 2849 if (idedma_ctl != 0) { 2850 /* Add software bits in status register */ 2851 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2852 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2853 idedma_ctl); 2854 } 2855 } 2856 2857 void 2858 cmd646_9_irqack(chp) 2859 struct channel_softc *chp; 2860 { 2861 u_int32_t priirq, secirq; 2862 struct pciide_channel *cp = (struct pciide_channel*)chp; 2863 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2864 2865 if (chp->channel == 0) { 2866 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2867 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2868 } else { 2869 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2870 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2871 } 2872 pciide_irqack(chp); 2873 } 2874 2875 void 2876 cmd680_chip_map(sc, pa) 2877 struct pciide_softc *sc; 2878 struct pci_attach_args *pa; 2879 { 2880 struct pciide_channel *cp; 2881 int channel; 2882 2883 if (pciide_chipen(sc, pa) == 0) 2884 return; 2885 2886 aprint_normal("%s: bus-master DMA support present", 2887 sc->sc_wdcdev.sc_dev.dv_xname); 2888 pciide_mapreg_dma(sc, pa); 2889 aprint_normal("\n"); 2890 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2891 WDC_CAPABILITY_MODE; 2892 if (sc->sc_dma_ok) { 2893 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2894 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2895 sc->sc_wdcdev.UDMA_cap = 6; 2896 sc->sc_wdcdev.irqack = pciide_irqack; 2897 } 2898 2899 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2900 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2901 sc->sc_wdcdev.PIO_cap = 4; 2902 sc->sc_wdcdev.DMA_cap = 2; 2903 sc->sc_wdcdev.set_modes = cmd680_setup_channel; 2904 2905 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x80, 0x00); 2906 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x84, 0x00); 2907 pciide_pci_write(sc->sc_pc, sc->sc_tag, 0x8a, 2908 pciide_pci_read(sc->sc_pc, sc->sc_tag, 0x8a) | 0x01); 2909 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2910 cp = &sc->pciide_channels[channel]; 2911 cmd680_channel_map(pa, sc, channel); 2912 } 2913 } 2914 2915 void 2916 cmd680_channel_map(pa, sc, channel) 2917 struct pci_attach_args *pa; 2918 struct pciide_softc *sc; 2919 int channel; 2920 { 2921 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2922 bus_size_t cmdsize, ctlsize; 2923 int interface, i, reg; 2924 static const u_int8_t init_val[] = 2925 { 0x8a, 0x32, 0x8a, 0x32, 0x8a, 0x32, 2926 0x92, 0x43, 0x92, 0x43, 0x09, 0x40, 0x09, 0x40 }; 2927 2928 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2929 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2930 PCIIDE_INTERFACE_SETTABLE(1); 2931 interface |= PCIIDE_INTERFACE_PCI(0) | 2932 PCIIDE_INTERFACE_PCI(1); 2933 } else { 2934 interface = PCI_INTERFACE(pa->pa_class); 2935 } 2936 2937 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2938 cp->name = PCIIDE_CHANNEL_NAME(channel); 2939 cp->wdc_channel.channel = channel; 2940 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2941 2942 cp->wdc_channel.ch_queue = 2943 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2944 if (cp->wdc_channel.ch_queue == NULL) { 2945 aprint_error("%s %s channel: " 2946 "can't allocate memory for command queue", 2947 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2948 return; 2949 } 2950 2951 /* XXX */ 2952 reg = 0xa2 + channel * 16; 2953 for (i = 0; i < sizeof(init_val); i++) 2954 pciide_pci_write(sc->sc_pc, sc->sc_tag, reg + i, init_val[i]); 2955 2956 aprint_normal("%s: %s channel %s to %s mode\n", 2957 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2958 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2959 "configured" : "wired", 2960 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2961 "native-PCI" : "compatibility"); 2962 2963 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, pciide_pci_intr); 2964 } 2965 2966 void 2967 cmd680_setup_channel(chp) 2968 struct channel_softc *chp; 2969 { 2970 struct ata_drive_datas *drvp; 2971 u_int8_t mode, off, scsc; 2972 u_int16_t val; 2973 u_int32_t idedma_ctl; 2974 int drive; 2975 struct pciide_channel *cp = (struct pciide_channel*)chp; 2976 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2977 pci_chipset_tag_t pc = sc->sc_pc; 2978 pcitag_t pa = sc->sc_tag; 2979 static const u_int8_t udma2_tbl[] = 2980 { 0x0f, 0x0b, 0x07, 0x06, 0x03, 0x02, 0x01 }; 2981 static const u_int8_t udma_tbl[] = 2982 { 0x0c, 0x07, 0x05, 0x04, 0x02, 0x01, 0x00 }; 2983 static const u_int16_t dma_tbl[] = 2984 { 0x2208, 0x10c2, 0x10c1 }; 2985 static const u_int16_t pio_tbl[] = 2986 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 }; 2987 2988 idedma_ctl = 0; 2989 pciide_channel_dma_setup(cp); 2990 mode = pciide_pci_read(pc, pa, 0x80 + chp->channel * 4); 2991 2992 for (drive = 0; drive < 2; drive++) { 2993 drvp = &chp->ch_drive[drive]; 2994 /* If no drive, skip */ 2995 if ((drvp->drive_flags & DRIVE) == 0) 2996 continue; 2997 mode &= ~(0x03 << (drive * 4)); 2998 if (drvp->drive_flags & DRIVE_UDMA) { 2999 drvp->drive_flags &= ~DRIVE_DMA; 3000 off = 0xa0 + chp->channel * 16; 3001 if (drvp->UDMA_mode > 2 && 3002 (pciide_pci_read(pc, pa, off) & 0x01) == 0) 3003 drvp->UDMA_mode = 2; 3004 scsc = pciide_pci_read(pc, pa, 0x8a); 3005 if (drvp->UDMA_mode == 6 && (scsc & 0x30) == 0) { 3006 pciide_pci_write(pc, pa, 0x8a, scsc | 0x01); 3007 scsc = pciide_pci_read(pc, pa, 0x8a); 3008 if ((scsc & 0x30) == 0) 3009 drvp->UDMA_mode = 5; 3010 } 3011 mode |= 0x03 << (drive * 4); 3012 off = 0xac + chp->channel * 16 + drive * 2; 3013 val = pciide_pci_read(pc, pa, off) & ~0x3f; 3014 if (scsc & 0x30) 3015 val |= udma2_tbl[drvp->UDMA_mode]; 3016 else 3017 val |= udma_tbl[drvp->UDMA_mode]; 3018 pciide_pci_write(pc, pa, off, val); 3019 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3020 } else if (drvp->drive_flags & DRIVE_DMA) { 3021 mode |= 0x02 << (drive * 4); 3022 off = 0xa8 + chp->channel * 16 + drive * 2; 3023 val = dma_tbl[drvp->DMA_mode]; 3024 pciide_pci_write(pc, pa, off, val & 0xff); 3025 pciide_pci_write(pc, pa, off, val >> 8); 3026 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3027 } else { 3028 mode |= 0x01 << (drive * 4); 3029 off = 0xa4 + chp->channel * 16 + drive * 2; 3030 val = pio_tbl[drvp->PIO_mode]; 3031 pciide_pci_write(pc, pa, off, val & 0xff); 3032 pciide_pci_write(pc, pa, off, val >> 8); 3033 } 3034 } 3035 3036 pciide_pci_write(pc, pa, 0x80 + chp->channel * 4, mode); 3037 if (idedma_ctl != 0) { 3038 /* Add software bits in status register */ 3039 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3040 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3041 idedma_ctl); 3042 } 3043 } 3044 3045 void 3046 cmd3112_chip_map(sc, pa) 3047 struct pciide_softc *sc; 3048 struct pci_attach_args *pa; 3049 { 3050 struct pciide_channel *cp; 3051 bus_size_t cmdsize, ctlsize; 3052 pcireg_t interface; 3053 int channel; 3054 3055 if (pciide_chipen(sc, pa) == 0) 3056 return; 3057 3058 aprint_normal("%s: bus-master DMA support present", 3059 sc->sc_wdcdev.sc_dev.dv_xname); 3060 pciide_mapreg_dma(sc, pa); 3061 aprint_normal("\n"); 3062 3063 /* 3064 * Rev. <= 0x01 of the 3112 have a bug that can cause data 3065 * corruption if DMA transfers cross an 8K boundary. This is 3066 * apparently hard to tickle, but we'll go ahead and play it 3067 * safe. 3068 */ 3069 if (PCI_REVISION(pa->pa_class) <= 0x01) { 3070 sc->sc_dma_maxsegsz = 8192; 3071 sc->sc_dma_boundary = 8192; 3072 } 3073 3074 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3075 WDC_CAPABILITY_MODE; 3076 sc->sc_wdcdev.PIO_cap = 4; 3077 if (sc->sc_dma_ok) { 3078 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3079 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3080 sc->sc_wdcdev.irqack = pciide_irqack; 3081 sc->sc_wdcdev.DMA_cap = 2; 3082 sc->sc_wdcdev.UDMA_cap = 6; 3083 } 3084 sc->sc_wdcdev.set_modes = cmd3112_setup_channel; 3085 3086 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3087 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3088 3089 /* 3090 * The 3112 can be told to identify as a RAID controller. 3091 * In this case, we have to fake interface 3092 */ 3093 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3094 interface = PCI_INTERFACE(pa->pa_class); 3095 } else { 3096 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3097 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3098 } 3099 3100 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3101 cp = &sc->pciide_channels[channel]; 3102 if (pciide_chansetup(sc, channel, interface) == 0) 3103 continue; 3104 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3105 pciide_pci_intr); 3106 } 3107 } 3108 3109 void 3110 cmd3112_setup_channel(chp) 3111 struct channel_softc *chp; 3112 { 3113 struct ata_drive_datas *drvp; 3114 int drive; 3115 u_int32_t idedma_ctl, dtm; 3116 struct pciide_channel *cp = (struct pciide_channel*)chp; 3117 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 3118 3119 /* setup DMA if needed */ 3120 pciide_channel_dma_setup(cp); 3121 3122 idedma_ctl = 0; 3123 dtm = 0; 3124 3125 for (drive = 0; drive < 2; drive++) { 3126 drvp = &chp->ch_drive[drive]; 3127 /* If no drive, skip */ 3128 if ((drvp->drive_flags & DRIVE) == 0) 3129 continue; 3130 if (drvp->drive_flags & DRIVE_UDMA) { 3131 /* use Ultra/DMA */ 3132 drvp->drive_flags &= ~DRIVE_DMA; 3133 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3134 dtm |= DTM_IDEx_DMA; 3135 } else if (drvp->drive_flags & DRIVE_DMA) { 3136 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3137 dtm |= DTM_IDEx_DMA; 3138 } else { 3139 dtm |= DTM_IDEx_PIO; 3140 } 3141 } 3142 3143 /* 3144 * Nothing to do to setup modes; it is meaningless in S-ATA 3145 * (but many S-ATA drives still want to get the SET_FEATURE 3146 * command). 3147 */ 3148 if (idedma_ctl != 0) { 3149 /* Add software bits in status register */ 3150 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3151 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3152 idedma_ctl); 3153 } 3154 pci_conf_write(sc->sc_pc, sc->sc_tag, 3155 chp->channel == 0 ? SII3112_DTM_IDE0 : SII3112_DTM_IDE1, dtm); 3156 } 3157 3158 void 3159 cy693_chip_map(sc, pa) 3160 struct pciide_softc *sc; 3161 struct pci_attach_args *pa; 3162 { 3163 struct pciide_channel *cp; 3164 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3165 bus_size_t cmdsize, ctlsize; 3166 3167 if (pciide_chipen(sc, pa) == 0) 3168 return; 3169 3170 /* 3171 * this chip has 2 PCI IDE functions, one for primary and one for 3172 * secondary. So we need to call pciide_mapregs_compat() with 3173 * the real channel 3174 */ 3175 if (pa->pa_function == 1) { 3176 sc->sc_cy_compatchan = 0; 3177 } else if (pa->pa_function == 2) { 3178 sc->sc_cy_compatchan = 1; 3179 } else { 3180 aprint_error("%s: unexpected PCI function %d\n", 3181 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3182 return; 3183 } 3184 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 3185 aprint_normal("%s: bus-master DMA support present", 3186 sc->sc_wdcdev.sc_dev.dv_xname); 3187 pciide_mapreg_dma(sc, pa); 3188 } else { 3189 aprint_normal("%s: hardware does not support DMA", 3190 sc->sc_wdcdev.sc_dev.dv_xname); 3191 sc->sc_dma_ok = 0; 3192 } 3193 aprint_normal("\n"); 3194 3195 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 3196 if (sc->sc_cy_handle == NULL) { 3197 aprint_error("%s: unable to map hyperCache control registers\n", 3198 sc->sc_wdcdev.sc_dev.dv_xname); 3199 sc->sc_dma_ok = 0; 3200 } 3201 3202 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3203 WDC_CAPABILITY_MODE; 3204 if (sc->sc_dma_ok) { 3205 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3206 sc->sc_wdcdev.irqack = pciide_irqack; 3207 } 3208 sc->sc_wdcdev.PIO_cap = 4; 3209 sc->sc_wdcdev.DMA_cap = 2; 3210 sc->sc_wdcdev.set_modes = cy693_setup_channel; 3211 3212 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3213 sc->sc_wdcdev.nchannels = 1; 3214 3215 /* Only one channel for this chip; if we are here it's enabled */ 3216 cp = &sc->pciide_channels[0]; 3217 sc->wdc_chanarray[0] = &cp->wdc_channel; 3218 cp->name = PCIIDE_CHANNEL_NAME(0); 3219 cp->wdc_channel.channel = 0; 3220 cp->wdc_channel.wdc = &sc->sc_wdcdev; 3221 cp->wdc_channel.ch_queue = 3222 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 3223 if (cp->wdc_channel.ch_queue == NULL) { 3224 aprint_error("%s primary channel: " 3225 "can't allocate memory for command queue", 3226 sc->sc_wdcdev.sc_dev.dv_xname); 3227 return; 3228 } 3229 aprint_normal("%s: primary channel %s to ", 3230 sc->sc_wdcdev.sc_dev.dv_xname, 3231 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 3232 "configured" : "wired"); 3233 if (interface & PCIIDE_INTERFACE_PCI(0)) { 3234 aprint_normal("native-PCI mode\n"); 3235 pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 3236 pciide_pci_intr); 3237 } else { 3238 aprint_normal("compatibility mode\n"); 3239 pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, &cmdsize, 3240 &ctlsize); 3241 } 3242 } 3243 3244 void 3245 cy693_setup_channel(chp) 3246 struct channel_softc *chp; 3247 { 3248 struct ata_drive_datas *drvp; 3249 int drive; 3250 u_int32_t cy_cmd_ctrl; 3251 u_int32_t idedma_ctl; 3252 struct pciide_channel *cp = (struct pciide_channel*)chp; 3253 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3254 int dma_mode = -1; 3255 3256 cy_cmd_ctrl = idedma_ctl = 0; 3257 3258 /* setup DMA if needed */ 3259 pciide_channel_dma_setup(cp); 3260 3261 for (drive = 0; drive < 2; drive++) { 3262 drvp = &chp->ch_drive[drive]; 3263 /* If no drive, skip */ 3264 if ((drvp->drive_flags & DRIVE) == 0) 3265 continue; 3266 /* add timing values, setup DMA if needed */ 3267 if (drvp->drive_flags & DRIVE_DMA) { 3268 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3269 /* use Multiword DMA */ 3270 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 3271 dma_mode = drvp->DMA_mode; 3272 } 3273 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3274 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 3275 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3276 CY_CMD_CTRL_IOW_REC_OFF(drive)); 3277 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 3278 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 3279 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 3280 CY_CMD_CTRL_IOR_REC_OFF(drive)); 3281 } 3282 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 3283 chp->ch_drive[0].DMA_mode = dma_mode; 3284 chp->ch_drive[1].DMA_mode = dma_mode; 3285 3286 if (dma_mode == -1) 3287 dma_mode = 0; 3288 3289 if (sc->sc_cy_handle != NULL) { 3290 /* Note: `multiple' is implied. */ 3291 cy82c693_write(sc->sc_cy_handle, 3292 (sc->sc_cy_compatchan == 0) ? 3293 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 3294 } 3295 3296 if (idedma_ctl != 0) { 3297 /* Add software bits in status register */ 3298 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3299 IDEDMA_CTL, idedma_ctl); 3300 } 3301 } 3302 3303 static struct sis_hostbr_type { 3304 u_int16_t id; 3305 u_int8_t rev; 3306 u_int8_t udma_mode; 3307 char *name; 3308 u_int8_t type; 3309 #define SIS_TYPE_NOUDMA 0 3310 #define SIS_TYPE_66 1 3311 #define SIS_TYPE_100OLD 2 3312 #define SIS_TYPE_100NEW 3 3313 #define SIS_TYPE_133OLD 4 3314 #define SIS_TYPE_133NEW 5 3315 #define SIS_TYPE_SOUTH 6 3316 } sis_hostbr_type[] = { 3317 /* Most infos here are from sos (at) freebsd.org */ 3318 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 3319 #if 0 3320 /* 3321 * controllers associated to a rev 0x2 530 Host to PCI Bridge 3322 * have problems with UDMA (info provided by Christos) 3323 */ 3324 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 3325 #endif 3326 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 3327 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 3328 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 3329 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 3330 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 3331 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 3332 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 3333 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 3334 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 3335 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 3336 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 3337 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 3338 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 3339 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 3340 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 3341 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 3342 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 3343 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 3344 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 3345 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 3346 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 3347 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 3348 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 3349 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 3350 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 3351 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 3352 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 3353 /* 3354 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 3355 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 3356 */ 3357 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 3358 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 3359 }; 3360 3361 static struct sis_hostbr_type *sis_hostbr_type_match; 3362 3363 static int 3364 sis_hostbr_match(pa) 3365 struct pci_attach_args *pa; 3366 { 3367 int i; 3368 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 3369 return 0; 3370 sis_hostbr_type_match = NULL; 3371 for (i = 0; 3372 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 3373 i++) { 3374 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 3375 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 3376 sis_hostbr_type_match = &sis_hostbr_type[i]; 3377 } 3378 return (sis_hostbr_type_match != NULL); 3379 } 3380 3381 static int sis_south_match(pa) 3382 struct pci_attach_args *pa; 3383 { 3384 return(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 3385 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 3386 PCI_REVISION(pa->pa_class) >= 0x10); 3387 } 3388 3389 void 3390 sis_chip_map(sc, pa) 3391 struct pciide_softc *sc; 3392 struct pci_attach_args *pa; 3393 { 3394 struct pciide_channel *cp; 3395 int channel; 3396 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 3397 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 3398 pcireg_t rev = PCI_REVISION(pa->pa_class); 3399 bus_size_t cmdsize, ctlsize; 3400 3401 if (pciide_chipen(sc, pa) == 0) 3402 return; 3403 3404 aprint_normal("%s: Silicon Integrated System ", 3405 sc->sc_wdcdev.sc_dev.dv_xname); 3406 pci_find_device(NULL, sis_hostbr_match); 3407 if (sis_hostbr_type_match) { 3408 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 3409 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 3410 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3411 SIS_REG_57) & 0x7f); 3412 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 3413 PCI_ID_REG)) == SIS_PRODUCT_5518) { 3414 aprint_normal("96X UDMA%d", 3415 sis_hostbr_type_match->udma_mode); 3416 sc->sis_type = SIS_TYPE_133NEW; 3417 sc->sc_wdcdev.UDMA_cap = 3418 sis_hostbr_type_match->udma_mode; 3419 } else { 3420 if (pci_find_device(NULL, sis_south_match)) { 3421 sc->sis_type = SIS_TYPE_133OLD; 3422 sc->sc_wdcdev.UDMA_cap = 3423 sis_hostbr_type_match->udma_mode; 3424 } else { 3425 sc->sis_type = SIS_TYPE_100NEW; 3426 sc->sc_wdcdev.UDMA_cap = 3427 sis_hostbr_type_match->udma_mode; 3428 } 3429 } 3430 } else { 3431 sc->sis_type = sis_hostbr_type_match->type; 3432 sc->sc_wdcdev.UDMA_cap = 3433 sis_hostbr_type_match->udma_mode; 3434 } 3435 aprint_normal(sis_hostbr_type_match->name); 3436 } else { 3437 aprint_normal("5597/5598"); 3438 if (rev >= 0xd0) { 3439 sc->sc_wdcdev.UDMA_cap = 2; 3440 sc->sis_type = SIS_TYPE_66; 3441 } else { 3442 sc->sc_wdcdev.UDMA_cap = 0; 3443 sc->sis_type = SIS_TYPE_NOUDMA; 3444 } 3445 } 3446 aprint_normal(" IDE controller (rev. 0x%02x)\n", 3447 PCI_REVISION(pa->pa_class)); 3448 aprint_normal("%s: bus-master DMA support present", 3449 sc->sc_wdcdev.sc_dev.dv_xname); 3450 pciide_mapreg_dma(sc, pa); 3451 aprint_normal("\n"); 3452 3453 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3454 WDC_CAPABILITY_MODE; 3455 if (sc->sc_dma_ok) { 3456 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3457 sc->sc_wdcdev.irqack = pciide_irqack; 3458 if (sc->sis_type >= SIS_TYPE_66) 3459 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3460 } 3461 3462 sc->sc_wdcdev.PIO_cap = 4; 3463 sc->sc_wdcdev.DMA_cap = 2; 3464 3465 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3466 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3467 switch(sc->sis_type) { 3468 case SIS_TYPE_NOUDMA: 3469 case SIS_TYPE_66: 3470 case SIS_TYPE_100OLD: 3471 sc->sc_wdcdev.set_modes = sis_setup_channel; 3472 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 3473 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 3474 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 3475 break; 3476 case SIS_TYPE_100NEW: 3477 case SIS_TYPE_133OLD: 3478 sc->sc_wdcdev.set_modes = sis_setup_channel; 3479 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 3480 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 3481 break; 3482 case SIS_TYPE_133NEW: 3483 sc->sc_wdcdev.set_modes = sis96x_setup_channel; 3484 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 3485 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 3486 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 3487 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 3488 break; 3489 } 3490 3491 3492 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3493 cp = &sc->pciide_channels[channel]; 3494 if (pciide_chansetup(sc, channel, interface) == 0) 3495 continue; 3496 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 3497 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 3498 aprint_normal("%s: %s channel ignored (disabled)\n", 3499 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3500 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 3501 continue; 3502 } 3503 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3504 pciide_pci_intr); 3505 } 3506 } 3507 3508 void 3509 sis96x_setup_channel(chp) 3510 struct channel_softc *chp; 3511 { 3512 struct ata_drive_datas *drvp; 3513 int drive; 3514 u_int32_t sis_tim; 3515 u_int32_t idedma_ctl; 3516 int regtim; 3517 struct pciide_channel *cp = (struct pciide_channel*)chp; 3518 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3519 3520 sis_tim = 0; 3521 idedma_ctl = 0; 3522 /* setup DMA if needed */ 3523 pciide_channel_dma_setup(cp); 3524 3525 for (drive = 0; drive < 2; drive++) { 3526 regtim = SIS_TIM133( 3527 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 3528 chp->channel, drive); 3529 drvp = &chp->ch_drive[drive]; 3530 /* If no drive, skip */ 3531 if ((drvp->drive_flags & DRIVE) == 0) 3532 continue; 3533 /* add timing values, setup DMA if needed */ 3534 if (drvp->drive_flags & DRIVE_UDMA) { 3535 /* use Ultra/DMA */ 3536 drvp->drive_flags &= ~DRIVE_DMA; 3537 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3538 SIS96x_REG_CBL(chp->channel)) & SIS96x_REG_CBL_33) { 3539 if (drvp->UDMA_mode > 2) 3540 drvp->UDMA_mode = 2; 3541 } 3542 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 3543 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3544 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3545 } else if (drvp->drive_flags & DRIVE_DMA) { 3546 /* 3547 * use Multiword DMA 3548 * Timings will be used for both PIO and DMA, 3549 * so adjust DMA mode if needed 3550 */ 3551 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3552 drvp->PIO_mode = drvp->DMA_mode + 2; 3553 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3554 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3555 drvp->PIO_mode - 2 : 0; 3556 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 3557 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3558 } else { 3559 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 3560 } 3561 WDCDEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 3562 "channel %d drive %d: 0x%x (reg 0x%x)\n", 3563 chp->channel, drive, sis_tim, regtim), DEBUG_PROBE); 3564 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 3565 } 3566 if (idedma_ctl != 0) { 3567 /* Add software bits in status register */ 3568 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3569 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3570 idedma_ctl); 3571 } 3572 } 3573 3574 void 3575 sis_setup_channel(chp) 3576 struct channel_softc *chp; 3577 { 3578 struct ata_drive_datas *drvp; 3579 int drive; 3580 u_int32_t sis_tim; 3581 u_int32_t idedma_ctl; 3582 struct pciide_channel *cp = (struct pciide_channel*)chp; 3583 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3584 3585 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 3586 "channel %d 0x%x\n", chp->channel, 3587 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 3588 DEBUG_PROBE); 3589 sis_tim = 0; 3590 idedma_ctl = 0; 3591 /* setup DMA if needed */ 3592 pciide_channel_dma_setup(cp); 3593 3594 for (drive = 0; drive < 2; drive++) { 3595 drvp = &chp->ch_drive[drive]; 3596 /* If no drive, skip */ 3597 if ((drvp->drive_flags & DRIVE) == 0) 3598 continue; 3599 /* add timing values, setup DMA if needed */ 3600 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3601 (drvp->drive_flags & DRIVE_UDMA) == 0) 3602 goto pio; 3603 3604 if (drvp->drive_flags & DRIVE_UDMA) { 3605 /* use Ultra/DMA */ 3606 drvp->drive_flags &= ~DRIVE_DMA; 3607 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 3608 SIS_REG_CBL) & SIS_REG_CBL_33(chp->channel)) { 3609 if (drvp->UDMA_mode > 2) 3610 drvp->UDMA_mode = 2; 3611 } 3612 switch (sc->sis_type) { 3613 case SIS_TYPE_66: 3614 case SIS_TYPE_100OLD: 3615 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 3616 SIS_TIM66_UDMA_TIME_OFF(drive); 3617 break; 3618 case SIS_TYPE_100NEW: 3619 sis_tim |= 3620 sis_udma100new_tim[drvp->UDMA_mode] << 3621 SIS_TIM100_UDMA_TIME_OFF(drive); 3622 case SIS_TYPE_133OLD: 3623 sis_tim |= 3624 sis_udma133old_tim[drvp->UDMA_mode] << 3625 SIS_TIM100_UDMA_TIME_OFF(drive); 3626 break; 3627 default: 3628 aprint_error("unknown SiS IDE type %d\n", 3629 sc->sis_type); 3630 } 3631 } else { 3632 /* 3633 * use Multiword DMA 3634 * Timings will be used for both PIO and DMA, 3635 * so adjust DMA mode if needed 3636 */ 3637 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3638 drvp->PIO_mode = drvp->DMA_mode + 2; 3639 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3640 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3641 drvp->PIO_mode - 2 : 0; 3642 if (drvp->DMA_mode == 0) 3643 drvp->PIO_mode = 0; 3644 } 3645 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3646 pio: switch (sc->sis_type) { 3647 case SIS_TYPE_NOUDMA: 3648 case SIS_TYPE_66: 3649 case SIS_TYPE_100OLD: 3650 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3651 SIS_TIM66_ACT_OFF(drive); 3652 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3653 SIS_TIM66_REC_OFF(drive); 3654 break; 3655 case SIS_TYPE_100NEW: 3656 case SIS_TYPE_133OLD: 3657 sis_tim |= sis_pio_act[drvp->PIO_mode] << 3658 SIS_TIM100_ACT_OFF(drive); 3659 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 3660 SIS_TIM100_REC_OFF(drive); 3661 break; 3662 default: 3663 aprint_error("unknown SiS IDE type %d\n", 3664 sc->sis_type); 3665 } 3666 } 3667 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 3668 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 3669 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 3670 if (idedma_ctl != 0) { 3671 /* Add software bits in status register */ 3672 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3673 IDEDMA_CTL+ (IDEDMA_SCH_OFFSET * chp->channel), 3674 idedma_ctl); 3675 } 3676 } 3677 3678 void 3679 acer_chip_map(sc, pa) 3680 struct pciide_softc *sc; 3681 struct pci_attach_args *pa; 3682 { 3683 struct pciide_channel *cp; 3684 int channel; 3685 pcireg_t cr, interface; 3686 bus_size_t cmdsize, ctlsize; 3687 pcireg_t rev = PCI_REVISION(pa->pa_class); 3688 3689 if (pciide_chipen(sc, pa) == 0) 3690 return; 3691 3692 aprint_normal("%s: bus-master DMA support present", 3693 sc->sc_wdcdev.sc_dev.dv_xname); 3694 pciide_mapreg_dma(sc, pa); 3695 aprint_normal("\n"); 3696 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3697 WDC_CAPABILITY_MODE; 3698 if (sc->sc_dma_ok) { 3699 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 3700 if (rev >= 0x20) { 3701 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 3702 if (rev >= 0xC4) 3703 sc->sc_wdcdev.UDMA_cap = 5; 3704 else if (rev >= 0xC2) 3705 sc->sc_wdcdev.UDMA_cap = 4; 3706 else 3707 sc->sc_wdcdev.UDMA_cap = 2; 3708 } 3709 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3710 sc->sc_wdcdev.irqack = pciide_irqack; 3711 } 3712 3713 sc->sc_wdcdev.PIO_cap = 4; 3714 sc->sc_wdcdev.DMA_cap = 2; 3715 sc->sc_wdcdev.set_modes = acer_setup_channel; 3716 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3717 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3718 3719 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 3720 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 3721 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 3722 3723 /* Enable "microsoft register bits" R/W. */ 3724 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 3725 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 3726 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 3727 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 3728 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 3729 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 3730 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 3731 ~ACER_CHANSTATUSREGS_RO); 3732 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 3733 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 3734 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 3735 /* Don't use cr, re-read the real register content instead */ 3736 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 3737 PCI_CLASS_REG)); 3738 3739 /* From linux: enable "Cable Detection" */ 3740 if (rev >= 0xC2) { 3741 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B, 3742 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B) 3743 | ACER_0x4B_CDETECT); 3744 } 3745 3746 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3747 cp = &sc->pciide_channels[channel]; 3748 if (pciide_chansetup(sc, channel, interface) == 0) 3749 continue; 3750 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 3751 aprint_normal("%s: %s channel ignored (disabled)\n", 3752 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3753 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 3754 continue; 3755 } 3756 /* newer controllers seems to lack the ACER_CHIDS. Sigh */ 3757 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3758 (rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr); 3759 } 3760 } 3761 3762 void 3763 acer_setup_channel(chp) 3764 struct channel_softc *chp; 3765 { 3766 struct ata_drive_datas *drvp; 3767 int drive; 3768 u_int32_t acer_fifo_udma; 3769 u_int32_t idedma_ctl; 3770 struct pciide_channel *cp = (struct pciide_channel*)chp; 3771 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3772 3773 idedma_ctl = 0; 3774 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 3775 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 3776 acer_fifo_udma), DEBUG_PROBE); 3777 /* setup DMA if needed */ 3778 pciide_channel_dma_setup(cp); 3779 3780 if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) & 3781 DRIVE_UDMA) { /* check 80 pins cable */ 3782 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) & 3783 ACER_0x4A_80PIN(chp->channel)) { 3784 if (chp->ch_drive[0].UDMA_mode > 2) 3785 chp->ch_drive[0].UDMA_mode = 2; 3786 if (chp->ch_drive[1].UDMA_mode > 2) 3787 chp->ch_drive[1].UDMA_mode = 2; 3788 } 3789 } 3790 3791 for (drive = 0; drive < 2; drive++) { 3792 drvp = &chp->ch_drive[drive]; 3793 /* If no drive, skip */ 3794 if ((drvp->drive_flags & DRIVE) == 0) 3795 continue; 3796 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 3797 "channel %d drive %d 0x%x\n", chp->channel, drive, 3798 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3799 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 3800 /* clear FIFO/DMA mode */ 3801 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 3802 ACER_UDMA_EN(chp->channel, drive) | 3803 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 3804 3805 /* add timing values, setup DMA if needed */ 3806 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 3807 (drvp->drive_flags & DRIVE_UDMA) == 0) { 3808 acer_fifo_udma |= 3809 ACER_FTH_OPL(chp->channel, drive, 0x1); 3810 goto pio; 3811 } 3812 3813 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 3814 if (drvp->drive_flags & DRIVE_UDMA) { 3815 /* use Ultra/DMA */ 3816 drvp->drive_flags &= ~DRIVE_DMA; 3817 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 3818 acer_fifo_udma |= 3819 ACER_UDMA_TIM(chp->channel, drive, 3820 acer_udma[drvp->UDMA_mode]); 3821 /* XXX disable if one drive < UDMA3 ? */ 3822 if (drvp->UDMA_mode >= 3) { 3823 pciide_pci_write(sc->sc_pc, sc->sc_tag, 3824 ACER_0x4B, 3825 pciide_pci_read(sc->sc_pc, sc->sc_tag, 3826 ACER_0x4B) | ACER_0x4B_UDMA66); 3827 } 3828 } else { 3829 /* 3830 * use Multiword DMA 3831 * Timings will be used for both PIO and DMA, 3832 * so adjust DMA mode if needed 3833 */ 3834 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3835 drvp->PIO_mode = drvp->DMA_mode + 2; 3836 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3837 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3838 drvp->PIO_mode - 2 : 0; 3839 if (drvp->DMA_mode == 0) 3840 drvp->PIO_mode = 0; 3841 } 3842 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3843 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3844 ACER_IDETIM(chp->channel, drive), 3845 acer_pio[drvp->PIO_mode]); 3846 } 3847 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3848 acer_fifo_udma), DEBUG_PROBE); 3849 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3850 if (idedma_ctl != 0) { 3851 /* Add software bits in status register */ 3852 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3853 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 3854 idedma_ctl); 3855 } 3856 } 3857 3858 int 3859 acer_pci_intr(arg) 3860 void *arg; 3861 { 3862 struct pciide_softc *sc = arg; 3863 struct pciide_channel *cp; 3864 struct channel_softc *wdc_cp; 3865 int i, rv, crv; 3866 u_int32_t chids; 3867 3868 rv = 0; 3869 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3870 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3871 cp = &sc->pciide_channels[i]; 3872 wdc_cp = &cp->wdc_channel; 3873 /* If a compat channel skip. */ 3874 if (cp->compat) 3875 continue; 3876 if (chids & ACER_CHIDS_INT(i)) { 3877 crv = wdcintr(wdc_cp); 3878 if (crv == 0) 3879 printf("%s:%d: bogus intr\n", 3880 sc->sc_wdcdev.sc_dev.dv_xname, i); 3881 else 3882 rv = 1; 3883 } 3884 } 3885 return rv; 3886 } 3887 3888 void 3889 hpt_chip_map(sc, pa) 3890 struct pciide_softc *sc; 3891 struct pci_attach_args *pa; 3892 { 3893 struct pciide_channel *cp; 3894 int i, compatchan, revision; 3895 pcireg_t interface; 3896 bus_size_t cmdsize, ctlsize; 3897 3898 if (pciide_chipen(sc, pa) == 0) 3899 return; 3900 3901 revision = PCI_REVISION(pa->pa_class); 3902 aprint_normal("%s: Triones/Highpoint ", 3903 sc->sc_wdcdev.sc_dev.dv_xname); 3904 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3905 aprint_normal("HPT374 IDE Controller\n"); 3906 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372) 3907 aprint_normal("HPT372 IDE Controller\n"); 3908 else if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366) { 3909 if (revision == HPT372_REV) 3910 aprint_normal("HPT372 IDE Controller\n"); 3911 else if (revision == HPT370_REV) 3912 aprint_normal("HPT370 IDE Controller\n"); 3913 else if (revision == HPT370A_REV) 3914 aprint_normal("HPT370A IDE Controller\n"); 3915 else if (revision == HPT366_REV) 3916 aprint_normal("HPT366 IDE Controller\n"); 3917 else 3918 aprint_normal("unknown HPT IDE controller rev %d\n", 3919 revision); 3920 } else 3921 aprint_normal("unknown HPT IDE controller 0x%x\n", 3922 sc->sc_pp->ide_product); 3923 3924 /* 3925 * when the chip is in native mode it identifies itself as a 3926 * 'misc mass storage'. Fake interface in this case. 3927 */ 3928 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3929 interface = PCI_INTERFACE(pa->pa_class); 3930 } else { 3931 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3932 PCIIDE_INTERFACE_PCI(0); 3933 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3934 (revision == HPT370_REV || revision == HPT370A_REV || 3935 revision == HPT372_REV)) || 3936 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3937 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 3938 interface |= PCIIDE_INTERFACE_PCI(1); 3939 } 3940 3941 aprint_normal("%s: bus-master DMA support present", 3942 sc->sc_wdcdev.sc_dev.dv_xname); 3943 pciide_mapreg_dma(sc, pa); 3944 aprint_normal("\n"); 3945 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3946 WDC_CAPABILITY_MODE; 3947 if (sc->sc_dma_ok) { 3948 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3949 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3950 sc->sc_wdcdev.irqack = pciide_irqack; 3951 } 3952 sc->sc_wdcdev.PIO_cap = 4; 3953 sc->sc_wdcdev.DMA_cap = 2; 3954 3955 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3956 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3957 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3958 revision == HPT366_REV) { 3959 sc->sc_wdcdev.UDMA_cap = 4; 3960 /* 3961 * The 366 has 2 PCI IDE functions, one for primary and one 3962 * for secondary. So we need to call pciide_mapregs_compat() 3963 * with the real channel 3964 */ 3965 if (pa->pa_function == 0) { 3966 compatchan = 0; 3967 } else if (pa->pa_function == 1) { 3968 compatchan = 1; 3969 } else { 3970 aprint_error("%s: unexpected PCI function %d\n", 3971 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3972 return; 3973 } 3974 sc->sc_wdcdev.nchannels = 1; 3975 } else { 3976 sc->sc_wdcdev.nchannels = 2; 3977 if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 || 3978 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 3979 (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 3980 revision == HPT372_REV)) 3981 sc->sc_wdcdev.UDMA_cap = 6; 3982 else 3983 sc->sc_wdcdev.UDMA_cap = 5; 3984 } 3985 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3986 cp = &sc->pciide_channels[i]; 3987 if (sc->sc_wdcdev.nchannels > 1) { 3988 compatchan = i; 3989 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3990 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3991 aprint_normal( 3992 "%s: %s channel ignored (disabled)\n", 3993 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3994 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 3995 continue; 3996 } 3997 } 3998 if (pciide_chansetup(sc, i, interface) == 0) 3999 continue; 4000 if (interface & PCIIDE_INTERFACE_PCI(i)) { 4001 pciide_mapregs_native(pa, cp, &cmdsize, 4002 &ctlsize, hpt_pci_intr); 4003 } else { 4004 pciide_mapregs_compat(pa, cp, compatchan, 4005 &cmdsize, &ctlsize); 4006 } 4007 } 4008 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 4009 (revision == HPT370_REV || revision == HPT370A_REV || 4010 revision == HPT372_REV)) || 4011 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 4012 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) { 4013 /* 4014 * HPT370_REV and highter has a bit to disable interrupts, 4015 * make sure to clear it 4016 */ 4017 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 4018 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 4019 ~HPT_CSEL_IRQDIS); 4020 } 4021 /* set clocks, etc (mandatory on 372/4, optional otherwise) */ 4022 if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 && 4023 revision == HPT372_REV ) || 4024 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372 || 4025 sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) 4026 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2, 4027 (pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) & 4028 HPT_SC2_MAEN) | HPT_SC2_OSC_EN); 4029 return; 4030 } 4031 4032 void 4033 hpt_setup_channel(chp) 4034 struct channel_softc *chp; 4035 { 4036 struct ata_drive_datas *drvp; 4037 int drive; 4038 int cable; 4039 u_int32_t before, after; 4040 u_int32_t idedma_ctl; 4041 struct pciide_channel *cp = (struct pciide_channel*)chp; 4042 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4043 int revision = 4044 PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 4045 4046 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 4047 4048 /* setup DMA if needed */ 4049 pciide_channel_dma_setup(cp); 4050 4051 idedma_ctl = 0; 4052 4053 /* Per drive settings */ 4054 for (drive = 0; drive < 2; drive++) { 4055 drvp = &chp->ch_drive[drive]; 4056 /* If no drive, skip */ 4057 if ((drvp->drive_flags & DRIVE) == 0) 4058 continue; 4059 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 4060 HPT_IDETIM(chp->channel, drive)); 4061 4062 /* add timing values, setup DMA if needed */ 4063 if (drvp->drive_flags & DRIVE_UDMA) { 4064 /* use Ultra/DMA */ 4065 drvp->drive_flags &= ~DRIVE_DMA; 4066 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 4067 drvp->UDMA_mode > 2) 4068 drvp->UDMA_mode = 2; 4069 switch (sc->sc_pp->ide_product) { 4070 case PCI_PRODUCT_TRIONES_HPT374: 4071 after = hpt374_udma[drvp->UDMA_mode]; 4072 break; 4073 case PCI_PRODUCT_TRIONES_HPT372: 4074 after = hpt372_udma[drvp->UDMA_mode]; 4075 break; 4076 case PCI_PRODUCT_TRIONES_HPT366: 4077 default: 4078 switch(revision) { 4079 case HPT372_REV: 4080 after = hpt372_udma[drvp->UDMA_mode]; 4081 break; 4082 case HPT370_REV: 4083 case HPT370A_REV: 4084 after = hpt370_udma[drvp->UDMA_mode]; 4085 break; 4086 case HPT366_REV: 4087 default: 4088 after = hpt366_udma[drvp->UDMA_mode]; 4089 break; 4090 } 4091 } 4092 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4093 } else if (drvp->drive_flags & DRIVE_DMA) { 4094 /* 4095 * use Multiword DMA. 4096 * Timings will be used for both PIO and DMA, so adjust 4097 * DMA mode if needed 4098 */ 4099 if (drvp->PIO_mode >= 3 && 4100 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 4101 drvp->DMA_mode = drvp->PIO_mode - 2; 4102 } 4103 switch (sc->sc_pp->ide_product) { 4104 case PCI_PRODUCT_TRIONES_HPT374: 4105 after = hpt374_dma[drvp->DMA_mode]; 4106 break; 4107 case PCI_PRODUCT_TRIONES_HPT372: 4108 after = hpt372_dma[drvp->DMA_mode]; 4109 break; 4110 case PCI_PRODUCT_TRIONES_HPT366: 4111 default: 4112 switch(revision) { 4113 case HPT372_REV: 4114 after = hpt372_dma[drvp->DMA_mode]; 4115 break; 4116 case HPT370_REV: 4117 case HPT370A_REV: 4118 after = hpt370_dma[drvp->DMA_mode]; 4119 break; 4120 case HPT366_REV: 4121 default: 4122 after = hpt366_dma[drvp->DMA_mode]; 4123 break; 4124 } 4125 } 4126 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4127 } else { 4128 /* PIO only */ 4129 switch (sc->sc_pp->ide_product) { 4130 case PCI_PRODUCT_TRIONES_HPT374: 4131 after = hpt374_pio[drvp->PIO_mode]; 4132 break; 4133 case PCI_PRODUCT_TRIONES_HPT372: 4134 after = hpt372_pio[drvp->PIO_mode]; 4135 break; 4136 case PCI_PRODUCT_TRIONES_HPT366: 4137 default: 4138 switch(revision) { 4139 case HPT372_REV: 4140 after = hpt372_pio[drvp->PIO_mode]; 4141 break; 4142 case HPT370_REV: 4143 case HPT370A_REV: 4144 after = hpt370_pio[drvp->PIO_mode]; 4145 break; 4146 case HPT366_REV: 4147 default: 4148 after = hpt366_pio[drvp->PIO_mode]; 4149 break; 4150 } 4151 } 4152 } 4153 pci_conf_write(sc->sc_pc, sc->sc_tag, 4154 HPT_IDETIM(chp->channel, drive), after); 4155 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 4156 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 4157 after, before), DEBUG_PROBE); 4158 } 4159 if (idedma_ctl != 0) { 4160 /* Add software bits in status register */ 4161 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4162 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4163 idedma_ctl); 4164 } 4165 } 4166 4167 int 4168 hpt_pci_intr(arg) 4169 void *arg; 4170 { 4171 struct pciide_softc *sc = arg; 4172 struct pciide_channel *cp; 4173 struct channel_softc *wdc_cp; 4174 int rv = 0; 4175 int dmastat, i, crv; 4176 4177 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4178 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4179 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4180 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 4181 IDEDMA_CTL_INTR) 4182 continue; 4183 cp = &sc->pciide_channels[i]; 4184 wdc_cp = &cp->wdc_channel; 4185 crv = wdcintr(wdc_cp); 4186 if (crv == 0) { 4187 printf("%s:%d: bogus intr\n", 4188 sc->sc_wdcdev.sc_dev.dv_xname, i); 4189 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4190 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 4191 } else 4192 rv = 1; 4193 } 4194 return rv; 4195 } 4196 4197 4198 /* Macros to test product */ 4199 #define PDC_IS_262(sc) \ 4200 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 4201 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 4202 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 4203 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4204 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4205 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4206 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4207 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4208 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4209 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4210 #define PDC_IS_265(sc) \ 4211 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 4212 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X || \ 4213 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4214 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4215 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4216 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4217 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4218 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4219 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4220 #define PDC_IS_268(sc) \ 4221 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2 || \ 4222 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100TX2v2 || \ 4223 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4224 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4225 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4226 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4227 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4228 #define PDC_IS_276(sc) \ 4229 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133 || \ 4230 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2 || \ 4231 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_MBULTRA133 || \ 4232 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA133TX2v2 || \ 4233 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_FASTTRAK133LITE) 4234 4235 void 4236 pdc202xx_chip_map(sc, pa) 4237 struct pciide_softc *sc; 4238 struct pci_attach_args *pa; 4239 { 4240 struct pciide_channel *cp; 4241 int channel; 4242 pcireg_t interface, st, mode; 4243 bus_size_t cmdsize, ctlsize; 4244 4245 if (!PDC_IS_268(sc)) { 4246 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4247 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", 4248 st), DEBUG_PROBE); 4249 } 4250 if (pciide_chipen(sc, pa) == 0) 4251 return; 4252 4253 /* turn off RAID mode */ 4254 if (!PDC_IS_268(sc)) 4255 st &= ~PDC2xx_STATE_IDERAID; 4256 4257 /* 4258 * can't rely on the PCI_CLASS_REG content if the chip was in raid 4259 * mode. We have to fake interface 4260 */ 4261 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 4262 if (PDC_IS_268(sc) || (st & PDC2xx_STATE_NATIVE)) 4263 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4264 4265 aprint_normal("%s: bus-master DMA support present", 4266 sc->sc_wdcdev.sc_dev.dv_xname); 4267 pciide_mapreg_dma(sc, pa); 4268 aprint_normal("\n"); 4269 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4270 WDC_CAPABILITY_MODE; 4271 if (sc->sc_dma_ok) { 4272 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4273 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4274 sc->sc_wdcdev.irqack = pciide_irqack; 4275 } 4276 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 4277 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_RAID) 4278 sc->sc_wdcdev.cap |= WDC_CAPABILITY_RAID; 4279 sc->sc_wdcdev.PIO_cap = 4; 4280 sc->sc_wdcdev.DMA_cap = 2; 4281 if (PDC_IS_276(sc)) 4282 sc->sc_wdcdev.UDMA_cap = 6; 4283 else if (PDC_IS_265(sc)) 4284 sc->sc_wdcdev.UDMA_cap = 5; 4285 else if (PDC_IS_262(sc)) 4286 sc->sc_wdcdev.UDMA_cap = 4; 4287 else 4288 sc->sc_wdcdev.UDMA_cap = 2; 4289 sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ? 4290 pdc20268_setup_channel : pdc202xx_setup_channel; 4291 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4292 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4293 4294 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || 4295 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || 4296 sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) { 4297 sc->sc_wdcdev.dma_start = pdc20262_dma_start; 4298 sc->sc_wdcdev.dma_finish = pdc20262_dma_finish; 4299 } 4300 4301 if (!PDC_IS_268(sc)) { 4302 /* setup failsafe defaults */ 4303 mode = 0; 4304 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 4305 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 4306 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 4307 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 4308 for (channel = 0; 4309 channel < sc->sc_wdcdev.nchannels; 4310 channel++) { 4311 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 4312 "drive 0 initial timings 0x%x, now 0x%x\n", 4313 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 4314 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 4315 DEBUG_PROBE); 4316 pci_conf_write(sc->sc_pc, sc->sc_tag, 4317 PDC2xx_TIM(channel, 0), mode | PDC2xx_TIM_IORDYp); 4318 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d " 4319 "drive 1 initial timings 0x%x, now 0x%x\n", 4320 channel, pci_conf_read(sc->sc_pc, sc->sc_tag, 4321 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 4322 pci_conf_write(sc->sc_pc, sc->sc_tag, 4323 PDC2xx_TIM(channel, 1), mode); 4324 } 4325 4326 mode = PDC2xx_SCR_DMA; 4327 if (PDC_IS_265(sc)) { 4328 mode = PDC2xx_SCR_SET_GEN(mode, PDC265_SCR_GEN_LAT); 4329 } else if (PDC_IS_262(sc)) { 4330 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 4331 } else { 4332 /* the BIOS set it up this way */ 4333 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 4334 } 4335 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 4336 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 4337 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, " 4338 "now 0x%x\n", 4339 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4340 PDC2xx_SCR), 4341 mode), DEBUG_PROBE); 4342 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4343 PDC2xx_SCR, mode); 4344 4345 /* controller initial state register is OK even without BIOS */ 4346 /* Set DMA mode to IDE DMA compatibility */ 4347 mode = 4348 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 4349 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode), 4350 DEBUG_PROBE); 4351 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 4352 mode | 0x1); 4353 mode = 4354 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 4355 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 4356 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 4357 mode | 0x1); 4358 } 4359 4360 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4361 cp = &sc->pciide_channels[channel]; 4362 if (pciide_chansetup(sc, channel, interface) == 0) 4363 continue; 4364 if (!PDC_IS_268(sc) && (st & (PDC_IS_262(sc) ? 4365 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 4366 aprint_normal("%s: %s channel ignored (disabled)\n", 4367 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4368 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 4369 continue; 4370 } 4371 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4372 PDC_IS_265(sc) ? pdc20265_pci_intr : pdc202xx_pci_intr); 4373 } 4374 if (!PDC_IS_268(sc)) { 4375 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state " 4376 "0x%x\n", st), DEBUG_PROBE); 4377 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 4378 } 4379 return; 4380 } 4381 4382 void 4383 pdc202xx_setup_channel(chp) 4384 struct channel_softc *chp; 4385 { 4386 struct ata_drive_datas *drvp; 4387 int drive; 4388 pcireg_t mode, st; 4389 u_int32_t idedma_ctl, scr, atapi; 4390 struct pciide_channel *cp = (struct pciide_channel*)chp; 4391 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4392 int channel = chp->channel; 4393 4394 /* setup DMA if needed */ 4395 pciide_channel_dma_setup(cp); 4396 4397 idedma_ctl = 0; 4398 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 4399 sc->sc_wdcdev.sc_dev.dv_xname, 4400 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 4401 DEBUG_PROBE); 4402 4403 /* Per channel settings */ 4404 if (PDC_IS_262(sc)) { 4405 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4406 PDC262_U66); 4407 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 4408 /* Trim UDMA mode */ 4409 if ((st & PDC262_STATE_80P(channel)) != 0 || 4410 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4411 chp->ch_drive[0].UDMA_mode <= 2) || 4412 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4413 chp->ch_drive[1].UDMA_mode <= 2)) { 4414 if (chp->ch_drive[0].UDMA_mode > 2) 4415 chp->ch_drive[0].UDMA_mode = 2; 4416 if (chp->ch_drive[1].UDMA_mode > 2) 4417 chp->ch_drive[1].UDMA_mode = 2; 4418 } 4419 /* Set U66 if needed */ 4420 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 4421 chp->ch_drive[0].UDMA_mode > 2) || 4422 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 4423 chp->ch_drive[1].UDMA_mode > 2)) 4424 scr |= PDC262_U66_EN(channel); 4425 else 4426 scr &= ~PDC262_U66_EN(channel); 4427 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4428 PDC262_U66, scr); 4429 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 4430 sc->sc_wdcdev.sc_dev.dv_xname, channel, 4431 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4432 PDC262_ATAPI(channel))), DEBUG_PROBE); 4433 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 4434 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 4435 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4436 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4437 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 4438 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 4439 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 4440 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 4441 atapi = 0; 4442 else 4443 atapi = PDC262_ATAPI_UDMA; 4444 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4445 PDC262_ATAPI(channel), atapi); 4446 } 4447 } 4448 for (drive = 0; drive < 2; drive++) { 4449 drvp = &chp->ch_drive[drive]; 4450 /* If no drive, skip */ 4451 if ((drvp->drive_flags & DRIVE) == 0) 4452 continue; 4453 mode = 0; 4454 if (drvp->drive_flags & DRIVE_UDMA) { 4455 /* use Ultra/DMA */ 4456 drvp->drive_flags &= ~DRIVE_DMA; 4457 mode = PDC2xx_TIM_SET_MB(mode, 4458 pdc2xx_udma_mb[drvp->UDMA_mode]); 4459 mode = PDC2xx_TIM_SET_MC(mode, 4460 pdc2xx_udma_mc[drvp->UDMA_mode]); 4461 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4462 } else if (drvp->drive_flags & DRIVE_DMA) { 4463 mode = PDC2xx_TIM_SET_MB(mode, 4464 pdc2xx_dma_mb[drvp->DMA_mode]); 4465 mode = PDC2xx_TIM_SET_MC(mode, 4466 pdc2xx_dma_mc[drvp->DMA_mode]); 4467 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4468 } else { 4469 mode = PDC2xx_TIM_SET_MB(mode, 4470 pdc2xx_dma_mb[0]); 4471 mode = PDC2xx_TIM_SET_MC(mode, 4472 pdc2xx_dma_mc[0]); 4473 } 4474 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 4475 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 4476 if (drvp->drive_flags & DRIVE_ATA) 4477 mode |= PDC2xx_TIM_PRE; 4478 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 4479 if (drvp->PIO_mode >= 3) { 4480 mode |= PDC2xx_TIM_IORDY; 4481 if (drive == 0) 4482 mode |= PDC2xx_TIM_IORDYp; 4483 } 4484 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 4485 "timings 0x%x\n", 4486 sc->sc_wdcdev.sc_dev.dv_xname, 4487 chp->channel, drive, mode), DEBUG_PROBE); 4488 pci_conf_write(sc->sc_pc, sc->sc_tag, 4489 PDC2xx_TIM(chp->channel, drive), mode); 4490 } 4491 if (idedma_ctl != 0) { 4492 /* Add software bits in status register */ 4493 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4494 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4495 idedma_ctl); 4496 } 4497 } 4498 4499 void 4500 pdc20268_setup_channel(chp) 4501 struct channel_softc *chp; 4502 { 4503 struct ata_drive_datas *drvp; 4504 int drive; 4505 u_int32_t idedma_ctl; 4506 struct pciide_channel *cp = (struct pciide_channel*)chp; 4507 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4508 int u100; 4509 4510 /* setup DMA if needed */ 4511 pciide_channel_dma_setup(cp); 4512 4513 idedma_ctl = 0; 4514 4515 /* I don't know what this is for, FreeBSD does it ... */ 4516 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4517 IDEDMA_CMD + 0x1 + IDEDMA_SCH_OFFSET * chp->channel, 0x0b); 4518 4519 /* 4520 * cable type detect, from FreeBSD 4521 */ 4522 u100 = (bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4523 IDEDMA_CMD + 0x3 + IDEDMA_SCH_OFFSET * chp->channel) & 0x04) ? 4524 0 : 1; 4525 4526 for (drive = 0; drive < 2; drive++) { 4527 drvp = &chp->ch_drive[drive]; 4528 /* If no drive, skip */ 4529 if ((drvp->drive_flags & DRIVE) == 0) 4530 continue; 4531 if (drvp->drive_flags & DRIVE_UDMA) { 4532 /* use Ultra/DMA */ 4533 drvp->drive_flags &= ~DRIVE_DMA; 4534 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4535 if (drvp->UDMA_mode > 2 && u100 == 0) 4536 drvp->UDMA_mode = 2; 4537 } else if (drvp->drive_flags & DRIVE_DMA) { 4538 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4539 } 4540 } 4541 /* nothing to do to setup modes, the controller snoop SET_FEATURE cmd */ 4542 if (idedma_ctl != 0) { 4543 /* Add software bits in status register */ 4544 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4545 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 4546 idedma_ctl); 4547 } 4548 } 4549 4550 int 4551 pdc202xx_pci_intr(arg) 4552 void *arg; 4553 { 4554 struct pciide_softc *sc = arg; 4555 struct pciide_channel *cp; 4556 struct channel_softc *wdc_cp; 4557 int i, rv, crv; 4558 u_int32_t scr; 4559 4560 rv = 0; 4561 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 4562 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4563 cp = &sc->pciide_channels[i]; 4564 wdc_cp = &cp->wdc_channel; 4565 /* If a compat channel skip. */ 4566 if (cp->compat) 4567 continue; 4568 if (scr & PDC2xx_SCR_INT(i)) { 4569 crv = wdcintr(wdc_cp); 4570 if (crv == 0) 4571 printf("%s:%d: bogus intr (reg 0x%x)\n", 4572 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 4573 else 4574 rv = 1; 4575 } 4576 } 4577 return rv; 4578 } 4579 4580 int 4581 pdc20265_pci_intr(arg) 4582 void *arg; 4583 { 4584 struct pciide_softc *sc = arg; 4585 struct pciide_channel *cp; 4586 struct channel_softc *wdc_cp; 4587 int i, rv, crv; 4588 u_int32_t dmastat; 4589 4590 rv = 0; 4591 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4592 cp = &sc->pciide_channels[i]; 4593 wdc_cp = &cp->wdc_channel; 4594 /* If a compat channel skip. */ 4595 if (cp->compat) 4596 continue; 4597 /* 4598 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 4599 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 4600 * So use it instead (requires 2 reg reads instead of 1, 4601 * but we can't do it another way). 4602 */ 4603 dmastat = bus_space_read_1(sc->sc_dma_iot, 4604 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 4605 if((dmastat & IDEDMA_CTL_INTR) == 0) 4606 continue; 4607 crv = wdcintr(wdc_cp); 4608 if (crv == 0) 4609 printf("%s:%d: bogus intr\n", 4610 sc->sc_wdcdev.sc_dev.dv_xname, i); 4611 else 4612 rv = 1; 4613 } 4614 return rv; 4615 } 4616 4617 static void 4618 pdc20262_dma_start(v, channel, drive) 4619 void *v; 4620 int channel, drive; 4621 { 4622 struct pciide_softc *sc = v; 4623 struct pciide_dma_maps *dma_maps = 4624 &sc->pciide_channels[channel].dma_maps[drive]; 4625 int atapi; 4626 4627 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 4628 atapi = (dma_maps->dma_flags & WDC_DMA_READ) ? 4629 PDC262_ATAPI_LBA48_READ : PDC262_ATAPI_LBA48_WRITE; 4630 atapi |= dma_maps->dmamap_xfer->dm_mapsize >> 1; 4631 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4632 PDC262_ATAPI(channel), atapi); 4633 } 4634 4635 pciide_dma_start(v, channel, drive); 4636 } 4637 4638 int 4639 pdc20262_dma_finish(v, channel, drive, force) 4640 void *v; 4641 int channel, drive; 4642 int force; 4643 { 4644 struct pciide_softc *sc = v; 4645 struct pciide_dma_maps *dma_maps = 4646 &sc->pciide_channels[channel].dma_maps[drive]; 4647 struct channel_softc *chp; 4648 int atapi, error; 4649 4650 error = pciide_dma_finish(v, channel, drive, force); 4651 4652 if (dma_maps->dma_flags & WDC_DMA_LBA48) { 4653 chp = sc->wdc_chanarray[channel]; 4654 atapi = 0; 4655 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 4656 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 4657 if ((!(chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4658 (chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 4659 !(chp->ch_drive[1].drive_flags & DRIVE_DMA)) && 4660 (!(chp->ch_drive[1].drive_flags & DRIVE_UDMA) || 4661 (chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4662 !(chp->ch_drive[0].drive_flags & DRIVE_DMA))) 4663 atapi = PDC262_ATAPI_UDMA; 4664 } 4665 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 4666 PDC262_ATAPI(channel), atapi); 4667 } 4668 4669 return error; 4670 } 4671 4672 void 4673 opti_chip_map(sc, pa) 4674 struct pciide_softc *sc; 4675 struct pci_attach_args *pa; 4676 { 4677 struct pciide_channel *cp; 4678 bus_size_t cmdsize, ctlsize; 4679 pcireg_t interface; 4680 u_int8_t init_ctrl; 4681 int channel; 4682 4683 if (pciide_chipen(sc, pa) == 0) 4684 return; 4685 4686 aprint_normal("%s: bus-master DMA support present", 4687 sc->sc_wdcdev.sc_dev.dv_xname); 4688 4689 /* 4690 * XXXSCW: 4691 * There seem to be a couple of buggy revisions/implementations 4692 * of the OPTi pciide chipset. This kludge seems to fix one of 4693 * the reported problems (PR/11644) but still fails for the 4694 * other (PR/13151), although the latter may be due to other 4695 * issues too... 4696 */ 4697 if (PCI_REVISION(pa->pa_class) <= 0x12) { 4698 aprint_normal(" but disabled due to chip rev. <= 0x12"); 4699 sc->sc_dma_ok = 0; 4700 } else 4701 pciide_mapreg_dma(sc, pa); 4702 4703 aprint_normal("\n"); 4704 4705 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 4706 WDC_CAPABILITY_MODE; 4707 sc->sc_wdcdev.PIO_cap = 4; 4708 if (sc->sc_dma_ok) { 4709 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 4710 sc->sc_wdcdev.irqack = pciide_irqack; 4711 sc->sc_wdcdev.DMA_cap = 2; 4712 } 4713 sc->sc_wdcdev.set_modes = opti_setup_channel; 4714 4715 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4716 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 4717 4718 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 4719 OPTI_REG_INIT_CONTROL); 4720 4721 interface = PCI_INTERFACE(pa->pa_class); 4722 4723 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 4724 cp = &sc->pciide_channels[channel]; 4725 if (pciide_chansetup(sc, channel, interface) == 0) 4726 continue; 4727 if (channel == 1 && 4728 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 4729 aprint_normal("%s: %s channel ignored (disabled)\n", 4730 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 4731 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 4732 continue; 4733 } 4734 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4735 pciide_pci_intr); 4736 } 4737 } 4738 4739 void 4740 opti_setup_channel(chp) 4741 struct channel_softc *chp; 4742 { 4743 struct ata_drive_datas *drvp; 4744 struct pciide_channel *cp = (struct pciide_channel*)chp; 4745 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4746 int drive, spd; 4747 int mode[2]; 4748 u_int8_t rv, mr; 4749 4750 /* 4751 * The `Delay' and `Address Setup Time' fields of the 4752 * Miscellaneous Register are always zero initially. 4753 */ 4754 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 4755 mr &= ~(OPTI_MISC_DELAY_MASK | 4756 OPTI_MISC_ADDR_SETUP_MASK | 4757 OPTI_MISC_INDEX_MASK); 4758 4759 /* Prime the control register before setting timing values */ 4760 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 4761 4762 /* Determine the clockrate of the PCIbus the chip is attached to */ 4763 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 4764 spd &= OPTI_STRAP_PCI_SPEED_MASK; 4765 4766 /* setup DMA if needed */ 4767 pciide_channel_dma_setup(cp); 4768 4769 for (drive = 0; drive < 2; drive++) { 4770 drvp = &chp->ch_drive[drive]; 4771 /* If no drive, skip */ 4772 if ((drvp->drive_flags & DRIVE) == 0) { 4773 mode[drive] = -1; 4774 continue; 4775 } 4776 4777 if ((drvp->drive_flags & DRIVE_DMA)) { 4778 /* 4779 * Timings will be used for both PIO and DMA, 4780 * so adjust DMA mode if needed 4781 */ 4782 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 4783 drvp->PIO_mode = drvp->DMA_mode + 2; 4784 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 4785 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 4786 drvp->PIO_mode - 2 : 0; 4787 if (drvp->DMA_mode == 0) 4788 drvp->PIO_mode = 0; 4789 4790 mode[drive] = drvp->DMA_mode + 5; 4791 } else 4792 mode[drive] = drvp->PIO_mode; 4793 4794 if (drive && mode[0] >= 0 && 4795 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 4796 /* 4797 * Can't have two drives using different values 4798 * for `Address Setup Time'. 4799 * Slow down the faster drive to compensate. 4800 */ 4801 int d = (opti_tim_as[spd][mode[0]] > 4802 opti_tim_as[spd][mode[1]]) ? 0 : 1; 4803 4804 mode[d] = mode[1-d]; 4805 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 4806 chp->ch_drive[d].DMA_mode = 0; 4807 chp->ch_drive[d].drive_flags &= ~DRIVE_DMA; 4808 } 4809 } 4810 4811 for (drive = 0; drive < 2; drive++) { 4812 int m; 4813 if ((m = mode[drive]) < 0) 4814 continue; 4815 4816 /* Set the Address Setup Time and select appropriate index */ 4817 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 4818 rv |= OPTI_MISC_INDEX(drive); 4819 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 4820 4821 /* Set the pulse width and recovery timing parameters */ 4822 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 4823 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 4824 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 4825 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 4826 4827 /* Set the Enhanced Mode register appropriately */ 4828 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 4829 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 4830 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 4831 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 4832 } 4833 4834 /* Finally, enable the timings */ 4835 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 4836 } 4837 4838 #define ACARD_IS_850(sc) \ 4839 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 4840 4841 void 4842 acard_chip_map(sc, pa) 4843 struct pciide_softc *sc; 4844 struct pci_attach_args *pa; 4845 { 4846 struct pciide_channel *cp; 4847 int i; 4848 pcireg_t interface; 4849 bus_size_t cmdsize, ctlsize; 4850 4851 if (pciide_chipen(sc, pa) == 0) 4852 return; 4853 4854 /* 4855 * when the chip is in native mode it identifies itself as a 4856 * 'misc mass storage'. Fake interface in this case. 4857 */ 4858 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 4859 interface = PCI_INTERFACE(pa->pa_class); 4860 } else { 4861 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 4862 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 4863 } 4864 4865 aprint_normal("%s: bus-master DMA support present", 4866 sc->sc_wdcdev.sc_dev.dv_xname); 4867 pciide_mapreg_dma(sc, pa); 4868 aprint_normal("\n"); 4869 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 4870 WDC_CAPABILITY_MODE; 4871 4872 if (sc->sc_dma_ok) { 4873 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 4874 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 4875 sc->sc_wdcdev.irqack = pciide_irqack; 4876 } 4877 sc->sc_wdcdev.PIO_cap = 4; 4878 sc->sc_wdcdev.DMA_cap = 2; 4879 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 4880 4881 sc->sc_wdcdev.set_modes = acard_setup_channel; 4882 sc->sc_wdcdev.channels = sc->wdc_chanarray; 4883 sc->sc_wdcdev.nchannels = 2; 4884 4885 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 4886 cp = &sc->pciide_channels[i]; 4887 if (pciide_chansetup(sc, i, interface) == 0) 4888 continue; 4889 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 4890 pciide_pci_intr); 4891 } 4892 if (!ACARD_IS_850(sc)) { 4893 u_int32_t reg; 4894 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 4895 reg &= ~ATP860_CTRL_INT; 4896 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 4897 } 4898 } 4899 4900 void 4901 acard_setup_channel(chp) 4902 struct channel_softc *chp; 4903 { 4904 struct ata_drive_datas *drvp; 4905 struct pciide_channel *cp = (struct pciide_channel*)chp; 4906 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 4907 int channel = chp->channel; 4908 int drive; 4909 u_int32_t idetime, udma_mode; 4910 u_int32_t idedma_ctl; 4911 4912 /* setup DMA if needed */ 4913 pciide_channel_dma_setup(cp); 4914 4915 if (ACARD_IS_850(sc)) { 4916 idetime = 0; 4917 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 4918 udma_mode &= ~ATP850_UDMA_MASK(channel); 4919 } else { 4920 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 4921 idetime &= ~ATP860_SETTIME_MASK(channel); 4922 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 4923 udma_mode &= ~ATP860_UDMA_MASK(channel); 4924 4925 /* check 80 pins cable */ 4926 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 4927 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 4928 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4929 & ATP860_CTRL_80P(chp->channel)) { 4930 if (chp->ch_drive[0].UDMA_mode > 2) 4931 chp->ch_drive[0].UDMA_mode = 2; 4932 if (chp->ch_drive[1].UDMA_mode > 2) 4933 chp->ch_drive[1].UDMA_mode = 2; 4934 } 4935 } 4936 } 4937 4938 idedma_ctl = 0; 4939 4940 /* Per drive settings */ 4941 for (drive = 0; drive < 2; drive++) { 4942 drvp = &chp->ch_drive[drive]; 4943 /* If no drive, skip */ 4944 if ((drvp->drive_flags & DRIVE) == 0) 4945 continue; 4946 /* add timing values, setup DMA if needed */ 4947 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 4948 (drvp->drive_flags & DRIVE_UDMA)) { 4949 /* use Ultra/DMA */ 4950 if (ACARD_IS_850(sc)) { 4951 idetime |= ATP850_SETTIME(drive, 4952 acard_act_udma[drvp->UDMA_mode], 4953 acard_rec_udma[drvp->UDMA_mode]); 4954 udma_mode |= ATP850_UDMA_MODE(channel, drive, 4955 acard_udma_conf[drvp->UDMA_mode]); 4956 } else { 4957 idetime |= ATP860_SETTIME(channel, drive, 4958 acard_act_udma[drvp->UDMA_mode], 4959 acard_rec_udma[drvp->UDMA_mode]); 4960 udma_mode |= ATP860_UDMA_MODE(channel, drive, 4961 acard_udma_conf[drvp->UDMA_mode]); 4962 } 4963 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4964 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 4965 (drvp->drive_flags & DRIVE_DMA)) { 4966 /* use Multiword DMA */ 4967 drvp->drive_flags &= ~DRIVE_UDMA; 4968 if (ACARD_IS_850(sc)) { 4969 idetime |= ATP850_SETTIME(drive, 4970 acard_act_dma[drvp->DMA_mode], 4971 acard_rec_dma[drvp->DMA_mode]); 4972 } else { 4973 idetime |= ATP860_SETTIME(channel, drive, 4974 acard_act_dma[drvp->DMA_mode], 4975 acard_rec_dma[drvp->DMA_mode]); 4976 } 4977 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 4978 } else { 4979 /* PIO only */ 4980 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 4981 if (ACARD_IS_850(sc)) { 4982 idetime |= ATP850_SETTIME(drive, 4983 acard_act_pio[drvp->PIO_mode], 4984 acard_rec_pio[drvp->PIO_mode]); 4985 } else { 4986 idetime |= ATP860_SETTIME(channel, drive, 4987 acard_act_pio[drvp->PIO_mode], 4988 acard_rec_pio[drvp->PIO_mode]); 4989 } 4990 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 4991 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 4992 | ATP8x0_CTRL_EN(channel)); 4993 } 4994 } 4995 4996 if (idedma_ctl != 0) { 4997 /* Add software bits in status register */ 4998 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 4999 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 5000 } 5001 5002 if (ACARD_IS_850(sc)) { 5003 pci_conf_write(sc->sc_pc, sc->sc_tag, 5004 ATP850_IDETIME(channel), idetime); 5005 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 5006 } else { 5007 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 5008 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 5009 } 5010 } 5011 5012 int 5013 acard_pci_intr(arg) 5014 void *arg; 5015 { 5016 struct pciide_softc *sc = arg; 5017 struct pciide_channel *cp; 5018 struct channel_softc *wdc_cp; 5019 int rv = 0; 5020 int dmastat, i, crv; 5021 5022 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5023 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5024 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 5025 if ((dmastat & IDEDMA_CTL_INTR) == 0) 5026 continue; 5027 cp = &sc->pciide_channels[i]; 5028 wdc_cp = &cp->wdc_channel; 5029 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 5030 (void)wdcintr(wdc_cp); 5031 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5032 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 5033 continue; 5034 } 5035 crv = wdcintr(wdc_cp); 5036 if (crv == 0) 5037 printf("%s:%d: bogus intr\n", 5038 sc->sc_wdcdev.sc_dev.dv_xname, i); 5039 else if (crv == 1) 5040 rv = 1; 5041 else if (rv == 0) 5042 rv = crv; 5043 } 5044 return rv; 5045 } 5046 5047 static int 5048 sl82c105_bugchk(struct pci_attach_args *pa) 5049 { 5050 5051 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 5052 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 5053 return (0); 5054 5055 if (PCI_REVISION(pa->pa_class) <= 0x05) 5056 return (1); 5057 5058 return (0); 5059 } 5060 5061 void 5062 sl82c105_chip_map(sc, pa) 5063 struct pciide_softc *sc; 5064 struct pci_attach_args *pa; 5065 { 5066 struct pciide_channel *cp; 5067 bus_size_t cmdsize, ctlsize; 5068 pcireg_t interface, idecr; 5069 int channel; 5070 5071 if (pciide_chipen(sc, pa) == 0) 5072 return; 5073 5074 aprint_normal("%s: bus-master DMA support present", 5075 sc->sc_wdcdev.sc_dev.dv_xname); 5076 5077 /* 5078 * Check to see if we're part of the Winbond 83c553 Southbridge. 5079 * If so, we need to disable DMA on rev. <= 5 of that chip. 5080 */ 5081 if (pci_find_device(pa, sl82c105_bugchk)) { 5082 aprint_normal(" but disabled due to 83c553 rev. <= 0x05"); 5083 sc->sc_dma_ok = 0; 5084 } else 5085 pciide_mapreg_dma(sc, pa); 5086 aprint_normal("\n"); 5087 5088 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 5089 WDC_CAPABILITY_MODE; 5090 sc->sc_wdcdev.PIO_cap = 4; 5091 if (sc->sc_dma_ok) { 5092 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 5093 sc->sc_wdcdev.irqack = pciide_irqack; 5094 sc->sc_wdcdev.DMA_cap = 2; 5095 } 5096 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 5097 5098 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5099 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5100 5101 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 5102 5103 interface = PCI_INTERFACE(pa->pa_class); 5104 5105 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5106 cp = &sc->pciide_channels[channel]; 5107 if (pciide_chansetup(sc, channel, interface) == 0) 5108 continue; 5109 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 5110 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 5111 aprint_normal("%s: %s channel ignored (disabled)\n", 5112 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 5113 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 5114 continue; 5115 } 5116 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5117 pciide_pci_intr); 5118 } 5119 } 5120 5121 void 5122 sl82c105_setup_channel(chp) 5123 struct channel_softc *chp; 5124 { 5125 struct ata_drive_datas *drvp; 5126 struct pciide_channel *cp = (struct pciide_channel*)chp; 5127 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5128 int pxdx_reg, drive; 5129 pcireg_t pxdx; 5130 5131 /* Set up DMA if needed. */ 5132 pciide_channel_dma_setup(cp); 5133 5134 for (drive = 0; drive < 2; drive++) { 5135 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 5136 : SYMPH_P1D0CR) + (drive * 4); 5137 5138 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 5139 5140 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 5141 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 5142 5143 drvp = &chp->ch_drive[drive]; 5144 /* If no drive, skip. */ 5145 if ((drvp->drive_flags & DRIVE) == 0) { 5146 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 5147 continue; 5148 } 5149 5150 if (drvp->drive_flags & DRIVE_DMA) { 5151 /* 5152 * Timings will be used for both PIO and DMA, 5153 * so adjust DMA mode if needed. 5154 */ 5155 if (drvp->PIO_mode >= 3) { 5156 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 5157 drvp->DMA_mode = drvp->PIO_mode - 2; 5158 if (drvp->DMA_mode < 1) { 5159 /* 5160 * Can't mix both PIO and DMA. 5161 * Disable DMA. 5162 */ 5163 drvp->drive_flags &= ~DRIVE_DMA; 5164 } 5165 } else { 5166 /* 5167 * Can't mix both PIO and DMA. Disable 5168 * DMA. 5169 */ 5170 drvp->drive_flags &= ~DRIVE_DMA; 5171 } 5172 } 5173 5174 if (drvp->drive_flags & DRIVE_DMA) { 5175 /* Use multi-word DMA. */ 5176 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 5177 PxDx_CMD_ON_SHIFT; 5178 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 5179 } else { 5180 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 5181 PxDx_CMD_ON_SHIFT; 5182 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 5183 } 5184 5185 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 5186 5187 /* ...and set the mode for this drive. */ 5188 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 5189 } 5190 } 5191 5192 void 5193 serverworks_chip_map(sc, pa) 5194 struct pciide_softc *sc; 5195 struct pci_attach_args *pa; 5196 { 5197 struct pciide_channel *cp; 5198 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 5199 pcitag_t pcib_tag; 5200 int channel; 5201 bus_size_t cmdsize, ctlsize; 5202 5203 if (pciide_chipen(sc, pa) == 0) 5204 return; 5205 5206 aprint_normal("%s: bus-master DMA support present", 5207 sc->sc_wdcdev.sc_dev.dv_xname); 5208 pciide_mapreg_dma(sc, pa); 5209 aprint_normal("\n"); 5210 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5211 WDC_CAPABILITY_MODE; 5212 5213 if (sc->sc_dma_ok) { 5214 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5215 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5216 sc->sc_wdcdev.irqack = pciide_irqack; 5217 } 5218 sc->sc_wdcdev.PIO_cap = 4; 5219 sc->sc_wdcdev.DMA_cap = 2; 5220 switch (sc->sc_pp->ide_product) { 5221 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 5222 sc->sc_wdcdev.UDMA_cap = 2; 5223 break; 5224 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 5225 if (PCI_REVISION(pa->pa_class) < 0x92) 5226 sc->sc_wdcdev.UDMA_cap = 4; 5227 else 5228 sc->sc_wdcdev.UDMA_cap = 5; 5229 break; 5230 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 5231 sc->sc_wdcdev.UDMA_cap = 5; 5232 break; 5233 } 5234 5235 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 5236 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5237 sc->sc_wdcdev.nchannels = 2; 5238 5239 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5240 cp = &sc->pciide_channels[channel]; 5241 if (pciide_chansetup(sc, channel, interface) == 0) 5242 continue; 5243 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5244 serverworks_pci_intr); 5245 } 5246 5247 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 5248 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 5249 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 5250 } 5251 5252 void 5253 serverworks_setup_channel(chp) 5254 struct channel_softc *chp; 5255 { 5256 struct ata_drive_datas *drvp; 5257 struct pciide_channel *cp = (struct pciide_channel*)chp; 5258 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 5259 int channel = chp->channel; 5260 int drive, unit; 5261 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 5262 u_int32_t idedma_ctl; 5263 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 5264 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 5265 5266 /* setup DMA if needed */ 5267 pciide_channel_dma_setup(cp); 5268 5269 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 5270 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 5271 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 5272 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 5273 5274 pio_time &= ~(0xffff << (16 * channel)); 5275 dma_time &= ~(0xffff << (16 * channel)); 5276 pio_mode &= ~(0xff << (8 * channel + 16)); 5277 udma_mode &= ~(0xff << (8 * channel + 16)); 5278 udma_mode &= ~(3 << (2 * channel)); 5279 5280 idedma_ctl = 0; 5281 5282 /* Per drive settings */ 5283 for (drive = 0; drive < 2; drive++) { 5284 drvp = &chp->ch_drive[drive]; 5285 /* If no drive, skip */ 5286 if ((drvp->drive_flags & DRIVE) == 0) 5287 continue; 5288 unit = drive + 2 * channel; 5289 /* add timing values, setup DMA if needed */ 5290 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 5291 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 5292 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 5293 (drvp->drive_flags & DRIVE_UDMA)) { 5294 /* use Ultra/DMA, check for 80-pin cable */ 5295 if (drvp->UDMA_mode > 2 && 5296 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 5297 drvp->UDMA_mode = 2; 5298 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 5299 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 5300 udma_mode |= 1 << unit; 5301 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5302 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 5303 (drvp->drive_flags & DRIVE_DMA)) { 5304 /* use Multiword DMA */ 5305 drvp->drive_flags &= ~DRIVE_UDMA; 5306 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 5307 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 5308 } else { 5309 /* PIO only */ 5310 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 5311 } 5312 } 5313 5314 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 5315 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 5316 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 5317 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 5318 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 5319 5320 if (idedma_ctl != 0) { 5321 /* Add software bits in status register */ 5322 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5323 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 5324 } 5325 } 5326 5327 int 5328 serverworks_pci_intr(arg) 5329 void *arg; 5330 { 5331 struct pciide_softc *sc = arg; 5332 struct pciide_channel *cp; 5333 struct channel_softc *wdc_cp; 5334 int rv = 0; 5335 int dmastat, i, crv; 5336 5337 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 5338 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5339 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 5340 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 5341 IDEDMA_CTL_INTR) 5342 continue; 5343 cp = &sc->pciide_channels[i]; 5344 wdc_cp = &cp->wdc_channel; 5345 crv = wdcintr(wdc_cp); 5346 if (crv == 0) { 5347 printf("%s:%d: bogus intr\n", 5348 sc->sc_wdcdev.sc_dev.dv_xname, i); 5349 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 5350 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 5351 } else 5352 rv = 1; 5353 } 5354 return rv; 5355 } 5356 5357 void 5358 artisea_chip_map(sc, pa) 5359 struct pciide_softc *sc; 5360 struct pci_attach_args *pa; 5361 { 5362 struct pciide_channel *cp; 5363 bus_size_t cmdsize, ctlsize; 5364 pcireg_t interface; 5365 int channel; 5366 5367 if (pciide_chipen(sc, pa) == 0) 5368 return; 5369 5370 aprint_normal("%s: bus-master DMA support present", 5371 sc->sc_wdcdev.sc_dev.dv_xname); 5372 #ifndef PCIIDE_I31244_ENABLEDMA 5373 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 && 5374 PCI_REVISION(pa->pa_class) == 0) { 5375 aprint_normal(" but disabled due to rev. 0"); 5376 sc->sc_dma_ok = 0; 5377 } else 5378 #endif 5379 pciide_mapreg_dma(sc, pa); 5380 aprint_normal("\n"); 5381 5382 /* 5383 * XXX Configure LEDs to show activity. 5384 */ 5385 5386 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 5387 WDC_CAPABILITY_MODE; 5388 sc->sc_wdcdev.PIO_cap = 4; 5389 if (sc->sc_dma_ok) { 5390 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 5391 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 5392 sc->sc_wdcdev.irqack = pciide_irqack; 5393 sc->sc_wdcdev.DMA_cap = 2; 5394 sc->sc_wdcdev.UDMA_cap = 6; 5395 } 5396 sc->sc_wdcdev.set_modes = sata_setup_channel; 5397 5398 sc->sc_wdcdev.channels = sc->wdc_chanarray; 5399 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 5400 5401 interface = PCI_INTERFACE(pa->pa_class); 5402 5403 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 5404 cp = &sc->pciide_channels[channel]; 5405 if (pciide_chansetup(sc, channel, interface) == 0) 5406 continue; 5407 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 5408 pciide_pci_intr); 5409 } 5410 } 5411
Indexes created Thu Oct 02 10:09:58 GMT 2025