pciide.c revision 1.33.2.6
1 /* $NetBSD: pciide.c,v 1.33.2.6 2000/07/23 17:29:08 he Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <vm/vm.h> 102 #include <vm/vm_param.h> 103 #include <vm/vm_kern.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 121 #if BYTE_ORDER == BIG_ENDIAN 122 #define htole16(x) bswap16((u_int16_t)(x)) 123 #define htole32(x) bswap32((u_int32_t)(x)) 124 #define htole64(x) bswap64((u_int64_t)(x)) 125 #else /* LITTLE_ENDIAN */ 126 #define htole16(x) (x) 127 #define htole32(x) (x) 128 #define htole64(x) (x) 129 #endif 130 #define le16toh(x) htole16(x) 131 #define le32toh(x) htole32(x) 132 #define le64toh(x) htole64(x) 133 134 /* inlines for reading/writing 8-bit PCI registers */ 135 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 136 int)); 137 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 138 int, u_int8_t)); 139 140 static __inline u_int8_t 141 pciide_pci_read(pc, pa, reg) 142 pci_chipset_tag_t pc; 143 pcitag_t pa; 144 int reg; 145 { 146 147 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 148 ((reg & 0x03) * 8) & 0xff); 149 } 150 151 static __inline void 152 pciide_pci_write(pc, pa, reg, val) 153 pci_chipset_tag_t pc; 154 pcitag_t pa; 155 int reg; 156 u_int8_t val; 157 { 158 pcireg_t pcival; 159 160 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 161 pcival &= ~(0xff << ((reg & 0x03) * 8)); 162 pcival |= (val << ((reg & 0x03) * 8)); 163 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 164 } 165 166 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 167 168 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 169 void piix_setup_channel __P((struct channel_softc*)); 170 void piix3_4_setup_channel __P((struct channel_softc*)); 171 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 172 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 173 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 174 175 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 176 void amd756_setup_channel __P((struct channel_softc*)); 177 178 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 179 void apollo_setup_channel __P((struct channel_softc*)); 180 181 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 183 void cmd0643_9_setup_channel __P((struct channel_softc*)); 184 void cmd_channel_map __P((struct pci_attach_args *, 185 struct pciide_softc *, int)); 186 int cmd_pci_intr __P((void *)); 187 void cmd648_9_irqack __P((struct channel_softc *)); 188 189 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 190 void cy693_setup_channel __P((struct channel_softc*)); 191 192 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void sis_setup_channel __P((struct channel_softc*)); 194 195 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 196 void acer_setup_channel __P((struct channel_softc*)); 197 int acer_pci_intr __P((void *)); 198 199 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 200 void pdc202xx_setup_channel __P((struct channel_softc*)); 201 int pdc202xx_pci_intr __P((void *)); 202 203 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 204 void opti_setup_channel __P((struct channel_softc*)); 205 206 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 207 void hpt_setup_channel __P((struct channel_softc*)); 208 int hpt_pci_intr __P((void *)); 209 210 void pciide_channel_dma_setup __P((struct pciide_channel *)); 211 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 212 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 213 void pciide_dma_start __P((void*, int, int)); 214 int pciide_dma_finish __P((void*, int, int, int)); 215 void pciide_irqack __P((struct channel_softc *)); 216 void pciide_print_modes __P((struct pciide_channel *)); 217 218 struct pciide_product_desc { 219 u_int32_t ide_product; 220 int ide_flags; 221 const char *ide_name; 222 /* map and setup chip, probe drives */ 223 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 224 }; 225 226 /* Flags for ide_flags */ 227 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 228 229 /* Default product description for devices not known from this controller */ 230 const struct pciide_product_desc default_product_desc = { 231 0, 232 0, 233 "Generic PCI IDE controller", 234 default_chip_map, 235 }; 236 237 const struct pciide_product_desc pciide_intel_products[] = { 238 { PCI_PRODUCT_INTEL_82092AA, 239 0, 240 "Intel 82092AA IDE controller", 241 default_chip_map, 242 }, 243 { PCI_PRODUCT_INTEL_82371FB_IDE, 244 0, 245 "Intel 82371FB IDE controller (PIIX)", 246 piix_chip_map, 247 }, 248 { PCI_PRODUCT_INTEL_82371SB_IDE, 249 0, 250 "Intel 82371SB IDE Interface (PIIX3)", 251 piix_chip_map, 252 }, 253 { PCI_PRODUCT_INTEL_82371AB_IDE, 254 0, 255 "Intel 82371AB IDE controller (PIIX4)", 256 piix_chip_map, 257 }, 258 { PCI_PRODUCT_INTEL_82801AA_IDE, 259 0, 260 "Intel 82801AA IDE Controller (ICH)", 261 piix_chip_map, 262 }, 263 { PCI_PRODUCT_INTEL_82801AB_IDE, 264 0, 265 "Intel 82801AB IDE Controller (ICH0)", 266 piix_chip_map, 267 }, 268 { 0, 269 0, 270 NULL, 271 } 272 }; 273 274 const struct pciide_product_desc pciide_amd_products[] = { 275 { PCI_PRODUCT_AMD_PBC756_IDE, 276 0, 277 "Advanced Micro Devices AMD756 IDE Controller", 278 amd756_chip_map 279 }, 280 { 0, 281 0, 282 NULL, 283 } 284 }; 285 286 const struct pciide_product_desc pciide_cmd_products[] = { 287 { PCI_PRODUCT_CMDTECH_640, 288 0, 289 "CMD Technology PCI0640", 290 cmd_chip_map 291 }, 292 { PCI_PRODUCT_CMDTECH_643, 293 0, 294 "CMD Technology PCI0643", 295 cmd0643_9_chip_map, 296 }, 297 { PCI_PRODUCT_CMDTECH_646, 298 0, 299 "CMD Technology PCI0646", 300 cmd0643_9_chip_map, 301 }, 302 { PCI_PRODUCT_CMDTECH_648, 303 IDE_PCI_CLASS_OVERRIDE, 304 "CMD Technology PCI0648", 305 cmd0643_9_chip_map, 306 }, 307 { PCI_PRODUCT_CMDTECH_649, 308 IDE_PCI_CLASS_OVERRIDE, 309 "CMD Technology PCI0649", 310 cmd0643_9_chip_map, 311 }, 312 { 0, 313 0, 314 NULL, 315 } 316 }; 317 318 const struct pciide_product_desc pciide_via_products[] = { 319 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 320 0, 321 "VIA Tech VT82C586 IDE Controller", 322 apollo_chip_map, 323 }, 324 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 325 0, 326 "VIA Tech VT82C586A IDE Controller", 327 apollo_chip_map, 328 }, 329 { 0, 330 0, 331 NULL, 332 } 333 }; 334 335 const struct pciide_product_desc pciide_cypress_products[] = { 336 { PCI_PRODUCT_CONTAQ_82C693, 337 0, 338 "Cypress 82C693 IDE Controller", 339 cy693_chip_map, 340 }, 341 { 0, 342 0, 343 NULL, 344 } 345 }; 346 347 const struct pciide_product_desc pciide_sis_products[] = { 348 { PCI_PRODUCT_SIS_5597_IDE, 349 0, 350 "Silicon Integrated System 5597/5598 IDE controller", 351 sis_chip_map, 352 }, 353 { 0, 354 0, 355 NULL, 356 } 357 }; 358 359 const struct pciide_product_desc pciide_acer_products[] = { 360 { PCI_PRODUCT_ALI_M5229, 361 0, 362 "Acer Labs M5229 UDMA IDE Controller", 363 acer_chip_map, 364 }, 365 { 0, 366 0, 367 NULL, 368 } 369 }; 370 371 const struct pciide_product_desc pciide_promise_products[] = { 372 { PCI_PRODUCT_PROMISE_ULTRA33, 373 IDE_PCI_CLASS_OVERRIDE, 374 "Promise Ultra33/ATA Bus Master IDE Accelerator", 375 pdc202xx_chip_map, 376 }, 377 { PCI_PRODUCT_PROMISE_ULTRA66, 378 IDE_PCI_CLASS_OVERRIDE, 379 "Promise Ultra66/ATA Bus Master IDE Accelerator", 380 pdc202xx_chip_map, 381 }, 382 { PCI_PRODUCT_PROMISE_ULTRA100, 383 IDE_PCI_CLASS_OVERRIDE, 384 "Promise Ultra100/ATA Bus Master IDE Accelerator", 385 pdc202xx_chip_map, 386 }, 387 { 0, 388 0, 389 NULL, 390 } 391 }; 392 393 const struct pciide_product_desc pciide_opti_products[] = { 394 { PCI_PRODUCT_OPTI_82C621, 395 0, 396 "OPTi 82c621 PCI IDE controller", 397 opti_chip_map, 398 }, 399 { PCI_PRODUCT_OPTI_82C568, 400 0, 401 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 402 opti_chip_map, 403 }, 404 { PCI_PRODUCT_OPTI_82D568, 405 0, 406 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 407 opti_chip_map, 408 }, 409 { 0, 410 0, 411 NULL, 412 } 413 }; 414 415 const struct pciide_product_desc pciide_triones_products[] = { 416 { PCI_PRODUCT_TRIONES_HPT366, 417 IDE_PCI_CLASS_OVERRIDE, 418 "Triones/Highpoint HPT366/370 IDE Controller", 419 hpt_chip_map, 420 }, 421 { 0, 422 0, 423 NULL, 424 } 425 }; 426 427 struct pciide_vendor_desc { 428 u_int32_t ide_vendor; 429 const struct pciide_product_desc *ide_products; 430 }; 431 432 const struct pciide_vendor_desc pciide_vendors[] = { 433 { PCI_VENDOR_INTEL, pciide_intel_products }, 434 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 435 { PCI_VENDOR_VIATECH, pciide_via_products }, 436 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 437 { PCI_VENDOR_SIS, pciide_sis_products }, 438 { PCI_VENDOR_ALI, pciide_acer_products }, 439 { PCI_VENDOR_PROMISE, pciide_promise_products }, 440 { PCI_VENDOR_AMD, pciide_amd_products }, 441 { PCI_VENDOR_OPTI, pciide_opti_products }, 442 { PCI_VENDOR_TRIONES, pciide_triones_products }, 443 { 0, NULL } 444 }; 445 446 /* options passed via the 'flags' config keyword */ 447 #define PCIIDE_OPTIONS_DMA 0x01 448 449 int pciide_match __P((struct device *, struct cfdata *, void *)); 450 void pciide_attach __P((struct device *, struct device *, void *)); 451 452 struct cfattach pciide_ca = { 453 sizeof(struct pciide_softc), pciide_match, pciide_attach 454 }; 455 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 456 int pciide_mapregs_compat __P(( struct pci_attach_args *, 457 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 458 int pciide_mapregs_native __P((struct pci_attach_args *, 459 struct pciide_channel *, bus_size_t *, bus_size_t *, 460 int (*pci_intr) __P((void *)))); 461 void pciide_mapreg_dma __P((struct pciide_softc *, 462 struct pci_attach_args *)); 463 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 464 void pciide_mapchan __P((struct pci_attach_args *, 465 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 466 int (*pci_intr) __P((void *)))); 467 int pciide_chan_candisable __P((struct pciide_channel *)); 468 void pciide_map_compat_intr __P(( struct pci_attach_args *, 469 struct pciide_channel *, int, int)); 470 int pciide_print __P((void *, const char *pnp)); 471 int pciide_compat_intr __P((void *)); 472 int pciide_pci_intr __P((void *)); 473 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 474 475 const struct pciide_product_desc * 476 pciide_lookup_product(id) 477 u_int32_t id; 478 { 479 const struct pciide_product_desc *pp; 480 const struct pciide_vendor_desc *vp; 481 482 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 483 if (PCI_VENDOR(id) == vp->ide_vendor) 484 break; 485 486 if ((pp = vp->ide_products) == NULL) 487 return NULL; 488 489 for (; pp->ide_name != NULL; pp++) 490 if (PCI_PRODUCT(id) == pp->ide_product) 491 break; 492 493 if (pp->ide_name == NULL) 494 return NULL; 495 return pp; 496 } 497 498 int 499 pciide_match(parent, match, aux) 500 struct device *parent; 501 struct cfdata *match; 502 void *aux; 503 { 504 struct pci_attach_args *pa = aux; 505 const struct pciide_product_desc *pp; 506 507 /* 508 * Check the ID register to see that it's a PCI IDE controller. 509 * If it is, we assume that we can deal with it; it _should_ 510 * work in a standardized way... 511 */ 512 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 513 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 514 return (1); 515 } 516 517 /* 518 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 519 * controllers. Let see if we can deal with it anyway. 520 */ 521 pp = pciide_lookup_product(pa->pa_id); 522 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 523 return (1); 524 } 525 526 return (0); 527 } 528 529 void 530 pciide_attach(parent, self, aux) 531 struct device *parent, *self; 532 void *aux; 533 { 534 struct pci_attach_args *pa = aux; 535 pci_chipset_tag_t pc = pa->pa_pc; 536 pcitag_t tag = pa->pa_tag; 537 struct pciide_softc *sc = (struct pciide_softc *)self; 538 pcireg_t csr; 539 char devinfo[256]; 540 const char *displaydev; 541 542 sc->sc_pp = pciide_lookup_product(pa->pa_id); 543 if (sc->sc_pp == NULL) { 544 sc->sc_pp = &default_product_desc; 545 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 546 displaydev = devinfo; 547 } else 548 displaydev = sc->sc_pp->ide_name; 549 550 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 551 552 sc->sc_pc = pa->pa_pc; 553 sc->sc_tag = pa->pa_tag; 554 #ifdef WDCDEBUG 555 if (wdcdebug_pciide_mask & DEBUG_PROBE) 556 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 557 #endif 558 sc->sc_pp->chip_map(sc, pa); 559 560 if (sc->sc_dma_ok) { 561 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 562 csr |= PCI_COMMAND_MASTER_ENABLE; 563 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 564 } 565 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 566 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 567 } 568 569 /* tell wether the chip is enabled or not */ 570 int 571 pciide_chipen(sc, pa) 572 struct pciide_softc *sc; 573 struct pci_attach_args *pa; 574 { 575 pcireg_t csr; 576 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 577 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 578 PCI_COMMAND_STATUS_REG); 579 printf("%s: device disabled (at %s)\n", 580 sc->sc_wdcdev.sc_dev.dv_xname, 581 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 582 "device" : "bridge"); 583 return 0; 584 } 585 return 1; 586 } 587 588 int 589 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 590 struct pci_attach_args *pa; 591 struct pciide_channel *cp; 592 int compatchan; 593 bus_size_t *cmdsizep, *ctlsizep; 594 { 595 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 596 struct channel_softc *wdc_cp = &cp->wdc_channel; 597 598 cp->compat = 1; 599 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 600 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 601 602 wdc_cp->cmd_iot = pa->pa_iot; 603 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 604 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 605 printf("%s: couldn't map %s channel cmd regs\n", 606 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 607 return (0); 608 } 609 610 wdc_cp->ctl_iot = pa->pa_iot; 611 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 612 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 613 printf("%s: couldn't map %s channel ctl regs\n", 614 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 615 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 616 PCIIDE_COMPAT_CMD_SIZE); 617 return (0); 618 } 619 620 return (1); 621 } 622 623 int 624 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 625 struct pci_attach_args * pa; 626 struct pciide_channel *cp; 627 bus_size_t *cmdsizep, *ctlsizep; 628 int (*pci_intr) __P((void *)); 629 { 630 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 631 struct channel_softc *wdc_cp = &cp->wdc_channel; 632 const char *intrstr; 633 pci_intr_handle_t intrhandle; 634 635 cp->compat = 0; 636 637 if (sc->sc_pci_ih == NULL) { 638 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 639 pa->pa_intrline, &intrhandle) != 0) { 640 printf("%s: couldn't map native-PCI interrupt\n", 641 sc->sc_wdcdev.sc_dev.dv_xname); 642 return 0; 643 } 644 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 645 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 646 intrhandle, IPL_BIO, pci_intr, sc); 647 if (sc->sc_pci_ih != NULL) { 648 printf("%s: using %s for native-PCI interrupt\n", 649 sc->sc_wdcdev.sc_dev.dv_xname, 650 intrstr ? intrstr : "unknown interrupt"); 651 } else { 652 printf("%s: couldn't establish native-PCI interrupt", 653 sc->sc_wdcdev.sc_dev.dv_xname); 654 if (intrstr != NULL) 655 printf(" at %s", intrstr); 656 printf("\n"); 657 return 0; 658 } 659 } 660 cp->ih = sc->sc_pci_ih; 661 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 662 PCI_MAPREG_TYPE_IO, 0, 663 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 664 printf("%s: couldn't map %s channel cmd regs\n", 665 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 666 return 0; 667 } 668 669 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 670 PCI_MAPREG_TYPE_IO, 0, 671 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 672 printf("%s: couldn't map %s channel ctl regs\n", 673 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 674 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 675 return 0; 676 } 677 return (1); 678 } 679 680 void 681 pciide_mapreg_dma(sc, pa) 682 struct pciide_softc *sc; 683 struct pci_attach_args *pa; 684 { 685 /* 686 * Map DMA registers 687 * 688 * Note that sc_dma_ok is the right variable to test to see if 689 * DMA can be done. If the interface doesn't support DMA, 690 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 691 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 692 * non-zero if the interface supports DMA and the registers 693 * could be mapped. 694 * 695 * XXX Note that despite the fact that the Bus Master IDE specs 696 * XXX say that "The bus master IDE function uses 16 bytes of IO 697 * XXX space," some controllers (at least the United 698 * XXX Microelectronics UM8886BF) place it in memory space. 699 */ 700 sc->sc_dma_ok = (pci_mapreg_map(pa, 701 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0, 702 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 703 sc->sc_dmat = pa->pa_dmat; 704 if (sc->sc_dma_ok == 0) { 705 printf(", but unused (couldn't map registers)"); 706 } else { 707 sc->sc_wdcdev.dma_arg = sc; 708 sc->sc_wdcdev.dma_init = pciide_dma_init; 709 sc->sc_wdcdev.dma_start = pciide_dma_start; 710 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 711 } 712 } 713 714 int 715 pciide_compat_intr(arg) 716 void *arg; 717 { 718 struct pciide_channel *cp = arg; 719 720 #ifdef DIAGNOSTIC 721 /* should only be called for a compat channel */ 722 if (cp->compat == 0) 723 panic("pciide compat intr called for non-compat chan %p\n", cp); 724 #endif 725 return (wdcintr(&cp->wdc_channel)); 726 } 727 728 int 729 pciide_pci_intr(arg) 730 void *arg; 731 { 732 struct pciide_softc *sc = arg; 733 struct pciide_channel *cp; 734 struct channel_softc *wdc_cp; 735 int i, rv, crv; 736 737 rv = 0; 738 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 739 cp = &sc->pciide_channels[i]; 740 wdc_cp = &cp->wdc_channel; 741 742 /* If a compat channel skip. */ 743 if (cp->compat) 744 continue; 745 /* if this channel not waiting for intr, skip */ 746 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 747 continue; 748 749 crv = wdcintr(wdc_cp); 750 if (crv == 0) 751 ; /* leave rv alone */ 752 else if (crv == 1) 753 rv = 1; /* claim the intr */ 754 else if (rv == 0) /* crv should be -1 in this case */ 755 rv = crv; /* if we've done no better, take it */ 756 } 757 return (rv); 758 } 759 760 void 761 pciide_channel_dma_setup(cp) 762 struct pciide_channel *cp; 763 { 764 int drive; 765 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 766 struct ata_drive_datas *drvp; 767 768 for (drive = 0; drive < 2; drive++) { 769 drvp = &cp->wdc_channel.ch_drive[drive]; 770 /* If no drive, skip */ 771 if ((drvp->drive_flags & DRIVE) == 0) 772 continue; 773 /* setup DMA if needed */ 774 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 775 (drvp->drive_flags & DRIVE_UDMA) == 0) || 776 sc->sc_dma_ok == 0) { 777 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 778 continue; 779 } 780 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 781 != 0) { 782 /* Abort DMA setup */ 783 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 784 continue; 785 } 786 } 787 } 788 789 int 790 pciide_dma_table_setup(sc, channel, drive) 791 struct pciide_softc *sc; 792 int channel, drive; 793 { 794 bus_dma_segment_t seg; 795 int error, rseg; 796 const bus_size_t dma_table_size = 797 sizeof(struct idedma_table) * NIDEDMA_TABLES; 798 struct pciide_dma_maps *dma_maps = 799 &sc->pciide_channels[channel].dma_maps[drive]; 800 801 /* If table was already allocated, just return */ 802 if (dma_maps->dma_table) 803 return 0; 804 805 /* Allocate memory for the DMA tables and map it */ 806 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 807 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 808 BUS_DMA_NOWAIT)) != 0) { 809 printf("%s:%d: unable to allocate table DMA for " 810 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 811 channel, drive, error); 812 return error; 813 } 814 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 815 dma_table_size, 816 (caddr_t *)&dma_maps->dma_table, 817 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 818 printf("%s:%d: unable to map table DMA for" 819 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 820 channel, drive, error); 821 return error; 822 } 823 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 824 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 825 seg.ds_addr), DEBUG_PROBE); 826 827 /* Create and load table DMA map for this disk */ 828 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 829 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 830 &dma_maps->dmamap_table)) != 0) { 831 printf("%s:%d: unable to create table DMA map for " 832 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 833 channel, drive, error); 834 return error; 835 } 836 if ((error = bus_dmamap_load(sc->sc_dmat, 837 dma_maps->dmamap_table, 838 dma_maps->dma_table, 839 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 840 printf("%s:%d: unable to load table DMA map for " 841 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 842 channel, drive, error); 843 return error; 844 } 845 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 846 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 847 /* Create a xfer DMA map for this drive */ 848 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 849 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 850 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 851 &dma_maps->dmamap_xfer)) != 0) { 852 printf("%s:%d: unable to create xfer DMA map for " 853 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 854 channel, drive, error); 855 return error; 856 } 857 return 0; 858 } 859 860 int 861 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 862 void *v; 863 int channel, drive; 864 void *databuf; 865 size_t datalen; 866 int flags; 867 { 868 struct pciide_softc *sc = v; 869 int error, seg; 870 struct pciide_dma_maps *dma_maps = 871 &sc->pciide_channels[channel].dma_maps[drive]; 872 873 error = bus_dmamap_load(sc->sc_dmat, 874 dma_maps->dmamap_xfer, 875 databuf, datalen, NULL, BUS_DMA_NOWAIT); 876 if (error) { 877 printf("%s:%d: unable to load xfer DMA map for" 878 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 879 channel, drive, error); 880 return error; 881 } 882 883 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 884 dma_maps->dmamap_xfer->dm_mapsize, 885 (flags & WDC_DMA_READ) ? 886 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 887 888 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 889 #ifdef DIAGNOSTIC 890 /* A segment must not cross a 64k boundary */ 891 { 892 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 893 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 894 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 895 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 896 printf("pciide_dma: segment %d physical addr 0x%lx" 897 " len 0x%lx not properly aligned\n", 898 seg, phys, len); 899 panic("pciide_dma: buf align"); 900 } 901 } 902 #endif 903 dma_maps->dma_table[seg].base_addr = 904 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 905 dma_maps->dma_table[seg].byte_count = 906 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 907 IDEDMA_BYTE_COUNT_MASK); 908 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 909 seg, le32toh(dma_maps->dma_table[seg].byte_count), 910 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 911 912 } 913 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 914 htole32(IDEDMA_BYTE_COUNT_EOT); 915 916 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 917 dma_maps->dmamap_table->dm_mapsize, 918 BUS_DMASYNC_PREWRITE); 919 920 /* Maps are ready. Start DMA function */ 921 #ifdef DIAGNOSTIC 922 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 923 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 924 dma_maps->dmamap_table->dm_segs[0].ds_addr); 925 panic("pciide_dma_init: table align"); 926 } 927 #endif 928 929 /* Clear status bits */ 930 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 931 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 932 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 933 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 934 /* Write table addr */ 935 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 936 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 937 dma_maps->dmamap_table->dm_segs[0].ds_addr); 938 /* set read/write */ 939 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 940 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 941 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 942 /* remember flags */ 943 dma_maps->dma_flags = flags; 944 return 0; 945 } 946 947 void 948 pciide_dma_start(v, channel, drive) 949 void *v; 950 int channel, drive; 951 { 952 struct pciide_softc *sc = v; 953 954 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 955 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 956 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 957 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 958 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 959 } 960 961 int 962 pciide_dma_finish(v, channel, drive, force) 963 void *v; 964 int channel, drive; 965 int force; 966 { 967 struct pciide_softc *sc = v; 968 u_int8_t status; 969 int error = 0; 970 struct pciide_dma_maps *dma_maps = 971 &sc->pciide_channels[channel].dma_maps[drive]; 972 973 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 974 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 975 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 976 DEBUG_XFERS); 977 978 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 979 return WDC_DMAST_NOIRQ; 980 981 /* stop DMA channel */ 982 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 983 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 984 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 985 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 986 987 /* Unload the map of the data buffer */ 988 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 989 dma_maps->dmamap_xfer->dm_mapsize, 990 (dma_maps->dma_flags & WDC_DMA_READ) ? 991 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 992 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 993 994 if ((status & IDEDMA_CTL_ERR) != 0) { 995 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 996 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 997 error |= WDC_DMAST_ERR; 998 } 999 1000 if ((status & IDEDMA_CTL_INTR) == 0) { 1001 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1002 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1003 drive, status); 1004 error |= WDC_DMAST_NOIRQ; 1005 } 1006 1007 if ((status & IDEDMA_CTL_ACT) != 0) { 1008 /* data underrun, may be a valid condition for ATAPI */ 1009 error |= WDC_DMAST_UNDER; 1010 } 1011 return error; 1012 } 1013 1014 void 1015 pciide_irqack(chp) 1016 struct channel_softc *chp; 1017 { 1018 struct pciide_channel *cp = (struct pciide_channel*)chp; 1019 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1020 1021 /* clear status bits in IDE DMA registers */ 1022 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1023 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1024 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1025 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1026 } 1027 1028 /* some common code used by several chip_map */ 1029 int 1030 pciide_chansetup(sc, channel, interface) 1031 struct pciide_softc *sc; 1032 int channel; 1033 pcireg_t interface; 1034 { 1035 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1036 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1037 cp->name = PCIIDE_CHANNEL_NAME(channel); 1038 cp->wdc_channel.channel = channel; 1039 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1040 cp->wdc_channel.ch_queue = 1041 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1042 if (cp->wdc_channel.ch_queue == NULL) { 1043 printf("%s %s channel: " 1044 "can't allocate memory for command queue", 1045 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1046 return 0; 1047 } 1048 printf("%s: %s channel %s to %s mode\n", 1049 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1050 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1051 "configured" : "wired", 1052 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1053 "native-PCI" : "compatibility"); 1054 return 1; 1055 } 1056 1057 /* some common code used by several chip channel_map */ 1058 void 1059 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1060 struct pci_attach_args *pa; 1061 struct pciide_channel *cp; 1062 pcireg_t interface; 1063 bus_size_t *cmdsizep, *ctlsizep; 1064 int (*pci_intr) __P((void *)); 1065 { 1066 struct channel_softc *wdc_cp = &cp->wdc_channel; 1067 1068 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1069 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1070 pci_intr); 1071 else 1072 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1073 wdc_cp->channel, cmdsizep, ctlsizep); 1074 1075 if (cp->hw_ok == 0) 1076 return; 1077 wdc_cp->data32iot = wdc_cp->cmd_iot; 1078 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1079 wdcattach(wdc_cp); 1080 } 1081 1082 /* 1083 * Generic code to call to know if a channel can be disabled. Return 1 1084 * if channel can be disabled, 0 if not 1085 */ 1086 int 1087 pciide_chan_candisable(cp) 1088 struct pciide_channel *cp; 1089 { 1090 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1091 struct channel_softc *wdc_cp = &cp->wdc_channel; 1092 1093 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1094 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1095 printf("%s: disabling %s channel (no drives)\n", 1096 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1097 cp->hw_ok = 0; 1098 return 1; 1099 } 1100 return 0; 1101 } 1102 1103 /* 1104 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1105 * Set hw_ok=0 on failure 1106 */ 1107 void 1108 pciide_map_compat_intr(pa, cp, compatchan, interface) 1109 struct pci_attach_args *pa; 1110 struct pciide_channel *cp; 1111 int compatchan, interface; 1112 { 1113 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1114 struct channel_softc *wdc_cp = &cp->wdc_channel; 1115 1116 if (cp->hw_ok == 0) 1117 return; 1118 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1119 return; 1120 1121 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1122 pa, compatchan, pciide_compat_intr, cp); 1123 if (cp->ih == NULL) { 1124 printf("%s: no compatibility interrupt for use by %s " 1125 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1126 cp->hw_ok = 0; 1127 } 1128 } 1129 1130 void 1131 pciide_print_modes(cp) 1132 struct pciide_channel *cp; 1133 { 1134 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1135 int drive; 1136 struct channel_softc *chp; 1137 struct ata_drive_datas *drvp; 1138 1139 chp = &cp->wdc_channel; 1140 for (drive = 0; drive < 2; drive++) { 1141 drvp = &chp->ch_drive[drive]; 1142 if ((drvp->drive_flags & DRIVE) == 0) 1143 continue; 1144 printf("%s(%s:%d:%d): using PIO mode %d", 1145 drvp->drv_softc->dv_xname, 1146 sc->sc_wdcdev.sc_dev.dv_xname, 1147 chp->channel, drive, drvp->PIO_mode); 1148 if (drvp->drive_flags & DRIVE_DMA) 1149 printf(", DMA mode %d", drvp->DMA_mode); 1150 if (drvp->drive_flags & DRIVE_UDMA) 1151 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1152 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1153 printf(" (using DMA data transfers)"); 1154 printf("\n"); 1155 } 1156 } 1157 1158 void 1159 default_chip_map(sc, pa) 1160 struct pciide_softc *sc; 1161 struct pci_attach_args *pa; 1162 { 1163 struct pciide_channel *cp; 1164 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1165 pcireg_t csr; 1166 int channel, drive; 1167 struct ata_drive_datas *drvp; 1168 u_int8_t idedma_ctl; 1169 bus_size_t cmdsize, ctlsize; 1170 char *failreason; 1171 1172 if (pciide_chipen(sc, pa) == 0) 1173 return; 1174 1175 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1176 printf("%s: bus-master DMA support present", 1177 sc->sc_wdcdev.sc_dev.dv_xname); 1178 if (sc->sc_pp == &default_product_desc && 1179 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1180 PCIIDE_OPTIONS_DMA) == 0) { 1181 printf(", but unused (no driver support)"); 1182 sc->sc_dma_ok = 0; 1183 } else { 1184 pciide_mapreg_dma(sc, pa); 1185 if (sc->sc_dma_ok != 0) 1186 printf(", used without full driver " 1187 "support"); 1188 } 1189 } else { 1190 printf("%s: hardware does not support DMA", 1191 sc->sc_wdcdev.sc_dev.dv_xname); 1192 sc->sc_dma_ok = 0; 1193 } 1194 printf("\n"); 1195 if (sc->sc_dma_ok) { 1196 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1197 sc->sc_wdcdev.irqack = pciide_irqack; 1198 } 1199 sc->sc_wdcdev.PIO_cap = 0; 1200 sc->sc_wdcdev.DMA_cap = 0; 1201 1202 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1203 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1204 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1205 1206 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1207 cp = &sc->pciide_channels[channel]; 1208 if (pciide_chansetup(sc, channel, interface) == 0) 1209 continue; 1210 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1211 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1212 &ctlsize, pciide_pci_intr); 1213 } else { 1214 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1215 channel, &cmdsize, &ctlsize); 1216 } 1217 if (cp->hw_ok == 0) 1218 continue; 1219 /* 1220 * Check to see if something appears to be there. 1221 */ 1222 failreason = NULL; 1223 if (!wdcprobe(&cp->wdc_channel)) { 1224 failreason = "not responding; disabled or no drives?"; 1225 goto next; 1226 } 1227 /* 1228 * Now, make sure it's actually attributable to this PCI IDE 1229 * channel by trying to access the channel again while the 1230 * PCI IDE controller's I/O space is disabled. (If the 1231 * channel no longer appears to be there, it belongs to 1232 * this controller.) YUCK! 1233 */ 1234 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1235 PCI_COMMAND_STATUS_REG); 1236 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1237 csr & ~PCI_COMMAND_IO_ENABLE); 1238 if (wdcprobe(&cp->wdc_channel)) 1239 failreason = "other hardware responding at addresses"; 1240 pci_conf_write(sc->sc_pc, sc->sc_tag, 1241 PCI_COMMAND_STATUS_REG, csr); 1242 next: 1243 if (failreason) { 1244 printf("%s: %s channel ignored (%s)\n", 1245 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1246 failreason); 1247 cp->hw_ok = 0; 1248 bus_space_unmap(cp->wdc_channel.cmd_iot, 1249 cp->wdc_channel.cmd_ioh, cmdsize); 1250 bus_space_unmap(cp->wdc_channel.ctl_iot, 1251 cp->wdc_channel.ctl_ioh, ctlsize); 1252 } else { 1253 pciide_map_compat_intr(pa, cp, channel, interface); 1254 } 1255 if (cp->hw_ok) { 1256 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1257 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1258 wdcattach(&cp->wdc_channel); 1259 } 1260 } 1261 1262 if (sc->sc_dma_ok == 0) 1263 return; 1264 1265 /* Allocate DMA maps */ 1266 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1267 idedma_ctl = 0; 1268 cp = &sc->pciide_channels[channel]; 1269 for (drive = 0; drive < 2; drive++) { 1270 drvp = &cp->wdc_channel.ch_drive[drive]; 1271 /* If no drive, skip */ 1272 if ((drvp->drive_flags & DRIVE) == 0) 1273 continue; 1274 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1275 continue; 1276 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1277 /* Abort DMA setup */ 1278 printf("%s:%d:%d: can't allocate DMA maps, " 1279 "using PIO transfers\n", 1280 sc->sc_wdcdev.sc_dev.dv_xname, 1281 channel, drive); 1282 drvp->drive_flags &= ~DRIVE_DMA; 1283 } 1284 printf("%s:%d:%d: using DMA data transfers\n", 1285 sc->sc_wdcdev.sc_dev.dv_xname, 1286 channel, drive); 1287 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1288 } 1289 if (idedma_ctl != 0) { 1290 /* Add software bits in status register */ 1291 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1292 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1293 idedma_ctl); 1294 } 1295 } 1296 } 1297 1298 void 1299 piix_chip_map(sc, pa) 1300 struct pciide_softc *sc; 1301 struct pci_attach_args *pa; 1302 { 1303 struct pciide_channel *cp; 1304 int channel; 1305 u_int32_t idetim; 1306 bus_size_t cmdsize, ctlsize; 1307 1308 if (pciide_chipen(sc, pa) == 0) 1309 return; 1310 1311 printf("%s: bus-master DMA support present", 1312 sc->sc_wdcdev.sc_dev.dv_xname); 1313 pciide_mapreg_dma(sc, pa); 1314 printf("\n"); 1315 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1316 WDC_CAPABILITY_MODE; 1317 if (sc->sc_dma_ok) { 1318 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1319 sc->sc_wdcdev.irqack = pciide_irqack; 1320 switch(sc->sc_pp->ide_product) { 1321 case PCI_PRODUCT_INTEL_82371AB_IDE: 1322 case PCI_PRODUCT_INTEL_82801AA_IDE: 1323 case PCI_PRODUCT_INTEL_82801AB_IDE: 1324 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1325 } 1326 } 1327 sc->sc_wdcdev.PIO_cap = 4; 1328 sc->sc_wdcdev.DMA_cap = 2; 1329 sc->sc_wdcdev.UDMA_cap = 1330 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1331 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1332 sc->sc_wdcdev.set_modes = piix_setup_channel; 1333 else 1334 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1335 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1336 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1337 1338 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1339 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1340 DEBUG_PROBE); 1341 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1342 WDCDEBUG_PRINT((", sidetim=0x%x", 1343 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1344 DEBUG_PROBE); 1345 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1346 WDCDEBUG_PRINT((", udamreg 0x%x", 1347 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1348 DEBUG_PROBE); 1349 } 1350 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1351 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1352 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1353 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1354 DEBUG_PROBE); 1355 } 1356 1357 } 1358 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1359 1360 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1361 cp = &sc->pciide_channels[channel]; 1362 /* PIIX is compat-only */ 1363 if (pciide_chansetup(sc, channel, 0) == 0) 1364 continue; 1365 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1366 if ((PIIX_IDETIM_READ(idetim, channel) & 1367 PIIX_IDETIM_IDE) == 0) { 1368 printf("%s: %s channel ignored (disabled)\n", 1369 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1370 continue; 1371 } 1372 /* PIIX are compat-only pciide devices */ 1373 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1374 if (cp->hw_ok == 0) 1375 continue; 1376 if (pciide_chan_candisable(cp)) { 1377 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1378 channel); 1379 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1380 idetim); 1381 } 1382 pciide_map_compat_intr(pa, cp, channel, 0); 1383 if (cp->hw_ok == 0) 1384 continue; 1385 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1386 } 1387 1388 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1389 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1390 DEBUG_PROBE); 1391 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1392 WDCDEBUG_PRINT((", sidetim=0x%x", 1393 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1394 DEBUG_PROBE); 1395 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1396 WDCDEBUG_PRINT((", udamreg 0x%x", 1397 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1398 DEBUG_PROBE); 1399 } 1400 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1401 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1402 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1403 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1404 DEBUG_PROBE); 1405 } 1406 } 1407 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1408 } 1409 1410 void 1411 piix_setup_channel(chp) 1412 struct channel_softc *chp; 1413 { 1414 u_int8_t mode[2], drive; 1415 u_int32_t oidetim, idetim, idedma_ctl; 1416 struct pciide_channel *cp = (struct pciide_channel*)chp; 1417 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1418 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1419 1420 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1421 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1422 idedma_ctl = 0; 1423 1424 /* set up new idetim: Enable IDE registers decode */ 1425 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1426 chp->channel); 1427 1428 /* setup DMA */ 1429 pciide_channel_dma_setup(cp); 1430 1431 /* 1432 * Here we have to mess up with drives mode: PIIX can't have 1433 * different timings for master and slave drives. 1434 * We need to find the best combination. 1435 */ 1436 1437 /* If both drives supports DMA, take the lower mode */ 1438 if ((drvp[0].drive_flags & DRIVE_DMA) && 1439 (drvp[1].drive_flags & DRIVE_DMA)) { 1440 mode[0] = mode[1] = 1441 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1442 drvp[0].DMA_mode = mode[0]; 1443 drvp[1].DMA_mode = mode[1]; 1444 goto ok; 1445 } 1446 /* 1447 * If only one drive supports DMA, use its mode, and 1448 * put the other one in PIO mode 0 if mode not compatible 1449 */ 1450 if (drvp[0].drive_flags & DRIVE_DMA) { 1451 mode[0] = drvp[0].DMA_mode; 1452 mode[1] = drvp[1].PIO_mode; 1453 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1454 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1455 mode[1] = drvp[1].PIO_mode = 0; 1456 goto ok; 1457 } 1458 if (drvp[1].drive_flags & DRIVE_DMA) { 1459 mode[1] = drvp[1].DMA_mode; 1460 mode[0] = drvp[0].PIO_mode; 1461 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1462 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1463 mode[0] = drvp[0].PIO_mode = 0; 1464 goto ok; 1465 } 1466 /* 1467 * If both drives are not DMA, takes the lower mode, unless 1468 * one of them is PIO mode < 2 1469 */ 1470 if (drvp[0].PIO_mode < 2) { 1471 mode[0] = drvp[0].PIO_mode = 0; 1472 mode[1] = drvp[1].PIO_mode; 1473 } else if (drvp[1].PIO_mode < 2) { 1474 mode[1] = drvp[1].PIO_mode = 0; 1475 mode[0] = drvp[0].PIO_mode; 1476 } else { 1477 mode[0] = mode[1] = 1478 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1479 drvp[0].PIO_mode = mode[0]; 1480 drvp[1].PIO_mode = mode[1]; 1481 } 1482 ok: /* The modes are setup */ 1483 for (drive = 0; drive < 2; drive++) { 1484 if (drvp[drive].drive_flags & DRIVE_DMA) { 1485 idetim |= piix_setup_idetim_timings( 1486 mode[drive], 1, chp->channel); 1487 goto end; 1488 } 1489 } 1490 /* If we are there, none of the drives are DMA */ 1491 if (mode[0] >= 2) 1492 idetim |= piix_setup_idetim_timings( 1493 mode[0], 0, chp->channel); 1494 else 1495 idetim |= piix_setup_idetim_timings( 1496 mode[1], 0, chp->channel); 1497 end: /* 1498 * timing mode is now set up in the controller. Enable 1499 * it per-drive 1500 */ 1501 for (drive = 0; drive < 2; drive++) { 1502 /* If no drive, skip */ 1503 if ((drvp[drive].drive_flags & DRIVE) == 0) 1504 continue; 1505 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1506 if (drvp[drive].drive_flags & DRIVE_DMA) 1507 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1508 } 1509 if (idedma_ctl != 0) { 1510 /* Add software bits in status register */ 1511 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1512 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1513 idedma_ctl); 1514 } 1515 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1516 pciide_print_modes(cp); 1517 } 1518 1519 void 1520 piix3_4_setup_channel(chp) 1521 struct channel_softc *chp; 1522 { 1523 struct ata_drive_datas *drvp; 1524 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1525 struct pciide_channel *cp = (struct pciide_channel*)chp; 1526 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1527 int drive; 1528 int channel = chp->channel; 1529 1530 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1531 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1532 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1533 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1534 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1535 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1536 PIIX_SIDETIM_RTC_MASK(channel)); 1537 1538 idedma_ctl = 0; 1539 /* If channel disabled, no need to go further */ 1540 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1541 return; 1542 /* set up new idetim: Enable IDE registers decode */ 1543 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1544 1545 /* setup DMA if needed */ 1546 pciide_channel_dma_setup(cp); 1547 1548 for (drive = 0; drive < 2; drive++) { 1549 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1550 PIIX_UDMATIM_SET(0x3, channel, drive)); 1551 drvp = &chp->ch_drive[drive]; 1552 /* If no drive, skip */ 1553 if ((drvp->drive_flags & DRIVE) == 0) 1554 continue; 1555 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1556 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1557 goto pio; 1558 1559 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1560 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1561 ideconf |= PIIX_CONFIG_PINGPONG; 1562 } 1563 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1564 /* setup Ultra/66 */ 1565 if (drvp->UDMA_mode > 2 && 1566 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1567 drvp->UDMA_mode = 2; 1568 if (drvp->UDMA_mode > 2) 1569 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1570 else 1571 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1572 } 1573 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1574 (drvp->drive_flags & DRIVE_UDMA)) { 1575 /* use Ultra/DMA */ 1576 drvp->drive_flags &= ~DRIVE_DMA; 1577 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1578 udmareg |= PIIX_UDMATIM_SET( 1579 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1580 } else { 1581 /* use Multiword DMA */ 1582 drvp->drive_flags &= ~DRIVE_UDMA; 1583 if (drive == 0) { 1584 idetim |= piix_setup_idetim_timings( 1585 drvp->DMA_mode, 1, channel); 1586 } else { 1587 sidetim |= piix_setup_sidetim_timings( 1588 drvp->DMA_mode, 1, channel); 1589 idetim =PIIX_IDETIM_SET(idetim, 1590 PIIX_IDETIM_SITRE, channel); 1591 } 1592 } 1593 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1594 1595 pio: /* use PIO mode */ 1596 idetim |= piix_setup_idetim_drvs(drvp); 1597 if (drive == 0) { 1598 idetim |= piix_setup_idetim_timings( 1599 drvp->PIO_mode, 0, channel); 1600 } else { 1601 sidetim |= piix_setup_sidetim_timings( 1602 drvp->PIO_mode, 0, channel); 1603 idetim =PIIX_IDETIM_SET(idetim, 1604 PIIX_IDETIM_SITRE, channel); 1605 } 1606 } 1607 if (idedma_ctl != 0) { 1608 /* Add software bits in status register */ 1609 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1610 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1611 idedma_ctl); 1612 } 1613 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1614 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1615 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1616 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1617 pciide_print_modes(cp); 1618 } 1619 1620 1621 /* setup ISP and RTC fields, based on mode */ 1622 static u_int32_t 1623 piix_setup_idetim_timings(mode, dma, channel) 1624 u_int8_t mode; 1625 u_int8_t dma; 1626 u_int8_t channel; 1627 { 1628 1629 if (dma) 1630 return PIIX_IDETIM_SET(0, 1631 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1632 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1633 channel); 1634 else 1635 return PIIX_IDETIM_SET(0, 1636 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1637 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1638 channel); 1639 } 1640 1641 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1642 static u_int32_t 1643 piix_setup_idetim_drvs(drvp) 1644 struct ata_drive_datas *drvp; 1645 { 1646 u_int32_t ret = 0; 1647 struct channel_softc *chp = drvp->chnl_softc; 1648 u_int8_t channel = chp->channel; 1649 u_int8_t drive = drvp->drive; 1650 1651 /* 1652 * If drive is using UDMA, timings setups are independant 1653 * So just check DMA and PIO here. 1654 */ 1655 if (drvp->drive_flags & DRIVE_DMA) { 1656 /* if mode = DMA mode 0, use compatible timings */ 1657 if ((drvp->drive_flags & DRIVE_DMA) && 1658 drvp->DMA_mode == 0) { 1659 drvp->PIO_mode = 0; 1660 return ret; 1661 } 1662 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1663 /* 1664 * PIO and DMA timings are the same, use fast timings for PIO 1665 * too, else use compat timings. 1666 */ 1667 if ((piix_isp_pio[drvp->PIO_mode] != 1668 piix_isp_dma[drvp->DMA_mode]) || 1669 (piix_rtc_pio[drvp->PIO_mode] != 1670 piix_rtc_dma[drvp->DMA_mode])) 1671 drvp->PIO_mode = 0; 1672 /* if PIO mode <= 2, use compat timings for PIO */ 1673 if (drvp->PIO_mode <= 2) { 1674 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1675 channel); 1676 return ret; 1677 } 1678 } 1679 1680 /* 1681 * Now setup PIO modes. If mode < 2, use compat timings. 1682 * Else enable fast timings. Enable IORDY and prefetch/post 1683 * if PIO mode >= 3. 1684 */ 1685 1686 if (drvp->PIO_mode < 2) 1687 return ret; 1688 1689 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1690 if (drvp->PIO_mode >= 3) { 1691 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1692 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1693 } 1694 return ret; 1695 } 1696 1697 /* setup values in SIDETIM registers, based on mode */ 1698 static u_int32_t 1699 piix_setup_sidetim_timings(mode, dma, channel) 1700 u_int8_t mode; 1701 u_int8_t dma; 1702 u_int8_t channel; 1703 { 1704 if (dma) 1705 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1706 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1707 else 1708 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1709 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1710 } 1711 1712 void 1713 amd756_chip_map(sc, pa) 1714 struct pciide_softc *sc; 1715 struct pci_attach_args *pa; 1716 { 1717 struct pciide_channel *cp; 1718 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1719 int channel; 1720 pcireg_t chanenable; 1721 bus_size_t cmdsize, ctlsize; 1722 1723 if (pciide_chipen(sc, pa) == 0) 1724 return; 1725 printf("%s: bus-master DMA support present", 1726 sc->sc_wdcdev.sc_dev.dv_xname); 1727 pciide_mapreg_dma(sc, pa); 1728 printf("\n"); 1729 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1730 WDC_CAPABILITY_MODE; 1731 if (sc->sc_dma_ok) { 1732 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1733 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1734 sc->sc_wdcdev.irqack = pciide_irqack; 1735 } 1736 sc->sc_wdcdev.PIO_cap = 4; 1737 sc->sc_wdcdev.DMA_cap = 2; 1738 sc->sc_wdcdev.UDMA_cap = 4; 1739 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1740 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1741 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1742 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1743 1744 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1745 DEBUG_PROBE); 1746 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1747 cp = &sc->pciide_channels[channel]; 1748 if (pciide_chansetup(sc, channel, interface) == 0) 1749 continue; 1750 1751 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1752 printf("%s: %s channel ignored (disabled)\n", 1753 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1754 continue; 1755 } 1756 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1757 pciide_pci_intr); 1758 1759 if (pciide_chan_candisable(cp)) 1760 chanenable &= ~AMD756_CHAN_EN(channel); 1761 pciide_map_compat_intr(pa, cp, channel, interface); 1762 if (cp->hw_ok == 0) 1763 continue; 1764 1765 amd756_setup_channel(&cp->wdc_channel); 1766 } 1767 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1768 chanenable); 1769 return; 1770 } 1771 1772 void 1773 amd756_setup_channel(chp) 1774 struct channel_softc *chp; 1775 { 1776 u_int32_t udmatim_reg, datatim_reg; 1777 u_int8_t idedma_ctl; 1778 int mode, drive; 1779 struct ata_drive_datas *drvp; 1780 struct pciide_channel *cp = (struct pciide_channel*)chp; 1781 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1782 int rev = PCI_REVISION( 1783 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1784 1785 idedma_ctl = 0; 1786 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1787 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1788 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1789 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1790 1791 /* setup DMA if needed */ 1792 pciide_channel_dma_setup(cp); 1793 1794 for (drive = 0; drive < 2; drive++) { 1795 drvp = &chp->ch_drive[drive]; 1796 /* If no drive, skip */ 1797 if ((drvp->drive_flags & DRIVE) == 0) 1798 continue; 1799 /* add timing values, setup DMA if needed */ 1800 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1801 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1802 mode = drvp->PIO_mode; 1803 goto pio; 1804 } 1805 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1806 (drvp->drive_flags & DRIVE_UDMA)) { 1807 /* use Ultra/DMA */ 1808 drvp->drive_flags &= ~DRIVE_DMA; 1809 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1810 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1811 AMD756_UDMA_TIME(chp->channel, drive, 1812 amd756_udma_tim[drvp->UDMA_mode]); 1813 /* can use PIO timings, MW DMA unused */ 1814 mode = drvp->PIO_mode; 1815 } else { 1816 /* use Multiword DMA, but only if revision is OK */ 1817 drvp->drive_flags &= ~DRIVE_UDMA; 1818 #ifndef PCIIDE_AMD756_ENABLEDMA 1819 /* 1820 * The workaround doesn't seem to be necessary 1821 * with all drives, so it can be disabled by 1822 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1823 * triggered. 1824 */ 1825 if (AMD756_CHIPREV_DISABLEDMA(rev)) { 1826 printf("%s:%d:%d: multi-word DMA disabled due " 1827 "to chip revision\n", 1828 sc->sc_wdcdev.sc_dev.dv_xname, 1829 chp->channel, drive); 1830 mode = drvp->PIO_mode; 1831 drvp->drive_flags &= ~DRIVE_DMA; 1832 goto pio; 1833 } 1834 #endif 1835 /* mode = min(pio, dma+2) */ 1836 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1837 mode = drvp->PIO_mode; 1838 else 1839 mode = drvp->DMA_mode + 2; 1840 } 1841 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1842 1843 pio: /* setup PIO mode */ 1844 if (mode <= 2) { 1845 drvp->DMA_mode = 0; 1846 drvp->PIO_mode = 0; 1847 mode = 0; 1848 } else { 1849 drvp->PIO_mode = mode; 1850 drvp->DMA_mode = mode - 2; 1851 } 1852 datatim_reg |= 1853 AMD756_DATATIM_PULSE(chp->channel, drive, 1854 amd756_pio_set[mode]) | 1855 AMD756_DATATIM_RECOV(chp->channel, drive, 1856 amd756_pio_rec[mode]); 1857 } 1858 if (idedma_ctl != 0) { 1859 /* Add software bits in status register */ 1860 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1861 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1862 idedma_ctl); 1863 } 1864 pciide_print_modes(cp); 1865 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1866 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1867 } 1868 1869 void 1870 apollo_chip_map(sc, pa) 1871 struct pciide_softc *sc; 1872 struct pci_attach_args *pa; 1873 { 1874 struct pciide_channel *cp; 1875 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1876 int channel; 1877 u_int32_t ideconf; 1878 bus_size_t cmdsize, ctlsize; 1879 1880 if (pciide_chipen(sc, pa) == 0) 1881 return; 1882 printf("%s: bus-master DMA support present", 1883 sc->sc_wdcdev.sc_dev.dv_xname); 1884 pciide_mapreg_dma(sc, pa); 1885 printf("\n"); 1886 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1887 WDC_CAPABILITY_MODE; 1888 if (sc->sc_dma_ok) { 1889 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1890 sc->sc_wdcdev.irqack = pciide_irqack; 1891 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1892 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1893 } 1894 sc->sc_wdcdev.PIO_cap = 4; 1895 sc->sc_wdcdev.DMA_cap = 2; 1896 sc->sc_wdcdev.UDMA_cap = 2; 1897 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1898 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1899 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1900 1901 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1902 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1903 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1904 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1905 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1906 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1907 DEBUG_PROBE); 1908 1909 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1910 cp = &sc->pciide_channels[channel]; 1911 if (pciide_chansetup(sc, channel, interface) == 0) 1912 continue; 1913 1914 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1915 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1916 printf("%s: %s channel ignored (disabled)\n", 1917 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1918 continue; 1919 } 1920 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1921 pciide_pci_intr); 1922 if (cp->hw_ok == 0) 1923 continue; 1924 if (pciide_chan_candisable(cp)) { 1925 ideconf &= ~APO_IDECONF_EN(channel); 1926 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1927 ideconf); 1928 } 1929 pciide_map_compat_intr(pa, cp, channel, interface); 1930 1931 if (cp->hw_ok == 0) 1932 continue; 1933 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1934 } 1935 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1936 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1937 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1938 } 1939 1940 void 1941 apollo_setup_channel(chp) 1942 struct channel_softc *chp; 1943 { 1944 u_int32_t udmatim_reg, datatim_reg; 1945 u_int8_t idedma_ctl; 1946 int mode, drive; 1947 struct ata_drive_datas *drvp; 1948 struct pciide_channel *cp = (struct pciide_channel*)chp; 1949 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1950 1951 idedma_ctl = 0; 1952 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1953 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1954 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1955 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1956 1957 /* setup DMA if needed */ 1958 pciide_channel_dma_setup(cp); 1959 1960 for (drive = 0; drive < 2; drive++) { 1961 drvp = &chp->ch_drive[drive]; 1962 /* If no drive, skip */ 1963 if ((drvp->drive_flags & DRIVE) == 0) 1964 continue; 1965 /* add timing values, setup DMA if needed */ 1966 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1967 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1968 mode = drvp->PIO_mode; 1969 goto pio; 1970 } 1971 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1972 (drvp->drive_flags & DRIVE_UDMA)) { 1973 /* use Ultra/DMA */ 1974 drvp->drive_flags &= ~DRIVE_DMA; 1975 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1976 APO_UDMA_EN_MTH(chp->channel, drive) | 1977 APO_UDMA_TIME(chp->channel, drive, 1978 apollo_udma_tim[drvp->UDMA_mode]); 1979 /* can use PIO timings, MW DMA unused */ 1980 mode = drvp->PIO_mode; 1981 } else { 1982 /* use Multiword DMA */ 1983 drvp->drive_flags &= ~DRIVE_UDMA; 1984 /* mode = min(pio, dma+2) */ 1985 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1986 mode = drvp->PIO_mode; 1987 else 1988 mode = drvp->DMA_mode + 2; 1989 } 1990 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1991 1992 pio: /* setup PIO mode */ 1993 if (mode <= 2) { 1994 drvp->DMA_mode = 0; 1995 drvp->PIO_mode = 0; 1996 mode = 0; 1997 } else { 1998 drvp->PIO_mode = mode; 1999 drvp->DMA_mode = mode - 2; 2000 } 2001 datatim_reg |= 2002 APO_DATATIM_PULSE(chp->channel, drive, 2003 apollo_pio_set[mode]) | 2004 APO_DATATIM_RECOV(chp->channel, drive, 2005 apollo_pio_rec[mode]); 2006 } 2007 if (idedma_ctl != 0) { 2008 /* Add software bits in status register */ 2009 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2010 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2011 idedma_ctl); 2012 } 2013 pciide_print_modes(cp); 2014 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2015 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2016 } 2017 2018 void 2019 cmd_channel_map(pa, sc, channel) 2020 struct pci_attach_args *pa; 2021 struct pciide_softc *sc; 2022 int channel; 2023 { 2024 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2025 bus_size_t cmdsize, ctlsize; 2026 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2027 int interface; 2028 2029 /* 2030 * The 0648/0649 can be told to identify as a RAID controller. 2031 * In this case, we have to fake interface 2032 */ 2033 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2034 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2035 PCIIDE_INTERFACE_SETTABLE(1); 2036 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2037 CMD_CONF_DSA1) 2038 interface |= PCIIDE_INTERFACE_PCI(0) | 2039 PCIIDE_INTERFACE_PCI(1); 2040 } else { 2041 interface = PCI_INTERFACE(pa->pa_class); 2042 } 2043 2044 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2045 cp->name = PCIIDE_CHANNEL_NAME(channel); 2046 cp->wdc_channel.channel = channel; 2047 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2048 2049 if (channel > 0) { 2050 cp->wdc_channel.ch_queue = 2051 sc->pciide_channels[0].wdc_channel.ch_queue; 2052 } else { 2053 cp->wdc_channel.ch_queue = 2054 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2055 } 2056 if (cp->wdc_channel.ch_queue == NULL) { 2057 printf("%s %s channel: " 2058 "can't allocate memory for command queue", 2059 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2060 return; 2061 } 2062 2063 printf("%s: %s channel %s to %s mode\n", 2064 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2065 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2066 "configured" : "wired", 2067 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2068 "native-PCI" : "compatibility"); 2069 2070 /* 2071 * with a CMD PCI64x, if we get here, the first channel is enabled: 2072 * there's no way to disable the first channel without disabling 2073 * the whole device 2074 */ 2075 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2076 printf("%s: %s channel ignored (disabled)\n", 2077 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2078 return; 2079 } 2080 2081 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2082 if (cp->hw_ok == 0) 2083 return; 2084 if (channel == 1) { 2085 if (pciide_chan_candisable(cp)) { 2086 ctrl &= ~CMD_CTRL_2PORT; 2087 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2088 CMD_CTRL, ctrl); 2089 } 2090 } 2091 pciide_map_compat_intr(pa, cp, channel, interface); 2092 } 2093 2094 int 2095 cmd_pci_intr(arg) 2096 void *arg; 2097 { 2098 struct pciide_softc *sc = arg; 2099 struct pciide_channel *cp; 2100 struct channel_softc *wdc_cp; 2101 int i, rv, crv; 2102 u_int32_t priirq, secirq; 2103 2104 rv = 0; 2105 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2106 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2107 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2108 cp = &sc->pciide_channels[i]; 2109 wdc_cp = &cp->wdc_channel; 2110 /* If a compat channel skip. */ 2111 if (cp->compat) 2112 continue; 2113 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2114 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2115 crv = wdcintr(wdc_cp); 2116 if (crv == 0) 2117 printf("%s:%d: bogus intr\n", 2118 sc->sc_wdcdev.sc_dev.dv_xname, i); 2119 else 2120 rv = 1; 2121 } 2122 } 2123 return rv; 2124 } 2125 2126 void 2127 cmd_chip_map(sc, pa) 2128 struct pciide_softc *sc; 2129 struct pci_attach_args *pa; 2130 { 2131 int channel; 2132 2133 /* 2134 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2135 * and base adresses registers can be disabled at 2136 * hardware level. In this case, the device is wired 2137 * in compat mode and its first channel is always enabled, 2138 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2139 * In fact, it seems that the first channel of the CMD PCI0640 2140 * can't be disabled. 2141 */ 2142 2143 #ifdef PCIIDE_CMD064x_DISABLE 2144 if (pciide_chipen(sc, pa) == 0) 2145 return; 2146 #endif 2147 2148 printf("%s: hardware does not support DMA\n", 2149 sc->sc_wdcdev.sc_dev.dv_xname); 2150 sc->sc_dma_ok = 0; 2151 2152 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2153 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2154 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2155 2156 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2157 cmd_channel_map(pa, sc, channel); 2158 } 2159 } 2160 2161 void 2162 cmd0643_9_chip_map(sc, pa) 2163 struct pciide_softc *sc; 2164 struct pci_attach_args *pa; 2165 { 2166 struct pciide_channel *cp; 2167 int channel; 2168 2169 /* 2170 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2171 * and base adresses registers can be disabled at 2172 * hardware level. In this case, the device is wired 2173 * in compat mode and its first channel is always enabled, 2174 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2175 * In fact, it seems that the first channel of the CMD PCI0640 2176 * can't be disabled. 2177 */ 2178 2179 #ifdef PCIIDE_CMD064x_DISABLE 2180 if (pciide_chipen(sc, pa) == 0) 2181 return; 2182 #endif 2183 printf("%s: bus-master DMA support present", 2184 sc->sc_wdcdev.sc_dev.dv_xname); 2185 pciide_mapreg_dma(sc, pa); 2186 printf("\n"); 2187 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2188 WDC_CAPABILITY_MODE; 2189 if (sc->sc_dma_ok) { 2190 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2191 switch (sc->sc_pp->ide_product) { 2192 case PCI_PRODUCT_CMDTECH_649: 2193 case PCI_PRODUCT_CMDTECH_648: 2194 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2195 sc->sc_wdcdev.UDMA_cap = 4; 2196 sc->sc_wdcdev.irqack = cmd648_9_irqack; 2197 break; 2198 default: 2199 sc->sc_wdcdev.irqack = pciide_irqack; 2200 } 2201 } 2202 2203 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2204 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2205 sc->sc_wdcdev.PIO_cap = 4; 2206 sc->sc_wdcdev.DMA_cap = 2; 2207 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2208 2209 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2210 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2211 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2212 DEBUG_PROBE); 2213 2214 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2215 cp = &sc->pciide_channels[channel]; 2216 cmd_channel_map(pa, sc, channel); 2217 if (cp->hw_ok == 0) 2218 continue; 2219 cmd0643_9_setup_channel(&cp->wdc_channel); 2220 } 2221 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2222 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2223 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2224 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2225 DEBUG_PROBE); 2226 } 2227 2228 void 2229 cmd0643_9_setup_channel(chp) 2230 struct channel_softc *chp; 2231 { 2232 struct ata_drive_datas *drvp; 2233 u_int8_t tim; 2234 u_int32_t idedma_ctl, udma_reg; 2235 int drive; 2236 struct pciide_channel *cp = (struct pciide_channel*)chp; 2237 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2238 2239 idedma_ctl = 0; 2240 /* setup DMA if needed */ 2241 pciide_channel_dma_setup(cp); 2242 2243 for (drive = 0; drive < 2; drive++) { 2244 drvp = &chp->ch_drive[drive]; 2245 /* If no drive, skip */ 2246 if ((drvp->drive_flags & DRIVE) == 0) 2247 continue; 2248 /* add timing values, setup DMA if needed */ 2249 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2250 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2251 if (drvp->drive_flags & DRIVE_UDMA) { 2252 /* UltraDMA on a 0648 or 0649 */ 2253 udma_reg = pciide_pci_read(sc->sc_pc, 2254 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2255 if (drvp->UDMA_mode > 2 && 2256 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2257 CMD_BICSR) & 2258 CMD_BICSR_80(chp->channel)) == 0) 2259 drvp->UDMA_mode = 2; 2260 if (drvp->UDMA_mode > 2) 2261 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2262 else 2263 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2264 udma_reg |= CMD_UDMATIM_UDMA(drive); 2265 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2266 CMD_UDMATIM_TIM_OFF(drive)); 2267 udma_reg |= 2268 (cmd0648_9_tim_udma[drvp->UDMA_mode] << 2269 CMD_UDMATIM_TIM_OFF(drive)); 2270 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2271 CMD_UDMATIM(chp->channel), udma_reg); 2272 } else { 2273 /* 2274 * use Multiword DMA. 2275 * Timings will be used for both PIO and DMA, 2276 * so adjust DMA mode if needed 2277 * if we have a 0648/9, turn off UDMA 2278 */ 2279 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2280 udma_reg = pciide_pci_read(sc->sc_pc, 2281 sc->sc_tag, 2282 CMD_UDMATIM(chp->channel)); 2283 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2284 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2285 CMD_UDMATIM(chp->channel), 2286 udma_reg); 2287 } 2288 if (drvp->PIO_mode >= 3 && 2289 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2290 drvp->DMA_mode = drvp->PIO_mode - 2; 2291 } 2292 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2293 } 2294 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2295 } 2296 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2297 CMD_DATA_TIM(chp->channel, drive), tim); 2298 } 2299 if (idedma_ctl != 0) { 2300 /* Add software bits in status register */ 2301 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2302 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2303 idedma_ctl); 2304 } 2305 pciide_print_modes(cp); 2306 } 2307 2308 void 2309 cmd648_9_irqack(chp) 2310 struct channel_softc *chp; 2311 { 2312 u_int32_t priirq, secirq; 2313 struct pciide_channel *cp = (struct pciide_channel*)chp; 2314 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2315 2316 if (chp->channel == 0) { 2317 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2318 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2319 } else { 2320 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2321 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2322 } 2323 pciide_irqack(chp); 2324 } 2325 2326 void 2327 cy693_chip_map(sc, pa) 2328 struct pciide_softc *sc; 2329 struct pci_attach_args *pa; 2330 { 2331 struct pciide_channel *cp; 2332 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2333 bus_size_t cmdsize, ctlsize; 2334 2335 if (pciide_chipen(sc, pa) == 0) 2336 return; 2337 /* 2338 * this chip has 2 PCI IDE functions, one for primary and one for 2339 * secondary. So we need to call pciide_mapregs_compat() with 2340 * the real channel 2341 */ 2342 if (pa->pa_function == 1) { 2343 sc->sc_cy_compatchan = 0; 2344 } else if (pa->pa_function == 2) { 2345 sc->sc_cy_compatchan = 1; 2346 } else { 2347 printf("%s: unexpected PCI function %d\n", 2348 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2349 return; 2350 } 2351 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2352 printf("%s: bus-master DMA support present, " 2353 "but unused (no driver support)", 2354 sc->sc_wdcdev.sc_dev.dv_xname); 2355 } else { 2356 printf("%s: hardware does not support DMA", 2357 sc->sc_wdcdev.sc_dev.dv_xname); 2358 } 2359 sc->sc_dma_ok = 0; 2360 printf("\n"); 2361 2362 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2363 WDC_CAPABILITY_MODE; 2364 sc->sc_wdcdev.PIO_cap = 4; 2365 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2366 2367 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2368 sc->sc_wdcdev.nchannels = 1; 2369 2370 /* Only one channel for this chip; if we are here it's enabled */ 2371 cp = &sc->pciide_channels[0]; 2372 sc->wdc_chanarray[0] = &cp->wdc_channel; 2373 cp->name = PCIIDE_CHANNEL_NAME(0); 2374 cp->wdc_channel.channel = 0; 2375 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2376 cp->wdc_channel.ch_queue = 2377 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2378 if (cp->wdc_channel.ch_queue == NULL) { 2379 printf("%s primary channel: " 2380 "can't allocate memory for command queue", 2381 sc->sc_wdcdev.sc_dev.dv_xname); 2382 return; 2383 } 2384 printf("%s: primary channel %s to ", 2385 sc->sc_wdcdev.sc_dev.dv_xname, 2386 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2387 "configured" : "wired"); 2388 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2389 printf("native-PCI"); 2390 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2391 pciide_pci_intr); 2392 } else { 2393 printf("compatibility"); 2394 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2395 &cmdsize, &ctlsize); 2396 } 2397 printf(" mode\n"); 2398 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2399 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2400 wdcattach(&cp->wdc_channel); 2401 if (pciide_chan_candisable(cp)) { 2402 pci_conf_write(sc->sc_pc, sc->sc_tag, 2403 PCI_COMMAND_STATUS_REG, 0); 2404 } 2405 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2406 if (cp->hw_ok == 0) 2407 return; 2408 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2409 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2410 cy693_setup_channel(&cp->wdc_channel); 2411 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2412 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2413 } 2414 2415 void 2416 cy693_setup_channel(chp) 2417 struct channel_softc *chp; 2418 { 2419 struct ata_drive_datas *drvp; 2420 int drive; 2421 u_int32_t cy_cmd_ctrl; 2422 u_int32_t idedma_ctl; 2423 struct pciide_channel *cp = (struct pciide_channel*)chp; 2424 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2425 cy_cmd_ctrl = idedma_ctl = 0; 2426 2427 for (drive = 0; drive < 2; drive++) { 2428 drvp = &chp->ch_drive[drive]; 2429 /* If no drive, skip */ 2430 if ((drvp->drive_flags & DRIVE) == 0) 2431 continue; 2432 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2433 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2434 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2435 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2436 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2437 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2438 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2439 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2440 } 2441 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2442 2443 pciide_print_modes(cp); 2444 2445 if (idedma_ctl != 0) { 2446 /* Add software bits in status register */ 2447 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2448 IDEDMA_CTL, idedma_ctl); 2449 } 2450 } 2451 2452 void 2453 sis_chip_map(sc, pa) 2454 struct pciide_softc *sc; 2455 struct pci_attach_args *pa; 2456 { 2457 struct pciide_channel *cp; 2458 int channel; 2459 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2460 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2461 pcireg_t rev = PCI_REVISION(pa->pa_class); 2462 bus_size_t cmdsize, ctlsize; 2463 2464 if (pciide_chipen(sc, pa) == 0) 2465 return; 2466 printf("%s: bus-master DMA support present", 2467 sc->sc_wdcdev.sc_dev.dv_xname); 2468 pciide_mapreg_dma(sc, pa); 2469 printf("\n"); 2470 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2471 WDC_CAPABILITY_MODE; 2472 if (sc->sc_dma_ok) { 2473 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2474 sc->sc_wdcdev.irqack = pciide_irqack; 2475 if (rev >= 0xd0) 2476 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2477 } 2478 2479 sc->sc_wdcdev.PIO_cap = 4; 2480 sc->sc_wdcdev.DMA_cap = 2; 2481 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2482 sc->sc_wdcdev.UDMA_cap = 2; 2483 sc->sc_wdcdev.set_modes = sis_setup_channel; 2484 2485 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2486 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2487 2488 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2489 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2490 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2491 2492 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2493 cp = &sc->pciide_channels[channel]; 2494 if (pciide_chansetup(sc, channel, interface) == 0) 2495 continue; 2496 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2497 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2498 printf("%s: %s channel ignored (disabled)\n", 2499 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2500 continue; 2501 } 2502 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2503 pciide_pci_intr); 2504 if (cp->hw_ok == 0) 2505 continue; 2506 if (pciide_chan_candisable(cp)) { 2507 if (channel == 0) 2508 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2509 else 2510 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2511 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2512 sis_ctr0); 2513 } 2514 pciide_map_compat_intr(pa, cp, channel, interface); 2515 if (cp->hw_ok == 0) 2516 continue; 2517 sis_setup_channel(&cp->wdc_channel); 2518 } 2519 } 2520 2521 void 2522 sis_setup_channel(chp) 2523 struct channel_softc *chp; 2524 { 2525 struct ata_drive_datas *drvp; 2526 int drive; 2527 u_int32_t sis_tim; 2528 u_int32_t idedma_ctl; 2529 struct pciide_channel *cp = (struct pciide_channel*)chp; 2530 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2531 2532 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2533 "channel %d 0x%x\n", chp->channel, 2534 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2535 DEBUG_PROBE); 2536 sis_tim = 0; 2537 idedma_ctl = 0; 2538 /* setup DMA if needed */ 2539 pciide_channel_dma_setup(cp); 2540 2541 for (drive = 0; drive < 2; drive++) { 2542 drvp = &chp->ch_drive[drive]; 2543 /* If no drive, skip */ 2544 if ((drvp->drive_flags & DRIVE) == 0) 2545 continue; 2546 /* add timing values, setup DMA if needed */ 2547 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2548 (drvp->drive_flags & DRIVE_UDMA) == 0) 2549 goto pio; 2550 2551 if (drvp->drive_flags & DRIVE_UDMA) { 2552 /* use Ultra/DMA */ 2553 drvp->drive_flags &= ~DRIVE_DMA; 2554 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2555 SIS_TIM_UDMA_TIME_OFF(drive); 2556 sis_tim |= SIS_TIM_UDMA_EN(drive); 2557 } else { 2558 /* 2559 * use Multiword DMA 2560 * Timings will be used for both PIO and DMA, 2561 * so adjust DMA mode if needed 2562 */ 2563 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2564 drvp->PIO_mode = drvp->DMA_mode + 2; 2565 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2566 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2567 drvp->PIO_mode - 2 : 0; 2568 if (drvp->DMA_mode == 0) 2569 drvp->PIO_mode = 0; 2570 } 2571 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2572 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2573 SIS_TIM_ACT_OFF(drive); 2574 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2575 SIS_TIM_REC_OFF(drive); 2576 } 2577 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2578 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2579 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2580 if (idedma_ctl != 0) { 2581 /* Add software bits in status register */ 2582 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2583 IDEDMA_CTL, idedma_ctl); 2584 } 2585 pciide_print_modes(cp); 2586 } 2587 2588 void 2589 acer_chip_map(sc, pa) 2590 struct pciide_softc *sc; 2591 struct pci_attach_args *pa; 2592 { 2593 struct pciide_channel *cp; 2594 int channel; 2595 pcireg_t cr, interface; 2596 bus_size_t cmdsize, ctlsize; 2597 2598 if (pciide_chipen(sc, pa) == 0) 2599 return; 2600 printf("%s: bus-master DMA support present", 2601 sc->sc_wdcdev.sc_dev.dv_xname); 2602 pciide_mapreg_dma(sc, pa); 2603 printf("\n"); 2604 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2605 WDC_CAPABILITY_MODE; 2606 if (sc->sc_dma_ok) { 2607 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2608 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2609 sc->sc_wdcdev.irqack = pciide_irqack; 2610 } 2611 2612 sc->sc_wdcdev.PIO_cap = 4; 2613 sc->sc_wdcdev.DMA_cap = 2; 2614 sc->sc_wdcdev.UDMA_cap = 2; 2615 sc->sc_wdcdev.set_modes = acer_setup_channel; 2616 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2617 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2618 2619 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2620 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2621 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2622 2623 /* Enable "microsoft register bits" R/W. */ 2624 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2625 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2626 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2627 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2628 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2629 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2630 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2631 ~ACER_CHANSTATUSREGS_RO); 2632 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2633 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2634 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2635 /* Don't use cr, re-read the real register content instead */ 2636 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2637 PCI_CLASS_REG)); 2638 2639 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2640 cp = &sc->pciide_channels[channel]; 2641 if (pciide_chansetup(sc, channel, interface) == 0) 2642 continue; 2643 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2644 printf("%s: %s channel ignored (disabled)\n", 2645 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2646 continue; 2647 } 2648 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2649 acer_pci_intr); 2650 if (cp->hw_ok == 0) 2651 continue; 2652 if (pciide_chan_candisable(cp)) { 2653 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2654 pci_conf_write(sc->sc_pc, sc->sc_tag, 2655 PCI_CLASS_REG, cr); 2656 } 2657 pciide_map_compat_intr(pa, cp, channel, interface); 2658 acer_setup_channel(&cp->wdc_channel); 2659 } 2660 } 2661 2662 void 2663 acer_setup_channel(chp) 2664 struct channel_softc *chp; 2665 { 2666 struct ata_drive_datas *drvp; 2667 int drive; 2668 u_int32_t acer_fifo_udma; 2669 u_int32_t idedma_ctl; 2670 struct pciide_channel *cp = (struct pciide_channel*)chp; 2671 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2672 2673 idedma_ctl = 0; 2674 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2675 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2676 acer_fifo_udma), DEBUG_PROBE); 2677 /* setup DMA if needed */ 2678 pciide_channel_dma_setup(cp); 2679 2680 for (drive = 0; drive < 2; drive++) { 2681 drvp = &chp->ch_drive[drive]; 2682 /* If no drive, skip */ 2683 if ((drvp->drive_flags & DRIVE) == 0) 2684 continue; 2685 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2686 "channel %d drive %d 0x%x\n", chp->channel, drive, 2687 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2688 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2689 /* clear FIFO/DMA mode */ 2690 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2691 ACER_UDMA_EN(chp->channel, drive) | 2692 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2693 2694 /* add timing values, setup DMA if needed */ 2695 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2696 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2697 acer_fifo_udma |= 2698 ACER_FTH_OPL(chp->channel, drive, 0x1); 2699 goto pio; 2700 } 2701 2702 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2703 if (drvp->drive_flags & DRIVE_UDMA) { 2704 /* use Ultra/DMA */ 2705 drvp->drive_flags &= ~DRIVE_DMA; 2706 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2707 acer_fifo_udma |= 2708 ACER_UDMA_TIM(chp->channel, drive, 2709 acer_udma[drvp->UDMA_mode]); 2710 } else { 2711 /* 2712 * use Multiword DMA 2713 * Timings will be used for both PIO and DMA, 2714 * so adjust DMA mode if needed 2715 */ 2716 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2717 drvp->PIO_mode = drvp->DMA_mode + 2; 2718 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2719 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2720 drvp->PIO_mode - 2 : 0; 2721 if (drvp->DMA_mode == 0) 2722 drvp->PIO_mode = 0; 2723 } 2724 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2725 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2726 ACER_IDETIM(chp->channel, drive), 2727 acer_pio[drvp->PIO_mode]); 2728 } 2729 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2730 acer_fifo_udma), DEBUG_PROBE); 2731 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2732 if (idedma_ctl != 0) { 2733 /* Add software bits in status register */ 2734 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2735 IDEDMA_CTL, idedma_ctl); 2736 } 2737 pciide_print_modes(cp); 2738 } 2739 2740 int 2741 acer_pci_intr(arg) 2742 void *arg; 2743 { 2744 struct pciide_softc *sc = arg; 2745 struct pciide_channel *cp; 2746 struct channel_softc *wdc_cp; 2747 int i, rv, crv; 2748 u_int32_t chids; 2749 2750 rv = 0; 2751 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2752 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2753 cp = &sc->pciide_channels[i]; 2754 wdc_cp = &cp->wdc_channel; 2755 /* If a compat channel skip. */ 2756 if (cp->compat) 2757 continue; 2758 if (chids & ACER_CHIDS_INT(i)) { 2759 crv = wdcintr(wdc_cp); 2760 if (crv == 0) 2761 printf("%s:%d: bogus intr\n", 2762 sc->sc_wdcdev.sc_dev.dv_xname, i); 2763 else 2764 rv = 1; 2765 } 2766 } 2767 return rv; 2768 } 2769 2770 void 2771 hpt_chip_map(sc, pa) 2772 struct pciide_softc *sc; 2773 struct pci_attach_args *pa; 2774 { 2775 struct pciide_channel *cp; 2776 int i, compatchan, revision; 2777 pcireg_t interface; 2778 bus_size_t cmdsize, ctlsize; 2779 2780 if (pciide_chipen(sc, pa) == 0) 2781 return; 2782 revision = PCI_REVISION(pa->pa_class); 2783 2784 /* 2785 * when the chip is in native mode it identifies itself as a 2786 * 'misc mass storage'. Fake interface in this case. 2787 */ 2788 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2789 interface = PCI_INTERFACE(pa->pa_class); 2790 } else { 2791 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2792 PCIIDE_INTERFACE_PCI(0); 2793 if (revision == HPT370_REV) 2794 interface |= PCIIDE_INTERFACE_PCI(1); 2795 } 2796 2797 printf("%s: bus-master DMA support present", 2798 sc->sc_wdcdev.sc_dev.dv_xname); 2799 pciide_mapreg_dma(sc, pa); 2800 printf("\n"); 2801 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2802 WDC_CAPABILITY_MODE; 2803 if (sc->sc_dma_ok) { 2804 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2805 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2806 sc->sc_wdcdev.irqack = pciide_irqack; 2807 } 2808 sc->sc_wdcdev.PIO_cap = 4; 2809 sc->sc_wdcdev.DMA_cap = 2; 2810 sc->sc_wdcdev.UDMA_cap = 4; 2811 2812 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2813 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2814 if (revision == HPT366_REV) { 2815 /* 2816 * The 366 has 2 PCI IDE functions, one for primary and one 2817 * for secondary. So we need to call pciide_mapregs_compat() 2818 * with the real channel 2819 */ 2820 if (pa->pa_function == 0) { 2821 compatchan = 0; 2822 } else if (pa->pa_function == 1) { 2823 compatchan = 1; 2824 } else { 2825 printf("%s: unexpected PCI function %d\n", 2826 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2827 return; 2828 } 2829 sc->sc_wdcdev.nchannels = 1; 2830 } else { 2831 sc->sc_wdcdev.nchannels = 2; 2832 } 2833 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2834 cp = &sc->pciide_channels[i]; 2835 if (sc->sc_wdcdev.nchannels > 1) { 2836 compatchan = i; 2837 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2838 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2839 printf("%s: %s channel ignored (disabled)\n", 2840 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2841 continue; 2842 } 2843 } 2844 if (pciide_chansetup(sc, i, interface) == 0) 2845 continue; 2846 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2847 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2848 &ctlsize, hpt_pci_intr); 2849 } else { 2850 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2851 &cmdsize, &ctlsize); 2852 } 2853 if (cp->hw_ok == 0) 2854 return; 2855 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2856 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2857 wdcattach(&cp->wdc_channel); 2858 hpt_setup_channel(&cp->wdc_channel); 2859 } 2860 2861 return; 2862 } 2863 2864 2865 void 2866 hpt_setup_channel(chp) 2867 struct channel_softc *chp; 2868 { 2869 struct ata_drive_datas *drvp; 2870 int drive; 2871 int cable; 2872 u_int32_t before, after; 2873 u_int32_t idedma_ctl; 2874 struct pciide_channel *cp = (struct pciide_channel*)chp; 2875 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2876 2877 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 2878 2879 /* setup DMA if needed */ 2880 pciide_channel_dma_setup(cp); 2881 2882 idedma_ctl = 0; 2883 2884 /* Per drive settings */ 2885 for (drive = 0; drive < 2; drive++) { 2886 drvp = &chp->ch_drive[drive]; 2887 /* If no drive, skip */ 2888 if ((drvp->drive_flags & DRIVE) == 0) 2889 continue; 2890 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 2891 HPT_IDETIM(chp->channel, drive)); 2892 2893 /* add timing values, setup DMA if needed */ 2894 if (drvp->drive_flags & DRIVE_UDMA) { 2895 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 2896 drvp->UDMA_mode > 2) 2897 drvp->UDMA_mode = 2; 2898 after = (sc->sc_wdcdev.nchannels == 2) ? 2899 hpt370_udma[drvp->UDMA_mode] : 2900 hpt366_udma[drvp->UDMA_mode]; 2901 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2902 } else if (drvp->drive_flags & DRIVE_DMA) { 2903 /* 2904 * use Multiword DMA. 2905 * Timings will be used for both PIO and DMA, so adjust 2906 * DMA mode if needed 2907 */ 2908 if (drvp->PIO_mode >= 3 && 2909 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2910 drvp->DMA_mode = drvp->PIO_mode - 2; 2911 } 2912 after = (sc->sc_wdcdev.nchannels == 2) ? 2913 hpt370_dma[drvp->DMA_mode] : 2914 hpt366_dma[drvp->DMA_mode]; 2915 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2916 } else { 2917 /* PIO only */ 2918 after = (sc->sc_wdcdev.nchannels == 2) ? 2919 hpt370_pio[drvp->PIO_mode] : 2920 hpt366_pio[drvp->PIO_mode]; 2921 } 2922 pci_conf_write(sc->sc_pc, sc->sc_tag, 2923 HPT_IDETIM(chp->channel, drive), after); 2924 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 2925 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 2926 after, before), DEBUG_PROBE); 2927 } 2928 if (idedma_ctl != 0) { 2929 /* Add software bits in status register */ 2930 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2931 IDEDMA_CTL, idedma_ctl); 2932 } 2933 pciide_print_modes(cp); 2934 } 2935 2936 int 2937 hpt_pci_intr(arg) 2938 void *arg; 2939 { 2940 struct pciide_softc *sc = arg; 2941 struct pciide_channel *cp; 2942 struct channel_softc *wdc_cp; 2943 int rv = 0; 2944 int dmastat, i, crv; 2945 2946 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2947 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2948 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 2949 if((dmastat & IDEDMA_CTL_INTR) == 0) 2950 continue; 2951 cp = &sc->pciide_channels[i]; 2952 wdc_cp = &cp->wdc_channel; 2953 crv = wdcintr(wdc_cp); 2954 if (crv == 0) { 2955 printf("%s:%d: bogus intr\n", 2956 sc->sc_wdcdev.sc_dev.dv_xname, i); 2957 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2958 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 2959 } else 2960 rv = 1; 2961 } 2962 return rv; 2963 } 2964 2965 2966 /* A macro to test product */ 2967 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 2968 2969 void 2970 pdc202xx_chip_map(sc, pa) 2971 struct pciide_softc *sc; 2972 struct pci_attach_args *pa; 2973 { 2974 struct pciide_channel *cp; 2975 int channel; 2976 pcireg_t interface, st, mode; 2977 bus_size_t cmdsize, ctlsize; 2978 2979 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2980 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 2981 DEBUG_PROBE); 2982 if (pciide_chipen(sc, pa) == 0) 2983 return; 2984 2985 /* turn off RAID mode */ 2986 st &= ~PDC2xx_STATE_IDERAID; 2987 2988 /* 2989 * can't rely on the PCI_CLASS_REG content if the chip was in raid 2990 * mode. We have to fake interface 2991 */ 2992 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 2993 if (st & PDC2xx_STATE_NATIVE) 2994 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2995 2996 printf("%s: bus-master DMA support present", 2997 sc->sc_wdcdev.sc_dev.dv_xname); 2998 pciide_mapreg_dma(sc, pa); 2999 printf("\n"); 3000 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3001 WDC_CAPABILITY_MODE; 3002 if (sc->sc_dma_ok) { 3003 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3004 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3005 sc->sc_wdcdev.irqack = pciide_irqack; 3006 } 3007 sc->sc_wdcdev.PIO_cap = 4; 3008 sc->sc_wdcdev.DMA_cap = 2; 3009 if (PDC_IS_262(sc)) 3010 sc->sc_wdcdev.UDMA_cap = 4; 3011 else 3012 sc->sc_wdcdev.UDMA_cap = 2; 3013 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3014 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3015 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3016 3017 /* setup failsafe defaults */ 3018 mode = 0; 3019 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3020 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3021 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3022 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3023 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3024 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3025 "initial timings 0x%x, now 0x%x\n", channel, 3026 pci_conf_read(sc->sc_pc, sc->sc_tag, 3027 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3028 DEBUG_PROBE); 3029 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3030 mode | PDC2xx_TIM_IORDYp); 3031 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3032 "initial timings 0x%x, now 0x%x\n", channel, 3033 pci_conf_read(sc->sc_pc, sc->sc_tag, 3034 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3035 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3036 mode); 3037 } 3038 3039 mode = PDC2xx_SCR_DMA; 3040 if (PDC_IS_262(sc)) { 3041 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3042 } else { 3043 /* the BIOS set it up this way */ 3044 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3045 } 3046 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3047 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3048 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3049 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3050 DEBUG_PROBE); 3051 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3052 3053 /* controller initial state register is OK even without BIOS */ 3054 /* Set DMA mode to IDE DMA compatibility */ 3055 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3056 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3057 DEBUG_PROBE); 3058 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3059 mode | 0x1); 3060 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3061 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3062 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3063 mode | 0x1); 3064 3065 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3066 cp = &sc->pciide_channels[channel]; 3067 if (pciide_chansetup(sc, channel, interface) == 0) 3068 continue; 3069 if ((st & (PDC_IS_262(sc) ? 3070 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3071 printf("%s: %s channel ignored (disabled)\n", 3072 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3073 continue; 3074 } 3075 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3076 pdc202xx_pci_intr); 3077 if (cp->hw_ok == 0) 3078 continue; 3079 if (pciide_chan_candisable(cp)) 3080 st &= ~(PDC_IS_262(sc) ? 3081 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3082 pciide_map_compat_intr(pa, cp, channel, interface); 3083 pdc202xx_setup_channel(&cp->wdc_channel); 3084 } 3085 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3086 DEBUG_PROBE); 3087 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3088 return; 3089 } 3090 3091 void 3092 pdc202xx_setup_channel(chp) 3093 struct channel_softc *chp; 3094 { 3095 struct ata_drive_datas *drvp; 3096 int drive; 3097 pcireg_t mode, st; 3098 u_int32_t idedma_ctl, scr, atapi; 3099 struct pciide_channel *cp = (struct pciide_channel*)chp; 3100 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3101 int channel = chp->channel; 3102 3103 /* setup DMA if needed */ 3104 pciide_channel_dma_setup(cp); 3105 3106 idedma_ctl = 0; 3107 3108 /* Per channel settings */ 3109 if (PDC_IS_262(sc)) { 3110 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3111 PDC262_U66); 3112 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3113 /* Trimm UDMA mode */ 3114 if ((st & PDC262_STATE_80P(channel)) != 0 || 3115 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3116 chp->ch_drive[0].UDMA_mode <= 2) || 3117 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3118 chp->ch_drive[1].UDMA_mode <= 2)) { 3119 if (chp->ch_drive[0].UDMA_mode > 2) 3120 chp->ch_drive[0].UDMA_mode = 2; 3121 if (chp->ch_drive[1].UDMA_mode > 2) 3122 chp->ch_drive[1].UDMA_mode = 2; 3123 } 3124 /* Set U66 if needed */ 3125 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3126 chp->ch_drive[0].UDMA_mode > 2) || 3127 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3128 chp->ch_drive[1].UDMA_mode > 2)) 3129 scr |= PDC262_U66_EN(channel); 3130 else 3131 scr &= ~PDC262_U66_EN(channel); 3132 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3133 PDC262_U66, scr); 3134 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3135 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3136 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3137 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3138 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3139 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3140 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3141 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3142 atapi = 0; 3143 else 3144 atapi = PDC262_ATAPI_UDMA; 3145 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3146 PDC262_ATAPI(channel), atapi); 3147 } 3148 } 3149 for (drive = 0; drive < 2; drive++) { 3150 drvp = &chp->ch_drive[drive]; 3151 /* If no drive, skip */ 3152 if ((drvp->drive_flags & DRIVE) == 0) 3153 continue; 3154 mode = 0; 3155 if (drvp->drive_flags & DRIVE_UDMA) { 3156 mode = PDC2xx_TIM_SET_MB(mode, 3157 pdc2xx_udma_mb[drvp->UDMA_mode]); 3158 mode = PDC2xx_TIM_SET_MC(mode, 3159 pdc2xx_udma_mc[drvp->UDMA_mode]); 3160 drvp->drive_flags &= ~DRIVE_DMA; 3161 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3162 } else if (drvp->drive_flags & DRIVE_DMA) { 3163 mode = PDC2xx_TIM_SET_MB(mode, 3164 pdc2xx_dma_mb[drvp->DMA_mode]); 3165 mode = PDC2xx_TIM_SET_MC(mode, 3166 pdc2xx_dma_mc[drvp->DMA_mode]); 3167 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3168 } else { 3169 mode = PDC2xx_TIM_SET_MB(mode, 3170 pdc2xx_dma_mb[0]); 3171 mode = PDC2xx_TIM_SET_MC(mode, 3172 pdc2xx_dma_mc[0]); 3173 } 3174 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3175 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3176 if (drvp->drive_flags & DRIVE_ATA) 3177 mode |= PDC2xx_TIM_PRE; 3178 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3179 if (drvp->PIO_mode >= 3) { 3180 mode |= PDC2xx_TIM_IORDY; 3181 if (drive == 0) 3182 mode |= PDC2xx_TIM_IORDYp; 3183 } 3184 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3185 "timings 0x%x\n", 3186 sc->sc_wdcdev.sc_dev.dv_xname, 3187 chp->channel, drive, mode), DEBUG_PROBE); 3188 pci_conf_write(sc->sc_pc, sc->sc_tag, 3189 PDC2xx_TIM(chp->channel, drive), mode); 3190 } 3191 if (idedma_ctl != 0) { 3192 /* Add software bits in status register */ 3193 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3194 IDEDMA_CTL, idedma_ctl); 3195 } 3196 pciide_print_modes(cp); 3197 } 3198 3199 int 3200 pdc202xx_pci_intr(arg) 3201 void *arg; 3202 { 3203 struct pciide_softc *sc = arg; 3204 struct pciide_channel *cp; 3205 struct channel_softc *wdc_cp; 3206 int i, rv, crv; 3207 u_int32_t scr; 3208 3209 rv = 0; 3210 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3211 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3212 cp = &sc->pciide_channels[i]; 3213 wdc_cp = &cp->wdc_channel; 3214 /* If a compat channel skip. */ 3215 if (cp->compat) 3216 continue; 3217 if (scr & PDC2xx_SCR_INT(i)) { 3218 crv = wdcintr(wdc_cp); 3219 if (crv == 0) 3220 printf("%s:%d: bogus intr\n", 3221 sc->sc_wdcdev.sc_dev.dv_xname, i); 3222 else 3223 rv = 1; 3224 } 3225 } 3226 return rv; 3227 } 3228 3229 void 3230 opti_chip_map(sc, pa) 3231 struct pciide_softc *sc; 3232 struct pci_attach_args *pa; 3233 { 3234 struct pciide_channel *cp; 3235 bus_size_t cmdsize, ctlsize; 3236 pcireg_t interface; 3237 u_int8_t init_ctrl; 3238 int channel; 3239 3240 if (pciide_chipen(sc, pa) == 0) 3241 return; 3242 printf("%s: bus-master DMA support present", 3243 sc->sc_wdcdev.sc_dev.dv_xname); 3244 pciide_mapreg_dma(sc, pa); 3245 printf("\n"); 3246 3247 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3248 WDC_CAPABILITY_MODE; 3249 sc->sc_wdcdev.PIO_cap = 4; 3250 if (sc->sc_dma_ok) { 3251 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3252 sc->sc_wdcdev.irqack = pciide_irqack; 3253 sc->sc_wdcdev.DMA_cap = 2; 3254 } 3255 sc->sc_wdcdev.set_modes = opti_setup_channel; 3256 3257 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3258 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3259 3260 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3261 OPTI_REG_INIT_CONTROL); 3262 3263 interface = PCI_INTERFACE(pa->pa_class); 3264 3265 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3266 cp = &sc->pciide_channels[channel]; 3267 if (pciide_chansetup(sc, channel, interface) == 0) 3268 continue; 3269 if (channel == 1 && 3270 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3271 printf("%s: %s channel ignored (disabled)\n", 3272 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3273 continue; 3274 } 3275 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3276 pciide_pci_intr); 3277 if (cp->hw_ok == 0) 3278 continue; 3279 pciide_map_compat_intr(pa, cp, channel, interface); 3280 if (cp->hw_ok == 0) 3281 continue; 3282 opti_setup_channel(&cp->wdc_channel); 3283 } 3284 } 3285 3286 void 3287 opti_setup_channel(chp) 3288 struct channel_softc *chp; 3289 { 3290 struct ata_drive_datas *drvp; 3291 struct pciide_channel *cp = (struct pciide_channel*)chp; 3292 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3293 int drive, spd; 3294 int mode[2]; 3295 u_int8_t rv, mr; 3296 3297 /* 3298 * The `Delay' and `Address Setup Time' fields of the 3299 * Miscellaneous Register are always zero initially. 3300 */ 3301 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3302 mr &= ~(OPTI_MISC_DELAY_MASK | 3303 OPTI_MISC_ADDR_SETUP_MASK | 3304 OPTI_MISC_INDEX_MASK); 3305 3306 /* Prime the control register before setting timing values */ 3307 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3308 3309 /* Determine the clockrate of the PCIbus the chip is attached to */ 3310 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3311 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3312 3313 /* setup DMA if needed */ 3314 pciide_channel_dma_setup(cp); 3315 3316 for (drive = 0; drive < 2; drive++) { 3317 drvp = &chp->ch_drive[drive]; 3318 /* If no drive, skip */ 3319 if ((drvp->drive_flags & DRIVE) == 0) { 3320 mode[drive] = -1; 3321 continue; 3322 } 3323 3324 if ((drvp->drive_flags & DRIVE_DMA)) { 3325 /* 3326 * Timings will be used for both PIO and DMA, 3327 * so adjust DMA mode if needed 3328 */ 3329 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3330 drvp->PIO_mode = drvp->DMA_mode + 2; 3331 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3332 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3333 drvp->PIO_mode - 2 : 0; 3334 if (drvp->DMA_mode == 0) 3335 drvp->PIO_mode = 0; 3336 3337 mode[drive] = drvp->DMA_mode + 5; 3338 } else 3339 mode[drive] = drvp->PIO_mode; 3340 3341 if (drive && mode[0] >= 0 && 3342 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3343 /* 3344 * Can't have two drives using different values 3345 * for `Address Setup Time'. 3346 * Slow down the faster drive to compensate. 3347 */ 3348 int d = (opti_tim_as[spd][mode[0]] > 3349 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3350 3351 mode[d] = mode[1-d]; 3352 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3353 chp->ch_drive[d].DMA_mode = 0; 3354 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3355 } 3356 } 3357 3358 for (drive = 0; drive < 2; drive++) { 3359 int m; 3360 if ((m = mode[drive]) < 0) 3361 continue; 3362 3363 /* Set the Address Setup Time and select appropriate index */ 3364 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3365 rv |= OPTI_MISC_INDEX(drive); 3366 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3367 3368 /* Set the pulse width and recovery timing parameters */ 3369 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3370 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3371 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3372 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3373 3374 /* Set the Enhanced Mode register appropriately */ 3375 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3376 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3377 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3378 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3379 } 3380 3381 /* Finally, enable the timings */ 3382 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3383 3384 pciide_print_modes(cp); 3385 } 3386
Indexes created Thu Oct 02 10:09:58 GMT 2025