pciide.c revision 1.42
1 /* $NetBSD: pciide.c,v 1.42 1999/08/30 12:49:21 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 38 /* 39 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by Christopher G. Demetriou 52 * for the NetBSD Project. 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * PCI IDE controller driver. 70 * 71 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 72 * sys/dev/pci/ppb.c, revision 1.16). 73 * 74 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 75 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 76 * 5/16/94" from the PCI SIG. 77 * 78 */ 79 80 #ifndef WDCDEBUG 81 #define WDCDEBUG 82 #endif 83 84 #define DEBUG_DMA 0x01 85 #define DEBUG_XFERS 0x02 86 #define DEBUG_FUNCS 0x08 87 #define DEBUG_PROBE 0x10 88 #ifdef WDCDEBUG 89 int wdcdebug_pciide_mask = 0; 90 #define WDCDEBUG_PRINT(args, level) \ 91 if (wdcdebug_pciide_mask & (level)) printf args 92 #else 93 #define WDCDEBUG_PRINT(args, level) 94 #endif 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/device.h> 98 #include <sys/malloc.h> 99 100 #include <vm/vm.h> 101 #include <vm/vm_param.h> 102 #include <vm/vm_kern.h> 103 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcivar.h> 106 #include <dev/pci/pcidevs.h> 107 #include <dev/pci/pciidereg.h> 108 #include <dev/pci/pciidevar.h> 109 #include <dev/pci/pciide_piix_reg.h> 110 #include <dev/pci/pciide_apollo_reg.h> 111 #include <dev/pci/pciide_cmd_reg.h> 112 #include <dev/pci/pciide_cy693_reg.h> 113 #include <dev/pci/pciide_sis_reg.h> 114 #include <dev/pci/pciide_acer_reg.h> 115 #include <dev/pci/pciide_pdc202xx_reg.h> 116 #include <dev/ata/atavar.h> 117 #include <dev/ic/wdcreg.h> 118 #include <dev/ic/wdcvar.h> 119 120 #if BYTE_ORDER == BIG_ENDIAN 121 #include <machine/bswap.h> 122 #define htopci(x) bswap32(x) 123 #define pcitoh(x) bswap32(x) 124 #else 125 #define htopci(x) (x) 126 #define pcitoh(x) (x) 127 #endif 128 129 /* inlines for reading/writing 8-bit PCI registers */ 130 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 131 int)); 132 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 133 int, u_int8_t)); 134 135 static __inline u_int8_t 136 pciide_pci_read(pc, pa, reg) 137 pci_chipset_tag_t pc; 138 pcitag_t pa; 139 int reg; 140 { 141 142 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 143 ((reg & 0x03) * 8) & 0xff); 144 } 145 146 static __inline void 147 pciide_pci_write(pc, pa, reg, val) 148 pci_chipset_tag_t pc; 149 pcitag_t pa; 150 int reg; 151 u_int8_t val; 152 { 153 pcireg_t pcival; 154 155 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 156 pcival &= ~(0xff << ((reg & 0x03) * 8)); 157 pcival |= (val << ((reg & 0x03) * 8)); 158 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 159 } 160 161 struct pciide_softc { 162 struct wdc_softc sc_wdcdev; /* common wdc definitions */ 163 pci_chipset_tag_t sc_pc; /* PCI registers info */ 164 pcitag_t sc_tag; 165 void *sc_pci_ih; /* PCI interrupt handle */ 166 int sc_dma_ok; /* bus-master DMA info */ 167 bus_space_tag_t sc_dma_iot; 168 bus_space_handle_t sc_dma_ioh; 169 bus_dma_tag_t sc_dmat; 170 /* Chip description */ 171 const struct pciide_product_desc *sc_pp; 172 /* common definitions */ 173 struct channel_softc *wdc_chanarray[PCIIDE_NUM_CHANNELS]; 174 /* internal bookkeeping */ 175 struct pciide_channel { /* per-channel data */ 176 struct channel_softc wdc_channel; /* generic part */ 177 char *name; 178 int hw_ok; /* hardware mapped & OK? */ 179 int compat; /* is it compat? */ 180 void *ih; /* compat or pci handle */ 181 /* DMA tables and DMA map for xfer, for each drive */ 182 struct pciide_dma_maps { 183 bus_dmamap_t dmamap_table; 184 struct idedma_table *dma_table; 185 bus_dmamap_t dmamap_xfer; 186 } dma_maps[2]; 187 } pciide_channels[PCIIDE_NUM_CHANNELS]; 188 }; 189 190 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 191 192 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void piix_setup_channel __P((struct channel_softc*)); 194 void piix3_4_setup_channel __P((struct channel_softc*)); 195 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 196 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 197 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 198 199 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 200 void apollo_setup_channel __P((struct channel_softc*)); 201 202 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 203 void cmd0643_6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 204 void cmd0643_6_setup_channel __P((struct channel_softc*)); 205 void cmd_channel_map __P((struct pci_attach_args *, 206 struct pciide_softc *, int)); 207 int cmd_pci_intr __P((void *)); 208 209 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 210 void cy693_setup_channel __P((struct channel_softc*)); 211 212 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 213 void sis_setup_channel __P((struct channel_softc*)); 214 215 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 216 void acer_setup_channel __P((struct channel_softc*)); 217 int acer_pci_intr __P((void *)); 218 219 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 220 void pdc202xx_setup_channel __P((struct channel_softc*)); 221 int pdc202xx_pci_intr __P((void *)); 222 223 void pciide_channel_dma_setup __P((struct pciide_channel *)); 224 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 225 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 226 void pciide_dma_start __P((void*, int, int, int)); 227 int pciide_dma_finish __P((void*, int, int, int)); 228 void pciide_print_modes __P((struct pciide_channel *)); 229 230 struct pciide_product_desc { 231 u_int32_t ide_product; 232 int ide_flags; 233 const char *ide_name; 234 /* map and setup chip, probe drives */ 235 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 236 }; 237 238 /* Flags for ide_flags */ 239 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 240 241 /* Default product description for devices not known from this controller */ 242 const struct pciide_product_desc default_product_desc = { 243 0, 244 0, 245 "Generic PCI IDE controller", 246 default_chip_map, 247 }; 248 249 const struct pciide_product_desc pciide_intel_products[] = { 250 { PCI_PRODUCT_INTEL_82092AA, 251 0, 252 "Intel 82092AA IDE controller", 253 default_chip_map, 254 }, 255 { PCI_PRODUCT_INTEL_82371FB_IDE, 256 0, 257 "Intel 82371FB IDE controller (PIIX)", 258 piix_chip_map, 259 }, 260 { PCI_PRODUCT_INTEL_82371SB_IDE, 261 0, 262 "Intel 82371SB IDE Interface (PIIX3)", 263 piix_chip_map, 264 }, 265 { PCI_PRODUCT_INTEL_82371AB_IDE, 266 0, 267 "Intel 82371AB IDE controller (PIIX4)", 268 piix_chip_map, 269 }, 270 { PCI_PRODUCT_INTEL_82801AA_IDE, 271 0, 272 "Intel 82801AA IDE Controller (ICH)", 273 piix_chip_map, 274 }, 275 { PCI_PRODUCT_INTEL_82801AB_IDE, 276 0, 277 "Intel 82801AB IDE Controller (ICH0)", 278 piix_chip_map, 279 }, 280 { 0, 281 0, 282 NULL, 283 } 284 }; 285 286 const struct pciide_product_desc pciide_cmd_products[] = { 287 { PCI_PRODUCT_CMDTECH_640, 288 0, 289 "CMD Technology PCI0640", 290 cmd_chip_map 291 }, 292 { PCI_PRODUCT_CMDTECH_643, 293 0, 294 "CMD Technology PCI0643", 295 cmd0643_6_chip_map, 296 }, 297 { PCI_PRODUCT_CMDTECH_646, 298 0, 299 "CMD Technology PCI0646", 300 cmd0643_6_chip_map, 301 }, 302 { 0, 303 0, 304 NULL, 305 } 306 }; 307 308 const struct pciide_product_desc pciide_via_products[] = { 309 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 310 0, 311 "VIA Technologies VT82C586 (Apollo VP) IDE Controller", 312 apollo_chip_map, 313 }, 314 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 315 0, 316 "VIA Technologies VT82C586A IDE Controller", 317 apollo_chip_map, 318 }, 319 { 0, 320 0, 321 NULL, 322 } 323 }; 324 325 const struct pciide_product_desc pciide_cypress_products[] = { 326 { PCI_PRODUCT_CONTAQ_82C693, 327 0, 328 "Contaq Microsystems CY82C693 IDE Controller", 329 cy693_chip_map, 330 }, 331 { 0, 332 0, 333 NULL, 334 } 335 }; 336 337 const struct pciide_product_desc pciide_sis_products[] = { 338 { PCI_PRODUCT_SIS_5597_IDE, 339 0, 340 "Silicon Integrated System 5597/5598 IDE controller", 341 sis_chip_map, 342 }, 343 { 0, 344 0, 345 NULL, 346 } 347 }; 348 349 const struct pciide_product_desc pciide_acer_products[] = { 350 { PCI_PRODUCT_ALI_M5229, 351 0, 352 "Acer Labs M5229 UDMA IDE Controller", 353 acer_chip_map, 354 }, 355 { 0, 356 0, 357 NULL, 358 } 359 }; 360 361 const struct pciide_product_desc pciide_promise_products[] = { 362 { PCI_PRODUCT_PROMISE_ULTRA33, 363 IDE_PCI_CLASS_OVERRIDE, 364 "Promise Ultra33/ATA Bus Master IDE Accelerator", 365 pdc202xx_chip_map, 366 }, 367 { PCI_PRODUCT_PROMISE_ULTRA66, 368 IDE_PCI_CLASS_OVERRIDE, 369 "Promise Ultra66/ATA Bus Master IDE Accelerator", 370 pdc202xx_chip_map, 371 }, 372 { 0, 373 0, 374 NULL, 375 } 376 }; 377 378 struct pciide_vendor_desc { 379 u_int32_t ide_vendor; 380 const struct pciide_product_desc *ide_products; 381 }; 382 383 const struct pciide_vendor_desc pciide_vendors[] = { 384 { PCI_VENDOR_INTEL, pciide_intel_products }, 385 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 386 { PCI_VENDOR_VIATECH, pciide_via_products }, 387 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 388 { PCI_VENDOR_SIS, pciide_sis_products }, 389 { PCI_VENDOR_ALI, pciide_acer_products }, 390 { PCI_VENDOR_PROMISE, pciide_promise_products }, 391 { 0, NULL } 392 }; 393 394 #define PCIIDE_CHANNEL_NAME(chan) ((chan) == 0 ? "primary" : "secondary") 395 396 /* options passed via the 'flags' config keyword */ 397 #define PCIIDE_OPTIONS_DMA 0x01 398 399 int pciide_match __P((struct device *, struct cfdata *, void *)); 400 void pciide_attach __P((struct device *, struct device *, void *)); 401 402 struct cfattach pciide_ca = { 403 sizeof(struct pciide_softc), pciide_match, pciide_attach 404 }; 405 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 406 int pciide_mapregs_compat __P(( struct pci_attach_args *, 407 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 408 int pciide_mapregs_native __P((struct pci_attach_args *, 409 struct pciide_channel *, bus_size_t *, bus_size_t *, 410 int (*pci_intr) __P((void *)))); 411 void pciide_mapreg_dma __P((struct pciide_softc *, 412 struct pci_attach_args *)); 413 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 414 void pciide_mapchan __P((struct pci_attach_args *, 415 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 416 int (*pci_intr) __P((void *)))); 417 int pciiide_chan_candisable __P((struct pciide_channel *)); 418 void pciide_map_compat_intr __P(( struct pci_attach_args *, 419 struct pciide_channel *, int, int)); 420 int pciide_print __P((void *, const char *pnp)); 421 int pciide_compat_intr __P((void *)); 422 int pciide_pci_intr __P((void *)); 423 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 424 425 const struct pciide_product_desc * 426 pciide_lookup_product(id) 427 u_int32_t id; 428 { 429 const struct pciide_product_desc *pp; 430 const struct pciide_vendor_desc *vp; 431 432 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 433 if (PCI_VENDOR(id) == vp->ide_vendor) 434 break; 435 436 if ((pp = vp->ide_products) == NULL) 437 return NULL; 438 439 for (; pp->ide_name != NULL; pp++) 440 if (PCI_PRODUCT(id) == pp->ide_product) 441 break; 442 443 if (pp->ide_name == NULL) 444 return NULL; 445 return pp; 446 } 447 448 int 449 pciide_match(parent, match, aux) 450 struct device *parent; 451 struct cfdata *match; 452 void *aux; 453 { 454 struct pci_attach_args *pa = aux; 455 const struct pciide_product_desc *pp; 456 457 /* 458 * Check the ID register to see that it's a PCI IDE controller. 459 * If it is, we assume that we can deal with it; it _should_ 460 * work in a standardized way... 461 */ 462 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 463 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 464 return (1); 465 } 466 467 /* 468 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 469 * controllers. Let see if we can deal with it anyway. 470 */ 471 pp = pciide_lookup_product(pa->pa_id); 472 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 473 return (1); 474 } 475 476 return (0); 477 } 478 479 void 480 pciide_attach(parent, self, aux) 481 struct device *parent, *self; 482 void *aux; 483 { 484 struct pci_attach_args *pa = aux; 485 pci_chipset_tag_t pc = pa->pa_pc; 486 pcitag_t tag = pa->pa_tag; 487 struct pciide_softc *sc = (struct pciide_softc *)self; 488 pcireg_t csr; 489 char devinfo[256]; 490 491 sc->sc_pp = pciide_lookup_product(pa->pa_id); 492 if (sc->sc_pp == NULL) { 493 sc->sc_pp = &default_product_desc; 494 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 495 printf(": %s (rev. 0x%02x)\n", devinfo, 496 PCI_REVISION(pa->pa_class)); 497 } else { 498 printf(": %s\n", sc->sc_pp->ide_name); 499 } 500 sc->sc_pc = pa->pa_pc; 501 sc->sc_tag = pa->pa_tag; 502 #ifdef WDCDEBUG 503 if (wdcdebug_pciide_mask & DEBUG_PROBE) 504 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 505 #endif 506 507 sc->sc_pp->chip_map(sc, pa); 508 509 if (sc->sc_dma_ok) { 510 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 511 csr |= PCI_COMMAND_MASTER_ENABLE; 512 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 513 } 514 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 515 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 516 } 517 518 /* tell wether the chip is enabled or not */ 519 int 520 pciide_chipen(sc, pa) 521 struct pciide_softc *sc; 522 struct pci_attach_args *pa; 523 { 524 pcireg_t csr; 525 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 526 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 527 PCI_COMMAND_STATUS_REG); 528 printf("%s: device disabled (at %s)\n", 529 sc->sc_wdcdev.sc_dev.dv_xname, 530 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 531 "device" : "bridge"); 532 return 0; 533 } 534 return 1; 535 } 536 537 int 538 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 539 struct pci_attach_args *pa; 540 struct pciide_channel *cp; 541 int compatchan; 542 bus_size_t *cmdsizep, *ctlsizep; 543 { 544 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 545 struct channel_softc *wdc_cp = &cp->wdc_channel; 546 int rv = 1; 547 548 cp->compat = 1; 549 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 550 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 551 552 wdc_cp->cmd_iot = pa->pa_iot; 553 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 554 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 555 printf("%s: couldn't map %s channel cmd regs\n", 556 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 557 rv = 0; 558 } 559 560 wdc_cp->ctl_iot = pa->pa_iot; 561 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 562 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 563 printf("%s: couldn't map %s channel ctl regs\n", 564 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 565 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 566 PCIIDE_COMPAT_CMD_SIZE); 567 rv = 0; 568 } 569 570 return (rv); 571 } 572 573 int 574 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 575 struct pci_attach_args * pa; 576 struct pciide_channel *cp; 577 bus_size_t *cmdsizep, *ctlsizep; 578 int (*pci_intr) __P((void *)); 579 { 580 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 581 struct channel_softc *wdc_cp = &cp->wdc_channel; 582 const char *intrstr; 583 pci_intr_handle_t intrhandle; 584 585 cp->compat = 0; 586 587 if (sc->sc_pci_ih == NULL) { 588 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 589 pa->pa_intrline, &intrhandle) != 0) { 590 printf("%s: couldn't map native-PCI interrupt\n", 591 sc->sc_wdcdev.sc_dev.dv_xname); 592 return 0; 593 } 594 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 595 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 596 intrhandle, IPL_BIO, pci_intr, sc); 597 if (sc->sc_pci_ih != NULL) { 598 printf("%s: using %s for native-PCI interrupt\n", 599 sc->sc_wdcdev.sc_dev.dv_xname, 600 intrstr ? intrstr : "unknown interrupt"); 601 } else { 602 printf("%s: couldn't establish native-PCI interrupt", 603 sc->sc_wdcdev.sc_dev.dv_xname); 604 if (intrstr != NULL) 605 printf(" at %s", intrstr); 606 printf("\n"); 607 return 0; 608 } 609 } 610 cp->ih = sc->sc_pci_ih; 611 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 612 PCI_MAPREG_TYPE_IO, 0, 613 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 614 printf("%s: couldn't map %s channel cmd regs\n", 615 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 616 return 0; 617 } 618 619 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 620 PCI_MAPREG_TYPE_IO, 0, 621 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 622 printf("%s: couldn't map %s channel ctl regs\n", 623 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 624 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 625 return 0; 626 } 627 return (1); 628 } 629 630 void 631 pciide_mapreg_dma(sc, pa) 632 struct pciide_softc *sc; 633 struct pci_attach_args *pa; 634 { 635 /* 636 * Map DMA registers 637 * 638 * Note that sc_dma_ok is the right variable to test to see if 639 * DMA can be done. If the interface doesn't support DMA, 640 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 641 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 642 * non-zero if the interface supports DMA and the registers 643 * could be mapped. 644 * 645 * XXX Note that despite the fact that the Bus Master IDE specs 646 * XXX say that "The bus master IDE function uses 16 bytes of IO 647 * XXX space," some controllers (at least the United 648 * XXX Microelectronics UM8886BF) place it in memory space. 649 * XXX eventually, we should probably read the register and check 650 * XXX which type it is. Either that or 'quirk' certain devices. 651 */ 652 sc->sc_dma_ok = (pci_mapreg_map(pa, 653 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0, 654 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 655 sc->sc_dmat = pa->pa_dmat; 656 if (sc->sc_dma_ok == 0) { 657 printf(", but unused (couldn't map registers)"); 658 } else { 659 sc->sc_wdcdev.dma_arg = sc; 660 sc->sc_wdcdev.dma_init = pciide_dma_init; 661 sc->sc_wdcdev.dma_start = pciide_dma_start; 662 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 663 } 664 } 665 int 666 pciide_compat_intr(arg) 667 void *arg; 668 { 669 struct pciide_channel *cp = arg; 670 671 #ifdef DIAGNOSTIC 672 /* should only be called for a compat channel */ 673 if (cp->compat == 0) 674 panic("pciide compat intr called for non-compat chan %p\n", cp); 675 #endif 676 return (wdcintr(&cp->wdc_channel)); 677 } 678 679 int 680 pciide_pci_intr(arg) 681 void *arg; 682 { 683 struct pciide_softc *sc = arg; 684 struct pciide_channel *cp; 685 struct channel_softc *wdc_cp; 686 int i, rv, crv; 687 688 rv = 0; 689 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 690 cp = &sc->pciide_channels[i]; 691 wdc_cp = &cp->wdc_channel; 692 693 /* If a compat channel skip. */ 694 if (cp->compat) 695 continue; 696 /* if this channel not waiting for intr, skip */ 697 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 698 continue; 699 700 crv = wdcintr(wdc_cp); 701 if (crv == 0) 702 ; /* leave rv alone */ 703 else if (crv == 1) 704 rv = 1; /* claim the intr */ 705 else if (rv == 0) /* crv should be -1 in this case */ 706 rv = crv; /* if we've done no better, take it */ 707 } 708 return (rv); 709 } 710 711 void 712 pciide_channel_dma_setup(cp) 713 struct pciide_channel *cp; 714 { 715 int drive; 716 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 717 struct ata_drive_datas *drvp; 718 719 for (drive = 0; drive < 2; drive++) { 720 drvp = &cp->wdc_channel.ch_drive[drive]; 721 /* If no drive, skip */ 722 if ((drvp->drive_flags & DRIVE) == 0) 723 continue; 724 /* setup DMA if needed */ 725 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 726 (drvp->drive_flags & DRIVE_UDMA) == 0) || 727 sc->sc_dma_ok == 0) { 728 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 729 continue; 730 } 731 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 732 != 0) { 733 /* Abort DMA setup */ 734 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 735 continue; 736 } 737 } 738 } 739 740 int 741 pciide_dma_table_setup(sc, channel, drive) 742 struct pciide_softc *sc; 743 int channel, drive; 744 { 745 bus_dma_segment_t seg; 746 int error, rseg; 747 const bus_size_t dma_table_size = 748 sizeof(struct idedma_table) * NIDEDMA_TABLES; 749 struct pciide_dma_maps *dma_maps = 750 &sc->pciide_channels[channel].dma_maps[drive]; 751 752 /* If table was already allocated, just return */ 753 if (dma_maps->dma_table) 754 return 0; 755 756 /* Allocate memory for the DMA tables and map it */ 757 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 758 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 759 BUS_DMA_NOWAIT)) != 0) { 760 printf("%s:%d: unable to allocate table DMA for " 761 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 762 channel, drive, error); 763 return error; 764 } 765 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 766 dma_table_size, 767 (caddr_t *)&dma_maps->dma_table, 768 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 769 printf("%s:%d: unable to map table DMA for" 770 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 771 channel, drive, error); 772 return error; 773 } 774 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 775 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 776 seg.ds_addr), DEBUG_PROBE); 777 778 /* Create and load table DMA map for this disk */ 779 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 780 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 781 &dma_maps->dmamap_table)) != 0) { 782 printf("%s:%d: unable to create table DMA map for " 783 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 784 channel, drive, error); 785 return error; 786 } 787 if ((error = bus_dmamap_load(sc->sc_dmat, 788 dma_maps->dmamap_table, 789 dma_maps->dma_table, 790 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 791 printf("%s:%d: unable to load table DMA map for " 792 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 793 channel, drive, error); 794 return error; 795 } 796 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 797 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 798 /* Create a xfer DMA map for this drive */ 799 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 800 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 801 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 802 &dma_maps->dmamap_xfer)) != 0) { 803 printf("%s:%d: unable to create xfer DMA map for " 804 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 805 channel, drive, error); 806 return error; 807 } 808 return 0; 809 } 810 811 int 812 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 813 void *v; 814 int channel, drive; 815 void *databuf; 816 size_t datalen; 817 int flags; 818 { 819 struct pciide_softc *sc = v; 820 int error, seg; 821 struct pciide_dma_maps *dma_maps = 822 &sc->pciide_channels[channel].dma_maps[drive]; 823 824 error = bus_dmamap_load(sc->sc_dmat, 825 dma_maps->dmamap_xfer, 826 databuf, datalen, NULL, BUS_DMA_NOWAIT); 827 if (error) { 828 printf("%s:%d: unable to load xfer DMA map for" 829 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 830 channel, drive, error); 831 return error; 832 } 833 834 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 835 dma_maps->dmamap_xfer->dm_mapsize, 836 (flags & WDC_DMA_READ) ? 837 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 838 839 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 840 #ifdef DIAGNOSTIC 841 /* A segment must not cross a 64k boundary */ 842 { 843 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 844 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 845 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 846 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 847 printf("pciide_dma: segment %d physical addr 0x%lx" 848 " len 0x%lx not properly aligned\n", 849 seg, phys, len); 850 panic("pciide_dma: buf align"); 851 } 852 } 853 #endif 854 dma_maps->dma_table[seg].base_addr = 855 htopci(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 856 dma_maps->dma_table[seg].byte_count = 857 htopci(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 858 IDEDMA_BYTE_COUNT_MASK); 859 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 860 seg, pcitoh(dma_maps->dma_table[seg].byte_count), 861 pcitoh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 862 863 } 864 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 865 htopci(IDEDMA_BYTE_COUNT_EOT); 866 867 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 868 dma_maps->dmamap_table->dm_mapsize, 869 BUS_DMASYNC_PREWRITE); 870 871 /* Maps are ready. Start DMA function */ 872 #ifdef DIAGNOSTIC 873 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 874 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 875 dma_maps->dmamap_table->dm_segs[0].ds_addr); 876 panic("pciide_dma_init: table align"); 877 } 878 #endif 879 880 /* Clear status bits */ 881 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 882 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 883 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 884 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 885 /* Write table addr */ 886 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 887 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 888 dma_maps->dmamap_table->dm_segs[0].ds_addr); 889 /* set read/write */ 890 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 891 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 892 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 893 return 0; 894 } 895 896 void 897 pciide_dma_start(v, channel, drive, flags) 898 void *v; 899 int channel, drive, flags; 900 { 901 struct pciide_softc *sc = v; 902 903 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 904 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 905 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 906 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 907 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 908 } 909 910 int 911 pciide_dma_finish(v, channel, drive, flags) 912 void *v; 913 int channel, drive; 914 int flags; 915 { 916 struct pciide_softc *sc = v; 917 u_int8_t status; 918 struct pciide_dma_maps *dma_maps = 919 &sc->pciide_channels[channel].dma_maps[drive]; 920 921 /* Unload the map of the data buffer */ 922 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 923 dma_maps->dmamap_xfer->dm_mapsize, 924 (flags & WDC_DMA_READ) ? 925 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 926 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 927 928 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 929 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 930 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 931 DEBUG_XFERS); 932 933 /* stop DMA channel */ 934 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 935 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 936 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 937 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 938 939 /* Clear status bits */ 940 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 941 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 942 status); 943 944 if ((status & IDEDMA_CTL_ERR) != 0) { 945 printf("%s:%d:%d: Bus-Master DMA error: status=0x%x\n", 946 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 947 return -1; 948 } 949 950 if ((flags & WDC_DMA_POLL) == 0 && (status & IDEDMA_CTL_INTR) == 0) { 951 printf("%s:%d:%d: Bus-Master DMA error: missing interrupt, " 952 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 953 drive, status); 954 return -1; 955 } 956 957 if ((status & IDEDMA_CTL_ACT) != 0) { 958 /* data underrun, may be a valid condition for ATAPI */ 959 return 1; 960 } 961 return 0; 962 } 963 964 /* some common code used by several chip_map */ 965 int 966 pciide_chansetup(sc, channel, interface) 967 struct pciide_softc *sc; 968 int channel; 969 pcireg_t interface; 970 { 971 struct pciide_channel *cp = &sc->pciide_channels[channel]; 972 sc->wdc_chanarray[channel] = &cp->wdc_channel; 973 cp->name = PCIIDE_CHANNEL_NAME(channel); 974 cp->wdc_channel.channel = channel; 975 cp->wdc_channel.wdc = &sc->sc_wdcdev; 976 cp->wdc_channel.ch_queue = 977 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 978 if (cp->wdc_channel.ch_queue == NULL) { 979 printf("%s %s channel: " 980 "can't allocate memory for command queue", 981 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 982 return 0; 983 } 984 printf("%s: %s channel %s to %s mode\n", 985 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 986 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 987 "configured" : "wired", 988 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 989 "native-PCI" : "compatibility"); 990 return 1; 991 } 992 993 /* some common code used by several chip channel_map */ 994 void 995 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 996 struct pci_attach_args *pa; 997 struct pciide_channel *cp; 998 pcireg_t interface; 999 bus_size_t *cmdsizep, *ctlsizep; 1000 int (*pci_intr) __P((void *)); 1001 { 1002 struct channel_softc *wdc_cp = &cp->wdc_channel; 1003 1004 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1005 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1006 pci_intr); 1007 else 1008 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1009 wdc_cp->channel, cmdsizep, ctlsizep); 1010 1011 if (cp->hw_ok == 0) 1012 return; 1013 wdc_cp->data32iot = wdc_cp->cmd_iot; 1014 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1015 wdcattach(wdc_cp); 1016 } 1017 1018 /* 1019 * Generic code to call to know if a channel can be disabled. Return 1 1020 * if channel can be disabled, 0 if not 1021 */ 1022 int 1023 pciiide_chan_candisable(cp) 1024 struct pciide_channel *cp; 1025 { 1026 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1027 struct channel_softc *wdc_cp = &cp->wdc_channel; 1028 1029 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1030 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1031 printf("%s: disabling %s channel (no drives)\n", 1032 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1033 cp->hw_ok = 0; 1034 return 1; 1035 } 1036 return 0; 1037 } 1038 1039 /* 1040 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1041 * Set hw_ok=0 on failure 1042 */ 1043 void 1044 pciide_map_compat_intr(pa, cp, compatchan, interface) 1045 struct pci_attach_args *pa; 1046 struct pciide_channel *cp; 1047 int compatchan, interface; 1048 { 1049 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1050 struct channel_softc *wdc_cp = &cp->wdc_channel; 1051 1052 if (cp->hw_ok == 0) 1053 return; 1054 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1055 return; 1056 1057 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1058 pa, compatchan, pciide_compat_intr, cp); 1059 if (cp->ih == NULL) { 1060 printf("%s: no compatibility interrupt for use by %s " 1061 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1062 cp->hw_ok = 0; 1063 } 1064 } 1065 1066 void 1067 pciide_print_modes(cp) 1068 struct pciide_channel *cp; 1069 { 1070 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1071 int drive; 1072 struct channel_softc *chp; 1073 struct ata_drive_datas *drvp; 1074 1075 chp = &cp->wdc_channel; 1076 for (drive = 0; drive < 2; drive++) { 1077 drvp = &chp->ch_drive[drive]; 1078 if ((drvp->drive_flags & DRIVE) == 0) 1079 continue; 1080 printf("%s(%s:%d:%d): using PIO mode %d", 1081 drvp->drv_softc->dv_xname, 1082 sc->sc_wdcdev.sc_dev.dv_xname, 1083 chp->channel, drive, drvp->PIO_mode); 1084 if (drvp->drive_flags & DRIVE_DMA) 1085 printf(", DMA mode %d", drvp->DMA_mode); 1086 if (drvp->drive_flags & DRIVE_UDMA) 1087 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1088 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1089 printf(" (using DMA data transfers)"); 1090 printf("\n"); 1091 } 1092 } 1093 1094 void 1095 default_chip_map(sc, pa) 1096 struct pciide_softc *sc; 1097 struct pci_attach_args *pa; 1098 { 1099 struct pciide_channel *cp; 1100 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1101 sc->sc_tag, PCI_CLASS_REG)); 1102 pcireg_t csr; 1103 int channel, drive; 1104 struct ata_drive_datas *drvp; 1105 u_int8_t idedma_ctl; 1106 bus_size_t cmdsize, ctlsize; 1107 char *failreason; 1108 1109 if (pciide_chipen(sc, pa) == 0) 1110 return; 1111 1112 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1113 printf("%s: bus-master DMA support present", 1114 sc->sc_wdcdev.sc_dev.dv_xname); 1115 if (sc->sc_pp == &default_product_desc && 1116 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1117 PCIIDE_OPTIONS_DMA) == 0) { 1118 printf(", but unused (no driver support)"); 1119 sc->sc_dma_ok = 0; 1120 } else { 1121 pciide_mapreg_dma(sc, pa); 1122 if (sc->sc_dma_ok != 0) 1123 printf(", used without full driver " 1124 "support"); 1125 } 1126 } else { 1127 printf("%s: hardware does not support DMA", 1128 sc->sc_wdcdev.sc_dev.dv_xname); 1129 sc->sc_dma_ok = 0; 1130 } 1131 printf("\n"); 1132 if (sc->sc_dma_ok) 1133 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1134 sc->sc_wdcdev.PIO_cap = 0; 1135 sc->sc_wdcdev.DMA_cap = 0; 1136 1137 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1138 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1139 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1140 1141 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1142 cp = &sc->pciide_channels[channel]; 1143 if (pciide_chansetup(sc, channel, interface) == 0) 1144 continue; 1145 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1146 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1147 &ctlsize, pciide_pci_intr); 1148 } else { 1149 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1150 channel, &cmdsize, &ctlsize); 1151 } 1152 if (cp->hw_ok == 0) 1153 continue; 1154 /* 1155 * Check to see if something appears to be there. 1156 */ 1157 failreason = NULL; 1158 if (!wdcprobe(&cp->wdc_channel)) { 1159 failreason = "not responding; disabled or no drives?"; 1160 goto next; 1161 } 1162 /* 1163 * Now, make sure it's actually attributable to this PCI IDE 1164 * channel by trying to access the channel again while the 1165 * PCI IDE controller's I/O space is disabled. (If the 1166 * channel no longer appears to be there, it belongs to 1167 * this controller.) YUCK! 1168 */ 1169 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1170 PCI_COMMAND_STATUS_REG); 1171 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1172 csr & ~PCI_COMMAND_IO_ENABLE); 1173 if (wdcprobe(&cp->wdc_channel)) 1174 failreason = "other hardware responding at addresses"; 1175 pci_conf_write(sc->sc_pc, sc->sc_tag, 1176 PCI_COMMAND_STATUS_REG, csr); 1177 next: 1178 if (failreason) { 1179 printf("%s: %s channel ignored (%s)\n", 1180 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1181 failreason); 1182 cp->hw_ok = 0; 1183 bus_space_unmap(cp->wdc_channel.cmd_iot, 1184 cp->wdc_channel.cmd_ioh, cmdsize); 1185 bus_space_unmap(cp->wdc_channel.ctl_iot, 1186 cp->wdc_channel.ctl_ioh, ctlsize); 1187 } else { 1188 pciide_map_compat_intr(pa, cp, channel, interface); 1189 } 1190 if (cp->hw_ok) { 1191 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1192 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1193 wdcattach(&cp->wdc_channel); 1194 } 1195 } 1196 1197 if (sc->sc_dma_ok == 0) 1198 return; 1199 1200 /* Allocate DMA maps */ 1201 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1202 idedma_ctl = 0; 1203 cp = &sc->pciide_channels[channel]; 1204 for (drive = 0; drive < 2; drive++) { 1205 drvp = &cp->wdc_channel.ch_drive[drive]; 1206 /* If no drive, skip */ 1207 if ((drvp->drive_flags & DRIVE) == 0) 1208 continue; 1209 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1210 continue; 1211 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1212 /* Abort DMA setup */ 1213 printf("%s:%d:%d: can't allocate DMA maps, " 1214 "using PIO transfers\n", 1215 sc->sc_wdcdev.sc_dev.dv_xname, 1216 channel, drive); 1217 drvp->drive_flags &= ~DRIVE_DMA; 1218 } 1219 printf("%s:%d:%d: using DMA data transfers\n", 1220 sc->sc_wdcdev.sc_dev.dv_xname, 1221 channel, drive); 1222 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1223 } 1224 if (idedma_ctl != 0) { 1225 /* Add software bits in status register */ 1226 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1227 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1228 idedma_ctl); 1229 } 1230 } 1231 } 1232 1233 void 1234 piix_chip_map(sc, pa) 1235 struct pciide_softc *sc; 1236 struct pci_attach_args *pa; 1237 { 1238 struct pciide_channel *cp; 1239 int channel; 1240 u_int32_t idetim; 1241 bus_size_t cmdsize, ctlsize; 1242 1243 if (pciide_chipen(sc, pa) == 0) 1244 return; 1245 1246 printf("%s: bus-master DMA support present", 1247 sc->sc_wdcdev.sc_dev.dv_xname); 1248 pciide_mapreg_dma(sc, pa); 1249 printf("\n"); 1250 if (sc->sc_dma_ok) { 1251 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1252 switch(sc->sc_pp->ide_product) { 1253 case PCI_PRODUCT_INTEL_82371AB_IDE: 1254 case PCI_PRODUCT_INTEL_82801AA_IDE: 1255 case PCI_PRODUCT_INTEL_82801AB_IDE: 1256 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1257 } 1258 } 1259 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1260 WDC_CAPABILITY_MODE; 1261 sc->sc_wdcdev.PIO_cap = 4; 1262 sc->sc_wdcdev.DMA_cap = 2; 1263 sc->sc_wdcdev.UDMA_cap = 1264 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1265 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1266 sc->sc_wdcdev.set_modes = piix_setup_channel; 1267 else 1268 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1269 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1270 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1271 1272 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1273 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1274 DEBUG_PROBE); 1275 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1276 WDCDEBUG_PRINT((", sidetim=0x%x", 1277 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1278 DEBUG_PROBE); 1279 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1280 WDCDEBUG_PRINT((", udamreg 0x%x", 1281 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1282 DEBUG_PROBE); 1283 } 1284 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1285 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1286 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1287 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1288 DEBUG_PROBE); 1289 } 1290 1291 } 1292 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1293 1294 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1295 cp = &sc->pciide_channels[channel]; 1296 /* PIIX is compat-only */ 1297 if (pciide_chansetup(sc, channel, 0) == 0) 1298 continue; 1299 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1300 if ((PIIX_IDETIM_READ(idetim, channel) & 1301 PIIX_IDETIM_IDE) == 0) { 1302 printf("%s: %s channel ignored (disabled)\n", 1303 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1304 return; 1305 } 1306 /* PIIX are compat-only pciide devices */ 1307 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1308 if (cp->hw_ok == 0) 1309 continue; 1310 if (pciiide_chan_candisable(cp)) { 1311 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1312 channel); 1313 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1314 idetim); 1315 } 1316 pciide_map_compat_intr(pa, cp, channel, 0); 1317 if (cp->hw_ok == 0) 1318 continue; 1319 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1320 } 1321 1322 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1323 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1324 DEBUG_PROBE); 1325 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1326 WDCDEBUG_PRINT((", sidetim=0x%x", 1327 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1328 DEBUG_PROBE); 1329 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1330 WDCDEBUG_PRINT((", udamreg 0x%x", 1331 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1332 DEBUG_PROBE); 1333 } 1334 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1335 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1336 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1337 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1338 DEBUG_PROBE); 1339 } 1340 } 1341 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1342 } 1343 1344 void 1345 piix_setup_channel(chp) 1346 struct channel_softc *chp; 1347 { 1348 u_int8_t mode[2], drive; 1349 u_int32_t oidetim, idetim, idedma_ctl; 1350 struct pciide_channel *cp = (struct pciide_channel*)chp; 1351 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1352 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1353 1354 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1355 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1356 idedma_ctl = 0; 1357 1358 /* set up new idetim: Enable IDE registers decode */ 1359 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1360 chp->channel); 1361 1362 /* setup DMA */ 1363 pciide_channel_dma_setup(cp); 1364 1365 /* 1366 * Here we have to mess up with drives mode: PIIX can't have 1367 * different timings for master and slave drives. 1368 * We need to find the best combination. 1369 */ 1370 1371 /* If both drives supports DMA, take the lower mode */ 1372 if ((drvp[0].drive_flags & DRIVE_DMA) && 1373 (drvp[1].drive_flags & DRIVE_DMA)) { 1374 mode[0] = mode[1] = 1375 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1376 drvp[0].DMA_mode = mode[0]; 1377 drvp[1].DMA_mode = mode[1]; 1378 goto ok; 1379 } 1380 /* 1381 * If only one drive supports DMA, use its mode, and 1382 * put the other one in PIO mode 0 if mode not compatible 1383 */ 1384 if (drvp[0].drive_flags & DRIVE_DMA) { 1385 mode[0] = drvp[0].DMA_mode; 1386 mode[1] = drvp[1].PIO_mode; 1387 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1388 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1389 mode[1] = drvp[1].PIO_mode = 0; 1390 goto ok; 1391 } 1392 if (drvp[1].drive_flags & DRIVE_DMA) { 1393 mode[1] = drvp[1].DMA_mode; 1394 mode[0] = drvp[0].PIO_mode; 1395 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1396 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1397 mode[0] = drvp[0].PIO_mode = 0; 1398 goto ok; 1399 } 1400 /* 1401 * If both drives are not DMA, takes the lower mode, unless 1402 * one of them is PIO mode < 2 1403 */ 1404 if (drvp[0].PIO_mode < 2) { 1405 mode[0] = drvp[0].PIO_mode = 0; 1406 mode[1] = drvp[1].PIO_mode; 1407 } else if (drvp[1].PIO_mode < 2) { 1408 mode[1] = drvp[1].PIO_mode = 0; 1409 mode[0] = drvp[0].PIO_mode; 1410 } else { 1411 mode[0] = mode[1] = 1412 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1413 drvp[0].PIO_mode = mode[0]; 1414 drvp[1].PIO_mode = mode[1]; 1415 } 1416 ok: /* The modes are setup */ 1417 for (drive = 0; drive < 2; drive++) { 1418 if (drvp[drive].drive_flags & DRIVE_DMA) { 1419 idetim |= piix_setup_idetim_timings( 1420 mode[drive], 1, chp->channel); 1421 goto end; 1422 } 1423 } 1424 /* If we are there, none of the drives are DMA */ 1425 if (mode[0] >= 2) 1426 idetim |= piix_setup_idetim_timings( 1427 mode[0], 0, chp->channel); 1428 else 1429 idetim |= piix_setup_idetim_timings( 1430 mode[1], 0, chp->channel); 1431 end: /* 1432 * timing mode is now set up in the controller. Enable 1433 * it per-drive 1434 */ 1435 for (drive = 0; drive < 2; drive++) { 1436 /* If no drive, skip */ 1437 if ((drvp[drive].drive_flags & DRIVE) == 0) 1438 continue; 1439 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1440 if (drvp[drive].drive_flags & DRIVE_DMA) 1441 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1442 } 1443 if (idedma_ctl != 0) { 1444 /* Add software bits in status register */ 1445 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1446 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1447 idedma_ctl); 1448 } 1449 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1450 pciide_print_modes(cp); 1451 } 1452 1453 void 1454 piix3_4_setup_channel(chp) 1455 struct channel_softc *chp; 1456 { 1457 struct ata_drive_datas *drvp; 1458 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1459 struct pciide_channel *cp = (struct pciide_channel*)chp; 1460 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1461 int drive; 1462 int channel = chp->channel; 1463 1464 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1465 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1466 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1467 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1468 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1469 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1470 PIIX_SIDETIM_RTC_MASK(channel)); 1471 1472 idedma_ctl = 0; 1473 /* If channel disabled, no need to go further */ 1474 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1475 return; 1476 /* set up new idetim: Enable IDE registers decode */ 1477 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1478 1479 /* setup DMA if needed */ 1480 pciide_channel_dma_setup(cp); 1481 1482 for (drive = 0; drive < 2; drive++) { 1483 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1484 PIIX_UDMATIM_SET(0x3, channel, drive)); 1485 drvp = &chp->ch_drive[drive]; 1486 /* If no drive, skip */ 1487 if ((drvp->drive_flags & DRIVE) == 0) 1488 continue; 1489 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1490 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1491 goto pio; 1492 1493 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1494 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1495 ideconf |= PIIX_CONFIG_PINGPONG; 1496 } 1497 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1498 /* setup Ultra/66 */ 1499 if (drvp->UDMA_mode > 2 && 1500 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1501 drvp->UDMA_mode = 2; 1502 if (drvp->UDMA_mode > 2) 1503 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1504 else 1505 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1506 } 1507 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1508 (drvp->drive_flags & DRIVE_UDMA)) { 1509 /* use Ultra/DMA */ 1510 drvp->drive_flags &= ~DRIVE_DMA; 1511 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1512 udmareg |= PIIX_UDMATIM_SET( 1513 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1514 } else { 1515 /* use Multiword DMA */ 1516 drvp->drive_flags &= ~DRIVE_UDMA; 1517 if (drive == 0) { 1518 idetim |= piix_setup_idetim_timings( 1519 drvp->DMA_mode, 1, channel); 1520 } else { 1521 sidetim |= piix_setup_sidetim_timings( 1522 drvp->DMA_mode, 1, channel); 1523 idetim =PIIX_IDETIM_SET(idetim, 1524 PIIX_IDETIM_SITRE, channel); 1525 } 1526 } 1527 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1528 1529 pio: /* use PIO mode */ 1530 idetim |= piix_setup_idetim_drvs(drvp); 1531 if (drive == 0) { 1532 idetim |= piix_setup_idetim_timings( 1533 drvp->PIO_mode, 0, channel); 1534 } else { 1535 sidetim |= piix_setup_sidetim_timings( 1536 drvp->PIO_mode, 0, channel); 1537 idetim =PIIX_IDETIM_SET(idetim, 1538 PIIX_IDETIM_SITRE, channel); 1539 } 1540 } 1541 if (idedma_ctl != 0) { 1542 /* Add software bits in status register */ 1543 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1544 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1545 idedma_ctl); 1546 } 1547 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1548 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1549 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1550 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1551 pciide_print_modes(cp); 1552 } 1553 1554 1555 /* setup ISP and RTC fields, based on mode */ 1556 static u_int32_t 1557 piix_setup_idetim_timings(mode, dma, channel) 1558 u_int8_t mode; 1559 u_int8_t dma; 1560 u_int8_t channel; 1561 { 1562 1563 if (dma) 1564 return PIIX_IDETIM_SET(0, 1565 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1566 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1567 channel); 1568 else 1569 return PIIX_IDETIM_SET(0, 1570 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1571 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1572 channel); 1573 } 1574 1575 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1576 static u_int32_t 1577 piix_setup_idetim_drvs(drvp) 1578 struct ata_drive_datas *drvp; 1579 { 1580 u_int32_t ret = 0; 1581 struct channel_softc *chp = drvp->chnl_softc; 1582 u_int8_t channel = chp->channel; 1583 u_int8_t drive = drvp->drive; 1584 1585 /* 1586 * If drive is using UDMA, timings setups are independant 1587 * So just check DMA and PIO here. 1588 */ 1589 if (drvp->drive_flags & DRIVE_DMA) { 1590 /* if mode = DMA mode 0, use compatible timings */ 1591 if ((drvp->drive_flags & DRIVE_DMA) && 1592 drvp->DMA_mode == 0) { 1593 drvp->PIO_mode = 0; 1594 return ret; 1595 } 1596 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1597 /* 1598 * PIO and DMA timings are the same, use fast timings for PIO 1599 * too, else use compat timings. 1600 */ 1601 if ((piix_isp_pio[drvp->PIO_mode] != 1602 piix_isp_dma[drvp->DMA_mode]) || 1603 (piix_rtc_pio[drvp->PIO_mode] != 1604 piix_rtc_dma[drvp->DMA_mode])) 1605 drvp->PIO_mode = 0; 1606 /* if PIO mode <= 2, use compat timings for PIO */ 1607 if (drvp->PIO_mode <= 2) { 1608 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1609 channel); 1610 return ret; 1611 } 1612 } 1613 1614 /* 1615 * Now setup PIO modes. If mode < 2, use compat timings. 1616 * Else enable fast timings. Enable IORDY and prefetch/post 1617 * if PIO mode >= 3. 1618 */ 1619 1620 if (drvp->PIO_mode < 2) 1621 return ret; 1622 1623 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1624 if (drvp->PIO_mode >= 3) { 1625 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1626 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1627 } 1628 return ret; 1629 } 1630 1631 /* setup values in SIDETIM registers, based on mode */ 1632 static u_int32_t 1633 piix_setup_sidetim_timings(mode, dma, channel) 1634 u_int8_t mode; 1635 u_int8_t dma; 1636 u_int8_t channel; 1637 { 1638 if (dma) 1639 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1640 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1641 else 1642 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1643 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1644 } 1645 1646 void 1647 apollo_chip_map(sc, pa) 1648 struct pciide_softc *sc; 1649 struct pci_attach_args *pa; 1650 { 1651 struct pciide_channel *cp; 1652 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1653 sc->sc_tag, PCI_CLASS_REG)); 1654 int channel; 1655 u_int32_t ideconf; 1656 bus_size_t cmdsize, ctlsize; 1657 1658 if (pciide_chipen(sc, pa) == 0) 1659 return; 1660 printf("%s: bus-master DMA support present", 1661 sc->sc_wdcdev.sc_dev.dv_xname); 1662 pciide_mapreg_dma(sc, pa); 1663 printf("\n"); 1664 if (sc->sc_dma_ok) { 1665 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1666 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1667 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1668 } 1669 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE; 1670 sc->sc_wdcdev.PIO_cap = 4; 1671 sc->sc_wdcdev.DMA_cap = 2; 1672 sc->sc_wdcdev.UDMA_cap = 2; 1673 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1674 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1675 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1676 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1677 1678 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1679 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1680 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1681 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1682 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1683 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1684 DEBUG_PROBE); 1685 1686 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1687 cp = &sc->pciide_channels[channel]; 1688 if (pciide_chansetup(sc, channel, interface) == 0) 1689 continue; 1690 1691 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1692 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1693 printf("%s: %s channel ignored (disabled)\n", 1694 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1695 return; 1696 } 1697 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1698 pciide_pci_intr); 1699 if (cp->hw_ok == 0) 1700 continue; 1701 if (pciiide_chan_candisable(cp)) { 1702 ideconf &= ~APO_IDECONF_EN(channel); 1703 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1704 ideconf); 1705 } 1706 pciide_map_compat_intr(pa, cp, channel, interface); 1707 1708 if (cp->hw_ok == 0) 1709 continue; 1710 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1711 } 1712 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1713 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1714 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1715 } 1716 1717 void 1718 apollo_setup_channel(chp) 1719 struct channel_softc *chp; 1720 { 1721 u_int32_t udmatim_reg, datatim_reg; 1722 u_int8_t idedma_ctl; 1723 int mode, drive; 1724 struct ata_drive_datas *drvp; 1725 struct pciide_channel *cp = (struct pciide_channel*)chp; 1726 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1727 1728 idedma_ctl = 0; 1729 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1730 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1731 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1732 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1733 1734 /* setup DMA if needed */ 1735 pciide_channel_dma_setup(cp); 1736 1737 for (drive = 0; drive < 2; drive++) { 1738 drvp = &chp->ch_drive[drive]; 1739 /* If no drive, skip */ 1740 if ((drvp->drive_flags & DRIVE) == 0) 1741 continue; 1742 /* add timing values, setup DMA if needed */ 1743 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1744 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1745 mode = drvp->PIO_mode; 1746 goto pio; 1747 } 1748 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1749 (drvp->drive_flags & DRIVE_UDMA)) { 1750 /* use Ultra/DMA */ 1751 drvp->drive_flags &= ~DRIVE_DMA; 1752 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1753 APO_UDMA_EN_MTH(chp->channel, drive) | 1754 APO_UDMA_TIME(chp->channel, drive, 1755 apollo_udma_tim[drvp->UDMA_mode]); 1756 /* can use PIO timings, MW DMA unused */ 1757 mode = drvp->PIO_mode; 1758 } else { 1759 /* use Multiword DMA */ 1760 drvp->drive_flags &= ~DRIVE_UDMA; 1761 /* mode = min(pio, dma+2) */ 1762 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1763 mode = drvp->PIO_mode; 1764 else 1765 mode = drvp->DMA_mode + 2; 1766 } 1767 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1768 1769 pio: /* setup PIO mode */ 1770 if (mode <= 2) { 1771 drvp->DMA_mode = 0; 1772 drvp->PIO_mode = 0; 1773 mode = 0; 1774 } else { 1775 drvp->PIO_mode = mode; 1776 drvp->DMA_mode = mode - 2; 1777 } 1778 datatim_reg |= 1779 APO_DATATIM_PULSE(chp->channel, drive, 1780 apollo_pio_set[mode]) | 1781 APO_DATATIM_RECOV(chp->channel, drive, 1782 apollo_pio_rec[mode]); 1783 } 1784 if (idedma_ctl != 0) { 1785 /* Add software bits in status register */ 1786 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1787 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1788 idedma_ctl); 1789 } 1790 pciide_print_modes(cp); 1791 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 1792 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 1793 } 1794 1795 void 1796 cmd_channel_map(pa, sc, channel) 1797 struct pci_attach_args *pa; 1798 struct pciide_softc *sc; 1799 int channel; 1800 { 1801 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1802 bus_size_t cmdsize, ctlsize; 1803 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 1804 int interface = 1805 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1806 1807 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1808 cp->name = PCIIDE_CHANNEL_NAME(channel); 1809 cp->wdc_channel.channel = channel; 1810 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1811 1812 if (channel > 0) { 1813 cp->wdc_channel.ch_queue = 1814 sc->pciide_channels[0].wdc_channel.ch_queue; 1815 } else { 1816 cp->wdc_channel.ch_queue = 1817 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1818 } 1819 if (cp->wdc_channel.ch_queue == NULL) { 1820 printf("%s %s channel: " 1821 "can't allocate memory for command queue", 1822 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1823 return; 1824 } 1825 1826 printf("%s: %s channel %s to %s mode\n", 1827 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1828 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1829 "configured" : "wired", 1830 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1831 "native-PCI" : "compatibility"); 1832 1833 /* 1834 * with a CMD PCI64x, if we get here, the first channel is enabled: 1835 * there's no way to disable the first channel without disabling 1836 * the whole device 1837 */ 1838 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 1839 printf("%s: %s channel ignored (disabled)\n", 1840 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1841 return; 1842 } 1843 1844 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 1845 if (cp->hw_ok == 0) 1846 return; 1847 if (channel == 1) { 1848 if (pciiide_chan_candisable(cp)) { 1849 ctrl &= ~CMD_CTRL_2PORT; 1850 pciide_pci_write(pa->pa_pc, pa->pa_tag, 1851 CMD_CTRL, ctrl); 1852 } 1853 } 1854 pciide_map_compat_intr(pa, cp, channel, interface); 1855 } 1856 1857 int 1858 cmd_pci_intr(arg) 1859 void *arg; 1860 { 1861 struct pciide_softc *sc = arg; 1862 struct pciide_channel *cp; 1863 struct channel_softc *wdc_cp; 1864 int i, rv, crv; 1865 u_int32_t priirq, secirq; 1866 1867 rv = 0; 1868 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 1869 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 1870 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1871 cp = &sc->pciide_channels[i]; 1872 wdc_cp = &cp->wdc_channel; 1873 /* If a compat channel skip. */ 1874 if (cp->compat) 1875 continue; 1876 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 1877 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 1878 crv = wdcintr(wdc_cp); 1879 if (crv == 0) 1880 printf("%s:%d: bogus intr\n", 1881 sc->sc_wdcdev.sc_dev.dv_xname, i); 1882 else 1883 rv = 1; 1884 } 1885 } 1886 return rv; 1887 } 1888 1889 void 1890 cmd_chip_map(sc, pa) 1891 struct pciide_softc *sc; 1892 struct pci_attach_args *pa; 1893 { 1894 int channel; 1895 1896 /* 1897 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 1898 * and base adresses registers can be disabled at 1899 * hardware level. In this case, the device is wired 1900 * in compat mode and its first channel is always enabled, 1901 * but we can't rely on PCI_COMMAND_IO_ENABLE. 1902 * In fact, it seems that the first channel of the CMD PCI0640 1903 * can't be disabled. 1904 */ 1905 1906 #ifdef PCIIDE_CMD064x_DISABLE 1907 if (pciide_chipen(sc, pa) == 0) 1908 return; 1909 #endif 1910 1911 printf("%s: hardware does not support DMA", 1912 sc->sc_wdcdev.sc_dev.dv_xname); 1913 sc->sc_dma_ok = 0; 1914 1915 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1916 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1917 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1918 1919 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1920 cmd_channel_map(pa, sc, channel); 1921 } 1922 } 1923 1924 void 1925 cmd0643_6_chip_map(sc, pa) 1926 struct pciide_softc *sc; 1927 struct pci_attach_args *pa; 1928 { 1929 struct pciide_channel *cp; 1930 int channel; 1931 1932 /* 1933 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 1934 * and base adresses registers can be disabled at 1935 * hardware level. In this case, the device is wired 1936 * in compat mode and its first channel is always enabled, 1937 * but we can't rely on PCI_COMMAND_IO_ENABLE. 1938 * In fact, it seems that the first channel of the CMD PCI0640 1939 * can't be disabled. 1940 */ 1941 1942 #ifdef PCIIDE_CMD064x_DISABLE 1943 if (pciide_chipen(sc, pa) == 0) 1944 return; 1945 #endif 1946 printf("%s: bus-master DMA support present", 1947 sc->sc_wdcdev.sc_dev.dv_xname); 1948 pciide_mapreg_dma(sc, pa); 1949 printf("\n"); 1950 if (sc->sc_dma_ok) 1951 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1952 1953 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1954 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1955 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1956 WDC_CAPABILITY_MODE; 1957 sc->sc_wdcdev.PIO_cap = 4; 1958 sc->sc_wdcdev.DMA_cap = 2; 1959 sc->sc_wdcdev.set_modes = cmd0643_6_setup_channel; 1960 1961 WDCDEBUG_PRINT(("cmd0643_6_chip_map: old timings reg 0x%x 0x%x\n", 1962 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 1963 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 1964 DEBUG_PROBE); 1965 1966 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1967 cp = &sc->pciide_channels[channel]; 1968 cmd_channel_map(pa, sc, channel); 1969 if (cp->hw_ok == 0) 1970 continue; 1971 cmd0643_6_setup_channel(&cp->wdc_channel); 1972 } 1973 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 1974 WDCDEBUG_PRINT(("cmd0643_6_chip_map: timings reg now 0x%x 0x%x\n", 1975 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 1976 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 1977 DEBUG_PROBE); 1978 } 1979 1980 void 1981 cmd0643_6_setup_channel(chp) 1982 struct channel_softc *chp; 1983 { 1984 struct ata_drive_datas *drvp; 1985 u_int8_t tim; 1986 u_int32_t idedma_ctl; 1987 int drive; 1988 struct pciide_channel *cp = (struct pciide_channel*)chp; 1989 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1990 1991 idedma_ctl = 0; 1992 /* setup DMA if needed */ 1993 pciide_channel_dma_setup(cp); 1994 1995 for (drive = 0; drive < 2; drive++) { 1996 drvp = &chp->ch_drive[drive]; 1997 /* If no drive, skip */ 1998 if ((drvp->drive_flags & DRIVE) == 0) 1999 continue; 2000 /* add timing values, setup DMA if needed */ 2001 tim = cmd0643_6_data_tim_pio[drvp->PIO_mode]; 2002 if (drvp->drive_flags & DRIVE_DMA) { 2003 /* 2004 * use Multiword DMA. 2005 * Timings will be used for both PIO and DMA, so adjust 2006 * DMA mode if needed 2007 */ 2008 if (drvp->PIO_mode >= 3 && 2009 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2010 drvp->DMA_mode = drvp->PIO_mode - 2; 2011 } 2012 tim = cmd0643_6_data_tim_dma[drvp->DMA_mode]; 2013 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2014 } 2015 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2016 CMD_DATA_TIM(chp->channel, drive), tim); 2017 } 2018 if (idedma_ctl != 0) { 2019 /* Add software bits in status register */ 2020 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2021 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2022 idedma_ctl); 2023 } 2024 pciide_print_modes(cp); 2025 } 2026 2027 void 2028 cy693_chip_map(sc, pa) 2029 struct pciide_softc *sc; 2030 struct pci_attach_args *pa; 2031 { 2032 struct pciide_channel *cp; 2033 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2034 sc->sc_tag, PCI_CLASS_REG)); 2035 int compatchan; 2036 bus_size_t cmdsize, ctlsize; 2037 2038 if (pciide_chipen(sc, pa) == 0) 2039 return; 2040 /* 2041 * this chip has 2 PCI IDE functions, one for primary and one for 2042 * secondary. So we need to call pciide_mapregs_compat() with 2043 * the real channel 2044 */ 2045 if (pa->pa_function == 1) { 2046 compatchan = 0; 2047 } else if (pa->pa_function == 2) { 2048 compatchan = 1; 2049 } else { 2050 printf("%s: unexpected PCI function %d\n", 2051 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2052 cp->hw_ok = 0; 2053 return; 2054 } 2055 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2056 printf("%s: bus-master DMA support present", 2057 sc->sc_wdcdev.sc_dev.dv_xname); 2058 pciide_mapreg_dma(sc, pa); 2059 } else { 2060 printf("%s: hardware does not support DMA", 2061 sc->sc_wdcdev.sc_dev.dv_xname); 2062 sc->sc_dma_ok = 0; 2063 } 2064 printf("\n"); 2065 2066 if (sc->sc_dma_ok) 2067 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2068 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2069 WDC_CAPABILITY_MODE; 2070 sc->sc_wdcdev.PIO_cap = 4; 2071 sc->sc_wdcdev.DMA_cap = 2; 2072 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2073 2074 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2075 sc->sc_wdcdev.nchannels = 1; 2076 2077 /* Only one channel for this chip; if we are here it's enabled */ 2078 cp = &sc->pciide_channels[0]; 2079 sc->wdc_chanarray[0] = &cp->wdc_channel; 2080 cp->name = PCIIDE_CHANNEL_NAME(0); 2081 cp->wdc_channel.channel = 0; 2082 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2083 cp->wdc_channel.ch_queue = 2084 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2085 if (cp->wdc_channel.ch_queue == NULL) { 2086 printf("%s primary channel: " 2087 "can't allocate memory for command queue", 2088 sc->sc_wdcdev.sc_dev.dv_xname); 2089 return; 2090 } 2091 printf("%s: primary channel %s to ", 2092 sc->sc_wdcdev.sc_dev.dv_xname, 2093 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2094 "configured" : "wired"); 2095 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2096 printf("native-PCI"); 2097 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2098 pciide_pci_intr); 2099 } else { 2100 printf("compatibility"); 2101 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2102 &cmdsize, &ctlsize); 2103 } 2104 printf(" mode\n"); 2105 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2106 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2107 wdcattach(&cp->wdc_channel); 2108 if (pciiide_chan_candisable(cp)) { 2109 pci_conf_write(sc->sc_pc, sc->sc_tag, 2110 PCI_COMMAND_STATUS_REG, 0); 2111 } 2112 pciide_map_compat_intr(pa, cp, compatchan, interface); 2113 if (cp->hw_ok == 0) 2114 return; 2115 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2116 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2117 cy693_setup_channel(&cp->wdc_channel); 2118 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2119 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2120 } 2121 2122 void 2123 cy693_setup_channel(chp) 2124 struct channel_softc *chp; 2125 { 2126 struct ata_drive_datas *drvp; 2127 int drive; 2128 u_int32_t cy_cmd_ctrl; 2129 u_int32_t idedma_ctl; 2130 struct pciide_channel *cp = (struct pciide_channel*)chp; 2131 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2132 int dma_mode = -1; 2133 2134 cy_cmd_ctrl = idedma_ctl = 0; 2135 2136 /* setup DMA if needed */ 2137 pciide_channel_dma_setup(cp); 2138 2139 for (drive = 0; drive < 2; drive++) { 2140 drvp = &chp->ch_drive[drive]; 2141 /* If no drive, skip */ 2142 if ((drvp->drive_flags & DRIVE) == 0) 2143 continue; 2144 /* add timing values, setup DMA if needed */ 2145 if (drvp->drive_flags & DRIVE_DMA) { 2146 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2147 /* use Multiword DMA */ 2148 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2149 dma_mode = drvp->DMA_mode; 2150 } 2151 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2152 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2153 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2154 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2155 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2156 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2157 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2158 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2159 } 2160 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2161 chp->ch_drive[0].DMA_mode = dma_mode; 2162 chp->ch_drive[1].DMA_mode = dma_mode; 2163 pciide_print_modes(cp); 2164 if (idedma_ctl != 0) { 2165 /* Add software bits in status register */ 2166 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2167 IDEDMA_CTL, idedma_ctl); 2168 } 2169 } 2170 2171 void 2172 sis_chip_map(sc, pa) 2173 struct pciide_softc *sc; 2174 struct pci_attach_args *pa; 2175 { 2176 struct pciide_channel *cp; 2177 int channel; 2178 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2179 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2180 sc->sc_tag, PCI_CLASS_REG)); 2181 bus_size_t cmdsize, ctlsize; 2182 2183 if (pciide_chipen(sc, pa) == 0) 2184 return; 2185 printf("%s: bus-master DMA support present", 2186 sc->sc_wdcdev.sc_dev.dv_xname); 2187 pciide_mapreg_dma(sc, pa); 2188 printf("\n"); 2189 if (sc->sc_dma_ok) 2190 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2191 2192 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2193 WDC_CAPABILITY_MODE; 2194 sc->sc_wdcdev.PIO_cap = 4; 2195 sc->sc_wdcdev.DMA_cap = 2; 2196 sc->sc_wdcdev.UDMA_cap = 2; 2197 sc->sc_wdcdev.set_modes = sis_setup_channel; 2198 2199 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2200 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2201 2202 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2203 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2204 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2205 2206 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2207 cp = &sc->pciide_channels[channel]; 2208 if (pciide_chansetup(sc, channel, interface) == 0) 2209 continue; 2210 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2211 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2212 printf("%s: %s channel ignored (disabled)\n", 2213 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2214 return; 2215 } 2216 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2217 pciide_pci_intr); 2218 if (cp->hw_ok == 0) 2219 continue; 2220 if (pciiide_chan_candisable(cp)) { 2221 if (channel == 0) 2222 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2223 else 2224 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2225 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2226 sis_ctr0); 2227 } 2228 pciide_map_compat_intr(pa, cp, channel, interface); 2229 if (cp->hw_ok == 0) 2230 continue; 2231 sis_setup_channel(&cp->wdc_channel); 2232 } 2233 } 2234 2235 void 2236 sis_setup_channel(chp) 2237 struct channel_softc *chp; 2238 { 2239 struct ata_drive_datas *drvp; 2240 int drive; 2241 u_int32_t sis_tim; 2242 u_int32_t idedma_ctl; 2243 struct pciide_channel *cp = (struct pciide_channel*)chp; 2244 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2245 2246 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2247 "channel %d 0x%x\n", chp->channel, 2248 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2249 DEBUG_PROBE); 2250 sis_tim = 0; 2251 idedma_ctl = 0; 2252 /* setup DMA if needed */ 2253 pciide_channel_dma_setup(cp); 2254 2255 for (drive = 0; drive < 2; drive++) { 2256 drvp = &chp->ch_drive[drive]; 2257 /* If no drive, skip */ 2258 if ((drvp->drive_flags & DRIVE) == 0) 2259 continue; 2260 /* add timing values, setup DMA if needed */ 2261 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2262 (drvp->drive_flags & DRIVE_UDMA) == 0) 2263 goto pio; 2264 2265 if (drvp->drive_flags & DRIVE_UDMA) { 2266 /* use Ultra/DMA */ 2267 drvp->drive_flags &= ~DRIVE_DMA; 2268 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2269 SIS_TIM_UDMA_TIME_OFF(drive); 2270 sis_tim |= SIS_TIM_UDMA_EN(drive); 2271 } else { 2272 /* 2273 * use Multiword DMA 2274 * Timings will be used for both PIO and DMA, 2275 * so adjust DMA mode if needed 2276 */ 2277 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2278 drvp->PIO_mode = drvp->DMA_mode + 2; 2279 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2280 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2281 drvp->PIO_mode - 2 : 0; 2282 if (drvp->DMA_mode == 0) 2283 drvp->PIO_mode = 0; 2284 } 2285 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2286 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2287 SIS_TIM_ACT_OFF(drive); 2288 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2289 SIS_TIM_REC_OFF(drive); 2290 } 2291 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2292 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2293 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2294 if (idedma_ctl != 0) { 2295 /* Add software bits in status register */ 2296 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2297 IDEDMA_CTL, idedma_ctl); 2298 } 2299 pciide_print_modes(cp); 2300 } 2301 2302 void 2303 acer_chip_map(sc, pa) 2304 struct pciide_softc *sc; 2305 struct pci_attach_args *pa; 2306 { 2307 struct pciide_channel *cp; 2308 int channel; 2309 pcireg_t cr, interface; 2310 bus_size_t cmdsize, ctlsize; 2311 2312 if (pciide_chipen(sc, pa) == 0) 2313 return; 2314 printf("%s: bus-master DMA support present", 2315 sc->sc_wdcdev.sc_dev.dv_xname); 2316 pciide_mapreg_dma(sc, pa); 2317 printf("\n"); 2318 if (sc->sc_dma_ok) 2319 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2320 2321 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2322 WDC_CAPABILITY_MODE; 2323 2324 sc->sc_wdcdev.PIO_cap = 4; 2325 sc->sc_wdcdev.DMA_cap = 2; 2326 sc->sc_wdcdev.UDMA_cap = 2; 2327 sc->sc_wdcdev.set_modes = acer_setup_channel; 2328 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2329 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2330 2331 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2332 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2333 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2334 2335 /* Enable "microsoft register bits" R/W. */ 2336 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2337 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2338 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2339 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2340 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2341 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2342 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2343 ~ACER_CHANSTATUSREGS_RO); 2344 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2345 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2346 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2347 /* Don't use cr, re-read the real register content instead */ 2348 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2349 PCI_CLASS_REG)); 2350 2351 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2352 cp = &sc->pciide_channels[channel]; 2353 if (pciide_chansetup(sc, channel, interface) == 0) 2354 continue; 2355 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2356 printf("%s: %s channel ignored (disabled)\n", 2357 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2358 continue; 2359 } 2360 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2361 acer_pci_intr); 2362 if (cp->hw_ok == 0) 2363 continue; 2364 if (pciiide_chan_candisable(cp)) { 2365 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2366 pci_conf_write(sc->sc_pc, sc->sc_tag, 2367 PCI_CLASS_REG, cr); 2368 } 2369 pciide_map_compat_intr(pa, cp, channel, interface); 2370 acer_setup_channel(&cp->wdc_channel); 2371 } 2372 } 2373 2374 void 2375 acer_setup_channel(chp) 2376 struct channel_softc *chp; 2377 { 2378 struct ata_drive_datas *drvp; 2379 int drive; 2380 u_int32_t acer_fifo_udma; 2381 u_int32_t idedma_ctl; 2382 struct pciide_channel *cp = (struct pciide_channel*)chp; 2383 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2384 2385 idedma_ctl = 0; 2386 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2387 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2388 acer_fifo_udma), DEBUG_PROBE); 2389 /* setup DMA if needed */ 2390 pciide_channel_dma_setup(cp); 2391 2392 for (drive = 0; drive < 2; drive++) { 2393 drvp = &chp->ch_drive[drive]; 2394 /* If no drive, skip */ 2395 if ((drvp->drive_flags & DRIVE) == 0) 2396 continue; 2397 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2398 "channel %d drive %d 0x%x\n", chp->channel, drive, 2399 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2400 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2401 /* clear FIFO/DMA mode */ 2402 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2403 ACER_UDMA_EN(chp->channel, drive) | 2404 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2405 2406 /* add timing values, setup DMA if needed */ 2407 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2408 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2409 acer_fifo_udma |= 2410 ACER_FTH_OPL(chp->channel, drive, 0x1); 2411 goto pio; 2412 } 2413 2414 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2415 if (drvp->drive_flags & DRIVE_UDMA) { 2416 /* use Ultra/DMA */ 2417 drvp->drive_flags &= ~DRIVE_DMA; 2418 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2419 acer_fifo_udma |= 2420 ACER_UDMA_TIM(chp->channel, drive, 2421 acer_udma[drvp->UDMA_mode]); 2422 } else { 2423 /* 2424 * use Multiword DMA 2425 * Timings will be used for both PIO and DMA, 2426 * so adjust DMA mode if needed 2427 */ 2428 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2429 drvp->PIO_mode = drvp->DMA_mode + 2; 2430 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2431 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2432 drvp->PIO_mode - 2 : 0; 2433 if (drvp->DMA_mode == 0) 2434 drvp->PIO_mode = 0; 2435 } 2436 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2437 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2438 ACER_IDETIM(chp->channel, drive), 2439 acer_pio[drvp->PIO_mode]); 2440 } 2441 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2442 acer_fifo_udma), DEBUG_PROBE); 2443 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2444 if (idedma_ctl != 0) { 2445 /* Add software bits in status register */ 2446 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2447 IDEDMA_CTL, idedma_ctl); 2448 } 2449 pciide_print_modes(cp); 2450 } 2451 2452 int 2453 acer_pci_intr(arg) 2454 void *arg; 2455 { 2456 struct pciide_softc *sc = arg; 2457 struct pciide_channel *cp; 2458 struct channel_softc *wdc_cp; 2459 int i, rv, crv; 2460 u_int32_t chids; 2461 2462 rv = 0; 2463 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2464 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2465 cp = &sc->pciide_channels[i]; 2466 wdc_cp = &cp->wdc_channel; 2467 /* If a compat channel skip. */ 2468 if (cp->compat) 2469 continue; 2470 if (chids & ACER_CHIDS_INT(i)) { 2471 crv = wdcintr(wdc_cp); 2472 if (crv == 0) 2473 printf("%s:%d: bogus intr\n", 2474 sc->sc_wdcdev.sc_dev.dv_xname, i); 2475 else 2476 rv = 1; 2477 } 2478 } 2479 return rv; 2480 } 2481 2482 void 2483 pdc202xx_chip_map(sc, pa) 2484 struct pciide_softc *sc; 2485 struct pci_attach_args *pa; 2486 { 2487 struct pciide_channel *cp; 2488 int channel; 2489 pcireg_t interface, st, mode; 2490 bus_size_t cmdsize, ctlsize; 2491 2492 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2493 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 2494 DEBUG_PROBE); 2495 if (pciide_chipen(sc, pa) == 0) 2496 return; 2497 2498 /* turn off RAID mode */ 2499 st &= ~PDC2xx_STATE_IDERAID; 2500 2501 /* 2502 * can't rely on the PCI_CLASS_REG content if the chip was in raid 2503 * mode. We have to fake interface 2504 */ 2505 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 2506 if (st & PDC2xx_STATE_NATIVE) 2507 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2508 2509 printf("%s: bus-master DMA support present", 2510 sc->sc_wdcdev.sc_dev.dv_xname); 2511 pciide_mapreg_dma(sc, pa); 2512 printf("\n"); 2513 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2514 WDC_CAPABILITY_MODE; 2515 if (sc->sc_dma_ok) 2516 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2517 sc->sc_wdcdev.PIO_cap = 4; 2518 sc->sc_wdcdev.DMA_cap = 2; 2519 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 2520 sc->sc_wdcdev.UDMA_cap = 4; 2521 else 2522 sc->sc_wdcdev.UDMA_cap = 2; 2523 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 2524 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2525 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2526 2527 /* setup failsafe defaults */ 2528 mode = 0; 2529 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 2530 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 2531 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 2532 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 2533 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2534 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 2535 "initial timings 0x%x, now 0x%x\n", channel, 2536 pci_conf_read(sc->sc_pc, sc->sc_tag, 2537 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 2538 DEBUG_PROBE); 2539 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 2540 mode | PDC2xx_TIM_IORDYp); 2541 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 2542 "initial timings 0x%x, now 0x%x\n", channel, 2543 pci_conf_read(sc->sc_pc, sc->sc_tag, 2544 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 2545 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 2546 mode); 2547 } 2548 2549 mode = PDC2xx_SCR_DMA; 2550 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); /* the BIOS set it up this way */ 2551 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 2552 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 2553 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 2554 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 2555 DEBUG_PROBE); 2556 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 2557 2558 /* controller initial state register is OK even without BIOS */ 2559 /* The Linux driver does this */ 2560 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 2561 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 2562 DEBUG_PROBE); 2563 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 2564 mode | 0x1); 2565 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 2566 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 2567 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 2568 mode | 0x1); 2569 2570 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2571 cp = &sc->pciide_channels[channel]; 2572 if (pciide_chansetup(sc, channel, interface) == 0) 2573 continue; 2574 if ((st & PDC2xx_STATE_EN(channel)) == 0) { 2575 printf("%s: %s channel ignored (disabled)\n", 2576 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2577 continue; 2578 } 2579 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2580 pdc202xx_pci_intr); 2581 if (cp->hw_ok == 0) 2582 continue; 2583 if (pciiide_chan_candisable(cp)) 2584 st &= ~PDC2xx_STATE_EN(channel); 2585 pciide_map_compat_intr(pa, cp, channel, interface); 2586 pdc202xx_setup_channel(&cp->wdc_channel); 2587 } 2588 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 2589 DEBUG_PROBE); 2590 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 2591 return; 2592 } 2593 2594 void 2595 pdc202xx_setup_channel(chp) 2596 struct channel_softc *chp; 2597 { 2598 struct ata_drive_datas *drvp; 2599 int drive; 2600 pcireg_t mode; 2601 u_int32_t idedma_ctl; 2602 struct pciide_channel *cp = (struct pciide_channel*)chp; 2603 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2604 2605 /* setup DMA if needed */ 2606 pciide_channel_dma_setup(cp); 2607 2608 idedma_ctl = 0; 2609 for (drive = 0; drive < 2; drive++) { 2610 drvp = &chp->ch_drive[drive]; 2611 /* If no drive, skip */ 2612 if ((drvp->drive_flags & DRIVE) == 0) 2613 continue; 2614 mode = PDC2xx_TIM_IORDY; 2615 if (drvp->drive_flags & DRIVE_ATA) 2616 mode |= PDC2xx_TIM_PRE; 2617 if (drvp->drive_flags & DRIVE_UDMA) { 2618 mode = PDC2xx_TIM_SET_MB(mode, 2619 pdc2xx_udma_mb[drvp->UDMA_mode]); 2620 mode = PDC2xx_TIM_SET_MC(mode, 2621 pdc2xx_udma_mc[drvp->UDMA_mode]); 2622 drvp->drive_flags &= ~DRIVE_DMA; 2623 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2624 } else if (drvp->drive_flags & DRIVE_DMA) { 2625 mode = PDC2xx_TIM_SET_MB(mode, 2626 pdc2xx_dma_mb[drvp->DMA_mode]); 2627 mode = PDC2xx_TIM_SET_MC(mode, 2628 pdc2xx_dma_mc[drvp->DMA_mode]); 2629 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2630 } else { 2631 mode = PDC2xx_TIM_SET_MB(mode, 2632 pdc2xx_dma_mb[0]); 2633 mode = PDC2xx_TIM_SET_MC(mode, 2634 pdc2xx_dma_mc[0]); 2635 } 2636 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 2637 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 2638 mode |= PDC2xx_TIM_SYNC; 2639 if (drvp->PIO_mode >= 3 &&(drvp->drive_flags & DRIVE_ATA)) 2640 mode |= PDC2xx_TIM_ERRDY; 2641 if (drive == 0) 2642 mode |= PDC2xx_TIM_IORDYp; 2643 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 2644 "timings 0x%x\n", 2645 sc->sc_wdcdev.sc_dev.dv_xname, 2646 chp->channel, drive, mode), DEBUG_PROBE); 2647 pci_conf_write(sc->sc_pc, sc->sc_tag, 2648 PDC2xx_TIM(chp->channel, drive), mode); 2649 } 2650 if (idedma_ctl != 0) { 2651 /* Add software bits in status register */ 2652 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2653 IDEDMA_CTL, idedma_ctl); 2654 } 2655 pciide_print_modes(cp); 2656 } 2657 2658 int 2659 pdc202xx_pci_intr(arg) 2660 void *arg; 2661 { 2662 struct pciide_softc *sc = arg; 2663 struct pciide_channel *cp; 2664 struct channel_softc *wdc_cp; 2665 int i, rv, crv; 2666 u_int32_t scr; 2667 2668 rv = 0; 2669 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 2670 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2671 cp = &sc->pciide_channels[i]; 2672 wdc_cp = &cp->wdc_channel; 2673 /* If a compat channel skip. */ 2674 if (cp->compat) 2675 continue; 2676 if (scr & PDC2xx_SCR_INT(i)) { 2677 crv = wdcintr(wdc_cp); 2678 if (crv == 0) 2679 printf("%s:%d: bogus intr\n", 2680 sc->sc_wdcdev.sc_dev.dv_xname, i); 2681 else 2682 rv = 1; 2683 } 2684 } 2685 return rv; 2686 } 2687
Indexes created Thu Oct 02 10:09:58 GMT 2025