pciide.c revision 1.44.4.1
1 /* $NetBSD: pciide.c,v 1.44.4.1 1999/11/15 00:41:10 fvdl Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 38 /* 39 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by Christopher G. Demetriou 52 * for the NetBSD Project. 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * PCI IDE controller driver. 70 * 71 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 72 * sys/dev/pci/ppb.c, revision 1.16). 73 * 74 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 75 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 76 * 5/16/94" from the PCI SIG. 77 * 78 */ 79 80 #ifndef WDCDEBUG 81 #define WDCDEBUG 82 #endif 83 84 #define DEBUG_DMA 0x01 85 #define DEBUG_XFERS 0x02 86 #define DEBUG_FUNCS 0x08 87 #define DEBUG_PROBE 0x10 88 #ifdef WDCDEBUG 89 int wdcdebug_pciide_mask = 0; 90 #define WDCDEBUG_PRINT(args, level) \ 91 if (wdcdebug_pciide_mask & (level)) printf args 92 #else 93 #define WDCDEBUG_PRINT(args, level) 94 #endif 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/device.h> 98 #include <sys/malloc.h> 99 100 #include <vm/vm.h> 101 #include <vm/vm_param.h> 102 #include <vm/vm_kern.h> 103 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcivar.h> 106 #include <dev/pci/pcidevs.h> 107 #include <dev/pci/pciidereg.h> 108 #include <dev/pci/pciidevar.h> 109 #include <dev/pci/pciide_piix_reg.h> 110 #include <dev/pci/pciide_apollo_reg.h> 111 #include <dev/pci/pciide_cmd_reg.h> 112 #include <dev/pci/pciide_cy693_reg.h> 113 #include <dev/pci/pciide_sis_reg.h> 114 #include <dev/pci/pciide_acer_reg.h> 115 #include <dev/pci/pciide_pdc202xx_reg.h> 116 117 #if BYTE_ORDER == BIG_ENDIAN 118 #include <machine/bswap.h> 119 #define htopci(x) bswap32(x) 120 #define pcitoh(x) bswap32(x) 121 #else 122 #define htopci(x) (x) 123 #define pcitoh(x) (x) 124 #endif 125 126 /* inlines for reading/writing 8-bit PCI registers */ 127 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 128 int)); 129 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 130 int, u_int8_t)); 131 132 static __inline u_int8_t 133 pciide_pci_read(pc, pa, reg) 134 pci_chipset_tag_t pc; 135 pcitag_t pa; 136 int reg; 137 { 138 139 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 140 ((reg & 0x03) * 8) & 0xff); 141 } 142 143 static __inline void 144 pciide_pci_write(pc, pa, reg, val) 145 pci_chipset_tag_t pc; 146 pcitag_t pa; 147 int reg; 148 u_int8_t val; 149 { 150 pcireg_t pcival; 151 152 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 153 pcival &= ~(0xff << ((reg & 0x03) * 8)); 154 pcival |= (val << ((reg & 0x03) * 8)); 155 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 156 } 157 158 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 160 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 void piix_setup_channel __P((struct channel_softc*)); 162 void piix3_4_setup_channel __P((struct channel_softc*)); 163 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 165 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 166 167 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void apollo_setup_channel __P((struct channel_softc*)); 169 170 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void cmd0643_6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 172 void cmd0643_6_setup_channel __P((struct channel_softc*)); 173 void cmd_channel_map __P((struct pci_attach_args *, 174 struct pciide_softc *, int)); 175 int cmd_pci_intr __P((void *)); 176 177 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void cy693_setup_channel __P((struct channel_softc*)); 179 180 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void sis_setup_channel __P((struct channel_softc*)); 182 183 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 184 void acer_setup_channel __P((struct channel_softc*)); 185 int acer_pci_intr __P((void *)); 186 187 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 188 void pdc202xx_setup_channel __P((struct channel_softc*)); 189 int pdc202xx_pci_intr __P((void *)); 190 191 void pciide_channel_dma_setup __P((struct pciide_channel *)); 192 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 193 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 194 void pciide_dma_start __P((void*, int, int, int)); 195 int pciide_dma_finish __P((void*, int, int, int)); 196 void pciide_print_modes __P((struct pciide_channel *)); 197 198 struct pciide_product_desc { 199 u_int32_t ide_product; 200 int ide_flags; 201 const char *ide_name; 202 /* map and setup chip, probe drives */ 203 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 204 }; 205 206 /* Flags for ide_flags */ 207 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 208 209 /* Default product description for devices not known from this controller */ 210 const struct pciide_product_desc default_product_desc = { 211 0, 212 0, 213 "Generic PCI IDE controller", 214 default_chip_map, 215 }; 216 217 const struct pciide_product_desc pciide_intel_products[] = { 218 { PCI_PRODUCT_INTEL_82092AA, 219 0, 220 "Intel 82092AA IDE controller", 221 default_chip_map, 222 }, 223 { PCI_PRODUCT_INTEL_82371FB_IDE, 224 0, 225 "Intel 82371FB IDE controller (PIIX)", 226 piix_chip_map, 227 }, 228 { PCI_PRODUCT_INTEL_82371SB_IDE, 229 0, 230 "Intel 82371SB IDE Interface (PIIX3)", 231 piix_chip_map, 232 }, 233 { PCI_PRODUCT_INTEL_82371AB_IDE, 234 0, 235 "Intel 82371AB IDE controller (PIIX4)", 236 piix_chip_map, 237 }, 238 { PCI_PRODUCT_INTEL_82801AA_IDE, 239 0, 240 "Intel 82801AA IDE Controller (ICH)", 241 piix_chip_map, 242 }, 243 { PCI_PRODUCT_INTEL_82801AB_IDE, 244 0, 245 "Intel 82801AB IDE Controller (ICH0)", 246 piix_chip_map, 247 }, 248 { 0, 249 0, 250 NULL, 251 } 252 }; 253 254 const struct pciide_product_desc pciide_cmd_products[] = { 255 { PCI_PRODUCT_CMDTECH_640, 256 0, 257 "CMD Technology PCI0640", 258 cmd_chip_map 259 }, 260 { PCI_PRODUCT_CMDTECH_643, 261 0, 262 "CMD Technology PCI0643", 263 cmd0643_6_chip_map, 264 }, 265 { PCI_PRODUCT_CMDTECH_646, 266 0, 267 "CMD Technology PCI0646", 268 cmd0643_6_chip_map, 269 }, 270 { 0, 271 0, 272 NULL, 273 } 274 }; 275 276 const struct pciide_product_desc pciide_via_products[] = { 277 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 278 0, 279 "VIA Technologies VT82C586 (Apollo VP) IDE Controller", 280 apollo_chip_map, 281 }, 282 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 283 0, 284 "VIA Technologies VT82C586A IDE Controller", 285 apollo_chip_map, 286 }, 287 { 0, 288 0, 289 NULL, 290 } 291 }; 292 293 const struct pciide_product_desc pciide_cypress_products[] = { 294 { PCI_PRODUCT_CONTAQ_82C693, 295 0, 296 "Contaq Microsystems CY82C693 IDE Controller", 297 cy693_chip_map, 298 }, 299 { 0, 300 0, 301 NULL, 302 } 303 }; 304 305 const struct pciide_product_desc pciide_sis_products[] = { 306 { PCI_PRODUCT_SIS_5597_IDE, 307 0, 308 "Silicon Integrated System 5597/5598 IDE controller", 309 sis_chip_map, 310 }, 311 { 0, 312 0, 313 NULL, 314 } 315 }; 316 317 const struct pciide_product_desc pciide_acer_products[] = { 318 { PCI_PRODUCT_ALI_M5229, 319 0, 320 "Acer Labs M5229 UDMA IDE Controller", 321 acer_chip_map, 322 }, 323 { 0, 324 0, 325 NULL, 326 } 327 }; 328 329 const struct pciide_product_desc pciide_promise_products[] = { 330 { PCI_PRODUCT_PROMISE_ULTRA33, 331 IDE_PCI_CLASS_OVERRIDE, 332 "Promise Ultra33/ATA Bus Master IDE Accelerator", 333 pdc202xx_chip_map, 334 }, 335 { PCI_PRODUCT_PROMISE_ULTRA66, 336 IDE_PCI_CLASS_OVERRIDE, 337 "Promise Ultra66/ATA Bus Master IDE Accelerator", 338 pdc202xx_chip_map, 339 }, 340 { 0, 341 0, 342 NULL, 343 } 344 }; 345 346 struct pciide_vendor_desc { 347 u_int32_t ide_vendor; 348 const struct pciide_product_desc *ide_products; 349 }; 350 351 const struct pciide_vendor_desc pciide_vendors[] = { 352 { PCI_VENDOR_INTEL, pciide_intel_products }, 353 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 354 { PCI_VENDOR_VIATECH, pciide_via_products }, 355 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 356 { PCI_VENDOR_SIS, pciide_sis_products }, 357 { PCI_VENDOR_ALI, pciide_acer_products }, 358 { PCI_VENDOR_PROMISE, pciide_promise_products }, 359 { 0, NULL } 360 }; 361 362 #define PCIIDE_CHANNEL_NAME(chan) ((chan) == 0 ? "primary" : "secondary") 363 364 /* options passed via the 'flags' config keyword */ 365 #define PCIIDE_OPTIONS_DMA 0x01 366 367 int pciide_match __P((struct device *, struct cfdata *, void *)); 368 void pciide_attach __P((struct device *, struct device *, void *)); 369 370 struct cfattach pciide_ca = { 371 sizeof(struct pciide_softc), pciide_match, pciide_attach 372 }; 373 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 374 int pciide_mapregs_compat __P(( struct pci_attach_args *, 375 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 376 int pciide_mapregs_native __P((struct pci_attach_args *, 377 struct pciide_channel *, bus_size_t *, bus_size_t *, 378 int (*pci_intr) __P((void *)))); 379 void pciide_mapreg_dma __P((struct pciide_softc *, 380 struct pci_attach_args *)); 381 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 382 void pciide_mapchan __P((struct pci_attach_args *, 383 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 384 int (*pci_intr) __P((void *)))); 385 int pciiide_chan_candisable __P((struct pciide_channel *)); 386 void pciide_map_compat_intr __P(( struct pci_attach_args *, 387 struct pciide_channel *, int, int)); 388 int pciide_print __P((void *, const char *pnp)); 389 int pciide_compat_intr __P((void *)); 390 int pciide_pci_intr __P((void *)); 391 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 392 393 const struct pciide_product_desc * 394 pciide_lookup_product(id) 395 u_int32_t id; 396 { 397 const struct pciide_product_desc *pp; 398 const struct pciide_vendor_desc *vp; 399 400 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 401 if (PCI_VENDOR(id) == vp->ide_vendor) 402 break; 403 404 if ((pp = vp->ide_products) == NULL) 405 return NULL; 406 407 for (; pp->ide_name != NULL; pp++) 408 if (PCI_PRODUCT(id) == pp->ide_product) 409 break; 410 411 if (pp->ide_name == NULL) 412 return NULL; 413 return pp; 414 } 415 416 int 417 pciide_match(parent, match, aux) 418 struct device *parent; 419 struct cfdata *match; 420 void *aux; 421 { 422 struct pci_attach_args *pa = aux; 423 const struct pciide_product_desc *pp; 424 425 /* 426 * Check the ID register to see that it's a PCI IDE controller. 427 * If it is, we assume that we can deal with it; it _should_ 428 * work in a standardized way... 429 */ 430 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 431 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 432 return (1); 433 } 434 435 /* 436 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 437 * controllers. Let see if we can deal with it anyway. 438 */ 439 pp = pciide_lookup_product(pa->pa_id); 440 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 441 return (1); 442 } 443 444 return (0); 445 } 446 447 void 448 pciide_attach(parent, self, aux) 449 struct device *parent, *self; 450 void *aux; 451 { 452 struct pci_attach_args *pa = aux; 453 pci_chipset_tag_t pc = pa->pa_pc; 454 pcitag_t tag = pa->pa_tag; 455 struct pciide_softc *sc = (struct pciide_softc *)self; 456 pcireg_t csr; 457 char devinfo[256]; 458 459 sc->sc_pp = pciide_lookup_product(pa->pa_id); 460 if (sc->sc_pp == NULL) { 461 sc->sc_pp = &default_product_desc; 462 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 463 printf(": %s (rev. 0x%02x)\n", devinfo, 464 PCI_REVISION(pa->pa_class)); 465 } else { 466 printf(": %s\n", sc->sc_pp->ide_name); 467 } 468 sc->sc_pc = pa->pa_pc; 469 sc->sc_tag = pa->pa_tag; 470 #ifdef WDCDEBUG 471 if (wdcdebug_pciide_mask & DEBUG_PROBE) 472 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 473 #endif 474 475 sc->sc_pp->chip_map(sc, pa); 476 477 if (sc->sc_dma_ok) { 478 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 479 csr |= PCI_COMMAND_MASTER_ENABLE; 480 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 481 } 482 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 483 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 484 } 485 486 /* tell wether the chip is enabled or not */ 487 int 488 pciide_chipen(sc, pa) 489 struct pciide_softc *sc; 490 struct pci_attach_args *pa; 491 { 492 pcireg_t csr; 493 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 494 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 495 PCI_COMMAND_STATUS_REG); 496 printf("%s: device disabled (at %s)\n", 497 sc->sc_wdcdev.sc_dev.dv_xname, 498 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 499 "device" : "bridge"); 500 return 0; 501 } 502 return 1; 503 } 504 505 int 506 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 507 struct pci_attach_args *pa; 508 struct pciide_channel *cp; 509 int compatchan; 510 bus_size_t *cmdsizep, *ctlsizep; 511 { 512 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 513 struct channel_softc *wdc_cp = &cp->wdc_channel; 514 515 cp->compat = 1; 516 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 517 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 518 519 wdc_cp->cmd_iot = pa->pa_iot; 520 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 521 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 522 printf("%s: couldn't map %s channel cmd regs\n", 523 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 524 return (0); 525 } 526 527 wdc_cp->ctl_iot = pa->pa_iot; 528 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 529 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 530 printf("%s: couldn't map %s channel ctl regs\n", 531 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 532 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 533 PCIIDE_COMPAT_CMD_SIZE); 534 return (0); 535 } 536 537 return (1); 538 } 539 540 int 541 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 542 struct pci_attach_args * pa; 543 struct pciide_channel *cp; 544 bus_size_t *cmdsizep, *ctlsizep; 545 int (*pci_intr) __P((void *)); 546 { 547 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 548 struct channel_softc *wdc_cp = &cp->wdc_channel; 549 const char *intrstr; 550 pci_intr_handle_t intrhandle; 551 552 cp->compat = 0; 553 554 if (sc->sc_pci_ih == NULL) { 555 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 556 pa->pa_intrline, &intrhandle) != 0) { 557 printf("%s: couldn't map native-PCI interrupt\n", 558 sc->sc_wdcdev.sc_dev.dv_xname); 559 return 0; 560 } 561 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 562 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 563 intrhandle, IPL_BIO, pci_intr, sc); 564 if (sc->sc_pci_ih != NULL) { 565 printf("%s: using %s for native-PCI interrupt\n", 566 sc->sc_wdcdev.sc_dev.dv_xname, 567 intrstr ? intrstr : "unknown interrupt"); 568 } else { 569 printf("%s: couldn't establish native-PCI interrupt", 570 sc->sc_wdcdev.sc_dev.dv_xname); 571 if (intrstr != NULL) 572 printf(" at %s", intrstr); 573 printf("\n"); 574 return 0; 575 } 576 } 577 cp->ih = sc->sc_pci_ih; 578 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 579 PCI_MAPREG_TYPE_IO, 0, 580 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 581 printf("%s: couldn't map %s channel cmd regs\n", 582 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 583 return 0; 584 } 585 586 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 587 PCI_MAPREG_TYPE_IO, 0, 588 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 589 printf("%s: couldn't map %s channel ctl regs\n", 590 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 591 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 592 return 0; 593 } 594 return (1); 595 } 596 597 void 598 pciide_mapreg_dma(sc, pa) 599 struct pciide_softc *sc; 600 struct pci_attach_args *pa; 601 { 602 /* 603 * Map DMA registers 604 * 605 * Note that sc_dma_ok is the right variable to test to see if 606 * DMA can be done. If the interface doesn't support DMA, 607 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 608 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 609 * non-zero if the interface supports DMA and the registers 610 * could be mapped. 611 * 612 * XXX Note that despite the fact that the Bus Master IDE specs 613 * XXX say that "The bus master IDE function uses 16 bytes of IO 614 * XXX space," some controllers (at least the United 615 * XXX Microelectronics UM8886BF) place it in memory space. 616 * XXX eventually, we should probably read the register and check 617 * XXX which type it is. Either that or 'quirk' certain devices. 618 */ 619 sc->sc_dma_ok = (pci_mapreg_map(pa, 620 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0, 621 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 622 sc->sc_dmat = pa->pa_dmat; 623 if (sc->sc_dma_ok == 0) { 624 printf(", but unused (couldn't map registers)"); 625 } else { 626 sc->sc_wdcdev.dma_arg = sc; 627 sc->sc_wdcdev.dma_init = pciide_dma_init; 628 sc->sc_wdcdev.dma_start = pciide_dma_start; 629 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 630 } 631 } 632 int 633 pciide_compat_intr(arg) 634 void *arg; 635 { 636 struct pciide_channel *cp = arg; 637 638 #ifdef DIAGNOSTIC 639 /* should only be called for a compat channel */ 640 if (cp->compat == 0) 641 panic("pciide compat intr called for non-compat chan %p\n", cp); 642 #endif 643 return (wdcintr(&cp->wdc_channel)); 644 } 645 646 int 647 pciide_pci_intr(arg) 648 void *arg; 649 { 650 struct pciide_softc *sc = arg; 651 struct pciide_channel *cp; 652 struct channel_softc *wdc_cp; 653 int i, rv, crv; 654 655 rv = 0; 656 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 657 cp = &sc->pciide_channels[i]; 658 wdc_cp = &cp->wdc_channel; 659 660 /* If a compat channel skip. */ 661 if (cp->compat) 662 continue; 663 /* if this channel not waiting for intr, skip */ 664 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 665 continue; 666 667 crv = wdcintr(wdc_cp); 668 if (crv == 0) 669 ; /* leave rv alone */ 670 else if (crv == 1) 671 rv = 1; /* claim the intr */ 672 else if (rv == 0) /* crv should be -1 in this case */ 673 rv = crv; /* if we've done no better, take it */ 674 } 675 return (rv); 676 } 677 678 void 679 pciide_channel_dma_setup(cp) 680 struct pciide_channel *cp; 681 { 682 int drive; 683 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 684 struct ata_drive_datas *drvp; 685 686 for (drive = 0; drive < 2; drive++) { 687 drvp = &cp->wdc_channel.ch_drive[drive]; 688 /* If no drive, skip */ 689 if ((drvp->drive_flags & DRIVE) == 0) 690 continue; 691 /* setup DMA if needed */ 692 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 693 (drvp->drive_flags & DRIVE_UDMA) == 0) || 694 sc->sc_dma_ok == 0) { 695 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 696 continue; 697 } 698 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 699 != 0) { 700 /* Abort DMA setup */ 701 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 702 continue; 703 } 704 } 705 } 706 707 int 708 pciide_dma_table_setup(sc, channel, drive) 709 struct pciide_softc *sc; 710 int channel, drive; 711 { 712 bus_dma_segment_t seg; 713 int error, rseg; 714 const bus_size_t dma_table_size = 715 sizeof(struct idedma_table) * NIDEDMA_TABLES; 716 struct pciide_dma_maps *dma_maps = 717 &sc->pciide_channels[channel].dma_maps[drive]; 718 719 /* If table was already allocated, just return */ 720 if (dma_maps->dma_table) 721 return 0; 722 723 /* Allocate memory for the DMA tables and map it */ 724 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 725 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 726 BUS_DMA_NOWAIT)) != 0) { 727 printf("%s:%d: unable to allocate table DMA for " 728 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 729 channel, drive, error); 730 return error; 731 } 732 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 733 dma_table_size, 734 (caddr_t *)&dma_maps->dma_table, 735 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 736 printf("%s:%d: unable to map table DMA for" 737 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 738 channel, drive, error); 739 return error; 740 } 741 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 742 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 743 seg.ds_addr), DEBUG_PROBE); 744 745 /* Create and load table DMA map for this disk */ 746 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 747 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 748 &dma_maps->dmamap_table)) != 0) { 749 printf("%s:%d: unable to create table DMA map for " 750 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 751 channel, drive, error); 752 return error; 753 } 754 if ((error = bus_dmamap_load(sc->sc_dmat, 755 dma_maps->dmamap_table, 756 dma_maps->dma_table, 757 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 758 printf("%s:%d: unable to load table DMA map for " 759 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 760 channel, drive, error); 761 return error; 762 } 763 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 764 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 765 /* Create a xfer DMA map for this drive */ 766 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 767 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 768 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 769 &dma_maps->dmamap_xfer)) != 0) { 770 printf("%s:%d: unable to create xfer DMA map for " 771 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 772 channel, drive, error); 773 return error; 774 } 775 return 0; 776 } 777 778 int 779 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 780 void *v; 781 int channel, drive; 782 void *databuf; 783 size_t datalen; 784 int flags; 785 { 786 struct pciide_softc *sc = v; 787 int error, seg; 788 struct pciide_dma_maps *dma_maps = 789 &sc->pciide_channels[channel].dma_maps[drive]; 790 791 error = bus_dmamap_load(sc->sc_dmat, 792 dma_maps->dmamap_xfer, 793 databuf, datalen, NULL, BUS_DMA_NOWAIT); 794 if (error) { 795 printf("%s:%d: unable to load xfer DMA map for" 796 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 797 channel, drive, error); 798 return error; 799 } 800 801 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 802 dma_maps->dmamap_xfer->dm_mapsize, 803 (flags & WDC_DMA_READ) ? 804 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 805 806 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 807 #ifdef DIAGNOSTIC 808 /* A segment must not cross a 64k boundary */ 809 { 810 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 811 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 812 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 813 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 814 printf("pciide_dma: segment %d physical addr 0x%lx" 815 " len 0x%lx not properly aligned\n", 816 seg, phys, len); 817 panic("pciide_dma: buf align"); 818 } 819 } 820 #endif 821 dma_maps->dma_table[seg].base_addr = 822 htopci(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 823 dma_maps->dma_table[seg].byte_count = 824 htopci(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 825 IDEDMA_BYTE_COUNT_MASK); 826 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 827 seg, pcitoh(dma_maps->dma_table[seg].byte_count), 828 pcitoh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 829 830 } 831 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 832 htopci(IDEDMA_BYTE_COUNT_EOT); 833 834 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 835 dma_maps->dmamap_table->dm_mapsize, 836 BUS_DMASYNC_PREWRITE); 837 838 /* Maps are ready. Start DMA function */ 839 #ifdef DIAGNOSTIC 840 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 841 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 842 dma_maps->dmamap_table->dm_segs[0].ds_addr); 843 panic("pciide_dma_init: table align"); 844 } 845 #endif 846 847 /* Clear status bits */ 848 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 849 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 850 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 851 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 852 /* Write table addr */ 853 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 854 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 855 dma_maps->dmamap_table->dm_segs[0].ds_addr); 856 /* set read/write */ 857 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 858 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 859 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 860 return 0; 861 } 862 863 void 864 pciide_dma_start(v, channel, drive, flags) 865 void *v; 866 int channel, drive, flags; 867 { 868 struct pciide_softc *sc = v; 869 870 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 871 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 872 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 873 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 874 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 875 } 876 877 int 878 pciide_dma_finish(v, channel, drive, flags) 879 void *v; 880 int channel, drive; 881 int flags; 882 { 883 struct pciide_softc *sc = v; 884 u_int8_t status; 885 struct pciide_dma_maps *dma_maps = 886 &sc->pciide_channels[channel].dma_maps[drive]; 887 888 /* Unload the map of the data buffer */ 889 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 890 dma_maps->dmamap_xfer->dm_mapsize, 891 (flags & WDC_DMA_READ) ? 892 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 893 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 894 895 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 896 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 897 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 898 DEBUG_XFERS); 899 900 /* stop DMA channel */ 901 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 902 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 903 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 904 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 905 906 /* Clear status bits */ 907 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 908 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 909 status); 910 911 if ((status & IDEDMA_CTL_ERR) != 0) { 912 printf("%s:%d:%d: Bus-Master DMA error: status=0x%x\n", 913 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 914 return -1; 915 } 916 917 if ((flags & WDC_DMA_POLL) == 0 && (status & IDEDMA_CTL_INTR) == 0) { 918 printf("%s:%d:%d: Bus-Master DMA error: missing interrupt, " 919 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 920 drive, status); 921 return -1; 922 } 923 924 if ((status & IDEDMA_CTL_ACT) != 0) { 925 /* data underrun, may be a valid condition for ATAPI */ 926 return 1; 927 } 928 return 0; 929 } 930 931 /* some common code used by several chip_map */ 932 int 933 pciide_chansetup(sc, channel, interface) 934 struct pciide_softc *sc; 935 int channel; 936 pcireg_t interface; 937 { 938 struct pciide_channel *cp = &sc->pciide_channels[channel]; 939 sc->wdc_chanarray[channel] = &cp->wdc_channel; 940 cp->name = PCIIDE_CHANNEL_NAME(channel); 941 cp->wdc_channel.channel = channel; 942 cp->wdc_channel.wdc = &sc->sc_wdcdev; 943 cp->wdc_channel.ch_queue = 944 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 945 if (cp->wdc_channel.ch_queue == NULL) { 946 printf("%s %s channel: " 947 "can't allocate memory for command queue", 948 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 949 return 0; 950 } 951 printf("%s: %s channel %s to %s mode\n", 952 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 953 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 954 "configured" : "wired", 955 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 956 "native-PCI" : "compatibility"); 957 return 1; 958 } 959 960 /* some common code used by several chip channel_map */ 961 void 962 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 963 struct pci_attach_args *pa; 964 struct pciide_channel *cp; 965 pcireg_t interface; 966 bus_size_t *cmdsizep, *ctlsizep; 967 int (*pci_intr) __P((void *)); 968 { 969 struct channel_softc *wdc_cp = &cp->wdc_channel; 970 971 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 972 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 973 pci_intr); 974 else 975 cp->hw_ok = pciide_mapregs_compat(pa, cp, 976 wdc_cp->channel, cmdsizep, ctlsizep); 977 978 if (cp->hw_ok == 0) 979 return; 980 wdc_cp->data32iot = wdc_cp->cmd_iot; 981 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 982 wdcattach(wdc_cp); 983 } 984 985 /* 986 * Generic code to call to know if a channel can be disabled. Return 1 987 * if channel can be disabled, 0 if not 988 */ 989 int 990 pciiide_chan_candisable(cp) 991 struct pciide_channel *cp; 992 { 993 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 994 struct channel_softc *wdc_cp = &cp->wdc_channel; 995 996 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 997 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 998 printf("%s: disabling %s channel (no drives)\n", 999 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1000 cp->hw_ok = 0; 1001 return 1; 1002 } 1003 return 0; 1004 } 1005 1006 /* 1007 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1008 * Set hw_ok=0 on failure 1009 */ 1010 void 1011 pciide_map_compat_intr(pa, cp, compatchan, interface) 1012 struct pci_attach_args *pa; 1013 struct pciide_channel *cp; 1014 int compatchan, interface; 1015 { 1016 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1017 struct channel_softc *wdc_cp = &cp->wdc_channel; 1018 1019 if (cp->hw_ok == 0) 1020 return; 1021 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1022 return; 1023 1024 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1025 pa, compatchan, pciide_compat_intr, cp); 1026 if (cp->ih == NULL) { 1027 printf("%s: no compatibility interrupt for use by %s " 1028 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1029 cp->hw_ok = 0; 1030 } 1031 } 1032 1033 void 1034 pciide_print_modes(cp) 1035 struct pciide_channel *cp; 1036 { 1037 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1038 int drive; 1039 struct channel_softc *chp; 1040 struct ata_drive_datas *drvp; 1041 1042 chp = &cp->wdc_channel; 1043 for (drive = 0; drive < 2; drive++) { 1044 drvp = &chp->ch_drive[drive]; 1045 if ((drvp->drive_flags & DRIVE) == 0) 1046 continue; 1047 printf("%s(%s:%d:%d): using PIO mode %d", 1048 drvp->drv_softc->dv_xname, 1049 sc->sc_wdcdev.sc_dev.dv_xname, 1050 chp->channel, drive, drvp->PIO_mode); 1051 if (drvp->drive_flags & DRIVE_DMA) 1052 printf(", DMA mode %d", drvp->DMA_mode); 1053 if (drvp->drive_flags & DRIVE_UDMA) 1054 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1055 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1056 printf(" (using DMA data transfers)"); 1057 printf("\n"); 1058 } 1059 } 1060 1061 void 1062 default_chip_map(sc, pa) 1063 struct pciide_softc *sc; 1064 struct pci_attach_args *pa; 1065 { 1066 struct pciide_channel *cp; 1067 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1068 sc->sc_tag, PCI_CLASS_REG)); 1069 pcireg_t csr; 1070 int channel, drive; 1071 struct ata_drive_datas *drvp; 1072 u_int8_t idedma_ctl; 1073 bus_size_t cmdsize, ctlsize; 1074 char *failreason; 1075 1076 if (pciide_chipen(sc, pa) == 0) 1077 return; 1078 1079 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1080 printf("%s: bus-master DMA support present", 1081 sc->sc_wdcdev.sc_dev.dv_xname); 1082 if (sc->sc_pp == &default_product_desc && 1083 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1084 PCIIDE_OPTIONS_DMA) == 0) { 1085 printf(", but unused (no driver support)"); 1086 sc->sc_dma_ok = 0; 1087 } else { 1088 pciide_mapreg_dma(sc, pa); 1089 if (sc->sc_dma_ok != 0) 1090 printf(", used without full driver " 1091 "support"); 1092 } 1093 } else { 1094 printf("%s: hardware does not support DMA", 1095 sc->sc_wdcdev.sc_dev.dv_xname); 1096 sc->sc_dma_ok = 0; 1097 } 1098 printf("\n"); 1099 if (sc->sc_dma_ok) 1100 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1101 sc->sc_wdcdev.PIO_cap = 0; 1102 sc->sc_wdcdev.DMA_cap = 0; 1103 1104 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1105 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1106 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1107 1108 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1109 cp = &sc->pciide_channels[channel]; 1110 if (pciide_chansetup(sc, channel, interface) == 0) 1111 continue; 1112 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1113 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1114 &ctlsize, pciide_pci_intr); 1115 } else { 1116 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1117 channel, &cmdsize, &ctlsize); 1118 } 1119 if (cp->hw_ok == 0) 1120 continue; 1121 /* 1122 * Check to see if something appears to be there. 1123 */ 1124 failreason = NULL; 1125 if (!wdcprobe(&cp->wdc_channel)) { 1126 failreason = "not responding; disabled or no drives?"; 1127 goto next; 1128 } 1129 /* 1130 * Now, make sure it's actually attributable to this PCI IDE 1131 * channel by trying to access the channel again while the 1132 * PCI IDE controller's I/O space is disabled. (If the 1133 * channel no longer appears to be there, it belongs to 1134 * this controller.) YUCK! 1135 */ 1136 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1137 PCI_COMMAND_STATUS_REG); 1138 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1139 csr & ~PCI_COMMAND_IO_ENABLE); 1140 if (wdcprobe(&cp->wdc_channel)) 1141 failreason = "other hardware responding at addresses"; 1142 pci_conf_write(sc->sc_pc, sc->sc_tag, 1143 PCI_COMMAND_STATUS_REG, csr); 1144 next: 1145 if (failreason) { 1146 printf("%s: %s channel ignored (%s)\n", 1147 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1148 failreason); 1149 cp->hw_ok = 0; 1150 bus_space_unmap(cp->wdc_channel.cmd_iot, 1151 cp->wdc_channel.cmd_ioh, cmdsize); 1152 bus_space_unmap(cp->wdc_channel.ctl_iot, 1153 cp->wdc_channel.ctl_ioh, ctlsize); 1154 } else { 1155 pciide_map_compat_intr(pa, cp, channel, interface); 1156 } 1157 if (cp->hw_ok) { 1158 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1159 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1160 wdcattach(&cp->wdc_channel); 1161 } 1162 } 1163 1164 if (sc->sc_dma_ok == 0) 1165 return; 1166 1167 /* Allocate DMA maps */ 1168 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1169 idedma_ctl = 0; 1170 cp = &sc->pciide_channels[channel]; 1171 for (drive = 0; drive < 2; drive++) { 1172 drvp = &cp->wdc_channel.ch_drive[drive]; 1173 /* If no drive, skip */ 1174 if ((drvp->drive_flags & DRIVE) == 0) 1175 continue; 1176 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1177 continue; 1178 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1179 /* Abort DMA setup */ 1180 printf("%s:%d:%d: can't allocate DMA maps, " 1181 "using PIO transfers\n", 1182 sc->sc_wdcdev.sc_dev.dv_xname, 1183 channel, drive); 1184 drvp->drive_flags &= ~DRIVE_DMA; 1185 } 1186 printf("%s:%d:%d: using DMA data transfers\n", 1187 sc->sc_wdcdev.sc_dev.dv_xname, 1188 channel, drive); 1189 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1190 } 1191 if (idedma_ctl != 0) { 1192 /* Add software bits in status register */ 1193 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1194 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1195 idedma_ctl); 1196 } 1197 } 1198 } 1199 1200 void 1201 piix_chip_map(sc, pa) 1202 struct pciide_softc *sc; 1203 struct pci_attach_args *pa; 1204 { 1205 struct pciide_channel *cp; 1206 int channel; 1207 u_int32_t idetim; 1208 bus_size_t cmdsize, ctlsize; 1209 1210 if (pciide_chipen(sc, pa) == 0) 1211 return; 1212 1213 printf("%s: bus-master DMA support present", 1214 sc->sc_wdcdev.sc_dev.dv_xname); 1215 pciide_mapreg_dma(sc, pa); 1216 printf("\n"); 1217 if (sc->sc_dma_ok) { 1218 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1219 switch(sc->sc_pp->ide_product) { 1220 case PCI_PRODUCT_INTEL_82371AB_IDE: 1221 case PCI_PRODUCT_INTEL_82801AA_IDE: 1222 case PCI_PRODUCT_INTEL_82801AB_IDE: 1223 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1224 } 1225 } 1226 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1227 WDC_CAPABILITY_MODE; 1228 sc->sc_wdcdev.PIO_cap = 4; 1229 sc->sc_wdcdev.DMA_cap = 2; 1230 sc->sc_wdcdev.UDMA_cap = 1231 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1232 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1233 sc->sc_wdcdev.set_modes = piix_setup_channel; 1234 else 1235 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1236 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1237 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1238 1239 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1240 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1241 DEBUG_PROBE); 1242 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1243 WDCDEBUG_PRINT((", sidetim=0x%x", 1244 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1245 DEBUG_PROBE); 1246 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1247 WDCDEBUG_PRINT((", udamreg 0x%x", 1248 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1249 DEBUG_PROBE); 1250 } 1251 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1252 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1253 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1254 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1255 DEBUG_PROBE); 1256 } 1257 1258 } 1259 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1260 1261 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1262 cp = &sc->pciide_channels[channel]; 1263 /* PIIX is compat-only */ 1264 if (pciide_chansetup(sc, channel, 0) == 0) 1265 continue; 1266 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1267 if ((PIIX_IDETIM_READ(idetim, channel) & 1268 PIIX_IDETIM_IDE) == 0) { 1269 printf("%s: %s channel ignored (disabled)\n", 1270 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1271 continue; 1272 } 1273 /* PIIX are compat-only pciide devices */ 1274 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1275 if (cp->hw_ok == 0) 1276 continue; 1277 if (pciiide_chan_candisable(cp)) { 1278 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1279 channel); 1280 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1281 idetim); 1282 } 1283 pciide_map_compat_intr(pa, cp, channel, 0); 1284 if (cp->hw_ok == 0) 1285 continue; 1286 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1287 } 1288 1289 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1290 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1291 DEBUG_PROBE); 1292 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1293 WDCDEBUG_PRINT((", sidetim=0x%x", 1294 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1295 DEBUG_PROBE); 1296 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1297 WDCDEBUG_PRINT((", udamreg 0x%x", 1298 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1299 DEBUG_PROBE); 1300 } 1301 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1302 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1303 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1304 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1305 DEBUG_PROBE); 1306 } 1307 } 1308 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1309 } 1310 1311 void 1312 piix_setup_channel(chp) 1313 struct channel_softc *chp; 1314 { 1315 u_int8_t mode[2], drive; 1316 u_int32_t oidetim, idetim, idedma_ctl; 1317 struct pciide_channel *cp = (struct pciide_channel*)chp; 1318 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1319 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1320 1321 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1322 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1323 idedma_ctl = 0; 1324 1325 /* set up new idetim: Enable IDE registers decode */ 1326 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1327 chp->channel); 1328 1329 /* setup DMA */ 1330 pciide_channel_dma_setup(cp); 1331 1332 /* 1333 * Here we have to mess up with drives mode: PIIX can't have 1334 * different timings for master and slave drives. 1335 * We need to find the best combination. 1336 */ 1337 1338 /* If both drives supports DMA, take the lower mode */ 1339 if ((drvp[0].drive_flags & DRIVE_DMA) && 1340 (drvp[1].drive_flags & DRIVE_DMA)) { 1341 mode[0] = mode[1] = 1342 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1343 drvp[0].DMA_mode = mode[0]; 1344 drvp[1].DMA_mode = mode[1]; 1345 goto ok; 1346 } 1347 /* 1348 * If only one drive supports DMA, use its mode, and 1349 * put the other one in PIO mode 0 if mode not compatible 1350 */ 1351 if (drvp[0].drive_flags & DRIVE_DMA) { 1352 mode[0] = drvp[0].DMA_mode; 1353 mode[1] = drvp[1].PIO_mode; 1354 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1355 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1356 mode[1] = drvp[1].PIO_mode = 0; 1357 goto ok; 1358 } 1359 if (drvp[1].drive_flags & DRIVE_DMA) { 1360 mode[1] = drvp[1].DMA_mode; 1361 mode[0] = drvp[0].PIO_mode; 1362 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1363 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1364 mode[0] = drvp[0].PIO_mode = 0; 1365 goto ok; 1366 } 1367 /* 1368 * If both drives are not DMA, takes the lower mode, unless 1369 * one of them is PIO mode < 2 1370 */ 1371 if (drvp[0].PIO_mode < 2) { 1372 mode[0] = drvp[0].PIO_mode = 0; 1373 mode[1] = drvp[1].PIO_mode; 1374 } else if (drvp[1].PIO_mode < 2) { 1375 mode[1] = drvp[1].PIO_mode = 0; 1376 mode[0] = drvp[0].PIO_mode; 1377 } else { 1378 mode[0] = mode[1] = 1379 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1380 drvp[0].PIO_mode = mode[0]; 1381 drvp[1].PIO_mode = mode[1]; 1382 } 1383 ok: /* The modes are setup */ 1384 for (drive = 0; drive < 2; drive++) { 1385 if (drvp[drive].drive_flags & DRIVE_DMA) { 1386 idetim |= piix_setup_idetim_timings( 1387 mode[drive], 1, chp->channel); 1388 goto end; 1389 } 1390 } 1391 /* If we are there, none of the drives are DMA */ 1392 if (mode[0] >= 2) 1393 idetim |= piix_setup_idetim_timings( 1394 mode[0], 0, chp->channel); 1395 else 1396 idetim |= piix_setup_idetim_timings( 1397 mode[1], 0, chp->channel); 1398 end: /* 1399 * timing mode is now set up in the controller. Enable 1400 * it per-drive 1401 */ 1402 for (drive = 0; drive < 2; drive++) { 1403 /* If no drive, skip */ 1404 if ((drvp[drive].drive_flags & DRIVE) == 0) 1405 continue; 1406 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1407 if (drvp[drive].drive_flags & DRIVE_DMA) 1408 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1409 } 1410 if (idedma_ctl != 0) { 1411 /* Add software bits in status register */ 1412 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1413 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1414 idedma_ctl); 1415 } 1416 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1417 pciide_print_modes(cp); 1418 } 1419 1420 void 1421 piix3_4_setup_channel(chp) 1422 struct channel_softc *chp; 1423 { 1424 struct ata_drive_datas *drvp; 1425 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1426 struct pciide_channel *cp = (struct pciide_channel*)chp; 1427 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1428 int drive; 1429 int channel = chp->channel; 1430 1431 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1432 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1433 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1434 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1435 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1436 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1437 PIIX_SIDETIM_RTC_MASK(channel)); 1438 1439 idedma_ctl = 0; 1440 /* If channel disabled, no need to go further */ 1441 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1442 return; 1443 /* set up new idetim: Enable IDE registers decode */ 1444 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1445 1446 /* setup DMA if needed */ 1447 pciide_channel_dma_setup(cp); 1448 1449 for (drive = 0; drive < 2; drive++) { 1450 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1451 PIIX_UDMATIM_SET(0x3, channel, drive)); 1452 drvp = &chp->ch_drive[drive]; 1453 /* If no drive, skip */ 1454 if ((drvp->drive_flags & DRIVE) == 0) 1455 continue; 1456 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1457 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1458 goto pio; 1459 1460 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1461 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1462 ideconf |= PIIX_CONFIG_PINGPONG; 1463 } 1464 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1465 /* setup Ultra/66 */ 1466 if (drvp->UDMA_mode > 2 && 1467 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1468 drvp->UDMA_mode = 2; 1469 if (drvp->UDMA_mode > 2) 1470 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1471 else 1472 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1473 } 1474 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1475 (drvp->drive_flags & DRIVE_UDMA)) { 1476 /* use Ultra/DMA */ 1477 drvp->drive_flags &= ~DRIVE_DMA; 1478 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1479 udmareg |= PIIX_UDMATIM_SET( 1480 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1481 } else { 1482 /* use Multiword DMA */ 1483 drvp->drive_flags &= ~DRIVE_UDMA; 1484 if (drive == 0) { 1485 idetim |= piix_setup_idetim_timings( 1486 drvp->DMA_mode, 1, channel); 1487 } else { 1488 sidetim |= piix_setup_sidetim_timings( 1489 drvp->DMA_mode, 1, channel); 1490 idetim =PIIX_IDETIM_SET(idetim, 1491 PIIX_IDETIM_SITRE, channel); 1492 } 1493 } 1494 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1495 1496 pio: /* use PIO mode */ 1497 idetim |= piix_setup_idetim_drvs(drvp); 1498 if (drive == 0) { 1499 idetim |= piix_setup_idetim_timings( 1500 drvp->PIO_mode, 0, channel); 1501 } else { 1502 sidetim |= piix_setup_sidetim_timings( 1503 drvp->PIO_mode, 0, channel); 1504 idetim =PIIX_IDETIM_SET(idetim, 1505 PIIX_IDETIM_SITRE, channel); 1506 } 1507 } 1508 if (idedma_ctl != 0) { 1509 /* Add software bits in status register */ 1510 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1511 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1512 idedma_ctl); 1513 } 1514 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1515 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1516 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1517 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1518 pciide_print_modes(cp); 1519 } 1520 1521 1522 /* setup ISP and RTC fields, based on mode */ 1523 static u_int32_t 1524 piix_setup_idetim_timings(mode, dma, channel) 1525 u_int8_t mode; 1526 u_int8_t dma; 1527 u_int8_t channel; 1528 { 1529 1530 if (dma) 1531 return PIIX_IDETIM_SET(0, 1532 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1533 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1534 channel); 1535 else 1536 return PIIX_IDETIM_SET(0, 1537 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1538 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1539 channel); 1540 } 1541 1542 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1543 static u_int32_t 1544 piix_setup_idetim_drvs(drvp) 1545 struct ata_drive_datas *drvp; 1546 { 1547 u_int32_t ret = 0; 1548 struct channel_softc *chp = drvp->chnl_softc; 1549 u_int8_t channel = chp->channel; 1550 u_int8_t drive = drvp->drive; 1551 1552 /* 1553 * If drive is using UDMA, timings setups are independant 1554 * So just check DMA and PIO here. 1555 */ 1556 if (drvp->drive_flags & DRIVE_DMA) { 1557 /* if mode = DMA mode 0, use compatible timings */ 1558 if ((drvp->drive_flags & DRIVE_DMA) && 1559 drvp->DMA_mode == 0) { 1560 drvp->PIO_mode = 0; 1561 return ret; 1562 } 1563 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1564 /* 1565 * PIO and DMA timings are the same, use fast timings for PIO 1566 * too, else use compat timings. 1567 */ 1568 if ((piix_isp_pio[drvp->PIO_mode] != 1569 piix_isp_dma[drvp->DMA_mode]) || 1570 (piix_rtc_pio[drvp->PIO_mode] != 1571 piix_rtc_dma[drvp->DMA_mode])) 1572 drvp->PIO_mode = 0; 1573 /* if PIO mode <= 2, use compat timings for PIO */ 1574 if (drvp->PIO_mode <= 2) { 1575 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1576 channel); 1577 return ret; 1578 } 1579 } 1580 1581 /* 1582 * Now setup PIO modes. If mode < 2, use compat timings. 1583 * Else enable fast timings. Enable IORDY and prefetch/post 1584 * if PIO mode >= 3. 1585 */ 1586 1587 if (drvp->PIO_mode < 2) 1588 return ret; 1589 1590 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1591 if (drvp->PIO_mode >= 3) { 1592 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1593 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1594 } 1595 return ret; 1596 } 1597 1598 /* setup values in SIDETIM registers, based on mode */ 1599 static u_int32_t 1600 piix_setup_sidetim_timings(mode, dma, channel) 1601 u_int8_t mode; 1602 u_int8_t dma; 1603 u_int8_t channel; 1604 { 1605 if (dma) 1606 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1607 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1608 else 1609 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1610 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1611 } 1612 1613 void 1614 apollo_chip_map(sc, pa) 1615 struct pciide_softc *sc; 1616 struct pci_attach_args *pa; 1617 { 1618 struct pciide_channel *cp; 1619 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1620 sc->sc_tag, PCI_CLASS_REG)); 1621 int channel; 1622 u_int32_t ideconf; 1623 bus_size_t cmdsize, ctlsize; 1624 1625 if (pciide_chipen(sc, pa) == 0) 1626 return; 1627 printf("%s: bus-master DMA support present", 1628 sc->sc_wdcdev.sc_dev.dv_xname); 1629 pciide_mapreg_dma(sc, pa); 1630 printf("\n"); 1631 if (sc->sc_dma_ok) { 1632 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1633 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1634 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1635 } 1636 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE; 1637 sc->sc_wdcdev.PIO_cap = 4; 1638 sc->sc_wdcdev.DMA_cap = 2; 1639 sc->sc_wdcdev.UDMA_cap = 2; 1640 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1641 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1642 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1643 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1644 1645 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1646 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1647 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1648 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1649 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1650 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1651 DEBUG_PROBE); 1652 1653 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1654 cp = &sc->pciide_channels[channel]; 1655 if (pciide_chansetup(sc, channel, interface) == 0) 1656 continue; 1657 1658 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1659 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1660 printf("%s: %s channel ignored (disabled)\n", 1661 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1662 continue; 1663 } 1664 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1665 pciide_pci_intr); 1666 if (cp->hw_ok == 0) 1667 continue; 1668 if (pciiide_chan_candisable(cp)) { 1669 ideconf &= ~APO_IDECONF_EN(channel); 1670 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1671 ideconf); 1672 } 1673 pciide_map_compat_intr(pa, cp, channel, interface); 1674 1675 if (cp->hw_ok == 0) 1676 continue; 1677 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1678 } 1679 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1680 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1681 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1682 } 1683 1684 void 1685 apollo_setup_channel(chp) 1686 struct channel_softc *chp; 1687 { 1688 u_int32_t udmatim_reg, datatim_reg; 1689 u_int8_t idedma_ctl; 1690 int mode, drive; 1691 struct ata_drive_datas *drvp; 1692 struct pciide_channel *cp = (struct pciide_channel*)chp; 1693 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1694 1695 idedma_ctl = 0; 1696 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1697 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1698 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1699 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1700 1701 /* setup DMA if needed */ 1702 pciide_channel_dma_setup(cp); 1703 1704 for (drive = 0; drive < 2; drive++) { 1705 drvp = &chp->ch_drive[drive]; 1706 /* If no drive, skip */ 1707 if ((drvp->drive_flags & DRIVE) == 0) 1708 continue; 1709 /* add timing values, setup DMA if needed */ 1710 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1711 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1712 mode = drvp->PIO_mode; 1713 goto pio; 1714 } 1715 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1716 (drvp->drive_flags & DRIVE_UDMA)) { 1717 /* use Ultra/DMA */ 1718 drvp->drive_flags &= ~DRIVE_DMA; 1719 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1720 APO_UDMA_EN_MTH(chp->channel, drive) | 1721 APO_UDMA_TIME(chp->channel, drive, 1722 apollo_udma_tim[drvp->UDMA_mode]); 1723 /* can use PIO timings, MW DMA unused */ 1724 mode = drvp->PIO_mode; 1725 } else { 1726 /* use Multiword DMA */ 1727 drvp->drive_flags &= ~DRIVE_UDMA; 1728 /* mode = min(pio, dma+2) */ 1729 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1730 mode = drvp->PIO_mode; 1731 else 1732 mode = drvp->DMA_mode + 2; 1733 } 1734 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1735 1736 pio: /* setup PIO mode */ 1737 if (mode <= 2) { 1738 drvp->DMA_mode = 0; 1739 drvp->PIO_mode = 0; 1740 mode = 0; 1741 } else { 1742 drvp->PIO_mode = mode; 1743 drvp->DMA_mode = mode - 2; 1744 } 1745 datatim_reg |= 1746 APO_DATATIM_PULSE(chp->channel, drive, 1747 apollo_pio_set[mode]) | 1748 APO_DATATIM_RECOV(chp->channel, drive, 1749 apollo_pio_rec[mode]); 1750 } 1751 if (idedma_ctl != 0) { 1752 /* Add software bits in status register */ 1753 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1754 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1755 idedma_ctl); 1756 } 1757 pciide_print_modes(cp); 1758 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 1759 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 1760 } 1761 1762 void 1763 cmd_channel_map(pa, sc, channel) 1764 struct pci_attach_args *pa; 1765 struct pciide_softc *sc; 1766 int channel; 1767 { 1768 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1769 bus_size_t cmdsize, ctlsize; 1770 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 1771 int interface = 1772 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1773 1774 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1775 cp->name = PCIIDE_CHANNEL_NAME(channel); 1776 cp->wdc_channel.channel = channel; 1777 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1778 1779 if (channel > 0) { 1780 cp->wdc_channel.ch_queue = 1781 sc->pciide_channels[0].wdc_channel.ch_queue; 1782 } else { 1783 cp->wdc_channel.ch_queue = 1784 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1785 } 1786 if (cp->wdc_channel.ch_queue == NULL) { 1787 printf("%s %s channel: " 1788 "can't allocate memory for command queue", 1789 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1790 return; 1791 } 1792 1793 printf("%s: %s channel %s to %s mode\n", 1794 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1795 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1796 "configured" : "wired", 1797 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1798 "native-PCI" : "compatibility"); 1799 1800 /* 1801 * with a CMD PCI64x, if we get here, the first channel is enabled: 1802 * there's no way to disable the first channel without disabling 1803 * the whole device 1804 */ 1805 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 1806 printf("%s: %s channel ignored (disabled)\n", 1807 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1808 return; 1809 } 1810 1811 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 1812 if (cp->hw_ok == 0) 1813 return; 1814 if (channel == 1) { 1815 if (pciiide_chan_candisable(cp)) { 1816 ctrl &= ~CMD_CTRL_2PORT; 1817 pciide_pci_write(pa->pa_pc, pa->pa_tag, 1818 CMD_CTRL, ctrl); 1819 } 1820 } 1821 pciide_map_compat_intr(pa, cp, channel, interface); 1822 } 1823 1824 int 1825 cmd_pci_intr(arg) 1826 void *arg; 1827 { 1828 struct pciide_softc *sc = arg; 1829 struct pciide_channel *cp; 1830 struct channel_softc *wdc_cp; 1831 int i, rv, crv; 1832 u_int32_t priirq, secirq; 1833 1834 rv = 0; 1835 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 1836 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 1837 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1838 cp = &sc->pciide_channels[i]; 1839 wdc_cp = &cp->wdc_channel; 1840 /* If a compat channel skip. */ 1841 if (cp->compat) 1842 continue; 1843 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 1844 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 1845 crv = wdcintr(wdc_cp); 1846 if (crv == 0) 1847 printf("%s:%d: bogus intr\n", 1848 sc->sc_wdcdev.sc_dev.dv_xname, i); 1849 else 1850 rv = 1; 1851 } 1852 } 1853 return rv; 1854 } 1855 1856 void 1857 cmd_chip_map(sc, pa) 1858 struct pciide_softc *sc; 1859 struct pci_attach_args *pa; 1860 { 1861 int channel; 1862 1863 /* 1864 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 1865 * and base adresses registers can be disabled at 1866 * hardware level. In this case, the device is wired 1867 * in compat mode and its first channel is always enabled, 1868 * but we can't rely on PCI_COMMAND_IO_ENABLE. 1869 * In fact, it seems that the first channel of the CMD PCI0640 1870 * can't be disabled. 1871 */ 1872 1873 #ifdef PCIIDE_CMD064x_DISABLE 1874 if (pciide_chipen(sc, pa) == 0) 1875 return; 1876 #endif 1877 1878 printf("%s: hardware does not support DMA\n", 1879 sc->sc_wdcdev.sc_dev.dv_xname); 1880 sc->sc_dma_ok = 0; 1881 1882 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1883 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1884 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1885 1886 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1887 cmd_channel_map(pa, sc, channel); 1888 } 1889 } 1890 1891 void 1892 cmd0643_6_chip_map(sc, pa) 1893 struct pciide_softc *sc; 1894 struct pci_attach_args *pa; 1895 { 1896 struct pciide_channel *cp; 1897 int channel; 1898 1899 /* 1900 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 1901 * and base adresses registers can be disabled at 1902 * hardware level. In this case, the device is wired 1903 * in compat mode and its first channel is always enabled, 1904 * but we can't rely on PCI_COMMAND_IO_ENABLE. 1905 * In fact, it seems that the first channel of the CMD PCI0640 1906 * can't be disabled. 1907 */ 1908 1909 #ifdef PCIIDE_CMD064x_DISABLE 1910 if (pciide_chipen(sc, pa) == 0) 1911 return; 1912 #endif 1913 printf("%s: bus-master DMA support present", 1914 sc->sc_wdcdev.sc_dev.dv_xname); 1915 pciide_mapreg_dma(sc, pa); 1916 printf("\n"); 1917 if (sc->sc_dma_ok) 1918 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1919 1920 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1921 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1922 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1923 WDC_CAPABILITY_MODE; 1924 sc->sc_wdcdev.PIO_cap = 4; 1925 sc->sc_wdcdev.DMA_cap = 2; 1926 sc->sc_wdcdev.set_modes = cmd0643_6_setup_channel; 1927 1928 WDCDEBUG_PRINT(("cmd0643_6_chip_map: old timings reg 0x%x 0x%x\n", 1929 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 1930 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 1931 DEBUG_PROBE); 1932 1933 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1934 cp = &sc->pciide_channels[channel]; 1935 cmd_channel_map(pa, sc, channel); 1936 if (cp->hw_ok == 0) 1937 continue; 1938 cmd0643_6_setup_channel(&cp->wdc_channel); 1939 } 1940 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 1941 WDCDEBUG_PRINT(("cmd0643_6_chip_map: timings reg now 0x%x 0x%x\n", 1942 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 1943 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 1944 DEBUG_PROBE); 1945 } 1946 1947 void 1948 cmd0643_6_setup_channel(chp) 1949 struct channel_softc *chp; 1950 { 1951 struct ata_drive_datas *drvp; 1952 u_int8_t tim; 1953 u_int32_t idedma_ctl; 1954 int drive; 1955 struct pciide_channel *cp = (struct pciide_channel*)chp; 1956 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1957 1958 idedma_ctl = 0; 1959 /* setup DMA if needed */ 1960 pciide_channel_dma_setup(cp); 1961 1962 for (drive = 0; drive < 2; drive++) { 1963 drvp = &chp->ch_drive[drive]; 1964 /* If no drive, skip */ 1965 if ((drvp->drive_flags & DRIVE) == 0) 1966 continue; 1967 /* add timing values, setup DMA if needed */ 1968 tim = cmd0643_6_data_tim_pio[drvp->PIO_mode]; 1969 if (drvp->drive_flags & DRIVE_DMA) { 1970 /* 1971 * use Multiword DMA. 1972 * Timings will be used for both PIO and DMA, so adjust 1973 * DMA mode if needed 1974 */ 1975 if (drvp->PIO_mode >= 3 && 1976 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 1977 drvp->DMA_mode = drvp->PIO_mode - 2; 1978 } 1979 tim = cmd0643_6_data_tim_dma[drvp->DMA_mode]; 1980 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1981 } 1982 pciide_pci_write(sc->sc_pc, sc->sc_tag, 1983 CMD_DATA_TIM(chp->channel, drive), tim); 1984 } 1985 if (idedma_ctl != 0) { 1986 /* Add software bits in status register */ 1987 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1988 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1989 idedma_ctl); 1990 } 1991 pciide_print_modes(cp); 1992 } 1993 1994 void 1995 cy693_chip_map(sc, pa) 1996 struct pciide_softc *sc; 1997 struct pci_attach_args *pa; 1998 { 1999 struct pciide_channel *cp; 2000 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2001 sc->sc_tag, PCI_CLASS_REG)); 2002 int compatchan; 2003 bus_size_t cmdsize, ctlsize; 2004 2005 if (pciide_chipen(sc, pa) == 0) 2006 return; 2007 /* 2008 * this chip has 2 PCI IDE functions, one for primary and one for 2009 * secondary. So we need to call pciide_mapregs_compat() with 2010 * the real channel 2011 */ 2012 if (pa->pa_function == 1) { 2013 compatchan = 0; 2014 } else if (pa->pa_function == 2) { 2015 compatchan = 1; 2016 } else { 2017 printf("%s: unexpected PCI function %d\n", 2018 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2019 cp->hw_ok = 0; 2020 return; 2021 } 2022 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2023 printf("%s: bus-master DMA support present", 2024 sc->sc_wdcdev.sc_dev.dv_xname); 2025 pciide_mapreg_dma(sc, pa); 2026 } else { 2027 printf("%s: hardware does not support DMA", 2028 sc->sc_wdcdev.sc_dev.dv_xname); 2029 sc->sc_dma_ok = 0; 2030 } 2031 printf("\n"); 2032 2033 if (sc->sc_dma_ok) 2034 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2035 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2036 WDC_CAPABILITY_MODE; 2037 sc->sc_wdcdev.PIO_cap = 4; 2038 sc->sc_wdcdev.DMA_cap = 2; 2039 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2040 2041 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2042 sc->sc_wdcdev.nchannels = 1; 2043 2044 /* Only one channel for this chip; if we are here it's enabled */ 2045 cp = &sc->pciide_channels[0]; 2046 sc->wdc_chanarray[0] = &cp->wdc_channel; 2047 cp->name = PCIIDE_CHANNEL_NAME(0); 2048 cp->wdc_channel.channel = 0; 2049 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2050 cp->wdc_channel.ch_queue = 2051 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2052 if (cp->wdc_channel.ch_queue == NULL) { 2053 printf("%s primary channel: " 2054 "can't allocate memory for command queue", 2055 sc->sc_wdcdev.sc_dev.dv_xname); 2056 return; 2057 } 2058 printf("%s: primary channel %s to ", 2059 sc->sc_wdcdev.sc_dev.dv_xname, 2060 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2061 "configured" : "wired"); 2062 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2063 printf("native-PCI"); 2064 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2065 pciide_pci_intr); 2066 } else { 2067 printf("compatibility"); 2068 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2069 &cmdsize, &ctlsize); 2070 } 2071 printf(" mode\n"); 2072 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2073 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2074 wdcattach(&cp->wdc_channel); 2075 if (pciiide_chan_candisable(cp)) { 2076 pci_conf_write(sc->sc_pc, sc->sc_tag, 2077 PCI_COMMAND_STATUS_REG, 0); 2078 } 2079 pciide_map_compat_intr(pa, cp, compatchan, interface); 2080 if (cp->hw_ok == 0) 2081 return; 2082 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2083 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2084 cy693_setup_channel(&cp->wdc_channel); 2085 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2086 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2087 } 2088 2089 void 2090 cy693_setup_channel(chp) 2091 struct channel_softc *chp; 2092 { 2093 struct ata_drive_datas *drvp; 2094 int drive; 2095 u_int32_t cy_cmd_ctrl; 2096 u_int32_t idedma_ctl; 2097 struct pciide_channel *cp = (struct pciide_channel*)chp; 2098 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2099 int dma_mode = -1; 2100 2101 cy_cmd_ctrl = idedma_ctl = 0; 2102 2103 /* setup DMA if needed */ 2104 pciide_channel_dma_setup(cp); 2105 2106 for (drive = 0; drive < 2; drive++) { 2107 drvp = &chp->ch_drive[drive]; 2108 /* If no drive, skip */ 2109 if ((drvp->drive_flags & DRIVE) == 0) 2110 continue; 2111 /* add timing values, setup DMA if needed */ 2112 if (drvp->drive_flags & DRIVE_DMA) { 2113 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2114 /* use Multiword DMA */ 2115 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2116 dma_mode = drvp->DMA_mode; 2117 } 2118 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2119 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2120 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2121 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2122 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2123 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2124 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2125 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2126 } 2127 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2128 chp->ch_drive[0].DMA_mode = dma_mode; 2129 chp->ch_drive[1].DMA_mode = dma_mode; 2130 pciide_print_modes(cp); 2131 if (idedma_ctl != 0) { 2132 /* Add software bits in status register */ 2133 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2134 IDEDMA_CTL, idedma_ctl); 2135 } 2136 } 2137 2138 void 2139 sis_chip_map(sc, pa) 2140 struct pciide_softc *sc; 2141 struct pci_attach_args *pa; 2142 { 2143 struct pciide_channel *cp; 2144 int channel; 2145 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2146 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2147 sc->sc_tag, PCI_CLASS_REG)); 2148 bus_size_t cmdsize, ctlsize; 2149 2150 if (pciide_chipen(sc, pa) == 0) 2151 return; 2152 printf("%s: bus-master DMA support present", 2153 sc->sc_wdcdev.sc_dev.dv_xname); 2154 pciide_mapreg_dma(sc, pa); 2155 printf("\n"); 2156 if (sc->sc_dma_ok) 2157 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2158 2159 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2160 WDC_CAPABILITY_MODE; 2161 sc->sc_wdcdev.PIO_cap = 4; 2162 sc->sc_wdcdev.DMA_cap = 2; 2163 sc->sc_wdcdev.UDMA_cap = 2; 2164 sc->sc_wdcdev.set_modes = sis_setup_channel; 2165 2166 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2167 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2168 2169 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2170 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2171 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2172 2173 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2174 cp = &sc->pciide_channels[channel]; 2175 if (pciide_chansetup(sc, channel, interface) == 0) 2176 continue; 2177 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2178 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2179 printf("%s: %s channel ignored (disabled)\n", 2180 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2181 continue; 2182 } 2183 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2184 pciide_pci_intr); 2185 if (cp->hw_ok == 0) 2186 continue; 2187 if (pciiide_chan_candisable(cp)) { 2188 if (channel == 0) 2189 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2190 else 2191 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2192 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2193 sis_ctr0); 2194 } 2195 pciide_map_compat_intr(pa, cp, channel, interface); 2196 if (cp->hw_ok == 0) 2197 continue; 2198 sis_setup_channel(&cp->wdc_channel); 2199 } 2200 } 2201 2202 void 2203 sis_setup_channel(chp) 2204 struct channel_softc *chp; 2205 { 2206 struct ata_drive_datas *drvp; 2207 int drive; 2208 u_int32_t sis_tim; 2209 u_int32_t idedma_ctl; 2210 struct pciide_channel *cp = (struct pciide_channel*)chp; 2211 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2212 2213 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2214 "channel %d 0x%x\n", chp->channel, 2215 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2216 DEBUG_PROBE); 2217 sis_tim = 0; 2218 idedma_ctl = 0; 2219 /* setup DMA if needed */ 2220 pciide_channel_dma_setup(cp); 2221 2222 for (drive = 0; drive < 2; drive++) { 2223 drvp = &chp->ch_drive[drive]; 2224 /* If no drive, skip */ 2225 if ((drvp->drive_flags & DRIVE) == 0) 2226 continue; 2227 /* add timing values, setup DMA if needed */ 2228 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2229 (drvp->drive_flags & DRIVE_UDMA) == 0) 2230 goto pio; 2231 2232 if (drvp->drive_flags & DRIVE_UDMA) { 2233 /* use Ultra/DMA */ 2234 drvp->drive_flags &= ~DRIVE_DMA; 2235 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2236 SIS_TIM_UDMA_TIME_OFF(drive); 2237 sis_tim |= SIS_TIM_UDMA_EN(drive); 2238 } else { 2239 /* 2240 * use Multiword DMA 2241 * Timings will be used for both PIO and DMA, 2242 * so adjust DMA mode if needed 2243 */ 2244 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2245 drvp->PIO_mode = drvp->DMA_mode + 2; 2246 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2247 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2248 drvp->PIO_mode - 2 : 0; 2249 if (drvp->DMA_mode == 0) 2250 drvp->PIO_mode = 0; 2251 } 2252 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2253 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2254 SIS_TIM_ACT_OFF(drive); 2255 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2256 SIS_TIM_REC_OFF(drive); 2257 } 2258 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2259 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2260 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2261 if (idedma_ctl != 0) { 2262 /* Add software bits in status register */ 2263 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2264 IDEDMA_CTL, idedma_ctl); 2265 } 2266 pciide_print_modes(cp); 2267 } 2268 2269 void 2270 acer_chip_map(sc, pa) 2271 struct pciide_softc *sc; 2272 struct pci_attach_args *pa; 2273 { 2274 struct pciide_channel *cp; 2275 int channel; 2276 pcireg_t cr, interface; 2277 bus_size_t cmdsize, ctlsize; 2278 2279 if (pciide_chipen(sc, pa) == 0) 2280 return; 2281 printf("%s: bus-master DMA support present", 2282 sc->sc_wdcdev.sc_dev.dv_xname); 2283 pciide_mapreg_dma(sc, pa); 2284 printf("\n"); 2285 if (sc->sc_dma_ok) 2286 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2287 2288 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2289 WDC_CAPABILITY_MODE; 2290 2291 sc->sc_wdcdev.PIO_cap = 4; 2292 sc->sc_wdcdev.DMA_cap = 2; 2293 sc->sc_wdcdev.UDMA_cap = 2; 2294 sc->sc_wdcdev.set_modes = acer_setup_channel; 2295 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2296 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2297 2298 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2299 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2300 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2301 2302 /* Enable "microsoft register bits" R/W. */ 2303 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2304 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2305 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2306 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2307 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2308 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2309 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2310 ~ACER_CHANSTATUSREGS_RO); 2311 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2312 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2313 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2314 /* Don't use cr, re-read the real register content instead */ 2315 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2316 PCI_CLASS_REG)); 2317 2318 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2319 cp = &sc->pciide_channels[channel]; 2320 if (pciide_chansetup(sc, channel, interface) == 0) 2321 continue; 2322 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2323 printf("%s: %s channel ignored (disabled)\n", 2324 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2325 continue; 2326 } 2327 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2328 acer_pci_intr); 2329 if (cp->hw_ok == 0) 2330 continue; 2331 if (pciiide_chan_candisable(cp)) { 2332 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2333 pci_conf_write(sc->sc_pc, sc->sc_tag, 2334 PCI_CLASS_REG, cr); 2335 } 2336 pciide_map_compat_intr(pa, cp, channel, interface); 2337 acer_setup_channel(&cp->wdc_channel); 2338 } 2339 } 2340 2341 void 2342 acer_setup_channel(chp) 2343 struct channel_softc *chp; 2344 { 2345 struct ata_drive_datas *drvp; 2346 int drive; 2347 u_int32_t acer_fifo_udma; 2348 u_int32_t idedma_ctl; 2349 struct pciide_channel *cp = (struct pciide_channel*)chp; 2350 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2351 2352 idedma_ctl = 0; 2353 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2354 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2355 acer_fifo_udma), DEBUG_PROBE); 2356 /* setup DMA if needed */ 2357 pciide_channel_dma_setup(cp); 2358 2359 for (drive = 0; drive < 2; drive++) { 2360 drvp = &chp->ch_drive[drive]; 2361 /* If no drive, skip */ 2362 if ((drvp->drive_flags & DRIVE) == 0) 2363 continue; 2364 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2365 "channel %d drive %d 0x%x\n", chp->channel, drive, 2366 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2367 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2368 /* clear FIFO/DMA mode */ 2369 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2370 ACER_UDMA_EN(chp->channel, drive) | 2371 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2372 2373 /* add timing values, setup DMA if needed */ 2374 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2375 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2376 acer_fifo_udma |= 2377 ACER_FTH_OPL(chp->channel, drive, 0x1); 2378 goto pio; 2379 } 2380 2381 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2382 if (drvp->drive_flags & DRIVE_UDMA) { 2383 /* use Ultra/DMA */ 2384 drvp->drive_flags &= ~DRIVE_DMA; 2385 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2386 acer_fifo_udma |= 2387 ACER_UDMA_TIM(chp->channel, drive, 2388 acer_udma[drvp->UDMA_mode]); 2389 } else { 2390 /* 2391 * use Multiword DMA 2392 * Timings will be used for both PIO and DMA, 2393 * so adjust DMA mode if needed 2394 */ 2395 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2396 drvp->PIO_mode = drvp->DMA_mode + 2; 2397 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2398 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2399 drvp->PIO_mode - 2 : 0; 2400 if (drvp->DMA_mode == 0) 2401 drvp->PIO_mode = 0; 2402 } 2403 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2404 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2405 ACER_IDETIM(chp->channel, drive), 2406 acer_pio[drvp->PIO_mode]); 2407 } 2408 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2409 acer_fifo_udma), DEBUG_PROBE); 2410 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2411 if (idedma_ctl != 0) { 2412 /* Add software bits in status register */ 2413 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2414 IDEDMA_CTL, idedma_ctl); 2415 } 2416 pciide_print_modes(cp); 2417 } 2418 2419 int 2420 acer_pci_intr(arg) 2421 void *arg; 2422 { 2423 struct pciide_softc *sc = arg; 2424 struct pciide_channel *cp; 2425 struct channel_softc *wdc_cp; 2426 int i, rv, crv; 2427 u_int32_t chids; 2428 2429 rv = 0; 2430 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2431 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2432 cp = &sc->pciide_channels[i]; 2433 wdc_cp = &cp->wdc_channel; 2434 /* If a compat channel skip. */ 2435 if (cp->compat) 2436 continue; 2437 if (chids & ACER_CHIDS_INT(i)) { 2438 crv = wdcintr(wdc_cp); 2439 if (crv == 0) 2440 printf("%s:%d: bogus intr\n", 2441 sc->sc_wdcdev.sc_dev.dv_xname, i); 2442 else 2443 rv = 1; 2444 } 2445 } 2446 return rv; 2447 } 2448 2449 void 2450 pdc202xx_chip_map(sc, pa) 2451 struct pciide_softc *sc; 2452 struct pci_attach_args *pa; 2453 { 2454 struct pciide_channel *cp; 2455 int channel; 2456 pcireg_t interface, st, mode; 2457 bus_size_t cmdsize, ctlsize; 2458 2459 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2460 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 2461 DEBUG_PROBE); 2462 if (pciide_chipen(sc, pa) == 0) 2463 return; 2464 2465 /* turn off RAID mode */ 2466 st &= ~PDC2xx_STATE_IDERAID; 2467 2468 /* 2469 * can't rely on the PCI_CLASS_REG content if the chip was in raid 2470 * mode. We have to fake interface 2471 */ 2472 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 2473 if (st & PDC2xx_STATE_NATIVE) 2474 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2475 2476 printf("%s: bus-master DMA support present", 2477 sc->sc_wdcdev.sc_dev.dv_xname); 2478 pciide_mapreg_dma(sc, pa); 2479 printf("\n"); 2480 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2481 WDC_CAPABILITY_MODE; 2482 if (sc->sc_dma_ok) 2483 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2484 sc->sc_wdcdev.PIO_cap = 4; 2485 sc->sc_wdcdev.DMA_cap = 2; 2486 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 2487 sc->sc_wdcdev.UDMA_cap = 4; 2488 else 2489 sc->sc_wdcdev.UDMA_cap = 2; 2490 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 2491 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2492 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2493 2494 /* setup failsafe defaults */ 2495 mode = 0; 2496 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 2497 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 2498 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 2499 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 2500 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2501 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 2502 "initial timings 0x%x, now 0x%x\n", channel, 2503 pci_conf_read(sc->sc_pc, sc->sc_tag, 2504 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 2505 DEBUG_PROBE); 2506 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 2507 mode | PDC2xx_TIM_IORDYp); 2508 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 2509 "initial timings 0x%x, now 0x%x\n", channel, 2510 pci_conf_read(sc->sc_pc, sc->sc_tag, 2511 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 2512 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 2513 mode); 2514 } 2515 2516 mode = PDC2xx_SCR_DMA; 2517 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); /* the BIOS set it up this way */ 2518 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 2519 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 2520 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 2521 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 2522 DEBUG_PROBE); 2523 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 2524 2525 /* controller initial state register is OK even without BIOS */ 2526 /* The Linux driver does this */ 2527 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 2528 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 2529 DEBUG_PROBE); 2530 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 2531 mode | 0x1); 2532 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 2533 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 2534 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 2535 mode | 0x1); 2536 2537 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2538 cp = &sc->pciide_channels[channel]; 2539 if (pciide_chansetup(sc, channel, interface) == 0) 2540 continue; 2541 if ((st & PDC2xx_STATE_EN(channel)) == 0) { 2542 printf("%s: %s channel ignored (disabled)\n", 2543 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2544 continue; 2545 } 2546 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2547 pdc202xx_pci_intr); 2548 if (cp->hw_ok == 0) 2549 continue; 2550 if (pciiide_chan_candisable(cp)) 2551 st &= ~PDC2xx_STATE_EN(channel); 2552 pciide_map_compat_intr(pa, cp, channel, interface); 2553 pdc202xx_setup_channel(&cp->wdc_channel); 2554 } 2555 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 2556 DEBUG_PROBE); 2557 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 2558 return; 2559 } 2560 2561 void 2562 pdc202xx_setup_channel(chp) 2563 struct channel_softc *chp; 2564 { 2565 struct ata_drive_datas *drvp; 2566 int drive; 2567 pcireg_t mode; 2568 u_int32_t idedma_ctl; 2569 struct pciide_channel *cp = (struct pciide_channel*)chp; 2570 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2571 2572 /* setup DMA if needed */ 2573 pciide_channel_dma_setup(cp); 2574 2575 idedma_ctl = 0; 2576 for (drive = 0; drive < 2; drive++) { 2577 drvp = &chp->ch_drive[drive]; 2578 /* If no drive, skip */ 2579 if ((drvp->drive_flags & DRIVE) == 0) 2580 continue; 2581 mode = PDC2xx_TIM_IORDY; 2582 if (drvp->drive_flags & DRIVE_ATA) 2583 mode |= PDC2xx_TIM_PRE; 2584 if (drvp->drive_flags & DRIVE_UDMA) { 2585 mode = PDC2xx_TIM_SET_MB(mode, 2586 pdc2xx_udma_mb[drvp->UDMA_mode]); 2587 mode = PDC2xx_TIM_SET_MC(mode, 2588 pdc2xx_udma_mc[drvp->UDMA_mode]); 2589 drvp->drive_flags &= ~DRIVE_DMA; 2590 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2591 } else if (drvp->drive_flags & DRIVE_DMA) { 2592 mode = PDC2xx_TIM_SET_MB(mode, 2593 pdc2xx_dma_mb[drvp->DMA_mode]); 2594 mode = PDC2xx_TIM_SET_MC(mode, 2595 pdc2xx_dma_mc[drvp->DMA_mode]); 2596 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2597 } else { 2598 mode = PDC2xx_TIM_SET_MB(mode, 2599 pdc2xx_dma_mb[0]); 2600 mode = PDC2xx_TIM_SET_MC(mode, 2601 pdc2xx_dma_mc[0]); 2602 } 2603 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 2604 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 2605 mode |= PDC2xx_TIM_SYNC; 2606 if (drvp->PIO_mode >= 3 &&(drvp->drive_flags & DRIVE_ATA)) 2607 mode |= PDC2xx_TIM_ERRDY; 2608 if (drive == 0) 2609 mode |= PDC2xx_TIM_IORDYp; 2610 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 2611 "timings 0x%x\n", 2612 sc->sc_wdcdev.sc_dev.dv_xname, 2613 chp->channel, drive, mode), DEBUG_PROBE); 2614 pci_conf_write(sc->sc_pc, sc->sc_tag, 2615 PDC2xx_TIM(chp->channel, drive), mode); 2616 } 2617 if (idedma_ctl != 0) { 2618 /* Add software bits in status register */ 2619 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2620 IDEDMA_CTL, idedma_ctl); 2621 } 2622 pciide_print_modes(cp); 2623 } 2624 2625 int 2626 pdc202xx_pci_intr(arg) 2627 void *arg; 2628 { 2629 struct pciide_softc *sc = arg; 2630 struct pciide_channel *cp; 2631 struct channel_softc *wdc_cp; 2632 int i, rv, crv; 2633 u_int32_t scr; 2634 2635 rv = 0; 2636 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 2637 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2638 cp = &sc->pciide_channels[i]; 2639 wdc_cp = &cp->wdc_channel; 2640 /* If a compat channel skip. */ 2641 if (cp->compat) 2642 continue; 2643 if (scr & PDC2xx_SCR_INT(i)) { 2644 crv = wdcintr(wdc_cp); 2645 if (crv == 0) 2646 printf("%s:%d: bogus intr\n", 2647 sc->sc_wdcdev.sc_dev.dv_xname, i); 2648 else 2649 rv = 1; 2650 } 2651 } 2652 return rv; 2653 } 2654
Indexes created Thu Oct 02 14:10:14 GMT 2025