pciide.c revision 1.45
1 /* $NetBSD: pciide.c,v 1.45 1999/10/25 14:13:12 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 38 /* 39 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by Christopher G. Demetriou 52 * for the NetBSD Project. 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * PCI IDE controller driver. 70 * 71 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 72 * sys/dev/pci/ppb.c, revision 1.16). 73 * 74 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 75 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 76 * 5/16/94" from the PCI SIG. 77 * 78 */ 79 80 #ifndef WDCDEBUG 81 #define WDCDEBUG 82 #endif 83 84 #define DEBUG_DMA 0x01 85 #define DEBUG_XFERS 0x02 86 #define DEBUG_FUNCS 0x08 87 #define DEBUG_PROBE 0x10 88 #ifdef WDCDEBUG 89 int wdcdebug_pciide_mask = 0; 90 #define WDCDEBUG_PRINT(args, level) \ 91 if (wdcdebug_pciide_mask & (level)) printf args 92 #else 93 #define WDCDEBUG_PRINT(args, level) 94 #endif 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/device.h> 98 #include <sys/malloc.h> 99 100 #include <vm/vm.h> 101 #include <vm/vm_param.h> 102 #include <vm/vm_kern.h> 103 104 #include <dev/pci/pcireg.h> 105 #include <dev/pci/pcivar.h> 106 #include <dev/pci/pcidevs.h> 107 #include <dev/pci/pciidereg.h> 108 #include <dev/pci/pciidevar.h> 109 #include <dev/pci/pciide_piix_reg.h> 110 #include <dev/pci/pciide_apollo_reg.h> 111 #include <dev/pci/pciide_cmd_reg.h> 112 #include <dev/pci/pciide_cy693_reg.h> 113 #include <dev/pci/pciide_sis_reg.h> 114 #include <dev/pci/pciide_acer_reg.h> 115 #include <dev/pci/pciide_pdc202xx_reg.h> 116 #include <dev/ata/atavar.h> 117 #include <dev/ic/wdcreg.h> 118 #include <dev/ic/wdcvar.h> 119 120 #if BYTE_ORDER == BIG_ENDIAN 121 #include <machine/bswap.h> 122 #define htopci(x) bswap32(x) 123 #define pcitoh(x) bswap32(x) 124 #else 125 #define htopci(x) (x) 126 #define pcitoh(x) (x) 127 #endif 128 129 /* inlines for reading/writing 8-bit PCI registers */ 130 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 131 int)); 132 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 133 int, u_int8_t)); 134 135 static __inline u_int8_t 136 pciide_pci_read(pc, pa, reg) 137 pci_chipset_tag_t pc; 138 pcitag_t pa; 139 int reg; 140 { 141 142 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 143 ((reg & 0x03) * 8) & 0xff); 144 } 145 146 static __inline void 147 pciide_pci_write(pc, pa, reg, val) 148 pci_chipset_tag_t pc; 149 pcitag_t pa; 150 int reg; 151 u_int8_t val; 152 { 153 pcireg_t pcival; 154 155 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 156 pcival &= ~(0xff << ((reg & 0x03) * 8)); 157 pcival |= (val << ((reg & 0x03) * 8)); 158 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 159 } 160 161 struct pciide_softc { 162 struct wdc_softc sc_wdcdev; /* common wdc definitions */ 163 pci_chipset_tag_t sc_pc; /* PCI registers info */ 164 pcitag_t sc_tag; 165 void *sc_pci_ih; /* PCI interrupt handle */ 166 int sc_dma_ok; /* bus-master DMA info */ 167 bus_space_tag_t sc_dma_iot; 168 bus_space_handle_t sc_dma_ioh; 169 bus_dma_tag_t sc_dmat; 170 /* Chip description */ 171 const struct pciide_product_desc *sc_pp; 172 /* common definitions */ 173 struct channel_softc *wdc_chanarray[PCIIDE_NUM_CHANNELS]; 174 /* internal bookkeeping */ 175 struct pciide_channel { /* per-channel data */ 176 struct channel_softc wdc_channel; /* generic part */ 177 char *name; 178 int hw_ok; /* hardware mapped & OK? */ 179 int compat; /* is it compat? */ 180 void *ih; /* compat or pci handle */ 181 /* DMA tables and DMA map for xfer, for each drive */ 182 struct pciide_dma_maps { 183 bus_dmamap_t dmamap_table; 184 struct idedma_table *dma_table; 185 bus_dmamap_t dmamap_xfer; 186 } dma_maps[2]; 187 } pciide_channels[PCIIDE_NUM_CHANNELS]; 188 }; 189 190 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 191 192 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void piix_setup_channel __P((struct channel_softc*)); 194 void piix3_4_setup_channel __P((struct channel_softc*)); 195 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 196 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 197 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 198 199 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 200 void apollo_setup_channel __P((struct channel_softc*)); 201 202 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 203 void cmd0643_6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 204 void cmd0643_6_setup_channel __P((struct channel_softc*)); 205 void cmd_channel_map __P((struct pci_attach_args *, 206 struct pciide_softc *, int)); 207 int cmd_pci_intr __P((void *)); 208 209 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 210 void cy693_setup_channel __P((struct channel_softc*)); 211 212 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 213 void sis_setup_channel __P((struct channel_softc*)); 214 215 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 216 void acer_setup_channel __P((struct channel_softc*)); 217 int acer_pci_intr __P((void *)); 218 219 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 220 void pdc202xx_setup_channel __P((struct channel_softc*)); 221 int pdc202xx_pci_intr __P((void *)); 222 223 void pciide_channel_dma_setup __P((struct pciide_channel *)); 224 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 225 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 226 void pciide_dma_start __P((void*, int, int, int)); 227 int pciide_dma_finish __P((void*, int, int, int)); 228 void pciide_print_modes __P((struct pciide_channel *)); 229 230 struct pciide_product_desc { 231 u_int32_t ide_product; 232 int ide_flags; 233 const char *ide_name; 234 /* map and setup chip, probe drives */ 235 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 236 }; 237 238 /* Flags for ide_flags */ 239 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 240 241 /* Default product description for devices not known from this controller */ 242 const struct pciide_product_desc default_product_desc = { 243 0, 244 0, 245 "Generic PCI IDE controller", 246 default_chip_map, 247 }; 248 249 const struct pciide_product_desc pciide_intel_products[] = { 250 { PCI_PRODUCT_INTEL_82092AA, 251 0, 252 "Intel 82092AA IDE controller", 253 default_chip_map, 254 }, 255 { PCI_PRODUCT_INTEL_82371FB_IDE, 256 0, 257 "Intel 82371FB IDE controller (PIIX)", 258 piix_chip_map, 259 }, 260 { PCI_PRODUCT_INTEL_82371SB_IDE, 261 0, 262 "Intel 82371SB IDE Interface (PIIX3)", 263 piix_chip_map, 264 }, 265 { PCI_PRODUCT_INTEL_82371AB_IDE, 266 0, 267 "Intel 82371AB IDE controller (PIIX4)", 268 piix_chip_map, 269 }, 270 { PCI_PRODUCT_INTEL_82801AA_IDE, 271 0, 272 "Intel 82801AA IDE Controller (ICH)", 273 piix_chip_map, 274 }, 275 { PCI_PRODUCT_INTEL_82801AB_IDE, 276 0, 277 "Intel 82801AB IDE Controller (ICH0)", 278 piix_chip_map, 279 }, 280 { 0, 281 0, 282 NULL, 283 } 284 }; 285 286 const struct pciide_product_desc pciide_cmd_products[] = { 287 { PCI_PRODUCT_CMDTECH_640, 288 0, 289 "CMD Technology PCI0640", 290 cmd_chip_map 291 }, 292 { PCI_PRODUCT_CMDTECH_643, 293 0, 294 "CMD Technology PCI0643", 295 cmd0643_6_chip_map, 296 }, 297 { PCI_PRODUCT_CMDTECH_646, 298 0, 299 "CMD Technology PCI0646", 300 cmd0643_6_chip_map, 301 }, 302 { 0, 303 0, 304 NULL, 305 } 306 }; 307 308 const struct pciide_product_desc pciide_via_products[] = { 309 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 310 0, 311 "VIA Technologies VT82C586 (Apollo VP) IDE Controller", 312 apollo_chip_map, 313 }, 314 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 315 0, 316 "VIA Technologies VT82C586A IDE Controller", 317 apollo_chip_map, 318 }, 319 { 0, 320 0, 321 NULL, 322 } 323 }; 324 325 const struct pciide_product_desc pciide_cypress_products[] = { 326 { PCI_PRODUCT_CONTAQ_82C693, 327 0, 328 "Contaq Microsystems CY82C693 IDE Controller", 329 cy693_chip_map, 330 }, 331 { 0, 332 0, 333 NULL, 334 } 335 }; 336 337 const struct pciide_product_desc pciide_sis_products[] = { 338 { PCI_PRODUCT_SIS_5597_IDE, 339 0, 340 "Silicon Integrated System 5597/5598 IDE controller", 341 sis_chip_map, 342 }, 343 { 0, 344 0, 345 NULL, 346 } 347 }; 348 349 const struct pciide_product_desc pciide_acer_products[] = { 350 { PCI_PRODUCT_ALI_M5229, 351 0, 352 "Acer Labs M5229 UDMA IDE Controller", 353 acer_chip_map, 354 }, 355 { 0, 356 0, 357 NULL, 358 } 359 }; 360 361 const struct pciide_product_desc pciide_promise_products[] = { 362 { PCI_PRODUCT_PROMISE_ULTRA33, 363 IDE_PCI_CLASS_OVERRIDE, 364 "Promise Ultra33/ATA Bus Master IDE Accelerator", 365 pdc202xx_chip_map, 366 }, 367 { PCI_PRODUCT_PROMISE_ULTRA66, 368 IDE_PCI_CLASS_OVERRIDE, 369 "Promise Ultra66/ATA Bus Master IDE Accelerator", 370 pdc202xx_chip_map, 371 }, 372 { 0, 373 0, 374 NULL, 375 } 376 }; 377 378 struct pciide_vendor_desc { 379 u_int32_t ide_vendor; 380 const struct pciide_product_desc *ide_products; 381 }; 382 383 const struct pciide_vendor_desc pciide_vendors[] = { 384 { PCI_VENDOR_INTEL, pciide_intel_products }, 385 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 386 { PCI_VENDOR_VIATECH, pciide_via_products }, 387 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 388 { PCI_VENDOR_SIS, pciide_sis_products }, 389 { PCI_VENDOR_ALI, pciide_acer_products }, 390 { PCI_VENDOR_PROMISE, pciide_promise_products }, 391 { 0, NULL } 392 }; 393 394 #define PCIIDE_CHANNEL_NAME(chan) ((chan) == 0 ? "primary" : "secondary") 395 396 /* options passed via the 'flags' config keyword */ 397 #define PCIIDE_OPTIONS_DMA 0x01 398 399 int pciide_match __P((struct device *, struct cfdata *, void *)); 400 void pciide_attach __P((struct device *, struct device *, void *)); 401 402 struct cfattach pciide_ca = { 403 sizeof(struct pciide_softc), pciide_match, pciide_attach 404 }; 405 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 406 int pciide_mapregs_compat __P(( struct pci_attach_args *, 407 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 408 int pciide_mapregs_native __P((struct pci_attach_args *, 409 struct pciide_channel *, bus_size_t *, bus_size_t *, 410 int (*pci_intr) __P((void *)))); 411 void pciide_mapreg_dma __P((struct pciide_softc *, 412 struct pci_attach_args *)); 413 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 414 void pciide_mapchan __P((struct pci_attach_args *, 415 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 416 int (*pci_intr) __P((void *)))); 417 int pciiide_chan_candisable __P((struct pciide_channel *)); 418 void pciide_map_compat_intr __P(( struct pci_attach_args *, 419 struct pciide_channel *, int, int)); 420 int pciide_print __P((void *, const char *pnp)); 421 int pciide_compat_intr __P((void *)); 422 int pciide_pci_intr __P((void *)); 423 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 424 425 const struct pciide_product_desc * 426 pciide_lookup_product(id) 427 u_int32_t id; 428 { 429 const struct pciide_product_desc *pp; 430 const struct pciide_vendor_desc *vp; 431 432 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 433 if (PCI_VENDOR(id) == vp->ide_vendor) 434 break; 435 436 if ((pp = vp->ide_products) == NULL) 437 return NULL; 438 439 for (; pp->ide_name != NULL; pp++) 440 if (PCI_PRODUCT(id) == pp->ide_product) 441 break; 442 443 if (pp->ide_name == NULL) 444 return NULL; 445 return pp; 446 } 447 448 int 449 pciide_match(parent, match, aux) 450 struct device *parent; 451 struct cfdata *match; 452 void *aux; 453 { 454 struct pci_attach_args *pa = aux; 455 const struct pciide_product_desc *pp; 456 457 /* 458 * Check the ID register to see that it's a PCI IDE controller. 459 * If it is, we assume that we can deal with it; it _should_ 460 * work in a standardized way... 461 */ 462 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 463 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 464 return (1); 465 } 466 467 /* 468 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 469 * controllers. Let see if we can deal with it anyway. 470 */ 471 pp = pciide_lookup_product(pa->pa_id); 472 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 473 return (1); 474 } 475 476 return (0); 477 } 478 479 void 480 pciide_attach(parent, self, aux) 481 struct device *parent, *self; 482 void *aux; 483 { 484 struct pci_attach_args *pa = aux; 485 pci_chipset_tag_t pc = pa->pa_pc; 486 pcitag_t tag = pa->pa_tag; 487 struct pciide_softc *sc = (struct pciide_softc *)self; 488 pcireg_t csr; 489 char devinfo[256]; 490 491 sc->sc_pp = pciide_lookup_product(pa->pa_id); 492 if (sc->sc_pp == NULL) { 493 sc->sc_pp = &default_product_desc; 494 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 495 printf(": %s (rev. 0x%02x)\n", devinfo, 496 PCI_REVISION(pa->pa_class)); 497 } else { 498 printf(": %s\n", sc->sc_pp->ide_name); 499 } 500 sc->sc_pc = pa->pa_pc; 501 sc->sc_tag = pa->pa_tag; 502 #ifdef WDCDEBUG 503 if (wdcdebug_pciide_mask & DEBUG_PROBE) 504 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 505 #endif 506 507 sc->sc_pp->chip_map(sc, pa); 508 509 if (sc->sc_dma_ok) { 510 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 511 csr |= PCI_COMMAND_MASTER_ENABLE; 512 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 513 } 514 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 515 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 516 } 517 518 /* tell wether the chip is enabled or not */ 519 int 520 pciide_chipen(sc, pa) 521 struct pciide_softc *sc; 522 struct pci_attach_args *pa; 523 { 524 pcireg_t csr; 525 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 526 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 527 PCI_COMMAND_STATUS_REG); 528 printf("%s: device disabled (at %s)\n", 529 sc->sc_wdcdev.sc_dev.dv_xname, 530 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 531 "device" : "bridge"); 532 return 0; 533 } 534 return 1; 535 } 536 537 int 538 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 539 struct pci_attach_args *pa; 540 struct pciide_channel *cp; 541 int compatchan; 542 bus_size_t *cmdsizep, *ctlsizep; 543 { 544 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 545 struct channel_softc *wdc_cp = &cp->wdc_channel; 546 547 cp->compat = 1; 548 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 549 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 550 551 wdc_cp->cmd_iot = pa->pa_iot; 552 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 553 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 554 printf("%s: couldn't map %s channel cmd regs\n", 555 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 556 return (0); 557 } 558 559 wdc_cp->ctl_iot = pa->pa_iot; 560 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 561 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 562 printf("%s: couldn't map %s channel ctl regs\n", 563 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 564 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 565 PCIIDE_COMPAT_CMD_SIZE); 566 return (0); 567 } 568 569 return (1); 570 } 571 572 int 573 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 574 struct pci_attach_args * pa; 575 struct pciide_channel *cp; 576 bus_size_t *cmdsizep, *ctlsizep; 577 int (*pci_intr) __P((void *)); 578 { 579 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 580 struct channel_softc *wdc_cp = &cp->wdc_channel; 581 const char *intrstr; 582 pci_intr_handle_t intrhandle; 583 584 cp->compat = 0; 585 586 if (sc->sc_pci_ih == NULL) { 587 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 588 pa->pa_intrline, &intrhandle) != 0) { 589 printf("%s: couldn't map native-PCI interrupt\n", 590 sc->sc_wdcdev.sc_dev.dv_xname); 591 return 0; 592 } 593 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 594 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 595 intrhandle, IPL_BIO, pci_intr, sc); 596 if (sc->sc_pci_ih != NULL) { 597 printf("%s: using %s for native-PCI interrupt\n", 598 sc->sc_wdcdev.sc_dev.dv_xname, 599 intrstr ? intrstr : "unknown interrupt"); 600 } else { 601 printf("%s: couldn't establish native-PCI interrupt", 602 sc->sc_wdcdev.sc_dev.dv_xname); 603 if (intrstr != NULL) 604 printf(" at %s", intrstr); 605 printf("\n"); 606 return 0; 607 } 608 } 609 cp->ih = sc->sc_pci_ih; 610 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 611 PCI_MAPREG_TYPE_IO, 0, 612 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 613 printf("%s: couldn't map %s channel cmd regs\n", 614 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 615 return 0; 616 } 617 618 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 619 PCI_MAPREG_TYPE_IO, 0, 620 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 621 printf("%s: couldn't map %s channel ctl regs\n", 622 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 623 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 624 return 0; 625 } 626 return (1); 627 } 628 629 void 630 pciide_mapreg_dma(sc, pa) 631 struct pciide_softc *sc; 632 struct pci_attach_args *pa; 633 { 634 /* 635 * Map DMA registers 636 * 637 * Note that sc_dma_ok is the right variable to test to see if 638 * DMA can be done. If the interface doesn't support DMA, 639 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 640 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 641 * non-zero if the interface supports DMA and the registers 642 * could be mapped. 643 * 644 * XXX Note that despite the fact that the Bus Master IDE specs 645 * XXX say that "The bus master IDE function uses 16 bytes of IO 646 * XXX space," some controllers (at least the United 647 * XXX Microelectronics UM8886BF) place it in memory space. 648 * XXX eventually, we should probably read the register and check 649 * XXX which type it is. Either that or 'quirk' certain devices. 650 */ 651 sc->sc_dma_ok = (pci_mapreg_map(pa, 652 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0, 653 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 654 sc->sc_dmat = pa->pa_dmat; 655 if (sc->sc_dma_ok == 0) { 656 printf(", but unused (couldn't map registers)"); 657 } else { 658 sc->sc_wdcdev.dma_arg = sc; 659 sc->sc_wdcdev.dma_init = pciide_dma_init; 660 sc->sc_wdcdev.dma_start = pciide_dma_start; 661 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 662 } 663 } 664 int 665 pciide_compat_intr(arg) 666 void *arg; 667 { 668 struct pciide_channel *cp = arg; 669 670 #ifdef DIAGNOSTIC 671 /* should only be called for a compat channel */ 672 if (cp->compat == 0) 673 panic("pciide compat intr called for non-compat chan %p\n", cp); 674 #endif 675 return (wdcintr(&cp->wdc_channel)); 676 } 677 678 int 679 pciide_pci_intr(arg) 680 void *arg; 681 { 682 struct pciide_softc *sc = arg; 683 struct pciide_channel *cp; 684 struct channel_softc *wdc_cp; 685 int i, rv, crv; 686 687 rv = 0; 688 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 689 cp = &sc->pciide_channels[i]; 690 wdc_cp = &cp->wdc_channel; 691 692 /* If a compat channel skip. */ 693 if (cp->compat) 694 continue; 695 /* if this channel not waiting for intr, skip */ 696 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 697 continue; 698 699 crv = wdcintr(wdc_cp); 700 if (crv == 0) 701 ; /* leave rv alone */ 702 else if (crv == 1) 703 rv = 1; /* claim the intr */ 704 else if (rv == 0) /* crv should be -1 in this case */ 705 rv = crv; /* if we've done no better, take it */ 706 } 707 return (rv); 708 } 709 710 void 711 pciide_channel_dma_setup(cp) 712 struct pciide_channel *cp; 713 { 714 int drive; 715 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 716 struct ata_drive_datas *drvp; 717 718 for (drive = 0; drive < 2; drive++) { 719 drvp = &cp->wdc_channel.ch_drive[drive]; 720 /* If no drive, skip */ 721 if ((drvp->drive_flags & DRIVE) == 0) 722 continue; 723 /* setup DMA if needed */ 724 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 725 (drvp->drive_flags & DRIVE_UDMA) == 0) || 726 sc->sc_dma_ok == 0) { 727 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 728 continue; 729 } 730 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 731 != 0) { 732 /* Abort DMA setup */ 733 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 734 continue; 735 } 736 } 737 } 738 739 int 740 pciide_dma_table_setup(sc, channel, drive) 741 struct pciide_softc *sc; 742 int channel, drive; 743 { 744 bus_dma_segment_t seg; 745 int error, rseg; 746 const bus_size_t dma_table_size = 747 sizeof(struct idedma_table) * NIDEDMA_TABLES; 748 struct pciide_dma_maps *dma_maps = 749 &sc->pciide_channels[channel].dma_maps[drive]; 750 751 /* If table was already allocated, just return */ 752 if (dma_maps->dma_table) 753 return 0; 754 755 /* Allocate memory for the DMA tables and map it */ 756 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 757 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 758 BUS_DMA_NOWAIT)) != 0) { 759 printf("%s:%d: unable to allocate table DMA for " 760 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 761 channel, drive, error); 762 return error; 763 } 764 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 765 dma_table_size, 766 (caddr_t *)&dma_maps->dma_table, 767 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 768 printf("%s:%d: unable to map table DMA for" 769 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 770 channel, drive, error); 771 return error; 772 } 773 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 774 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 775 seg.ds_addr), DEBUG_PROBE); 776 777 /* Create and load table DMA map for this disk */ 778 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 779 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 780 &dma_maps->dmamap_table)) != 0) { 781 printf("%s:%d: unable to create table DMA map for " 782 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 783 channel, drive, error); 784 return error; 785 } 786 if ((error = bus_dmamap_load(sc->sc_dmat, 787 dma_maps->dmamap_table, 788 dma_maps->dma_table, 789 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 790 printf("%s:%d: unable to load table DMA map for " 791 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 792 channel, drive, error); 793 return error; 794 } 795 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 796 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 797 /* Create a xfer DMA map for this drive */ 798 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 799 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 800 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 801 &dma_maps->dmamap_xfer)) != 0) { 802 printf("%s:%d: unable to create xfer DMA map for " 803 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 804 channel, drive, error); 805 return error; 806 } 807 return 0; 808 } 809 810 int 811 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 812 void *v; 813 int channel, drive; 814 void *databuf; 815 size_t datalen; 816 int flags; 817 { 818 struct pciide_softc *sc = v; 819 int error, seg; 820 struct pciide_dma_maps *dma_maps = 821 &sc->pciide_channels[channel].dma_maps[drive]; 822 823 error = bus_dmamap_load(sc->sc_dmat, 824 dma_maps->dmamap_xfer, 825 databuf, datalen, NULL, BUS_DMA_NOWAIT); 826 if (error) { 827 printf("%s:%d: unable to load xfer DMA map for" 828 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 829 channel, drive, error); 830 return error; 831 } 832 833 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 834 dma_maps->dmamap_xfer->dm_mapsize, 835 (flags & WDC_DMA_READ) ? 836 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 837 838 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 839 #ifdef DIAGNOSTIC 840 /* A segment must not cross a 64k boundary */ 841 { 842 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 843 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 844 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 845 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 846 printf("pciide_dma: segment %d physical addr 0x%lx" 847 " len 0x%lx not properly aligned\n", 848 seg, phys, len); 849 panic("pciide_dma: buf align"); 850 } 851 } 852 #endif 853 dma_maps->dma_table[seg].base_addr = 854 htopci(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 855 dma_maps->dma_table[seg].byte_count = 856 htopci(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 857 IDEDMA_BYTE_COUNT_MASK); 858 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 859 seg, pcitoh(dma_maps->dma_table[seg].byte_count), 860 pcitoh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 861 862 } 863 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 864 htopci(IDEDMA_BYTE_COUNT_EOT); 865 866 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 867 dma_maps->dmamap_table->dm_mapsize, 868 BUS_DMASYNC_PREWRITE); 869 870 /* Maps are ready. Start DMA function */ 871 #ifdef DIAGNOSTIC 872 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 873 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 874 dma_maps->dmamap_table->dm_segs[0].ds_addr); 875 panic("pciide_dma_init: table align"); 876 } 877 #endif 878 879 /* Clear status bits */ 880 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 881 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 882 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 883 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 884 /* Write table addr */ 885 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 886 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 887 dma_maps->dmamap_table->dm_segs[0].ds_addr); 888 /* set read/write */ 889 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 890 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 891 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 892 return 0; 893 } 894 895 void 896 pciide_dma_start(v, channel, drive, flags) 897 void *v; 898 int channel, drive, flags; 899 { 900 struct pciide_softc *sc = v; 901 902 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 903 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 904 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 905 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 906 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 907 } 908 909 int 910 pciide_dma_finish(v, channel, drive, flags) 911 void *v; 912 int channel, drive; 913 int flags; 914 { 915 struct pciide_softc *sc = v; 916 u_int8_t status; 917 struct pciide_dma_maps *dma_maps = 918 &sc->pciide_channels[channel].dma_maps[drive]; 919 920 /* Unload the map of the data buffer */ 921 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 922 dma_maps->dmamap_xfer->dm_mapsize, 923 (flags & WDC_DMA_READ) ? 924 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 925 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 926 927 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 928 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 929 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 930 DEBUG_XFERS); 931 932 /* stop DMA channel */ 933 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 934 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 935 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 936 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 937 938 /* Clear status bits */ 939 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 940 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 941 status); 942 943 if ((status & IDEDMA_CTL_ERR) != 0) { 944 printf("%s:%d:%d: Bus-Master DMA error: status=0x%x\n", 945 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 946 return -1; 947 } 948 949 if ((flags & WDC_DMA_POLL) == 0 && (status & IDEDMA_CTL_INTR) == 0) { 950 printf("%s:%d:%d: Bus-Master DMA error: missing interrupt, " 951 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 952 drive, status); 953 return -1; 954 } 955 956 if ((status & IDEDMA_CTL_ACT) != 0) { 957 /* data underrun, may be a valid condition for ATAPI */ 958 return 1; 959 } 960 return 0; 961 } 962 963 /* some common code used by several chip_map */ 964 int 965 pciide_chansetup(sc, channel, interface) 966 struct pciide_softc *sc; 967 int channel; 968 pcireg_t interface; 969 { 970 struct pciide_channel *cp = &sc->pciide_channels[channel]; 971 sc->wdc_chanarray[channel] = &cp->wdc_channel; 972 cp->name = PCIIDE_CHANNEL_NAME(channel); 973 cp->wdc_channel.channel = channel; 974 cp->wdc_channel.wdc = &sc->sc_wdcdev; 975 cp->wdc_channel.ch_queue = 976 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 977 if (cp->wdc_channel.ch_queue == NULL) { 978 printf("%s %s channel: " 979 "can't allocate memory for command queue", 980 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 981 return 0; 982 } 983 printf("%s: %s channel %s to %s mode\n", 984 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 985 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 986 "configured" : "wired", 987 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 988 "native-PCI" : "compatibility"); 989 return 1; 990 } 991 992 /* some common code used by several chip channel_map */ 993 void 994 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 995 struct pci_attach_args *pa; 996 struct pciide_channel *cp; 997 pcireg_t interface; 998 bus_size_t *cmdsizep, *ctlsizep; 999 int (*pci_intr) __P((void *)); 1000 { 1001 struct channel_softc *wdc_cp = &cp->wdc_channel; 1002 1003 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1004 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1005 pci_intr); 1006 else 1007 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1008 wdc_cp->channel, cmdsizep, ctlsizep); 1009 1010 if (cp->hw_ok == 0) 1011 return; 1012 wdc_cp->data32iot = wdc_cp->cmd_iot; 1013 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1014 wdcattach(wdc_cp); 1015 } 1016 1017 /* 1018 * Generic code to call to know if a channel can be disabled. Return 1 1019 * if channel can be disabled, 0 if not 1020 */ 1021 int 1022 pciiide_chan_candisable(cp) 1023 struct pciide_channel *cp; 1024 { 1025 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1026 struct channel_softc *wdc_cp = &cp->wdc_channel; 1027 1028 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1029 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1030 printf("%s: disabling %s channel (no drives)\n", 1031 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1032 cp->hw_ok = 0; 1033 return 1; 1034 } 1035 return 0; 1036 } 1037 1038 /* 1039 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1040 * Set hw_ok=0 on failure 1041 */ 1042 void 1043 pciide_map_compat_intr(pa, cp, compatchan, interface) 1044 struct pci_attach_args *pa; 1045 struct pciide_channel *cp; 1046 int compatchan, interface; 1047 { 1048 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1049 struct channel_softc *wdc_cp = &cp->wdc_channel; 1050 1051 if (cp->hw_ok == 0) 1052 return; 1053 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1054 return; 1055 1056 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1057 pa, compatchan, pciide_compat_intr, cp); 1058 if (cp->ih == NULL) { 1059 printf("%s: no compatibility interrupt for use by %s " 1060 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1061 cp->hw_ok = 0; 1062 } 1063 } 1064 1065 void 1066 pciide_print_modes(cp) 1067 struct pciide_channel *cp; 1068 { 1069 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1070 int drive; 1071 struct channel_softc *chp; 1072 struct ata_drive_datas *drvp; 1073 1074 chp = &cp->wdc_channel; 1075 for (drive = 0; drive < 2; drive++) { 1076 drvp = &chp->ch_drive[drive]; 1077 if ((drvp->drive_flags & DRIVE) == 0) 1078 continue; 1079 printf("%s(%s:%d:%d): using PIO mode %d", 1080 drvp->drv_softc->dv_xname, 1081 sc->sc_wdcdev.sc_dev.dv_xname, 1082 chp->channel, drive, drvp->PIO_mode); 1083 if (drvp->drive_flags & DRIVE_DMA) 1084 printf(", DMA mode %d", drvp->DMA_mode); 1085 if (drvp->drive_flags & DRIVE_UDMA) 1086 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1087 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1088 printf(" (using DMA data transfers)"); 1089 printf("\n"); 1090 } 1091 } 1092 1093 void 1094 default_chip_map(sc, pa) 1095 struct pciide_softc *sc; 1096 struct pci_attach_args *pa; 1097 { 1098 struct pciide_channel *cp; 1099 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1100 sc->sc_tag, PCI_CLASS_REG)); 1101 pcireg_t csr; 1102 int channel, drive; 1103 struct ata_drive_datas *drvp; 1104 u_int8_t idedma_ctl; 1105 bus_size_t cmdsize, ctlsize; 1106 char *failreason; 1107 1108 if (pciide_chipen(sc, pa) == 0) 1109 return; 1110 1111 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1112 printf("%s: bus-master DMA support present", 1113 sc->sc_wdcdev.sc_dev.dv_xname); 1114 if (sc->sc_pp == &default_product_desc && 1115 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1116 PCIIDE_OPTIONS_DMA) == 0) { 1117 printf(", but unused (no driver support)"); 1118 sc->sc_dma_ok = 0; 1119 } else { 1120 pciide_mapreg_dma(sc, pa); 1121 if (sc->sc_dma_ok != 0) 1122 printf(", used without full driver " 1123 "support"); 1124 } 1125 } else { 1126 printf("%s: hardware does not support DMA", 1127 sc->sc_wdcdev.sc_dev.dv_xname); 1128 sc->sc_dma_ok = 0; 1129 } 1130 printf("\n"); 1131 if (sc->sc_dma_ok) 1132 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1133 sc->sc_wdcdev.PIO_cap = 0; 1134 sc->sc_wdcdev.DMA_cap = 0; 1135 1136 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1137 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1138 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1139 1140 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1141 cp = &sc->pciide_channels[channel]; 1142 if (pciide_chansetup(sc, channel, interface) == 0) 1143 continue; 1144 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1145 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1146 &ctlsize, pciide_pci_intr); 1147 } else { 1148 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1149 channel, &cmdsize, &ctlsize); 1150 } 1151 if (cp->hw_ok == 0) 1152 continue; 1153 /* 1154 * Check to see if something appears to be there. 1155 */ 1156 failreason = NULL; 1157 if (!wdcprobe(&cp->wdc_channel)) { 1158 failreason = "not responding; disabled or no drives?"; 1159 goto next; 1160 } 1161 /* 1162 * Now, make sure it's actually attributable to this PCI IDE 1163 * channel by trying to access the channel again while the 1164 * PCI IDE controller's I/O space is disabled. (If the 1165 * channel no longer appears to be there, it belongs to 1166 * this controller.) YUCK! 1167 */ 1168 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1169 PCI_COMMAND_STATUS_REG); 1170 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1171 csr & ~PCI_COMMAND_IO_ENABLE); 1172 if (wdcprobe(&cp->wdc_channel)) 1173 failreason = "other hardware responding at addresses"; 1174 pci_conf_write(sc->sc_pc, sc->sc_tag, 1175 PCI_COMMAND_STATUS_REG, csr); 1176 next: 1177 if (failreason) { 1178 printf("%s: %s channel ignored (%s)\n", 1179 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1180 failreason); 1181 cp->hw_ok = 0; 1182 bus_space_unmap(cp->wdc_channel.cmd_iot, 1183 cp->wdc_channel.cmd_ioh, cmdsize); 1184 bus_space_unmap(cp->wdc_channel.ctl_iot, 1185 cp->wdc_channel.ctl_ioh, ctlsize); 1186 } else { 1187 pciide_map_compat_intr(pa, cp, channel, interface); 1188 } 1189 if (cp->hw_ok) { 1190 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1191 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1192 wdcattach(&cp->wdc_channel); 1193 } 1194 } 1195 1196 if (sc->sc_dma_ok == 0) 1197 return; 1198 1199 /* Allocate DMA maps */ 1200 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1201 idedma_ctl = 0; 1202 cp = &sc->pciide_channels[channel]; 1203 for (drive = 0; drive < 2; drive++) { 1204 drvp = &cp->wdc_channel.ch_drive[drive]; 1205 /* If no drive, skip */ 1206 if ((drvp->drive_flags & DRIVE) == 0) 1207 continue; 1208 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1209 continue; 1210 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1211 /* Abort DMA setup */ 1212 printf("%s:%d:%d: can't allocate DMA maps, " 1213 "using PIO transfers\n", 1214 sc->sc_wdcdev.sc_dev.dv_xname, 1215 channel, drive); 1216 drvp->drive_flags &= ~DRIVE_DMA; 1217 } 1218 printf("%s:%d:%d: using DMA data transfers\n", 1219 sc->sc_wdcdev.sc_dev.dv_xname, 1220 channel, drive); 1221 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1222 } 1223 if (idedma_ctl != 0) { 1224 /* Add software bits in status register */ 1225 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1226 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1227 idedma_ctl); 1228 } 1229 } 1230 } 1231 1232 void 1233 piix_chip_map(sc, pa) 1234 struct pciide_softc *sc; 1235 struct pci_attach_args *pa; 1236 { 1237 struct pciide_channel *cp; 1238 int channel; 1239 u_int32_t idetim; 1240 bus_size_t cmdsize, ctlsize; 1241 1242 if (pciide_chipen(sc, pa) == 0) 1243 return; 1244 1245 printf("%s: bus-master DMA support present", 1246 sc->sc_wdcdev.sc_dev.dv_xname); 1247 pciide_mapreg_dma(sc, pa); 1248 printf("\n"); 1249 if (sc->sc_dma_ok) { 1250 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1251 switch(sc->sc_pp->ide_product) { 1252 case PCI_PRODUCT_INTEL_82371AB_IDE: 1253 case PCI_PRODUCT_INTEL_82801AA_IDE: 1254 case PCI_PRODUCT_INTEL_82801AB_IDE: 1255 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1256 } 1257 } 1258 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1259 WDC_CAPABILITY_MODE; 1260 sc->sc_wdcdev.PIO_cap = 4; 1261 sc->sc_wdcdev.DMA_cap = 2; 1262 sc->sc_wdcdev.UDMA_cap = 1263 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1264 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1265 sc->sc_wdcdev.set_modes = piix_setup_channel; 1266 else 1267 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1268 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1269 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1270 1271 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1272 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1273 DEBUG_PROBE); 1274 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1275 WDCDEBUG_PRINT((", sidetim=0x%x", 1276 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1277 DEBUG_PROBE); 1278 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1279 WDCDEBUG_PRINT((", udamreg 0x%x", 1280 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1281 DEBUG_PROBE); 1282 } 1283 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1284 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1285 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1286 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1287 DEBUG_PROBE); 1288 } 1289 1290 } 1291 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1292 1293 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1294 cp = &sc->pciide_channels[channel]; 1295 /* PIIX is compat-only */ 1296 if (pciide_chansetup(sc, channel, 0) == 0) 1297 continue; 1298 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1299 if ((PIIX_IDETIM_READ(idetim, channel) & 1300 PIIX_IDETIM_IDE) == 0) { 1301 printf("%s: %s channel ignored (disabled)\n", 1302 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1303 return; 1304 } 1305 /* PIIX are compat-only pciide devices */ 1306 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1307 if (cp->hw_ok == 0) 1308 continue; 1309 if (pciiide_chan_candisable(cp)) { 1310 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1311 channel); 1312 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1313 idetim); 1314 } 1315 pciide_map_compat_intr(pa, cp, channel, 0); 1316 if (cp->hw_ok == 0) 1317 continue; 1318 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1319 } 1320 1321 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1322 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1323 DEBUG_PROBE); 1324 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1325 WDCDEBUG_PRINT((", sidetim=0x%x", 1326 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1327 DEBUG_PROBE); 1328 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1329 WDCDEBUG_PRINT((", udamreg 0x%x", 1330 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1331 DEBUG_PROBE); 1332 } 1333 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1334 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1335 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1336 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1337 DEBUG_PROBE); 1338 } 1339 } 1340 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1341 } 1342 1343 void 1344 piix_setup_channel(chp) 1345 struct channel_softc *chp; 1346 { 1347 u_int8_t mode[2], drive; 1348 u_int32_t oidetim, idetim, idedma_ctl; 1349 struct pciide_channel *cp = (struct pciide_channel*)chp; 1350 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1351 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1352 1353 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1354 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1355 idedma_ctl = 0; 1356 1357 /* set up new idetim: Enable IDE registers decode */ 1358 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1359 chp->channel); 1360 1361 /* setup DMA */ 1362 pciide_channel_dma_setup(cp); 1363 1364 /* 1365 * Here we have to mess up with drives mode: PIIX can't have 1366 * different timings for master and slave drives. 1367 * We need to find the best combination. 1368 */ 1369 1370 /* If both drives supports DMA, take the lower mode */ 1371 if ((drvp[0].drive_flags & DRIVE_DMA) && 1372 (drvp[1].drive_flags & DRIVE_DMA)) { 1373 mode[0] = mode[1] = 1374 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1375 drvp[0].DMA_mode = mode[0]; 1376 drvp[1].DMA_mode = mode[1]; 1377 goto ok; 1378 } 1379 /* 1380 * If only one drive supports DMA, use its mode, and 1381 * put the other one in PIO mode 0 if mode not compatible 1382 */ 1383 if (drvp[0].drive_flags & DRIVE_DMA) { 1384 mode[0] = drvp[0].DMA_mode; 1385 mode[1] = drvp[1].PIO_mode; 1386 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1387 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1388 mode[1] = drvp[1].PIO_mode = 0; 1389 goto ok; 1390 } 1391 if (drvp[1].drive_flags & DRIVE_DMA) { 1392 mode[1] = drvp[1].DMA_mode; 1393 mode[0] = drvp[0].PIO_mode; 1394 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1395 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1396 mode[0] = drvp[0].PIO_mode = 0; 1397 goto ok; 1398 } 1399 /* 1400 * If both drives are not DMA, takes the lower mode, unless 1401 * one of them is PIO mode < 2 1402 */ 1403 if (drvp[0].PIO_mode < 2) { 1404 mode[0] = drvp[0].PIO_mode = 0; 1405 mode[1] = drvp[1].PIO_mode; 1406 } else if (drvp[1].PIO_mode < 2) { 1407 mode[1] = drvp[1].PIO_mode = 0; 1408 mode[0] = drvp[0].PIO_mode; 1409 } else { 1410 mode[0] = mode[1] = 1411 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1412 drvp[0].PIO_mode = mode[0]; 1413 drvp[1].PIO_mode = mode[1]; 1414 } 1415 ok: /* The modes are setup */ 1416 for (drive = 0; drive < 2; drive++) { 1417 if (drvp[drive].drive_flags & DRIVE_DMA) { 1418 idetim |= piix_setup_idetim_timings( 1419 mode[drive], 1, chp->channel); 1420 goto end; 1421 } 1422 } 1423 /* If we are there, none of the drives are DMA */ 1424 if (mode[0] >= 2) 1425 idetim |= piix_setup_idetim_timings( 1426 mode[0], 0, chp->channel); 1427 else 1428 idetim |= piix_setup_idetim_timings( 1429 mode[1], 0, chp->channel); 1430 end: /* 1431 * timing mode is now set up in the controller. Enable 1432 * it per-drive 1433 */ 1434 for (drive = 0; drive < 2; drive++) { 1435 /* If no drive, skip */ 1436 if ((drvp[drive].drive_flags & DRIVE) == 0) 1437 continue; 1438 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1439 if (drvp[drive].drive_flags & DRIVE_DMA) 1440 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1441 } 1442 if (idedma_ctl != 0) { 1443 /* Add software bits in status register */ 1444 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1445 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1446 idedma_ctl); 1447 } 1448 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1449 pciide_print_modes(cp); 1450 } 1451 1452 void 1453 piix3_4_setup_channel(chp) 1454 struct channel_softc *chp; 1455 { 1456 struct ata_drive_datas *drvp; 1457 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1458 struct pciide_channel *cp = (struct pciide_channel*)chp; 1459 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1460 int drive; 1461 int channel = chp->channel; 1462 1463 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1464 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1465 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1466 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1467 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1468 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1469 PIIX_SIDETIM_RTC_MASK(channel)); 1470 1471 idedma_ctl = 0; 1472 /* If channel disabled, no need to go further */ 1473 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1474 return; 1475 /* set up new idetim: Enable IDE registers decode */ 1476 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1477 1478 /* setup DMA if needed */ 1479 pciide_channel_dma_setup(cp); 1480 1481 for (drive = 0; drive < 2; drive++) { 1482 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1483 PIIX_UDMATIM_SET(0x3, channel, drive)); 1484 drvp = &chp->ch_drive[drive]; 1485 /* If no drive, skip */ 1486 if ((drvp->drive_flags & DRIVE) == 0) 1487 continue; 1488 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1489 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1490 goto pio; 1491 1492 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1493 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1494 ideconf |= PIIX_CONFIG_PINGPONG; 1495 } 1496 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1497 /* setup Ultra/66 */ 1498 if (drvp->UDMA_mode > 2 && 1499 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1500 drvp->UDMA_mode = 2; 1501 if (drvp->UDMA_mode > 2) 1502 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1503 else 1504 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1505 } 1506 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1507 (drvp->drive_flags & DRIVE_UDMA)) { 1508 /* use Ultra/DMA */ 1509 drvp->drive_flags &= ~DRIVE_DMA; 1510 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1511 udmareg |= PIIX_UDMATIM_SET( 1512 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1513 } else { 1514 /* use Multiword DMA */ 1515 drvp->drive_flags &= ~DRIVE_UDMA; 1516 if (drive == 0) { 1517 idetim |= piix_setup_idetim_timings( 1518 drvp->DMA_mode, 1, channel); 1519 } else { 1520 sidetim |= piix_setup_sidetim_timings( 1521 drvp->DMA_mode, 1, channel); 1522 idetim =PIIX_IDETIM_SET(idetim, 1523 PIIX_IDETIM_SITRE, channel); 1524 } 1525 } 1526 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1527 1528 pio: /* use PIO mode */ 1529 idetim |= piix_setup_idetim_drvs(drvp); 1530 if (drive == 0) { 1531 idetim |= piix_setup_idetim_timings( 1532 drvp->PIO_mode, 0, channel); 1533 } else { 1534 sidetim |= piix_setup_sidetim_timings( 1535 drvp->PIO_mode, 0, channel); 1536 idetim =PIIX_IDETIM_SET(idetim, 1537 PIIX_IDETIM_SITRE, channel); 1538 } 1539 } 1540 if (idedma_ctl != 0) { 1541 /* Add software bits in status register */ 1542 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1543 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1544 idedma_ctl); 1545 } 1546 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1547 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1548 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1549 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1550 pciide_print_modes(cp); 1551 } 1552 1553 1554 /* setup ISP and RTC fields, based on mode */ 1555 static u_int32_t 1556 piix_setup_idetim_timings(mode, dma, channel) 1557 u_int8_t mode; 1558 u_int8_t dma; 1559 u_int8_t channel; 1560 { 1561 1562 if (dma) 1563 return PIIX_IDETIM_SET(0, 1564 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1565 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1566 channel); 1567 else 1568 return PIIX_IDETIM_SET(0, 1569 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1570 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1571 channel); 1572 } 1573 1574 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1575 static u_int32_t 1576 piix_setup_idetim_drvs(drvp) 1577 struct ata_drive_datas *drvp; 1578 { 1579 u_int32_t ret = 0; 1580 struct channel_softc *chp = drvp->chnl_softc; 1581 u_int8_t channel = chp->channel; 1582 u_int8_t drive = drvp->drive; 1583 1584 /* 1585 * If drive is using UDMA, timings setups are independant 1586 * So just check DMA and PIO here. 1587 */ 1588 if (drvp->drive_flags & DRIVE_DMA) { 1589 /* if mode = DMA mode 0, use compatible timings */ 1590 if ((drvp->drive_flags & DRIVE_DMA) && 1591 drvp->DMA_mode == 0) { 1592 drvp->PIO_mode = 0; 1593 return ret; 1594 } 1595 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1596 /* 1597 * PIO and DMA timings are the same, use fast timings for PIO 1598 * too, else use compat timings. 1599 */ 1600 if ((piix_isp_pio[drvp->PIO_mode] != 1601 piix_isp_dma[drvp->DMA_mode]) || 1602 (piix_rtc_pio[drvp->PIO_mode] != 1603 piix_rtc_dma[drvp->DMA_mode])) 1604 drvp->PIO_mode = 0; 1605 /* if PIO mode <= 2, use compat timings for PIO */ 1606 if (drvp->PIO_mode <= 2) { 1607 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1608 channel); 1609 return ret; 1610 } 1611 } 1612 1613 /* 1614 * Now setup PIO modes. If mode < 2, use compat timings. 1615 * Else enable fast timings. Enable IORDY and prefetch/post 1616 * if PIO mode >= 3. 1617 */ 1618 1619 if (drvp->PIO_mode < 2) 1620 return ret; 1621 1622 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1623 if (drvp->PIO_mode >= 3) { 1624 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1625 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1626 } 1627 return ret; 1628 } 1629 1630 /* setup values in SIDETIM registers, based on mode */ 1631 static u_int32_t 1632 piix_setup_sidetim_timings(mode, dma, channel) 1633 u_int8_t mode; 1634 u_int8_t dma; 1635 u_int8_t channel; 1636 { 1637 if (dma) 1638 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1639 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1640 else 1641 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1642 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1643 } 1644 1645 void 1646 apollo_chip_map(sc, pa) 1647 struct pciide_softc *sc; 1648 struct pci_attach_args *pa; 1649 { 1650 struct pciide_channel *cp; 1651 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1652 sc->sc_tag, PCI_CLASS_REG)); 1653 int channel; 1654 u_int32_t ideconf; 1655 bus_size_t cmdsize, ctlsize; 1656 1657 if (pciide_chipen(sc, pa) == 0) 1658 return; 1659 printf("%s: bus-master DMA support present", 1660 sc->sc_wdcdev.sc_dev.dv_xname); 1661 pciide_mapreg_dma(sc, pa); 1662 printf("\n"); 1663 if (sc->sc_dma_ok) { 1664 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1665 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1666 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1667 } 1668 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE; 1669 sc->sc_wdcdev.PIO_cap = 4; 1670 sc->sc_wdcdev.DMA_cap = 2; 1671 sc->sc_wdcdev.UDMA_cap = 2; 1672 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1673 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1674 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1675 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1676 1677 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1678 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1679 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1680 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1681 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1682 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1683 DEBUG_PROBE); 1684 1685 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1686 cp = &sc->pciide_channels[channel]; 1687 if (pciide_chansetup(sc, channel, interface) == 0) 1688 continue; 1689 1690 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1691 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1692 printf("%s: %s channel ignored (disabled)\n", 1693 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1694 return; 1695 } 1696 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1697 pciide_pci_intr); 1698 if (cp->hw_ok == 0) 1699 continue; 1700 if (pciiide_chan_candisable(cp)) { 1701 ideconf &= ~APO_IDECONF_EN(channel); 1702 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1703 ideconf); 1704 } 1705 pciide_map_compat_intr(pa, cp, channel, interface); 1706 1707 if (cp->hw_ok == 0) 1708 continue; 1709 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1710 } 1711 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1712 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1713 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1714 } 1715 1716 void 1717 apollo_setup_channel(chp) 1718 struct channel_softc *chp; 1719 { 1720 u_int32_t udmatim_reg, datatim_reg; 1721 u_int8_t idedma_ctl; 1722 int mode, drive; 1723 struct ata_drive_datas *drvp; 1724 struct pciide_channel *cp = (struct pciide_channel*)chp; 1725 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1726 1727 idedma_ctl = 0; 1728 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1729 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1730 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1731 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1732 1733 /* setup DMA if needed */ 1734 pciide_channel_dma_setup(cp); 1735 1736 for (drive = 0; drive < 2; drive++) { 1737 drvp = &chp->ch_drive[drive]; 1738 /* If no drive, skip */ 1739 if ((drvp->drive_flags & DRIVE) == 0) 1740 continue; 1741 /* add timing values, setup DMA if needed */ 1742 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1743 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1744 mode = drvp->PIO_mode; 1745 goto pio; 1746 } 1747 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1748 (drvp->drive_flags & DRIVE_UDMA)) { 1749 /* use Ultra/DMA */ 1750 drvp->drive_flags &= ~DRIVE_DMA; 1751 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1752 APO_UDMA_EN_MTH(chp->channel, drive) | 1753 APO_UDMA_TIME(chp->channel, drive, 1754 apollo_udma_tim[drvp->UDMA_mode]); 1755 /* can use PIO timings, MW DMA unused */ 1756 mode = drvp->PIO_mode; 1757 } else { 1758 /* use Multiword DMA */ 1759 drvp->drive_flags &= ~DRIVE_UDMA; 1760 /* mode = min(pio, dma+2) */ 1761 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1762 mode = drvp->PIO_mode; 1763 else 1764 mode = drvp->DMA_mode + 2; 1765 } 1766 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1767 1768 pio: /* setup PIO mode */ 1769 if (mode <= 2) { 1770 drvp->DMA_mode = 0; 1771 drvp->PIO_mode = 0; 1772 mode = 0; 1773 } else { 1774 drvp->PIO_mode = mode; 1775 drvp->DMA_mode = mode - 2; 1776 } 1777 datatim_reg |= 1778 APO_DATATIM_PULSE(chp->channel, drive, 1779 apollo_pio_set[mode]) | 1780 APO_DATATIM_RECOV(chp->channel, drive, 1781 apollo_pio_rec[mode]); 1782 } 1783 if (idedma_ctl != 0) { 1784 /* Add software bits in status register */ 1785 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1786 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1787 idedma_ctl); 1788 } 1789 pciide_print_modes(cp); 1790 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 1791 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 1792 } 1793 1794 void 1795 cmd_channel_map(pa, sc, channel) 1796 struct pci_attach_args *pa; 1797 struct pciide_softc *sc; 1798 int channel; 1799 { 1800 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1801 bus_size_t cmdsize, ctlsize; 1802 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 1803 int interface = 1804 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1805 1806 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1807 cp->name = PCIIDE_CHANNEL_NAME(channel); 1808 cp->wdc_channel.channel = channel; 1809 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1810 1811 if (channel > 0) { 1812 cp->wdc_channel.ch_queue = 1813 sc->pciide_channels[0].wdc_channel.ch_queue; 1814 } else { 1815 cp->wdc_channel.ch_queue = 1816 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1817 } 1818 if (cp->wdc_channel.ch_queue == NULL) { 1819 printf("%s %s channel: " 1820 "can't allocate memory for command queue", 1821 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1822 return; 1823 } 1824 1825 printf("%s: %s channel %s to %s mode\n", 1826 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1827 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1828 "configured" : "wired", 1829 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1830 "native-PCI" : "compatibility"); 1831 1832 /* 1833 * with a CMD PCI64x, if we get here, the first channel is enabled: 1834 * there's no way to disable the first channel without disabling 1835 * the whole device 1836 */ 1837 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 1838 printf("%s: %s channel ignored (disabled)\n", 1839 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1840 return; 1841 } 1842 1843 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 1844 if (cp->hw_ok == 0) 1845 return; 1846 if (channel == 1) { 1847 if (pciiide_chan_candisable(cp)) { 1848 ctrl &= ~CMD_CTRL_2PORT; 1849 pciide_pci_write(pa->pa_pc, pa->pa_tag, 1850 CMD_CTRL, ctrl); 1851 } 1852 } 1853 pciide_map_compat_intr(pa, cp, channel, interface); 1854 } 1855 1856 int 1857 cmd_pci_intr(arg) 1858 void *arg; 1859 { 1860 struct pciide_softc *sc = arg; 1861 struct pciide_channel *cp; 1862 struct channel_softc *wdc_cp; 1863 int i, rv, crv; 1864 u_int32_t priirq, secirq; 1865 1866 rv = 0; 1867 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 1868 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 1869 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1870 cp = &sc->pciide_channels[i]; 1871 wdc_cp = &cp->wdc_channel; 1872 /* If a compat channel skip. */ 1873 if (cp->compat) 1874 continue; 1875 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 1876 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 1877 crv = wdcintr(wdc_cp); 1878 if (crv == 0) 1879 printf("%s:%d: bogus intr\n", 1880 sc->sc_wdcdev.sc_dev.dv_xname, i); 1881 else 1882 rv = 1; 1883 } 1884 } 1885 return rv; 1886 } 1887 1888 void 1889 cmd_chip_map(sc, pa) 1890 struct pciide_softc *sc; 1891 struct pci_attach_args *pa; 1892 { 1893 int channel; 1894 1895 /* 1896 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 1897 * and base adresses registers can be disabled at 1898 * hardware level. In this case, the device is wired 1899 * in compat mode and its first channel is always enabled, 1900 * but we can't rely on PCI_COMMAND_IO_ENABLE. 1901 * In fact, it seems that the first channel of the CMD PCI0640 1902 * can't be disabled. 1903 */ 1904 1905 #ifdef PCIIDE_CMD064x_DISABLE 1906 if (pciide_chipen(sc, pa) == 0) 1907 return; 1908 #endif 1909 1910 printf("%s: hardware does not support DMA\n", 1911 sc->sc_wdcdev.sc_dev.dv_xname); 1912 sc->sc_dma_ok = 0; 1913 1914 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1915 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1916 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1917 1918 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1919 cmd_channel_map(pa, sc, channel); 1920 } 1921 } 1922 1923 void 1924 cmd0643_6_chip_map(sc, pa) 1925 struct pciide_softc *sc; 1926 struct pci_attach_args *pa; 1927 { 1928 struct pciide_channel *cp; 1929 int channel; 1930 1931 /* 1932 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 1933 * and base adresses registers can be disabled at 1934 * hardware level. In this case, the device is wired 1935 * in compat mode and its first channel is always enabled, 1936 * but we can't rely on PCI_COMMAND_IO_ENABLE. 1937 * In fact, it seems that the first channel of the CMD PCI0640 1938 * can't be disabled. 1939 */ 1940 1941 #ifdef PCIIDE_CMD064x_DISABLE 1942 if (pciide_chipen(sc, pa) == 0) 1943 return; 1944 #endif 1945 printf("%s: bus-master DMA support present", 1946 sc->sc_wdcdev.sc_dev.dv_xname); 1947 pciide_mapreg_dma(sc, pa); 1948 printf("\n"); 1949 if (sc->sc_dma_ok) 1950 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1951 1952 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1953 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1954 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1955 WDC_CAPABILITY_MODE; 1956 sc->sc_wdcdev.PIO_cap = 4; 1957 sc->sc_wdcdev.DMA_cap = 2; 1958 sc->sc_wdcdev.set_modes = cmd0643_6_setup_channel; 1959 1960 WDCDEBUG_PRINT(("cmd0643_6_chip_map: old timings reg 0x%x 0x%x\n", 1961 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 1962 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 1963 DEBUG_PROBE); 1964 1965 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1966 cp = &sc->pciide_channels[channel]; 1967 cmd_channel_map(pa, sc, channel); 1968 if (cp->hw_ok == 0) 1969 continue; 1970 cmd0643_6_setup_channel(&cp->wdc_channel); 1971 } 1972 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 1973 WDCDEBUG_PRINT(("cmd0643_6_chip_map: timings reg now 0x%x 0x%x\n", 1974 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 1975 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 1976 DEBUG_PROBE); 1977 } 1978 1979 void 1980 cmd0643_6_setup_channel(chp) 1981 struct channel_softc *chp; 1982 { 1983 struct ata_drive_datas *drvp; 1984 u_int8_t tim; 1985 u_int32_t idedma_ctl; 1986 int drive; 1987 struct pciide_channel *cp = (struct pciide_channel*)chp; 1988 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1989 1990 idedma_ctl = 0; 1991 /* setup DMA if needed */ 1992 pciide_channel_dma_setup(cp); 1993 1994 for (drive = 0; drive < 2; drive++) { 1995 drvp = &chp->ch_drive[drive]; 1996 /* If no drive, skip */ 1997 if ((drvp->drive_flags & DRIVE) == 0) 1998 continue; 1999 /* add timing values, setup DMA if needed */ 2000 tim = cmd0643_6_data_tim_pio[drvp->PIO_mode]; 2001 if (drvp->drive_flags & DRIVE_DMA) { 2002 /* 2003 * use Multiword DMA. 2004 * Timings will be used for both PIO and DMA, so adjust 2005 * DMA mode if needed 2006 */ 2007 if (drvp->PIO_mode >= 3 && 2008 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2009 drvp->DMA_mode = drvp->PIO_mode - 2; 2010 } 2011 tim = cmd0643_6_data_tim_dma[drvp->DMA_mode]; 2012 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2013 } 2014 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2015 CMD_DATA_TIM(chp->channel, drive), tim); 2016 } 2017 if (idedma_ctl != 0) { 2018 /* Add software bits in status register */ 2019 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2020 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2021 idedma_ctl); 2022 } 2023 pciide_print_modes(cp); 2024 } 2025 2026 void 2027 cy693_chip_map(sc, pa) 2028 struct pciide_softc *sc; 2029 struct pci_attach_args *pa; 2030 { 2031 struct pciide_channel *cp; 2032 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2033 sc->sc_tag, PCI_CLASS_REG)); 2034 int compatchan; 2035 bus_size_t cmdsize, ctlsize; 2036 2037 if (pciide_chipen(sc, pa) == 0) 2038 return; 2039 /* 2040 * this chip has 2 PCI IDE functions, one for primary and one for 2041 * secondary. So we need to call pciide_mapregs_compat() with 2042 * the real channel 2043 */ 2044 if (pa->pa_function == 1) { 2045 compatchan = 0; 2046 } else if (pa->pa_function == 2) { 2047 compatchan = 1; 2048 } else { 2049 printf("%s: unexpected PCI function %d\n", 2050 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2051 cp->hw_ok = 0; 2052 return; 2053 } 2054 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2055 printf("%s: bus-master DMA support present", 2056 sc->sc_wdcdev.sc_dev.dv_xname); 2057 pciide_mapreg_dma(sc, pa); 2058 } else { 2059 printf("%s: hardware does not support DMA", 2060 sc->sc_wdcdev.sc_dev.dv_xname); 2061 sc->sc_dma_ok = 0; 2062 } 2063 printf("\n"); 2064 2065 if (sc->sc_dma_ok) 2066 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2067 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2068 WDC_CAPABILITY_MODE; 2069 sc->sc_wdcdev.PIO_cap = 4; 2070 sc->sc_wdcdev.DMA_cap = 2; 2071 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2072 2073 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2074 sc->sc_wdcdev.nchannels = 1; 2075 2076 /* Only one channel for this chip; if we are here it's enabled */ 2077 cp = &sc->pciide_channels[0]; 2078 sc->wdc_chanarray[0] = &cp->wdc_channel; 2079 cp->name = PCIIDE_CHANNEL_NAME(0); 2080 cp->wdc_channel.channel = 0; 2081 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2082 cp->wdc_channel.ch_queue = 2083 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2084 if (cp->wdc_channel.ch_queue == NULL) { 2085 printf("%s primary channel: " 2086 "can't allocate memory for command queue", 2087 sc->sc_wdcdev.sc_dev.dv_xname); 2088 return; 2089 } 2090 printf("%s: primary channel %s to ", 2091 sc->sc_wdcdev.sc_dev.dv_xname, 2092 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2093 "configured" : "wired"); 2094 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2095 printf("native-PCI"); 2096 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2097 pciide_pci_intr); 2098 } else { 2099 printf("compatibility"); 2100 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2101 &cmdsize, &ctlsize); 2102 } 2103 printf(" mode\n"); 2104 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2105 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2106 wdcattach(&cp->wdc_channel); 2107 if (pciiide_chan_candisable(cp)) { 2108 pci_conf_write(sc->sc_pc, sc->sc_tag, 2109 PCI_COMMAND_STATUS_REG, 0); 2110 } 2111 pciide_map_compat_intr(pa, cp, compatchan, interface); 2112 if (cp->hw_ok == 0) 2113 return; 2114 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2115 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2116 cy693_setup_channel(&cp->wdc_channel); 2117 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2118 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2119 } 2120 2121 void 2122 cy693_setup_channel(chp) 2123 struct channel_softc *chp; 2124 { 2125 struct ata_drive_datas *drvp; 2126 int drive; 2127 u_int32_t cy_cmd_ctrl; 2128 u_int32_t idedma_ctl; 2129 struct pciide_channel *cp = (struct pciide_channel*)chp; 2130 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2131 int dma_mode = -1; 2132 2133 cy_cmd_ctrl = idedma_ctl = 0; 2134 2135 /* setup DMA if needed */ 2136 pciide_channel_dma_setup(cp); 2137 2138 for (drive = 0; drive < 2; drive++) { 2139 drvp = &chp->ch_drive[drive]; 2140 /* If no drive, skip */ 2141 if ((drvp->drive_flags & DRIVE) == 0) 2142 continue; 2143 /* add timing values, setup DMA if needed */ 2144 if (drvp->drive_flags & DRIVE_DMA) { 2145 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2146 /* use Multiword DMA */ 2147 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2148 dma_mode = drvp->DMA_mode; 2149 } 2150 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2151 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2152 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2153 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2154 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2155 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2156 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2157 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2158 } 2159 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2160 chp->ch_drive[0].DMA_mode = dma_mode; 2161 chp->ch_drive[1].DMA_mode = dma_mode; 2162 pciide_print_modes(cp); 2163 if (idedma_ctl != 0) { 2164 /* Add software bits in status register */ 2165 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2166 IDEDMA_CTL, idedma_ctl); 2167 } 2168 } 2169 2170 void 2171 sis_chip_map(sc, pa) 2172 struct pciide_softc *sc; 2173 struct pci_attach_args *pa; 2174 { 2175 struct pciide_channel *cp; 2176 int channel; 2177 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2178 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2179 sc->sc_tag, PCI_CLASS_REG)); 2180 bus_size_t cmdsize, ctlsize; 2181 2182 if (pciide_chipen(sc, pa) == 0) 2183 return; 2184 printf("%s: bus-master DMA support present", 2185 sc->sc_wdcdev.sc_dev.dv_xname); 2186 pciide_mapreg_dma(sc, pa); 2187 printf("\n"); 2188 if (sc->sc_dma_ok) 2189 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2190 2191 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2192 WDC_CAPABILITY_MODE; 2193 sc->sc_wdcdev.PIO_cap = 4; 2194 sc->sc_wdcdev.DMA_cap = 2; 2195 sc->sc_wdcdev.UDMA_cap = 2; 2196 sc->sc_wdcdev.set_modes = sis_setup_channel; 2197 2198 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2199 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2200 2201 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2202 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2203 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2204 2205 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2206 cp = &sc->pciide_channels[channel]; 2207 if (pciide_chansetup(sc, channel, interface) == 0) 2208 continue; 2209 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2210 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2211 printf("%s: %s channel ignored (disabled)\n", 2212 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2213 return; 2214 } 2215 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2216 pciide_pci_intr); 2217 if (cp->hw_ok == 0) 2218 continue; 2219 if (pciiide_chan_candisable(cp)) { 2220 if (channel == 0) 2221 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2222 else 2223 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2224 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2225 sis_ctr0); 2226 } 2227 pciide_map_compat_intr(pa, cp, channel, interface); 2228 if (cp->hw_ok == 0) 2229 continue; 2230 sis_setup_channel(&cp->wdc_channel); 2231 } 2232 } 2233 2234 void 2235 sis_setup_channel(chp) 2236 struct channel_softc *chp; 2237 { 2238 struct ata_drive_datas *drvp; 2239 int drive; 2240 u_int32_t sis_tim; 2241 u_int32_t idedma_ctl; 2242 struct pciide_channel *cp = (struct pciide_channel*)chp; 2243 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2244 2245 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2246 "channel %d 0x%x\n", chp->channel, 2247 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2248 DEBUG_PROBE); 2249 sis_tim = 0; 2250 idedma_ctl = 0; 2251 /* setup DMA if needed */ 2252 pciide_channel_dma_setup(cp); 2253 2254 for (drive = 0; drive < 2; drive++) { 2255 drvp = &chp->ch_drive[drive]; 2256 /* If no drive, skip */ 2257 if ((drvp->drive_flags & DRIVE) == 0) 2258 continue; 2259 /* add timing values, setup DMA if needed */ 2260 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2261 (drvp->drive_flags & DRIVE_UDMA) == 0) 2262 goto pio; 2263 2264 if (drvp->drive_flags & DRIVE_UDMA) { 2265 /* use Ultra/DMA */ 2266 drvp->drive_flags &= ~DRIVE_DMA; 2267 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2268 SIS_TIM_UDMA_TIME_OFF(drive); 2269 sis_tim |= SIS_TIM_UDMA_EN(drive); 2270 } else { 2271 /* 2272 * use Multiword DMA 2273 * Timings will be used for both PIO and DMA, 2274 * so adjust DMA mode if needed 2275 */ 2276 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2277 drvp->PIO_mode = drvp->DMA_mode + 2; 2278 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2279 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2280 drvp->PIO_mode - 2 : 0; 2281 if (drvp->DMA_mode == 0) 2282 drvp->PIO_mode = 0; 2283 } 2284 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2285 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2286 SIS_TIM_ACT_OFF(drive); 2287 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2288 SIS_TIM_REC_OFF(drive); 2289 } 2290 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2291 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2292 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2293 if (idedma_ctl != 0) { 2294 /* Add software bits in status register */ 2295 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2296 IDEDMA_CTL, idedma_ctl); 2297 } 2298 pciide_print_modes(cp); 2299 } 2300 2301 void 2302 acer_chip_map(sc, pa) 2303 struct pciide_softc *sc; 2304 struct pci_attach_args *pa; 2305 { 2306 struct pciide_channel *cp; 2307 int channel; 2308 pcireg_t cr, interface; 2309 bus_size_t cmdsize, ctlsize; 2310 2311 if (pciide_chipen(sc, pa) == 0) 2312 return; 2313 printf("%s: bus-master DMA support present", 2314 sc->sc_wdcdev.sc_dev.dv_xname); 2315 pciide_mapreg_dma(sc, pa); 2316 printf("\n"); 2317 if (sc->sc_dma_ok) 2318 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2319 2320 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2321 WDC_CAPABILITY_MODE; 2322 2323 sc->sc_wdcdev.PIO_cap = 4; 2324 sc->sc_wdcdev.DMA_cap = 2; 2325 sc->sc_wdcdev.UDMA_cap = 2; 2326 sc->sc_wdcdev.set_modes = acer_setup_channel; 2327 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2328 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2329 2330 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2331 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2332 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2333 2334 /* Enable "microsoft register bits" R/W. */ 2335 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2336 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2337 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2338 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2339 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2340 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2341 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2342 ~ACER_CHANSTATUSREGS_RO); 2343 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2344 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2345 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2346 /* Don't use cr, re-read the real register content instead */ 2347 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2348 PCI_CLASS_REG)); 2349 2350 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2351 cp = &sc->pciide_channels[channel]; 2352 if (pciide_chansetup(sc, channel, interface) == 0) 2353 continue; 2354 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2355 printf("%s: %s channel ignored (disabled)\n", 2356 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2357 continue; 2358 } 2359 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2360 acer_pci_intr); 2361 if (cp->hw_ok == 0) 2362 continue; 2363 if (pciiide_chan_candisable(cp)) { 2364 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2365 pci_conf_write(sc->sc_pc, sc->sc_tag, 2366 PCI_CLASS_REG, cr); 2367 } 2368 pciide_map_compat_intr(pa, cp, channel, interface); 2369 acer_setup_channel(&cp->wdc_channel); 2370 } 2371 } 2372 2373 void 2374 acer_setup_channel(chp) 2375 struct channel_softc *chp; 2376 { 2377 struct ata_drive_datas *drvp; 2378 int drive; 2379 u_int32_t acer_fifo_udma; 2380 u_int32_t idedma_ctl; 2381 struct pciide_channel *cp = (struct pciide_channel*)chp; 2382 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2383 2384 idedma_ctl = 0; 2385 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2386 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2387 acer_fifo_udma), DEBUG_PROBE); 2388 /* setup DMA if needed */ 2389 pciide_channel_dma_setup(cp); 2390 2391 for (drive = 0; drive < 2; drive++) { 2392 drvp = &chp->ch_drive[drive]; 2393 /* If no drive, skip */ 2394 if ((drvp->drive_flags & DRIVE) == 0) 2395 continue; 2396 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2397 "channel %d drive %d 0x%x\n", chp->channel, drive, 2398 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2399 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2400 /* clear FIFO/DMA mode */ 2401 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2402 ACER_UDMA_EN(chp->channel, drive) | 2403 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2404 2405 /* add timing values, setup DMA if needed */ 2406 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2407 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2408 acer_fifo_udma |= 2409 ACER_FTH_OPL(chp->channel, drive, 0x1); 2410 goto pio; 2411 } 2412 2413 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2414 if (drvp->drive_flags & DRIVE_UDMA) { 2415 /* use Ultra/DMA */ 2416 drvp->drive_flags &= ~DRIVE_DMA; 2417 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2418 acer_fifo_udma |= 2419 ACER_UDMA_TIM(chp->channel, drive, 2420 acer_udma[drvp->UDMA_mode]); 2421 } else { 2422 /* 2423 * use Multiword DMA 2424 * Timings will be used for both PIO and DMA, 2425 * so adjust DMA mode if needed 2426 */ 2427 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2428 drvp->PIO_mode = drvp->DMA_mode + 2; 2429 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2430 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2431 drvp->PIO_mode - 2 : 0; 2432 if (drvp->DMA_mode == 0) 2433 drvp->PIO_mode = 0; 2434 } 2435 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2436 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2437 ACER_IDETIM(chp->channel, drive), 2438 acer_pio[drvp->PIO_mode]); 2439 } 2440 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2441 acer_fifo_udma), DEBUG_PROBE); 2442 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2443 if (idedma_ctl != 0) { 2444 /* Add software bits in status register */ 2445 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2446 IDEDMA_CTL, idedma_ctl); 2447 } 2448 pciide_print_modes(cp); 2449 } 2450 2451 int 2452 acer_pci_intr(arg) 2453 void *arg; 2454 { 2455 struct pciide_softc *sc = arg; 2456 struct pciide_channel *cp; 2457 struct channel_softc *wdc_cp; 2458 int i, rv, crv; 2459 u_int32_t chids; 2460 2461 rv = 0; 2462 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2463 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2464 cp = &sc->pciide_channels[i]; 2465 wdc_cp = &cp->wdc_channel; 2466 /* If a compat channel skip. */ 2467 if (cp->compat) 2468 continue; 2469 if (chids & ACER_CHIDS_INT(i)) { 2470 crv = wdcintr(wdc_cp); 2471 if (crv == 0) 2472 printf("%s:%d: bogus intr\n", 2473 sc->sc_wdcdev.sc_dev.dv_xname, i); 2474 else 2475 rv = 1; 2476 } 2477 } 2478 return rv; 2479 } 2480 2481 void 2482 pdc202xx_chip_map(sc, pa) 2483 struct pciide_softc *sc; 2484 struct pci_attach_args *pa; 2485 { 2486 struct pciide_channel *cp; 2487 int channel; 2488 pcireg_t interface, st, mode; 2489 bus_size_t cmdsize, ctlsize; 2490 2491 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2492 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 2493 DEBUG_PROBE); 2494 if (pciide_chipen(sc, pa) == 0) 2495 return; 2496 2497 /* turn off RAID mode */ 2498 st &= ~PDC2xx_STATE_IDERAID; 2499 2500 /* 2501 * can't rely on the PCI_CLASS_REG content if the chip was in raid 2502 * mode. We have to fake interface 2503 */ 2504 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 2505 if (st & PDC2xx_STATE_NATIVE) 2506 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2507 2508 printf("%s: bus-master DMA support present", 2509 sc->sc_wdcdev.sc_dev.dv_xname); 2510 pciide_mapreg_dma(sc, pa); 2511 printf("\n"); 2512 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2513 WDC_CAPABILITY_MODE; 2514 if (sc->sc_dma_ok) 2515 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2516 sc->sc_wdcdev.PIO_cap = 4; 2517 sc->sc_wdcdev.DMA_cap = 2; 2518 if (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 2519 sc->sc_wdcdev.UDMA_cap = 4; 2520 else 2521 sc->sc_wdcdev.UDMA_cap = 2; 2522 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 2523 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2524 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2525 2526 /* setup failsafe defaults */ 2527 mode = 0; 2528 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 2529 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 2530 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 2531 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 2532 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2533 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 2534 "initial timings 0x%x, now 0x%x\n", channel, 2535 pci_conf_read(sc->sc_pc, sc->sc_tag, 2536 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 2537 DEBUG_PROBE); 2538 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 2539 mode | PDC2xx_TIM_IORDYp); 2540 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 2541 "initial timings 0x%x, now 0x%x\n", channel, 2542 pci_conf_read(sc->sc_pc, sc->sc_tag, 2543 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 2544 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 2545 mode); 2546 } 2547 2548 mode = PDC2xx_SCR_DMA; 2549 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); /* the BIOS set it up this way */ 2550 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 2551 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 2552 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 2553 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 2554 DEBUG_PROBE); 2555 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 2556 2557 /* controller initial state register is OK even without BIOS */ 2558 /* The Linux driver does this */ 2559 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 2560 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 2561 DEBUG_PROBE); 2562 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 2563 mode | 0x1); 2564 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 2565 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 2566 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 2567 mode | 0x1); 2568 2569 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2570 cp = &sc->pciide_channels[channel]; 2571 if (pciide_chansetup(sc, channel, interface) == 0) 2572 continue; 2573 if ((st & PDC2xx_STATE_EN(channel)) == 0) { 2574 printf("%s: %s channel ignored (disabled)\n", 2575 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2576 continue; 2577 } 2578 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2579 pdc202xx_pci_intr); 2580 if (cp->hw_ok == 0) 2581 continue; 2582 if (pciiide_chan_candisable(cp)) 2583 st &= ~PDC2xx_STATE_EN(channel); 2584 pciide_map_compat_intr(pa, cp, channel, interface); 2585 pdc202xx_setup_channel(&cp->wdc_channel); 2586 } 2587 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 2588 DEBUG_PROBE); 2589 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 2590 return; 2591 } 2592 2593 void 2594 pdc202xx_setup_channel(chp) 2595 struct channel_softc *chp; 2596 { 2597 struct ata_drive_datas *drvp; 2598 int drive; 2599 pcireg_t mode; 2600 u_int32_t idedma_ctl; 2601 struct pciide_channel *cp = (struct pciide_channel*)chp; 2602 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2603 2604 /* setup DMA if needed */ 2605 pciide_channel_dma_setup(cp); 2606 2607 idedma_ctl = 0; 2608 for (drive = 0; drive < 2; drive++) { 2609 drvp = &chp->ch_drive[drive]; 2610 /* If no drive, skip */ 2611 if ((drvp->drive_flags & DRIVE) == 0) 2612 continue; 2613 mode = PDC2xx_TIM_IORDY; 2614 if (drvp->drive_flags & DRIVE_ATA) 2615 mode |= PDC2xx_TIM_PRE; 2616 if (drvp->drive_flags & DRIVE_UDMA) { 2617 mode = PDC2xx_TIM_SET_MB(mode, 2618 pdc2xx_udma_mb[drvp->UDMA_mode]); 2619 mode = PDC2xx_TIM_SET_MC(mode, 2620 pdc2xx_udma_mc[drvp->UDMA_mode]); 2621 drvp->drive_flags &= ~DRIVE_DMA; 2622 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2623 } else if (drvp->drive_flags & DRIVE_DMA) { 2624 mode = PDC2xx_TIM_SET_MB(mode, 2625 pdc2xx_dma_mb[drvp->DMA_mode]); 2626 mode = PDC2xx_TIM_SET_MC(mode, 2627 pdc2xx_dma_mc[drvp->DMA_mode]); 2628 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2629 } else { 2630 mode = PDC2xx_TIM_SET_MB(mode, 2631 pdc2xx_dma_mb[0]); 2632 mode = PDC2xx_TIM_SET_MC(mode, 2633 pdc2xx_dma_mc[0]); 2634 } 2635 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 2636 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 2637 mode |= PDC2xx_TIM_SYNC; 2638 if (drvp->PIO_mode >= 3 &&(drvp->drive_flags & DRIVE_ATA)) 2639 mode |= PDC2xx_TIM_ERRDY; 2640 if (drive == 0) 2641 mode |= PDC2xx_TIM_IORDYp; 2642 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 2643 "timings 0x%x\n", 2644 sc->sc_wdcdev.sc_dev.dv_xname, 2645 chp->channel, drive, mode), DEBUG_PROBE); 2646 pci_conf_write(sc->sc_pc, sc->sc_tag, 2647 PDC2xx_TIM(chp->channel, drive), mode); 2648 } 2649 if (idedma_ctl != 0) { 2650 /* Add software bits in status register */ 2651 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2652 IDEDMA_CTL, idedma_ctl); 2653 } 2654 pciide_print_modes(cp); 2655 } 2656 2657 int 2658 pdc202xx_pci_intr(arg) 2659 void *arg; 2660 { 2661 struct pciide_softc *sc = arg; 2662 struct pciide_channel *cp; 2663 struct channel_softc *wdc_cp; 2664 int i, rv, crv; 2665 u_int32_t scr; 2666 2667 rv = 0; 2668 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 2669 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2670 cp = &sc->pciide_channels[i]; 2671 wdc_cp = &cp->wdc_channel; 2672 /* If a compat channel skip. */ 2673 if (cp->compat) 2674 continue; 2675 if (scr & PDC2xx_SCR_INT(i)) { 2676 crv = wdcintr(wdc_cp); 2677 if (crv == 0) 2678 printf("%s:%d: bogus intr\n", 2679 sc->sc_wdcdev.sc_dev.dv_xname, i); 2680 else 2681 rv = 1; 2682 } 2683 } 2684 return rv; 2685 } 2686
Indexes created Thu Oct 02 10:09:58 GMT 2025