pciide.c revision 1.50
1 /* $NetBSD: pciide.c,v 1.50 1999/12/26 21:46:23 soren Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 38 /* 39 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by Christopher G. Demetriou 52 * for the NetBSD Project. 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * PCI IDE controller driver. 70 * 71 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 72 * sys/dev/pci/ppb.c, revision 1.16). 73 * 74 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 75 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 76 * 5/16/94" from the PCI SIG. 77 * 78 */ 79 80 #ifndef WDCDEBUG 81 #define WDCDEBUG 82 #endif 83 84 #define DEBUG_DMA 0x01 85 #define DEBUG_XFERS 0x02 86 #define DEBUG_FUNCS 0x08 87 #define DEBUG_PROBE 0x10 88 #ifdef WDCDEBUG 89 int wdcdebug_pciide_mask = 0; 90 #define WDCDEBUG_PRINT(args, level) \ 91 if (wdcdebug_pciide_mask & (level)) printf args 92 #else 93 #define WDCDEBUG_PRINT(args, level) 94 #endif 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/device.h> 98 #include <sys/malloc.h> 99 100 #include <machine/endian.h> 101 102 #include <vm/vm.h> 103 #include <vm/vm_param.h> 104 #include <vm/vm_kern.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 #include <dev/pci/pcidevs.h> 109 #include <dev/pci/pciidereg.h> 110 #include <dev/pci/pciidevar.h> 111 #include <dev/pci/pciide_piix_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 119 /* inlines for reading/writing 8-bit PCI registers */ 120 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 121 int)); 122 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 123 int, u_int8_t)); 124 125 static __inline u_int8_t 126 pciide_pci_read(pc, pa, reg) 127 pci_chipset_tag_t pc; 128 pcitag_t pa; 129 int reg; 130 { 131 132 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 133 ((reg & 0x03) * 8) & 0xff); 134 } 135 136 static __inline void 137 pciide_pci_write(pc, pa, reg, val) 138 pci_chipset_tag_t pc; 139 pcitag_t pa; 140 int reg; 141 u_int8_t val; 142 { 143 pcireg_t pcival; 144 145 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 146 pcival &= ~(0xff << ((reg & 0x03) * 8)); 147 pcival |= (val << ((reg & 0x03) * 8)); 148 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 149 } 150 151 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 152 153 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 154 void piix_setup_channel __P((struct channel_softc*)); 155 void piix3_4_setup_channel __P((struct channel_softc*)); 156 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 157 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 158 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 159 160 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 void apollo_setup_channel __P((struct channel_softc*)); 162 163 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 164 void cmd0643_6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void cmd0643_6_setup_channel __P((struct channel_softc*)); 166 void cmd_channel_map __P((struct pci_attach_args *, 167 struct pciide_softc *, int)); 168 int cmd_pci_intr __P((void *)); 169 170 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void cy693_setup_channel __P((struct channel_softc*)); 172 173 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void sis_setup_channel __P((struct channel_softc*)); 175 176 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 177 void acer_setup_channel __P((struct channel_softc*)); 178 int acer_pci_intr __P((void *)); 179 180 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void pdc202xx_setup_channel __P((struct channel_softc*)); 182 int pdc202xx_pci_intr __P((void *)); 183 184 void pciide_channel_dma_setup __P((struct pciide_channel *)); 185 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 186 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 187 void pciide_dma_start __P((void*, int, int, int)); 188 int pciide_dma_finish __P((void*, int, int, int)); 189 void pciide_print_modes __P((struct pciide_channel *)); 190 191 struct pciide_product_desc { 192 u_int32_t ide_product; 193 int ide_flags; 194 const char *ide_name; 195 /* map and setup chip, probe drives */ 196 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 197 }; 198 199 /* Flags for ide_flags */ 200 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 201 202 /* Default product description for devices not known from this controller */ 203 const struct pciide_product_desc default_product_desc = { 204 0, 205 0, 206 "Generic PCI IDE controller", 207 default_chip_map, 208 }; 209 210 const struct pciide_product_desc pciide_intel_products[] = { 211 { PCI_PRODUCT_INTEL_82092AA, 212 0, 213 "Intel 82092AA IDE controller", 214 default_chip_map, 215 }, 216 { PCI_PRODUCT_INTEL_82371FB_IDE, 217 0, 218 "Intel 82371FB IDE controller (PIIX)", 219 piix_chip_map, 220 }, 221 { PCI_PRODUCT_INTEL_82371SB_IDE, 222 0, 223 "Intel 82371SB IDE Interface (PIIX3)", 224 piix_chip_map, 225 }, 226 { PCI_PRODUCT_INTEL_82371AB_IDE, 227 0, 228 "Intel 82371AB IDE controller (PIIX4)", 229 piix_chip_map, 230 }, 231 { PCI_PRODUCT_INTEL_82801AA_IDE, 232 0, 233 "Intel 82801AA IDE Controller (ICH)", 234 piix_chip_map, 235 }, 236 { PCI_PRODUCT_INTEL_82801AB_IDE, 237 0, 238 "Intel 82801AB IDE Controller (ICH0)", 239 piix_chip_map, 240 }, 241 { 0, 242 0, 243 NULL, 244 } 245 }; 246 247 const struct pciide_product_desc pciide_cmd_products[] = { 248 { PCI_PRODUCT_CMDTECH_640, 249 0, 250 "CMD Technology PCI0640", 251 cmd_chip_map 252 }, 253 { PCI_PRODUCT_CMDTECH_643, 254 0, 255 "CMD Technology PCI0643", 256 cmd0643_6_chip_map, 257 }, 258 { PCI_PRODUCT_CMDTECH_646, 259 0, 260 "CMD Technology PCI0646", 261 cmd0643_6_chip_map, 262 }, 263 { 0, 264 0, 265 NULL, 266 } 267 }; 268 269 const struct pciide_product_desc pciide_via_products[] = { 270 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 271 0, 272 "VIA Technologies VT82C586 (Apollo VP) IDE Controller", 273 apollo_chip_map, 274 }, 275 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 276 0, 277 "VIA Technologies VT82C586A IDE Controller", 278 apollo_chip_map, 279 }, 280 { 0, 281 0, 282 NULL, 283 } 284 }; 285 286 const struct pciide_product_desc pciide_cypress_products[] = { 287 { PCI_PRODUCT_CONTAQ_82C693, 288 0, 289 "Contaq Microsystems CY82C693 IDE Controller", 290 cy693_chip_map, 291 }, 292 { 0, 293 0, 294 NULL, 295 } 296 }; 297 298 const struct pciide_product_desc pciide_sis_products[] = { 299 { PCI_PRODUCT_SIS_5597_IDE, 300 0, 301 "Silicon Integrated System 5597/5598 IDE controller", 302 sis_chip_map, 303 }, 304 { 0, 305 0, 306 NULL, 307 } 308 }; 309 310 const struct pciide_product_desc pciide_acer_products[] = { 311 { PCI_PRODUCT_ALI_M5229, 312 0, 313 "Acer Labs M5229 UDMA IDE Controller", 314 acer_chip_map, 315 }, 316 { 0, 317 0, 318 NULL, 319 } 320 }; 321 322 const struct pciide_product_desc pciide_promise_products[] = { 323 { PCI_PRODUCT_PROMISE_ULTRA33, 324 IDE_PCI_CLASS_OVERRIDE, 325 "Promise Ultra33/ATA Bus Master IDE Accelerator", 326 pdc202xx_chip_map, 327 }, 328 { PCI_PRODUCT_PROMISE_ULTRA66, 329 IDE_PCI_CLASS_OVERRIDE, 330 "Promise Ultra66/ATA Bus Master IDE Accelerator", 331 pdc202xx_chip_map, 332 }, 333 { 0, 334 0, 335 NULL, 336 } 337 }; 338 339 struct pciide_vendor_desc { 340 u_int32_t ide_vendor; 341 const struct pciide_product_desc *ide_products; 342 }; 343 344 const struct pciide_vendor_desc pciide_vendors[] = { 345 { PCI_VENDOR_INTEL, pciide_intel_products }, 346 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 347 { PCI_VENDOR_VIATECH, pciide_via_products }, 348 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 349 { PCI_VENDOR_SIS, pciide_sis_products }, 350 { PCI_VENDOR_ALI, pciide_acer_products }, 351 { PCI_VENDOR_PROMISE, pciide_promise_products }, 352 { 0, NULL } 353 }; 354 355 #define PCIIDE_CHANNEL_NAME(chan) ((chan) == 0 ? "primary" : "secondary") 356 357 /* options passed via the 'flags' config keyword */ 358 #define PCIIDE_OPTIONS_DMA 0x01 359 360 int pciide_match __P((struct device *, struct cfdata *, void *)); 361 void pciide_attach __P((struct device *, struct device *, void *)); 362 363 struct cfattach pciide_ca = { 364 sizeof(struct pciide_softc), pciide_match, pciide_attach 365 }; 366 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 367 int pciide_mapregs_compat __P(( struct pci_attach_args *, 368 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 369 int pciide_mapregs_native __P((struct pci_attach_args *, 370 struct pciide_channel *, bus_size_t *, bus_size_t *, 371 int (*pci_intr) __P((void *)))); 372 void pciide_mapreg_dma __P((struct pciide_softc *, 373 struct pci_attach_args *)); 374 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 375 void pciide_mapchan __P((struct pci_attach_args *, 376 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 377 int (*pci_intr) __P((void *)))); 378 int pciiide_chan_candisable __P((struct pciide_channel *)); 379 void pciide_map_compat_intr __P(( struct pci_attach_args *, 380 struct pciide_channel *, int, int)); 381 int pciide_print __P((void *, const char *pnp)); 382 int pciide_compat_intr __P((void *)); 383 int pciide_pci_intr __P((void *)); 384 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 385 386 const struct pciide_product_desc * 387 pciide_lookup_product(id) 388 u_int32_t id; 389 { 390 const struct pciide_product_desc *pp; 391 const struct pciide_vendor_desc *vp; 392 393 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 394 if (PCI_VENDOR(id) == vp->ide_vendor) 395 break; 396 397 if ((pp = vp->ide_products) == NULL) 398 return NULL; 399 400 for (; pp->ide_name != NULL; pp++) 401 if (PCI_PRODUCT(id) == pp->ide_product) 402 break; 403 404 if (pp->ide_name == NULL) 405 return NULL; 406 return pp; 407 } 408 409 int 410 pciide_match(parent, match, aux) 411 struct device *parent; 412 struct cfdata *match; 413 void *aux; 414 { 415 struct pci_attach_args *pa = aux; 416 const struct pciide_product_desc *pp; 417 418 /* 419 * Check the ID register to see that it's a PCI IDE controller. 420 * If it is, we assume that we can deal with it; it _should_ 421 * work in a standardized way... 422 */ 423 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 424 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 425 return (1); 426 } 427 428 /* 429 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 430 * controllers. Let see if we can deal with it anyway. 431 */ 432 pp = pciide_lookup_product(pa->pa_id); 433 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 434 return (1); 435 } 436 437 return (0); 438 } 439 440 void 441 pciide_attach(parent, self, aux) 442 struct device *parent, *self; 443 void *aux; 444 { 445 struct pci_attach_args *pa = aux; 446 pci_chipset_tag_t pc = pa->pa_pc; 447 pcitag_t tag = pa->pa_tag; 448 struct pciide_softc *sc = (struct pciide_softc *)self; 449 pcireg_t csr; 450 char devinfo[256]; 451 452 sc->sc_pp = pciide_lookup_product(pa->pa_id); 453 if (sc->sc_pp == NULL) { 454 sc->sc_pp = &default_product_desc; 455 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 456 printf(": %s (rev. 0x%02x)\n", devinfo, 457 PCI_REVISION(pa->pa_class)); 458 } else { 459 printf(": %s\n", sc->sc_pp->ide_name); 460 } 461 sc->sc_pc = pa->pa_pc; 462 sc->sc_tag = pa->pa_tag; 463 #ifdef WDCDEBUG 464 if (wdcdebug_pciide_mask & DEBUG_PROBE) 465 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 466 #endif 467 468 sc->sc_pp->chip_map(sc, pa); 469 470 if (sc->sc_dma_ok) { 471 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 472 csr |= PCI_COMMAND_MASTER_ENABLE; 473 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 474 } 475 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 476 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 477 } 478 479 /* tell wether the chip is enabled or not */ 480 int 481 pciide_chipen(sc, pa) 482 struct pciide_softc *sc; 483 struct pci_attach_args *pa; 484 { 485 pcireg_t csr; 486 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 487 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 488 PCI_COMMAND_STATUS_REG); 489 printf("%s: device disabled (at %s)\n", 490 sc->sc_wdcdev.sc_dev.dv_xname, 491 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 492 "device" : "bridge"); 493 return 0; 494 } 495 return 1; 496 } 497 498 int 499 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 500 struct pci_attach_args *pa; 501 struct pciide_channel *cp; 502 int compatchan; 503 bus_size_t *cmdsizep, *ctlsizep; 504 { 505 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 506 struct channel_softc *wdc_cp = &cp->wdc_channel; 507 508 cp->compat = 1; 509 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 510 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 511 512 wdc_cp->cmd_iot = pa->pa_iot; 513 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 514 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 515 printf("%s: couldn't map %s channel cmd regs\n", 516 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 517 return (0); 518 } 519 520 wdc_cp->ctl_iot = pa->pa_iot; 521 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 522 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 523 printf("%s: couldn't map %s channel ctl regs\n", 524 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 525 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 526 PCIIDE_COMPAT_CMD_SIZE); 527 return (0); 528 } 529 530 return (1); 531 } 532 533 int 534 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 535 struct pci_attach_args * pa; 536 struct pciide_channel *cp; 537 bus_size_t *cmdsizep, *ctlsizep; 538 int (*pci_intr) __P((void *)); 539 { 540 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 541 struct channel_softc *wdc_cp = &cp->wdc_channel; 542 const char *intrstr; 543 pci_intr_handle_t intrhandle; 544 545 cp->compat = 0; 546 547 if (sc->sc_pci_ih == NULL) { 548 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 549 pa->pa_intrline, &intrhandle) != 0) { 550 printf("%s: couldn't map native-PCI interrupt\n", 551 sc->sc_wdcdev.sc_dev.dv_xname); 552 return 0; 553 } 554 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 555 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 556 intrhandle, IPL_BIO, pci_intr, sc); 557 if (sc->sc_pci_ih != NULL) { 558 printf("%s: using %s for native-PCI interrupt\n", 559 sc->sc_wdcdev.sc_dev.dv_xname, 560 intrstr ? intrstr : "unknown interrupt"); 561 } else { 562 printf("%s: couldn't establish native-PCI interrupt", 563 sc->sc_wdcdev.sc_dev.dv_xname); 564 if (intrstr != NULL) 565 printf(" at %s", intrstr); 566 printf("\n"); 567 return 0; 568 } 569 } 570 cp->ih = sc->sc_pci_ih; 571 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 572 PCI_MAPREG_TYPE_IO, 0, 573 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 574 printf("%s: couldn't map %s channel cmd regs\n", 575 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 576 return 0; 577 } 578 579 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 580 PCI_MAPREG_TYPE_IO, 0, 581 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 582 printf("%s: couldn't map %s channel ctl regs\n", 583 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 584 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 585 return 0; 586 } 587 return (1); 588 } 589 590 void 591 pciide_mapreg_dma(sc, pa) 592 struct pciide_softc *sc; 593 struct pci_attach_args *pa; 594 { 595 /* 596 * Map DMA registers 597 * 598 * Note that sc_dma_ok is the right variable to test to see if 599 * DMA can be done. If the interface doesn't support DMA, 600 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 601 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 602 * non-zero if the interface supports DMA and the registers 603 * could be mapped. 604 * 605 * XXX Note that despite the fact that the Bus Master IDE specs 606 * XXX say that "The bus master IDE function uses 16 bytes of IO 607 * XXX space," some controllers (at least the United 608 * XXX Microelectronics UM8886BF) place it in memory space. 609 * XXX eventually, we should probably read the register and check 610 * XXX which type it is. Either that or 'quirk' certain devices. 611 */ 612 sc->sc_dma_ok = (pci_mapreg_map(pa, 613 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0, 614 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 615 sc->sc_dmat = pa->pa_dmat; 616 if (sc->sc_dma_ok == 0) { 617 printf(", but unused (couldn't map registers)"); 618 } else { 619 sc->sc_wdcdev.dma_arg = sc; 620 sc->sc_wdcdev.dma_init = pciide_dma_init; 621 sc->sc_wdcdev.dma_start = pciide_dma_start; 622 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 623 } 624 } 625 int 626 pciide_compat_intr(arg) 627 void *arg; 628 { 629 struct pciide_channel *cp = arg; 630 631 #ifdef DIAGNOSTIC 632 /* should only be called for a compat channel */ 633 if (cp->compat == 0) 634 panic("pciide compat intr called for non-compat chan %p\n", cp); 635 #endif 636 return (wdcintr(&cp->wdc_channel)); 637 } 638 639 int 640 pciide_pci_intr(arg) 641 void *arg; 642 { 643 struct pciide_softc *sc = arg; 644 struct pciide_channel *cp; 645 struct channel_softc *wdc_cp; 646 int i, rv, crv; 647 648 rv = 0; 649 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 650 cp = &sc->pciide_channels[i]; 651 wdc_cp = &cp->wdc_channel; 652 653 /* If a compat channel skip. */ 654 if (cp->compat) 655 continue; 656 /* if this channel not waiting for intr, skip */ 657 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 658 continue; 659 660 crv = wdcintr(wdc_cp); 661 if (crv == 0) 662 ; /* leave rv alone */ 663 else if (crv == 1) 664 rv = 1; /* claim the intr */ 665 else if (rv == 0) /* crv should be -1 in this case */ 666 rv = crv; /* if we've done no better, take it */ 667 } 668 return (rv); 669 } 670 671 void 672 pciide_channel_dma_setup(cp) 673 struct pciide_channel *cp; 674 { 675 int drive; 676 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 677 struct ata_drive_datas *drvp; 678 679 for (drive = 0; drive < 2; drive++) { 680 drvp = &cp->wdc_channel.ch_drive[drive]; 681 /* If no drive, skip */ 682 if ((drvp->drive_flags & DRIVE) == 0) 683 continue; 684 /* setup DMA if needed */ 685 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 686 (drvp->drive_flags & DRIVE_UDMA) == 0) || 687 sc->sc_dma_ok == 0) { 688 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 689 continue; 690 } 691 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 692 != 0) { 693 /* Abort DMA setup */ 694 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 695 continue; 696 } 697 } 698 } 699 700 int 701 pciide_dma_table_setup(sc, channel, drive) 702 struct pciide_softc *sc; 703 int channel, drive; 704 { 705 bus_dma_segment_t seg; 706 int error, rseg; 707 const bus_size_t dma_table_size = 708 sizeof(struct idedma_table) * NIDEDMA_TABLES; 709 struct pciide_dma_maps *dma_maps = 710 &sc->pciide_channels[channel].dma_maps[drive]; 711 712 /* If table was already allocated, just return */ 713 if (dma_maps->dma_table) 714 return 0; 715 716 /* Allocate memory for the DMA tables and map it */ 717 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 718 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 719 BUS_DMA_NOWAIT)) != 0) { 720 printf("%s:%d: unable to allocate table DMA for " 721 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 722 channel, drive, error); 723 return error; 724 } 725 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 726 dma_table_size, 727 (caddr_t *)&dma_maps->dma_table, 728 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 729 printf("%s:%d: unable to map table DMA for" 730 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 731 channel, drive, error); 732 return error; 733 } 734 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 735 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 736 seg.ds_addr), DEBUG_PROBE); 737 738 /* Create and load table DMA map for this disk */ 739 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 740 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 741 &dma_maps->dmamap_table)) != 0) { 742 printf("%s:%d: unable to create table DMA map for " 743 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 744 channel, drive, error); 745 return error; 746 } 747 if ((error = bus_dmamap_load(sc->sc_dmat, 748 dma_maps->dmamap_table, 749 dma_maps->dma_table, 750 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 751 printf("%s:%d: unable to load table DMA map for " 752 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 753 channel, drive, error); 754 return error; 755 } 756 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 757 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 758 /* Create a xfer DMA map for this drive */ 759 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 760 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 761 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 762 &dma_maps->dmamap_xfer)) != 0) { 763 printf("%s:%d: unable to create xfer DMA map for " 764 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 765 channel, drive, error); 766 return error; 767 } 768 return 0; 769 } 770 771 int 772 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 773 void *v; 774 int channel, drive; 775 void *databuf; 776 size_t datalen; 777 int flags; 778 { 779 struct pciide_softc *sc = v; 780 int error, seg; 781 struct pciide_dma_maps *dma_maps = 782 &sc->pciide_channels[channel].dma_maps[drive]; 783 784 error = bus_dmamap_load(sc->sc_dmat, 785 dma_maps->dmamap_xfer, 786 databuf, datalen, NULL, BUS_DMA_NOWAIT); 787 if (error) { 788 printf("%s:%d: unable to load xfer DMA map for" 789 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 790 channel, drive, error); 791 return error; 792 } 793 794 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 795 dma_maps->dmamap_xfer->dm_mapsize, 796 (flags & WDC_DMA_READ) ? 797 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 798 799 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 800 #ifdef DIAGNOSTIC 801 /* A segment must not cross a 64k boundary */ 802 { 803 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 804 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 805 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 806 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 807 printf("pciide_dma: segment %d physical addr 0x%lx" 808 " len 0x%lx not properly aligned\n", 809 seg, phys, len); 810 panic("pciide_dma: buf align"); 811 } 812 } 813 #endif 814 dma_maps->dma_table[seg].base_addr = 815 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 816 dma_maps->dma_table[seg].byte_count = 817 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 818 IDEDMA_BYTE_COUNT_MASK); 819 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 820 seg, le32toh(dma_maps->dma_table[seg].byte_count), 821 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 822 823 } 824 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 825 htole32(IDEDMA_BYTE_COUNT_EOT); 826 827 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 828 dma_maps->dmamap_table->dm_mapsize, 829 BUS_DMASYNC_PREWRITE); 830 831 /* Maps are ready. Start DMA function */ 832 #ifdef DIAGNOSTIC 833 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 834 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 835 dma_maps->dmamap_table->dm_segs[0].ds_addr); 836 panic("pciide_dma_init: table align"); 837 } 838 #endif 839 840 /* Clear status bits */ 841 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 842 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 843 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 844 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 845 /* Write table addr */ 846 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 847 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 848 dma_maps->dmamap_table->dm_segs[0].ds_addr); 849 /* set read/write */ 850 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 851 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 852 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 853 return 0; 854 } 855 856 void 857 pciide_dma_start(v, channel, drive, flags) 858 void *v; 859 int channel, drive, flags; 860 { 861 struct pciide_softc *sc = v; 862 863 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 864 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 865 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 866 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 867 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 868 } 869 870 int 871 pciide_dma_finish(v, channel, drive, flags) 872 void *v; 873 int channel, drive; 874 int flags; 875 { 876 struct pciide_softc *sc = v; 877 u_int8_t status; 878 struct pciide_dma_maps *dma_maps = 879 &sc->pciide_channels[channel].dma_maps[drive]; 880 881 /* Unload the map of the data buffer */ 882 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 883 dma_maps->dmamap_xfer->dm_mapsize, 884 (flags & WDC_DMA_READ) ? 885 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 886 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 887 888 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 889 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 890 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 891 DEBUG_XFERS); 892 893 /* stop DMA channel */ 894 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 895 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 896 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 897 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 898 899 /* Clear status bits */ 900 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 901 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 902 status); 903 904 if ((status & IDEDMA_CTL_ERR) != 0) { 905 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 906 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 907 return -1; 908 } 909 910 if ((flags & WDC_DMA_POLL) == 0 && (status & IDEDMA_CTL_INTR) == 0) { 911 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 912 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 913 drive, status); 914 return -1; 915 } 916 917 if ((status & IDEDMA_CTL_ACT) != 0) { 918 /* data underrun, may be a valid condition for ATAPI */ 919 return 1; 920 } 921 return 0; 922 } 923 924 /* some common code used by several chip_map */ 925 int 926 pciide_chansetup(sc, channel, interface) 927 struct pciide_softc *sc; 928 int channel; 929 pcireg_t interface; 930 { 931 struct pciide_channel *cp = &sc->pciide_channels[channel]; 932 sc->wdc_chanarray[channel] = &cp->wdc_channel; 933 cp->name = PCIIDE_CHANNEL_NAME(channel); 934 cp->wdc_channel.channel = channel; 935 cp->wdc_channel.wdc = &sc->sc_wdcdev; 936 cp->wdc_channel.ch_queue = 937 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 938 if (cp->wdc_channel.ch_queue == NULL) { 939 printf("%s %s channel: " 940 "can't allocate memory for command queue", 941 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 942 return 0; 943 } 944 printf("%s: %s channel %s to %s mode\n", 945 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 946 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 947 "configured" : "wired", 948 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 949 "native-PCI" : "compatibility"); 950 return 1; 951 } 952 953 /* some common code used by several chip channel_map */ 954 void 955 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 956 struct pci_attach_args *pa; 957 struct pciide_channel *cp; 958 pcireg_t interface; 959 bus_size_t *cmdsizep, *ctlsizep; 960 int (*pci_intr) __P((void *)); 961 { 962 struct channel_softc *wdc_cp = &cp->wdc_channel; 963 964 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 965 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 966 pci_intr); 967 else 968 cp->hw_ok = pciide_mapregs_compat(pa, cp, 969 wdc_cp->channel, cmdsizep, ctlsizep); 970 971 if (cp->hw_ok == 0) 972 return; 973 wdc_cp->data32iot = wdc_cp->cmd_iot; 974 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 975 wdcattach(wdc_cp); 976 } 977 978 /* 979 * Generic code to call to know if a channel can be disabled. Return 1 980 * if channel can be disabled, 0 if not 981 */ 982 int 983 pciiide_chan_candisable(cp) 984 struct pciide_channel *cp; 985 { 986 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 987 struct channel_softc *wdc_cp = &cp->wdc_channel; 988 989 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 990 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 991 printf("%s: disabling %s channel (no drives)\n", 992 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 993 cp->hw_ok = 0; 994 return 1; 995 } 996 return 0; 997 } 998 999 /* 1000 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1001 * Set hw_ok=0 on failure 1002 */ 1003 void 1004 pciide_map_compat_intr(pa, cp, compatchan, interface) 1005 struct pci_attach_args *pa; 1006 struct pciide_channel *cp; 1007 int compatchan, interface; 1008 { 1009 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1010 struct channel_softc *wdc_cp = &cp->wdc_channel; 1011 1012 if (cp->hw_ok == 0) 1013 return; 1014 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1015 return; 1016 1017 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1018 pa, compatchan, pciide_compat_intr, cp); 1019 if (cp->ih == NULL) { 1020 printf("%s: no compatibility interrupt for use by %s " 1021 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1022 cp->hw_ok = 0; 1023 } 1024 } 1025 1026 void 1027 pciide_print_modes(cp) 1028 struct pciide_channel *cp; 1029 { 1030 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1031 int drive; 1032 struct channel_softc *chp; 1033 struct ata_drive_datas *drvp; 1034 1035 chp = &cp->wdc_channel; 1036 for (drive = 0; drive < 2; drive++) { 1037 drvp = &chp->ch_drive[drive]; 1038 if ((drvp->drive_flags & DRIVE) == 0) 1039 continue; 1040 printf("%s(%s:%d:%d): using PIO mode %d", 1041 drvp->drv_softc->dv_xname, 1042 sc->sc_wdcdev.sc_dev.dv_xname, 1043 chp->channel, drive, drvp->PIO_mode); 1044 if (drvp->drive_flags & DRIVE_DMA) 1045 printf(", DMA mode %d", drvp->DMA_mode); 1046 if (drvp->drive_flags & DRIVE_UDMA) 1047 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1048 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1049 printf(" (using DMA data transfers)"); 1050 printf("\n"); 1051 } 1052 } 1053 1054 void 1055 default_chip_map(sc, pa) 1056 struct pciide_softc *sc; 1057 struct pci_attach_args *pa; 1058 { 1059 struct pciide_channel *cp; 1060 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1061 sc->sc_tag, PCI_CLASS_REG)); 1062 pcireg_t csr; 1063 int channel, drive; 1064 struct ata_drive_datas *drvp; 1065 u_int8_t idedma_ctl; 1066 bus_size_t cmdsize, ctlsize; 1067 char *failreason; 1068 1069 if (pciide_chipen(sc, pa) == 0) 1070 return; 1071 1072 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1073 printf("%s: bus-master DMA support present", 1074 sc->sc_wdcdev.sc_dev.dv_xname); 1075 if (sc->sc_pp == &default_product_desc && 1076 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1077 PCIIDE_OPTIONS_DMA) == 0) { 1078 printf(", but unused (no driver support)"); 1079 sc->sc_dma_ok = 0; 1080 } else { 1081 pciide_mapreg_dma(sc, pa); 1082 if (sc->sc_dma_ok != 0) 1083 printf(", used without full driver " 1084 "support"); 1085 } 1086 } else { 1087 printf("%s: hardware does not support DMA", 1088 sc->sc_wdcdev.sc_dev.dv_xname); 1089 sc->sc_dma_ok = 0; 1090 } 1091 printf("\n"); 1092 if (sc->sc_dma_ok) 1093 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1094 sc->sc_wdcdev.PIO_cap = 0; 1095 sc->sc_wdcdev.DMA_cap = 0; 1096 1097 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1098 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1099 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1100 1101 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1102 cp = &sc->pciide_channels[channel]; 1103 if (pciide_chansetup(sc, channel, interface) == 0) 1104 continue; 1105 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1106 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1107 &ctlsize, pciide_pci_intr); 1108 } else { 1109 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1110 channel, &cmdsize, &ctlsize); 1111 } 1112 if (cp->hw_ok == 0) 1113 continue; 1114 /* 1115 * Check to see if something appears to be there. 1116 */ 1117 failreason = NULL; 1118 if (!wdcprobe(&cp->wdc_channel)) { 1119 failreason = "not responding; disabled or no drives?"; 1120 goto next; 1121 } 1122 /* 1123 * Now, make sure it's actually attributable to this PCI IDE 1124 * channel by trying to access the channel again while the 1125 * PCI IDE controller's I/O space is disabled. (If the 1126 * channel no longer appears to be there, it belongs to 1127 * this controller.) YUCK! 1128 */ 1129 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1130 PCI_COMMAND_STATUS_REG); 1131 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1132 csr & ~PCI_COMMAND_IO_ENABLE); 1133 if (wdcprobe(&cp->wdc_channel)) 1134 failreason = "other hardware responding at addresses"; 1135 pci_conf_write(sc->sc_pc, sc->sc_tag, 1136 PCI_COMMAND_STATUS_REG, csr); 1137 next: 1138 if (failreason) { 1139 printf("%s: %s channel ignored (%s)\n", 1140 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1141 failreason); 1142 cp->hw_ok = 0; 1143 bus_space_unmap(cp->wdc_channel.cmd_iot, 1144 cp->wdc_channel.cmd_ioh, cmdsize); 1145 bus_space_unmap(cp->wdc_channel.ctl_iot, 1146 cp->wdc_channel.ctl_ioh, ctlsize); 1147 } else { 1148 pciide_map_compat_intr(pa, cp, channel, interface); 1149 } 1150 if (cp->hw_ok) { 1151 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1152 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1153 wdcattach(&cp->wdc_channel); 1154 } 1155 } 1156 1157 if (sc->sc_dma_ok == 0) 1158 return; 1159 1160 /* Allocate DMA maps */ 1161 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1162 idedma_ctl = 0; 1163 cp = &sc->pciide_channels[channel]; 1164 for (drive = 0; drive < 2; drive++) { 1165 drvp = &cp->wdc_channel.ch_drive[drive]; 1166 /* If no drive, skip */ 1167 if ((drvp->drive_flags & DRIVE) == 0) 1168 continue; 1169 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1170 continue; 1171 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1172 /* Abort DMA setup */ 1173 printf("%s:%d:%d: can't allocate DMA maps, " 1174 "using PIO transfers\n", 1175 sc->sc_wdcdev.sc_dev.dv_xname, 1176 channel, drive); 1177 drvp->drive_flags &= ~DRIVE_DMA; 1178 } 1179 printf("%s:%d:%d: using DMA data transfers\n", 1180 sc->sc_wdcdev.sc_dev.dv_xname, 1181 channel, drive); 1182 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1183 } 1184 if (idedma_ctl != 0) { 1185 /* Add software bits in status register */ 1186 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1187 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1188 idedma_ctl); 1189 } 1190 } 1191 } 1192 1193 void 1194 piix_chip_map(sc, pa) 1195 struct pciide_softc *sc; 1196 struct pci_attach_args *pa; 1197 { 1198 struct pciide_channel *cp; 1199 int channel; 1200 u_int32_t idetim; 1201 bus_size_t cmdsize, ctlsize; 1202 1203 if (pciide_chipen(sc, pa) == 0) 1204 return; 1205 1206 printf("%s: bus-master DMA support present", 1207 sc->sc_wdcdev.sc_dev.dv_xname); 1208 pciide_mapreg_dma(sc, pa); 1209 printf("\n"); 1210 if (sc->sc_dma_ok) { 1211 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1212 switch(sc->sc_pp->ide_product) { 1213 case PCI_PRODUCT_INTEL_82371AB_IDE: 1214 case PCI_PRODUCT_INTEL_82801AA_IDE: 1215 case PCI_PRODUCT_INTEL_82801AB_IDE: 1216 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1217 } 1218 } 1219 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1220 WDC_CAPABILITY_MODE; 1221 sc->sc_wdcdev.PIO_cap = 4; 1222 sc->sc_wdcdev.DMA_cap = 2; 1223 sc->sc_wdcdev.UDMA_cap = 1224 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1225 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1226 sc->sc_wdcdev.set_modes = piix_setup_channel; 1227 else 1228 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1229 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1230 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1231 1232 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1233 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1234 DEBUG_PROBE); 1235 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1236 WDCDEBUG_PRINT((", sidetim=0x%x", 1237 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1238 DEBUG_PROBE); 1239 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1240 WDCDEBUG_PRINT((", udamreg 0x%x", 1241 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1242 DEBUG_PROBE); 1243 } 1244 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1245 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1246 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1247 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1248 DEBUG_PROBE); 1249 } 1250 1251 } 1252 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1253 1254 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1255 cp = &sc->pciide_channels[channel]; 1256 /* PIIX is compat-only */ 1257 if (pciide_chansetup(sc, channel, 0) == 0) 1258 continue; 1259 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1260 if ((PIIX_IDETIM_READ(idetim, channel) & 1261 PIIX_IDETIM_IDE) == 0) { 1262 printf("%s: %s channel ignored (disabled)\n", 1263 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1264 continue; 1265 } 1266 /* PIIX are compat-only pciide devices */ 1267 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1268 if (cp->hw_ok == 0) 1269 continue; 1270 if (pciiide_chan_candisable(cp)) { 1271 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1272 channel); 1273 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1274 idetim); 1275 } 1276 pciide_map_compat_intr(pa, cp, channel, 0); 1277 if (cp->hw_ok == 0) 1278 continue; 1279 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1280 } 1281 1282 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1283 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1284 DEBUG_PROBE); 1285 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1286 WDCDEBUG_PRINT((", sidetim=0x%x", 1287 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1288 DEBUG_PROBE); 1289 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1290 WDCDEBUG_PRINT((", udamreg 0x%x", 1291 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1292 DEBUG_PROBE); 1293 } 1294 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1295 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1296 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1297 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1298 DEBUG_PROBE); 1299 } 1300 } 1301 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1302 } 1303 1304 void 1305 piix_setup_channel(chp) 1306 struct channel_softc *chp; 1307 { 1308 u_int8_t mode[2], drive; 1309 u_int32_t oidetim, idetim, idedma_ctl; 1310 struct pciide_channel *cp = (struct pciide_channel*)chp; 1311 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1312 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1313 1314 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1315 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1316 idedma_ctl = 0; 1317 1318 /* set up new idetim: Enable IDE registers decode */ 1319 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1320 chp->channel); 1321 1322 /* setup DMA */ 1323 pciide_channel_dma_setup(cp); 1324 1325 /* 1326 * Here we have to mess up with drives mode: PIIX can't have 1327 * different timings for master and slave drives. 1328 * We need to find the best combination. 1329 */ 1330 1331 /* If both drives supports DMA, take the lower mode */ 1332 if ((drvp[0].drive_flags & DRIVE_DMA) && 1333 (drvp[1].drive_flags & DRIVE_DMA)) { 1334 mode[0] = mode[1] = 1335 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1336 drvp[0].DMA_mode = mode[0]; 1337 drvp[1].DMA_mode = mode[1]; 1338 goto ok; 1339 } 1340 /* 1341 * If only one drive supports DMA, use its mode, and 1342 * put the other one in PIO mode 0 if mode not compatible 1343 */ 1344 if (drvp[0].drive_flags & DRIVE_DMA) { 1345 mode[0] = drvp[0].DMA_mode; 1346 mode[1] = drvp[1].PIO_mode; 1347 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1348 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1349 mode[1] = drvp[1].PIO_mode = 0; 1350 goto ok; 1351 } 1352 if (drvp[1].drive_flags & DRIVE_DMA) { 1353 mode[1] = drvp[1].DMA_mode; 1354 mode[0] = drvp[0].PIO_mode; 1355 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1356 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1357 mode[0] = drvp[0].PIO_mode = 0; 1358 goto ok; 1359 } 1360 /* 1361 * If both drives are not DMA, takes the lower mode, unless 1362 * one of them is PIO mode < 2 1363 */ 1364 if (drvp[0].PIO_mode < 2) { 1365 mode[0] = drvp[0].PIO_mode = 0; 1366 mode[1] = drvp[1].PIO_mode; 1367 } else if (drvp[1].PIO_mode < 2) { 1368 mode[1] = drvp[1].PIO_mode = 0; 1369 mode[0] = drvp[0].PIO_mode; 1370 } else { 1371 mode[0] = mode[1] = 1372 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1373 drvp[0].PIO_mode = mode[0]; 1374 drvp[1].PIO_mode = mode[1]; 1375 } 1376 ok: /* The modes are setup */ 1377 for (drive = 0; drive < 2; drive++) { 1378 if (drvp[drive].drive_flags & DRIVE_DMA) { 1379 idetim |= piix_setup_idetim_timings( 1380 mode[drive], 1, chp->channel); 1381 goto end; 1382 } 1383 } 1384 /* If we are there, none of the drives are DMA */ 1385 if (mode[0] >= 2) 1386 idetim |= piix_setup_idetim_timings( 1387 mode[0], 0, chp->channel); 1388 else 1389 idetim |= piix_setup_idetim_timings( 1390 mode[1], 0, chp->channel); 1391 end: /* 1392 * timing mode is now set up in the controller. Enable 1393 * it per-drive 1394 */ 1395 for (drive = 0; drive < 2; drive++) { 1396 /* If no drive, skip */ 1397 if ((drvp[drive].drive_flags & DRIVE) == 0) 1398 continue; 1399 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1400 if (drvp[drive].drive_flags & DRIVE_DMA) 1401 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1402 } 1403 if (idedma_ctl != 0) { 1404 /* Add software bits in status register */ 1405 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1406 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1407 idedma_ctl); 1408 } 1409 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1410 pciide_print_modes(cp); 1411 } 1412 1413 void 1414 piix3_4_setup_channel(chp) 1415 struct channel_softc *chp; 1416 { 1417 struct ata_drive_datas *drvp; 1418 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1419 struct pciide_channel *cp = (struct pciide_channel*)chp; 1420 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1421 int drive; 1422 int channel = chp->channel; 1423 1424 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1425 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1426 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1427 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1428 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1429 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1430 PIIX_SIDETIM_RTC_MASK(channel)); 1431 1432 idedma_ctl = 0; 1433 /* If channel disabled, no need to go further */ 1434 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1435 return; 1436 /* set up new idetim: Enable IDE registers decode */ 1437 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1438 1439 /* setup DMA if needed */ 1440 pciide_channel_dma_setup(cp); 1441 1442 for (drive = 0; drive < 2; drive++) { 1443 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1444 PIIX_UDMATIM_SET(0x3, channel, drive)); 1445 drvp = &chp->ch_drive[drive]; 1446 /* If no drive, skip */ 1447 if ((drvp->drive_flags & DRIVE) == 0) 1448 continue; 1449 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1450 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1451 goto pio; 1452 1453 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1454 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1455 ideconf |= PIIX_CONFIG_PINGPONG; 1456 } 1457 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1458 /* setup Ultra/66 */ 1459 if (drvp->UDMA_mode > 2 && 1460 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1461 drvp->UDMA_mode = 2; 1462 if (drvp->UDMA_mode > 2) 1463 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1464 else 1465 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1466 } 1467 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1468 (drvp->drive_flags & DRIVE_UDMA)) { 1469 /* use Ultra/DMA */ 1470 drvp->drive_flags &= ~DRIVE_DMA; 1471 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1472 udmareg |= PIIX_UDMATIM_SET( 1473 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1474 } else { 1475 /* use Multiword DMA */ 1476 drvp->drive_flags &= ~DRIVE_UDMA; 1477 if (drive == 0) { 1478 idetim |= piix_setup_idetim_timings( 1479 drvp->DMA_mode, 1, channel); 1480 } else { 1481 sidetim |= piix_setup_sidetim_timings( 1482 drvp->DMA_mode, 1, channel); 1483 idetim =PIIX_IDETIM_SET(idetim, 1484 PIIX_IDETIM_SITRE, channel); 1485 } 1486 } 1487 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1488 1489 pio: /* use PIO mode */ 1490 idetim |= piix_setup_idetim_drvs(drvp); 1491 if (drive == 0) { 1492 idetim |= piix_setup_idetim_timings( 1493 drvp->PIO_mode, 0, channel); 1494 } else { 1495 sidetim |= piix_setup_sidetim_timings( 1496 drvp->PIO_mode, 0, channel); 1497 idetim =PIIX_IDETIM_SET(idetim, 1498 PIIX_IDETIM_SITRE, channel); 1499 } 1500 } 1501 if (idedma_ctl != 0) { 1502 /* Add software bits in status register */ 1503 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1504 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1505 idedma_ctl); 1506 } 1507 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1508 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1509 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1510 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1511 pciide_print_modes(cp); 1512 } 1513 1514 1515 /* setup ISP and RTC fields, based on mode */ 1516 static u_int32_t 1517 piix_setup_idetim_timings(mode, dma, channel) 1518 u_int8_t mode; 1519 u_int8_t dma; 1520 u_int8_t channel; 1521 { 1522 1523 if (dma) 1524 return PIIX_IDETIM_SET(0, 1525 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1526 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1527 channel); 1528 else 1529 return PIIX_IDETIM_SET(0, 1530 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1531 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1532 channel); 1533 } 1534 1535 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1536 static u_int32_t 1537 piix_setup_idetim_drvs(drvp) 1538 struct ata_drive_datas *drvp; 1539 { 1540 u_int32_t ret = 0; 1541 struct channel_softc *chp = drvp->chnl_softc; 1542 u_int8_t channel = chp->channel; 1543 u_int8_t drive = drvp->drive; 1544 1545 /* 1546 * If drive is using UDMA, timings setups are independant 1547 * So just check DMA and PIO here. 1548 */ 1549 if (drvp->drive_flags & DRIVE_DMA) { 1550 /* if mode = DMA mode 0, use compatible timings */ 1551 if ((drvp->drive_flags & DRIVE_DMA) && 1552 drvp->DMA_mode == 0) { 1553 drvp->PIO_mode = 0; 1554 return ret; 1555 } 1556 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1557 /* 1558 * PIO and DMA timings are the same, use fast timings for PIO 1559 * too, else use compat timings. 1560 */ 1561 if ((piix_isp_pio[drvp->PIO_mode] != 1562 piix_isp_dma[drvp->DMA_mode]) || 1563 (piix_rtc_pio[drvp->PIO_mode] != 1564 piix_rtc_dma[drvp->DMA_mode])) 1565 drvp->PIO_mode = 0; 1566 /* if PIO mode <= 2, use compat timings for PIO */ 1567 if (drvp->PIO_mode <= 2) { 1568 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1569 channel); 1570 return ret; 1571 } 1572 } 1573 1574 /* 1575 * Now setup PIO modes. If mode < 2, use compat timings. 1576 * Else enable fast timings. Enable IORDY and prefetch/post 1577 * if PIO mode >= 3. 1578 */ 1579 1580 if (drvp->PIO_mode < 2) 1581 return ret; 1582 1583 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1584 if (drvp->PIO_mode >= 3) { 1585 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1586 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1587 } 1588 return ret; 1589 } 1590 1591 /* setup values in SIDETIM registers, based on mode */ 1592 static u_int32_t 1593 piix_setup_sidetim_timings(mode, dma, channel) 1594 u_int8_t mode; 1595 u_int8_t dma; 1596 u_int8_t channel; 1597 { 1598 if (dma) 1599 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1600 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1601 else 1602 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1603 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1604 } 1605 1606 void 1607 apollo_chip_map(sc, pa) 1608 struct pciide_softc *sc; 1609 struct pci_attach_args *pa; 1610 { 1611 struct pciide_channel *cp; 1612 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1613 sc->sc_tag, PCI_CLASS_REG)); 1614 int channel; 1615 u_int32_t ideconf; 1616 bus_size_t cmdsize, ctlsize; 1617 1618 if (pciide_chipen(sc, pa) == 0) 1619 return; 1620 printf("%s: bus-master DMA support present", 1621 sc->sc_wdcdev.sc_dev.dv_xname); 1622 pciide_mapreg_dma(sc, pa); 1623 printf("\n"); 1624 if (sc->sc_dma_ok) { 1625 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1626 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1627 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1628 } 1629 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE; 1630 sc->sc_wdcdev.PIO_cap = 4; 1631 sc->sc_wdcdev.DMA_cap = 2; 1632 sc->sc_wdcdev.UDMA_cap = 2; 1633 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1634 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1635 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1636 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1637 1638 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1639 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1640 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1641 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1642 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1643 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1644 DEBUG_PROBE); 1645 1646 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1647 cp = &sc->pciide_channels[channel]; 1648 if (pciide_chansetup(sc, channel, interface) == 0) 1649 continue; 1650 1651 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1652 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1653 printf("%s: %s channel ignored (disabled)\n", 1654 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1655 continue; 1656 } 1657 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1658 pciide_pci_intr); 1659 if (cp->hw_ok == 0) 1660 continue; 1661 if (pciiide_chan_candisable(cp)) { 1662 ideconf &= ~APO_IDECONF_EN(channel); 1663 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1664 ideconf); 1665 } 1666 pciide_map_compat_intr(pa, cp, channel, interface); 1667 1668 if (cp->hw_ok == 0) 1669 continue; 1670 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1671 } 1672 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1673 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1674 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1675 } 1676 1677 void 1678 apollo_setup_channel(chp) 1679 struct channel_softc *chp; 1680 { 1681 u_int32_t udmatim_reg, datatim_reg; 1682 u_int8_t idedma_ctl; 1683 int mode, drive; 1684 struct ata_drive_datas *drvp; 1685 struct pciide_channel *cp = (struct pciide_channel*)chp; 1686 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1687 1688 idedma_ctl = 0; 1689 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1690 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1691 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1692 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1693 1694 /* setup DMA if needed */ 1695 pciide_channel_dma_setup(cp); 1696 1697 for (drive = 0; drive < 2; drive++) { 1698 drvp = &chp->ch_drive[drive]; 1699 /* If no drive, skip */ 1700 if ((drvp->drive_flags & DRIVE) == 0) 1701 continue; 1702 /* add timing values, setup DMA if needed */ 1703 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1704 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1705 mode = drvp->PIO_mode; 1706 goto pio; 1707 } 1708 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1709 (drvp->drive_flags & DRIVE_UDMA)) { 1710 /* use Ultra/DMA */ 1711 drvp->drive_flags &= ~DRIVE_DMA; 1712 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1713 APO_UDMA_EN_MTH(chp->channel, drive) | 1714 APO_UDMA_TIME(chp->channel, drive, 1715 apollo_udma_tim[drvp->UDMA_mode]); 1716 /* can use PIO timings, MW DMA unused */ 1717 mode = drvp->PIO_mode; 1718 } else { 1719 /* use Multiword DMA */ 1720 drvp->drive_flags &= ~DRIVE_UDMA; 1721 /* mode = min(pio, dma+2) */ 1722 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1723 mode = drvp->PIO_mode; 1724 else 1725 mode = drvp->DMA_mode + 2; 1726 } 1727 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1728 1729 pio: /* setup PIO mode */ 1730 if (mode <= 2) { 1731 drvp->DMA_mode = 0; 1732 drvp->PIO_mode = 0; 1733 mode = 0; 1734 } else { 1735 drvp->PIO_mode = mode; 1736 drvp->DMA_mode = mode - 2; 1737 } 1738 datatim_reg |= 1739 APO_DATATIM_PULSE(chp->channel, drive, 1740 apollo_pio_set[mode]) | 1741 APO_DATATIM_RECOV(chp->channel, drive, 1742 apollo_pio_rec[mode]); 1743 } 1744 if (idedma_ctl != 0) { 1745 /* Add software bits in status register */ 1746 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1747 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1748 idedma_ctl); 1749 } 1750 pciide_print_modes(cp); 1751 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 1752 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 1753 } 1754 1755 void 1756 cmd_channel_map(pa, sc, channel) 1757 struct pci_attach_args *pa; 1758 struct pciide_softc *sc; 1759 int channel; 1760 { 1761 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1762 bus_size_t cmdsize, ctlsize; 1763 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 1764 int interface = 1765 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1766 1767 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1768 cp->name = PCIIDE_CHANNEL_NAME(channel); 1769 cp->wdc_channel.channel = channel; 1770 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1771 1772 if (channel > 0) { 1773 cp->wdc_channel.ch_queue = 1774 sc->pciide_channels[0].wdc_channel.ch_queue; 1775 } else { 1776 cp->wdc_channel.ch_queue = 1777 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1778 } 1779 if (cp->wdc_channel.ch_queue == NULL) { 1780 printf("%s %s channel: " 1781 "can't allocate memory for command queue", 1782 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1783 return; 1784 } 1785 1786 printf("%s: %s channel %s to %s mode\n", 1787 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1788 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1789 "configured" : "wired", 1790 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1791 "native-PCI" : "compatibility"); 1792 1793 /* 1794 * with a CMD PCI64x, if we get here, the first channel is enabled: 1795 * there's no way to disable the first channel without disabling 1796 * the whole device 1797 */ 1798 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 1799 printf("%s: %s channel ignored (disabled)\n", 1800 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1801 return; 1802 } 1803 1804 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 1805 if (cp->hw_ok == 0) 1806 return; 1807 if (channel == 1) { 1808 if (pciiide_chan_candisable(cp)) { 1809 ctrl &= ~CMD_CTRL_2PORT; 1810 pciide_pci_write(pa->pa_pc, pa->pa_tag, 1811 CMD_CTRL, ctrl); 1812 } 1813 } 1814 pciide_map_compat_intr(pa, cp, channel, interface); 1815 } 1816 1817 int 1818 cmd_pci_intr(arg) 1819 void *arg; 1820 { 1821 struct pciide_softc *sc = arg; 1822 struct pciide_channel *cp; 1823 struct channel_softc *wdc_cp; 1824 int i, rv, crv; 1825 u_int32_t priirq, secirq; 1826 1827 rv = 0; 1828 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 1829 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 1830 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1831 cp = &sc->pciide_channels[i]; 1832 wdc_cp = &cp->wdc_channel; 1833 /* If a compat channel skip. */ 1834 if (cp->compat) 1835 continue; 1836 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 1837 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 1838 crv = wdcintr(wdc_cp); 1839 if (crv == 0) 1840 printf("%s:%d: bogus intr\n", 1841 sc->sc_wdcdev.sc_dev.dv_xname, i); 1842 else 1843 rv = 1; 1844 } 1845 } 1846 return rv; 1847 } 1848 1849 void 1850 cmd_chip_map(sc, pa) 1851 struct pciide_softc *sc; 1852 struct pci_attach_args *pa; 1853 { 1854 int channel; 1855 1856 /* 1857 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 1858 * and base adresses registers can be disabled at 1859 * hardware level. In this case, the device is wired 1860 * in compat mode and its first channel is always enabled, 1861 * but we can't rely on PCI_COMMAND_IO_ENABLE. 1862 * In fact, it seems that the first channel of the CMD PCI0640 1863 * can't be disabled. 1864 */ 1865 1866 #ifdef PCIIDE_CMD064x_DISABLE 1867 if (pciide_chipen(sc, pa) == 0) 1868 return; 1869 #endif 1870 1871 printf("%s: hardware does not support DMA\n", 1872 sc->sc_wdcdev.sc_dev.dv_xname); 1873 sc->sc_dma_ok = 0; 1874 1875 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1876 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1877 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1878 1879 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1880 cmd_channel_map(pa, sc, channel); 1881 } 1882 } 1883 1884 void 1885 cmd0643_6_chip_map(sc, pa) 1886 struct pciide_softc *sc; 1887 struct pci_attach_args *pa; 1888 { 1889 struct pciide_channel *cp; 1890 int channel; 1891 1892 /* 1893 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 1894 * and base adresses registers can be disabled at 1895 * hardware level. In this case, the device is wired 1896 * in compat mode and its first channel is always enabled, 1897 * but we can't rely on PCI_COMMAND_IO_ENABLE. 1898 * In fact, it seems that the first channel of the CMD PCI0640 1899 * can't be disabled. 1900 */ 1901 1902 #ifdef PCIIDE_CMD064x_DISABLE 1903 if (pciide_chipen(sc, pa) == 0) 1904 return; 1905 #endif 1906 printf("%s: bus-master DMA support present", 1907 sc->sc_wdcdev.sc_dev.dv_xname); 1908 pciide_mapreg_dma(sc, pa); 1909 printf("\n"); 1910 if (sc->sc_dma_ok) 1911 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1912 1913 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1914 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1915 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1916 WDC_CAPABILITY_MODE; 1917 sc->sc_wdcdev.PIO_cap = 4; 1918 sc->sc_wdcdev.DMA_cap = 2; 1919 sc->sc_wdcdev.set_modes = cmd0643_6_setup_channel; 1920 1921 WDCDEBUG_PRINT(("cmd0643_6_chip_map: old timings reg 0x%x 0x%x\n", 1922 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 1923 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 1924 DEBUG_PROBE); 1925 1926 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1927 cp = &sc->pciide_channels[channel]; 1928 cmd_channel_map(pa, sc, channel); 1929 if (cp->hw_ok == 0) 1930 continue; 1931 cmd0643_6_setup_channel(&cp->wdc_channel); 1932 } 1933 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 1934 WDCDEBUG_PRINT(("cmd0643_6_chip_map: timings reg now 0x%x 0x%x\n", 1935 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 1936 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 1937 DEBUG_PROBE); 1938 } 1939 1940 void 1941 cmd0643_6_setup_channel(chp) 1942 struct channel_softc *chp; 1943 { 1944 struct ata_drive_datas *drvp; 1945 u_int8_t tim; 1946 u_int32_t idedma_ctl; 1947 int drive; 1948 struct pciide_channel *cp = (struct pciide_channel*)chp; 1949 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1950 1951 idedma_ctl = 0; 1952 /* setup DMA if needed */ 1953 pciide_channel_dma_setup(cp); 1954 1955 for (drive = 0; drive < 2; drive++) { 1956 drvp = &chp->ch_drive[drive]; 1957 /* If no drive, skip */ 1958 if ((drvp->drive_flags & DRIVE) == 0) 1959 continue; 1960 /* add timing values, setup DMA if needed */ 1961 tim = cmd0643_6_data_tim_pio[drvp->PIO_mode]; 1962 if (drvp->drive_flags & DRIVE_DMA) { 1963 /* 1964 * use Multiword DMA. 1965 * Timings will be used for both PIO and DMA, so adjust 1966 * DMA mode if needed 1967 */ 1968 if (drvp->PIO_mode >= 3 && 1969 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 1970 drvp->DMA_mode = drvp->PIO_mode - 2; 1971 } 1972 tim = cmd0643_6_data_tim_dma[drvp->DMA_mode]; 1973 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1974 } 1975 pciide_pci_write(sc->sc_pc, sc->sc_tag, 1976 CMD_DATA_TIM(chp->channel, drive), tim); 1977 } 1978 if (idedma_ctl != 0) { 1979 /* Add software bits in status register */ 1980 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1981 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1982 idedma_ctl); 1983 } 1984 pciide_print_modes(cp); 1985 } 1986 1987 void 1988 cy693_chip_map(sc, pa) 1989 struct pciide_softc *sc; 1990 struct pci_attach_args *pa; 1991 { 1992 struct pciide_channel *cp; 1993 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1994 sc->sc_tag, PCI_CLASS_REG)); 1995 int compatchan; 1996 bus_size_t cmdsize, ctlsize; 1997 1998 if (pciide_chipen(sc, pa) == 0) 1999 return; 2000 /* 2001 * this chip has 2 PCI IDE functions, one for primary and one for 2002 * secondary. So we need to call pciide_mapregs_compat() with 2003 * the real channel 2004 */ 2005 if (pa->pa_function == 1) { 2006 compatchan = 0; 2007 } else if (pa->pa_function == 2) { 2008 compatchan = 1; 2009 } else { 2010 printf("%s: unexpected PCI function %d\n", 2011 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2012 cp->hw_ok = 0; 2013 return; 2014 } 2015 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2016 printf("%s: bus-master DMA support present", 2017 sc->sc_wdcdev.sc_dev.dv_xname); 2018 pciide_mapreg_dma(sc, pa); 2019 } else { 2020 printf("%s: hardware does not support DMA", 2021 sc->sc_wdcdev.sc_dev.dv_xname); 2022 sc->sc_dma_ok = 0; 2023 } 2024 printf("\n"); 2025 2026 if (sc->sc_dma_ok) 2027 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2028 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2029 WDC_CAPABILITY_MODE; 2030 sc->sc_wdcdev.PIO_cap = 4; 2031 sc->sc_wdcdev.DMA_cap = 2; 2032 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2033 2034 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2035 sc->sc_wdcdev.nchannels = 1; 2036 2037 /* Only one channel for this chip; if we are here it's enabled */ 2038 cp = &sc->pciide_channels[0]; 2039 sc->wdc_chanarray[0] = &cp->wdc_channel; 2040 cp->name = PCIIDE_CHANNEL_NAME(0); 2041 cp->wdc_channel.channel = 0; 2042 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2043 cp->wdc_channel.ch_queue = 2044 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2045 if (cp->wdc_channel.ch_queue == NULL) { 2046 printf("%s primary channel: " 2047 "can't allocate memory for command queue", 2048 sc->sc_wdcdev.sc_dev.dv_xname); 2049 return; 2050 } 2051 printf("%s: primary channel %s to ", 2052 sc->sc_wdcdev.sc_dev.dv_xname, 2053 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2054 "configured" : "wired"); 2055 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2056 printf("native-PCI"); 2057 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2058 pciide_pci_intr); 2059 } else { 2060 printf("compatibility"); 2061 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2062 &cmdsize, &ctlsize); 2063 } 2064 printf(" mode\n"); 2065 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2066 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2067 wdcattach(&cp->wdc_channel); 2068 if (pciiide_chan_candisable(cp)) { 2069 pci_conf_write(sc->sc_pc, sc->sc_tag, 2070 PCI_COMMAND_STATUS_REG, 0); 2071 } 2072 pciide_map_compat_intr(pa, cp, compatchan, interface); 2073 if (cp->hw_ok == 0) 2074 return; 2075 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2076 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2077 cy693_setup_channel(&cp->wdc_channel); 2078 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2079 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2080 } 2081 2082 void 2083 cy693_setup_channel(chp) 2084 struct channel_softc *chp; 2085 { 2086 struct ata_drive_datas *drvp; 2087 int drive; 2088 u_int32_t cy_cmd_ctrl; 2089 u_int32_t idedma_ctl; 2090 struct pciide_channel *cp = (struct pciide_channel*)chp; 2091 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2092 int dma_mode = -1; 2093 2094 cy_cmd_ctrl = idedma_ctl = 0; 2095 2096 /* setup DMA if needed */ 2097 pciide_channel_dma_setup(cp); 2098 2099 for (drive = 0; drive < 2; drive++) { 2100 drvp = &chp->ch_drive[drive]; 2101 /* If no drive, skip */ 2102 if ((drvp->drive_flags & DRIVE) == 0) 2103 continue; 2104 /* add timing values, setup DMA if needed */ 2105 if (drvp->drive_flags & DRIVE_DMA) { 2106 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2107 /* use Multiword DMA */ 2108 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2109 dma_mode = drvp->DMA_mode; 2110 } 2111 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2112 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2113 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2114 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2115 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2116 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2117 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2118 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2119 } 2120 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2121 chp->ch_drive[0].DMA_mode = dma_mode; 2122 chp->ch_drive[1].DMA_mode = dma_mode; 2123 pciide_print_modes(cp); 2124 if (idedma_ctl != 0) { 2125 /* Add software bits in status register */ 2126 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2127 IDEDMA_CTL, idedma_ctl); 2128 } 2129 } 2130 2131 void 2132 sis_chip_map(sc, pa) 2133 struct pciide_softc *sc; 2134 struct pci_attach_args *pa; 2135 { 2136 struct pciide_channel *cp; 2137 int channel; 2138 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2139 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2140 sc->sc_tag, PCI_CLASS_REG)); 2141 bus_size_t cmdsize, ctlsize; 2142 2143 if (pciide_chipen(sc, pa) == 0) 2144 return; 2145 printf("%s: bus-master DMA support present", 2146 sc->sc_wdcdev.sc_dev.dv_xname); 2147 pciide_mapreg_dma(sc, pa); 2148 printf("\n"); 2149 if (sc->sc_dma_ok) 2150 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2151 2152 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2153 WDC_CAPABILITY_MODE; 2154 sc->sc_wdcdev.PIO_cap = 4; 2155 sc->sc_wdcdev.DMA_cap = 2; 2156 sc->sc_wdcdev.UDMA_cap = 2; 2157 sc->sc_wdcdev.set_modes = sis_setup_channel; 2158 2159 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2160 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2161 2162 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2163 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2164 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2165 2166 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2167 cp = &sc->pciide_channels[channel]; 2168 if (pciide_chansetup(sc, channel, interface) == 0) 2169 continue; 2170 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2171 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2172 printf("%s: %s channel ignored (disabled)\n", 2173 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2174 continue; 2175 } 2176 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2177 pciide_pci_intr); 2178 if (cp->hw_ok == 0) 2179 continue; 2180 if (pciiide_chan_candisable(cp)) { 2181 if (channel == 0) 2182 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2183 else 2184 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2185 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2186 sis_ctr0); 2187 } 2188 pciide_map_compat_intr(pa, cp, channel, interface); 2189 if (cp->hw_ok == 0) 2190 continue; 2191 sis_setup_channel(&cp->wdc_channel); 2192 } 2193 } 2194 2195 void 2196 sis_setup_channel(chp) 2197 struct channel_softc *chp; 2198 { 2199 struct ata_drive_datas *drvp; 2200 int drive; 2201 u_int32_t sis_tim; 2202 u_int32_t idedma_ctl; 2203 struct pciide_channel *cp = (struct pciide_channel*)chp; 2204 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2205 2206 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2207 "channel %d 0x%x\n", chp->channel, 2208 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2209 DEBUG_PROBE); 2210 sis_tim = 0; 2211 idedma_ctl = 0; 2212 /* setup DMA if needed */ 2213 pciide_channel_dma_setup(cp); 2214 2215 for (drive = 0; drive < 2; drive++) { 2216 drvp = &chp->ch_drive[drive]; 2217 /* If no drive, skip */ 2218 if ((drvp->drive_flags & DRIVE) == 0) 2219 continue; 2220 /* add timing values, setup DMA if needed */ 2221 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2222 (drvp->drive_flags & DRIVE_UDMA) == 0) 2223 goto pio; 2224 2225 if (drvp->drive_flags & DRIVE_UDMA) { 2226 /* use Ultra/DMA */ 2227 drvp->drive_flags &= ~DRIVE_DMA; 2228 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2229 SIS_TIM_UDMA_TIME_OFF(drive); 2230 sis_tim |= SIS_TIM_UDMA_EN(drive); 2231 } else { 2232 /* 2233 * use Multiword DMA 2234 * Timings will be used for both PIO and DMA, 2235 * so adjust DMA mode if needed 2236 */ 2237 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2238 drvp->PIO_mode = drvp->DMA_mode + 2; 2239 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2240 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2241 drvp->PIO_mode - 2 : 0; 2242 if (drvp->DMA_mode == 0) 2243 drvp->PIO_mode = 0; 2244 } 2245 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2246 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2247 SIS_TIM_ACT_OFF(drive); 2248 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2249 SIS_TIM_REC_OFF(drive); 2250 } 2251 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2252 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2253 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2254 if (idedma_ctl != 0) { 2255 /* Add software bits in status register */ 2256 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2257 IDEDMA_CTL, idedma_ctl); 2258 } 2259 pciide_print_modes(cp); 2260 } 2261 2262 void 2263 acer_chip_map(sc, pa) 2264 struct pciide_softc *sc; 2265 struct pci_attach_args *pa; 2266 { 2267 struct pciide_channel *cp; 2268 int channel; 2269 pcireg_t cr, interface; 2270 bus_size_t cmdsize, ctlsize; 2271 2272 if (pciide_chipen(sc, pa) == 0) 2273 return; 2274 printf("%s: bus-master DMA support present", 2275 sc->sc_wdcdev.sc_dev.dv_xname); 2276 pciide_mapreg_dma(sc, pa); 2277 printf("\n"); 2278 if (sc->sc_dma_ok) 2279 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2280 2281 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2282 WDC_CAPABILITY_MODE; 2283 2284 sc->sc_wdcdev.PIO_cap = 4; 2285 sc->sc_wdcdev.DMA_cap = 2; 2286 sc->sc_wdcdev.UDMA_cap = 2; 2287 sc->sc_wdcdev.set_modes = acer_setup_channel; 2288 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2289 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2290 2291 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2292 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2293 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2294 2295 /* Enable "microsoft register bits" R/W. */ 2296 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2297 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2298 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2299 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2300 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2301 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2302 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2303 ~ACER_CHANSTATUSREGS_RO); 2304 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2305 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2306 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2307 /* Don't use cr, re-read the real register content instead */ 2308 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2309 PCI_CLASS_REG)); 2310 2311 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2312 cp = &sc->pciide_channels[channel]; 2313 if (pciide_chansetup(sc, channel, interface) == 0) 2314 continue; 2315 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2316 printf("%s: %s channel ignored (disabled)\n", 2317 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2318 continue; 2319 } 2320 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2321 acer_pci_intr); 2322 if (cp->hw_ok == 0) 2323 continue; 2324 if (pciiide_chan_candisable(cp)) { 2325 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2326 pci_conf_write(sc->sc_pc, sc->sc_tag, 2327 PCI_CLASS_REG, cr); 2328 } 2329 pciide_map_compat_intr(pa, cp, channel, interface); 2330 acer_setup_channel(&cp->wdc_channel); 2331 } 2332 } 2333 2334 void 2335 acer_setup_channel(chp) 2336 struct channel_softc *chp; 2337 { 2338 struct ata_drive_datas *drvp; 2339 int drive; 2340 u_int32_t acer_fifo_udma; 2341 u_int32_t idedma_ctl; 2342 struct pciide_channel *cp = (struct pciide_channel*)chp; 2343 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2344 2345 idedma_ctl = 0; 2346 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2347 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2348 acer_fifo_udma), DEBUG_PROBE); 2349 /* setup DMA if needed */ 2350 pciide_channel_dma_setup(cp); 2351 2352 for (drive = 0; drive < 2; drive++) { 2353 drvp = &chp->ch_drive[drive]; 2354 /* If no drive, skip */ 2355 if ((drvp->drive_flags & DRIVE) == 0) 2356 continue; 2357 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2358 "channel %d drive %d 0x%x\n", chp->channel, drive, 2359 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2360 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2361 /* clear FIFO/DMA mode */ 2362 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2363 ACER_UDMA_EN(chp->channel, drive) | 2364 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2365 2366 /* add timing values, setup DMA if needed */ 2367 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2368 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2369 acer_fifo_udma |= 2370 ACER_FTH_OPL(chp->channel, drive, 0x1); 2371 goto pio; 2372 } 2373 2374 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2375 if (drvp->drive_flags & DRIVE_UDMA) { 2376 /* use Ultra/DMA */ 2377 drvp->drive_flags &= ~DRIVE_DMA; 2378 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2379 acer_fifo_udma |= 2380 ACER_UDMA_TIM(chp->channel, drive, 2381 acer_udma[drvp->UDMA_mode]); 2382 } else { 2383 /* 2384 * use Multiword DMA 2385 * Timings will be used for both PIO and DMA, 2386 * so adjust DMA mode if needed 2387 */ 2388 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2389 drvp->PIO_mode = drvp->DMA_mode + 2; 2390 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2391 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2392 drvp->PIO_mode - 2 : 0; 2393 if (drvp->DMA_mode == 0) 2394 drvp->PIO_mode = 0; 2395 } 2396 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2397 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2398 ACER_IDETIM(chp->channel, drive), 2399 acer_pio[drvp->PIO_mode]); 2400 } 2401 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2402 acer_fifo_udma), DEBUG_PROBE); 2403 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2404 if (idedma_ctl != 0) { 2405 /* Add software bits in status register */ 2406 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2407 IDEDMA_CTL, idedma_ctl); 2408 } 2409 pciide_print_modes(cp); 2410 } 2411 2412 int 2413 acer_pci_intr(arg) 2414 void *arg; 2415 { 2416 struct pciide_softc *sc = arg; 2417 struct pciide_channel *cp; 2418 struct channel_softc *wdc_cp; 2419 int i, rv, crv; 2420 u_int32_t chids; 2421 2422 rv = 0; 2423 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2424 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2425 cp = &sc->pciide_channels[i]; 2426 wdc_cp = &cp->wdc_channel; 2427 /* If a compat channel skip. */ 2428 if (cp->compat) 2429 continue; 2430 if (chids & ACER_CHIDS_INT(i)) { 2431 crv = wdcintr(wdc_cp); 2432 if (crv == 0) 2433 printf("%s:%d: bogus intr\n", 2434 sc->sc_wdcdev.sc_dev.dv_xname, i); 2435 else 2436 rv = 1; 2437 } 2438 } 2439 return rv; 2440 } 2441 2442 /* A macro to test product */ 2443 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 2444 2445 void 2446 pdc202xx_chip_map(sc, pa) 2447 struct pciide_softc *sc; 2448 struct pci_attach_args *pa; 2449 { 2450 struct pciide_channel *cp; 2451 int channel; 2452 pcireg_t interface, st, mode; 2453 bus_size_t cmdsize, ctlsize; 2454 2455 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2456 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 2457 DEBUG_PROBE); 2458 if (pciide_chipen(sc, pa) == 0) 2459 return; 2460 2461 /* turn off RAID mode */ 2462 st &= ~PDC2xx_STATE_IDERAID; 2463 2464 /* 2465 * can't rely on the PCI_CLASS_REG content if the chip was in raid 2466 * mode. We have to fake interface 2467 */ 2468 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 2469 if (st & PDC2xx_STATE_NATIVE) 2470 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2471 2472 printf("%s: bus-master DMA support present", 2473 sc->sc_wdcdev.sc_dev.dv_xname); 2474 pciide_mapreg_dma(sc, pa); 2475 printf("\n"); 2476 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2477 WDC_CAPABILITY_MODE; 2478 if (sc->sc_dma_ok) 2479 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2480 sc->sc_wdcdev.PIO_cap = 4; 2481 sc->sc_wdcdev.DMA_cap = 2; 2482 if (PDC_IS_262(sc)) 2483 sc->sc_wdcdev.UDMA_cap = 4; 2484 else 2485 sc->sc_wdcdev.UDMA_cap = 2; 2486 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 2487 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2488 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2489 2490 /* setup failsafe defaults */ 2491 mode = 0; 2492 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 2493 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 2494 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 2495 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 2496 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2497 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 2498 "initial timings 0x%x, now 0x%x\n", channel, 2499 pci_conf_read(sc->sc_pc, sc->sc_tag, 2500 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 2501 DEBUG_PROBE); 2502 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 2503 mode | PDC2xx_TIM_IORDYp); 2504 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 2505 "initial timings 0x%x, now 0x%x\n", channel, 2506 pci_conf_read(sc->sc_pc, sc->sc_tag, 2507 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 2508 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 2509 mode); 2510 } 2511 2512 mode = PDC2xx_SCR_DMA; 2513 if (PDC_IS_262(sc)) { 2514 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 2515 } else { 2516 /* the BIOS set it up this way */ 2517 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 2518 } 2519 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 2520 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 2521 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 2522 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 2523 DEBUG_PROBE); 2524 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 2525 2526 /* controller initial state register is OK even without BIOS */ 2527 /* Set DMA mode to IDE DMA compatibility */ 2528 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 2529 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 2530 DEBUG_PROBE); 2531 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 2532 mode | 0x1); 2533 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 2534 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 2535 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 2536 mode | 0x1); 2537 2538 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2539 cp = &sc->pciide_channels[channel]; 2540 if (pciide_chansetup(sc, channel, interface) == 0) 2541 continue; 2542 if ((st & (PDC_IS_262(sc) ? 2543 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 2544 printf("%s: %s channel ignored (disabled)\n", 2545 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2546 continue; 2547 } 2548 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2549 pdc202xx_pci_intr); 2550 if (cp->hw_ok == 0) 2551 continue; 2552 if (pciiide_chan_candisable(cp)) 2553 st &= ~(PDC_IS_262(sc) ? 2554 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 2555 pciide_map_compat_intr(pa, cp, channel, interface); 2556 pdc202xx_setup_channel(&cp->wdc_channel); 2557 } 2558 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 2559 DEBUG_PROBE); 2560 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 2561 return; 2562 } 2563 2564 void 2565 pdc202xx_setup_channel(chp) 2566 struct channel_softc *chp; 2567 { 2568 struct ata_drive_datas *drvp; 2569 int drive; 2570 pcireg_t mode, st; 2571 u_int32_t idedma_ctl, scr, atapi; 2572 struct pciide_channel *cp = (struct pciide_channel*)chp; 2573 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2574 int channel = chp->channel; 2575 2576 /* setup DMA if needed */ 2577 pciide_channel_dma_setup(cp); 2578 2579 idedma_ctl = 0; 2580 2581 /* Per channel settings */ 2582 if (PDC_IS_262(sc)) { 2583 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2584 PDC262_U66); 2585 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2586 /* Trimm UDMA mode */ 2587 if ((st & PDC262_STATE_80P(channel)) == 0 || 2588 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 2589 chp->ch_drive[0].UDMA_mode <= 2) || 2590 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 2591 chp->ch_drive[1].UDMA_mode <= 2)) { 2592 if (chp->ch_drive[0].UDMA_mode > 2) 2593 chp->ch_drive[0].UDMA_mode = 2; 2594 if (chp->ch_drive[1].UDMA_mode > 2) 2595 chp->ch_drive[1].UDMA_mode = 2; 2596 } 2597 /* Set U66 if needed */ 2598 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 2599 chp->ch_drive[0].UDMA_mode > 2) || 2600 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 2601 chp->ch_drive[1].UDMA_mode > 2)) 2602 scr |= PDC262_U66_EN(channel); 2603 else 2604 scr &= ~PDC262_U66_EN(channel); 2605 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2606 PDC262_U66, scr); 2607 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 2608 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 2609 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2610 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 2611 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 2612 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 2613 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2614 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 2615 atapi = 0; 2616 else 2617 atapi = PDC262_ATAPI_UDMA; 2618 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 2619 PDC262_ATAPI(channel), atapi); 2620 } 2621 } 2622 for (drive = 0; drive < 2; drive++) { 2623 drvp = &chp->ch_drive[drive]; 2624 /* If no drive, skip */ 2625 if ((drvp->drive_flags & DRIVE) == 0) 2626 continue; 2627 mode = 0; 2628 if (drvp->drive_flags & DRIVE_UDMA) { 2629 mode = PDC2xx_TIM_SET_MB(mode, 2630 pdc2xx_udma_mb[drvp->UDMA_mode]); 2631 mode = PDC2xx_TIM_SET_MC(mode, 2632 pdc2xx_udma_mc[drvp->UDMA_mode]); 2633 drvp->drive_flags &= ~DRIVE_DMA; 2634 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2635 } else if (drvp->drive_flags & DRIVE_DMA) { 2636 mode = PDC2xx_TIM_SET_MB(mode, 2637 pdc2xx_dma_mb[drvp->DMA_mode]); 2638 mode = PDC2xx_TIM_SET_MC(mode, 2639 pdc2xx_dma_mc[drvp->DMA_mode]); 2640 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2641 } else { 2642 mode = PDC2xx_TIM_SET_MB(mode, 2643 pdc2xx_dma_mb[0]); 2644 mode = PDC2xx_TIM_SET_MC(mode, 2645 pdc2xx_dma_mc[0]); 2646 } 2647 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 2648 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 2649 if (drvp->drive_flags & DRIVE_ATA) 2650 mode |= PDC2xx_TIM_PRE; 2651 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 2652 if (drvp->PIO_mode >= 3) { 2653 mode |= PDC2xx_TIM_IORDY; 2654 if (drive == 0) 2655 mode |= PDC2xx_TIM_IORDYp; 2656 } 2657 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 2658 "timings 0x%x\n", 2659 sc->sc_wdcdev.sc_dev.dv_xname, 2660 chp->channel, drive, mode), DEBUG_PROBE); 2661 pci_conf_write(sc->sc_pc, sc->sc_tag, 2662 PDC2xx_TIM(chp->channel, drive), mode); 2663 } 2664 if (idedma_ctl != 0) { 2665 /* Add software bits in status register */ 2666 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2667 IDEDMA_CTL, idedma_ctl); 2668 } 2669 pciide_print_modes(cp); 2670 } 2671 2672 int 2673 pdc202xx_pci_intr(arg) 2674 void *arg; 2675 { 2676 struct pciide_softc *sc = arg; 2677 struct pciide_channel *cp; 2678 struct channel_softc *wdc_cp; 2679 int i, rv, crv; 2680 u_int32_t scr; 2681 2682 rv = 0; 2683 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 2684 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2685 cp = &sc->pciide_channels[i]; 2686 wdc_cp = &cp->wdc_channel; 2687 /* If a compat channel skip. */ 2688 if (cp->compat) 2689 continue; 2690 if (scr & PDC2xx_SCR_INT(i)) { 2691 crv = wdcintr(wdc_cp); 2692 if (crv == 0) 2693 printf("%s:%d: bogus intr\n", 2694 sc->sc_wdcdev.sc_dev.dv_xname, i); 2695 else 2696 rv = 1; 2697 } 2698 } 2699 return rv; 2700 } 2701
Indexes created Mon Sep 22 05:09:51 GMT 2025