pciide.c revision 1.53
1 /* $NetBSD: pciide.c,v 1.53 2000/03/06 18:02:26 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 38 /* 39 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by Christopher G. Demetriou 52 * for the NetBSD Project. 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * PCI IDE controller driver. 70 * 71 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 72 * sys/dev/pci/ppb.c, revision 1.16). 73 * 74 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 75 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 76 * 5/16/94" from the PCI SIG. 77 * 78 */ 79 80 #ifndef WDCDEBUG 81 #define WDCDEBUG 82 #endif 83 84 #define DEBUG_DMA 0x01 85 #define DEBUG_XFERS 0x02 86 #define DEBUG_FUNCS 0x08 87 #define DEBUG_PROBE 0x10 88 #ifdef WDCDEBUG 89 int wdcdebug_pciide_mask = 0; 90 #define WDCDEBUG_PRINT(args, level) \ 91 if (wdcdebug_pciide_mask & (level)) printf args 92 #else 93 #define WDCDEBUG_PRINT(args, level) 94 #endif 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/device.h> 98 #include <sys/malloc.h> 99 100 #include <machine/endian.h> 101 102 #include <vm/vm.h> 103 #include <vm/vm_param.h> 104 #include <vm/vm_kern.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 #include <dev/pci/pcidevs.h> 109 #include <dev/pci/pciidereg.h> 110 #include <dev/pci/pciidevar.h> 111 #include <dev/pci/pciide_piix_reg.h> 112 #include <dev/pci/pciide_amd_reg.h> 113 #include <dev/pci/pciide_apollo_reg.h> 114 #include <dev/pci/pciide_cmd_reg.h> 115 #include <dev/pci/pciide_cy693_reg.h> 116 #include <dev/pci/pciide_sis_reg.h> 117 #include <dev/pci/pciide_acer_reg.h> 118 #include <dev/pci/pciide_pdc202xx_reg.h> 119 120 /* inlines for reading/writing 8-bit PCI registers */ 121 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 122 int)); 123 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 124 int, u_int8_t)); 125 126 static __inline u_int8_t 127 pciide_pci_read(pc, pa, reg) 128 pci_chipset_tag_t pc; 129 pcitag_t pa; 130 int reg; 131 { 132 133 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 134 ((reg & 0x03) * 8) & 0xff); 135 } 136 137 static __inline void 138 pciide_pci_write(pc, pa, reg, val) 139 pci_chipset_tag_t pc; 140 pcitag_t pa; 141 int reg; 142 u_int8_t val; 143 { 144 pcireg_t pcival; 145 146 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 147 pcival &= ~(0xff << ((reg & 0x03) * 8)); 148 pcival |= (val << ((reg & 0x03) * 8)); 149 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 150 } 151 152 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 153 154 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 155 void piix_setup_channel __P((struct channel_softc*)); 156 void piix3_4_setup_channel __P((struct channel_softc*)); 157 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 158 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 159 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 160 161 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 162 void amd756_setup_channel __P((struct channel_softc*)); 163 164 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void apollo_setup_channel __P((struct channel_softc*)); 166 167 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void cmd0643_6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 169 void cmd0643_6_setup_channel __P((struct channel_softc*)); 170 void cmd_channel_map __P((struct pci_attach_args *, 171 struct pciide_softc *, int)); 172 int cmd_pci_intr __P((void *)); 173 174 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cy693_setup_channel __P((struct channel_softc*)); 176 177 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void sis_setup_channel __P((struct channel_softc*)); 179 180 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void acer_setup_channel __P((struct channel_softc*)); 182 int acer_pci_intr __P((void *)); 183 184 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void pdc202xx_setup_channel __P((struct channel_softc*)); 186 int pdc202xx_pci_intr __P((void *)); 187 188 void pciide_channel_dma_setup __P((struct pciide_channel *)); 189 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 190 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 191 void pciide_dma_start __P((void*, int, int, int)); 192 int pciide_dma_finish __P((void*, int, int, int)); 193 void pciide_print_modes __P((struct pciide_channel *)); 194 195 struct pciide_product_desc { 196 u_int32_t ide_product; 197 int ide_flags; 198 const char *ide_name; 199 /* map and setup chip, probe drives */ 200 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 201 }; 202 203 /* Flags for ide_flags */ 204 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 205 206 /* Default product description for devices not known from this controller */ 207 const struct pciide_product_desc default_product_desc = { 208 0, 209 0, 210 "Generic PCI IDE controller", 211 default_chip_map, 212 }; 213 214 const struct pciide_product_desc pciide_intel_products[] = { 215 { PCI_PRODUCT_INTEL_82092AA, 216 0, 217 "Intel 82092AA IDE controller", 218 default_chip_map, 219 }, 220 { PCI_PRODUCT_INTEL_82371FB_IDE, 221 0, 222 "Intel 82371FB IDE controller (PIIX)", 223 piix_chip_map, 224 }, 225 { PCI_PRODUCT_INTEL_82371SB_IDE, 226 0, 227 "Intel 82371SB IDE Interface (PIIX3)", 228 piix_chip_map, 229 }, 230 { PCI_PRODUCT_INTEL_82371AB_IDE, 231 0, 232 "Intel 82371AB IDE controller (PIIX4)", 233 piix_chip_map, 234 }, 235 { PCI_PRODUCT_INTEL_82801AA_IDE, 236 0, 237 "Intel 82801AA IDE Controller (ICH)", 238 piix_chip_map, 239 }, 240 { PCI_PRODUCT_INTEL_82801AB_IDE, 241 0, 242 "Intel 82801AB IDE Controller (ICH0)", 243 piix_chip_map, 244 }, 245 { 0, 246 0, 247 NULL, 248 } 249 }; 250 251 const struct pciide_product_desc pciide_amd_products[] = { 252 { PCI_PRODUCT_AMD_PBC756_IDE, 253 0, 254 "Advanced Micro Devices AMD756 IDE Controller", 255 amd756_chip_map 256 }, 257 { 0, 258 0, 259 NULL, 260 } 261 }; 262 263 const struct pciide_product_desc pciide_cmd_products[] = { 264 { PCI_PRODUCT_CMDTECH_640, 265 0, 266 "CMD Technology PCI0640", 267 cmd_chip_map 268 }, 269 { PCI_PRODUCT_CMDTECH_643, 270 0, 271 "CMD Technology PCI0643", 272 cmd0643_6_chip_map, 273 }, 274 { PCI_PRODUCT_CMDTECH_646, 275 0, 276 "CMD Technology PCI0646", 277 cmd0643_6_chip_map, 278 }, 279 { 0, 280 0, 281 NULL, 282 } 283 }; 284 285 const struct pciide_product_desc pciide_via_products[] = { 286 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 287 0, 288 "VIA Technologies VT82C586 (Apollo VP) IDE Controller", 289 apollo_chip_map, 290 }, 291 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 292 0, 293 "VIA Technologies VT82C586A IDE Controller", 294 apollo_chip_map, 295 }, 296 { 0, 297 0, 298 NULL, 299 } 300 }; 301 302 const struct pciide_product_desc pciide_cypress_products[] = { 303 { PCI_PRODUCT_CONTAQ_82C693, 304 0, 305 "Contaq Microsystems CY82C693 IDE Controller", 306 cy693_chip_map, 307 }, 308 { 0, 309 0, 310 NULL, 311 } 312 }; 313 314 const struct pciide_product_desc pciide_sis_products[] = { 315 { PCI_PRODUCT_SIS_5597_IDE, 316 0, 317 "Silicon Integrated System 5597/5598 IDE controller", 318 sis_chip_map, 319 }, 320 { 0, 321 0, 322 NULL, 323 } 324 }; 325 326 const struct pciide_product_desc pciide_acer_products[] = { 327 { PCI_PRODUCT_ALI_M5229, 328 0, 329 "Acer Labs M5229 UDMA IDE Controller", 330 acer_chip_map, 331 }, 332 { 0, 333 0, 334 NULL, 335 } 336 }; 337 338 const struct pciide_product_desc pciide_promise_products[] = { 339 { PCI_PRODUCT_PROMISE_ULTRA33, 340 IDE_PCI_CLASS_OVERRIDE, 341 "Promise Ultra33/ATA Bus Master IDE Accelerator", 342 pdc202xx_chip_map, 343 }, 344 { PCI_PRODUCT_PROMISE_ULTRA66, 345 IDE_PCI_CLASS_OVERRIDE, 346 "Promise Ultra66/ATA Bus Master IDE Accelerator", 347 pdc202xx_chip_map, 348 }, 349 { 0, 350 0, 351 NULL, 352 } 353 }; 354 355 struct pciide_vendor_desc { 356 u_int32_t ide_vendor; 357 const struct pciide_product_desc *ide_products; 358 }; 359 360 const struct pciide_vendor_desc pciide_vendors[] = { 361 { PCI_VENDOR_INTEL, pciide_intel_products }, 362 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 363 { PCI_VENDOR_VIATECH, pciide_via_products }, 364 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 365 { PCI_VENDOR_SIS, pciide_sis_products }, 366 { PCI_VENDOR_ALI, pciide_acer_products }, 367 { PCI_VENDOR_PROMISE, pciide_promise_products }, 368 { PCI_VENDOR_AMD, pciide_amd_products }, 369 { 0, NULL } 370 }; 371 372 #define PCIIDE_CHANNEL_NAME(chan) ((chan) == 0 ? "primary" : "secondary") 373 374 /* options passed via the 'flags' config keyword */ 375 #define PCIIDE_OPTIONS_DMA 0x01 376 377 int pciide_match __P((struct device *, struct cfdata *, void *)); 378 void pciide_attach __P((struct device *, struct device *, void *)); 379 380 struct cfattach pciide_ca = { 381 sizeof(struct pciide_softc), pciide_match, pciide_attach 382 }; 383 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 384 int pciide_mapregs_compat __P(( struct pci_attach_args *, 385 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 386 int pciide_mapregs_native __P((struct pci_attach_args *, 387 struct pciide_channel *, bus_size_t *, bus_size_t *, 388 int (*pci_intr) __P((void *)))); 389 void pciide_mapreg_dma __P((struct pciide_softc *, 390 struct pci_attach_args *)); 391 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 392 void pciide_mapchan __P((struct pci_attach_args *, 393 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 394 int (*pci_intr) __P((void *)))); 395 int pciiide_chan_candisable __P((struct pciide_channel *)); 396 void pciide_map_compat_intr __P(( struct pci_attach_args *, 397 struct pciide_channel *, int, int)); 398 int pciide_print __P((void *, const char *pnp)); 399 int pciide_compat_intr __P((void *)); 400 int pciide_pci_intr __P((void *)); 401 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 402 403 const struct pciide_product_desc * 404 pciide_lookup_product(id) 405 u_int32_t id; 406 { 407 const struct pciide_product_desc *pp; 408 const struct pciide_vendor_desc *vp; 409 410 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 411 if (PCI_VENDOR(id) == vp->ide_vendor) 412 break; 413 414 if ((pp = vp->ide_products) == NULL) 415 return NULL; 416 417 for (; pp->ide_name != NULL; pp++) 418 if (PCI_PRODUCT(id) == pp->ide_product) 419 break; 420 421 if (pp->ide_name == NULL) 422 return NULL; 423 return pp; 424 } 425 426 int 427 pciide_match(parent, match, aux) 428 struct device *parent; 429 struct cfdata *match; 430 void *aux; 431 { 432 struct pci_attach_args *pa = aux; 433 const struct pciide_product_desc *pp; 434 435 /* 436 * Check the ID register to see that it's a PCI IDE controller. 437 * If it is, we assume that we can deal with it; it _should_ 438 * work in a standardized way... 439 */ 440 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 441 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 442 return (1); 443 } 444 445 /* 446 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 447 * controllers. Let see if we can deal with it anyway. 448 */ 449 pp = pciide_lookup_product(pa->pa_id); 450 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 451 return (1); 452 } 453 454 return (0); 455 } 456 457 void 458 pciide_attach(parent, self, aux) 459 struct device *parent, *self; 460 void *aux; 461 { 462 struct pci_attach_args *pa = aux; 463 pci_chipset_tag_t pc = pa->pa_pc; 464 pcitag_t tag = pa->pa_tag; 465 struct pciide_softc *sc = (struct pciide_softc *)self; 466 pcireg_t csr; 467 char devinfo[256]; 468 469 sc->sc_pp = pciide_lookup_product(pa->pa_id); 470 if (sc->sc_pp == NULL) { 471 sc->sc_pp = &default_product_desc; 472 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 473 printf(": %s (rev. 0x%02x)\n", devinfo, 474 PCI_REVISION(pa->pa_class)); 475 } else { 476 printf(": %s\n", sc->sc_pp->ide_name); 477 } 478 sc->sc_pc = pa->pa_pc; 479 sc->sc_tag = pa->pa_tag; 480 #ifdef WDCDEBUG 481 if (wdcdebug_pciide_mask & DEBUG_PROBE) 482 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 483 #endif 484 485 sc->sc_pp->chip_map(sc, pa); 486 487 if (sc->sc_dma_ok) { 488 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 489 csr |= PCI_COMMAND_MASTER_ENABLE; 490 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 491 } 492 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 493 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 494 } 495 496 /* tell wether the chip is enabled or not */ 497 int 498 pciide_chipen(sc, pa) 499 struct pciide_softc *sc; 500 struct pci_attach_args *pa; 501 { 502 pcireg_t csr; 503 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 504 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 505 PCI_COMMAND_STATUS_REG); 506 printf("%s: device disabled (at %s)\n", 507 sc->sc_wdcdev.sc_dev.dv_xname, 508 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 509 "device" : "bridge"); 510 return 0; 511 } 512 return 1; 513 } 514 515 int 516 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 517 struct pci_attach_args *pa; 518 struct pciide_channel *cp; 519 int compatchan; 520 bus_size_t *cmdsizep, *ctlsizep; 521 { 522 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 523 struct channel_softc *wdc_cp = &cp->wdc_channel; 524 525 cp->compat = 1; 526 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 527 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 528 529 wdc_cp->cmd_iot = pa->pa_iot; 530 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 531 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 532 printf("%s: couldn't map %s channel cmd regs\n", 533 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 534 return (0); 535 } 536 537 wdc_cp->ctl_iot = pa->pa_iot; 538 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 539 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 540 printf("%s: couldn't map %s channel ctl regs\n", 541 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 542 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 543 PCIIDE_COMPAT_CMD_SIZE); 544 return (0); 545 } 546 547 return (1); 548 } 549 550 int 551 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 552 struct pci_attach_args * pa; 553 struct pciide_channel *cp; 554 bus_size_t *cmdsizep, *ctlsizep; 555 int (*pci_intr) __P((void *)); 556 { 557 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 558 struct channel_softc *wdc_cp = &cp->wdc_channel; 559 const char *intrstr; 560 pci_intr_handle_t intrhandle; 561 562 cp->compat = 0; 563 564 if (sc->sc_pci_ih == NULL) { 565 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 566 pa->pa_intrline, &intrhandle) != 0) { 567 printf("%s: couldn't map native-PCI interrupt\n", 568 sc->sc_wdcdev.sc_dev.dv_xname); 569 return 0; 570 } 571 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 572 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 573 intrhandle, IPL_BIO, pci_intr, sc); 574 if (sc->sc_pci_ih != NULL) { 575 printf("%s: using %s for native-PCI interrupt\n", 576 sc->sc_wdcdev.sc_dev.dv_xname, 577 intrstr ? intrstr : "unknown interrupt"); 578 } else { 579 printf("%s: couldn't establish native-PCI interrupt", 580 sc->sc_wdcdev.sc_dev.dv_xname); 581 if (intrstr != NULL) 582 printf(" at %s", intrstr); 583 printf("\n"); 584 return 0; 585 } 586 } 587 cp->ih = sc->sc_pci_ih; 588 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 589 PCI_MAPREG_TYPE_IO, 0, 590 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 591 printf("%s: couldn't map %s channel cmd regs\n", 592 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 593 return 0; 594 } 595 596 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 597 PCI_MAPREG_TYPE_IO, 0, 598 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 599 printf("%s: couldn't map %s channel ctl regs\n", 600 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 601 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 602 return 0; 603 } 604 return (1); 605 } 606 607 void 608 pciide_mapreg_dma(sc, pa) 609 struct pciide_softc *sc; 610 struct pci_attach_args *pa; 611 { 612 /* 613 * Map DMA registers 614 * 615 * Note that sc_dma_ok is the right variable to test to see if 616 * DMA can be done. If the interface doesn't support DMA, 617 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 618 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 619 * non-zero if the interface supports DMA and the registers 620 * could be mapped. 621 * 622 * XXX Note that despite the fact that the Bus Master IDE specs 623 * XXX say that "The bus master IDE function uses 16 bytes of IO 624 * XXX space," some controllers (at least the United 625 * XXX Microelectronics UM8886BF) place it in memory space. 626 * XXX eventually, we should probably read the register and check 627 * XXX which type it is. Either that or 'quirk' certain devices. 628 */ 629 sc->sc_dma_ok = (pci_mapreg_map(pa, 630 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0, 631 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 632 sc->sc_dmat = pa->pa_dmat; 633 if (sc->sc_dma_ok == 0) { 634 printf(", but unused (couldn't map registers)"); 635 } else { 636 sc->sc_wdcdev.dma_arg = sc; 637 sc->sc_wdcdev.dma_init = pciide_dma_init; 638 sc->sc_wdcdev.dma_start = pciide_dma_start; 639 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 640 } 641 } 642 int 643 pciide_compat_intr(arg) 644 void *arg; 645 { 646 struct pciide_channel *cp = arg; 647 648 #ifdef DIAGNOSTIC 649 /* should only be called for a compat channel */ 650 if (cp->compat == 0) 651 panic("pciide compat intr called for non-compat chan %p\n", cp); 652 #endif 653 return (wdcintr(&cp->wdc_channel)); 654 } 655 656 int 657 pciide_pci_intr(arg) 658 void *arg; 659 { 660 struct pciide_softc *sc = arg; 661 struct pciide_channel *cp; 662 struct channel_softc *wdc_cp; 663 int i, rv, crv; 664 665 rv = 0; 666 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 667 cp = &sc->pciide_channels[i]; 668 wdc_cp = &cp->wdc_channel; 669 670 /* If a compat channel skip. */ 671 if (cp->compat) 672 continue; 673 /* if this channel not waiting for intr, skip */ 674 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 675 continue; 676 677 crv = wdcintr(wdc_cp); 678 if (crv == 0) 679 ; /* leave rv alone */ 680 else if (crv == 1) 681 rv = 1; /* claim the intr */ 682 else if (rv == 0) /* crv should be -1 in this case */ 683 rv = crv; /* if we've done no better, take it */ 684 } 685 return (rv); 686 } 687 688 void 689 pciide_channel_dma_setup(cp) 690 struct pciide_channel *cp; 691 { 692 int drive; 693 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 694 struct ata_drive_datas *drvp; 695 696 for (drive = 0; drive < 2; drive++) { 697 drvp = &cp->wdc_channel.ch_drive[drive]; 698 /* If no drive, skip */ 699 if ((drvp->drive_flags & DRIVE) == 0) 700 continue; 701 /* setup DMA if needed */ 702 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 703 (drvp->drive_flags & DRIVE_UDMA) == 0) || 704 sc->sc_dma_ok == 0) { 705 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 706 continue; 707 } 708 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 709 != 0) { 710 /* Abort DMA setup */ 711 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 712 continue; 713 } 714 } 715 } 716 717 int 718 pciide_dma_table_setup(sc, channel, drive) 719 struct pciide_softc *sc; 720 int channel, drive; 721 { 722 bus_dma_segment_t seg; 723 int error, rseg; 724 const bus_size_t dma_table_size = 725 sizeof(struct idedma_table) * NIDEDMA_TABLES; 726 struct pciide_dma_maps *dma_maps = 727 &sc->pciide_channels[channel].dma_maps[drive]; 728 729 /* If table was already allocated, just return */ 730 if (dma_maps->dma_table) 731 return 0; 732 733 /* Allocate memory for the DMA tables and map it */ 734 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 735 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 736 BUS_DMA_NOWAIT)) != 0) { 737 printf("%s:%d: unable to allocate table DMA for " 738 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 739 channel, drive, error); 740 return error; 741 } 742 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 743 dma_table_size, 744 (caddr_t *)&dma_maps->dma_table, 745 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 746 printf("%s:%d: unable to map table DMA for" 747 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 748 channel, drive, error); 749 return error; 750 } 751 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 752 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 753 seg.ds_addr), DEBUG_PROBE); 754 755 /* Create and load table DMA map for this disk */ 756 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 757 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 758 &dma_maps->dmamap_table)) != 0) { 759 printf("%s:%d: unable to create table DMA map for " 760 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 761 channel, drive, error); 762 return error; 763 } 764 if ((error = bus_dmamap_load(sc->sc_dmat, 765 dma_maps->dmamap_table, 766 dma_maps->dma_table, 767 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 768 printf("%s:%d: unable to load table DMA map for " 769 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 770 channel, drive, error); 771 return error; 772 } 773 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 774 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 775 /* Create a xfer DMA map for this drive */ 776 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 777 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 778 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 779 &dma_maps->dmamap_xfer)) != 0) { 780 printf("%s:%d: unable to create xfer DMA map for " 781 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 782 channel, drive, error); 783 return error; 784 } 785 return 0; 786 } 787 788 int 789 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 790 void *v; 791 int channel, drive; 792 void *databuf; 793 size_t datalen; 794 int flags; 795 { 796 struct pciide_softc *sc = v; 797 int error, seg; 798 struct pciide_dma_maps *dma_maps = 799 &sc->pciide_channels[channel].dma_maps[drive]; 800 801 error = bus_dmamap_load(sc->sc_dmat, 802 dma_maps->dmamap_xfer, 803 databuf, datalen, NULL, BUS_DMA_NOWAIT); 804 if (error) { 805 printf("%s:%d: unable to load xfer DMA map for" 806 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 807 channel, drive, error); 808 return error; 809 } 810 811 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 812 dma_maps->dmamap_xfer->dm_mapsize, 813 (flags & WDC_DMA_READ) ? 814 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 815 816 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 817 #ifdef DIAGNOSTIC 818 /* A segment must not cross a 64k boundary */ 819 { 820 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 821 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 822 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 823 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 824 printf("pciide_dma: segment %d physical addr 0x%lx" 825 " len 0x%lx not properly aligned\n", 826 seg, phys, len); 827 panic("pciide_dma: buf align"); 828 } 829 } 830 #endif 831 dma_maps->dma_table[seg].base_addr = 832 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 833 dma_maps->dma_table[seg].byte_count = 834 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 835 IDEDMA_BYTE_COUNT_MASK); 836 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 837 seg, le32toh(dma_maps->dma_table[seg].byte_count), 838 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 839 840 } 841 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 842 htole32(IDEDMA_BYTE_COUNT_EOT); 843 844 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 845 dma_maps->dmamap_table->dm_mapsize, 846 BUS_DMASYNC_PREWRITE); 847 848 /* Maps are ready. Start DMA function */ 849 #ifdef DIAGNOSTIC 850 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 851 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 852 dma_maps->dmamap_table->dm_segs[0].ds_addr); 853 panic("pciide_dma_init: table align"); 854 } 855 #endif 856 857 /* Clear status bits */ 858 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 859 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 860 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 861 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 862 /* Write table addr */ 863 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 864 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 865 dma_maps->dmamap_table->dm_segs[0].ds_addr); 866 /* set read/write */ 867 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 868 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 869 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 870 return 0; 871 } 872 873 void 874 pciide_dma_start(v, channel, drive, flags) 875 void *v; 876 int channel, drive, flags; 877 { 878 struct pciide_softc *sc = v; 879 880 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 881 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 882 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 883 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 884 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 885 } 886 887 int 888 pciide_dma_finish(v, channel, drive, flags) 889 void *v; 890 int channel, drive; 891 int flags; 892 { 893 struct pciide_softc *sc = v; 894 u_int8_t status; 895 struct pciide_dma_maps *dma_maps = 896 &sc->pciide_channels[channel].dma_maps[drive]; 897 898 /* Unload the map of the data buffer */ 899 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 900 dma_maps->dmamap_xfer->dm_mapsize, 901 (flags & WDC_DMA_READ) ? 902 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 903 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 904 905 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 906 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 907 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 908 DEBUG_XFERS); 909 910 /* stop DMA channel */ 911 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 912 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 913 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 914 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 915 916 /* Clear status bits */ 917 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 918 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 919 status); 920 921 if ((status & IDEDMA_CTL_ERR) != 0) { 922 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 923 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 924 return -1; 925 } 926 927 if ((flags & WDC_DMA_POLL) == 0 && (status & IDEDMA_CTL_INTR) == 0) { 928 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 929 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 930 drive, status); 931 return -1; 932 } 933 934 if ((status & IDEDMA_CTL_ACT) != 0) { 935 /* data underrun, may be a valid condition for ATAPI */ 936 return 1; 937 } 938 return 0; 939 } 940 941 /* some common code used by several chip_map */ 942 int 943 pciide_chansetup(sc, channel, interface) 944 struct pciide_softc *sc; 945 int channel; 946 pcireg_t interface; 947 { 948 struct pciide_channel *cp = &sc->pciide_channels[channel]; 949 sc->wdc_chanarray[channel] = &cp->wdc_channel; 950 cp->name = PCIIDE_CHANNEL_NAME(channel); 951 cp->wdc_channel.channel = channel; 952 cp->wdc_channel.wdc = &sc->sc_wdcdev; 953 cp->wdc_channel.ch_queue = 954 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 955 if (cp->wdc_channel.ch_queue == NULL) { 956 printf("%s %s channel: " 957 "can't allocate memory for command queue", 958 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 959 return 0; 960 } 961 printf("%s: %s channel %s to %s mode\n", 962 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 963 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 964 "configured" : "wired", 965 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 966 "native-PCI" : "compatibility"); 967 return 1; 968 } 969 970 /* some common code used by several chip channel_map */ 971 void 972 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 973 struct pci_attach_args *pa; 974 struct pciide_channel *cp; 975 pcireg_t interface; 976 bus_size_t *cmdsizep, *ctlsizep; 977 int (*pci_intr) __P((void *)); 978 { 979 struct channel_softc *wdc_cp = &cp->wdc_channel; 980 981 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 982 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 983 pci_intr); 984 else 985 cp->hw_ok = pciide_mapregs_compat(pa, cp, 986 wdc_cp->channel, cmdsizep, ctlsizep); 987 988 if (cp->hw_ok == 0) 989 return; 990 wdc_cp->data32iot = wdc_cp->cmd_iot; 991 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 992 wdcattach(wdc_cp); 993 } 994 995 /* 996 * Generic code to call to know if a channel can be disabled. Return 1 997 * if channel can be disabled, 0 if not 998 */ 999 int 1000 pciiide_chan_candisable(cp) 1001 struct pciide_channel *cp; 1002 { 1003 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1004 struct channel_softc *wdc_cp = &cp->wdc_channel; 1005 1006 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1007 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1008 printf("%s: disabling %s channel (no drives)\n", 1009 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1010 cp->hw_ok = 0; 1011 return 1; 1012 } 1013 return 0; 1014 } 1015 1016 /* 1017 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1018 * Set hw_ok=0 on failure 1019 */ 1020 void 1021 pciide_map_compat_intr(pa, cp, compatchan, interface) 1022 struct pci_attach_args *pa; 1023 struct pciide_channel *cp; 1024 int compatchan, interface; 1025 { 1026 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1027 struct channel_softc *wdc_cp = &cp->wdc_channel; 1028 1029 if (cp->hw_ok == 0) 1030 return; 1031 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1032 return; 1033 1034 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1035 pa, compatchan, pciide_compat_intr, cp); 1036 if (cp->ih == NULL) { 1037 printf("%s: no compatibility interrupt for use by %s " 1038 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1039 cp->hw_ok = 0; 1040 } 1041 } 1042 1043 void 1044 pciide_print_modes(cp) 1045 struct pciide_channel *cp; 1046 { 1047 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1048 int drive; 1049 struct channel_softc *chp; 1050 struct ata_drive_datas *drvp; 1051 1052 chp = &cp->wdc_channel; 1053 for (drive = 0; drive < 2; drive++) { 1054 drvp = &chp->ch_drive[drive]; 1055 if ((drvp->drive_flags & DRIVE) == 0) 1056 continue; 1057 printf("%s(%s:%d:%d): using PIO mode %d", 1058 drvp->drv_softc->dv_xname, 1059 sc->sc_wdcdev.sc_dev.dv_xname, 1060 chp->channel, drive, drvp->PIO_mode); 1061 if (drvp->drive_flags & DRIVE_DMA) 1062 printf(", DMA mode %d", drvp->DMA_mode); 1063 if (drvp->drive_flags & DRIVE_UDMA) 1064 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1065 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1066 printf(" (using DMA data transfers)"); 1067 printf("\n"); 1068 } 1069 } 1070 1071 void 1072 default_chip_map(sc, pa) 1073 struct pciide_softc *sc; 1074 struct pci_attach_args *pa; 1075 { 1076 struct pciide_channel *cp; 1077 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1078 sc->sc_tag, PCI_CLASS_REG)); 1079 pcireg_t csr; 1080 int channel, drive; 1081 struct ata_drive_datas *drvp; 1082 u_int8_t idedma_ctl; 1083 bus_size_t cmdsize, ctlsize; 1084 char *failreason; 1085 1086 if (pciide_chipen(sc, pa) == 0) 1087 return; 1088 1089 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1090 printf("%s: bus-master DMA support present", 1091 sc->sc_wdcdev.sc_dev.dv_xname); 1092 if (sc->sc_pp == &default_product_desc && 1093 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1094 PCIIDE_OPTIONS_DMA) == 0) { 1095 printf(", but unused (no driver support)"); 1096 sc->sc_dma_ok = 0; 1097 } else { 1098 pciide_mapreg_dma(sc, pa); 1099 if (sc->sc_dma_ok != 0) 1100 printf(", used without full driver " 1101 "support"); 1102 } 1103 } else { 1104 printf("%s: hardware does not support DMA", 1105 sc->sc_wdcdev.sc_dev.dv_xname); 1106 sc->sc_dma_ok = 0; 1107 } 1108 printf("\n"); 1109 if (sc->sc_dma_ok) 1110 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1111 sc->sc_wdcdev.PIO_cap = 0; 1112 sc->sc_wdcdev.DMA_cap = 0; 1113 1114 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1115 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1116 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1117 1118 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1119 cp = &sc->pciide_channels[channel]; 1120 if (pciide_chansetup(sc, channel, interface) == 0) 1121 continue; 1122 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1123 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1124 &ctlsize, pciide_pci_intr); 1125 } else { 1126 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1127 channel, &cmdsize, &ctlsize); 1128 } 1129 if (cp->hw_ok == 0) 1130 continue; 1131 /* 1132 * Check to see if something appears to be there. 1133 */ 1134 failreason = NULL; 1135 if (!wdcprobe(&cp->wdc_channel)) { 1136 failreason = "not responding; disabled or no drives?"; 1137 goto next; 1138 } 1139 /* 1140 * Now, make sure it's actually attributable to this PCI IDE 1141 * channel by trying to access the channel again while the 1142 * PCI IDE controller's I/O space is disabled. (If the 1143 * channel no longer appears to be there, it belongs to 1144 * this controller.) YUCK! 1145 */ 1146 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1147 PCI_COMMAND_STATUS_REG); 1148 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1149 csr & ~PCI_COMMAND_IO_ENABLE); 1150 if (wdcprobe(&cp->wdc_channel)) 1151 failreason = "other hardware responding at addresses"; 1152 pci_conf_write(sc->sc_pc, sc->sc_tag, 1153 PCI_COMMAND_STATUS_REG, csr); 1154 next: 1155 if (failreason) { 1156 printf("%s: %s channel ignored (%s)\n", 1157 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1158 failreason); 1159 cp->hw_ok = 0; 1160 bus_space_unmap(cp->wdc_channel.cmd_iot, 1161 cp->wdc_channel.cmd_ioh, cmdsize); 1162 bus_space_unmap(cp->wdc_channel.ctl_iot, 1163 cp->wdc_channel.ctl_ioh, ctlsize); 1164 } else { 1165 pciide_map_compat_intr(pa, cp, channel, interface); 1166 } 1167 if (cp->hw_ok) { 1168 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1169 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1170 wdcattach(&cp->wdc_channel); 1171 } 1172 } 1173 1174 if (sc->sc_dma_ok == 0) 1175 return; 1176 1177 /* Allocate DMA maps */ 1178 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1179 idedma_ctl = 0; 1180 cp = &sc->pciide_channels[channel]; 1181 for (drive = 0; drive < 2; drive++) { 1182 drvp = &cp->wdc_channel.ch_drive[drive]; 1183 /* If no drive, skip */ 1184 if ((drvp->drive_flags & DRIVE) == 0) 1185 continue; 1186 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1187 continue; 1188 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1189 /* Abort DMA setup */ 1190 printf("%s:%d:%d: can't allocate DMA maps, " 1191 "using PIO transfers\n", 1192 sc->sc_wdcdev.sc_dev.dv_xname, 1193 channel, drive); 1194 drvp->drive_flags &= ~DRIVE_DMA; 1195 } 1196 printf("%s:%d:%d: using DMA data transfers\n", 1197 sc->sc_wdcdev.sc_dev.dv_xname, 1198 channel, drive); 1199 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1200 } 1201 if (idedma_ctl != 0) { 1202 /* Add software bits in status register */ 1203 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1204 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1205 idedma_ctl); 1206 } 1207 } 1208 } 1209 1210 void 1211 piix_chip_map(sc, pa) 1212 struct pciide_softc *sc; 1213 struct pci_attach_args *pa; 1214 { 1215 struct pciide_channel *cp; 1216 int channel; 1217 u_int32_t idetim; 1218 bus_size_t cmdsize, ctlsize; 1219 1220 if (pciide_chipen(sc, pa) == 0) 1221 return; 1222 1223 printf("%s: bus-master DMA support present", 1224 sc->sc_wdcdev.sc_dev.dv_xname); 1225 pciide_mapreg_dma(sc, pa); 1226 printf("\n"); 1227 if (sc->sc_dma_ok) { 1228 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1229 switch(sc->sc_pp->ide_product) { 1230 case PCI_PRODUCT_INTEL_82371AB_IDE: 1231 case PCI_PRODUCT_INTEL_82801AA_IDE: 1232 case PCI_PRODUCT_INTEL_82801AB_IDE: 1233 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1234 } 1235 } 1236 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1237 WDC_CAPABILITY_MODE; 1238 sc->sc_wdcdev.PIO_cap = 4; 1239 sc->sc_wdcdev.DMA_cap = 2; 1240 sc->sc_wdcdev.UDMA_cap = 1241 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1242 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1243 sc->sc_wdcdev.set_modes = piix_setup_channel; 1244 else 1245 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1246 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1247 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1248 1249 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1250 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1251 DEBUG_PROBE); 1252 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1253 WDCDEBUG_PRINT((", sidetim=0x%x", 1254 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1255 DEBUG_PROBE); 1256 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1257 WDCDEBUG_PRINT((", udamreg 0x%x", 1258 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1259 DEBUG_PROBE); 1260 } 1261 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1262 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1263 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1264 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1265 DEBUG_PROBE); 1266 } 1267 1268 } 1269 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1270 1271 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1272 cp = &sc->pciide_channels[channel]; 1273 /* PIIX is compat-only */ 1274 if (pciide_chansetup(sc, channel, 0) == 0) 1275 continue; 1276 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1277 if ((PIIX_IDETIM_READ(idetim, channel) & 1278 PIIX_IDETIM_IDE) == 0) { 1279 printf("%s: %s channel ignored (disabled)\n", 1280 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1281 continue; 1282 } 1283 /* PIIX are compat-only pciide devices */ 1284 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1285 if (cp->hw_ok == 0) 1286 continue; 1287 if (pciiide_chan_candisable(cp)) { 1288 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1289 channel); 1290 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1291 idetim); 1292 } 1293 pciide_map_compat_intr(pa, cp, channel, 0); 1294 if (cp->hw_ok == 0) 1295 continue; 1296 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1297 } 1298 1299 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1300 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1301 DEBUG_PROBE); 1302 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1303 WDCDEBUG_PRINT((", sidetim=0x%x", 1304 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1305 DEBUG_PROBE); 1306 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1307 WDCDEBUG_PRINT((", udamreg 0x%x", 1308 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1309 DEBUG_PROBE); 1310 } 1311 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1312 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1313 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1314 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1315 DEBUG_PROBE); 1316 } 1317 } 1318 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1319 } 1320 1321 void 1322 piix_setup_channel(chp) 1323 struct channel_softc *chp; 1324 { 1325 u_int8_t mode[2], drive; 1326 u_int32_t oidetim, idetim, idedma_ctl; 1327 struct pciide_channel *cp = (struct pciide_channel*)chp; 1328 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1329 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1330 1331 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1332 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1333 idedma_ctl = 0; 1334 1335 /* set up new idetim: Enable IDE registers decode */ 1336 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1337 chp->channel); 1338 1339 /* setup DMA */ 1340 pciide_channel_dma_setup(cp); 1341 1342 /* 1343 * Here we have to mess up with drives mode: PIIX can't have 1344 * different timings for master and slave drives. 1345 * We need to find the best combination. 1346 */ 1347 1348 /* If both drives supports DMA, take the lower mode */ 1349 if ((drvp[0].drive_flags & DRIVE_DMA) && 1350 (drvp[1].drive_flags & DRIVE_DMA)) { 1351 mode[0] = mode[1] = 1352 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1353 drvp[0].DMA_mode = mode[0]; 1354 drvp[1].DMA_mode = mode[1]; 1355 goto ok; 1356 } 1357 /* 1358 * If only one drive supports DMA, use its mode, and 1359 * put the other one in PIO mode 0 if mode not compatible 1360 */ 1361 if (drvp[0].drive_flags & DRIVE_DMA) { 1362 mode[0] = drvp[0].DMA_mode; 1363 mode[1] = drvp[1].PIO_mode; 1364 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1365 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1366 mode[1] = drvp[1].PIO_mode = 0; 1367 goto ok; 1368 } 1369 if (drvp[1].drive_flags & DRIVE_DMA) { 1370 mode[1] = drvp[1].DMA_mode; 1371 mode[0] = drvp[0].PIO_mode; 1372 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1373 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1374 mode[0] = drvp[0].PIO_mode = 0; 1375 goto ok; 1376 } 1377 /* 1378 * If both drives are not DMA, takes the lower mode, unless 1379 * one of them is PIO mode < 2 1380 */ 1381 if (drvp[0].PIO_mode < 2) { 1382 mode[0] = drvp[0].PIO_mode = 0; 1383 mode[1] = drvp[1].PIO_mode; 1384 } else if (drvp[1].PIO_mode < 2) { 1385 mode[1] = drvp[1].PIO_mode = 0; 1386 mode[0] = drvp[0].PIO_mode; 1387 } else { 1388 mode[0] = mode[1] = 1389 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1390 drvp[0].PIO_mode = mode[0]; 1391 drvp[1].PIO_mode = mode[1]; 1392 } 1393 ok: /* The modes are setup */ 1394 for (drive = 0; drive < 2; drive++) { 1395 if (drvp[drive].drive_flags & DRIVE_DMA) { 1396 idetim |= piix_setup_idetim_timings( 1397 mode[drive], 1, chp->channel); 1398 goto end; 1399 } 1400 } 1401 /* If we are there, none of the drives are DMA */ 1402 if (mode[0] >= 2) 1403 idetim |= piix_setup_idetim_timings( 1404 mode[0], 0, chp->channel); 1405 else 1406 idetim |= piix_setup_idetim_timings( 1407 mode[1], 0, chp->channel); 1408 end: /* 1409 * timing mode is now set up in the controller. Enable 1410 * it per-drive 1411 */ 1412 for (drive = 0; drive < 2; drive++) { 1413 /* If no drive, skip */ 1414 if ((drvp[drive].drive_flags & DRIVE) == 0) 1415 continue; 1416 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1417 if (drvp[drive].drive_flags & DRIVE_DMA) 1418 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1419 } 1420 if (idedma_ctl != 0) { 1421 /* Add software bits in status register */ 1422 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1423 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1424 idedma_ctl); 1425 } 1426 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1427 pciide_print_modes(cp); 1428 } 1429 1430 void 1431 piix3_4_setup_channel(chp) 1432 struct channel_softc *chp; 1433 { 1434 struct ata_drive_datas *drvp; 1435 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1436 struct pciide_channel *cp = (struct pciide_channel*)chp; 1437 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1438 int drive; 1439 int channel = chp->channel; 1440 1441 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1442 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1443 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1444 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1445 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1446 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1447 PIIX_SIDETIM_RTC_MASK(channel)); 1448 1449 idedma_ctl = 0; 1450 /* If channel disabled, no need to go further */ 1451 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1452 return; 1453 /* set up new idetim: Enable IDE registers decode */ 1454 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1455 1456 /* setup DMA if needed */ 1457 pciide_channel_dma_setup(cp); 1458 1459 for (drive = 0; drive < 2; drive++) { 1460 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1461 PIIX_UDMATIM_SET(0x3, channel, drive)); 1462 drvp = &chp->ch_drive[drive]; 1463 /* If no drive, skip */ 1464 if ((drvp->drive_flags & DRIVE) == 0) 1465 continue; 1466 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1467 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1468 goto pio; 1469 1470 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1471 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1472 ideconf |= PIIX_CONFIG_PINGPONG; 1473 } 1474 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1475 /* setup Ultra/66 */ 1476 if (drvp->UDMA_mode > 2 && 1477 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1478 drvp->UDMA_mode = 2; 1479 if (drvp->UDMA_mode > 2) 1480 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1481 else 1482 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1483 } 1484 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1485 (drvp->drive_flags & DRIVE_UDMA)) { 1486 /* use Ultra/DMA */ 1487 drvp->drive_flags &= ~DRIVE_DMA; 1488 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1489 udmareg |= PIIX_UDMATIM_SET( 1490 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1491 } else { 1492 /* use Multiword DMA */ 1493 drvp->drive_flags &= ~DRIVE_UDMA; 1494 if (drive == 0) { 1495 idetim |= piix_setup_idetim_timings( 1496 drvp->DMA_mode, 1, channel); 1497 } else { 1498 sidetim |= piix_setup_sidetim_timings( 1499 drvp->DMA_mode, 1, channel); 1500 idetim =PIIX_IDETIM_SET(idetim, 1501 PIIX_IDETIM_SITRE, channel); 1502 } 1503 } 1504 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1505 1506 pio: /* use PIO mode */ 1507 idetim |= piix_setup_idetim_drvs(drvp); 1508 if (drive == 0) { 1509 idetim |= piix_setup_idetim_timings( 1510 drvp->PIO_mode, 0, channel); 1511 } else { 1512 sidetim |= piix_setup_sidetim_timings( 1513 drvp->PIO_mode, 0, channel); 1514 idetim =PIIX_IDETIM_SET(idetim, 1515 PIIX_IDETIM_SITRE, channel); 1516 } 1517 } 1518 if (idedma_ctl != 0) { 1519 /* Add software bits in status register */ 1520 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1521 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1522 idedma_ctl); 1523 } 1524 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1525 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1526 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1527 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1528 pciide_print_modes(cp); 1529 } 1530 1531 1532 /* setup ISP and RTC fields, based on mode */ 1533 static u_int32_t 1534 piix_setup_idetim_timings(mode, dma, channel) 1535 u_int8_t mode; 1536 u_int8_t dma; 1537 u_int8_t channel; 1538 { 1539 1540 if (dma) 1541 return PIIX_IDETIM_SET(0, 1542 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1543 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1544 channel); 1545 else 1546 return PIIX_IDETIM_SET(0, 1547 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1548 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1549 channel); 1550 } 1551 1552 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1553 static u_int32_t 1554 piix_setup_idetim_drvs(drvp) 1555 struct ata_drive_datas *drvp; 1556 { 1557 u_int32_t ret = 0; 1558 struct channel_softc *chp = drvp->chnl_softc; 1559 u_int8_t channel = chp->channel; 1560 u_int8_t drive = drvp->drive; 1561 1562 /* 1563 * If drive is using UDMA, timings setups are independant 1564 * So just check DMA and PIO here. 1565 */ 1566 if (drvp->drive_flags & DRIVE_DMA) { 1567 /* if mode = DMA mode 0, use compatible timings */ 1568 if ((drvp->drive_flags & DRIVE_DMA) && 1569 drvp->DMA_mode == 0) { 1570 drvp->PIO_mode = 0; 1571 return ret; 1572 } 1573 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1574 /* 1575 * PIO and DMA timings are the same, use fast timings for PIO 1576 * too, else use compat timings. 1577 */ 1578 if ((piix_isp_pio[drvp->PIO_mode] != 1579 piix_isp_dma[drvp->DMA_mode]) || 1580 (piix_rtc_pio[drvp->PIO_mode] != 1581 piix_rtc_dma[drvp->DMA_mode])) 1582 drvp->PIO_mode = 0; 1583 /* if PIO mode <= 2, use compat timings for PIO */ 1584 if (drvp->PIO_mode <= 2) { 1585 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1586 channel); 1587 return ret; 1588 } 1589 } 1590 1591 /* 1592 * Now setup PIO modes. If mode < 2, use compat timings. 1593 * Else enable fast timings. Enable IORDY and prefetch/post 1594 * if PIO mode >= 3. 1595 */ 1596 1597 if (drvp->PIO_mode < 2) 1598 return ret; 1599 1600 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1601 if (drvp->PIO_mode >= 3) { 1602 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1603 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1604 } 1605 return ret; 1606 } 1607 1608 /* setup values in SIDETIM registers, based on mode */ 1609 static u_int32_t 1610 piix_setup_sidetim_timings(mode, dma, channel) 1611 u_int8_t mode; 1612 u_int8_t dma; 1613 u_int8_t channel; 1614 { 1615 if (dma) 1616 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1617 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1618 else 1619 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1620 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1621 } 1622 1623 void 1624 amd756_chip_map(sc, pa) 1625 struct pciide_softc *sc; 1626 struct pci_attach_args *pa; 1627 { 1628 struct pciide_channel *cp; 1629 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1630 sc->sc_tag, PCI_CLASS_REG)); 1631 int channel; 1632 pcireg_t chanenable; 1633 bus_size_t cmdsize, ctlsize; 1634 1635 if (pciide_chipen(sc, pa) == 0) 1636 return; 1637 printf("%s: bus-master DMA support present", 1638 sc->sc_wdcdev.sc_dev.dv_xname); 1639 pciide_mapreg_dma(sc, pa); 1640 printf("\n"); 1641 if (sc->sc_dma_ok) 1642 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1643 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1644 WDC_CAPABILITY_MODE; 1645 sc->sc_wdcdev.PIO_cap = 4; 1646 sc->sc_wdcdev.DMA_cap = 2; 1647 sc->sc_wdcdev.UDMA_cap = 4; 1648 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1649 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1650 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1651 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1652 1653 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1654 DEBUG_PROBE); 1655 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1656 cp = &sc->pciide_channels[channel]; 1657 if (pciide_chansetup(sc, channel, interface) == 0) 1658 continue; 1659 1660 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1661 printf("%s: %s channel ignored (disabled)\n", 1662 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1663 continue; 1664 } 1665 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1666 pciide_pci_intr); 1667 1668 if (pciiide_chan_candisable(cp)) 1669 chanenable &= ~AMD756_CHAN_EN(channel); 1670 pciide_map_compat_intr(pa, cp, channel, interface); 1671 if (cp->hw_ok == 0) 1672 continue; 1673 1674 amd756_setup_channel(&cp->wdc_channel); 1675 } 1676 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1677 chanenable); 1678 return; 1679 } 1680 1681 void 1682 amd756_setup_channel(chp) 1683 struct channel_softc *chp; 1684 { 1685 u_int32_t udmatim_reg, datatim_reg; 1686 u_int8_t idedma_ctl; 1687 int mode, drive; 1688 struct ata_drive_datas *drvp; 1689 struct pciide_channel *cp = (struct pciide_channel*)chp; 1690 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1691 1692 idedma_ctl = 0; 1693 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1694 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1695 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1696 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1697 1698 /* setup DMA if needed */ 1699 pciide_channel_dma_setup(cp); 1700 1701 for (drive = 0; drive < 2; drive++) { 1702 drvp = &chp->ch_drive[drive]; 1703 /* If no drive, skip */ 1704 if ((drvp->drive_flags & DRIVE) == 0) 1705 continue; 1706 /* add timing values, setup DMA if needed */ 1707 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1708 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1709 mode = drvp->PIO_mode; 1710 goto pio; 1711 } 1712 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1713 (drvp->drive_flags & DRIVE_UDMA)) { 1714 /* use Ultra/DMA */ 1715 drvp->drive_flags &= ~DRIVE_DMA; 1716 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1717 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1718 AMD756_UDMA_TIME(chp->channel, drive, 1719 amd756_udma_tim[drvp->UDMA_mode]); 1720 /* can use PIO timings, MW DMA unused */ 1721 mode = drvp->PIO_mode; 1722 } else { 1723 /* use Multiword DMA */ 1724 drvp->drive_flags &= ~DRIVE_UDMA; 1725 /* mode = min(pio, dma+2) */ 1726 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1727 mode = drvp->PIO_mode; 1728 else 1729 mode = drvp->DMA_mode + 2; 1730 } 1731 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1732 1733 pio: /* setup PIO mode */ 1734 if (mode <= 2) { 1735 drvp->DMA_mode = 0; 1736 drvp->PIO_mode = 0; 1737 mode = 0; 1738 } else { 1739 drvp->PIO_mode = mode; 1740 drvp->DMA_mode = mode - 2; 1741 } 1742 datatim_reg |= 1743 AMD756_DATATIM_PULSE(chp->channel, drive, 1744 amd756_pio_set[mode]) | 1745 AMD756_DATATIM_RECOV(chp->channel, drive, 1746 amd756_pio_rec[mode]); 1747 } 1748 if (idedma_ctl != 0) { 1749 /* Add software bits in status register */ 1750 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1751 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1752 idedma_ctl); 1753 } 1754 pciide_print_modes(cp); 1755 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1756 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1757 } 1758 1759 void 1760 apollo_chip_map(sc, pa) 1761 struct pciide_softc *sc; 1762 struct pci_attach_args *pa; 1763 { 1764 struct pciide_channel *cp; 1765 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1766 sc->sc_tag, PCI_CLASS_REG)); 1767 int channel; 1768 u_int32_t ideconf; 1769 bus_size_t cmdsize, ctlsize; 1770 1771 if (pciide_chipen(sc, pa) == 0) 1772 return; 1773 printf("%s: bus-master DMA support present", 1774 sc->sc_wdcdev.sc_dev.dv_xname); 1775 pciide_mapreg_dma(sc, pa); 1776 printf("\n"); 1777 if (sc->sc_dma_ok) { 1778 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1779 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1780 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1781 } 1782 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE; 1783 sc->sc_wdcdev.PIO_cap = 4; 1784 sc->sc_wdcdev.DMA_cap = 2; 1785 sc->sc_wdcdev.UDMA_cap = 2; 1786 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1787 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1788 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1789 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1790 1791 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1792 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1793 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1794 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1795 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1796 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1797 DEBUG_PROBE); 1798 1799 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1800 cp = &sc->pciide_channels[channel]; 1801 if (pciide_chansetup(sc, channel, interface) == 0) 1802 continue; 1803 1804 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1805 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1806 printf("%s: %s channel ignored (disabled)\n", 1807 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1808 continue; 1809 } 1810 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1811 pciide_pci_intr); 1812 if (cp->hw_ok == 0) 1813 continue; 1814 if (pciiide_chan_candisable(cp)) { 1815 ideconf &= ~APO_IDECONF_EN(channel); 1816 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1817 ideconf); 1818 } 1819 pciide_map_compat_intr(pa, cp, channel, interface); 1820 1821 if (cp->hw_ok == 0) 1822 continue; 1823 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1824 } 1825 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1826 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1827 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1828 } 1829 1830 void 1831 apollo_setup_channel(chp) 1832 struct channel_softc *chp; 1833 { 1834 u_int32_t udmatim_reg, datatim_reg; 1835 u_int8_t idedma_ctl; 1836 int mode, drive; 1837 struct ata_drive_datas *drvp; 1838 struct pciide_channel *cp = (struct pciide_channel*)chp; 1839 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1840 1841 idedma_ctl = 0; 1842 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1843 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1844 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1845 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1846 1847 /* setup DMA if needed */ 1848 pciide_channel_dma_setup(cp); 1849 1850 for (drive = 0; drive < 2; drive++) { 1851 drvp = &chp->ch_drive[drive]; 1852 /* If no drive, skip */ 1853 if ((drvp->drive_flags & DRIVE) == 0) 1854 continue; 1855 /* add timing values, setup DMA if needed */ 1856 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1857 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1858 mode = drvp->PIO_mode; 1859 goto pio; 1860 } 1861 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1862 (drvp->drive_flags & DRIVE_UDMA)) { 1863 /* use Ultra/DMA */ 1864 drvp->drive_flags &= ~DRIVE_DMA; 1865 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1866 APO_UDMA_EN_MTH(chp->channel, drive) | 1867 APO_UDMA_TIME(chp->channel, drive, 1868 apollo_udma_tim[drvp->UDMA_mode]); 1869 /* can use PIO timings, MW DMA unused */ 1870 mode = drvp->PIO_mode; 1871 } else { 1872 /* use Multiword DMA */ 1873 drvp->drive_flags &= ~DRIVE_UDMA; 1874 /* mode = min(pio, dma+2) */ 1875 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1876 mode = drvp->PIO_mode; 1877 else 1878 mode = drvp->DMA_mode + 2; 1879 } 1880 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1881 1882 pio: /* setup PIO mode */ 1883 if (mode <= 2) { 1884 drvp->DMA_mode = 0; 1885 drvp->PIO_mode = 0; 1886 mode = 0; 1887 } else { 1888 drvp->PIO_mode = mode; 1889 drvp->DMA_mode = mode - 2; 1890 } 1891 datatim_reg |= 1892 APO_DATATIM_PULSE(chp->channel, drive, 1893 apollo_pio_set[mode]) | 1894 APO_DATATIM_RECOV(chp->channel, drive, 1895 apollo_pio_rec[mode]); 1896 } 1897 if (idedma_ctl != 0) { 1898 /* Add software bits in status register */ 1899 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1900 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1901 idedma_ctl); 1902 } 1903 pciide_print_modes(cp); 1904 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 1905 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 1906 } 1907 1908 void 1909 cmd_channel_map(pa, sc, channel) 1910 struct pci_attach_args *pa; 1911 struct pciide_softc *sc; 1912 int channel; 1913 { 1914 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1915 bus_size_t cmdsize, ctlsize; 1916 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 1917 int interface = 1918 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1919 1920 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1921 cp->name = PCIIDE_CHANNEL_NAME(channel); 1922 cp->wdc_channel.channel = channel; 1923 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1924 1925 if (channel > 0) { 1926 cp->wdc_channel.ch_queue = 1927 sc->pciide_channels[0].wdc_channel.ch_queue; 1928 } else { 1929 cp->wdc_channel.ch_queue = 1930 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1931 } 1932 if (cp->wdc_channel.ch_queue == NULL) { 1933 printf("%s %s channel: " 1934 "can't allocate memory for command queue", 1935 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1936 return; 1937 } 1938 1939 printf("%s: %s channel %s to %s mode\n", 1940 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1941 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1942 "configured" : "wired", 1943 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1944 "native-PCI" : "compatibility"); 1945 1946 /* 1947 * with a CMD PCI64x, if we get here, the first channel is enabled: 1948 * there's no way to disable the first channel without disabling 1949 * the whole device 1950 */ 1951 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 1952 printf("%s: %s channel ignored (disabled)\n", 1953 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1954 return; 1955 } 1956 1957 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 1958 if (cp->hw_ok == 0) 1959 return; 1960 if (channel == 1) { 1961 if (pciiide_chan_candisable(cp)) { 1962 ctrl &= ~CMD_CTRL_2PORT; 1963 pciide_pci_write(pa->pa_pc, pa->pa_tag, 1964 CMD_CTRL, ctrl); 1965 } 1966 } 1967 pciide_map_compat_intr(pa, cp, channel, interface); 1968 } 1969 1970 int 1971 cmd_pci_intr(arg) 1972 void *arg; 1973 { 1974 struct pciide_softc *sc = arg; 1975 struct pciide_channel *cp; 1976 struct channel_softc *wdc_cp; 1977 int i, rv, crv; 1978 u_int32_t priirq, secirq; 1979 1980 rv = 0; 1981 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 1982 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 1983 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1984 cp = &sc->pciide_channels[i]; 1985 wdc_cp = &cp->wdc_channel; 1986 /* If a compat channel skip. */ 1987 if (cp->compat) 1988 continue; 1989 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 1990 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 1991 crv = wdcintr(wdc_cp); 1992 if (crv == 0) 1993 printf("%s:%d: bogus intr\n", 1994 sc->sc_wdcdev.sc_dev.dv_xname, i); 1995 else 1996 rv = 1; 1997 } 1998 } 1999 return rv; 2000 } 2001 2002 void 2003 cmd_chip_map(sc, pa) 2004 struct pciide_softc *sc; 2005 struct pci_attach_args *pa; 2006 { 2007 int channel; 2008 2009 /* 2010 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2011 * and base adresses registers can be disabled at 2012 * hardware level. In this case, the device is wired 2013 * in compat mode and its first channel is always enabled, 2014 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2015 * In fact, it seems that the first channel of the CMD PCI0640 2016 * can't be disabled. 2017 */ 2018 2019 #ifdef PCIIDE_CMD064x_DISABLE 2020 if (pciide_chipen(sc, pa) == 0) 2021 return; 2022 #endif 2023 2024 printf("%s: hardware does not support DMA\n", 2025 sc->sc_wdcdev.sc_dev.dv_xname); 2026 sc->sc_dma_ok = 0; 2027 2028 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2029 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2030 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 2031 2032 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2033 cmd_channel_map(pa, sc, channel); 2034 } 2035 } 2036 2037 void 2038 cmd0643_6_chip_map(sc, pa) 2039 struct pciide_softc *sc; 2040 struct pci_attach_args *pa; 2041 { 2042 struct pciide_channel *cp; 2043 int channel; 2044 2045 /* 2046 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2047 * and base adresses registers can be disabled at 2048 * hardware level. In this case, the device is wired 2049 * in compat mode and its first channel is always enabled, 2050 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2051 * In fact, it seems that the first channel of the CMD PCI0640 2052 * can't be disabled. 2053 */ 2054 2055 #ifdef PCIIDE_CMD064x_DISABLE 2056 if (pciide_chipen(sc, pa) == 0) 2057 return; 2058 #endif 2059 printf("%s: bus-master DMA support present", 2060 sc->sc_wdcdev.sc_dev.dv_xname); 2061 pciide_mapreg_dma(sc, pa); 2062 printf("\n"); 2063 if (sc->sc_dma_ok) 2064 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2065 2066 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2067 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2068 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2069 WDC_CAPABILITY_MODE; 2070 sc->sc_wdcdev.PIO_cap = 4; 2071 sc->sc_wdcdev.DMA_cap = 2; 2072 sc->sc_wdcdev.set_modes = cmd0643_6_setup_channel; 2073 2074 WDCDEBUG_PRINT(("cmd0643_6_chip_map: old timings reg 0x%x 0x%x\n", 2075 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2076 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2077 DEBUG_PROBE); 2078 2079 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2080 cp = &sc->pciide_channels[channel]; 2081 cmd_channel_map(pa, sc, channel); 2082 if (cp->hw_ok == 0) 2083 continue; 2084 cmd0643_6_setup_channel(&cp->wdc_channel); 2085 } 2086 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2087 WDCDEBUG_PRINT(("cmd0643_6_chip_map: timings reg now 0x%x 0x%x\n", 2088 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2089 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2090 DEBUG_PROBE); 2091 } 2092 2093 void 2094 cmd0643_6_setup_channel(chp) 2095 struct channel_softc *chp; 2096 { 2097 struct ata_drive_datas *drvp; 2098 u_int8_t tim; 2099 u_int32_t idedma_ctl; 2100 int drive; 2101 struct pciide_channel *cp = (struct pciide_channel*)chp; 2102 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2103 2104 idedma_ctl = 0; 2105 /* setup DMA if needed */ 2106 pciide_channel_dma_setup(cp); 2107 2108 for (drive = 0; drive < 2; drive++) { 2109 drvp = &chp->ch_drive[drive]; 2110 /* If no drive, skip */ 2111 if ((drvp->drive_flags & DRIVE) == 0) 2112 continue; 2113 /* add timing values, setup DMA if needed */ 2114 tim = cmd0643_6_data_tim_pio[drvp->PIO_mode]; 2115 if (drvp->drive_flags & DRIVE_DMA) { 2116 /* 2117 * use Multiword DMA. 2118 * Timings will be used for both PIO and DMA, so adjust 2119 * DMA mode if needed 2120 */ 2121 if (drvp->PIO_mode >= 3 && 2122 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2123 drvp->DMA_mode = drvp->PIO_mode - 2; 2124 } 2125 tim = cmd0643_6_data_tim_dma[drvp->DMA_mode]; 2126 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2127 } 2128 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2129 CMD_DATA_TIM(chp->channel, drive), tim); 2130 } 2131 if (idedma_ctl != 0) { 2132 /* Add software bits in status register */ 2133 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2134 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2135 idedma_ctl); 2136 } 2137 pciide_print_modes(cp); 2138 } 2139 2140 void 2141 cy693_chip_map(sc, pa) 2142 struct pciide_softc *sc; 2143 struct pci_attach_args *pa; 2144 { 2145 struct pciide_channel *cp; 2146 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2147 sc->sc_tag, PCI_CLASS_REG)); 2148 int compatchan; 2149 bus_size_t cmdsize, ctlsize; 2150 2151 if (pciide_chipen(sc, pa) == 0) 2152 return; 2153 /* 2154 * this chip has 2 PCI IDE functions, one for primary and one for 2155 * secondary. So we need to call pciide_mapregs_compat() with 2156 * the real channel 2157 */ 2158 if (pa->pa_function == 1) { 2159 compatchan = 0; 2160 } else if (pa->pa_function == 2) { 2161 compatchan = 1; 2162 } else { 2163 printf("%s: unexpected PCI function %d\n", 2164 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2165 cp->hw_ok = 0; 2166 return; 2167 } 2168 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2169 printf("%s: bus-master DMA support present", 2170 sc->sc_wdcdev.sc_dev.dv_xname); 2171 pciide_mapreg_dma(sc, pa); 2172 } else { 2173 printf("%s: hardware does not support DMA", 2174 sc->sc_wdcdev.sc_dev.dv_xname); 2175 sc->sc_dma_ok = 0; 2176 } 2177 printf("\n"); 2178 2179 if (sc->sc_dma_ok) 2180 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2181 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2182 WDC_CAPABILITY_MODE; 2183 sc->sc_wdcdev.PIO_cap = 4; 2184 sc->sc_wdcdev.DMA_cap = 2; 2185 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2186 2187 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2188 sc->sc_wdcdev.nchannels = 1; 2189 2190 /* Only one channel for this chip; if we are here it's enabled */ 2191 cp = &sc->pciide_channels[0]; 2192 sc->wdc_chanarray[0] = &cp->wdc_channel; 2193 cp->name = PCIIDE_CHANNEL_NAME(0); 2194 cp->wdc_channel.channel = 0; 2195 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2196 cp->wdc_channel.ch_queue = 2197 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2198 if (cp->wdc_channel.ch_queue == NULL) { 2199 printf("%s primary channel: " 2200 "can't allocate memory for command queue", 2201 sc->sc_wdcdev.sc_dev.dv_xname); 2202 return; 2203 } 2204 printf("%s: primary channel %s to ", 2205 sc->sc_wdcdev.sc_dev.dv_xname, 2206 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2207 "configured" : "wired"); 2208 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2209 printf("native-PCI"); 2210 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2211 pciide_pci_intr); 2212 } else { 2213 printf("compatibility"); 2214 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2215 &cmdsize, &ctlsize); 2216 } 2217 printf(" mode\n"); 2218 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2219 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2220 wdcattach(&cp->wdc_channel); 2221 if (pciiide_chan_candisable(cp)) { 2222 pci_conf_write(sc->sc_pc, sc->sc_tag, 2223 PCI_COMMAND_STATUS_REG, 0); 2224 } 2225 pciide_map_compat_intr(pa, cp, compatchan, interface); 2226 if (cp->hw_ok == 0) 2227 return; 2228 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2229 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2230 cy693_setup_channel(&cp->wdc_channel); 2231 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2232 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2233 } 2234 2235 void 2236 cy693_setup_channel(chp) 2237 struct channel_softc *chp; 2238 { 2239 struct ata_drive_datas *drvp; 2240 int drive; 2241 u_int32_t cy_cmd_ctrl; 2242 u_int32_t idedma_ctl; 2243 struct pciide_channel *cp = (struct pciide_channel*)chp; 2244 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2245 int dma_mode = -1; 2246 2247 cy_cmd_ctrl = idedma_ctl = 0; 2248 2249 /* setup DMA if needed */ 2250 pciide_channel_dma_setup(cp); 2251 2252 for (drive = 0; drive < 2; drive++) { 2253 drvp = &chp->ch_drive[drive]; 2254 /* If no drive, skip */ 2255 if ((drvp->drive_flags & DRIVE) == 0) 2256 continue; 2257 /* add timing values, setup DMA if needed */ 2258 if (drvp->drive_flags & DRIVE_DMA) { 2259 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2260 /* use Multiword DMA */ 2261 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2262 dma_mode = drvp->DMA_mode; 2263 } 2264 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2265 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2266 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2267 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2268 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2269 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2270 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2271 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2272 } 2273 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2274 chp->ch_drive[0].DMA_mode = dma_mode; 2275 chp->ch_drive[1].DMA_mode = dma_mode; 2276 pciide_print_modes(cp); 2277 if (idedma_ctl != 0) { 2278 /* Add software bits in status register */ 2279 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2280 IDEDMA_CTL, idedma_ctl); 2281 } 2282 } 2283 2284 void 2285 sis_chip_map(sc, pa) 2286 struct pciide_softc *sc; 2287 struct pci_attach_args *pa; 2288 { 2289 struct pciide_channel *cp; 2290 int channel; 2291 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2292 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2293 sc->sc_tag, PCI_CLASS_REG)); 2294 pcireg_t rev = PCI_REVISION(pci_conf_read(sc->sc_pc, 2295 sc->sc_tag, PCI_CLASS_REG)); 2296 bus_size_t cmdsize, ctlsize; 2297 2298 if (pciide_chipen(sc, pa) == 0) 2299 return; 2300 printf("%s: bus-master DMA support present", 2301 sc->sc_wdcdev.sc_dev.dv_xname); 2302 pciide_mapreg_dma(sc, pa); 2303 printf("\n"); 2304 if (sc->sc_dma_ok) { 2305 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2306 if (rev >= 0xd0) 2307 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2308 } 2309 2310 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2311 WDC_CAPABILITY_MODE; 2312 sc->sc_wdcdev.PIO_cap = 4; 2313 sc->sc_wdcdev.DMA_cap = 2; 2314 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2315 sc->sc_wdcdev.UDMA_cap = 2; 2316 sc->sc_wdcdev.set_modes = sis_setup_channel; 2317 2318 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2319 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2320 2321 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2322 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2323 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2324 2325 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2326 cp = &sc->pciide_channels[channel]; 2327 if (pciide_chansetup(sc, channel, interface) == 0) 2328 continue; 2329 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2330 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2331 printf("%s: %s channel ignored (disabled)\n", 2332 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2333 continue; 2334 } 2335 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2336 pciide_pci_intr); 2337 if (cp->hw_ok == 0) 2338 continue; 2339 if (pciiide_chan_candisable(cp)) { 2340 if (channel == 0) 2341 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2342 else 2343 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2344 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2345 sis_ctr0); 2346 } 2347 pciide_map_compat_intr(pa, cp, channel, interface); 2348 if (cp->hw_ok == 0) 2349 continue; 2350 sis_setup_channel(&cp->wdc_channel); 2351 } 2352 } 2353 2354 void 2355 sis_setup_channel(chp) 2356 struct channel_softc *chp; 2357 { 2358 struct ata_drive_datas *drvp; 2359 int drive; 2360 u_int32_t sis_tim; 2361 u_int32_t idedma_ctl; 2362 struct pciide_channel *cp = (struct pciide_channel*)chp; 2363 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2364 2365 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2366 "channel %d 0x%x\n", chp->channel, 2367 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2368 DEBUG_PROBE); 2369 sis_tim = 0; 2370 idedma_ctl = 0; 2371 /* setup DMA if needed */ 2372 pciide_channel_dma_setup(cp); 2373 2374 for (drive = 0; drive < 2; drive++) { 2375 drvp = &chp->ch_drive[drive]; 2376 /* If no drive, skip */ 2377 if ((drvp->drive_flags & DRIVE) == 0) 2378 continue; 2379 /* add timing values, setup DMA if needed */ 2380 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2381 (drvp->drive_flags & DRIVE_UDMA) == 0) 2382 goto pio; 2383 2384 if (drvp->drive_flags & DRIVE_UDMA) { 2385 /* use Ultra/DMA */ 2386 drvp->drive_flags &= ~DRIVE_DMA; 2387 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2388 SIS_TIM_UDMA_TIME_OFF(drive); 2389 sis_tim |= SIS_TIM_UDMA_EN(drive); 2390 } else { 2391 /* 2392 * use Multiword DMA 2393 * Timings will be used for both PIO and DMA, 2394 * so adjust DMA mode if needed 2395 */ 2396 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2397 drvp->PIO_mode = drvp->DMA_mode + 2; 2398 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2399 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2400 drvp->PIO_mode - 2 : 0; 2401 if (drvp->DMA_mode == 0) 2402 drvp->PIO_mode = 0; 2403 } 2404 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2405 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2406 SIS_TIM_ACT_OFF(drive); 2407 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2408 SIS_TIM_REC_OFF(drive); 2409 } 2410 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2411 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2412 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2413 if (idedma_ctl != 0) { 2414 /* Add software bits in status register */ 2415 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2416 IDEDMA_CTL, idedma_ctl); 2417 } 2418 pciide_print_modes(cp); 2419 } 2420 2421 void 2422 acer_chip_map(sc, pa) 2423 struct pciide_softc *sc; 2424 struct pci_attach_args *pa; 2425 { 2426 struct pciide_channel *cp; 2427 int channel; 2428 pcireg_t cr, interface; 2429 bus_size_t cmdsize, ctlsize; 2430 2431 if (pciide_chipen(sc, pa) == 0) 2432 return; 2433 printf("%s: bus-master DMA support present", 2434 sc->sc_wdcdev.sc_dev.dv_xname); 2435 pciide_mapreg_dma(sc, pa); 2436 printf("\n"); 2437 if (sc->sc_dma_ok) 2438 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2439 2440 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2441 WDC_CAPABILITY_MODE; 2442 2443 sc->sc_wdcdev.PIO_cap = 4; 2444 sc->sc_wdcdev.DMA_cap = 2; 2445 sc->sc_wdcdev.UDMA_cap = 2; 2446 sc->sc_wdcdev.set_modes = acer_setup_channel; 2447 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2448 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2449 2450 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2451 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2452 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2453 2454 /* Enable "microsoft register bits" R/W. */ 2455 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2456 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2457 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2458 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2459 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2460 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2461 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2462 ~ACER_CHANSTATUSREGS_RO); 2463 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2464 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2465 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2466 /* Don't use cr, re-read the real register content instead */ 2467 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2468 PCI_CLASS_REG)); 2469 2470 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2471 cp = &sc->pciide_channels[channel]; 2472 if (pciide_chansetup(sc, channel, interface) == 0) 2473 continue; 2474 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2475 printf("%s: %s channel ignored (disabled)\n", 2476 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2477 continue; 2478 } 2479 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2480 acer_pci_intr); 2481 if (cp->hw_ok == 0) 2482 continue; 2483 if (pciiide_chan_candisable(cp)) { 2484 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2485 pci_conf_write(sc->sc_pc, sc->sc_tag, 2486 PCI_CLASS_REG, cr); 2487 } 2488 pciide_map_compat_intr(pa, cp, channel, interface); 2489 acer_setup_channel(&cp->wdc_channel); 2490 } 2491 } 2492 2493 void 2494 acer_setup_channel(chp) 2495 struct channel_softc *chp; 2496 { 2497 struct ata_drive_datas *drvp; 2498 int drive; 2499 u_int32_t acer_fifo_udma; 2500 u_int32_t idedma_ctl; 2501 struct pciide_channel *cp = (struct pciide_channel*)chp; 2502 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2503 2504 idedma_ctl = 0; 2505 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2506 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2507 acer_fifo_udma), DEBUG_PROBE); 2508 /* setup DMA if needed */ 2509 pciide_channel_dma_setup(cp); 2510 2511 for (drive = 0; drive < 2; drive++) { 2512 drvp = &chp->ch_drive[drive]; 2513 /* If no drive, skip */ 2514 if ((drvp->drive_flags & DRIVE) == 0) 2515 continue; 2516 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2517 "channel %d drive %d 0x%x\n", chp->channel, drive, 2518 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2519 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2520 /* clear FIFO/DMA mode */ 2521 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2522 ACER_UDMA_EN(chp->channel, drive) | 2523 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2524 2525 /* add timing values, setup DMA if needed */ 2526 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2527 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2528 acer_fifo_udma |= 2529 ACER_FTH_OPL(chp->channel, drive, 0x1); 2530 goto pio; 2531 } 2532 2533 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2534 if (drvp->drive_flags & DRIVE_UDMA) { 2535 /* use Ultra/DMA */ 2536 drvp->drive_flags &= ~DRIVE_DMA; 2537 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2538 acer_fifo_udma |= 2539 ACER_UDMA_TIM(chp->channel, drive, 2540 acer_udma[drvp->UDMA_mode]); 2541 } else { 2542 /* 2543 * use Multiword DMA 2544 * Timings will be used for both PIO and DMA, 2545 * so adjust DMA mode if needed 2546 */ 2547 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2548 drvp->PIO_mode = drvp->DMA_mode + 2; 2549 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2550 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2551 drvp->PIO_mode - 2 : 0; 2552 if (drvp->DMA_mode == 0) 2553 drvp->PIO_mode = 0; 2554 } 2555 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2556 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2557 ACER_IDETIM(chp->channel, drive), 2558 acer_pio[drvp->PIO_mode]); 2559 } 2560 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2561 acer_fifo_udma), DEBUG_PROBE); 2562 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2563 if (idedma_ctl != 0) { 2564 /* Add software bits in status register */ 2565 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2566 IDEDMA_CTL, idedma_ctl); 2567 } 2568 pciide_print_modes(cp); 2569 } 2570 2571 int 2572 acer_pci_intr(arg) 2573 void *arg; 2574 { 2575 struct pciide_softc *sc = arg; 2576 struct pciide_channel *cp; 2577 struct channel_softc *wdc_cp; 2578 int i, rv, crv; 2579 u_int32_t chids; 2580 2581 rv = 0; 2582 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2583 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2584 cp = &sc->pciide_channels[i]; 2585 wdc_cp = &cp->wdc_channel; 2586 /* If a compat channel skip. */ 2587 if (cp->compat) 2588 continue; 2589 if (chids & ACER_CHIDS_INT(i)) { 2590 crv = wdcintr(wdc_cp); 2591 if (crv == 0) 2592 printf("%s:%d: bogus intr\n", 2593 sc->sc_wdcdev.sc_dev.dv_xname, i); 2594 else 2595 rv = 1; 2596 } 2597 } 2598 return rv; 2599 } 2600 2601 /* A macro to test product */ 2602 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 2603 2604 void 2605 pdc202xx_chip_map(sc, pa) 2606 struct pciide_softc *sc; 2607 struct pci_attach_args *pa; 2608 { 2609 struct pciide_channel *cp; 2610 int channel; 2611 pcireg_t interface, st, mode; 2612 bus_size_t cmdsize, ctlsize; 2613 2614 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2615 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 2616 DEBUG_PROBE); 2617 if (pciide_chipen(sc, pa) == 0) 2618 return; 2619 2620 /* turn off RAID mode */ 2621 st &= ~PDC2xx_STATE_IDERAID; 2622 2623 /* 2624 * can't rely on the PCI_CLASS_REG content if the chip was in raid 2625 * mode. We have to fake interface 2626 */ 2627 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 2628 if (st & PDC2xx_STATE_NATIVE) 2629 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2630 2631 printf("%s: bus-master DMA support present", 2632 sc->sc_wdcdev.sc_dev.dv_xname); 2633 pciide_mapreg_dma(sc, pa); 2634 printf("\n"); 2635 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2636 WDC_CAPABILITY_MODE; 2637 if (sc->sc_dma_ok) 2638 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2639 sc->sc_wdcdev.PIO_cap = 4; 2640 sc->sc_wdcdev.DMA_cap = 2; 2641 if (PDC_IS_262(sc)) 2642 sc->sc_wdcdev.UDMA_cap = 4; 2643 else 2644 sc->sc_wdcdev.UDMA_cap = 2; 2645 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 2646 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2647 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2648 2649 /* setup failsafe defaults */ 2650 mode = 0; 2651 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 2652 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 2653 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 2654 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 2655 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2656 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 2657 "initial timings 0x%x, now 0x%x\n", channel, 2658 pci_conf_read(sc->sc_pc, sc->sc_tag, 2659 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 2660 DEBUG_PROBE); 2661 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 2662 mode | PDC2xx_TIM_IORDYp); 2663 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 2664 "initial timings 0x%x, now 0x%x\n", channel, 2665 pci_conf_read(sc->sc_pc, sc->sc_tag, 2666 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 2667 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 2668 mode); 2669 } 2670 2671 mode = PDC2xx_SCR_DMA; 2672 if (PDC_IS_262(sc)) { 2673 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 2674 } else { 2675 /* the BIOS set it up this way */ 2676 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 2677 } 2678 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 2679 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 2680 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 2681 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 2682 DEBUG_PROBE); 2683 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 2684 2685 /* controller initial state register is OK even without BIOS */ 2686 /* Set DMA mode to IDE DMA compatibility */ 2687 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 2688 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 2689 DEBUG_PROBE); 2690 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 2691 mode | 0x1); 2692 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 2693 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 2694 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 2695 mode | 0x1); 2696 2697 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2698 cp = &sc->pciide_channels[channel]; 2699 if (pciide_chansetup(sc, channel, interface) == 0) 2700 continue; 2701 if ((st & (PDC_IS_262(sc) ? 2702 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 2703 printf("%s: %s channel ignored (disabled)\n", 2704 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2705 continue; 2706 } 2707 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2708 pdc202xx_pci_intr); 2709 if (cp->hw_ok == 0) 2710 continue; 2711 if (pciiide_chan_candisable(cp)) 2712 st &= ~(PDC_IS_262(sc) ? 2713 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 2714 pciide_map_compat_intr(pa, cp, channel, interface); 2715 pdc202xx_setup_channel(&cp->wdc_channel); 2716 } 2717 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 2718 DEBUG_PROBE); 2719 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 2720 return; 2721 } 2722 2723 void 2724 pdc202xx_setup_channel(chp) 2725 struct channel_softc *chp; 2726 { 2727 struct ata_drive_datas *drvp; 2728 int drive; 2729 pcireg_t mode, st; 2730 u_int32_t idedma_ctl, scr, atapi; 2731 struct pciide_channel *cp = (struct pciide_channel*)chp; 2732 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2733 int channel = chp->channel; 2734 2735 /* setup DMA if needed */ 2736 pciide_channel_dma_setup(cp); 2737 2738 idedma_ctl = 0; 2739 2740 /* Per channel settings */ 2741 if (PDC_IS_262(sc)) { 2742 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2743 PDC262_U66); 2744 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2745 /* Trimm UDMA mode */ 2746 if ((st & PDC262_STATE_80P(channel)) == 0 || 2747 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 2748 chp->ch_drive[0].UDMA_mode <= 2) || 2749 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 2750 chp->ch_drive[1].UDMA_mode <= 2)) { 2751 if (chp->ch_drive[0].UDMA_mode > 2) 2752 chp->ch_drive[0].UDMA_mode = 2; 2753 if (chp->ch_drive[1].UDMA_mode > 2) 2754 chp->ch_drive[1].UDMA_mode = 2; 2755 } 2756 /* Set U66 if needed */ 2757 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 2758 chp->ch_drive[0].UDMA_mode > 2) || 2759 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 2760 chp->ch_drive[1].UDMA_mode > 2)) 2761 scr |= PDC262_U66_EN(channel); 2762 else 2763 scr &= ~PDC262_U66_EN(channel); 2764 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2765 PDC262_U66, scr); 2766 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 2767 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 2768 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2769 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 2770 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 2771 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 2772 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2773 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 2774 atapi = 0; 2775 else 2776 atapi = PDC262_ATAPI_UDMA; 2777 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 2778 PDC262_ATAPI(channel), atapi); 2779 } 2780 } 2781 for (drive = 0; drive < 2; drive++) { 2782 drvp = &chp->ch_drive[drive]; 2783 /* If no drive, skip */ 2784 if ((drvp->drive_flags & DRIVE) == 0) 2785 continue; 2786 mode = 0; 2787 if (drvp->drive_flags & DRIVE_UDMA) { 2788 mode = PDC2xx_TIM_SET_MB(mode, 2789 pdc2xx_udma_mb[drvp->UDMA_mode]); 2790 mode = PDC2xx_TIM_SET_MC(mode, 2791 pdc2xx_udma_mc[drvp->UDMA_mode]); 2792 drvp->drive_flags &= ~DRIVE_DMA; 2793 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2794 } else if (drvp->drive_flags & DRIVE_DMA) { 2795 mode = PDC2xx_TIM_SET_MB(mode, 2796 pdc2xx_dma_mb[drvp->DMA_mode]); 2797 mode = PDC2xx_TIM_SET_MC(mode, 2798 pdc2xx_dma_mc[drvp->DMA_mode]); 2799 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2800 } else { 2801 mode = PDC2xx_TIM_SET_MB(mode, 2802 pdc2xx_dma_mb[0]); 2803 mode = PDC2xx_TIM_SET_MC(mode, 2804 pdc2xx_dma_mc[0]); 2805 } 2806 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 2807 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 2808 if (drvp->drive_flags & DRIVE_ATA) 2809 mode |= PDC2xx_TIM_PRE; 2810 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 2811 if (drvp->PIO_mode >= 3) { 2812 mode |= PDC2xx_TIM_IORDY; 2813 if (drive == 0) 2814 mode |= PDC2xx_TIM_IORDYp; 2815 } 2816 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 2817 "timings 0x%x\n", 2818 sc->sc_wdcdev.sc_dev.dv_xname, 2819 chp->channel, drive, mode), DEBUG_PROBE); 2820 pci_conf_write(sc->sc_pc, sc->sc_tag, 2821 PDC2xx_TIM(chp->channel, drive), mode); 2822 } 2823 if (idedma_ctl != 0) { 2824 /* Add software bits in status register */ 2825 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2826 IDEDMA_CTL, idedma_ctl); 2827 } 2828 pciide_print_modes(cp); 2829 } 2830 2831 int 2832 pdc202xx_pci_intr(arg) 2833 void *arg; 2834 { 2835 struct pciide_softc *sc = arg; 2836 struct pciide_channel *cp; 2837 struct channel_softc *wdc_cp; 2838 int i, rv, crv; 2839 u_int32_t scr; 2840 2841 rv = 0; 2842 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 2843 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2844 cp = &sc->pciide_channels[i]; 2845 wdc_cp = &cp->wdc_channel; 2846 /* If a compat channel skip. */ 2847 if (cp->compat) 2848 continue; 2849 if (scr & PDC2xx_SCR_INT(i)) { 2850 crv = wdcintr(wdc_cp); 2851 if (crv == 0) 2852 printf("%s:%d: bogus intr\n", 2853 sc->sc_wdcdev.sc_dev.dv_xname, i); 2854 else 2855 rv = 1; 2856 } 2857 } 2858 return rv; 2859 } 2860
Indexes created Thu Oct 02 10:09:58 GMT 2025