pciide.c revision 1.54
1 /* $NetBSD: pciide.c,v 1.54 2000/03/09 20:26:31 soren Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 38 /* 39 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by Christopher G. Demetriou 52 * for the NetBSD Project. 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * PCI IDE controller driver. 70 * 71 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 72 * sys/dev/pci/ppb.c, revision 1.16). 73 * 74 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 75 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 76 * 5/16/94" from the PCI SIG. 77 * 78 */ 79 80 #ifndef WDCDEBUG 81 #define WDCDEBUG 82 #endif 83 84 #define DEBUG_DMA 0x01 85 #define DEBUG_XFERS 0x02 86 #define DEBUG_FUNCS 0x08 87 #define DEBUG_PROBE 0x10 88 #ifdef WDCDEBUG 89 int wdcdebug_pciide_mask = 0; 90 #define WDCDEBUG_PRINT(args, level) \ 91 if (wdcdebug_pciide_mask & (level)) printf args 92 #else 93 #define WDCDEBUG_PRINT(args, level) 94 #endif 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/device.h> 98 #include <sys/malloc.h> 99 100 #include <machine/endian.h> 101 102 #include <vm/vm.h> 103 #include <vm/vm_param.h> 104 #include <vm/vm_kern.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 #include <dev/pci/pcidevs.h> 109 #include <dev/pci/pciidereg.h> 110 #include <dev/pci/pciidevar.h> 111 #include <dev/pci/pciide_piix_reg.h> 112 #include <dev/pci/pciide_amd_reg.h> 113 #include <dev/pci/pciide_apollo_reg.h> 114 #include <dev/pci/pciide_cmd_reg.h> 115 #include <dev/pci/pciide_cy693_reg.h> 116 #include <dev/pci/pciide_sis_reg.h> 117 #include <dev/pci/pciide_acer_reg.h> 118 #include <dev/pci/pciide_pdc202xx_reg.h> 119 120 /* inlines for reading/writing 8-bit PCI registers */ 121 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 122 int)); 123 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 124 int, u_int8_t)); 125 126 static __inline u_int8_t 127 pciide_pci_read(pc, pa, reg) 128 pci_chipset_tag_t pc; 129 pcitag_t pa; 130 int reg; 131 { 132 133 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 134 ((reg & 0x03) * 8) & 0xff); 135 } 136 137 static __inline void 138 pciide_pci_write(pc, pa, reg, val) 139 pci_chipset_tag_t pc; 140 pcitag_t pa; 141 int reg; 142 u_int8_t val; 143 { 144 pcireg_t pcival; 145 146 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 147 pcival &= ~(0xff << ((reg & 0x03) * 8)); 148 pcival |= (val << ((reg & 0x03) * 8)); 149 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 150 } 151 152 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 153 154 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 155 void piix_setup_channel __P((struct channel_softc*)); 156 void piix3_4_setup_channel __P((struct channel_softc*)); 157 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 158 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 159 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 160 161 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 162 void amd756_setup_channel __P((struct channel_softc*)); 163 164 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void apollo_setup_channel __P((struct channel_softc*)); 166 167 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void cmd0643_6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 169 void cmd0643_6_setup_channel __P((struct channel_softc*)); 170 void cmd_channel_map __P((struct pci_attach_args *, 171 struct pciide_softc *, int)); 172 int cmd_pci_intr __P((void *)); 173 174 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cy693_setup_channel __P((struct channel_softc*)); 176 177 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void sis_setup_channel __P((struct channel_softc*)); 179 180 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void acer_setup_channel __P((struct channel_softc*)); 182 int acer_pci_intr __P((void *)); 183 184 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void pdc202xx_setup_channel __P((struct channel_softc*)); 186 int pdc202xx_pci_intr __P((void *)); 187 188 void pciide_channel_dma_setup __P((struct pciide_channel *)); 189 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 190 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 191 void pciide_dma_start __P((void*, int, int, int)); 192 int pciide_dma_finish __P((void*, int, int, int)); 193 void pciide_print_modes __P((struct pciide_channel *)); 194 195 struct pciide_product_desc { 196 u_int32_t ide_product; 197 int ide_flags; 198 const char *ide_name; 199 /* map and setup chip, probe drives */ 200 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 201 }; 202 203 /* Flags for ide_flags */ 204 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 205 206 /* Default product description for devices not known from this controller */ 207 const struct pciide_product_desc default_product_desc = { 208 0, 209 0, 210 "Generic PCI IDE controller", 211 default_chip_map, 212 }; 213 214 const struct pciide_product_desc pciide_intel_products[] = { 215 { PCI_PRODUCT_INTEL_82092AA, 216 0, 217 "Intel 82092AA IDE controller", 218 default_chip_map, 219 }, 220 { PCI_PRODUCT_INTEL_82371FB_IDE, 221 0, 222 "Intel 82371FB IDE controller (PIIX)", 223 piix_chip_map, 224 }, 225 { PCI_PRODUCT_INTEL_82371SB_IDE, 226 0, 227 "Intel 82371SB IDE Interface (PIIX3)", 228 piix_chip_map, 229 }, 230 { PCI_PRODUCT_INTEL_82371AB_IDE, 231 0, 232 "Intel 82371AB IDE controller (PIIX4)", 233 piix_chip_map, 234 }, 235 { PCI_PRODUCT_INTEL_82801AA_IDE, 236 0, 237 "Intel 82801AA IDE Controller (ICH)", 238 piix_chip_map, 239 }, 240 { PCI_PRODUCT_INTEL_82801AB_IDE, 241 0, 242 "Intel 82801AB IDE Controller (ICH0)", 243 piix_chip_map, 244 }, 245 { 0, 246 0, 247 NULL, 248 } 249 }; 250 251 const struct pciide_product_desc pciide_amd_products[] = { 252 { PCI_PRODUCT_AMD_PBC756_IDE, 253 0, 254 "Advanced Micro Devices AMD756 IDE Controller", 255 amd756_chip_map 256 }, 257 { 0, 258 0, 259 NULL, 260 } 261 }; 262 263 const struct pciide_product_desc pciide_cmd_products[] = { 264 { PCI_PRODUCT_CMDTECH_640, 265 0, 266 "CMD Technology PCI0640", 267 cmd_chip_map 268 }, 269 { PCI_PRODUCT_CMDTECH_643, 270 0, 271 "CMD Technology PCI0643", 272 cmd0643_6_chip_map, 273 }, 274 { PCI_PRODUCT_CMDTECH_646, 275 0, 276 "CMD Technology PCI0646", 277 cmd0643_6_chip_map, 278 }, 279 { 0, 280 0, 281 NULL, 282 } 283 }; 284 285 const struct pciide_product_desc pciide_via_products[] = { 286 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 287 0, 288 "VIA Technologies VT82C586 (Apollo VP) IDE Controller", 289 apollo_chip_map, 290 }, 291 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 292 0, 293 "VIA Technologies VT82C586A IDE Controller", 294 apollo_chip_map, 295 }, 296 { 0, 297 0, 298 NULL, 299 } 300 }; 301 302 const struct pciide_product_desc pciide_cypress_products[] = { 303 { PCI_PRODUCT_CONTAQ_82C693, 304 0, 305 "Contaq Microsystems CY82C693 IDE Controller", 306 cy693_chip_map, 307 }, 308 { 0, 309 0, 310 NULL, 311 } 312 }; 313 314 const struct pciide_product_desc pciide_sis_products[] = { 315 { PCI_PRODUCT_SIS_5597_IDE, 316 0, 317 "Silicon Integrated System 5597/5598 IDE controller", 318 sis_chip_map, 319 }, 320 { 0, 321 0, 322 NULL, 323 } 324 }; 325 326 const struct pciide_product_desc pciide_acer_products[] = { 327 { PCI_PRODUCT_ALI_M5229, 328 0, 329 "Acer Labs M5229 UDMA IDE Controller", 330 acer_chip_map, 331 }, 332 { 0, 333 0, 334 NULL, 335 } 336 }; 337 338 const struct pciide_product_desc pciide_promise_products[] = { 339 { PCI_PRODUCT_PROMISE_ULTRA33, 340 IDE_PCI_CLASS_OVERRIDE, 341 "Promise Ultra33/ATA Bus Master IDE Accelerator", 342 pdc202xx_chip_map, 343 }, 344 { PCI_PRODUCT_PROMISE_ULTRA66, 345 IDE_PCI_CLASS_OVERRIDE, 346 "Promise Ultra66/ATA Bus Master IDE Accelerator", 347 pdc202xx_chip_map, 348 }, 349 { 0, 350 0, 351 NULL, 352 } 353 }; 354 355 struct pciide_vendor_desc { 356 u_int32_t ide_vendor; 357 const struct pciide_product_desc *ide_products; 358 }; 359 360 const struct pciide_vendor_desc pciide_vendors[] = { 361 { PCI_VENDOR_INTEL, pciide_intel_products }, 362 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 363 { PCI_VENDOR_VIATECH, pciide_via_products }, 364 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 365 { PCI_VENDOR_SIS, pciide_sis_products }, 366 { PCI_VENDOR_ALI, pciide_acer_products }, 367 { PCI_VENDOR_PROMISE, pciide_promise_products }, 368 { PCI_VENDOR_AMD, pciide_amd_products }, 369 { 0, NULL } 370 }; 371 372 /* options passed via the 'flags' config keyword */ 373 #define PCIIDE_OPTIONS_DMA 0x01 374 375 int pciide_match __P((struct device *, struct cfdata *, void *)); 376 void pciide_attach __P((struct device *, struct device *, void *)); 377 378 struct cfattach pciide_ca = { 379 sizeof(struct pciide_softc), pciide_match, pciide_attach 380 }; 381 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 382 int pciide_mapregs_compat __P(( struct pci_attach_args *, 383 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 384 int pciide_mapregs_native __P((struct pci_attach_args *, 385 struct pciide_channel *, bus_size_t *, bus_size_t *, 386 int (*pci_intr) __P((void *)))); 387 void pciide_mapreg_dma __P((struct pciide_softc *, 388 struct pci_attach_args *)); 389 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 390 void pciide_mapchan __P((struct pci_attach_args *, 391 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 392 int (*pci_intr) __P((void *)))); 393 int pciiide_chan_candisable __P((struct pciide_channel *)); 394 void pciide_map_compat_intr __P(( struct pci_attach_args *, 395 struct pciide_channel *, int, int)); 396 int pciide_print __P((void *, const char *pnp)); 397 int pciide_compat_intr __P((void *)); 398 int pciide_pci_intr __P((void *)); 399 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 400 401 const struct pciide_product_desc * 402 pciide_lookup_product(id) 403 u_int32_t id; 404 { 405 const struct pciide_product_desc *pp; 406 const struct pciide_vendor_desc *vp; 407 408 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 409 if (PCI_VENDOR(id) == vp->ide_vendor) 410 break; 411 412 if ((pp = vp->ide_products) == NULL) 413 return NULL; 414 415 for (; pp->ide_name != NULL; pp++) 416 if (PCI_PRODUCT(id) == pp->ide_product) 417 break; 418 419 if (pp->ide_name == NULL) 420 return NULL; 421 return pp; 422 } 423 424 int 425 pciide_match(parent, match, aux) 426 struct device *parent; 427 struct cfdata *match; 428 void *aux; 429 { 430 struct pci_attach_args *pa = aux; 431 const struct pciide_product_desc *pp; 432 433 /* 434 * Check the ID register to see that it's a PCI IDE controller. 435 * If it is, we assume that we can deal with it; it _should_ 436 * work in a standardized way... 437 */ 438 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 439 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 440 return (1); 441 } 442 443 /* 444 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 445 * controllers. Let see if we can deal with it anyway. 446 */ 447 pp = pciide_lookup_product(pa->pa_id); 448 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 449 return (1); 450 } 451 452 return (0); 453 } 454 455 void 456 pciide_attach(parent, self, aux) 457 struct device *parent, *self; 458 void *aux; 459 { 460 struct pci_attach_args *pa = aux; 461 pci_chipset_tag_t pc = pa->pa_pc; 462 pcitag_t tag = pa->pa_tag; 463 struct pciide_softc *sc = (struct pciide_softc *)self; 464 pcireg_t csr; 465 char devinfo[256]; 466 467 sc->sc_pp = pciide_lookup_product(pa->pa_id); 468 if (sc->sc_pp == NULL) { 469 sc->sc_pp = &default_product_desc; 470 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 471 printf(": %s (rev. 0x%02x)\n", devinfo, 472 PCI_REVISION(pa->pa_class)); 473 } else { 474 printf(": %s\n", sc->sc_pp->ide_name); 475 } 476 sc->sc_pc = pa->pa_pc; 477 sc->sc_tag = pa->pa_tag; 478 #ifdef WDCDEBUG 479 if (wdcdebug_pciide_mask & DEBUG_PROBE) 480 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 481 #endif 482 483 sc->sc_pp->chip_map(sc, pa); 484 485 if (sc->sc_dma_ok) { 486 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 487 csr |= PCI_COMMAND_MASTER_ENABLE; 488 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 489 } 490 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 491 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 492 } 493 494 /* tell wether the chip is enabled or not */ 495 int 496 pciide_chipen(sc, pa) 497 struct pciide_softc *sc; 498 struct pci_attach_args *pa; 499 { 500 pcireg_t csr; 501 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 502 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 503 PCI_COMMAND_STATUS_REG); 504 printf("%s: device disabled (at %s)\n", 505 sc->sc_wdcdev.sc_dev.dv_xname, 506 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 507 "device" : "bridge"); 508 return 0; 509 } 510 return 1; 511 } 512 513 int 514 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 515 struct pci_attach_args *pa; 516 struct pciide_channel *cp; 517 int compatchan; 518 bus_size_t *cmdsizep, *ctlsizep; 519 { 520 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 521 struct channel_softc *wdc_cp = &cp->wdc_channel; 522 523 cp->compat = 1; 524 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 525 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 526 527 wdc_cp->cmd_iot = pa->pa_iot; 528 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 529 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 530 printf("%s: couldn't map %s channel cmd regs\n", 531 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 532 return (0); 533 } 534 535 wdc_cp->ctl_iot = pa->pa_iot; 536 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 537 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 538 printf("%s: couldn't map %s channel ctl regs\n", 539 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 540 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 541 PCIIDE_COMPAT_CMD_SIZE); 542 return (0); 543 } 544 545 return (1); 546 } 547 548 int 549 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 550 struct pci_attach_args * pa; 551 struct pciide_channel *cp; 552 bus_size_t *cmdsizep, *ctlsizep; 553 int (*pci_intr) __P((void *)); 554 { 555 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 556 struct channel_softc *wdc_cp = &cp->wdc_channel; 557 const char *intrstr; 558 pci_intr_handle_t intrhandle; 559 560 cp->compat = 0; 561 562 if (sc->sc_pci_ih == NULL) { 563 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 564 pa->pa_intrline, &intrhandle) != 0) { 565 printf("%s: couldn't map native-PCI interrupt\n", 566 sc->sc_wdcdev.sc_dev.dv_xname); 567 return 0; 568 } 569 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 570 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 571 intrhandle, IPL_BIO, pci_intr, sc); 572 if (sc->sc_pci_ih != NULL) { 573 printf("%s: using %s for native-PCI interrupt\n", 574 sc->sc_wdcdev.sc_dev.dv_xname, 575 intrstr ? intrstr : "unknown interrupt"); 576 } else { 577 printf("%s: couldn't establish native-PCI interrupt", 578 sc->sc_wdcdev.sc_dev.dv_xname); 579 if (intrstr != NULL) 580 printf(" at %s", intrstr); 581 printf("\n"); 582 return 0; 583 } 584 } 585 cp->ih = sc->sc_pci_ih; 586 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 587 PCI_MAPREG_TYPE_IO, 0, 588 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 589 printf("%s: couldn't map %s channel cmd regs\n", 590 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 591 return 0; 592 } 593 594 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 595 PCI_MAPREG_TYPE_IO, 0, 596 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 597 printf("%s: couldn't map %s channel ctl regs\n", 598 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 599 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 600 return 0; 601 } 602 return (1); 603 } 604 605 void 606 pciide_mapreg_dma(sc, pa) 607 struct pciide_softc *sc; 608 struct pci_attach_args *pa; 609 { 610 /* 611 * Map DMA registers 612 * 613 * Note that sc_dma_ok is the right variable to test to see if 614 * DMA can be done. If the interface doesn't support DMA, 615 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 616 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 617 * non-zero if the interface supports DMA and the registers 618 * could be mapped. 619 * 620 * XXX Note that despite the fact that the Bus Master IDE specs 621 * XXX say that "The bus master IDE function uses 16 bytes of IO 622 * XXX space," some controllers (at least the United 623 * XXX Microelectronics UM8886BF) place it in memory space. 624 * XXX eventually, we should probably read the register and check 625 * XXX which type it is. Either that or 'quirk' certain devices. 626 */ 627 sc->sc_dma_ok = (pci_mapreg_map(pa, 628 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0, 629 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 630 sc->sc_dmat = pa->pa_dmat; 631 if (sc->sc_dma_ok == 0) { 632 printf(", but unused (couldn't map registers)"); 633 } else { 634 sc->sc_wdcdev.dma_arg = sc; 635 sc->sc_wdcdev.dma_init = pciide_dma_init; 636 sc->sc_wdcdev.dma_start = pciide_dma_start; 637 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 638 } 639 } 640 int 641 pciide_compat_intr(arg) 642 void *arg; 643 { 644 struct pciide_channel *cp = arg; 645 646 #ifdef DIAGNOSTIC 647 /* should only be called for a compat channel */ 648 if (cp->compat == 0) 649 panic("pciide compat intr called for non-compat chan %p\n", cp); 650 #endif 651 return (wdcintr(&cp->wdc_channel)); 652 } 653 654 int 655 pciide_pci_intr(arg) 656 void *arg; 657 { 658 struct pciide_softc *sc = arg; 659 struct pciide_channel *cp; 660 struct channel_softc *wdc_cp; 661 int i, rv, crv; 662 663 rv = 0; 664 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 665 cp = &sc->pciide_channels[i]; 666 wdc_cp = &cp->wdc_channel; 667 668 /* If a compat channel skip. */ 669 if (cp->compat) 670 continue; 671 /* if this channel not waiting for intr, skip */ 672 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 673 continue; 674 675 crv = wdcintr(wdc_cp); 676 if (crv == 0) 677 ; /* leave rv alone */ 678 else if (crv == 1) 679 rv = 1; /* claim the intr */ 680 else if (rv == 0) /* crv should be -1 in this case */ 681 rv = crv; /* if we've done no better, take it */ 682 } 683 return (rv); 684 } 685 686 void 687 pciide_channel_dma_setup(cp) 688 struct pciide_channel *cp; 689 { 690 int drive; 691 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 692 struct ata_drive_datas *drvp; 693 694 for (drive = 0; drive < 2; drive++) { 695 drvp = &cp->wdc_channel.ch_drive[drive]; 696 /* If no drive, skip */ 697 if ((drvp->drive_flags & DRIVE) == 0) 698 continue; 699 /* setup DMA if needed */ 700 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 701 (drvp->drive_flags & DRIVE_UDMA) == 0) || 702 sc->sc_dma_ok == 0) { 703 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 704 continue; 705 } 706 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 707 != 0) { 708 /* Abort DMA setup */ 709 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 710 continue; 711 } 712 } 713 } 714 715 int 716 pciide_dma_table_setup(sc, channel, drive) 717 struct pciide_softc *sc; 718 int channel, drive; 719 { 720 bus_dma_segment_t seg; 721 int error, rseg; 722 const bus_size_t dma_table_size = 723 sizeof(struct idedma_table) * NIDEDMA_TABLES; 724 struct pciide_dma_maps *dma_maps = 725 &sc->pciide_channels[channel].dma_maps[drive]; 726 727 /* If table was already allocated, just return */ 728 if (dma_maps->dma_table) 729 return 0; 730 731 /* Allocate memory for the DMA tables and map it */ 732 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 733 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 734 BUS_DMA_NOWAIT)) != 0) { 735 printf("%s:%d: unable to allocate table DMA for " 736 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 737 channel, drive, error); 738 return error; 739 } 740 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 741 dma_table_size, 742 (caddr_t *)&dma_maps->dma_table, 743 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 744 printf("%s:%d: unable to map table DMA for" 745 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 746 channel, drive, error); 747 return error; 748 } 749 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 750 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 751 seg.ds_addr), DEBUG_PROBE); 752 753 /* Create and load table DMA map for this disk */ 754 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 755 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 756 &dma_maps->dmamap_table)) != 0) { 757 printf("%s:%d: unable to create table DMA map for " 758 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 759 channel, drive, error); 760 return error; 761 } 762 if ((error = bus_dmamap_load(sc->sc_dmat, 763 dma_maps->dmamap_table, 764 dma_maps->dma_table, 765 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 766 printf("%s:%d: unable to load table DMA map for " 767 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 768 channel, drive, error); 769 return error; 770 } 771 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 772 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 773 /* Create a xfer DMA map for this drive */ 774 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 775 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 776 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 777 &dma_maps->dmamap_xfer)) != 0) { 778 printf("%s:%d: unable to create xfer DMA map for " 779 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 780 channel, drive, error); 781 return error; 782 } 783 return 0; 784 } 785 786 int 787 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 788 void *v; 789 int channel, drive; 790 void *databuf; 791 size_t datalen; 792 int flags; 793 { 794 struct pciide_softc *sc = v; 795 int error, seg; 796 struct pciide_dma_maps *dma_maps = 797 &sc->pciide_channels[channel].dma_maps[drive]; 798 799 error = bus_dmamap_load(sc->sc_dmat, 800 dma_maps->dmamap_xfer, 801 databuf, datalen, NULL, BUS_DMA_NOWAIT); 802 if (error) { 803 printf("%s:%d: unable to load xfer DMA map for" 804 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 805 channel, drive, error); 806 return error; 807 } 808 809 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 810 dma_maps->dmamap_xfer->dm_mapsize, 811 (flags & WDC_DMA_READ) ? 812 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 813 814 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 815 #ifdef DIAGNOSTIC 816 /* A segment must not cross a 64k boundary */ 817 { 818 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 819 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 820 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 821 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 822 printf("pciide_dma: segment %d physical addr 0x%lx" 823 " len 0x%lx not properly aligned\n", 824 seg, phys, len); 825 panic("pciide_dma: buf align"); 826 } 827 } 828 #endif 829 dma_maps->dma_table[seg].base_addr = 830 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 831 dma_maps->dma_table[seg].byte_count = 832 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 833 IDEDMA_BYTE_COUNT_MASK); 834 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 835 seg, le32toh(dma_maps->dma_table[seg].byte_count), 836 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 837 838 } 839 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 840 htole32(IDEDMA_BYTE_COUNT_EOT); 841 842 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 843 dma_maps->dmamap_table->dm_mapsize, 844 BUS_DMASYNC_PREWRITE); 845 846 /* Maps are ready. Start DMA function */ 847 #ifdef DIAGNOSTIC 848 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 849 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 850 dma_maps->dmamap_table->dm_segs[0].ds_addr); 851 panic("pciide_dma_init: table align"); 852 } 853 #endif 854 855 /* Clear status bits */ 856 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 857 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 858 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 859 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 860 /* Write table addr */ 861 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 862 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 863 dma_maps->dmamap_table->dm_segs[0].ds_addr); 864 /* set read/write */ 865 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 866 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 867 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 868 return 0; 869 } 870 871 void 872 pciide_dma_start(v, channel, drive, flags) 873 void *v; 874 int channel, drive, flags; 875 { 876 struct pciide_softc *sc = v; 877 878 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 879 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 880 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 881 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 882 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 883 } 884 885 int 886 pciide_dma_finish(v, channel, drive, flags) 887 void *v; 888 int channel, drive; 889 int flags; 890 { 891 struct pciide_softc *sc = v; 892 u_int8_t status; 893 struct pciide_dma_maps *dma_maps = 894 &sc->pciide_channels[channel].dma_maps[drive]; 895 896 /* Unload the map of the data buffer */ 897 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 898 dma_maps->dmamap_xfer->dm_mapsize, 899 (flags & WDC_DMA_READ) ? 900 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 901 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 902 903 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 904 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 905 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 906 DEBUG_XFERS); 907 908 /* stop DMA channel */ 909 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 910 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 911 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 912 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 913 914 /* Clear status bits */ 915 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 916 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 917 status); 918 919 if ((status & IDEDMA_CTL_ERR) != 0) { 920 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 921 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 922 return -1; 923 } 924 925 if ((flags & WDC_DMA_POLL) == 0 && (status & IDEDMA_CTL_INTR) == 0) { 926 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 927 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 928 drive, status); 929 return -1; 930 } 931 932 if ((status & IDEDMA_CTL_ACT) != 0) { 933 /* data underrun, may be a valid condition for ATAPI */ 934 return 1; 935 } 936 return 0; 937 } 938 939 /* some common code used by several chip_map */ 940 int 941 pciide_chansetup(sc, channel, interface) 942 struct pciide_softc *sc; 943 int channel; 944 pcireg_t interface; 945 { 946 struct pciide_channel *cp = &sc->pciide_channels[channel]; 947 sc->wdc_chanarray[channel] = &cp->wdc_channel; 948 cp->name = PCIIDE_CHANNEL_NAME(channel); 949 cp->wdc_channel.channel = channel; 950 cp->wdc_channel.wdc = &sc->sc_wdcdev; 951 cp->wdc_channel.ch_queue = 952 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 953 if (cp->wdc_channel.ch_queue == NULL) { 954 printf("%s %s channel: " 955 "can't allocate memory for command queue", 956 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 957 return 0; 958 } 959 printf("%s: %s channel %s to %s mode\n", 960 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 961 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 962 "configured" : "wired", 963 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 964 "native-PCI" : "compatibility"); 965 return 1; 966 } 967 968 /* some common code used by several chip channel_map */ 969 void 970 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 971 struct pci_attach_args *pa; 972 struct pciide_channel *cp; 973 pcireg_t interface; 974 bus_size_t *cmdsizep, *ctlsizep; 975 int (*pci_intr) __P((void *)); 976 { 977 struct channel_softc *wdc_cp = &cp->wdc_channel; 978 979 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 980 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 981 pci_intr); 982 else 983 cp->hw_ok = pciide_mapregs_compat(pa, cp, 984 wdc_cp->channel, cmdsizep, ctlsizep); 985 986 if (cp->hw_ok == 0) 987 return; 988 wdc_cp->data32iot = wdc_cp->cmd_iot; 989 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 990 wdcattach(wdc_cp); 991 } 992 993 /* 994 * Generic code to call to know if a channel can be disabled. Return 1 995 * if channel can be disabled, 0 if not 996 */ 997 int 998 pciiide_chan_candisable(cp) 999 struct pciide_channel *cp; 1000 { 1001 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1002 struct channel_softc *wdc_cp = &cp->wdc_channel; 1003 1004 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1005 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1006 printf("%s: disabling %s channel (no drives)\n", 1007 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1008 cp->hw_ok = 0; 1009 return 1; 1010 } 1011 return 0; 1012 } 1013 1014 /* 1015 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1016 * Set hw_ok=0 on failure 1017 */ 1018 void 1019 pciide_map_compat_intr(pa, cp, compatchan, interface) 1020 struct pci_attach_args *pa; 1021 struct pciide_channel *cp; 1022 int compatchan, interface; 1023 { 1024 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1025 struct channel_softc *wdc_cp = &cp->wdc_channel; 1026 1027 if (cp->hw_ok == 0) 1028 return; 1029 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1030 return; 1031 1032 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1033 pa, compatchan, pciide_compat_intr, cp); 1034 if (cp->ih == NULL) { 1035 printf("%s: no compatibility interrupt for use by %s " 1036 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1037 cp->hw_ok = 0; 1038 } 1039 } 1040 1041 void 1042 pciide_print_modes(cp) 1043 struct pciide_channel *cp; 1044 { 1045 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1046 int drive; 1047 struct channel_softc *chp; 1048 struct ata_drive_datas *drvp; 1049 1050 chp = &cp->wdc_channel; 1051 for (drive = 0; drive < 2; drive++) { 1052 drvp = &chp->ch_drive[drive]; 1053 if ((drvp->drive_flags & DRIVE) == 0) 1054 continue; 1055 printf("%s(%s:%d:%d): using PIO mode %d", 1056 drvp->drv_softc->dv_xname, 1057 sc->sc_wdcdev.sc_dev.dv_xname, 1058 chp->channel, drive, drvp->PIO_mode); 1059 if (drvp->drive_flags & DRIVE_DMA) 1060 printf(", DMA mode %d", drvp->DMA_mode); 1061 if (drvp->drive_flags & DRIVE_UDMA) 1062 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1063 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1064 printf(" (using DMA data transfers)"); 1065 printf("\n"); 1066 } 1067 } 1068 1069 void 1070 default_chip_map(sc, pa) 1071 struct pciide_softc *sc; 1072 struct pci_attach_args *pa; 1073 { 1074 struct pciide_channel *cp; 1075 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1076 sc->sc_tag, PCI_CLASS_REG)); 1077 pcireg_t csr; 1078 int channel, drive; 1079 struct ata_drive_datas *drvp; 1080 u_int8_t idedma_ctl; 1081 bus_size_t cmdsize, ctlsize; 1082 char *failreason; 1083 1084 if (pciide_chipen(sc, pa) == 0) 1085 return; 1086 1087 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1088 printf("%s: bus-master DMA support present", 1089 sc->sc_wdcdev.sc_dev.dv_xname); 1090 if (sc->sc_pp == &default_product_desc && 1091 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1092 PCIIDE_OPTIONS_DMA) == 0) { 1093 printf(", but unused (no driver support)"); 1094 sc->sc_dma_ok = 0; 1095 } else { 1096 pciide_mapreg_dma(sc, pa); 1097 if (sc->sc_dma_ok != 0) 1098 printf(", used without full driver " 1099 "support"); 1100 } 1101 } else { 1102 printf("%s: hardware does not support DMA", 1103 sc->sc_wdcdev.sc_dev.dv_xname); 1104 sc->sc_dma_ok = 0; 1105 } 1106 printf("\n"); 1107 if (sc->sc_dma_ok) 1108 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1109 sc->sc_wdcdev.PIO_cap = 0; 1110 sc->sc_wdcdev.DMA_cap = 0; 1111 1112 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1113 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1114 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1115 1116 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1117 cp = &sc->pciide_channels[channel]; 1118 if (pciide_chansetup(sc, channel, interface) == 0) 1119 continue; 1120 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1121 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1122 &ctlsize, pciide_pci_intr); 1123 } else { 1124 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1125 channel, &cmdsize, &ctlsize); 1126 } 1127 if (cp->hw_ok == 0) 1128 continue; 1129 /* 1130 * Check to see if something appears to be there. 1131 */ 1132 failreason = NULL; 1133 if (!wdcprobe(&cp->wdc_channel)) { 1134 failreason = "not responding; disabled or no drives?"; 1135 goto next; 1136 } 1137 /* 1138 * Now, make sure it's actually attributable to this PCI IDE 1139 * channel by trying to access the channel again while the 1140 * PCI IDE controller's I/O space is disabled. (If the 1141 * channel no longer appears to be there, it belongs to 1142 * this controller.) YUCK! 1143 */ 1144 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1145 PCI_COMMAND_STATUS_REG); 1146 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1147 csr & ~PCI_COMMAND_IO_ENABLE); 1148 if (wdcprobe(&cp->wdc_channel)) 1149 failreason = "other hardware responding at addresses"; 1150 pci_conf_write(sc->sc_pc, sc->sc_tag, 1151 PCI_COMMAND_STATUS_REG, csr); 1152 next: 1153 if (failreason) { 1154 printf("%s: %s channel ignored (%s)\n", 1155 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1156 failreason); 1157 cp->hw_ok = 0; 1158 bus_space_unmap(cp->wdc_channel.cmd_iot, 1159 cp->wdc_channel.cmd_ioh, cmdsize); 1160 bus_space_unmap(cp->wdc_channel.ctl_iot, 1161 cp->wdc_channel.ctl_ioh, ctlsize); 1162 } else { 1163 pciide_map_compat_intr(pa, cp, channel, interface); 1164 } 1165 if (cp->hw_ok) { 1166 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1167 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1168 wdcattach(&cp->wdc_channel); 1169 } 1170 } 1171 1172 if (sc->sc_dma_ok == 0) 1173 return; 1174 1175 /* Allocate DMA maps */ 1176 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1177 idedma_ctl = 0; 1178 cp = &sc->pciide_channels[channel]; 1179 for (drive = 0; drive < 2; drive++) { 1180 drvp = &cp->wdc_channel.ch_drive[drive]; 1181 /* If no drive, skip */ 1182 if ((drvp->drive_flags & DRIVE) == 0) 1183 continue; 1184 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1185 continue; 1186 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1187 /* Abort DMA setup */ 1188 printf("%s:%d:%d: can't allocate DMA maps, " 1189 "using PIO transfers\n", 1190 sc->sc_wdcdev.sc_dev.dv_xname, 1191 channel, drive); 1192 drvp->drive_flags &= ~DRIVE_DMA; 1193 } 1194 printf("%s:%d:%d: using DMA data transfers\n", 1195 sc->sc_wdcdev.sc_dev.dv_xname, 1196 channel, drive); 1197 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1198 } 1199 if (idedma_ctl != 0) { 1200 /* Add software bits in status register */ 1201 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1202 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1203 idedma_ctl); 1204 } 1205 } 1206 } 1207 1208 void 1209 piix_chip_map(sc, pa) 1210 struct pciide_softc *sc; 1211 struct pci_attach_args *pa; 1212 { 1213 struct pciide_channel *cp; 1214 int channel; 1215 u_int32_t idetim; 1216 bus_size_t cmdsize, ctlsize; 1217 1218 if (pciide_chipen(sc, pa) == 0) 1219 return; 1220 1221 printf("%s: bus-master DMA support present", 1222 sc->sc_wdcdev.sc_dev.dv_xname); 1223 pciide_mapreg_dma(sc, pa); 1224 printf("\n"); 1225 if (sc->sc_dma_ok) { 1226 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1227 switch(sc->sc_pp->ide_product) { 1228 case PCI_PRODUCT_INTEL_82371AB_IDE: 1229 case PCI_PRODUCT_INTEL_82801AA_IDE: 1230 case PCI_PRODUCT_INTEL_82801AB_IDE: 1231 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1232 } 1233 } 1234 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1235 WDC_CAPABILITY_MODE; 1236 sc->sc_wdcdev.PIO_cap = 4; 1237 sc->sc_wdcdev.DMA_cap = 2; 1238 sc->sc_wdcdev.UDMA_cap = 1239 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1240 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1241 sc->sc_wdcdev.set_modes = piix_setup_channel; 1242 else 1243 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1244 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1245 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1246 1247 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1248 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1249 DEBUG_PROBE); 1250 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1251 WDCDEBUG_PRINT((", sidetim=0x%x", 1252 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1253 DEBUG_PROBE); 1254 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1255 WDCDEBUG_PRINT((", udamreg 0x%x", 1256 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1257 DEBUG_PROBE); 1258 } 1259 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1260 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1261 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1262 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1263 DEBUG_PROBE); 1264 } 1265 1266 } 1267 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1268 1269 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1270 cp = &sc->pciide_channels[channel]; 1271 /* PIIX is compat-only */ 1272 if (pciide_chansetup(sc, channel, 0) == 0) 1273 continue; 1274 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1275 if ((PIIX_IDETIM_READ(idetim, channel) & 1276 PIIX_IDETIM_IDE) == 0) { 1277 printf("%s: %s channel ignored (disabled)\n", 1278 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1279 continue; 1280 } 1281 /* PIIX are compat-only pciide devices */ 1282 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1283 if (cp->hw_ok == 0) 1284 continue; 1285 if (pciiide_chan_candisable(cp)) { 1286 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1287 channel); 1288 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1289 idetim); 1290 } 1291 pciide_map_compat_intr(pa, cp, channel, 0); 1292 if (cp->hw_ok == 0) 1293 continue; 1294 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1295 } 1296 1297 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1298 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1299 DEBUG_PROBE); 1300 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1301 WDCDEBUG_PRINT((", sidetim=0x%x", 1302 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1303 DEBUG_PROBE); 1304 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1305 WDCDEBUG_PRINT((", udamreg 0x%x", 1306 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1307 DEBUG_PROBE); 1308 } 1309 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1310 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1311 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1312 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1313 DEBUG_PROBE); 1314 } 1315 } 1316 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1317 } 1318 1319 void 1320 piix_setup_channel(chp) 1321 struct channel_softc *chp; 1322 { 1323 u_int8_t mode[2], drive; 1324 u_int32_t oidetim, idetim, idedma_ctl; 1325 struct pciide_channel *cp = (struct pciide_channel*)chp; 1326 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1327 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1328 1329 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1330 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1331 idedma_ctl = 0; 1332 1333 /* set up new idetim: Enable IDE registers decode */ 1334 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1335 chp->channel); 1336 1337 /* setup DMA */ 1338 pciide_channel_dma_setup(cp); 1339 1340 /* 1341 * Here we have to mess up with drives mode: PIIX can't have 1342 * different timings for master and slave drives. 1343 * We need to find the best combination. 1344 */ 1345 1346 /* If both drives supports DMA, take the lower mode */ 1347 if ((drvp[0].drive_flags & DRIVE_DMA) && 1348 (drvp[1].drive_flags & DRIVE_DMA)) { 1349 mode[0] = mode[1] = 1350 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1351 drvp[0].DMA_mode = mode[0]; 1352 drvp[1].DMA_mode = mode[1]; 1353 goto ok; 1354 } 1355 /* 1356 * If only one drive supports DMA, use its mode, and 1357 * put the other one in PIO mode 0 if mode not compatible 1358 */ 1359 if (drvp[0].drive_flags & DRIVE_DMA) { 1360 mode[0] = drvp[0].DMA_mode; 1361 mode[1] = drvp[1].PIO_mode; 1362 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1363 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1364 mode[1] = drvp[1].PIO_mode = 0; 1365 goto ok; 1366 } 1367 if (drvp[1].drive_flags & DRIVE_DMA) { 1368 mode[1] = drvp[1].DMA_mode; 1369 mode[0] = drvp[0].PIO_mode; 1370 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1371 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1372 mode[0] = drvp[0].PIO_mode = 0; 1373 goto ok; 1374 } 1375 /* 1376 * If both drives are not DMA, takes the lower mode, unless 1377 * one of them is PIO mode < 2 1378 */ 1379 if (drvp[0].PIO_mode < 2) { 1380 mode[0] = drvp[0].PIO_mode = 0; 1381 mode[1] = drvp[1].PIO_mode; 1382 } else if (drvp[1].PIO_mode < 2) { 1383 mode[1] = drvp[1].PIO_mode = 0; 1384 mode[0] = drvp[0].PIO_mode; 1385 } else { 1386 mode[0] = mode[1] = 1387 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1388 drvp[0].PIO_mode = mode[0]; 1389 drvp[1].PIO_mode = mode[1]; 1390 } 1391 ok: /* The modes are setup */ 1392 for (drive = 0; drive < 2; drive++) { 1393 if (drvp[drive].drive_flags & DRIVE_DMA) { 1394 idetim |= piix_setup_idetim_timings( 1395 mode[drive], 1, chp->channel); 1396 goto end; 1397 } 1398 } 1399 /* If we are there, none of the drives are DMA */ 1400 if (mode[0] >= 2) 1401 idetim |= piix_setup_idetim_timings( 1402 mode[0], 0, chp->channel); 1403 else 1404 idetim |= piix_setup_idetim_timings( 1405 mode[1], 0, chp->channel); 1406 end: /* 1407 * timing mode is now set up in the controller. Enable 1408 * it per-drive 1409 */ 1410 for (drive = 0; drive < 2; drive++) { 1411 /* If no drive, skip */ 1412 if ((drvp[drive].drive_flags & DRIVE) == 0) 1413 continue; 1414 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1415 if (drvp[drive].drive_flags & DRIVE_DMA) 1416 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1417 } 1418 if (idedma_ctl != 0) { 1419 /* Add software bits in status register */ 1420 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1421 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1422 idedma_ctl); 1423 } 1424 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1425 pciide_print_modes(cp); 1426 } 1427 1428 void 1429 piix3_4_setup_channel(chp) 1430 struct channel_softc *chp; 1431 { 1432 struct ata_drive_datas *drvp; 1433 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1434 struct pciide_channel *cp = (struct pciide_channel*)chp; 1435 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1436 int drive; 1437 int channel = chp->channel; 1438 1439 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1440 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1441 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1442 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1443 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1444 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1445 PIIX_SIDETIM_RTC_MASK(channel)); 1446 1447 idedma_ctl = 0; 1448 /* If channel disabled, no need to go further */ 1449 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1450 return; 1451 /* set up new idetim: Enable IDE registers decode */ 1452 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1453 1454 /* setup DMA if needed */ 1455 pciide_channel_dma_setup(cp); 1456 1457 for (drive = 0; drive < 2; drive++) { 1458 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1459 PIIX_UDMATIM_SET(0x3, channel, drive)); 1460 drvp = &chp->ch_drive[drive]; 1461 /* If no drive, skip */ 1462 if ((drvp->drive_flags & DRIVE) == 0) 1463 continue; 1464 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1465 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1466 goto pio; 1467 1468 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1469 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1470 ideconf |= PIIX_CONFIG_PINGPONG; 1471 } 1472 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1473 /* setup Ultra/66 */ 1474 if (drvp->UDMA_mode > 2 && 1475 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1476 drvp->UDMA_mode = 2; 1477 if (drvp->UDMA_mode > 2) 1478 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1479 else 1480 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1481 } 1482 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1483 (drvp->drive_flags & DRIVE_UDMA)) { 1484 /* use Ultra/DMA */ 1485 drvp->drive_flags &= ~DRIVE_DMA; 1486 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1487 udmareg |= PIIX_UDMATIM_SET( 1488 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1489 } else { 1490 /* use Multiword DMA */ 1491 drvp->drive_flags &= ~DRIVE_UDMA; 1492 if (drive == 0) { 1493 idetim |= piix_setup_idetim_timings( 1494 drvp->DMA_mode, 1, channel); 1495 } else { 1496 sidetim |= piix_setup_sidetim_timings( 1497 drvp->DMA_mode, 1, channel); 1498 idetim =PIIX_IDETIM_SET(idetim, 1499 PIIX_IDETIM_SITRE, channel); 1500 } 1501 } 1502 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1503 1504 pio: /* use PIO mode */ 1505 idetim |= piix_setup_idetim_drvs(drvp); 1506 if (drive == 0) { 1507 idetim |= piix_setup_idetim_timings( 1508 drvp->PIO_mode, 0, channel); 1509 } else { 1510 sidetim |= piix_setup_sidetim_timings( 1511 drvp->PIO_mode, 0, channel); 1512 idetim =PIIX_IDETIM_SET(idetim, 1513 PIIX_IDETIM_SITRE, channel); 1514 } 1515 } 1516 if (idedma_ctl != 0) { 1517 /* Add software bits in status register */ 1518 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1519 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1520 idedma_ctl); 1521 } 1522 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1523 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1524 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1525 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1526 pciide_print_modes(cp); 1527 } 1528 1529 1530 /* setup ISP and RTC fields, based on mode */ 1531 static u_int32_t 1532 piix_setup_idetim_timings(mode, dma, channel) 1533 u_int8_t mode; 1534 u_int8_t dma; 1535 u_int8_t channel; 1536 { 1537 1538 if (dma) 1539 return PIIX_IDETIM_SET(0, 1540 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1541 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1542 channel); 1543 else 1544 return PIIX_IDETIM_SET(0, 1545 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1546 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1547 channel); 1548 } 1549 1550 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1551 static u_int32_t 1552 piix_setup_idetim_drvs(drvp) 1553 struct ata_drive_datas *drvp; 1554 { 1555 u_int32_t ret = 0; 1556 struct channel_softc *chp = drvp->chnl_softc; 1557 u_int8_t channel = chp->channel; 1558 u_int8_t drive = drvp->drive; 1559 1560 /* 1561 * If drive is using UDMA, timings setups are independant 1562 * So just check DMA and PIO here. 1563 */ 1564 if (drvp->drive_flags & DRIVE_DMA) { 1565 /* if mode = DMA mode 0, use compatible timings */ 1566 if ((drvp->drive_flags & DRIVE_DMA) && 1567 drvp->DMA_mode == 0) { 1568 drvp->PIO_mode = 0; 1569 return ret; 1570 } 1571 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1572 /* 1573 * PIO and DMA timings are the same, use fast timings for PIO 1574 * too, else use compat timings. 1575 */ 1576 if ((piix_isp_pio[drvp->PIO_mode] != 1577 piix_isp_dma[drvp->DMA_mode]) || 1578 (piix_rtc_pio[drvp->PIO_mode] != 1579 piix_rtc_dma[drvp->DMA_mode])) 1580 drvp->PIO_mode = 0; 1581 /* if PIO mode <= 2, use compat timings for PIO */ 1582 if (drvp->PIO_mode <= 2) { 1583 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1584 channel); 1585 return ret; 1586 } 1587 } 1588 1589 /* 1590 * Now setup PIO modes. If mode < 2, use compat timings. 1591 * Else enable fast timings. Enable IORDY and prefetch/post 1592 * if PIO mode >= 3. 1593 */ 1594 1595 if (drvp->PIO_mode < 2) 1596 return ret; 1597 1598 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1599 if (drvp->PIO_mode >= 3) { 1600 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1601 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1602 } 1603 return ret; 1604 } 1605 1606 /* setup values in SIDETIM registers, based on mode */ 1607 static u_int32_t 1608 piix_setup_sidetim_timings(mode, dma, channel) 1609 u_int8_t mode; 1610 u_int8_t dma; 1611 u_int8_t channel; 1612 { 1613 if (dma) 1614 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1615 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1616 else 1617 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1618 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1619 } 1620 1621 void 1622 amd756_chip_map(sc, pa) 1623 struct pciide_softc *sc; 1624 struct pci_attach_args *pa; 1625 { 1626 struct pciide_channel *cp; 1627 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1628 sc->sc_tag, PCI_CLASS_REG)); 1629 int channel; 1630 pcireg_t chanenable; 1631 bus_size_t cmdsize, ctlsize; 1632 1633 if (pciide_chipen(sc, pa) == 0) 1634 return; 1635 printf("%s: bus-master DMA support present", 1636 sc->sc_wdcdev.sc_dev.dv_xname); 1637 pciide_mapreg_dma(sc, pa); 1638 printf("\n"); 1639 if (sc->sc_dma_ok) 1640 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1641 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1642 WDC_CAPABILITY_MODE; 1643 sc->sc_wdcdev.PIO_cap = 4; 1644 sc->sc_wdcdev.DMA_cap = 2; 1645 sc->sc_wdcdev.UDMA_cap = 4; 1646 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1647 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1648 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1649 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1650 1651 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1652 DEBUG_PROBE); 1653 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1654 cp = &sc->pciide_channels[channel]; 1655 if (pciide_chansetup(sc, channel, interface) == 0) 1656 continue; 1657 1658 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1659 printf("%s: %s channel ignored (disabled)\n", 1660 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1661 continue; 1662 } 1663 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1664 pciide_pci_intr); 1665 1666 if (pciiide_chan_candisable(cp)) 1667 chanenable &= ~AMD756_CHAN_EN(channel); 1668 pciide_map_compat_intr(pa, cp, channel, interface); 1669 if (cp->hw_ok == 0) 1670 continue; 1671 1672 amd756_setup_channel(&cp->wdc_channel); 1673 } 1674 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1675 chanenable); 1676 return; 1677 } 1678 1679 void 1680 amd756_setup_channel(chp) 1681 struct channel_softc *chp; 1682 { 1683 u_int32_t udmatim_reg, datatim_reg; 1684 u_int8_t idedma_ctl; 1685 int mode, drive; 1686 struct ata_drive_datas *drvp; 1687 struct pciide_channel *cp = (struct pciide_channel*)chp; 1688 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1689 1690 idedma_ctl = 0; 1691 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1692 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1693 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1694 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1695 1696 /* setup DMA if needed */ 1697 pciide_channel_dma_setup(cp); 1698 1699 for (drive = 0; drive < 2; drive++) { 1700 drvp = &chp->ch_drive[drive]; 1701 /* If no drive, skip */ 1702 if ((drvp->drive_flags & DRIVE) == 0) 1703 continue; 1704 /* add timing values, setup DMA if needed */ 1705 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1706 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1707 mode = drvp->PIO_mode; 1708 goto pio; 1709 } 1710 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1711 (drvp->drive_flags & DRIVE_UDMA)) { 1712 /* use Ultra/DMA */ 1713 drvp->drive_flags &= ~DRIVE_DMA; 1714 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1715 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1716 AMD756_UDMA_TIME(chp->channel, drive, 1717 amd756_udma_tim[drvp->UDMA_mode]); 1718 /* can use PIO timings, MW DMA unused */ 1719 mode = drvp->PIO_mode; 1720 } else { 1721 /* use Multiword DMA */ 1722 drvp->drive_flags &= ~DRIVE_UDMA; 1723 /* mode = min(pio, dma+2) */ 1724 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1725 mode = drvp->PIO_mode; 1726 else 1727 mode = drvp->DMA_mode + 2; 1728 } 1729 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1730 1731 pio: /* setup PIO mode */ 1732 if (mode <= 2) { 1733 drvp->DMA_mode = 0; 1734 drvp->PIO_mode = 0; 1735 mode = 0; 1736 } else { 1737 drvp->PIO_mode = mode; 1738 drvp->DMA_mode = mode - 2; 1739 } 1740 datatim_reg |= 1741 AMD756_DATATIM_PULSE(chp->channel, drive, 1742 amd756_pio_set[mode]) | 1743 AMD756_DATATIM_RECOV(chp->channel, drive, 1744 amd756_pio_rec[mode]); 1745 } 1746 if (idedma_ctl != 0) { 1747 /* Add software bits in status register */ 1748 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1749 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1750 idedma_ctl); 1751 } 1752 pciide_print_modes(cp); 1753 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1754 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1755 } 1756 1757 void 1758 apollo_chip_map(sc, pa) 1759 struct pciide_softc *sc; 1760 struct pci_attach_args *pa; 1761 { 1762 struct pciide_channel *cp; 1763 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1764 sc->sc_tag, PCI_CLASS_REG)); 1765 int channel; 1766 u_int32_t ideconf; 1767 bus_size_t cmdsize, ctlsize; 1768 1769 if (pciide_chipen(sc, pa) == 0) 1770 return; 1771 printf("%s: bus-master DMA support present", 1772 sc->sc_wdcdev.sc_dev.dv_xname); 1773 pciide_mapreg_dma(sc, pa); 1774 printf("\n"); 1775 if (sc->sc_dma_ok) { 1776 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1777 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1778 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1779 } 1780 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE; 1781 sc->sc_wdcdev.PIO_cap = 4; 1782 sc->sc_wdcdev.DMA_cap = 2; 1783 sc->sc_wdcdev.UDMA_cap = 2; 1784 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1785 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1786 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1787 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1788 1789 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1790 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1791 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1792 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1793 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1794 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1795 DEBUG_PROBE); 1796 1797 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1798 cp = &sc->pciide_channels[channel]; 1799 if (pciide_chansetup(sc, channel, interface) == 0) 1800 continue; 1801 1802 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1803 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1804 printf("%s: %s channel ignored (disabled)\n", 1805 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1806 continue; 1807 } 1808 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1809 pciide_pci_intr); 1810 if (cp->hw_ok == 0) 1811 continue; 1812 if (pciiide_chan_candisable(cp)) { 1813 ideconf &= ~APO_IDECONF_EN(channel); 1814 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1815 ideconf); 1816 } 1817 pciide_map_compat_intr(pa, cp, channel, interface); 1818 1819 if (cp->hw_ok == 0) 1820 continue; 1821 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1822 } 1823 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1824 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1825 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1826 } 1827 1828 void 1829 apollo_setup_channel(chp) 1830 struct channel_softc *chp; 1831 { 1832 u_int32_t udmatim_reg, datatim_reg; 1833 u_int8_t idedma_ctl; 1834 int mode, drive; 1835 struct ata_drive_datas *drvp; 1836 struct pciide_channel *cp = (struct pciide_channel*)chp; 1837 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1838 1839 idedma_ctl = 0; 1840 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1841 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1842 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1843 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1844 1845 /* setup DMA if needed */ 1846 pciide_channel_dma_setup(cp); 1847 1848 for (drive = 0; drive < 2; drive++) { 1849 drvp = &chp->ch_drive[drive]; 1850 /* If no drive, skip */ 1851 if ((drvp->drive_flags & DRIVE) == 0) 1852 continue; 1853 /* add timing values, setup DMA if needed */ 1854 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1855 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1856 mode = drvp->PIO_mode; 1857 goto pio; 1858 } 1859 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1860 (drvp->drive_flags & DRIVE_UDMA)) { 1861 /* use Ultra/DMA */ 1862 drvp->drive_flags &= ~DRIVE_DMA; 1863 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1864 APO_UDMA_EN_MTH(chp->channel, drive) | 1865 APO_UDMA_TIME(chp->channel, drive, 1866 apollo_udma_tim[drvp->UDMA_mode]); 1867 /* can use PIO timings, MW DMA unused */ 1868 mode = drvp->PIO_mode; 1869 } else { 1870 /* use Multiword DMA */ 1871 drvp->drive_flags &= ~DRIVE_UDMA; 1872 /* mode = min(pio, dma+2) */ 1873 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1874 mode = drvp->PIO_mode; 1875 else 1876 mode = drvp->DMA_mode + 2; 1877 } 1878 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1879 1880 pio: /* setup PIO mode */ 1881 if (mode <= 2) { 1882 drvp->DMA_mode = 0; 1883 drvp->PIO_mode = 0; 1884 mode = 0; 1885 } else { 1886 drvp->PIO_mode = mode; 1887 drvp->DMA_mode = mode - 2; 1888 } 1889 datatim_reg |= 1890 APO_DATATIM_PULSE(chp->channel, drive, 1891 apollo_pio_set[mode]) | 1892 APO_DATATIM_RECOV(chp->channel, drive, 1893 apollo_pio_rec[mode]); 1894 } 1895 if (idedma_ctl != 0) { 1896 /* Add software bits in status register */ 1897 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1898 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1899 idedma_ctl); 1900 } 1901 pciide_print_modes(cp); 1902 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 1903 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 1904 } 1905 1906 void 1907 cmd_channel_map(pa, sc, channel) 1908 struct pci_attach_args *pa; 1909 struct pciide_softc *sc; 1910 int channel; 1911 { 1912 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1913 bus_size_t cmdsize, ctlsize; 1914 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 1915 int interface = 1916 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1917 1918 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1919 cp->name = PCIIDE_CHANNEL_NAME(channel); 1920 cp->wdc_channel.channel = channel; 1921 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1922 1923 if (channel > 0) { 1924 cp->wdc_channel.ch_queue = 1925 sc->pciide_channels[0].wdc_channel.ch_queue; 1926 } else { 1927 cp->wdc_channel.ch_queue = 1928 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1929 } 1930 if (cp->wdc_channel.ch_queue == NULL) { 1931 printf("%s %s channel: " 1932 "can't allocate memory for command queue", 1933 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1934 return; 1935 } 1936 1937 printf("%s: %s channel %s to %s mode\n", 1938 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1939 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1940 "configured" : "wired", 1941 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1942 "native-PCI" : "compatibility"); 1943 1944 /* 1945 * with a CMD PCI64x, if we get here, the first channel is enabled: 1946 * there's no way to disable the first channel without disabling 1947 * the whole device 1948 */ 1949 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 1950 printf("%s: %s channel ignored (disabled)\n", 1951 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1952 return; 1953 } 1954 1955 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 1956 if (cp->hw_ok == 0) 1957 return; 1958 if (channel == 1) { 1959 if (pciiide_chan_candisable(cp)) { 1960 ctrl &= ~CMD_CTRL_2PORT; 1961 pciide_pci_write(pa->pa_pc, pa->pa_tag, 1962 CMD_CTRL, ctrl); 1963 } 1964 } 1965 pciide_map_compat_intr(pa, cp, channel, interface); 1966 } 1967 1968 int 1969 cmd_pci_intr(arg) 1970 void *arg; 1971 { 1972 struct pciide_softc *sc = arg; 1973 struct pciide_channel *cp; 1974 struct channel_softc *wdc_cp; 1975 int i, rv, crv; 1976 u_int32_t priirq, secirq; 1977 1978 rv = 0; 1979 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 1980 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 1981 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1982 cp = &sc->pciide_channels[i]; 1983 wdc_cp = &cp->wdc_channel; 1984 /* If a compat channel skip. */ 1985 if (cp->compat) 1986 continue; 1987 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 1988 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 1989 crv = wdcintr(wdc_cp); 1990 if (crv == 0) 1991 printf("%s:%d: bogus intr\n", 1992 sc->sc_wdcdev.sc_dev.dv_xname, i); 1993 else 1994 rv = 1; 1995 } 1996 } 1997 return rv; 1998 } 1999 2000 void 2001 cmd_chip_map(sc, pa) 2002 struct pciide_softc *sc; 2003 struct pci_attach_args *pa; 2004 { 2005 int channel; 2006 2007 /* 2008 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2009 * and base adresses registers can be disabled at 2010 * hardware level. In this case, the device is wired 2011 * in compat mode and its first channel is always enabled, 2012 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2013 * In fact, it seems that the first channel of the CMD PCI0640 2014 * can't be disabled. 2015 */ 2016 2017 #ifdef PCIIDE_CMD064x_DISABLE 2018 if (pciide_chipen(sc, pa) == 0) 2019 return; 2020 #endif 2021 2022 printf("%s: hardware does not support DMA\n", 2023 sc->sc_wdcdev.sc_dev.dv_xname); 2024 sc->sc_dma_ok = 0; 2025 2026 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2027 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2028 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 2029 2030 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2031 cmd_channel_map(pa, sc, channel); 2032 } 2033 } 2034 2035 void 2036 cmd0643_6_chip_map(sc, pa) 2037 struct pciide_softc *sc; 2038 struct pci_attach_args *pa; 2039 { 2040 struct pciide_channel *cp; 2041 int channel; 2042 2043 /* 2044 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2045 * and base adresses registers can be disabled at 2046 * hardware level. In this case, the device is wired 2047 * in compat mode and its first channel is always enabled, 2048 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2049 * In fact, it seems that the first channel of the CMD PCI0640 2050 * can't be disabled. 2051 */ 2052 2053 #ifdef PCIIDE_CMD064x_DISABLE 2054 if (pciide_chipen(sc, pa) == 0) 2055 return; 2056 #endif 2057 printf("%s: bus-master DMA support present", 2058 sc->sc_wdcdev.sc_dev.dv_xname); 2059 pciide_mapreg_dma(sc, pa); 2060 printf("\n"); 2061 if (sc->sc_dma_ok) 2062 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2063 2064 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2065 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2066 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2067 WDC_CAPABILITY_MODE; 2068 sc->sc_wdcdev.PIO_cap = 4; 2069 sc->sc_wdcdev.DMA_cap = 2; 2070 sc->sc_wdcdev.set_modes = cmd0643_6_setup_channel; 2071 2072 WDCDEBUG_PRINT(("cmd0643_6_chip_map: old timings reg 0x%x 0x%x\n", 2073 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2074 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2075 DEBUG_PROBE); 2076 2077 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2078 cp = &sc->pciide_channels[channel]; 2079 cmd_channel_map(pa, sc, channel); 2080 if (cp->hw_ok == 0) 2081 continue; 2082 cmd0643_6_setup_channel(&cp->wdc_channel); 2083 } 2084 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2085 WDCDEBUG_PRINT(("cmd0643_6_chip_map: timings reg now 0x%x 0x%x\n", 2086 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2087 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2088 DEBUG_PROBE); 2089 } 2090 2091 void 2092 cmd0643_6_setup_channel(chp) 2093 struct channel_softc *chp; 2094 { 2095 struct ata_drive_datas *drvp; 2096 u_int8_t tim; 2097 u_int32_t idedma_ctl; 2098 int drive; 2099 struct pciide_channel *cp = (struct pciide_channel*)chp; 2100 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2101 2102 idedma_ctl = 0; 2103 /* setup DMA if needed */ 2104 pciide_channel_dma_setup(cp); 2105 2106 for (drive = 0; drive < 2; drive++) { 2107 drvp = &chp->ch_drive[drive]; 2108 /* If no drive, skip */ 2109 if ((drvp->drive_flags & DRIVE) == 0) 2110 continue; 2111 /* add timing values, setup DMA if needed */ 2112 tim = cmd0643_6_data_tim_pio[drvp->PIO_mode]; 2113 if (drvp->drive_flags & DRIVE_DMA) { 2114 /* 2115 * use Multiword DMA. 2116 * Timings will be used for both PIO and DMA, so adjust 2117 * DMA mode if needed 2118 */ 2119 if (drvp->PIO_mode >= 3 && 2120 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2121 drvp->DMA_mode = drvp->PIO_mode - 2; 2122 } 2123 tim = cmd0643_6_data_tim_dma[drvp->DMA_mode]; 2124 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2125 } 2126 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2127 CMD_DATA_TIM(chp->channel, drive), tim); 2128 } 2129 if (idedma_ctl != 0) { 2130 /* Add software bits in status register */ 2131 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2132 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2133 idedma_ctl); 2134 } 2135 pciide_print_modes(cp); 2136 } 2137 2138 void 2139 cy693_chip_map(sc, pa) 2140 struct pciide_softc *sc; 2141 struct pci_attach_args *pa; 2142 { 2143 struct pciide_channel *cp; 2144 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2145 sc->sc_tag, PCI_CLASS_REG)); 2146 int compatchan; 2147 bus_size_t cmdsize, ctlsize; 2148 2149 if (pciide_chipen(sc, pa) == 0) 2150 return; 2151 /* 2152 * this chip has 2 PCI IDE functions, one for primary and one for 2153 * secondary. So we need to call pciide_mapregs_compat() with 2154 * the real channel 2155 */ 2156 if (pa->pa_function == 1) { 2157 compatchan = 0; 2158 } else if (pa->pa_function == 2) { 2159 compatchan = 1; 2160 } else { 2161 printf("%s: unexpected PCI function %d\n", 2162 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2163 cp->hw_ok = 0; 2164 return; 2165 } 2166 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2167 printf("%s: bus-master DMA support present", 2168 sc->sc_wdcdev.sc_dev.dv_xname); 2169 pciide_mapreg_dma(sc, pa); 2170 } else { 2171 printf("%s: hardware does not support DMA", 2172 sc->sc_wdcdev.sc_dev.dv_xname); 2173 sc->sc_dma_ok = 0; 2174 } 2175 printf("\n"); 2176 2177 if (sc->sc_dma_ok) 2178 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2179 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2180 WDC_CAPABILITY_MODE; 2181 sc->sc_wdcdev.PIO_cap = 4; 2182 sc->sc_wdcdev.DMA_cap = 2; 2183 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2184 2185 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2186 sc->sc_wdcdev.nchannels = 1; 2187 2188 /* Only one channel for this chip; if we are here it's enabled */ 2189 cp = &sc->pciide_channels[0]; 2190 sc->wdc_chanarray[0] = &cp->wdc_channel; 2191 cp->name = PCIIDE_CHANNEL_NAME(0); 2192 cp->wdc_channel.channel = 0; 2193 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2194 cp->wdc_channel.ch_queue = 2195 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2196 if (cp->wdc_channel.ch_queue == NULL) { 2197 printf("%s primary channel: " 2198 "can't allocate memory for command queue", 2199 sc->sc_wdcdev.sc_dev.dv_xname); 2200 return; 2201 } 2202 printf("%s: primary channel %s to ", 2203 sc->sc_wdcdev.sc_dev.dv_xname, 2204 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2205 "configured" : "wired"); 2206 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2207 printf("native-PCI"); 2208 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2209 pciide_pci_intr); 2210 } else { 2211 printf("compatibility"); 2212 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2213 &cmdsize, &ctlsize); 2214 } 2215 printf(" mode\n"); 2216 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2217 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2218 wdcattach(&cp->wdc_channel); 2219 if (pciiide_chan_candisable(cp)) { 2220 pci_conf_write(sc->sc_pc, sc->sc_tag, 2221 PCI_COMMAND_STATUS_REG, 0); 2222 } 2223 pciide_map_compat_intr(pa, cp, compatchan, interface); 2224 if (cp->hw_ok == 0) 2225 return; 2226 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2227 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2228 cy693_setup_channel(&cp->wdc_channel); 2229 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2230 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2231 } 2232 2233 void 2234 cy693_setup_channel(chp) 2235 struct channel_softc *chp; 2236 { 2237 struct ata_drive_datas *drvp; 2238 int drive; 2239 u_int32_t cy_cmd_ctrl; 2240 u_int32_t idedma_ctl; 2241 struct pciide_channel *cp = (struct pciide_channel*)chp; 2242 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2243 int dma_mode = -1; 2244 2245 cy_cmd_ctrl = idedma_ctl = 0; 2246 2247 /* setup DMA if needed */ 2248 pciide_channel_dma_setup(cp); 2249 2250 for (drive = 0; drive < 2; drive++) { 2251 drvp = &chp->ch_drive[drive]; 2252 /* If no drive, skip */ 2253 if ((drvp->drive_flags & DRIVE) == 0) 2254 continue; 2255 /* add timing values, setup DMA if needed */ 2256 if (drvp->drive_flags & DRIVE_DMA) { 2257 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2258 /* use Multiword DMA */ 2259 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2260 dma_mode = drvp->DMA_mode; 2261 } 2262 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2263 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2264 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2265 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2266 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2267 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2268 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2269 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2270 } 2271 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2272 chp->ch_drive[0].DMA_mode = dma_mode; 2273 chp->ch_drive[1].DMA_mode = dma_mode; 2274 pciide_print_modes(cp); 2275 if (idedma_ctl != 0) { 2276 /* Add software bits in status register */ 2277 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2278 IDEDMA_CTL, idedma_ctl); 2279 } 2280 } 2281 2282 void 2283 sis_chip_map(sc, pa) 2284 struct pciide_softc *sc; 2285 struct pci_attach_args *pa; 2286 { 2287 struct pciide_channel *cp; 2288 int channel; 2289 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2290 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2291 sc->sc_tag, PCI_CLASS_REG)); 2292 pcireg_t rev = PCI_REVISION(pci_conf_read(sc->sc_pc, 2293 sc->sc_tag, PCI_CLASS_REG)); 2294 bus_size_t cmdsize, ctlsize; 2295 2296 if (pciide_chipen(sc, pa) == 0) 2297 return; 2298 printf("%s: bus-master DMA support present", 2299 sc->sc_wdcdev.sc_dev.dv_xname); 2300 pciide_mapreg_dma(sc, pa); 2301 printf("\n"); 2302 if (sc->sc_dma_ok) { 2303 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2304 if (rev >= 0xd0) 2305 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2306 } 2307 2308 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2309 WDC_CAPABILITY_MODE; 2310 sc->sc_wdcdev.PIO_cap = 4; 2311 sc->sc_wdcdev.DMA_cap = 2; 2312 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2313 sc->sc_wdcdev.UDMA_cap = 2; 2314 sc->sc_wdcdev.set_modes = sis_setup_channel; 2315 2316 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2317 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2318 2319 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2320 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2321 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2322 2323 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2324 cp = &sc->pciide_channels[channel]; 2325 if (pciide_chansetup(sc, channel, interface) == 0) 2326 continue; 2327 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2328 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2329 printf("%s: %s channel ignored (disabled)\n", 2330 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2331 continue; 2332 } 2333 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2334 pciide_pci_intr); 2335 if (cp->hw_ok == 0) 2336 continue; 2337 if (pciiide_chan_candisable(cp)) { 2338 if (channel == 0) 2339 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2340 else 2341 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2342 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2343 sis_ctr0); 2344 } 2345 pciide_map_compat_intr(pa, cp, channel, interface); 2346 if (cp->hw_ok == 0) 2347 continue; 2348 sis_setup_channel(&cp->wdc_channel); 2349 } 2350 } 2351 2352 void 2353 sis_setup_channel(chp) 2354 struct channel_softc *chp; 2355 { 2356 struct ata_drive_datas *drvp; 2357 int drive; 2358 u_int32_t sis_tim; 2359 u_int32_t idedma_ctl; 2360 struct pciide_channel *cp = (struct pciide_channel*)chp; 2361 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2362 2363 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2364 "channel %d 0x%x\n", chp->channel, 2365 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2366 DEBUG_PROBE); 2367 sis_tim = 0; 2368 idedma_ctl = 0; 2369 /* setup DMA if needed */ 2370 pciide_channel_dma_setup(cp); 2371 2372 for (drive = 0; drive < 2; drive++) { 2373 drvp = &chp->ch_drive[drive]; 2374 /* If no drive, skip */ 2375 if ((drvp->drive_flags & DRIVE) == 0) 2376 continue; 2377 /* add timing values, setup DMA if needed */ 2378 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2379 (drvp->drive_flags & DRIVE_UDMA) == 0) 2380 goto pio; 2381 2382 if (drvp->drive_flags & DRIVE_UDMA) { 2383 /* use Ultra/DMA */ 2384 drvp->drive_flags &= ~DRIVE_DMA; 2385 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2386 SIS_TIM_UDMA_TIME_OFF(drive); 2387 sis_tim |= SIS_TIM_UDMA_EN(drive); 2388 } else { 2389 /* 2390 * use Multiword DMA 2391 * Timings will be used for both PIO and DMA, 2392 * so adjust DMA mode if needed 2393 */ 2394 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2395 drvp->PIO_mode = drvp->DMA_mode + 2; 2396 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2397 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2398 drvp->PIO_mode - 2 : 0; 2399 if (drvp->DMA_mode == 0) 2400 drvp->PIO_mode = 0; 2401 } 2402 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2403 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2404 SIS_TIM_ACT_OFF(drive); 2405 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2406 SIS_TIM_REC_OFF(drive); 2407 } 2408 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2409 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2410 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2411 if (idedma_ctl != 0) { 2412 /* Add software bits in status register */ 2413 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2414 IDEDMA_CTL, idedma_ctl); 2415 } 2416 pciide_print_modes(cp); 2417 } 2418 2419 void 2420 acer_chip_map(sc, pa) 2421 struct pciide_softc *sc; 2422 struct pci_attach_args *pa; 2423 { 2424 struct pciide_channel *cp; 2425 int channel; 2426 pcireg_t cr, interface; 2427 bus_size_t cmdsize, ctlsize; 2428 2429 if (pciide_chipen(sc, pa) == 0) 2430 return; 2431 printf("%s: bus-master DMA support present", 2432 sc->sc_wdcdev.sc_dev.dv_xname); 2433 pciide_mapreg_dma(sc, pa); 2434 printf("\n"); 2435 if (sc->sc_dma_ok) 2436 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2437 2438 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2439 WDC_CAPABILITY_MODE; 2440 2441 sc->sc_wdcdev.PIO_cap = 4; 2442 sc->sc_wdcdev.DMA_cap = 2; 2443 sc->sc_wdcdev.UDMA_cap = 2; 2444 sc->sc_wdcdev.set_modes = acer_setup_channel; 2445 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2446 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2447 2448 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2449 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2450 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2451 2452 /* Enable "microsoft register bits" R/W. */ 2453 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2454 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2455 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2456 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2457 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2458 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2459 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2460 ~ACER_CHANSTATUSREGS_RO); 2461 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2462 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2463 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2464 /* Don't use cr, re-read the real register content instead */ 2465 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2466 PCI_CLASS_REG)); 2467 2468 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2469 cp = &sc->pciide_channels[channel]; 2470 if (pciide_chansetup(sc, channel, interface) == 0) 2471 continue; 2472 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2473 printf("%s: %s channel ignored (disabled)\n", 2474 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2475 continue; 2476 } 2477 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2478 acer_pci_intr); 2479 if (cp->hw_ok == 0) 2480 continue; 2481 if (pciiide_chan_candisable(cp)) { 2482 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2483 pci_conf_write(sc->sc_pc, sc->sc_tag, 2484 PCI_CLASS_REG, cr); 2485 } 2486 pciide_map_compat_intr(pa, cp, channel, interface); 2487 acer_setup_channel(&cp->wdc_channel); 2488 } 2489 } 2490 2491 void 2492 acer_setup_channel(chp) 2493 struct channel_softc *chp; 2494 { 2495 struct ata_drive_datas *drvp; 2496 int drive; 2497 u_int32_t acer_fifo_udma; 2498 u_int32_t idedma_ctl; 2499 struct pciide_channel *cp = (struct pciide_channel*)chp; 2500 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2501 2502 idedma_ctl = 0; 2503 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2504 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2505 acer_fifo_udma), DEBUG_PROBE); 2506 /* setup DMA if needed */ 2507 pciide_channel_dma_setup(cp); 2508 2509 for (drive = 0; drive < 2; drive++) { 2510 drvp = &chp->ch_drive[drive]; 2511 /* If no drive, skip */ 2512 if ((drvp->drive_flags & DRIVE) == 0) 2513 continue; 2514 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2515 "channel %d drive %d 0x%x\n", chp->channel, drive, 2516 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2517 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2518 /* clear FIFO/DMA mode */ 2519 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2520 ACER_UDMA_EN(chp->channel, drive) | 2521 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2522 2523 /* add timing values, setup DMA if needed */ 2524 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2525 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2526 acer_fifo_udma |= 2527 ACER_FTH_OPL(chp->channel, drive, 0x1); 2528 goto pio; 2529 } 2530 2531 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2532 if (drvp->drive_flags & DRIVE_UDMA) { 2533 /* use Ultra/DMA */ 2534 drvp->drive_flags &= ~DRIVE_DMA; 2535 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2536 acer_fifo_udma |= 2537 ACER_UDMA_TIM(chp->channel, drive, 2538 acer_udma[drvp->UDMA_mode]); 2539 } else { 2540 /* 2541 * use Multiword DMA 2542 * Timings will be used for both PIO and DMA, 2543 * so adjust DMA mode if needed 2544 */ 2545 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2546 drvp->PIO_mode = drvp->DMA_mode + 2; 2547 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2548 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2549 drvp->PIO_mode - 2 : 0; 2550 if (drvp->DMA_mode == 0) 2551 drvp->PIO_mode = 0; 2552 } 2553 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2554 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2555 ACER_IDETIM(chp->channel, drive), 2556 acer_pio[drvp->PIO_mode]); 2557 } 2558 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2559 acer_fifo_udma), DEBUG_PROBE); 2560 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2561 if (idedma_ctl != 0) { 2562 /* Add software bits in status register */ 2563 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2564 IDEDMA_CTL, idedma_ctl); 2565 } 2566 pciide_print_modes(cp); 2567 } 2568 2569 int 2570 acer_pci_intr(arg) 2571 void *arg; 2572 { 2573 struct pciide_softc *sc = arg; 2574 struct pciide_channel *cp; 2575 struct channel_softc *wdc_cp; 2576 int i, rv, crv; 2577 u_int32_t chids; 2578 2579 rv = 0; 2580 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2581 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2582 cp = &sc->pciide_channels[i]; 2583 wdc_cp = &cp->wdc_channel; 2584 /* If a compat channel skip. */ 2585 if (cp->compat) 2586 continue; 2587 if (chids & ACER_CHIDS_INT(i)) { 2588 crv = wdcintr(wdc_cp); 2589 if (crv == 0) 2590 printf("%s:%d: bogus intr\n", 2591 sc->sc_wdcdev.sc_dev.dv_xname, i); 2592 else 2593 rv = 1; 2594 } 2595 } 2596 return rv; 2597 } 2598 2599 /* A macro to test product */ 2600 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 2601 2602 void 2603 pdc202xx_chip_map(sc, pa) 2604 struct pciide_softc *sc; 2605 struct pci_attach_args *pa; 2606 { 2607 struct pciide_channel *cp; 2608 int channel; 2609 pcireg_t interface, st, mode; 2610 bus_size_t cmdsize, ctlsize; 2611 2612 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2613 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 2614 DEBUG_PROBE); 2615 if (pciide_chipen(sc, pa) == 0) 2616 return; 2617 2618 /* turn off RAID mode */ 2619 st &= ~PDC2xx_STATE_IDERAID; 2620 2621 /* 2622 * can't rely on the PCI_CLASS_REG content if the chip was in raid 2623 * mode. We have to fake interface 2624 */ 2625 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 2626 if (st & PDC2xx_STATE_NATIVE) 2627 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2628 2629 printf("%s: bus-master DMA support present", 2630 sc->sc_wdcdev.sc_dev.dv_xname); 2631 pciide_mapreg_dma(sc, pa); 2632 printf("\n"); 2633 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2634 WDC_CAPABILITY_MODE; 2635 if (sc->sc_dma_ok) 2636 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2637 sc->sc_wdcdev.PIO_cap = 4; 2638 sc->sc_wdcdev.DMA_cap = 2; 2639 if (PDC_IS_262(sc)) 2640 sc->sc_wdcdev.UDMA_cap = 4; 2641 else 2642 sc->sc_wdcdev.UDMA_cap = 2; 2643 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 2644 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2645 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2646 2647 /* setup failsafe defaults */ 2648 mode = 0; 2649 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 2650 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 2651 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 2652 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 2653 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2654 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 2655 "initial timings 0x%x, now 0x%x\n", channel, 2656 pci_conf_read(sc->sc_pc, sc->sc_tag, 2657 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 2658 DEBUG_PROBE); 2659 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 2660 mode | PDC2xx_TIM_IORDYp); 2661 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 2662 "initial timings 0x%x, now 0x%x\n", channel, 2663 pci_conf_read(sc->sc_pc, sc->sc_tag, 2664 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 2665 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 2666 mode); 2667 } 2668 2669 mode = PDC2xx_SCR_DMA; 2670 if (PDC_IS_262(sc)) { 2671 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 2672 } else { 2673 /* the BIOS set it up this way */ 2674 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 2675 } 2676 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 2677 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 2678 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 2679 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 2680 DEBUG_PROBE); 2681 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 2682 2683 /* controller initial state register is OK even without BIOS */ 2684 /* Set DMA mode to IDE DMA compatibility */ 2685 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 2686 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 2687 DEBUG_PROBE); 2688 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 2689 mode | 0x1); 2690 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 2691 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 2692 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 2693 mode | 0x1); 2694 2695 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2696 cp = &sc->pciide_channels[channel]; 2697 if (pciide_chansetup(sc, channel, interface) == 0) 2698 continue; 2699 if ((st & (PDC_IS_262(sc) ? 2700 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 2701 printf("%s: %s channel ignored (disabled)\n", 2702 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2703 continue; 2704 } 2705 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2706 pdc202xx_pci_intr); 2707 if (cp->hw_ok == 0) 2708 continue; 2709 if (pciiide_chan_candisable(cp)) 2710 st &= ~(PDC_IS_262(sc) ? 2711 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 2712 pciide_map_compat_intr(pa, cp, channel, interface); 2713 pdc202xx_setup_channel(&cp->wdc_channel); 2714 } 2715 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 2716 DEBUG_PROBE); 2717 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 2718 return; 2719 } 2720 2721 void 2722 pdc202xx_setup_channel(chp) 2723 struct channel_softc *chp; 2724 { 2725 struct ata_drive_datas *drvp; 2726 int drive; 2727 pcireg_t mode, st; 2728 u_int32_t idedma_ctl, scr, atapi; 2729 struct pciide_channel *cp = (struct pciide_channel*)chp; 2730 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2731 int channel = chp->channel; 2732 2733 /* setup DMA if needed */ 2734 pciide_channel_dma_setup(cp); 2735 2736 idedma_ctl = 0; 2737 2738 /* Per channel settings */ 2739 if (PDC_IS_262(sc)) { 2740 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2741 PDC262_U66); 2742 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2743 /* Trimm UDMA mode */ 2744 if ((st & PDC262_STATE_80P(channel)) == 0 || 2745 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 2746 chp->ch_drive[0].UDMA_mode <= 2) || 2747 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 2748 chp->ch_drive[1].UDMA_mode <= 2)) { 2749 if (chp->ch_drive[0].UDMA_mode > 2) 2750 chp->ch_drive[0].UDMA_mode = 2; 2751 if (chp->ch_drive[1].UDMA_mode > 2) 2752 chp->ch_drive[1].UDMA_mode = 2; 2753 } 2754 /* Set U66 if needed */ 2755 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 2756 chp->ch_drive[0].UDMA_mode > 2) || 2757 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 2758 chp->ch_drive[1].UDMA_mode > 2)) 2759 scr |= PDC262_U66_EN(channel); 2760 else 2761 scr &= ~PDC262_U66_EN(channel); 2762 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2763 PDC262_U66, scr); 2764 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 2765 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 2766 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2767 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 2768 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 2769 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 2770 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2771 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 2772 atapi = 0; 2773 else 2774 atapi = PDC262_ATAPI_UDMA; 2775 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 2776 PDC262_ATAPI(channel), atapi); 2777 } 2778 } 2779 for (drive = 0; drive < 2; drive++) { 2780 drvp = &chp->ch_drive[drive]; 2781 /* If no drive, skip */ 2782 if ((drvp->drive_flags & DRIVE) == 0) 2783 continue; 2784 mode = 0; 2785 if (drvp->drive_flags & DRIVE_UDMA) { 2786 mode = PDC2xx_TIM_SET_MB(mode, 2787 pdc2xx_udma_mb[drvp->UDMA_mode]); 2788 mode = PDC2xx_TIM_SET_MC(mode, 2789 pdc2xx_udma_mc[drvp->UDMA_mode]); 2790 drvp->drive_flags &= ~DRIVE_DMA; 2791 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2792 } else if (drvp->drive_flags & DRIVE_DMA) { 2793 mode = PDC2xx_TIM_SET_MB(mode, 2794 pdc2xx_dma_mb[drvp->DMA_mode]); 2795 mode = PDC2xx_TIM_SET_MC(mode, 2796 pdc2xx_dma_mc[drvp->DMA_mode]); 2797 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2798 } else { 2799 mode = PDC2xx_TIM_SET_MB(mode, 2800 pdc2xx_dma_mb[0]); 2801 mode = PDC2xx_TIM_SET_MC(mode, 2802 pdc2xx_dma_mc[0]); 2803 } 2804 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 2805 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 2806 if (drvp->drive_flags & DRIVE_ATA) 2807 mode |= PDC2xx_TIM_PRE; 2808 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 2809 if (drvp->PIO_mode >= 3) { 2810 mode |= PDC2xx_TIM_IORDY; 2811 if (drive == 0) 2812 mode |= PDC2xx_TIM_IORDYp; 2813 } 2814 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 2815 "timings 0x%x\n", 2816 sc->sc_wdcdev.sc_dev.dv_xname, 2817 chp->channel, drive, mode), DEBUG_PROBE); 2818 pci_conf_write(sc->sc_pc, sc->sc_tag, 2819 PDC2xx_TIM(chp->channel, drive), mode); 2820 } 2821 if (idedma_ctl != 0) { 2822 /* Add software bits in status register */ 2823 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2824 IDEDMA_CTL, idedma_ctl); 2825 } 2826 pciide_print_modes(cp); 2827 } 2828 2829 int 2830 pdc202xx_pci_intr(arg) 2831 void *arg; 2832 { 2833 struct pciide_softc *sc = arg; 2834 struct pciide_channel *cp; 2835 struct channel_softc *wdc_cp; 2836 int i, rv, crv; 2837 u_int32_t scr; 2838 2839 rv = 0; 2840 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 2841 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2842 cp = &sc->pciide_channels[i]; 2843 wdc_cp = &cp->wdc_channel; 2844 /* If a compat channel skip. */ 2845 if (cp->compat) 2846 continue; 2847 if (scr & PDC2xx_SCR_INT(i)) { 2848 crv = wdcintr(wdc_cp); 2849 if (crv == 0) 2850 printf("%s:%d: bogus intr\n", 2851 sc->sc_wdcdev.sc_dev.dv_xname, i); 2852 else 2853 rv = 1; 2854 } 2855 } 2856 return rv; 2857 } 2858
Indexes created Thu Oct 02 10:09:58 GMT 2025