pciide.c revision 1.56
1 /* $NetBSD: pciide.c,v 1.56 2000/04/01 14:32:23 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 38 /* 39 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by Christopher G. Demetriou 52 * for the NetBSD Project. 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * PCI IDE controller driver. 70 * 71 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 72 * sys/dev/pci/ppb.c, revision 1.16). 73 * 74 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 75 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 76 * 5/16/94" from the PCI SIG. 77 * 78 */ 79 80 #ifndef WDCDEBUG 81 #define WDCDEBUG 82 #endif 83 84 #define DEBUG_DMA 0x01 85 #define DEBUG_XFERS 0x02 86 #define DEBUG_FUNCS 0x08 87 #define DEBUG_PROBE 0x10 88 #ifdef WDCDEBUG 89 int wdcdebug_pciide_mask = 0; 90 #define WDCDEBUG_PRINT(args, level) \ 91 if (wdcdebug_pciide_mask & (level)) printf args 92 #else 93 #define WDCDEBUG_PRINT(args, level) 94 #endif 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/device.h> 98 #include <sys/malloc.h> 99 100 #include <machine/endian.h> 101 102 #include <vm/vm.h> 103 #include <vm/vm_param.h> 104 #include <vm/vm_kern.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 #include <dev/pci/pcidevs.h> 109 #include <dev/pci/pciidereg.h> 110 #include <dev/pci/pciidevar.h> 111 #include <dev/pci/pciide_piix_reg.h> 112 #include <dev/pci/pciide_amd_reg.h> 113 #include <dev/pci/pciide_apollo_reg.h> 114 #include <dev/pci/pciide_cmd_reg.h> 115 #include <dev/pci/pciide_cy693_reg.h> 116 #include <dev/pci/pciide_sis_reg.h> 117 #include <dev/pci/pciide_acer_reg.h> 118 #include <dev/pci/pciide_pdc202xx_reg.h> 119 120 /* inlines for reading/writing 8-bit PCI registers */ 121 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 122 int)); 123 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 124 int, u_int8_t)); 125 126 static __inline u_int8_t 127 pciide_pci_read(pc, pa, reg) 128 pci_chipset_tag_t pc; 129 pcitag_t pa; 130 int reg; 131 { 132 133 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 134 ((reg & 0x03) * 8) & 0xff); 135 } 136 137 static __inline void 138 pciide_pci_write(pc, pa, reg, val) 139 pci_chipset_tag_t pc; 140 pcitag_t pa; 141 int reg; 142 u_int8_t val; 143 { 144 pcireg_t pcival; 145 146 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 147 pcival &= ~(0xff << ((reg & 0x03) * 8)); 148 pcival |= (val << ((reg & 0x03) * 8)); 149 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 150 } 151 152 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 153 154 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 155 void piix_setup_channel __P((struct channel_softc*)); 156 void piix3_4_setup_channel __P((struct channel_softc*)); 157 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 158 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 159 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 160 161 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 162 void amd756_setup_channel __P((struct channel_softc*)); 163 164 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void apollo_setup_channel __P((struct channel_softc*)); 166 167 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void cmd0643_6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 169 void cmd0643_6_setup_channel __P((struct channel_softc*)); 170 void cmd_channel_map __P((struct pci_attach_args *, 171 struct pciide_softc *, int)); 172 int cmd_pci_intr __P((void *)); 173 174 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cy693_setup_channel __P((struct channel_softc*)); 176 177 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void sis_setup_channel __P((struct channel_softc*)); 179 180 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void acer_setup_channel __P((struct channel_softc*)); 182 int acer_pci_intr __P((void *)); 183 184 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void pdc202xx_setup_channel __P((struct channel_softc*)); 186 int pdc202xx_pci_intr __P((void *)); 187 188 void pciide_channel_dma_setup __P((struct pciide_channel *)); 189 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 190 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 191 void pciide_dma_start __P((void*, int, int)); 192 int pciide_dma_finish __P((void*, int, int, int)); 193 void pciide_print_modes __P((struct pciide_channel *)); 194 195 struct pciide_product_desc { 196 u_int32_t ide_product; 197 int ide_flags; 198 const char *ide_name; 199 /* map and setup chip, probe drives */ 200 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 201 }; 202 203 /* Flags for ide_flags */ 204 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 205 206 /* Default product description for devices not known from this controller */ 207 const struct pciide_product_desc default_product_desc = { 208 0, 209 0, 210 "Generic PCI IDE controller", 211 default_chip_map, 212 }; 213 214 const struct pciide_product_desc pciide_intel_products[] = { 215 { PCI_PRODUCT_INTEL_82092AA, 216 0, 217 "Intel 82092AA IDE controller", 218 default_chip_map, 219 }, 220 { PCI_PRODUCT_INTEL_82371FB_IDE, 221 0, 222 "Intel 82371FB IDE controller (PIIX)", 223 piix_chip_map, 224 }, 225 { PCI_PRODUCT_INTEL_82371SB_IDE, 226 0, 227 "Intel 82371SB IDE Interface (PIIX3)", 228 piix_chip_map, 229 }, 230 { PCI_PRODUCT_INTEL_82371AB_IDE, 231 0, 232 "Intel 82371AB IDE controller (PIIX4)", 233 piix_chip_map, 234 }, 235 { PCI_PRODUCT_INTEL_82801AA_IDE, 236 0, 237 "Intel 82801AA IDE Controller (ICH)", 238 piix_chip_map, 239 }, 240 { PCI_PRODUCT_INTEL_82801AB_IDE, 241 0, 242 "Intel 82801AB IDE Controller (ICH0)", 243 piix_chip_map, 244 }, 245 { 0, 246 0, 247 NULL, 248 } 249 }; 250 251 const struct pciide_product_desc pciide_amd_products[] = { 252 { PCI_PRODUCT_AMD_PBC756_IDE, 253 0, 254 "Advanced Micro Devices AMD756 IDE Controller", 255 amd756_chip_map 256 }, 257 { 0, 258 0, 259 NULL, 260 } 261 }; 262 263 const struct pciide_product_desc pciide_cmd_products[] = { 264 { PCI_PRODUCT_CMDTECH_640, 265 0, 266 "CMD Technology PCI0640", 267 cmd_chip_map 268 }, 269 { PCI_PRODUCT_CMDTECH_643, 270 0, 271 "CMD Technology PCI0643", 272 cmd0643_6_chip_map, 273 }, 274 { PCI_PRODUCT_CMDTECH_646, 275 0, 276 "CMD Technology PCI0646", 277 cmd0643_6_chip_map, 278 }, 279 { 0, 280 0, 281 NULL, 282 } 283 }; 284 285 const struct pciide_product_desc pciide_via_products[] = { 286 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 287 0, 288 "VIA Technologies VT82C586 (Apollo VP) IDE Controller", 289 apollo_chip_map, 290 }, 291 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 292 0, 293 "VIA Technologies VT82C586A IDE Controller", 294 apollo_chip_map, 295 }, 296 { 0, 297 0, 298 NULL, 299 } 300 }; 301 302 const struct pciide_product_desc pciide_cypress_products[] = { 303 { PCI_PRODUCT_CONTAQ_82C693, 304 0, 305 "Contaq Microsystems CY82C693 IDE Controller", 306 cy693_chip_map, 307 }, 308 { 0, 309 0, 310 NULL, 311 } 312 }; 313 314 const struct pciide_product_desc pciide_sis_products[] = { 315 { PCI_PRODUCT_SIS_5597_IDE, 316 0, 317 "Silicon Integrated System 5597/5598 IDE controller", 318 sis_chip_map, 319 }, 320 { 0, 321 0, 322 NULL, 323 } 324 }; 325 326 const struct pciide_product_desc pciide_acer_products[] = { 327 { PCI_PRODUCT_ALI_M5229, 328 0, 329 "Acer Labs M5229 UDMA IDE Controller", 330 acer_chip_map, 331 }, 332 { 0, 333 0, 334 NULL, 335 } 336 }; 337 338 const struct pciide_product_desc pciide_promise_products[] = { 339 { PCI_PRODUCT_PROMISE_ULTRA33, 340 IDE_PCI_CLASS_OVERRIDE, 341 "Promise Ultra33/ATA Bus Master IDE Accelerator", 342 pdc202xx_chip_map, 343 }, 344 { PCI_PRODUCT_PROMISE_ULTRA66, 345 IDE_PCI_CLASS_OVERRIDE, 346 "Promise Ultra66/ATA Bus Master IDE Accelerator", 347 pdc202xx_chip_map, 348 }, 349 { 0, 350 0, 351 NULL, 352 } 353 }; 354 355 struct pciide_vendor_desc { 356 u_int32_t ide_vendor; 357 const struct pciide_product_desc *ide_products; 358 }; 359 360 const struct pciide_vendor_desc pciide_vendors[] = { 361 { PCI_VENDOR_INTEL, pciide_intel_products }, 362 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 363 { PCI_VENDOR_VIATECH, pciide_via_products }, 364 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 365 { PCI_VENDOR_SIS, pciide_sis_products }, 366 { PCI_VENDOR_ALI, pciide_acer_products }, 367 { PCI_VENDOR_PROMISE, pciide_promise_products }, 368 { PCI_VENDOR_AMD, pciide_amd_products }, 369 { 0, NULL } 370 }; 371 372 /* options passed via the 'flags' config keyword */ 373 #define PCIIDE_OPTIONS_DMA 0x01 374 375 int pciide_match __P((struct device *, struct cfdata *, void *)); 376 void pciide_attach __P((struct device *, struct device *, void *)); 377 378 struct cfattach pciide_ca = { 379 sizeof(struct pciide_softc), pciide_match, pciide_attach 380 }; 381 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 382 int pciide_mapregs_compat __P(( struct pci_attach_args *, 383 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 384 int pciide_mapregs_native __P((struct pci_attach_args *, 385 struct pciide_channel *, bus_size_t *, bus_size_t *, 386 int (*pci_intr) __P((void *)))); 387 void pciide_mapreg_dma __P((struct pciide_softc *, 388 struct pci_attach_args *)); 389 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 390 void pciide_mapchan __P((struct pci_attach_args *, 391 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 392 int (*pci_intr) __P((void *)))); 393 int pciiide_chan_candisable __P((struct pciide_channel *)); 394 void pciide_map_compat_intr __P(( struct pci_attach_args *, 395 struct pciide_channel *, int, int)); 396 int pciide_print __P((void *, const char *pnp)); 397 int pciide_compat_intr __P((void *)); 398 int pciide_pci_intr __P((void *)); 399 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 400 401 const struct pciide_product_desc * 402 pciide_lookup_product(id) 403 u_int32_t id; 404 { 405 const struct pciide_product_desc *pp; 406 const struct pciide_vendor_desc *vp; 407 408 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 409 if (PCI_VENDOR(id) == vp->ide_vendor) 410 break; 411 412 if ((pp = vp->ide_products) == NULL) 413 return NULL; 414 415 for (; pp->ide_name != NULL; pp++) 416 if (PCI_PRODUCT(id) == pp->ide_product) 417 break; 418 419 if (pp->ide_name == NULL) 420 return NULL; 421 return pp; 422 } 423 424 int 425 pciide_match(parent, match, aux) 426 struct device *parent; 427 struct cfdata *match; 428 void *aux; 429 { 430 struct pci_attach_args *pa = aux; 431 const struct pciide_product_desc *pp; 432 433 /* 434 * Check the ID register to see that it's a PCI IDE controller. 435 * If it is, we assume that we can deal with it; it _should_ 436 * work in a standardized way... 437 */ 438 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 439 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 440 return (1); 441 } 442 443 /* 444 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 445 * controllers. Let see if we can deal with it anyway. 446 */ 447 pp = pciide_lookup_product(pa->pa_id); 448 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 449 return (1); 450 } 451 452 return (0); 453 } 454 455 void 456 pciide_attach(parent, self, aux) 457 struct device *parent, *self; 458 void *aux; 459 { 460 struct pci_attach_args *pa = aux; 461 pci_chipset_tag_t pc = pa->pa_pc; 462 pcitag_t tag = pa->pa_tag; 463 struct pciide_softc *sc = (struct pciide_softc *)self; 464 pcireg_t csr; 465 char devinfo[256]; 466 467 sc->sc_pp = pciide_lookup_product(pa->pa_id); 468 if (sc->sc_pp == NULL) { 469 sc->sc_pp = &default_product_desc; 470 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 471 printf(": %s (rev. 0x%02x)\n", devinfo, 472 PCI_REVISION(pa->pa_class)); 473 } else { 474 printf(": %s\n", sc->sc_pp->ide_name); 475 } 476 sc->sc_pc = pa->pa_pc; 477 sc->sc_tag = pa->pa_tag; 478 #ifdef WDCDEBUG 479 if (wdcdebug_pciide_mask & DEBUG_PROBE) 480 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 481 #endif 482 483 sc->sc_pp->chip_map(sc, pa); 484 485 if (sc->sc_dma_ok) { 486 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 487 csr |= PCI_COMMAND_MASTER_ENABLE; 488 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 489 } 490 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 491 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 492 } 493 494 /* tell wether the chip is enabled or not */ 495 int 496 pciide_chipen(sc, pa) 497 struct pciide_softc *sc; 498 struct pci_attach_args *pa; 499 { 500 pcireg_t csr; 501 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 502 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 503 PCI_COMMAND_STATUS_REG); 504 printf("%s: device disabled (at %s)\n", 505 sc->sc_wdcdev.sc_dev.dv_xname, 506 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 507 "device" : "bridge"); 508 return 0; 509 } 510 return 1; 511 } 512 513 int 514 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 515 struct pci_attach_args *pa; 516 struct pciide_channel *cp; 517 int compatchan; 518 bus_size_t *cmdsizep, *ctlsizep; 519 { 520 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 521 struct channel_softc *wdc_cp = &cp->wdc_channel; 522 523 cp->compat = 1; 524 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 525 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 526 527 wdc_cp->cmd_iot = pa->pa_iot; 528 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 529 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 530 printf("%s: couldn't map %s channel cmd regs\n", 531 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 532 return (0); 533 } 534 535 wdc_cp->ctl_iot = pa->pa_iot; 536 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 537 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 538 printf("%s: couldn't map %s channel ctl regs\n", 539 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 540 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 541 PCIIDE_COMPAT_CMD_SIZE); 542 return (0); 543 } 544 545 return (1); 546 } 547 548 int 549 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 550 struct pci_attach_args * pa; 551 struct pciide_channel *cp; 552 bus_size_t *cmdsizep, *ctlsizep; 553 int (*pci_intr) __P((void *)); 554 { 555 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 556 struct channel_softc *wdc_cp = &cp->wdc_channel; 557 const char *intrstr; 558 pci_intr_handle_t intrhandle; 559 560 cp->compat = 0; 561 562 if (sc->sc_pci_ih == NULL) { 563 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 564 pa->pa_intrline, &intrhandle) != 0) { 565 printf("%s: couldn't map native-PCI interrupt\n", 566 sc->sc_wdcdev.sc_dev.dv_xname); 567 return 0; 568 } 569 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 570 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 571 intrhandle, IPL_BIO, pci_intr, sc); 572 if (sc->sc_pci_ih != NULL) { 573 printf("%s: using %s for native-PCI interrupt\n", 574 sc->sc_wdcdev.sc_dev.dv_xname, 575 intrstr ? intrstr : "unknown interrupt"); 576 } else { 577 printf("%s: couldn't establish native-PCI interrupt", 578 sc->sc_wdcdev.sc_dev.dv_xname); 579 if (intrstr != NULL) 580 printf(" at %s", intrstr); 581 printf("\n"); 582 return 0; 583 } 584 } 585 cp->ih = sc->sc_pci_ih; 586 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 587 PCI_MAPREG_TYPE_IO, 0, 588 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 589 printf("%s: couldn't map %s channel cmd regs\n", 590 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 591 return 0; 592 } 593 594 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 595 PCI_MAPREG_TYPE_IO, 0, 596 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 597 printf("%s: couldn't map %s channel ctl regs\n", 598 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 599 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 600 return 0; 601 } 602 return (1); 603 } 604 605 void 606 pciide_mapreg_dma(sc, pa) 607 struct pciide_softc *sc; 608 struct pci_attach_args *pa; 609 { 610 /* 611 * Map DMA registers 612 * 613 * Note that sc_dma_ok is the right variable to test to see if 614 * DMA can be done. If the interface doesn't support DMA, 615 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 616 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 617 * non-zero if the interface supports DMA and the registers 618 * could be mapped. 619 * 620 * XXX Note that despite the fact that the Bus Master IDE specs 621 * XXX say that "The bus master IDE function uses 16 bytes of IO 622 * XXX space," some controllers (at least the United 623 * XXX Microelectronics UM8886BF) place it in memory space. 624 * XXX eventually, we should probably read the register and check 625 * XXX which type it is. Either that or 'quirk' certain devices. 626 */ 627 sc->sc_dma_ok = (pci_mapreg_map(pa, 628 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0, 629 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 630 sc->sc_dmat = pa->pa_dmat; 631 if (sc->sc_dma_ok == 0) { 632 printf(", but unused (couldn't map registers)"); 633 } else { 634 sc->sc_wdcdev.dma_arg = sc; 635 sc->sc_wdcdev.dma_init = pciide_dma_init; 636 sc->sc_wdcdev.dma_start = pciide_dma_start; 637 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 638 } 639 } 640 int 641 pciide_compat_intr(arg) 642 void *arg; 643 { 644 struct pciide_channel *cp = arg; 645 646 #ifdef DIAGNOSTIC 647 /* should only be called for a compat channel */ 648 if (cp->compat == 0) 649 panic("pciide compat intr called for non-compat chan %p\n", cp); 650 #endif 651 return (wdcintr(&cp->wdc_channel)); 652 } 653 654 int 655 pciide_pci_intr(arg) 656 void *arg; 657 { 658 struct pciide_softc *sc = arg; 659 struct pciide_channel *cp; 660 struct channel_softc *wdc_cp; 661 int i, rv, crv; 662 663 rv = 0; 664 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 665 cp = &sc->pciide_channels[i]; 666 wdc_cp = &cp->wdc_channel; 667 668 /* If a compat channel skip. */ 669 if (cp->compat) 670 continue; 671 /* if this channel not waiting for intr, skip */ 672 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 673 continue; 674 675 crv = wdcintr(wdc_cp); 676 if (crv == 0) 677 ; /* leave rv alone */ 678 else if (crv == 1) 679 rv = 1; /* claim the intr */ 680 else if (rv == 0) /* crv should be -1 in this case */ 681 rv = crv; /* if we've done no better, take it */ 682 } 683 return (rv); 684 } 685 686 void 687 pciide_channel_dma_setup(cp) 688 struct pciide_channel *cp; 689 { 690 int drive; 691 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 692 struct ata_drive_datas *drvp; 693 694 for (drive = 0; drive < 2; drive++) { 695 drvp = &cp->wdc_channel.ch_drive[drive]; 696 /* If no drive, skip */ 697 if ((drvp->drive_flags & DRIVE) == 0) 698 continue; 699 /* setup DMA if needed */ 700 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 701 (drvp->drive_flags & DRIVE_UDMA) == 0) || 702 sc->sc_dma_ok == 0) { 703 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 704 continue; 705 } 706 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 707 != 0) { 708 /* Abort DMA setup */ 709 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 710 continue; 711 } 712 } 713 } 714 715 int 716 pciide_dma_table_setup(sc, channel, drive) 717 struct pciide_softc *sc; 718 int channel, drive; 719 { 720 bus_dma_segment_t seg; 721 int error, rseg; 722 const bus_size_t dma_table_size = 723 sizeof(struct idedma_table) * NIDEDMA_TABLES; 724 struct pciide_dma_maps *dma_maps = 725 &sc->pciide_channels[channel].dma_maps[drive]; 726 727 /* If table was already allocated, just return */ 728 if (dma_maps->dma_table) 729 return 0; 730 731 /* Allocate memory for the DMA tables and map it */ 732 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 733 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 734 BUS_DMA_NOWAIT)) != 0) { 735 printf("%s:%d: unable to allocate table DMA for " 736 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 737 channel, drive, error); 738 return error; 739 } 740 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 741 dma_table_size, 742 (caddr_t *)&dma_maps->dma_table, 743 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 744 printf("%s:%d: unable to map table DMA for" 745 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 746 channel, drive, error); 747 return error; 748 } 749 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 750 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 751 seg.ds_addr), DEBUG_PROBE); 752 753 /* Create and load table DMA map for this disk */ 754 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 755 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 756 &dma_maps->dmamap_table)) != 0) { 757 printf("%s:%d: unable to create table DMA map for " 758 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 759 channel, drive, error); 760 return error; 761 } 762 if ((error = bus_dmamap_load(sc->sc_dmat, 763 dma_maps->dmamap_table, 764 dma_maps->dma_table, 765 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 766 printf("%s:%d: unable to load table DMA map for " 767 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 768 channel, drive, error); 769 return error; 770 } 771 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 772 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 773 /* Create a xfer DMA map for this drive */ 774 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 775 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 776 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 777 &dma_maps->dmamap_xfer)) != 0) { 778 printf("%s:%d: unable to create xfer DMA map for " 779 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 780 channel, drive, error); 781 return error; 782 } 783 return 0; 784 } 785 786 int 787 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 788 void *v; 789 int channel, drive; 790 void *databuf; 791 size_t datalen; 792 int flags; 793 { 794 struct pciide_softc *sc = v; 795 int error, seg; 796 struct pciide_dma_maps *dma_maps = 797 &sc->pciide_channels[channel].dma_maps[drive]; 798 799 error = bus_dmamap_load(sc->sc_dmat, 800 dma_maps->dmamap_xfer, 801 databuf, datalen, NULL, BUS_DMA_NOWAIT); 802 if (error) { 803 printf("%s:%d: unable to load xfer DMA map for" 804 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 805 channel, drive, error); 806 return error; 807 } 808 809 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 810 dma_maps->dmamap_xfer->dm_mapsize, 811 (flags & WDC_DMA_READ) ? 812 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 813 814 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 815 #ifdef DIAGNOSTIC 816 /* A segment must not cross a 64k boundary */ 817 { 818 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 819 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 820 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 821 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 822 printf("pciide_dma: segment %d physical addr 0x%lx" 823 " len 0x%lx not properly aligned\n", 824 seg, phys, len); 825 panic("pciide_dma: buf align"); 826 } 827 } 828 #endif 829 dma_maps->dma_table[seg].base_addr = 830 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 831 dma_maps->dma_table[seg].byte_count = 832 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 833 IDEDMA_BYTE_COUNT_MASK); 834 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 835 seg, le32toh(dma_maps->dma_table[seg].byte_count), 836 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 837 838 } 839 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 840 htole32(IDEDMA_BYTE_COUNT_EOT); 841 842 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 843 dma_maps->dmamap_table->dm_mapsize, 844 BUS_DMASYNC_PREWRITE); 845 846 /* Maps are ready. Start DMA function */ 847 #ifdef DIAGNOSTIC 848 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 849 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 850 dma_maps->dmamap_table->dm_segs[0].ds_addr); 851 panic("pciide_dma_init: table align"); 852 } 853 #endif 854 855 /* Clear status bits */ 856 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 857 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 858 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 859 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 860 /* Write table addr */ 861 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 862 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 863 dma_maps->dmamap_table->dm_segs[0].ds_addr); 864 /* set read/write */ 865 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 866 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 867 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 868 /* remember flags */ 869 dma_maps->dma_flags = flags; 870 return 0; 871 } 872 873 void 874 pciide_dma_start(v, channel, drive) 875 void *v; 876 int channel, drive; 877 { 878 struct pciide_softc *sc = v; 879 880 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 881 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 882 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 883 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 884 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 885 } 886 887 int 888 pciide_dma_finish(v, channel, drive, force) 889 void *v; 890 int channel, drive; 891 int force; 892 { 893 struct pciide_softc *sc = v; 894 u_int8_t status; 895 int error = 0; 896 struct pciide_dma_maps *dma_maps = 897 &sc->pciide_channels[channel].dma_maps[drive]; 898 899 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 900 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 901 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 902 DEBUG_XFERS); 903 904 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 905 return WDC_DMAST_NOIRQ; 906 907 /* stop DMA channel */ 908 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 909 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 910 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 911 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 912 913 /* Clear status bits */ 914 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 915 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 916 status); 917 918 /* Unload the map of the data buffer */ 919 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 920 dma_maps->dmamap_xfer->dm_mapsize, 921 (dma_maps->dma_flags & WDC_DMA_READ) ? 922 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 923 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 924 925 if ((status & IDEDMA_CTL_ERR) != 0) { 926 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 927 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 928 error |= WDC_DMAST_ERR; 929 } 930 931 if ((status & IDEDMA_CTL_INTR) == 0) { 932 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 933 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 934 drive, status); 935 error |= WDC_DMAST_NOIRQ; 936 } 937 938 if ((status & IDEDMA_CTL_ACT) != 0) { 939 /* data underrun, may be a valid condition for ATAPI */ 940 error |= WDC_DMAST_UNDER; 941 } 942 return error; 943 } 944 945 /* some common code used by several chip_map */ 946 int 947 pciide_chansetup(sc, channel, interface) 948 struct pciide_softc *sc; 949 int channel; 950 pcireg_t interface; 951 { 952 struct pciide_channel *cp = &sc->pciide_channels[channel]; 953 sc->wdc_chanarray[channel] = &cp->wdc_channel; 954 cp->name = PCIIDE_CHANNEL_NAME(channel); 955 cp->wdc_channel.channel = channel; 956 cp->wdc_channel.wdc = &sc->sc_wdcdev; 957 cp->wdc_channel.ch_queue = 958 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 959 if (cp->wdc_channel.ch_queue == NULL) { 960 printf("%s %s channel: " 961 "can't allocate memory for command queue", 962 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 963 return 0; 964 } 965 printf("%s: %s channel %s to %s mode\n", 966 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 967 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 968 "configured" : "wired", 969 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 970 "native-PCI" : "compatibility"); 971 return 1; 972 } 973 974 /* some common code used by several chip channel_map */ 975 void 976 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 977 struct pci_attach_args *pa; 978 struct pciide_channel *cp; 979 pcireg_t interface; 980 bus_size_t *cmdsizep, *ctlsizep; 981 int (*pci_intr) __P((void *)); 982 { 983 struct channel_softc *wdc_cp = &cp->wdc_channel; 984 985 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 986 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 987 pci_intr); 988 else 989 cp->hw_ok = pciide_mapregs_compat(pa, cp, 990 wdc_cp->channel, cmdsizep, ctlsizep); 991 992 if (cp->hw_ok == 0) 993 return; 994 wdc_cp->data32iot = wdc_cp->cmd_iot; 995 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 996 wdcattach(wdc_cp); 997 } 998 999 /* 1000 * Generic code to call to know if a channel can be disabled. Return 1 1001 * if channel can be disabled, 0 if not 1002 */ 1003 int 1004 pciiide_chan_candisable(cp) 1005 struct pciide_channel *cp; 1006 { 1007 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1008 struct channel_softc *wdc_cp = &cp->wdc_channel; 1009 1010 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1011 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1012 printf("%s: disabling %s channel (no drives)\n", 1013 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1014 cp->hw_ok = 0; 1015 return 1; 1016 } 1017 return 0; 1018 } 1019 1020 /* 1021 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1022 * Set hw_ok=0 on failure 1023 */ 1024 void 1025 pciide_map_compat_intr(pa, cp, compatchan, interface) 1026 struct pci_attach_args *pa; 1027 struct pciide_channel *cp; 1028 int compatchan, interface; 1029 { 1030 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1031 struct channel_softc *wdc_cp = &cp->wdc_channel; 1032 1033 if (cp->hw_ok == 0) 1034 return; 1035 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1036 return; 1037 1038 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1039 pa, compatchan, pciide_compat_intr, cp); 1040 if (cp->ih == NULL) { 1041 printf("%s: no compatibility interrupt for use by %s " 1042 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1043 cp->hw_ok = 0; 1044 } 1045 } 1046 1047 void 1048 pciide_print_modes(cp) 1049 struct pciide_channel *cp; 1050 { 1051 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1052 int drive; 1053 struct channel_softc *chp; 1054 struct ata_drive_datas *drvp; 1055 1056 chp = &cp->wdc_channel; 1057 for (drive = 0; drive < 2; drive++) { 1058 drvp = &chp->ch_drive[drive]; 1059 if ((drvp->drive_flags & DRIVE) == 0) 1060 continue; 1061 printf("%s(%s:%d:%d): using PIO mode %d", 1062 drvp->drv_softc->dv_xname, 1063 sc->sc_wdcdev.sc_dev.dv_xname, 1064 chp->channel, drive, drvp->PIO_mode); 1065 if (drvp->drive_flags & DRIVE_DMA) 1066 printf(", DMA mode %d", drvp->DMA_mode); 1067 if (drvp->drive_flags & DRIVE_UDMA) 1068 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1069 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1070 printf(" (using DMA data transfers)"); 1071 printf("\n"); 1072 } 1073 } 1074 1075 void 1076 default_chip_map(sc, pa) 1077 struct pciide_softc *sc; 1078 struct pci_attach_args *pa; 1079 { 1080 struct pciide_channel *cp; 1081 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1082 sc->sc_tag, PCI_CLASS_REG)); 1083 pcireg_t csr; 1084 int channel, drive; 1085 struct ata_drive_datas *drvp; 1086 u_int8_t idedma_ctl; 1087 bus_size_t cmdsize, ctlsize; 1088 char *failreason; 1089 1090 if (pciide_chipen(sc, pa) == 0) 1091 return; 1092 1093 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1094 printf("%s: bus-master DMA support present", 1095 sc->sc_wdcdev.sc_dev.dv_xname); 1096 if (sc->sc_pp == &default_product_desc && 1097 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1098 PCIIDE_OPTIONS_DMA) == 0) { 1099 printf(", but unused (no driver support)"); 1100 sc->sc_dma_ok = 0; 1101 } else { 1102 pciide_mapreg_dma(sc, pa); 1103 if (sc->sc_dma_ok != 0) 1104 printf(", used without full driver " 1105 "support"); 1106 } 1107 } else { 1108 printf("%s: hardware does not support DMA", 1109 sc->sc_wdcdev.sc_dev.dv_xname); 1110 sc->sc_dma_ok = 0; 1111 } 1112 printf("\n"); 1113 if (sc->sc_dma_ok) 1114 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1115 sc->sc_wdcdev.PIO_cap = 0; 1116 sc->sc_wdcdev.DMA_cap = 0; 1117 1118 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1119 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1120 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1121 1122 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1123 cp = &sc->pciide_channels[channel]; 1124 if (pciide_chansetup(sc, channel, interface) == 0) 1125 continue; 1126 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1127 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1128 &ctlsize, pciide_pci_intr); 1129 } else { 1130 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1131 channel, &cmdsize, &ctlsize); 1132 } 1133 if (cp->hw_ok == 0) 1134 continue; 1135 /* 1136 * Check to see if something appears to be there. 1137 */ 1138 failreason = NULL; 1139 if (!wdcprobe(&cp->wdc_channel)) { 1140 failreason = "not responding; disabled or no drives?"; 1141 goto next; 1142 } 1143 /* 1144 * Now, make sure it's actually attributable to this PCI IDE 1145 * channel by trying to access the channel again while the 1146 * PCI IDE controller's I/O space is disabled. (If the 1147 * channel no longer appears to be there, it belongs to 1148 * this controller.) YUCK! 1149 */ 1150 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1151 PCI_COMMAND_STATUS_REG); 1152 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1153 csr & ~PCI_COMMAND_IO_ENABLE); 1154 if (wdcprobe(&cp->wdc_channel)) 1155 failreason = "other hardware responding at addresses"; 1156 pci_conf_write(sc->sc_pc, sc->sc_tag, 1157 PCI_COMMAND_STATUS_REG, csr); 1158 next: 1159 if (failreason) { 1160 printf("%s: %s channel ignored (%s)\n", 1161 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1162 failreason); 1163 cp->hw_ok = 0; 1164 bus_space_unmap(cp->wdc_channel.cmd_iot, 1165 cp->wdc_channel.cmd_ioh, cmdsize); 1166 bus_space_unmap(cp->wdc_channel.ctl_iot, 1167 cp->wdc_channel.ctl_ioh, ctlsize); 1168 } else { 1169 pciide_map_compat_intr(pa, cp, channel, interface); 1170 } 1171 if (cp->hw_ok) { 1172 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1173 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1174 wdcattach(&cp->wdc_channel); 1175 } 1176 } 1177 1178 if (sc->sc_dma_ok == 0) 1179 return; 1180 1181 /* Allocate DMA maps */ 1182 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1183 idedma_ctl = 0; 1184 cp = &sc->pciide_channels[channel]; 1185 for (drive = 0; drive < 2; drive++) { 1186 drvp = &cp->wdc_channel.ch_drive[drive]; 1187 /* If no drive, skip */ 1188 if ((drvp->drive_flags & DRIVE) == 0) 1189 continue; 1190 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1191 continue; 1192 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1193 /* Abort DMA setup */ 1194 printf("%s:%d:%d: can't allocate DMA maps, " 1195 "using PIO transfers\n", 1196 sc->sc_wdcdev.sc_dev.dv_xname, 1197 channel, drive); 1198 drvp->drive_flags &= ~DRIVE_DMA; 1199 } 1200 printf("%s:%d:%d: using DMA data transfers\n", 1201 sc->sc_wdcdev.sc_dev.dv_xname, 1202 channel, drive); 1203 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1204 } 1205 if (idedma_ctl != 0) { 1206 /* Add software bits in status register */ 1207 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1208 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1209 idedma_ctl); 1210 } 1211 } 1212 } 1213 1214 void 1215 piix_chip_map(sc, pa) 1216 struct pciide_softc *sc; 1217 struct pci_attach_args *pa; 1218 { 1219 struct pciide_channel *cp; 1220 int channel; 1221 u_int32_t idetim; 1222 bus_size_t cmdsize, ctlsize; 1223 1224 if (pciide_chipen(sc, pa) == 0) 1225 return; 1226 1227 printf("%s: bus-master DMA support present", 1228 sc->sc_wdcdev.sc_dev.dv_xname); 1229 pciide_mapreg_dma(sc, pa); 1230 printf("\n"); 1231 if (sc->sc_dma_ok) { 1232 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1233 switch(sc->sc_pp->ide_product) { 1234 case PCI_PRODUCT_INTEL_82371AB_IDE: 1235 case PCI_PRODUCT_INTEL_82801AA_IDE: 1236 case PCI_PRODUCT_INTEL_82801AB_IDE: 1237 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1238 } 1239 } 1240 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1241 WDC_CAPABILITY_MODE; 1242 sc->sc_wdcdev.PIO_cap = 4; 1243 sc->sc_wdcdev.DMA_cap = 2; 1244 sc->sc_wdcdev.UDMA_cap = 1245 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1246 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1247 sc->sc_wdcdev.set_modes = piix_setup_channel; 1248 else 1249 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1250 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1251 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1252 1253 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1254 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1255 DEBUG_PROBE); 1256 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1257 WDCDEBUG_PRINT((", sidetim=0x%x", 1258 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1259 DEBUG_PROBE); 1260 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1261 WDCDEBUG_PRINT((", udamreg 0x%x", 1262 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1263 DEBUG_PROBE); 1264 } 1265 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1266 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1267 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1268 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1269 DEBUG_PROBE); 1270 } 1271 1272 } 1273 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1274 1275 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1276 cp = &sc->pciide_channels[channel]; 1277 /* PIIX is compat-only */ 1278 if (pciide_chansetup(sc, channel, 0) == 0) 1279 continue; 1280 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1281 if ((PIIX_IDETIM_READ(idetim, channel) & 1282 PIIX_IDETIM_IDE) == 0) { 1283 printf("%s: %s channel ignored (disabled)\n", 1284 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1285 continue; 1286 } 1287 /* PIIX are compat-only pciide devices */ 1288 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1289 if (cp->hw_ok == 0) 1290 continue; 1291 if (pciiide_chan_candisable(cp)) { 1292 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1293 channel); 1294 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1295 idetim); 1296 } 1297 pciide_map_compat_intr(pa, cp, channel, 0); 1298 if (cp->hw_ok == 0) 1299 continue; 1300 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1301 } 1302 1303 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1304 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1305 DEBUG_PROBE); 1306 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1307 WDCDEBUG_PRINT((", sidetim=0x%x", 1308 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1309 DEBUG_PROBE); 1310 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1311 WDCDEBUG_PRINT((", udamreg 0x%x", 1312 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1313 DEBUG_PROBE); 1314 } 1315 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1316 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1317 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1318 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1319 DEBUG_PROBE); 1320 } 1321 } 1322 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1323 } 1324 1325 void 1326 piix_setup_channel(chp) 1327 struct channel_softc *chp; 1328 { 1329 u_int8_t mode[2], drive; 1330 u_int32_t oidetim, idetim, idedma_ctl; 1331 struct pciide_channel *cp = (struct pciide_channel*)chp; 1332 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1333 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1334 1335 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1336 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1337 idedma_ctl = 0; 1338 1339 /* set up new idetim: Enable IDE registers decode */ 1340 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1341 chp->channel); 1342 1343 /* setup DMA */ 1344 pciide_channel_dma_setup(cp); 1345 1346 /* 1347 * Here we have to mess up with drives mode: PIIX can't have 1348 * different timings for master and slave drives. 1349 * We need to find the best combination. 1350 */ 1351 1352 /* If both drives supports DMA, take the lower mode */ 1353 if ((drvp[0].drive_flags & DRIVE_DMA) && 1354 (drvp[1].drive_flags & DRIVE_DMA)) { 1355 mode[0] = mode[1] = 1356 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1357 drvp[0].DMA_mode = mode[0]; 1358 drvp[1].DMA_mode = mode[1]; 1359 goto ok; 1360 } 1361 /* 1362 * If only one drive supports DMA, use its mode, and 1363 * put the other one in PIO mode 0 if mode not compatible 1364 */ 1365 if (drvp[0].drive_flags & DRIVE_DMA) { 1366 mode[0] = drvp[0].DMA_mode; 1367 mode[1] = drvp[1].PIO_mode; 1368 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1369 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1370 mode[1] = drvp[1].PIO_mode = 0; 1371 goto ok; 1372 } 1373 if (drvp[1].drive_flags & DRIVE_DMA) { 1374 mode[1] = drvp[1].DMA_mode; 1375 mode[0] = drvp[0].PIO_mode; 1376 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1377 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1378 mode[0] = drvp[0].PIO_mode = 0; 1379 goto ok; 1380 } 1381 /* 1382 * If both drives are not DMA, takes the lower mode, unless 1383 * one of them is PIO mode < 2 1384 */ 1385 if (drvp[0].PIO_mode < 2) { 1386 mode[0] = drvp[0].PIO_mode = 0; 1387 mode[1] = drvp[1].PIO_mode; 1388 } else if (drvp[1].PIO_mode < 2) { 1389 mode[1] = drvp[1].PIO_mode = 0; 1390 mode[0] = drvp[0].PIO_mode; 1391 } else { 1392 mode[0] = mode[1] = 1393 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1394 drvp[0].PIO_mode = mode[0]; 1395 drvp[1].PIO_mode = mode[1]; 1396 } 1397 ok: /* The modes are setup */ 1398 for (drive = 0; drive < 2; drive++) { 1399 if (drvp[drive].drive_flags & DRIVE_DMA) { 1400 idetim |= piix_setup_idetim_timings( 1401 mode[drive], 1, chp->channel); 1402 goto end; 1403 } 1404 } 1405 /* If we are there, none of the drives are DMA */ 1406 if (mode[0] >= 2) 1407 idetim |= piix_setup_idetim_timings( 1408 mode[0], 0, chp->channel); 1409 else 1410 idetim |= piix_setup_idetim_timings( 1411 mode[1], 0, chp->channel); 1412 end: /* 1413 * timing mode is now set up in the controller. Enable 1414 * it per-drive 1415 */ 1416 for (drive = 0; drive < 2; drive++) { 1417 /* If no drive, skip */ 1418 if ((drvp[drive].drive_flags & DRIVE) == 0) 1419 continue; 1420 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1421 if (drvp[drive].drive_flags & DRIVE_DMA) 1422 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1423 } 1424 if (idedma_ctl != 0) { 1425 /* Add software bits in status register */ 1426 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1427 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1428 idedma_ctl); 1429 } 1430 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1431 pciide_print_modes(cp); 1432 } 1433 1434 void 1435 piix3_4_setup_channel(chp) 1436 struct channel_softc *chp; 1437 { 1438 struct ata_drive_datas *drvp; 1439 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1440 struct pciide_channel *cp = (struct pciide_channel*)chp; 1441 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1442 int drive; 1443 int channel = chp->channel; 1444 1445 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1446 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1447 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1448 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1449 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1450 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1451 PIIX_SIDETIM_RTC_MASK(channel)); 1452 1453 idedma_ctl = 0; 1454 /* If channel disabled, no need to go further */ 1455 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1456 return; 1457 /* set up new idetim: Enable IDE registers decode */ 1458 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1459 1460 /* setup DMA if needed */ 1461 pciide_channel_dma_setup(cp); 1462 1463 for (drive = 0; drive < 2; drive++) { 1464 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1465 PIIX_UDMATIM_SET(0x3, channel, drive)); 1466 drvp = &chp->ch_drive[drive]; 1467 /* If no drive, skip */ 1468 if ((drvp->drive_flags & DRIVE) == 0) 1469 continue; 1470 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1471 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1472 goto pio; 1473 1474 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1475 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1476 ideconf |= PIIX_CONFIG_PINGPONG; 1477 } 1478 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1479 /* setup Ultra/66 */ 1480 if (drvp->UDMA_mode > 2 && 1481 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1482 drvp->UDMA_mode = 2; 1483 if (drvp->UDMA_mode > 2) 1484 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1485 else 1486 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1487 } 1488 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1489 (drvp->drive_flags & DRIVE_UDMA)) { 1490 /* use Ultra/DMA */ 1491 drvp->drive_flags &= ~DRIVE_DMA; 1492 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1493 udmareg |= PIIX_UDMATIM_SET( 1494 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1495 } else { 1496 /* use Multiword DMA */ 1497 drvp->drive_flags &= ~DRIVE_UDMA; 1498 if (drive == 0) { 1499 idetim |= piix_setup_idetim_timings( 1500 drvp->DMA_mode, 1, channel); 1501 } else { 1502 sidetim |= piix_setup_sidetim_timings( 1503 drvp->DMA_mode, 1, channel); 1504 idetim =PIIX_IDETIM_SET(idetim, 1505 PIIX_IDETIM_SITRE, channel); 1506 } 1507 } 1508 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1509 1510 pio: /* use PIO mode */ 1511 idetim |= piix_setup_idetim_drvs(drvp); 1512 if (drive == 0) { 1513 idetim |= piix_setup_idetim_timings( 1514 drvp->PIO_mode, 0, channel); 1515 } else { 1516 sidetim |= piix_setup_sidetim_timings( 1517 drvp->PIO_mode, 0, channel); 1518 idetim =PIIX_IDETIM_SET(idetim, 1519 PIIX_IDETIM_SITRE, channel); 1520 } 1521 } 1522 if (idedma_ctl != 0) { 1523 /* Add software bits in status register */ 1524 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1525 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1526 idedma_ctl); 1527 } 1528 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1529 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1530 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1531 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1532 pciide_print_modes(cp); 1533 } 1534 1535 1536 /* setup ISP and RTC fields, based on mode */ 1537 static u_int32_t 1538 piix_setup_idetim_timings(mode, dma, channel) 1539 u_int8_t mode; 1540 u_int8_t dma; 1541 u_int8_t channel; 1542 { 1543 1544 if (dma) 1545 return PIIX_IDETIM_SET(0, 1546 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1547 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1548 channel); 1549 else 1550 return PIIX_IDETIM_SET(0, 1551 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1552 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1553 channel); 1554 } 1555 1556 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1557 static u_int32_t 1558 piix_setup_idetim_drvs(drvp) 1559 struct ata_drive_datas *drvp; 1560 { 1561 u_int32_t ret = 0; 1562 struct channel_softc *chp = drvp->chnl_softc; 1563 u_int8_t channel = chp->channel; 1564 u_int8_t drive = drvp->drive; 1565 1566 /* 1567 * If drive is using UDMA, timings setups are independant 1568 * So just check DMA and PIO here. 1569 */ 1570 if (drvp->drive_flags & DRIVE_DMA) { 1571 /* if mode = DMA mode 0, use compatible timings */ 1572 if ((drvp->drive_flags & DRIVE_DMA) && 1573 drvp->DMA_mode == 0) { 1574 drvp->PIO_mode = 0; 1575 return ret; 1576 } 1577 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1578 /* 1579 * PIO and DMA timings are the same, use fast timings for PIO 1580 * too, else use compat timings. 1581 */ 1582 if ((piix_isp_pio[drvp->PIO_mode] != 1583 piix_isp_dma[drvp->DMA_mode]) || 1584 (piix_rtc_pio[drvp->PIO_mode] != 1585 piix_rtc_dma[drvp->DMA_mode])) 1586 drvp->PIO_mode = 0; 1587 /* if PIO mode <= 2, use compat timings for PIO */ 1588 if (drvp->PIO_mode <= 2) { 1589 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1590 channel); 1591 return ret; 1592 } 1593 } 1594 1595 /* 1596 * Now setup PIO modes. If mode < 2, use compat timings. 1597 * Else enable fast timings. Enable IORDY and prefetch/post 1598 * if PIO mode >= 3. 1599 */ 1600 1601 if (drvp->PIO_mode < 2) 1602 return ret; 1603 1604 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1605 if (drvp->PIO_mode >= 3) { 1606 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1607 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1608 } 1609 return ret; 1610 } 1611 1612 /* setup values in SIDETIM registers, based on mode */ 1613 static u_int32_t 1614 piix_setup_sidetim_timings(mode, dma, channel) 1615 u_int8_t mode; 1616 u_int8_t dma; 1617 u_int8_t channel; 1618 { 1619 if (dma) 1620 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1621 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1622 else 1623 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1624 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1625 } 1626 1627 void 1628 amd756_chip_map(sc, pa) 1629 struct pciide_softc *sc; 1630 struct pci_attach_args *pa; 1631 { 1632 struct pciide_channel *cp; 1633 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1634 sc->sc_tag, PCI_CLASS_REG)); 1635 int channel; 1636 pcireg_t chanenable; 1637 bus_size_t cmdsize, ctlsize; 1638 1639 if (pciide_chipen(sc, pa) == 0) 1640 return; 1641 printf("%s: bus-master DMA support present", 1642 sc->sc_wdcdev.sc_dev.dv_xname); 1643 pciide_mapreg_dma(sc, pa); 1644 printf("\n"); 1645 if (sc->sc_dma_ok) 1646 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1647 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1648 WDC_CAPABILITY_MODE; 1649 sc->sc_wdcdev.PIO_cap = 4; 1650 sc->sc_wdcdev.DMA_cap = 2; 1651 sc->sc_wdcdev.UDMA_cap = 4; 1652 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1653 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1654 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1655 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1656 1657 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1658 DEBUG_PROBE); 1659 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1660 cp = &sc->pciide_channels[channel]; 1661 if (pciide_chansetup(sc, channel, interface) == 0) 1662 continue; 1663 1664 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1665 printf("%s: %s channel ignored (disabled)\n", 1666 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1667 continue; 1668 } 1669 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1670 pciide_pci_intr); 1671 1672 if (pciiide_chan_candisable(cp)) 1673 chanenable &= ~AMD756_CHAN_EN(channel); 1674 pciide_map_compat_intr(pa, cp, channel, interface); 1675 if (cp->hw_ok == 0) 1676 continue; 1677 1678 amd756_setup_channel(&cp->wdc_channel); 1679 } 1680 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1681 chanenable); 1682 return; 1683 } 1684 1685 void 1686 amd756_setup_channel(chp) 1687 struct channel_softc *chp; 1688 { 1689 u_int32_t udmatim_reg, datatim_reg; 1690 u_int8_t idedma_ctl; 1691 int mode, drive; 1692 struct ata_drive_datas *drvp; 1693 struct pciide_channel *cp = (struct pciide_channel*)chp; 1694 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1695 1696 idedma_ctl = 0; 1697 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1698 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1699 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1700 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1701 1702 /* setup DMA if needed */ 1703 pciide_channel_dma_setup(cp); 1704 1705 for (drive = 0; drive < 2; drive++) { 1706 drvp = &chp->ch_drive[drive]; 1707 /* If no drive, skip */ 1708 if ((drvp->drive_flags & DRIVE) == 0) 1709 continue; 1710 /* add timing values, setup DMA if needed */ 1711 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1712 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1713 mode = drvp->PIO_mode; 1714 goto pio; 1715 } 1716 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1717 (drvp->drive_flags & DRIVE_UDMA)) { 1718 /* use Ultra/DMA */ 1719 drvp->drive_flags &= ~DRIVE_DMA; 1720 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1721 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1722 AMD756_UDMA_TIME(chp->channel, drive, 1723 amd756_udma_tim[drvp->UDMA_mode]); 1724 /* can use PIO timings, MW DMA unused */ 1725 mode = drvp->PIO_mode; 1726 } else { 1727 /* use Multiword DMA */ 1728 drvp->drive_flags &= ~DRIVE_UDMA; 1729 /* mode = min(pio, dma+2) */ 1730 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1731 mode = drvp->PIO_mode; 1732 else 1733 mode = drvp->DMA_mode + 2; 1734 } 1735 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1736 1737 pio: /* setup PIO mode */ 1738 if (mode <= 2) { 1739 drvp->DMA_mode = 0; 1740 drvp->PIO_mode = 0; 1741 mode = 0; 1742 } else { 1743 drvp->PIO_mode = mode; 1744 drvp->DMA_mode = mode - 2; 1745 } 1746 datatim_reg |= 1747 AMD756_DATATIM_PULSE(chp->channel, drive, 1748 amd756_pio_set[mode]) | 1749 AMD756_DATATIM_RECOV(chp->channel, drive, 1750 amd756_pio_rec[mode]); 1751 } 1752 if (idedma_ctl != 0) { 1753 /* Add software bits in status register */ 1754 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1755 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1756 idedma_ctl); 1757 } 1758 pciide_print_modes(cp); 1759 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1760 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1761 } 1762 1763 void 1764 apollo_chip_map(sc, pa) 1765 struct pciide_softc *sc; 1766 struct pci_attach_args *pa; 1767 { 1768 struct pciide_channel *cp; 1769 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1770 sc->sc_tag, PCI_CLASS_REG)); 1771 int channel; 1772 u_int32_t ideconf; 1773 bus_size_t cmdsize, ctlsize; 1774 1775 if (pciide_chipen(sc, pa) == 0) 1776 return; 1777 printf("%s: bus-master DMA support present", 1778 sc->sc_wdcdev.sc_dev.dv_xname); 1779 pciide_mapreg_dma(sc, pa); 1780 printf("\n"); 1781 if (sc->sc_dma_ok) { 1782 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1783 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1784 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1785 } 1786 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE; 1787 sc->sc_wdcdev.PIO_cap = 4; 1788 sc->sc_wdcdev.DMA_cap = 2; 1789 sc->sc_wdcdev.UDMA_cap = 2; 1790 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1791 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1792 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1793 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1794 1795 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1796 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1797 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1798 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1799 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1800 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1801 DEBUG_PROBE); 1802 1803 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1804 cp = &sc->pciide_channels[channel]; 1805 if (pciide_chansetup(sc, channel, interface) == 0) 1806 continue; 1807 1808 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1809 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1810 printf("%s: %s channel ignored (disabled)\n", 1811 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1812 continue; 1813 } 1814 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1815 pciide_pci_intr); 1816 if (cp->hw_ok == 0) 1817 continue; 1818 if (pciiide_chan_candisable(cp)) { 1819 ideconf &= ~APO_IDECONF_EN(channel); 1820 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1821 ideconf); 1822 } 1823 pciide_map_compat_intr(pa, cp, channel, interface); 1824 1825 if (cp->hw_ok == 0) 1826 continue; 1827 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1828 } 1829 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1830 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1831 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1832 } 1833 1834 void 1835 apollo_setup_channel(chp) 1836 struct channel_softc *chp; 1837 { 1838 u_int32_t udmatim_reg, datatim_reg; 1839 u_int8_t idedma_ctl; 1840 int mode, drive; 1841 struct ata_drive_datas *drvp; 1842 struct pciide_channel *cp = (struct pciide_channel*)chp; 1843 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1844 1845 idedma_ctl = 0; 1846 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1847 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1848 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1849 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1850 1851 /* setup DMA if needed */ 1852 pciide_channel_dma_setup(cp); 1853 1854 for (drive = 0; drive < 2; drive++) { 1855 drvp = &chp->ch_drive[drive]; 1856 /* If no drive, skip */ 1857 if ((drvp->drive_flags & DRIVE) == 0) 1858 continue; 1859 /* add timing values, setup DMA if needed */ 1860 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1861 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1862 mode = drvp->PIO_mode; 1863 goto pio; 1864 } 1865 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1866 (drvp->drive_flags & DRIVE_UDMA)) { 1867 /* use Ultra/DMA */ 1868 drvp->drive_flags &= ~DRIVE_DMA; 1869 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1870 APO_UDMA_EN_MTH(chp->channel, drive) | 1871 APO_UDMA_TIME(chp->channel, drive, 1872 apollo_udma_tim[drvp->UDMA_mode]); 1873 /* can use PIO timings, MW DMA unused */ 1874 mode = drvp->PIO_mode; 1875 } else { 1876 /* use Multiword DMA */ 1877 drvp->drive_flags &= ~DRIVE_UDMA; 1878 /* mode = min(pio, dma+2) */ 1879 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1880 mode = drvp->PIO_mode; 1881 else 1882 mode = drvp->DMA_mode + 2; 1883 } 1884 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1885 1886 pio: /* setup PIO mode */ 1887 if (mode <= 2) { 1888 drvp->DMA_mode = 0; 1889 drvp->PIO_mode = 0; 1890 mode = 0; 1891 } else { 1892 drvp->PIO_mode = mode; 1893 drvp->DMA_mode = mode - 2; 1894 } 1895 datatim_reg |= 1896 APO_DATATIM_PULSE(chp->channel, drive, 1897 apollo_pio_set[mode]) | 1898 APO_DATATIM_RECOV(chp->channel, drive, 1899 apollo_pio_rec[mode]); 1900 } 1901 if (idedma_ctl != 0) { 1902 /* Add software bits in status register */ 1903 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1904 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1905 idedma_ctl); 1906 } 1907 pciide_print_modes(cp); 1908 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 1909 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 1910 } 1911 1912 void 1913 cmd_channel_map(pa, sc, channel) 1914 struct pci_attach_args *pa; 1915 struct pciide_softc *sc; 1916 int channel; 1917 { 1918 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1919 bus_size_t cmdsize, ctlsize; 1920 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 1921 int interface = 1922 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1923 1924 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1925 cp->name = PCIIDE_CHANNEL_NAME(channel); 1926 cp->wdc_channel.channel = channel; 1927 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1928 1929 if (channel > 0) { 1930 cp->wdc_channel.ch_queue = 1931 sc->pciide_channels[0].wdc_channel.ch_queue; 1932 } else { 1933 cp->wdc_channel.ch_queue = 1934 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1935 } 1936 if (cp->wdc_channel.ch_queue == NULL) { 1937 printf("%s %s channel: " 1938 "can't allocate memory for command queue", 1939 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1940 return; 1941 } 1942 1943 printf("%s: %s channel %s to %s mode\n", 1944 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1945 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1946 "configured" : "wired", 1947 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1948 "native-PCI" : "compatibility"); 1949 1950 /* 1951 * with a CMD PCI64x, if we get here, the first channel is enabled: 1952 * there's no way to disable the first channel without disabling 1953 * the whole device 1954 */ 1955 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 1956 printf("%s: %s channel ignored (disabled)\n", 1957 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1958 return; 1959 } 1960 1961 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 1962 if (cp->hw_ok == 0) 1963 return; 1964 if (channel == 1) { 1965 if (pciiide_chan_candisable(cp)) { 1966 ctrl &= ~CMD_CTRL_2PORT; 1967 pciide_pci_write(pa->pa_pc, pa->pa_tag, 1968 CMD_CTRL, ctrl); 1969 } 1970 } 1971 pciide_map_compat_intr(pa, cp, channel, interface); 1972 } 1973 1974 int 1975 cmd_pci_intr(arg) 1976 void *arg; 1977 { 1978 struct pciide_softc *sc = arg; 1979 struct pciide_channel *cp; 1980 struct channel_softc *wdc_cp; 1981 int i, rv, crv; 1982 u_int32_t priirq, secirq; 1983 1984 rv = 0; 1985 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 1986 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 1987 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1988 cp = &sc->pciide_channels[i]; 1989 wdc_cp = &cp->wdc_channel; 1990 /* If a compat channel skip. */ 1991 if (cp->compat) 1992 continue; 1993 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 1994 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 1995 crv = wdcintr(wdc_cp); 1996 if (crv == 0) 1997 printf("%s:%d: bogus intr\n", 1998 sc->sc_wdcdev.sc_dev.dv_xname, i); 1999 else 2000 rv = 1; 2001 } 2002 } 2003 return rv; 2004 } 2005 2006 void 2007 cmd_chip_map(sc, pa) 2008 struct pciide_softc *sc; 2009 struct pci_attach_args *pa; 2010 { 2011 int channel; 2012 2013 /* 2014 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2015 * and base adresses registers can be disabled at 2016 * hardware level. In this case, the device is wired 2017 * in compat mode and its first channel is always enabled, 2018 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2019 * In fact, it seems that the first channel of the CMD PCI0640 2020 * can't be disabled. 2021 */ 2022 2023 #ifdef PCIIDE_CMD064x_DISABLE 2024 if (pciide_chipen(sc, pa) == 0) 2025 return; 2026 #endif 2027 2028 printf("%s: hardware does not support DMA\n", 2029 sc->sc_wdcdev.sc_dev.dv_xname); 2030 sc->sc_dma_ok = 0; 2031 2032 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2033 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2034 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 2035 2036 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2037 cmd_channel_map(pa, sc, channel); 2038 } 2039 } 2040 2041 void 2042 cmd0643_6_chip_map(sc, pa) 2043 struct pciide_softc *sc; 2044 struct pci_attach_args *pa; 2045 { 2046 struct pciide_channel *cp; 2047 int channel; 2048 2049 /* 2050 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2051 * and base adresses registers can be disabled at 2052 * hardware level. In this case, the device is wired 2053 * in compat mode and its first channel is always enabled, 2054 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2055 * In fact, it seems that the first channel of the CMD PCI0640 2056 * can't be disabled. 2057 */ 2058 2059 #ifdef PCIIDE_CMD064x_DISABLE 2060 if (pciide_chipen(sc, pa) == 0) 2061 return; 2062 #endif 2063 printf("%s: bus-master DMA support present", 2064 sc->sc_wdcdev.sc_dev.dv_xname); 2065 pciide_mapreg_dma(sc, pa); 2066 printf("\n"); 2067 if (sc->sc_dma_ok) 2068 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2069 2070 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2071 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2072 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2073 WDC_CAPABILITY_MODE; 2074 sc->sc_wdcdev.PIO_cap = 4; 2075 sc->sc_wdcdev.DMA_cap = 2; 2076 sc->sc_wdcdev.set_modes = cmd0643_6_setup_channel; 2077 2078 WDCDEBUG_PRINT(("cmd0643_6_chip_map: old timings reg 0x%x 0x%x\n", 2079 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2080 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2081 DEBUG_PROBE); 2082 2083 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2084 cp = &sc->pciide_channels[channel]; 2085 cmd_channel_map(pa, sc, channel); 2086 if (cp->hw_ok == 0) 2087 continue; 2088 cmd0643_6_setup_channel(&cp->wdc_channel); 2089 } 2090 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2091 WDCDEBUG_PRINT(("cmd0643_6_chip_map: timings reg now 0x%x 0x%x\n", 2092 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2093 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2094 DEBUG_PROBE); 2095 } 2096 2097 void 2098 cmd0643_6_setup_channel(chp) 2099 struct channel_softc *chp; 2100 { 2101 struct ata_drive_datas *drvp; 2102 u_int8_t tim; 2103 u_int32_t idedma_ctl; 2104 int drive; 2105 struct pciide_channel *cp = (struct pciide_channel*)chp; 2106 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2107 2108 idedma_ctl = 0; 2109 /* setup DMA if needed */ 2110 pciide_channel_dma_setup(cp); 2111 2112 for (drive = 0; drive < 2; drive++) { 2113 drvp = &chp->ch_drive[drive]; 2114 /* If no drive, skip */ 2115 if ((drvp->drive_flags & DRIVE) == 0) 2116 continue; 2117 /* add timing values, setup DMA if needed */ 2118 tim = cmd0643_6_data_tim_pio[drvp->PIO_mode]; 2119 if (drvp->drive_flags & DRIVE_DMA) { 2120 /* 2121 * use Multiword DMA. 2122 * Timings will be used for both PIO and DMA, so adjust 2123 * DMA mode if needed 2124 */ 2125 if (drvp->PIO_mode >= 3 && 2126 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2127 drvp->DMA_mode = drvp->PIO_mode - 2; 2128 } 2129 tim = cmd0643_6_data_tim_dma[drvp->DMA_mode]; 2130 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2131 } 2132 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2133 CMD_DATA_TIM(chp->channel, drive), tim); 2134 } 2135 if (idedma_ctl != 0) { 2136 /* Add software bits in status register */ 2137 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2138 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2139 idedma_ctl); 2140 } 2141 pciide_print_modes(cp); 2142 } 2143 2144 void 2145 cy693_chip_map(sc, pa) 2146 struct pciide_softc *sc; 2147 struct pci_attach_args *pa; 2148 { 2149 struct pciide_channel *cp; 2150 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2151 sc->sc_tag, PCI_CLASS_REG)); 2152 int compatchan; 2153 bus_size_t cmdsize, ctlsize; 2154 2155 if (pciide_chipen(sc, pa) == 0) 2156 return; 2157 /* 2158 * this chip has 2 PCI IDE functions, one for primary and one for 2159 * secondary. So we need to call pciide_mapregs_compat() with 2160 * the real channel 2161 */ 2162 if (pa->pa_function == 1) { 2163 compatchan = 0; 2164 } else if (pa->pa_function == 2) { 2165 compatchan = 1; 2166 } else { 2167 printf("%s: unexpected PCI function %d\n", 2168 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2169 return; 2170 } 2171 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2172 printf("%s: bus-master DMA support present", 2173 sc->sc_wdcdev.sc_dev.dv_xname); 2174 pciide_mapreg_dma(sc, pa); 2175 } else { 2176 printf("%s: hardware does not support DMA", 2177 sc->sc_wdcdev.sc_dev.dv_xname); 2178 sc->sc_dma_ok = 0; 2179 } 2180 printf("\n"); 2181 2182 if (sc->sc_dma_ok) 2183 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2184 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2185 WDC_CAPABILITY_MODE; 2186 sc->sc_wdcdev.PIO_cap = 4; 2187 sc->sc_wdcdev.DMA_cap = 2; 2188 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2189 2190 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2191 sc->sc_wdcdev.nchannels = 1; 2192 2193 /* Only one channel for this chip; if we are here it's enabled */ 2194 cp = &sc->pciide_channels[0]; 2195 sc->wdc_chanarray[0] = &cp->wdc_channel; 2196 cp->name = PCIIDE_CHANNEL_NAME(0); 2197 cp->wdc_channel.channel = 0; 2198 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2199 cp->wdc_channel.ch_queue = 2200 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2201 if (cp->wdc_channel.ch_queue == NULL) { 2202 printf("%s primary channel: " 2203 "can't allocate memory for command queue", 2204 sc->sc_wdcdev.sc_dev.dv_xname); 2205 return; 2206 } 2207 printf("%s: primary channel %s to ", 2208 sc->sc_wdcdev.sc_dev.dv_xname, 2209 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2210 "configured" : "wired"); 2211 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2212 printf("native-PCI"); 2213 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2214 pciide_pci_intr); 2215 } else { 2216 printf("compatibility"); 2217 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2218 &cmdsize, &ctlsize); 2219 } 2220 printf(" mode\n"); 2221 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2222 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2223 wdcattach(&cp->wdc_channel); 2224 if (pciiide_chan_candisable(cp)) { 2225 pci_conf_write(sc->sc_pc, sc->sc_tag, 2226 PCI_COMMAND_STATUS_REG, 0); 2227 } 2228 pciide_map_compat_intr(pa, cp, compatchan, interface); 2229 if (cp->hw_ok == 0) 2230 return; 2231 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2232 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2233 cy693_setup_channel(&cp->wdc_channel); 2234 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2235 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2236 } 2237 2238 void 2239 cy693_setup_channel(chp) 2240 struct channel_softc *chp; 2241 { 2242 struct ata_drive_datas *drvp; 2243 int drive; 2244 u_int32_t cy_cmd_ctrl; 2245 u_int32_t idedma_ctl; 2246 struct pciide_channel *cp = (struct pciide_channel*)chp; 2247 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2248 int dma_mode = -1; 2249 2250 cy_cmd_ctrl = idedma_ctl = 0; 2251 2252 /* setup DMA if needed */ 2253 pciide_channel_dma_setup(cp); 2254 2255 for (drive = 0; drive < 2; drive++) { 2256 drvp = &chp->ch_drive[drive]; 2257 /* If no drive, skip */ 2258 if ((drvp->drive_flags & DRIVE) == 0) 2259 continue; 2260 /* add timing values, setup DMA if needed */ 2261 if (drvp->drive_flags & DRIVE_DMA) { 2262 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2263 /* use Multiword DMA */ 2264 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2265 dma_mode = drvp->DMA_mode; 2266 } 2267 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2268 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2269 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2270 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2271 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2272 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2273 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2274 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2275 } 2276 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2277 chp->ch_drive[0].DMA_mode = dma_mode; 2278 chp->ch_drive[1].DMA_mode = dma_mode; 2279 pciide_print_modes(cp); 2280 if (idedma_ctl != 0) { 2281 /* Add software bits in status register */ 2282 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2283 IDEDMA_CTL, idedma_ctl); 2284 } 2285 } 2286 2287 void 2288 sis_chip_map(sc, pa) 2289 struct pciide_softc *sc; 2290 struct pci_attach_args *pa; 2291 { 2292 struct pciide_channel *cp; 2293 int channel; 2294 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2295 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2296 sc->sc_tag, PCI_CLASS_REG)); 2297 pcireg_t rev = PCI_REVISION(pci_conf_read(sc->sc_pc, 2298 sc->sc_tag, PCI_CLASS_REG)); 2299 bus_size_t cmdsize, ctlsize; 2300 2301 if (pciide_chipen(sc, pa) == 0) 2302 return; 2303 printf("%s: bus-master DMA support present", 2304 sc->sc_wdcdev.sc_dev.dv_xname); 2305 pciide_mapreg_dma(sc, pa); 2306 printf("\n"); 2307 if (sc->sc_dma_ok) { 2308 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2309 if (rev >= 0xd0) 2310 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2311 } 2312 2313 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2314 WDC_CAPABILITY_MODE; 2315 sc->sc_wdcdev.PIO_cap = 4; 2316 sc->sc_wdcdev.DMA_cap = 2; 2317 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2318 sc->sc_wdcdev.UDMA_cap = 2; 2319 sc->sc_wdcdev.set_modes = sis_setup_channel; 2320 2321 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2322 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2323 2324 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2325 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2326 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2327 2328 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2329 cp = &sc->pciide_channels[channel]; 2330 if (pciide_chansetup(sc, channel, interface) == 0) 2331 continue; 2332 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2333 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2334 printf("%s: %s channel ignored (disabled)\n", 2335 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2336 continue; 2337 } 2338 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2339 pciide_pci_intr); 2340 if (cp->hw_ok == 0) 2341 continue; 2342 if (pciiide_chan_candisable(cp)) { 2343 if (channel == 0) 2344 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2345 else 2346 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2347 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2348 sis_ctr0); 2349 } 2350 pciide_map_compat_intr(pa, cp, channel, interface); 2351 if (cp->hw_ok == 0) 2352 continue; 2353 sis_setup_channel(&cp->wdc_channel); 2354 } 2355 } 2356 2357 void 2358 sis_setup_channel(chp) 2359 struct channel_softc *chp; 2360 { 2361 struct ata_drive_datas *drvp; 2362 int drive; 2363 u_int32_t sis_tim; 2364 u_int32_t idedma_ctl; 2365 struct pciide_channel *cp = (struct pciide_channel*)chp; 2366 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2367 2368 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2369 "channel %d 0x%x\n", chp->channel, 2370 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2371 DEBUG_PROBE); 2372 sis_tim = 0; 2373 idedma_ctl = 0; 2374 /* setup DMA if needed */ 2375 pciide_channel_dma_setup(cp); 2376 2377 for (drive = 0; drive < 2; drive++) { 2378 drvp = &chp->ch_drive[drive]; 2379 /* If no drive, skip */ 2380 if ((drvp->drive_flags & DRIVE) == 0) 2381 continue; 2382 /* add timing values, setup DMA if needed */ 2383 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2384 (drvp->drive_flags & DRIVE_UDMA) == 0) 2385 goto pio; 2386 2387 if (drvp->drive_flags & DRIVE_UDMA) { 2388 /* use Ultra/DMA */ 2389 drvp->drive_flags &= ~DRIVE_DMA; 2390 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2391 SIS_TIM_UDMA_TIME_OFF(drive); 2392 sis_tim |= SIS_TIM_UDMA_EN(drive); 2393 } else { 2394 /* 2395 * use Multiword DMA 2396 * Timings will be used for both PIO and DMA, 2397 * so adjust DMA mode if needed 2398 */ 2399 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2400 drvp->PIO_mode = drvp->DMA_mode + 2; 2401 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2402 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2403 drvp->PIO_mode - 2 : 0; 2404 if (drvp->DMA_mode == 0) 2405 drvp->PIO_mode = 0; 2406 } 2407 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2408 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2409 SIS_TIM_ACT_OFF(drive); 2410 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2411 SIS_TIM_REC_OFF(drive); 2412 } 2413 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2414 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2415 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2416 if (idedma_ctl != 0) { 2417 /* Add software bits in status register */ 2418 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2419 IDEDMA_CTL, idedma_ctl); 2420 } 2421 pciide_print_modes(cp); 2422 } 2423 2424 void 2425 acer_chip_map(sc, pa) 2426 struct pciide_softc *sc; 2427 struct pci_attach_args *pa; 2428 { 2429 struct pciide_channel *cp; 2430 int channel; 2431 pcireg_t cr, interface; 2432 bus_size_t cmdsize, ctlsize; 2433 2434 if (pciide_chipen(sc, pa) == 0) 2435 return; 2436 printf("%s: bus-master DMA support present", 2437 sc->sc_wdcdev.sc_dev.dv_xname); 2438 pciide_mapreg_dma(sc, pa); 2439 printf("\n"); 2440 if (sc->sc_dma_ok) 2441 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2442 2443 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2444 WDC_CAPABILITY_MODE; 2445 2446 sc->sc_wdcdev.PIO_cap = 4; 2447 sc->sc_wdcdev.DMA_cap = 2; 2448 sc->sc_wdcdev.UDMA_cap = 2; 2449 sc->sc_wdcdev.set_modes = acer_setup_channel; 2450 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2451 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2452 2453 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2454 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2455 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2456 2457 /* Enable "microsoft register bits" R/W. */ 2458 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2459 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2460 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2461 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2462 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2463 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2464 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2465 ~ACER_CHANSTATUSREGS_RO); 2466 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2467 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2468 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2469 /* Don't use cr, re-read the real register content instead */ 2470 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2471 PCI_CLASS_REG)); 2472 2473 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2474 cp = &sc->pciide_channels[channel]; 2475 if (pciide_chansetup(sc, channel, interface) == 0) 2476 continue; 2477 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2478 printf("%s: %s channel ignored (disabled)\n", 2479 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2480 continue; 2481 } 2482 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2483 acer_pci_intr); 2484 if (cp->hw_ok == 0) 2485 continue; 2486 if (pciiide_chan_candisable(cp)) { 2487 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2488 pci_conf_write(sc->sc_pc, sc->sc_tag, 2489 PCI_CLASS_REG, cr); 2490 } 2491 pciide_map_compat_intr(pa, cp, channel, interface); 2492 acer_setup_channel(&cp->wdc_channel); 2493 } 2494 } 2495 2496 void 2497 acer_setup_channel(chp) 2498 struct channel_softc *chp; 2499 { 2500 struct ata_drive_datas *drvp; 2501 int drive; 2502 u_int32_t acer_fifo_udma; 2503 u_int32_t idedma_ctl; 2504 struct pciide_channel *cp = (struct pciide_channel*)chp; 2505 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2506 2507 idedma_ctl = 0; 2508 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2509 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2510 acer_fifo_udma), DEBUG_PROBE); 2511 /* setup DMA if needed */ 2512 pciide_channel_dma_setup(cp); 2513 2514 for (drive = 0; drive < 2; drive++) { 2515 drvp = &chp->ch_drive[drive]; 2516 /* If no drive, skip */ 2517 if ((drvp->drive_flags & DRIVE) == 0) 2518 continue; 2519 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2520 "channel %d drive %d 0x%x\n", chp->channel, drive, 2521 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2522 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2523 /* clear FIFO/DMA mode */ 2524 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2525 ACER_UDMA_EN(chp->channel, drive) | 2526 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2527 2528 /* add timing values, setup DMA if needed */ 2529 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2530 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2531 acer_fifo_udma |= 2532 ACER_FTH_OPL(chp->channel, drive, 0x1); 2533 goto pio; 2534 } 2535 2536 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2537 if (drvp->drive_flags & DRIVE_UDMA) { 2538 /* use Ultra/DMA */ 2539 drvp->drive_flags &= ~DRIVE_DMA; 2540 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2541 acer_fifo_udma |= 2542 ACER_UDMA_TIM(chp->channel, drive, 2543 acer_udma[drvp->UDMA_mode]); 2544 } else { 2545 /* 2546 * use Multiword DMA 2547 * Timings will be used for both PIO and DMA, 2548 * so adjust DMA mode if needed 2549 */ 2550 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2551 drvp->PIO_mode = drvp->DMA_mode + 2; 2552 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2553 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2554 drvp->PIO_mode - 2 : 0; 2555 if (drvp->DMA_mode == 0) 2556 drvp->PIO_mode = 0; 2557 } 2558 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2559 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2560 ACER_IDETIM(chp->channel, drive), 2561 acer_pio[drvp->PIO_mode]); 2562 } 2563 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2564 acer_fifo_udma), DEBUG_PROBE); 2565 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2566 if (idedma_ctl != 0) { 2567 /* Add software bits in status register */ 2568 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2569 IDEDMA_CTL, idedma_ctl); 2570 } 2571 pciide_print_modes(cp); 2572 } 2573 2574 int 2575 acer_pci_intr(arg) 2576 void *arg; 2577 { 2578 struct pciide_softc *sc = arg; 2579 struct pciide_channel *cp; 2580 struct channel_softc *wdc_cp; 2581 int i, rv, crv; 2582 u_int32_t chids; 2583 2584 rv = 0; 2585 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2586 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2587 cp = &sc->pciide_channels[i]; 2588 wdc_cp = &cp->wdc_channel; 2589 /* If a compat channel skip. */ 2590 if (cp->compat) 2591 continue; 2592 if (chids & ACER_CHIDS_INT(i)) { 2593 crv = wdcintr(wdc_cp); 2594 if (crv == 0) 2595 printf("%s:%d: bogus intr\n", 2596 sc->sc_wdcdev.sc_dev.dv_xname, i); 2597 else 2598 rv = 1; 2599 } 2600 } 2601 return rv; 2602 } 2603 2604 /* A macro to test product */ 2605 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 2606 2607 void 2608 pdc202xx_chip_map(sc, pa) 2609 struct pciide_softc *sc; 2610 struct pci_attach_args *pa; 2611 { 2612 struct pciide_channel *cp; 2613 int channel; 2614 pcireg_t interface, st, mode; 2615 bus_size_t cmdsize, ctlsize; 2616 2617 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2618 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 2619 DEBUG_PROBE); 2620 if (pciide_chipen(sc, pa) == 0) 2621 return; 2622 2623 /* turn off RAID mode */ 2624 st &= ~PDC2xx_STATE_IDERAID; 2625 2626 /* 2627 * can't rely on the PCI_CLASS_REG content if the chip was in raid 2628 * mode. We have to fake interface 2629 */ 2630 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 2631 if (st & PDC2xx_STATE_NATIVE) 2632 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2633 2634 printf("%s: bus-master DMA support present", 2635 sc->sc_wdcdev.sc_dev.dv_xname); 2636 pciide_mapreg_dma(sc, pa); 2637 printf("\n"); 2638 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2639 WDC_CAPABILITY_MODE; 2640 if (sc->sc_dma_ok) 2641 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2642 sc->sc_wdcdev.PIO_cap = 4; 2643 sc->sc_wdcdev.DMA_cap = 2; 2644 if (PDC_IS_262(sc)) 2645 sc->sc_wdcdev.UDMA_cap = 4; 2646 else 2647 sc->sc_wdcdev.UDMA_cap = 2; 2648 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 2649 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2650 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2651 2652 /* setup failsafe defaults */ 2653 mode = 0; 2654 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 2655 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 2656 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 2657 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 2658 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2659 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 2660 "initial timings 0x%x, now 0x%x\n", channel, 2661 pci_conf_read(sc->sc_pc, sc->sc_tag, 2662 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 2663 DEBUG_PROBE); 2664 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 2665 mode | PDC2xx_TIM_IORDYp); 2666 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 2667 "initial timings 0x%x, now 0x%x\n", channel, 2668 pci_conf_read(sc->sc_pc, sc->sc_tag, 2669 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 2670 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 2671 mode); 2672 } 2673 2674 mode = PDC2xx_SCR_DMA; 2675 if (PDC_IS_262(sc)) { 2676 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 2677 } else { 2678 /* the BIOS set it up this way */ 2679 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 2680 } 2681 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 2682 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 2683 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 2684 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 2685 DEBUG_PROBE); 2686 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 2687 2688 /* controller initial state register is OK even without BIOS */ 2689 /* Set DMA mode to IDE DMA compatibility */ 2690 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 2691 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 2692 DEBUG_PROBE); 2693 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 2694 mode | 0x1); 2695 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 2696 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 2697 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 2698 mode | 0x1); 2699 2700 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2701 cp = &sc->pciide_channels[channel]; 2702 if (pciide_chansetup(sc, channel, interface) == 0) 2703 continue; 2704 if ((st & (PDC_IS_262(sc) ? 2705 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 2706 printf("%s: %s channel ignored (disabled)\n", 2707 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2708 continue; 2709 } 2710 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2711 pdc202xx_pci_intr); 2712 if (cp->hw_ok == 0) 2713 continue; 2714 if (pciiide_chan_candisable(cp)) 2715 st &= ~(PDC_IS_262(sc) ? 2716 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 2717 pciide_map_compat_intr(pa, cp, channel, interface); 2718 pdc202xx_setup_channel(&cp->wdc_channel); 2719 } 2720 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 2721 DEBUG_PROBE); 2722 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 2723 return; 2724 } 2725 2726 void 2727 pdc202xx_setup_channel(chp) 2728 struct channel_softc *chp; 2729 { 2730 struct ata_drive_datas *drvp; 2731 int drive; 2732 pcireg_t mode, st; 2733 u_int32_t idedma_ctl, scr, atapi; 2734 struct pciide_channel *cp = (struct pciide_channel*)chp; 2735 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2736 int channel = chp->channel; 2737 2738 /* setup DMA if needed */ 2739 pciide_channel_dma_setup(cp); 2740 2741 idedma_ctl = 0; 2742 2743 /* Per channel settings */ 2744 if (PDC_IS_262(sc)) { 2745 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2746 PDC262_U66); 2747 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2748 /* Trimm UDMA mode */ 2749 if ((st & PDC262_STATE_80P(channel)) == 0 || 2750 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 2751 chp->ch_drive[0].UDMA_mode <= 2) || 2752 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 2753 chp->ch_drive[1].UDMA_mode <= 2)) { 2754 if (chp->ch_drive[0].UDMA_mode > 2) 2755 chp->ch_drive[0].UDMA_mode = 2; 2756 if (chp->ch_drive[1].UDMA_mode > 2) 2757 chp->ch_drive[1].UDMA_mode = 2; 2758 } 2759 /* Set U66 if needed */ 2760 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 2761 chp->ch_drive[0].UDMA_mode > 2) || 2762 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 2763 chp->ch_drive[1].UDMA_mode > 2)) 2764 scr |= PDC262_U66_EN(channel); 2765 else 2766 scr &= ~PDC262_U66_EN(channel); 2767 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2768 PDC262_U66, scr); 2769 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 2770 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 2771 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2772 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 2773 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 2774 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 2775 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2776 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 2777 atapi = 0; 2778 else 2779 atapi = PDC262_ATAPI_UDMA; 2780 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 2781 PDC262_ATAPI(channel), atapi); 2782 } 2783 } 2784 for (drive = 0; drive < 2; drive++) { 2785 drvp = &chp->ch_drive[drive]; 2786 /* If no drive, skip */ 2787 if ((drvp->drive_flags & DRIVE) == 0) 2788 continue; 2789 mode = 0; 2790 if (drvp->drive_flags & DRIVE_UDMA) { 2791 mode = PDC2xx_TIM_SET_MB(mode, 2792 pdc2xx_udma_mb[drvp->UDMA_mode]); 2793 mode = PDC2xx_TIM_SET_MC(mode, 2794 pdc2xx_udma_mc[drvp->UDMA_mode]); 2795 drvp->drive_flags &= ~DRIVE_DMA; 2796 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2797 } else if (drvp->drive_flags & DRIVE_DMA) { 2798 mode = PDC2xx_TIM_SET_MB(mode, 2799 pdc2xx_dma_mb[drvp->DMA_mode]); 2800 mode = PDC2xx_TIM_SET_MC(mode, 2801 pdc2xx_dma_mc[drvp->DMA_mode]); 2802 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2803 } else { 2804 mode = PDC2xx_TIM_SET_MB(mode, 2805 pdc2xx_dma_mb[0]); 2806 mode = PDC2xx_TIM_SET_MC(mode, 2807 pdc2xx_dma_mc[0]); 2808 } 2809 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 2810 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 2811 if (drvp->drive_flags & DRIVE_ATA) 2812 mode |= PDC2xx_TIM_PRE; 2813 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 2814 if (drvp->PIO_mode >= 3) { 2815 mode |= PDC2xx_TIM_IORDY; 2816 if (drive == 0) 2817 mode |= PDC2xx_TIM_IORDYp; 2818 } 2819 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 2820 "timings 0x%x\n", 2821 sc->sc_wdcdev.sc_dev.dv_xname, 2822 chp->channel, drive, mode), DEBUG_PROBE); 2823 pci_conf_write(sc->sc_pc, sc->sc_tag, 2824 PDC2xx_TIM(chp->channel, drive), mode); 2825 } 2826 if (idedma_ctl != 0) { 2827 /* Add software bits in status register */ 2828 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2829 IDEDMA_CTL, idedma_ctl); 2830 } 2831 pciide_print_modes(cp); 2832 } 2833 2834 int 2835 pdc202xx_pci_intr(arg) 2836 void *arg; 2837 { 2838 struct pciide_softc *sc = arg; 2839 struct pciide_channel *cp; 2840 struct channel_softc *wdc_cp; 2841 int i, rv, crv; 2842 u_int32_t scr; 2843 2844 rv = 0; 2845 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 2846 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2847 cp = &sc->pciide_channels[i]; 2848 wdc_cp = &cp->wdc_channel; 2849 /* If a compat channel skip. */ 2850 if (cp->compat) 2851 continue; 2852 if (scr & PDC2xx_SCR_INT(i)) { 2853 crv = wdcintr(wdc_cp); 2854 if (crv == 0) 2855 printf("%s:%d: bogus intr\n", 2856 sc->sc_wdcdev.sc_dev.dv_xname, i); 2857 else 2858 rv = 1; 2859 } 2860 } 2861 return rv; 2862 } 2863
Indexes created Thu Oct 02 10:09:58 GMT 2025