pciide.c revision 1.57
1 /* $NetBSD: pciide.c,v 1.57 2000/05/12 17:52:07 thorpej Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 */ 36 37 38 /* 39 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 3. All advertising materials mentioning features or use of this software 50 * must display the following acknowledgement: 51 * This product includes software developed by Christopher G. Demetriou 52 * for the NetBSD Project. 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * PCI IDE controller driver. 70 * 71 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 72 * sys/dev/pci/ppb.c, revision 1.16). 73 * 74 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 75 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 76 * 5/16/94" from the PCI SIG. 77 * 78 */ 79 80 #ifndef WDCDEBUG 81 #define WDCDEBUG 82 #endif 83 84 #define DEBUG_DMA 0x01 85 #define DEBUG_XFERS 0x02 86 #define DEBUG_FUNCS 0x08 87 #define DEBUG_PROBE 0x10 88 #ifdef WDCDEBUG 89 int wdcdebug_pciide_mask = 0; 90 #define WDCDEBUG_PRINT(args, level) \ 91 if (wdcdebug_pciide_mask & (level)) printf args 92 #else 93 #define WDCDEBUG_PRINT(args, level) 94 #endif 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/device.h> 98 #include <sys/malloc.h> 99 100 #include <machine/endian.h> 101 102 #include <vm/vm.h> 103 #include <vm/vm_param.h> 104 #include <vm/vm_kern.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 #include <dev/pci/pcidevs.h> 109 #include <dev/pci/pciidereg.h> 110 #include <dev/pci/pciidevar.h> 111 #include <dev/pci/pciide_piix_reg.h> 112 #include <dev/pci/pciide_amd_reg.h> 113 #include <dev/pci/pciide_apollo_reg.h> 114 #include <dev/pci/pciide_cmd_reg.h> 115 #include <dev/pci/pciide_cy693_reg.h> 116 #include <dev/pci/pciide_sis_reg.h> 117 #include <dev/pci/pciide_acer_reg.h> 118 #include <dev/pci/pciide_pdc202xx_reg.h> 119 120 /* inlines for reading/writing 8-bit PCI registers */ 121 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 122 int)); 123 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 124 int, u_int8_t)); 125 126 static __inline u_int8_t 127 pciide_pci_read(pc, pa, reg) 128 pci_chipset_tag_t pc; 129 pcitag_t pa; 130 int reg; 131 { 132 133 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 134 ((reg & 0x03) * 8) & 0xff); 135 } 136 137 static __inline void 138 pciide_pci_write(pc, pa, reg, val) 139 pci_chipset_tag_t pc; 140 pcitag_t pa; 141 int reg; 142 u_int8_t val; 143 { 144 pcireg_t pcival; 145 146 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 147 pcival &= ~(0xff << ((reg & 0x03) * 8)); 148 pcival |= (val << ((reg & 0x03) * 8)); 149 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 150 } 151 152 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 153 154 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 155 void piix_setup_channel __P((struct channel_softc*)); 156 void piix3_4_setup_channel __P((struct channel_softc*)); 157 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 158 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 159 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 160 161 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 162 void amd756_setup_channel __P((struct channel_softc*)); 163 164 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void apollo_setup_channel __P((struct channel_softc*)); 166 167 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void cmd0643_6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 169 void cmd0643_6_setup_channel __P((struct channel_softc*)); 170 void cmd_channel_map __P((struct pci_attach_args *, 171 struct pciide_softc *, int)); 172 int cmd_pci_intr __P((void *)); 173 174 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 175 void cy693_setup_channel __P((struct channel_softc*)); 176 177 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void sis_setup_channel __P((struct channel_softc*)); 179 180 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void acer_setup_channel __P((struct channel_softc*)); 182 int acer_pci_intr __P((void *)); 183 184 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 185 void pdc202xx_setup_channel __P((struct channel_softc*)); 186 int pdc202xx_pci_intr __P((void *)); 187 188 void pciide_channel_dma_setup __P((struct pciide_channel *)); 189 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 190 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 191 void pciide_dma_start __P((void*, int, int)); 192 int pciide_dma_finish __P((void*, int, int, int)); 193 void pciide_print_modes __P((struct pciide_channel *)); 194 195 struct pciide_product_desc { 196 u_int32_t ide_product; 197 int ide_flags; 198 const char *ide_name; 199 /* map and setup chip, probe drives */ 200 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 201 }; 202 203 /* Flags for ide_flags */ 204 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 205 206 /* Default product description for devices not known from this controller */ 207 const struct pciide_product_desc default_product_desc = { 208 0, 209 0, 210 "Generic PCI IDE controller", 211 default_chip_map, 212 }; 213 214 const struct pciide_product_desc pciide_intel_products[] = { 215 { PCI_PRODUCT_INTEL_82092AA, 216 0, 217 "Intel 82092AA IDE controller", 218 default_chip_map, 219 }, 220 { PCI_PRODUCT_INTEL_82371FB_IDE, 221 0, 222 "Intel 82371FB IDE controller (PIIX)", 223 piix_chip_map, 224 }, 225 { PCI_PRODUCT_INTEL_82371SB_IDE, 226 0, 227 "Intel 82371SB IDE Interface (PIIX3)", 228 piix_chip_map, 229 }, 230 { PCI_PRODUCT_INTEL_82371AB_IDE, 231 0, 232 "Intel 82371AB IDE controller (PIIX4)", 233 piix_chip_map, 234 }, 235 { PCI_PRODUCT_INTEL_82801AA_IDE, 236 0, 237 "Intel 82801AA IDE Controller (ICH)", 238 piix_chip_map, 239 }, 240 { PCI_PRODUCT_INTEL_82801AB_IDE, 241 0, 242 "Intel 82801AB IDE Controller (ICH0)", 243 piix_chip_map, 244 }, 245 { 0, 246 0, 247 NULL, 248 } 249 }; 250 251 const struct pciide_product_desc pciide_amd_products[] = { 252 { PCI_PRODUCT_AMD_PBC756_IDE, 253 0, 254 "Advanced Micro Devices AMD756 IDE Controller", 255 amd756_chip_map 256 }, 257 { 0, 258 0, 259 NULL, 260 } 261 }; 262 263 const struct pciide_product_desc pciide_cmd_products[] = { 264 { PCI_PRODUCT_CMDTECH_640, 265 0, 266 "CMD Technology PCI0640", 267 cmd_chip_map 268 }, 269 { PCI_PRODUCT_CMDTECH_643, 270 0, 271 "CMD Technology PCI0643", 272 cmd0643_6_chip_map, 273 }, 274 { PCI_PRODUCT_CMDTECH_646, 275 0, 276 "CMD Technology PCI0646", 277 cmd0643_6_chip_map, 278 }, 279 { 0, 280 0, 281 NULL, 282 } 283 }; 284 285 const struct pciide_product_desc pciide_via_products[] = { 286 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 287 0, 288 "VIA Technologies VT82C586 (Apollo VP) IDE Controller", 289 apollo_chip_map, 290 }, 291 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 292 0, 293 "VIA Technologies VT82C586A IDE Controller", 294 apollo_chip_map, 295 }, 296 { 0, 297 0, 298 NULL, 299 } 300 }; 301 302 const struct pciide_product_desc pciide_cypress_products[] = { 303 { PCI_PRODUCT_CONTAQ_82C693, 304 0, 305 "Contaq Microsystems CY82C693 IDE Controller", 306 cy693_chip_map, 307 }, 308 { 0, 309 0, 310 NULL, 311 } 312 }; 313 314 const struct pciide_product_desc pciide_sis_products[] = { 315 { PCI_PRODUCT_SIS_5597_IDE, 316 0, 317 "Silicon Integrated System 5597/5598 IDE controller", 318 sis_chip_map, 319 }, 320 { 0, 321 0, 322 NULL, 323 } 324 }; 325 326 const struct pciide_product_desc pciide_acer_products[] = { 327 { PCI_PRODUCT_ALI_M5229, 328 0, 329 "Acer Labs M5229 UDMA IDE Controller", 330 acer_chip_map, 331 }, 332 { 0, 333 0, 334 NULL, 335 } 336 }; 337 338 const struct pciide_product_desc pciide_promise_products[] = { 339 { PCI_PRODUCT_PROMISE_ULTRA33, 340 IDE_PCI_CLASS_OVERRIDE, 341 "Promise Ultra33/ATA Bus Master IDE Accelerator", 342 pdc202xx_chip_map, 343 }, 344 { PCI_PRODUCT_PROMISE_ULTRA66, 345 IDE_PCI_CLASS_OVERRIDE, 346 "Promise Ultra66/ATA Bus Master IDE Accelerator", 347 pdc202xx_chip_map, 348 }, 349 { 0, 350 0, 351 NULL, 352 } 353 }; 354 355 struct pciide_vendor_desc { 356 u_int32_t ide_vendor; 357 const struct pciide_product_desc *ide_products; 358 }; 359 360 const struct pciide_vendor_desc pciide_vendors[] = { 361 { PCI_VENDOR_INTEL, pciide_intel_products }, 362 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 363 { PCI_VENDOR_VIATECH, pciide_via_products }, 364 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 365 { PCI_VENDOR_SIS, pciide_sis_products }, 366 { PCI_VENDOR_ALI, pciide_acer_products }, 367 { PCI_VENDOR_PROMISE, pciide_promise_products }, 368 { PCI_VENDOR_AMD, pciide_amd_products }, 369 { 0, NULL } 370 }; 371 372 /* options passed via the 'flags' config keyword */ 373 #define PCIIDE_OPTIONS_DMA 0x01 374 375 int pciide_match __P((struct device *, struct cfdata *, void *)); 376 void pciide_attach __P((struct device *, struct device *, void *)); 377 378 struct cfattach pciide_ca = { 379 sizeof(struct pciide_softc), pciide_match, pciide_attach 380 }; 381 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 382 int pciide_mapregs_compat __P(( struct pci_attach_args *, 383 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 384 int pciide_mapregs_native __P((struct pci_attach_args *, 385 struct pciide_channel *, bus_size_t *, bus_size_t *, 386 int (*pci_intr) __P((void *)))); 387 void pciide_mapreg_dma __P((struct pciide_softc *, 388 struct pci_attach_args *)); 389 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 390 void pciide_mapchan __P((struct pci_attach_args *, 391 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 392 int (*pci_intr) __P((void *)))); 393 int pciiide_chan_candisable __P((struct pciide_channel *)); 394 void pciide_map_compat_intr __P(( struct pci_attach_args *, 395 struct pciide_channel *, int, int)); 396 int pciide_print __P((void *, const char *pnp)); 397 int pciide_compat_intr __P((void *)); 398 int pciide_pci_intr __P((void *)); 399 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 400 401 const struct pciide_product_desc * 402 pciide_lookup_product(id) 403 u_int32_t id; 404 { 405 const struct pciide_product_desc *pp; 406 const struct pciide_vendor_desc *vp; 407 408 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 409 if (PCI_VENDOR(id) == vp->ide_vendor) 410 break; 411 412 if ((pp = vp->ide_products) == NULL) 413 return NULL; 414 415 for (; pp->ide_name != NULL; pp++) 416 if (PCI_PRODUCT(id) == pp->ide_product) 417 break; 418 419 if (pp->ide_name == NULL) 420 return NULL; 421 return pp; 422 } 423 424 int 425 pciide_match(parent, match, aux) 426 struct device *parent; 427 struct cfdata *match; 428 void *aux; 429 { 430 struct pci_attach_args *pa = aux; 431 const struct pciide_product_desc *pp; 432 433 /* 434 * Check the ID register to see that it's a PCI IDE controller. 435 * If it is, we assume that we can deal with it; it _should_ 436 * work in a standardized way... 437 */ 438 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 439 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 440 return (1); 441 } 442 443 /* 444 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 445 * controllers. Let see if we can deal with it anyway. 446 */ 447 pp = pciide_lookup_product(pa->pa_id); 448 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 449 return (1); 450 } 451 452 return (0); 453 } 454 455 void 456 pciide_attach(parent, self, aux) 457 struct device *parent, *self; 458 void *aux; 459 { 460 struct pci_attach_args *pa = aux; 461 pci_chipset_tag_t pc = pa->pa_pc; 462 pcitag_t tag = pa->pa_tag; 463 struct pciide_softc *sc = (struct pciide_softc *)self; 464 pcireg_t csr; 465 char devinfo[256]; 466 const char *displaydev; 467 468 sc->sc_pp = pciide_lookup_product(pa->pa_id); 469 if (sc->sc_pp == NULL) { 470 sc->sc_pp = &default_product_desc; 471 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 472 displaydev = devinfo; 473 } else 474 displaydev = sc->sc_pp->ide_name; 475 476 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 477 478 sc->sc_pc = pa->pa_pc; 479 sc->sc_tag = pa->pa_tag; 480 #ifdef WDCDEBUG 481 if (wdcdebug_pciide_mask & DEBUG_PROBE) 482 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 483 #endif 484 485 sc->sc_pp->chip_map(sc, pa); 486 487 if (sc->sc_dma_ok) { 488 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 489 csr |= PCI_COMMAND_MASTER_ENABLE; 490 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 491 } 492 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 493 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 494 } 495 496 /* tell wether the chip is enabled or not */ 497 int 498 pciide_chipen(sc, pa) 499 struct pciide_softc *sc; 500 struct pci_attach_args *pa; 501 { 502 pcireg_t csr; 503 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 504 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 505 PCI_COMMAND_STATUS_REG); 506 printf("%s: device disabled (at %s)\n", 507 sc->sc_wdcdev.sc_dev.dv_xname, 508 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 509 "device" : "bridge"); 510 return 0; 511 } 512 return 1; 513 } 514 515 int 516 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 517 struct pci_attach_args *pa; 518 struct pciide_channel *cp; 519 int compatchan; 520 bus_size_t *cmdsizep, *ctlsizep; 521 { 522 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 523 struct channel_softc *wdc_cp = &cp->wdc_channel; 524 525 cp->compat = 1; 526 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 527 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 528 529 wdc_cp->cmd_iot = pa->pa_iot; 530 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 531 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 532 printf("%s: couldn't map %s channel cmd regs\n", 533 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 534 return (0); 535 } 536 537 wdc_cp->ctl_iot = pa->pa_iot; 538 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 539 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 540 printf("%s: couldn't map %s channel ctl regs\n", 541 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 542 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 543 PCIIDE_COMPAT_CMD_SIZE); 544 return (0); 545 } 546 547 return (1); 548 } 549 550 int 551 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 552 struct pci_attach_args * pa; 553 struct pciide_channel *cp; 554 bus_size_t *cmdsizep, *ctlsizep; 555 int (*pci_intr) __P((void *)); 556 { 557 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 558 struct channel_softc *wdc_cp = &cp->wdc_channel; 559 const char *intrstr; 560 pci_intr_handle_t intrhandle; 561 562 cp->compat = 0; 563 564 if (sc->sc_pci_ih == NULL) { 565 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 566 pa->pa_intrline, &intrhandle) != 0) { 567 printf("%s: couldn't map native-PCI interrupt\n", 568 sc->sc_wdcdev.sc_dev.dv_xname); 569 return 0; 570 } 571 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 572 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 573 intrhandle, IPL_BIO, pci_intr, sc); 574 if (sc->sc_pci_ih != NULL) { 575 printf("%s: using %s for native-PCI interrupt\n", 576 sc->sc_wdcdev.sc_dev.dv_xname, 577 intrstr ? intrstr : "unknown interrupt"); 578 } else { 579 printf("%s: couldn't establish native-PCI interrupt", 580 sc->sc_wdcdev.sc_dev.dv_xname); 581 if (intrstr != NULL) 582 printf(" at %s", intrstr); 583 printf("\n"); 584 return 0; 585 } 586 } 587 cp->ih = sc->sc_pci_ih; 588 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 589 PCI_MAPREG_TYPE_IO, 0, 590 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 591 printf("%s: couldn't map %s channel cmd regs\n", 592 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 593 return 0; 594 } 595 596 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 597 PCI_MAPREG_TYPE_IO, 0, 598 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 599 printf("%s: couldn't map %s channel ctl regs\n", 600 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 601 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 602 return 0; 603 } 604 return (1); 605 } 606 607 void 608 pciide_mapreg_dma(sc, pa) 609 struct pciide_softc *sc; 610 struct pci_attach_args *pa; 611 { 612 /* 613 * Map DMA registers 614 * 615 * Note that sc_dma_ok is the right variable to test to see if 616 * DMA can be done. If the interface doesn't support DMA, 617 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 618 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 619 * non-zero if the interface supports DMA and the registers 620 * could be mapped. 621 * 622 * XXX Note that despite the fact that the Bus Master IDE specs 623 * XXX say that "The bus master IDE function uses 16 bytes of IO 624 * XXX space," some controllers (at least the United 625 * XXX Microelectronics UM8886BF) place it in memory space. 626 * XXX eventually, we should probably read the register and check 627 * XXX which type it is. Either that or 'quirk' certain devices. 628 */ 629 sc->sc_dma_ok = (pci_mapreg_map(pa, 630 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0, 631 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 632 sc->sc_dmat = pa->pa_dmat; 633 if (sc->sc_dma_ok == 0) { 634 printf(", but unused (couldn't map registers)"); 635 } else { 636 sc->sc_wdcdev.dma_arg = sc; 637 sc->sc_wdcdev.dma_init = pciide_dma_init; 638 sc->sc_wdcdev.dma_start = pciide_dma_start; 639 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 640 } 641 } 642 int 643 pciide_compat_intr(arg) 644 void *arg; 645 { 646 struct pciide_channel *cp = arg; 647 648 #ifdef DIAGNOSTIC 649 /* should only be called for a compat channel */ 650 if (cp->compat == 0) 651 panic("pciide compat intr called for non-compat chan %p\n", cp); 652 #endif 653 return (wdcintr(&cp->wdc_channel)); 654 } 655 656 int 657 pciide_pci_intr(arg) 658 void *arg; 659 { 660 struct pciide_softc *sc = arg; 661 struct pciide_channel *cp; 662 struct channel_softc *wdc_cp; 663 int i, rv, crv; 664 665 rv = 0; 666 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 667 cp = &sc->pciide_channels[i]; 668 wdc_cp = &cp->wdc_channel; 669 670 /* If a compat channel skip. */ 671 if (cp->compat) 672 continue; 673 /* if this channel not waiting for intr, skip */ 674 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 675 continue; 676 677 crv = wdcintr(wdc_cp); 678 if (crv == 0) 679 ; /* leave rv alone */ 680 else if (crv == 1) 681 rv = 1; /* claim the intr */ 682 else if (rv == 0) /* crv should be -1 in this case */ 683 rv = crv; /* if we've done no better, take it */ 684 } 685 return (rv); 686 } 687 688 void 689 pciide_channel_dma_setup(cp) 690 struct pciide_channel *cp; 691 { 692 int drive; 693 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 694 struct ata_drive_datas *drvp; 695 696 for (drive = 0; drive < 2; drive++) { 697 drvp = &cp->wdc_channel.ch_drive[drive]; 698 /* If no drive, skip */ 699 if ((drvp->drive_flags & DRIVE) == 0) 700 continue; 701 /* setup DMA if needed */ 702 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 703 (drvp->drive_flags & DRIVE_UDMA) == 0) || 704 sc->sc_dma_ok == 0) { 705 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 706 continue; 707 } 708 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 709 != 0) { 710 /* Abort DMA setup */ 711 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 712 continue; 713 } 714 } 715 } 716 717 int 718 pciide_dma_table_setup(sc, channel, drive) 719 struct pciide_softc *sc; 720 int channel, drive; 721 { 722 bus_dma_segment_t seg; 723 int error, rseg; 724 const bus_size_t dma_table_size = 725 sizeof(struct idedma_table) * NIDEDMA_TABLES; 726 struct pciide_dma_maps *dma_maps = 727 &sc->pciide_channels[channel].dma_maps[drive]; 728 729 /* If table was already allocated, just return */ 730 if (dma_maps->dma_table) 731 return 0; 732 733 /* Allocate memory for the DMA tables and map it */ 734 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 735 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 736 BUS_DMA_NOWAIT)) != 0) { 737 printf("%s:%d: unable to allocate table DMA for " 738 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 739 channel, drive, error); 740 return error; 741 } 742 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 743 dma_table_size, 744 (caddr_t *)&dma_maps->dma_table, 745 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 746 printf("%s:%d: unable to map table DMA for" 747 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 748 channel, drive, error); 749 return error; 750 } 751 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 752 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 753 seg.ds_addr), DEBUG_PROBE); 754 755 /* Create and load table DMA map for this disk */ 756 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 757 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 758 &dma_maps->dmamap_table)) != 0) { 759 printf("%s:%d: unable to create table DMA map for " 760 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 761 channel, drive, error); 762 return error; 763 } 764 if ((error = bus_dmamap_load(sc->sc_dmat, 765 dma_maps->dmamap_table, 766 dma_maps->dma_table, 767 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 768 printf("%s:%d: unable to load table DMA map for " 769 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 770 channel, drive, error); 771 return error; 772 } 773 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 774 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 775 /* Create a xfer DMA map for this drive */ 776 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 777 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 778 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 779 &dma_maps->dmamap_xfer)) != 0) { 780 printf("%s:%d: unable to create xfer DMA map for " 781 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 782 channel, drive, error); 783 return error; 784 } 785 return 0; 786 } 787 788 int 789 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 790 void *v; 791 int channel, drive; 792 void *databuf; 793 size_t datalen; 794 int flags; 795 { 796 struct pciide_softc *sc = v; 797 int error, seg; 798 struct pciide_dma_maps *dma_maps = 799 &sc->pciide_channels[channel].dma_maps[drive]; 800 801 error = bus_dmamap_load(sc->sc_dmat, 802 dma_maps->dmamap_xfer, 803 databuf, datalen, NULL, BUS_DMA_NOWAIT); 804 if (error) { 805 printf("%s:%d: unable to load xfer DMA map for" 806 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 807 channel, drive, error); 808 return error; 809 } 810 811 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 812 dma_maps->dmamap_xfer->dm_mapsize, 813 (flags & WDC_DMA_READ) ? 814 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 815 816 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 817 #ifdef DIAGNOSTIC 818 /* A segment must not cross a 64k boundary */ 819 { 820 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 821 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 822 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 823 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 824 printf("pciide_dma: segment %d physical addr 0x%lx" 825 " len 0x%lx not properly aligned\n", 826 seg, phys, len); 827 panic("pciide_dma: buf align"); 828 } 829 } 830 #endif 831 dma_maps->dma_table[seg].base_addr = 832 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 833 dma_maps->dma_table[seg].byte_count = 834 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 835 IDEDMA_BYTE_COUNT_MASK); 836 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 837 seg, le32toh(dma_maps->dma_table[seg].byte_count), 838 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 839 840 } 841 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 842 htole32(IDEDMA_BYTE_COUNT_EOT); 843 844 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 845 dma_maps->dmamap_table->dm_mapsize, 846 BUS_DMASYNC_PREWRITE); 847 848 /* Maps are ready. Start DMA function */ 849 #ifdef DIAGNOSTIC 850 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 851 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 852 dma_maps->dmamap_table->dm_segs[0].ds_addr); 853 panic("pciide_dma_init: table align"); 854 } 855 #endif 856 857 /* Clear status bits */ 858 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 859 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 860 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 861 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 862 /* Write table addr */ 863 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 864 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 865 dma_maps->dmamap_table->dm_segs[0].ds_addr); 866 /* set read/write */ 867 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 868 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 869 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 870 /* remember flags */ 871 dma_maps->dma_flags = flags; 872 return 0; 873 } 874 875 void 876 pciide_dma_start(v, channel, drive) 877 void *v; 878 int channel, drive; 879 { 880 struct pciide_softc *sc = v; 881 882 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 883 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 884 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 885 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 886 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 887 } 888 889 int 890 pciide_dma_finish(v, channel, drive, force) 891 void *v; 892 int channel, drive; 893 int force; 894 { 895 struct pciide_softc *sc = v; 896 u_int8_t status; 897 int error = 0; 898 struct pciide_dma_maps *dma_maps = 899 &sc->pciide_channels[channel].dma_maps[drive]; 900 901 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 902 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 903 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 904 DEBUG_XFERS); 905 906 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 907 return WDC_DMAST_NOIRQ; 908 909 /* stop DMA channel */ 910 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 911 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 912 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 913 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 914 915 /* Clear status bits */ 916 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 917 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 918 status); 919 920 /* Unload the map of the data buffer */ 921 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 922 dma_maps->dmamap_xfer->dm_mapsize, 923 (dma_maps->dma_flags & WDC_DMA_READ) ? 924 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 925 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 926 927 if ((status & IDEDMA_CTL_ERR) != 0) { 928 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 929 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 930 error |= WDC_DMAST_ERR; 931 } 932 933 if ((status & IDEDMA_CTL_INTR) == 0) { 934 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 935 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 936 drive, status); 937 error |= WDC_DMAST_NOIRQ; 938 } 939 940 if ((status & IDEDMA_CTL_ACT) != 0) { 941 /* data underrun, may be a valid condition for ATAPI */ 942 error |= WDC_DMAST_UNDER; 943 } 944 return error; 945 } 946 947 /* some common code used by several chip_map */ 948 int 949 pciide_chansetup(sc, channel, interface) 950 struct pciide_softc *sc; 951 int channel; 952 pcireg_t interface; 953 { 954 struct pciide_channel *cp = &sc->pciide_channels[channel]; 955 sc->wdc_chanarray[channel] = &cp->wdc_channel; 956 cp->name = PCIIDE_CHANNEL_NAME(channel); 957 cp->wdc_channel.channel = channel; 958 cp->wdc_channel.wdc = &sc->sc_wdcdev; 959 cp->wdc_channel.ch_queue = 960 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 961 if (cp->wdc_channel.ch_queue == NULL) { 962 printf("%s %s channel: " 963 "can't allocate memory for command queue", 964 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 965 return 0; 966 } 967 printf("%s: %s channel %s to %s mode\n", 968 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 969 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 970 "configured" : "wired", 971 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 972 "native-PCI" : "compatibility"); 973 return 1; 974 } 975 976 /* some common code used by several chip channel_map */ 977 void 978 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 979 struct pci_attach_args *pa; 980 struct pciide_channel *cp; 981 pcireg_t interface; 982 bus_size_t *cmdsizep, *ctlsizep; 983 int (*pci_intr) __P((void *)); 984 { 985 struct channel_softc *wdc_cp = &cp->wdc_channel; 986 987 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 988 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 989 pci_intr); 990 else 991 cp->hw_ok = pciide_mapregs_compat(pa, cp, 992 wdc_cp->channel, cmdsizep, ctlsizep); 993 994 if (cp->hw_ok == 0) 995 return; 996 wdc_cp->data32iot = wdc_cp->cmd_iot; 997 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 998 wdcattach(wdc_cp); 999 } 1000 1001 /* 1002 * Generic code to call to know if a channel can be disabled. Return 1 1003 * if channel can be disabled, 0 if not 1004 */ 1005 int 1006 pciiide_chan_candisable(cp) 1007 struct pciide_channel *cp; 1008 { 1009 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1010 struct channel_softc *wdc_cp = &cp->wdc_channel; 1011 1012 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1013 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1014 printf("%s: disabling %s channel (no drives)\n", 1015 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1016 cp->hw_ok = 0; 1017 return 1; 1018 } 1019 return 0; 1020 } 1021 1022 /* 1023 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1024 * Set hw_ok=0 on failure 1025 */ 1026 void 1027 pciide_map_compat_intr(pa, cp, compatchan, interface) 1028 struct pci_attach_args *pa; 1029 struct pciide_channel *cp; 1030 int compatchan, interface; 1031 { 1032 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1033 struct channel_softc *wdc_cp = &cp->wdc_channel; 1034 1035 if (cp->hw_ok == 0) 1036 return; 1037 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1038 return; 1039 1040 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1041 pa, compatchan, pciide_compat_intr, cp); 1042 if (cp->ih == NULL) { 1043 printf("%s: no compatibility interrupt for use by %s " 1044 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1045 cp->hw_ok = 0; 1046 } 1047 } 1048 1049 void 1050 pciide_print_modes(cp) 1051 struct pciide_channel *cp; 1052 { 1053 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1054 int drive; 1055 struct channel_softc *chp; 1056 struct ata_drive_datas *drvp; 1057 1058 chp = &cp->wdc_channel; 1059 for (drive = 0; drive < 2; drive++) { 1060 drvp = &chp->ch_drive[drive]; 1061 if ((drvp->drive_flags & DRIVE) == 0) 1062 continue; 1063 printf("%s(%s:%d:%d): using PIO mode %d", 1064 drvp->drv_softc->dv_xname, 1065 sc->sc_wdcdev.sc_dev.dv_xname, 1066 chp->channel, drive, drvp->PIO_mode); 1067 if (drvp->drive_flags & DRIVE_DMA) 1068 printf(", DMA mode %d", drvp->DMA_mode); 1069 if (drvp->drive_flags & DRIVE_UDMA) 1070 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1071 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1072 printf(" (using DMA data transfers)"); 1073 printf("\n"); 1074 } 1075 } 1076 1077 void 1078 default_chip_map(sc, pa) 1079 struct pciide_softc *sc; 1080 struct pci_attach_args *pa; 1081 { 1082 struct pciide_channel *cp; 1083 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1084 sc->sc_tag, PCI_CLASS_REG)); 1085 pcireg_t csr; 1086 int channel, drive; 1087 struct ata_drive_datas *drvp; 1088 u_int8_t idedma_ctl; 1089 bus_size_t cmdsize, ctlsize; 1090 char *failreason; 1091 1092 if (pciide_chipen(sc, pa) == 0) 1093 return; 1094 1095 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1096 printf("%s: bus-master DMA support present", 1097 sc->sc_wdcdev.sc_dev.dv_xname); 1098 if (sc->sc_pp == &default_product_desc && 1099 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1100 PCIIDE_OPTIONS_DMA) == 0) { 1101 printf(", but unused (no driver support)"); 1102 sc->sc_dma_ok = 0; 1103 } else { 1104 pciide_mapreg_dma(sc, pa); 1105 if (sc->sc_dma_ok != 0) 1106 printf(", used without full driver " 1107 "support"); 1108 } 1109 } else { 1110 printf("%s: hardware does not support DMA", 1111 sc->sc_wdcdev.sc_dev.dv_xname); 1112 sc->sc_dma_ok = 0; 1113 } 1114 printf("\n"); 1115 if (sc->sc_dma_ok) 1116 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1117 sc->sc_wdcdev.PIO_cap = 0; 1118 sc->sc_wdcdev.DMA_cap = 0; 1119 1120 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1121 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1122 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1123 1124 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1125 cp = &sc->pciide_channels[channel]; 1126 if (pciide_chansetup(sc, channel, interface) == 0) 1127 continue; 1128 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1129 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1130 &ctlsize, pciide_pci_intr); 1131 } else { 1132 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1133 channel, &cmdsize, &ctlsize); 1134 } 1135 if (cp->hw_ok == 0) 1136 continue; 1137 /* 1138 * Check to see if something appears to be there. 1139 */ 1140 failreason = NULL; 1141 if (!wdcprobe(&cp->wdc_channel)) { 1142 failreason = "not responding; disabled or no drives?"; 1143 goto next; 1144 } 1145 /* 1146 * Now, make sure it's actually attributable to this PCI IDE 1147 * channel by trying to access the channel again while the 1148 * PCI IDE controller's I/O space is disabled. (If the 1149 * channel no longer appears to be there, it belongs to 1150 * this controller.) YUCK! 1151 */ 1152 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1153 PCI_COMMAND_STATUS_REG); 1154 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1155 csr & ~PCI_COMMAND_IO_ENABLE); 1156 if (wdcprobe(&cp->wdc_channel)) 1157 failreason = "other hardware responding at addresses"; 1158 pci_conf_write(sc->sc_pc, sc->sc_tag, 1159 PCI_COMMAND_STATUS_REG, csr); 1160 next: 1161 if (failreason) { 1162 printf("%s: %s channel ignored (%s)\n", 1163 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1164 failreason); 1165 cp->hw_ok = 0; 1166 bus_space_unmap(cp->wdc_channel.cmd_iot, 1167 cp->wdc_channel.cmd_ioh, cmdsize); 1168 bus_space_unmap(cp->wdc_channel.ctl_iot, 1169 cp->wdc_channel.ctl_ioh, ctlsize); 1170 } else { 1171 pciide_map_compat_intr(pa, cp, channel, interface); 1172 } 1173 if (cp->hw_ok) { 1174 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1175 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1176 wdcattach(&cp->wdc_channel); 1177 } 1178 } 1179 1180 if (sc->sc_dma_ok == 0) 1181 return; 1182 1183 /* Allocate DMA maps */ 1184 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1185 idedma_ctl = 0; 1186 cp = &sc->pciide_channels[channel]; 1187 for (drive = 0; drive < 2; drive++) { 1188 drvp = &cp->wdc_channel.ch_drive[drive]; 1189 /* If no drive, skip */ 1190 if ((drvp->drive_flags & DRIVE) == 0) 1191 continue; 1192 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1193 continue; 1194 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1195 /* Abort DMA setup */ 1196 printf("%s:%d:%d: can't allocate DMA maps, " 1197 "using PIO transfers\n", 1198 sc->sc_wdcdev.sc_dev.dv_xname, 1199 channel, drive); 1200 drvp->drive_flags &= ~DRIVE_DMA; 1201 } 1202 printf("%s:%d:%d: using DMA data transfers\n", 1203 sc->sc_wdcdev.sc_dev.dv_xname, 1204 channel, drive); 1205 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1206 } 1207 if (idedma_ctl != 0) { 1208 /* Add software bits in status register */ 1209 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1210 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1211 idedma_ctl); 1212 } 1213 } 1214 } 1215 1216 void 1217 piix_chip_map(sc, pa) 1218 struct pciide_softc *sc; 1219 struct pci_attach_args *pa; 1220 { 1221 struct pciide_channel *cp; 1222 int channel; 1223 u_int32_t idetim; 1224 bus_size_t cmdsize, ctlsize; 1225 1226 if (pciide_chipen(sc, pa) == 0) 1227 return; 1228 1229 printf("%s: bus-master DMA support present", 1230 sc->sc_wdcdev.sc_dev.dv_xname); 1231 pciide_mapreg_dma(sc, pa); 1232 printf("\n"); 1233 if (sc->sc_dma_ok) { 1234 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1235 switch(sc->sc_pp->ide_product) { 1236 case PCI_PRODUCT_INTEL_82371AB_IDE: 1237 case PCI_PRODUCT_INTEL_82801AA_IDE: 1238 case PCI_PRODUCT_INTEL_82801AB_IDE: 1239 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1240 } 1241 } 1242 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1243 WDC_CAPABILITY_MODE; 1244 sc->sc_wdcdev.PIO_cap = 4; 1245 sc->sc_wdcdev.DMA_cap = 2; 1246 sc->sc_wdcdev.UDMA_cap = 1247 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1248 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1249 sc->sc_wdcdev.set_modes = piix_setup_channel; 1250 else 1251 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1252 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1253 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1254 1255 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1256 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1257 DEBUG_PROBE); 1258 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1259 WDCDEBUG_PRINT((", sidetim=0x%x", 1260 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1261 DEBUG_PROBE); 1262 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1263 WDCDEBUG_PRINT((", udamreg 0x%x", 1264 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1265 DEBUG_PROBE); 1266 } 1267 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1268 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1269 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1270 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1271 DEBUG_PROBE); 1272 } 1273 1274 } 1275 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1276 1277 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1278 cp = &sc->pciide_channels[channel]; 1279 /* PIIX is compat-only */ 1280 if (pciide_chansetup(sc, channel, 0) == 0) 1281 continue; 1282 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1283 if ((PIIX_IDETIM_READ(idetim, channel) & 1284 PIIX_IDETIM_IDE) == 0) { 1285 printf("%s: %s channel ignored (disabled)\n", 1286 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1287 continue; 1288 } 1289 /* PIIX are compat-only pciide devices */ 1290 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1291 if (cp->hw_ok == 0) 1292 continue; 1293 if (pciiide_chan_candisable(cp)) { 1294 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1295 channel); 1296 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1297 idetim); 1298 } 1299 pciide_map_compat_intr(pa, cp, channel, 0); 1300 if (cp->hw_ok == 0) 1301 continue; 1302 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1303 } 1304 1305 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1306 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1307 DEBUG_PROBE); 1308 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1309 WDCDEBUG_PRINT((", sidetim=0x%x", 1310 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1311 DEBUG_PROBE); 1312 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1313 WDCDEBUG_PRINT((", udamreg 0x%x", 1314 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1315 DEBUG_PROBE); 1316 } 1317 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1318 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1319 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1320 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1321 DEBUG_PROBE); 1322 } 1323 } 1324 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1325 } 1326 1327 void 1328 piix_setup_channel(chp) 1329 struct channel_softc *chp; 1330 { 1331 u_int8_t mode[2], drive; 1332 u_int32_t oidetim, idetim, idedma_ctl; 1333 struct pciide_channel *cp = (struct pciide_channel*)chp; 1334 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1335 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1336 1337 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1338 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1339 idedma_ctl = 0; 1340 1341 /* set up new idetim: Enable IDE registers decode */ 1342 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1343 chp->channel); 1344 1345 /* setup DMA */ 1346 pciide_channel_dma_setup(cp); 1347 1348 /* 1349 * Here we have to mess up with drives mode: PIIX can't have 1350 * different timings for master and slave drives. 1351 * We need to find the best combination. 1352 */ 1353 1354 /* If both drives supports DMA, take the lower mode */ 1355 if ((drvp[0].drive_flags & DRIVE_DMA) && 1356 (drvp[1].drive_flags & DRIVE_DMA)) { 1357 mode[0] = mode[1] = 1358 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1359 drvp[0].DMA_mode = mode[0]; 1360 drvp[1].DMA_mode = mode[1]; 1361 goto ok; 1362 } 1363 /* 1364 * If only one drive supports DMA, use its mode, and 1365 * put the other one in PIO mode 0 if mode not compatible 1366 */ 1367 if (drvp[0].drive_flags & DRIVE_DMA) { 1368 mode[0] = drvp[0].DMA_mode; 1369 mode[1] = drvp[1].PIO_mode; 1370 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1371 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1372 mode[1] = drvp[1].PIO_mode = 0; 1373 goto ok; 1374 } 1375 if (drvp[1].drive_flags & DRIVE_DMA) { 1376 mode[1] = drvp[1].DMA_mode; 1377 mode[0] = drvp[0].PIO_mode; 1378 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1379 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1380 mode[0] = drvp[0].PIO_mode = 0; 1381 goto ok; 1382 } 1383 /* 1384 * If both drives are not DMA, takes the lower mode, unless 1385 * one of them is PIO mode < 2 1386 */ 1387 if (drvp[0].PIO_mode < 2) { 1388 mode[0] = drvp[0].PIO_mode = 0; 1389 mode[1] = drvp[1].PIO_mode; 1390 } else if (drvp[1].PIO_mode < 2) { 1391 mode[1] = drvp[1].PIO_mode = 0; 1392 mode[0] = drvp[0].PIO_mode; 1393 } else { 1394 mode[0] = mode[1] = 1395 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1396 drvp[0].PIO_mode = mode[0]; 1397 drvp[1].PIO_mode = mode[1]; 1398 } 1399 ok: /* The modes are setup */ 1400 for (drive = 0; drive < 2; drive++) { 1401 if (drvp[drive].drive_flags & DRIVE_DMA) { 1402 idetim |= piix_setup_idetim_timings( 1403 mode[drive], 1, chp->channel); 1404 goto end; 1405 } 1406 } 1407 /* If we are there, none of the drives are DMA */ 1408 if (mode[0] >= 2) 1409 idetim |= piix_setup_idetim_timings( 1410 mode[0], 0, chp->channel); 1411 else 1412 idetim |= piix_setup_idetim_timings( 1413 mode[1], 0, chp->channel); 1414 end: /* 1415 * timing mode is now set up in the controller. Enable 1416 * it per-drive 1417 */ 1418 for (drive = 0; drive < 2; drive++) { 1419 /* If no drive, skip */ 1420 if ((drvp[drive].drive_flags & DRIVE) == 0) 1421 continue; 1422 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1423 if (drvp[drive].drive_flags & DRIVE_DMA) 1424 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1425 } 1426 if (idedma_ctl != 0) { 1427 /* Add software bits in status register */ 1428 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1429 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1430 idedma_ctl); 1431 } 1432 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1433 pciide_print_modes(cp); 1434 } 1435 1436 void 1437 piix3_4_setup_channel(chp) 1438 struct channel_softc *chp; 1439 { 1440 struct ata_drive_datas *drvp; 1441 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1442 struct pciide_channel *cp = (struct pciide_channel*)chp; 1443 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1444 int drive; 1445 int channel = chp->channel; 1446 1447 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1448 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1449 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1450 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1451 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1452 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1453 PIIX_SIDETIM_RTC_MASK(channel)); 1454 1455 idedma_ctl = 0; 1456 /* If channel disabled, no need to go further */ 1457 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1458 return; 1459 /* set up new idetim: Enable IDE registers decode */ 1460 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1461 1462 /* setup DMA if needed */ 1463 pciide_channel_dma_setup(cp); 1464 1465 for (drive = 0; drive < 2; drive++) { 1466 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1467 PIIX_UDMATIM_SET(0x3, channel, drive)); 1468 drvp = &chp->ch_drive[drive]; 1469 /* If no drive, skip */ 1470 if ((drvp->drive_flags & DRIVE) == 0) 1471 continue; 1472 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1473 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1474 goto pio; 1475 1476 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1477 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1478 ideconf |= PIIX_CONFIG_PINGPONG; 1479 } 1480 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1481 /* setup Ultra/66 */ 1482 if (drvp->UDMA_mode > 2 && 1483 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1484 drvp->UDMA_mode = 2; 1485 if (drvp->UDMA_mode > 2) 1486 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1487 else 1488 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1489 } 1490 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1491 (drvp->drive_flags & DRIVE_UDMA)) { 1492 /* use Ultra/DMA */ 1493 drvp->drive_flags &= ~DRIVE_DMA; 1494 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1495 udmareg |= PIIX_UDMATIM_SET( 1496 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1497 } else { 1498 /* use Multiword DMA */ 1499 drvp->drive_flags &= ~DRIVE_UDMA; 1500 if (drive == 0) { 1501 idetim |= piix_setup_idetim_timings( 1502 drvp->DMA_mode, 1, channel); 1503 } else { 1504 sidetim |= piix_setup_sidetim_timings( 1505 drvp->DMA_mode, 1, channel); 1506 idetim =PIIX_IDETIM_SET(idetim, 1507 PIIX_IDETIM_SITRE, channel); 1508 } 1509 } 1510 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1511 1512 pio: /* use PIO mode */ 1513 idetim |= piix_setup_idetim_drvs(drvp); 1514 if (drive == 0) { 1515 idetim |= piix_setup_idetim_timings( 1516 drvp->PIO_mode, 0, channel); 1517 } else { 1518 sidetim |= piix_setup_sidetim_timings( 1519 drvp->PIO_mode, 0, channel); 1520 idetim =PIIX_IDETIM_SET(idetim, 1521 PIIX_IDETIM_SITRE, channel); 1522 } 1523 } 1524 if (idedma_ctl != 0) { 1525 /* Add software bits in status register */ 1526 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1527 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1528 idedma_ctl); 1529 } 1530 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1531 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1532 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1533 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1534 pciide_print_modes(cp); 1535 } 1536 1537 1538 /* setup ISP and RTC fields, based on mode */ 1539 static u_int32_t 1540 piix_setup_idetim_timings(mode, dma, channel) 1541 u_int8_t mode; 1542 u_int8_t dma; 1543 u_int8_t channel; 1544 { 1545 1546 if (dma) 1547 return PIIX_IDETIM_SET(0, 1548 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1549 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1550 channel); 1551 else 1552 return PIIX_IDETIM_SET(0, 1553 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1554 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1555 channel); 1556 } 1557 1558 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1559 static u_int32_t 1560 piix_setup_idetim_drvs(drvp) 1561 struct ata_drive_datas *drvp; 1562 { 1563 u_int32_t ret = 0; 1564 struct channel_softc *chp = drvp->chnl_softc; 1565 u_int8_t channel = chp->channel; 1566 u_int8_t drive = drvp->drive; 1567 1568 /* 1569 * If drive is using UDMA, timings setups are independant 1570 * So just check DMA and PIO here. 1571 */ 1572 if (drvp->drive_flags & DRIVE_DMA) { 1573 /* if mode = DMA mode 0, use compatible timings */ 1574 if ((drvp->drive_flags & DRIVE_DMA) && 1575 drvp->DMA_mode == 0) { 1576 drvp->PIO_mode = 0; 1577 return ret; 1578 } 1579 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1580 /* 1581 * PIO and DMA timings are the same, use fast timings for PIO 1582 * too, else use compat timings. 1583 */ 1584 if ((piix_isp_pio[drvp->PIO_mode] != 1585 piix_isp_dma[drvp->DMA_mode]) || 1586 (piix_rtc_pio[drvp->PIO_mode] != 1587 piix_rtc_dma[drvp->DMA_mode])) 1588 drvp->PIO_mode = 0; 1589 /* if PIO mode <= 2, use compat timings for PIO */ 1590 if (drvp->PIO_mode <= 2) { 1591 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1592 channel); 1593 return ret; 1594 } 1595 } 1596 1597 /* 1598 * Now setup PIO modes. If mode < 2, use compat timings. 1599 * Else enable fast timings. Enable IORDY and prefetch/post 1600 * if PIO mode >= 3. 1601 */ 1602 1603 if (drvp->PIO_mode < 2) 1604 return ret; 1605 1606 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1607 if (drvp->PIO_mode >= 3) { 1608 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1609 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1610 } 1611 return ret; 1612 } 1613 1614 /* setup values in SIDETIM registers, based on mode */ 1615 static u_int32_t 1616 piix_setup_sidetim_timings(mode, dma, channel) 1617 u_int8_t mode; 1618 u_int8_t dma; 1619 u_int8_t channel; 1620 { 1621 if (dma) 1622 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1623 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1624 else 1625 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1626 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1627 } 1628 1629 void 1630 amd756_chip_map(sc, pa) 1631 struct pciide_softc *sc; 1632 struct pci_attach_args *pa; 1633 { 1634 struct pciide_channel *cp; 1635 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1636 sc->sc_tag, PCI_CLASS_REG)); 1637 int channel; 1638 pcireg_t chanenable; 1639 bus_size_t cmdsize, ctlsize; 1640 1641 if (pciide_chipen(sc, pa) == 0) 1642 return; 1643 printf("%s: bus-master DMA support present", 1644 sc->sc_wdcdev.sc_dev.dv_xname); 1645 pciide_mapreg_dma(sc, pa); 1646 printf("\n"); 1647 if (sc->sc_dma_ok) 1648 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1649 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1650 WDC_CAPABILITY_MODE; 1651 sc->sc_wdcdev.PIO_cap = 4; 1652 sc->sc_wdcdev.DMA_cap = 2; 1653 sc->sc_wdcdev.UDMA_cap = 4; 1654 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1655 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1656 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1657 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1658 1659 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1660 DEBUG_PROBE); 1661 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1662 cp = &sc->pciide_channels[channel]; 1663 if (pciide_chansetup(sc, channel, interface) == 0) 1664 continue; 1665 1666 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1667 printf("%s: %s channel ignored (disabled)\n", 1668 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1669 continue; 1670 } 1671 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1672 pciide_pci_intr); 1673 1674 if (pciiide_chan_candisable(cp)) 1675 chanenable &= ~AMD756_CHAN_EN(channel); 1676 pciide_map_compat_intr(pa, cp, channel, interface); 1677 if (cp->hw_ok == 0) 1678 continue; 1679 1680 amd756_setup_channel(&cp->wdc_channel); 1681 } 1682 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1683 chanenable); 1684 return; 1685 } 1686 1687 void 1688 amd756_setup_channel(chp) 1689 struct channel_softc *chp; 1690 { 1691 u_int32_t udmatim_reg, datatim_reg; 1692 u_int8_t idedma_ctl; 1693 int mode, drive; 1694 struct ata_drive_datas *drvp; 1695 struct pciide_channel *cp = (struct pciide_channel*)chp; 1696 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1697 1698 idedma_ctl = 0; 1699 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1700 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1701 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1702 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1703 1704 /* setup DMA if needed */ 1705 pciide_channel_dma_setup(cp); 1706 1707 for (drive = 0; drive < 2; drive++) { 1708 drvp = &chp->ch_drive[drive]; 1709 /* If no drive, skip */ 1710 if ((drvp->drive_flags & DRIVE) == 0) 1711 continue; 1712 /* add timing values, setup DMA if needed */ 1713 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1714 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1715 mode = drvp->PIO_mode; 1716 goto pio; 1717 } 1718 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1719 (drvp->drive_flags & DRIVE_UDMA)) { 1720 /* use Ultra/DMA */ 1721 drvp->drive_flags &= ~DRIVE_DMA; 1722 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1723 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1724 AMD756_UDMA_TIME(chp->channel, drive, 1725 amd756_udma_tim[drvp->UDMA_mode]); 1726 /* can use PIO timings, MW DMA unused */ 1727 mode = drvp->PIO_mode; 1728 } else { 1729 /* use Multiword DMA */ 1730 drvp->drive_flags &= ~DRIVE_UDMA; 1731 /* mode = min(pio, dma+2) */ 1732 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1733 mode = drvp->PIO_mode; 1734 else 1735 mode = drvp->DMA_mode + 2; 1736 } 1737 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1738 1739 pio: /* setup PIO mode */ 1740 if (mode <= 2) { 1741 drvp->DMA_mode = 0; 1742 drvp->PIO_mode = 0; 1743 mode = 0; 1744 } else { 1745 drvp->PIO_mode = mode; 1746 drvp->DMA_mode = mode - 2; 1747 } 1748 datatim_reg |= 1749 AMD756_DATATIM_PULSE(chp->channel, drive, 1750 amd756_pio_set[mode]) | 1751 AMD756_DATATIM_RECOV(chp->channel, drive, 1752 amd756_pio_rec[mode]); 1753 } 1754 if (idedma_ctl != 0) { 1755 /* Add software bits in status register */ 1756 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1757 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1758 idedma_ctl); 1759 } 1760 pciide_print_modes(cp); 1761 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1762 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1763 } 1764 1765 void 1766 apollo_chip_map(sc, pa) 1767 struct pciide_softc *sc; 1768 struct pci_attach_args *pa; 1769 { 1770 struct pciide_channel *cp; 1771 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1772 sc->sc_tag, PCI_CLASS_REG)); 1773 int channel; 1774 u_int32_t ideconf; 1775 bus_size_t cmdsize, ctlsize; 1776 1777 if (pciide_chipen(sc, pa) == 0) 1778 return; 1779 printf("%s: bus-master DMA support present", 1780 sc->sc_wdcdev.sc_dev.dv_xname); 1781 pciide_mapreg_dma(sc, pa); 1782 printf("\n"); 1783 if (sc->sc_dma_ok) { 1784 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1785 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1786 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1787 } 1788 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE; 1789 sc->sc_wdcdev.PIO_cap = 4; 1790 sc->sc_wdcdev.DMA_cap = 2; 1791 sc->sc_wdcdev.UDMA_cap = 2; 1792 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1793 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1794 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1795 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1796 1797 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1798 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1799 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1800 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1801 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1802 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1803 DEBUG_PROBE); 1804 1805 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1806 cp = &sc->pciide_channels[channel]; 1807 if (pciide_chansetup(sc, channel, interface) == 0) 1808 continue; 1809 1810 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1811 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1812 printf("%s: %s channel ignored (disabled)\n", 1813 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1814 continue; 1815 } 1816 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1817 pciide_pci_intr); 1818 if (cp->hw_ok == 0) 1819 continue; 1820 if (pciiide_chan_candisable(cp)) { 1821 ideconf &= ~APO_IDECONF_EN(channel); 1822 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1823 ideconf); 1824 } 1825 pciide_map_compat_intr(pa, cp, channel, interface); 1826 1827 if (cp->hw_ok == 0) 1828 continue; 1829 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1830 } 1831 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1832 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1833 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1834 } 1835 1836 void 1837 apollo_setup_channel(chp) 1838 struct channel_softc *chp; 1839 { 1840 u_int32_t udmatim_reg, datatim_reg; 1841 u_int8_t idedma_ctl; 1842 int mode, drive; 1843 struct ata_drive_datas *drvp; 1844 struct pciide_channel *cp = (struct pciide_channel*)chp; 1845 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1846 1847 idedma_ctl = 0; 1848 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1849 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1850 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1851 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1852 1853 /* setup DMA if needed */ 1854 pciide_channel_dma_setup(cp); 1855 1856 for (drive = 0; drive < 2; drive++) { 1857 drvp = &chp->ch_drive[drive]; 1858 /* If no drive, skip */ 1859 if ((drvp->drive_flags & DRIVE) == 0) 1860 continue; 1861 /* add timing values, setup DMA if needed */ 1862 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1863 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1864 mode = drvp->PIO_mode; 1865 goto pio; 1866 } 1867 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1868 (drvp->drive_flags & DRIVE_UDMA)) { 1869 /* use Ultra/DMA */ 1870 drvp->drive_flags &= ~DRIVE_DMA; 1871 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1872 APO_UDMA_EN_MTH(chp->channel, drive) | 1873 APO_UDMA_TIME(chp->channel, drive, 1874 apollo_udma_tim[drvp->UDMA_mode]); 1875 /* can use PIO timings, MW DMA unused */ 1876 mode = drvp->PIO_mode; 1877 } else { 1878 /* use Multiword DMA */ 1879 drvp->drive_flags &= ~DRIVE_UDMA; 1880 /* mode = min(pio, dma+2) */ 1881 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1882 mode = drvp->PIO_mode; 1883 else 1884 mode = drvp->DMA_mode + 2; 1885 } 1886 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1887 1888 pio: /* setup PIO mode */ 1889 if (mode <= 2) { 1890 drvp->DMA_mode = 0; 1891 drvp->PIO_mode = 0; 1892 mode = 0; 1893 } else { 1894 drvp->PIO_mode = mode; 1895 drvp->DMA_mode = mode - 2; 1896 } 1897 datatim_reg |= 1898 APO_DATATIM_PULSE(chp->channel, drive, 1899 apollo_pio_set[mode]) | 1900 APO_DATATIM_RECOV(chp->channel, drive, 1901 apollo_pio_rec[mode]); 1902 } 1903 if (idedma_ctl != 0) { 1904 /* Add software bits in status register */ 1905 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1906 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1907 idedma_ctl); 1908 } 1909 pciide_print_modes(cp); 1910 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 1911 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 1912 } 1913 1914 void 1915 cmd_channel_map(pa, sc, channel) 1916 struct pci_attach_args *pa; 1917 struct pciide_softc *sc; 1918 int channel; 1919 { 1920 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1921 bus_size_t cmdsize, ctlsize; 1922 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 1923 int interface = 1924 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1925 1926 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1927 cp->name = PCIIDE_CHANNEL_NAME(channel); 1928 cp->wdc_channel.channel = channel; 1929 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1930 1931 if (channel > 0) { 1932 cp->wdc_channel.ch_queue = 1933 sc->pciide_channels[0].wdc_channel.ch_queue; 1934 } else { 1935 cp->wdc_channel.ch_queue = 1936 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1937 } 1938 if (cp->wdc_channel.ch_queue == NULL) { 1939 printf("%s %s channel: " 1940 "can't allocate memory for command queue", 1941 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1942 return; 1943 } 1944 1945 printf("%s: %s channel %s to %s mode\n", 1946 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1947 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1948 "configured" : "wired", 1949 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1950 "native-PCI" : "compatibility"); 1951 1952 /* 1953 * with a CMD PCI64x, if we get here, the first channel is enabled: 1954 * there's no way to disable the first channel without disabling 1955 * the whole device 1956 */ 1957 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 1958 printf("%s: %s channel ignored (disabled)\n", 1959 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1960 return; 1961 } 1962 1963 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 1964 if (cp->hw_ok == 0) 1965 return; 1966 if (channel == 1) { 1967 if (pciiide_chan_candisable(cp)) { 1968 ctrl &= ~CMD_CTRL_2PORT; 1969 pciide_pci_write(pa->pa_pc, pa->pa_tag, 1970 CMD_CTRL, ctrl); 1971 } 1972 } 1973 pciide_map_compat_intr(pa, cp, channel, interface); 1974 } 1975 1976 int 1977 cmd_pci_intr(arg) 1978 void *arg; 1979 { 1980 struct pciide_softc *sc = arg; 1981 struct pciide_channel *cp; 1982 struct channel_softc *wdc_cp; 1983 int i, rv, crv; 1984 u_int32_t priirq, secirq; 1985 1986 rv = 0; 1987 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 1988 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 1989 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1990 cp = &sc->pciide_channels[i]; 1991 wdc_cp = &cp->wdc_channel; 1992 /* If a compat channel skip. */ 1993 if (cp->compat) 1994 continue; 1995 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 1996 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 1997 crv = wdcintr(wdc_cp); 1998 if (crv == 0) 1999 printf("%s:%d: bogus intr\n", 2000 sc->sc_wdcdev.sc_dev.dv_xname, i); 2001 else 2002 rv = 1; 2003 } 2004 } 2005 return rv; 2006 } 2007 2008 void 2009 cmd_chip_map(sc, pa) 2010 struct pciide_softc *sc; 2011 struct pci_attach_args *pa; 2012 { 2013 int channel; 2014 2015 /* 2016 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2017 * and base adresses registers can be disabled at 2018 * hardware level. In this case, the device is wired 2019 * in compat mode and its first channel is always enabled, 2020 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2021 * In fact, it seems that the first channel of the CMD PCI0640 2022 * can't be disabled. 2023 */ 2024 2025 #ifdef PCIIDE_CMD064x_DISABLE 2026 if (pciide_chipen(sc, pa) == 0) 2027 return; 2028 #endif 2029 2030 printf("%s: hardware does not support DMA\n", 2031 sc->sc_wdcdev.sc_dev.dv_xname); 2032 sc->sc_dma_ok = 0; 2033 2034 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2035 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2036 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 2037 2038 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2039 cmd_channel_map(pa, sc, channel); 2040 } 2041 } 2042 2043 void 2044 cmd0643_6_chip_map(sc, pa) 2045 struct pciide_softc *sc; 2046 struct pci_attach_args *pa; 2047 { 2048 struct pciide_channel *cp; 2049 int channel; 2050 2051 /* 2052 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2053 * and base adresses registers can be disabled at 2054 * hardware level. In this case, the device is wired 2055 * in compat mode and its first channel is always enabled, 2056 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2057 * In fact, it seems that the first channel of the CMD PCI0640 2058 * can't be disabled. 2059 */ 2060 2061 #ifdef PCIIDE_CMD064x_DISABLE 2062 if (pciide_chipen(sc, pa) == 0) 2063 return; 2064 #endif 2065 printf("%s: bus-master DMA support present", 2066 sc->sc_wdcdev.sc_dev.dv_xname); 2067 pciide_mapreg_dma(sc, pa); 2068 printf("\n"); 2069 if (sc->sc_dma_ok) 2070 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2071 2072 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2073 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2074 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2075 WDC_CAPABILITY_MODE; 2076 sc->sc_wdcdev.PIO_cap = 4; 2077 sc->sc_wdcdev.DMA_cap = 2; 2078 sc->sc_wdcdev.set_modes = cmd0643_6_setup_channel; 2079 2080 WDCDEBUG_PRINT(("cmd0643_6_chip_map: old timings reg 0x%x 0x%x\n", 2081 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2082 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2083 DEBUG_PROBE); 2084 2085 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2086 cp = &sc->pciide_channels[channel]; 2087 cmd_channel_map(pa, sc, channel); 2088 if (cp->hw_ok == 0) 2089 continue; 2090 cmd0643_6_setup_channel(&cp->wdc_channel); 2091 } 2092 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2093 WDCDEBUG_PRINT(("cmd0643_6_chip_map: timings reg now 0x%x 0x%x\n", 2094 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2095 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2096 DEBUG_PROBE); 2097 } 2098 2099 void 2100 cmd0643_6_setup_channel(chp) 2101 struct channel_softc *chp; 2102 { 2103 struct ata_drive_datas *drvp; 2104 u_int8_t tim; 2105 u_int32_t idedma_ctl; 2106 int drive; 2107 struct pciide_channel *cp = (struct pciide_channel*)chp; 2108 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2109 2110 idedma_ctl = 0; 2111 /* setup DMA if needed */ 2112 pciide_channel_dma_setup(cp); 2113 2114 for (drive = 0; drive < 2; drive++) { 2115 drvp = &chp->ch_drive[drive]; 2116 /* If no drive, skip */ 2117 if ((drvp->drive_flags & DRIVE) == 0) 2118 continue; 2119 /* add timing values, setup DMA if needed */ 2120 tim = cmd0643_6_data_tim_pio[drvp->PIO_mode]; 2121 if (drvp->drive_flags & DRIVE_DMA) { 2122 /* 2123 * use Multiword DMA. 2124 * Timings will be used for both PIO and DMA, so adjust 2125 * DMA mode if needed 2126 */ 2127 if (drvp->PIO_mode >= 3 && 2128 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2129 drvp->DMA_mode = drvp->PIO_mode - 2; 2130 } 2131 tim = cmd0643_6_data_tim_dma[drvp->DMA_mode]; 2132 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2133 } 2134 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2135 CMD_DATA_TIM(chp->channel, drive), tim); 2136 } 2137 if (idedma_ctl != 0) { 2138 /* Add software bits in status register */ 2139 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2140 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2141 idedma_ctl); 2142 } 2143 pciide_print_modes(cp); 2144 } 2145 2146 void 2147 cy693_chip_map(sc, pa) 2148 struct pciide_softc *sc; 2149 struct pci_attach_args *pa; 2150 { 2151 struct pciide_channel *cp; 2152 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2153 sc->sc_tag, PCI_CLASS_REG)); 2154 int compatchan; 2155 bus_size_t cmdsize, ctlsize; 2156 2157 if (pciide_chipen(sc, pa) == 0) 2158 return; 2159 /* 2160 * this chip has 2 PCI IDE functions, one for primary and one for 2161 * secondary. So we need to call pciide_mapregs_compat() with 2162 * the real channel 2163 */ 2164 if (pa->pa_function == 1) { 2165 compatchan = 0; 2166 } else if (pa->pa_function == 2) { 2167 compatchan = 1; 2168 } else { 2169 printf("%s: unexpected PCI function %d\n", 2170 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2171 return; 2172 } 2173 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2174 printf("%s: bus-master DMA support present", 2175 sc->sc_wdcdev.sc_dev.dv_xname); 2176 pciide_mapreg_dma(sc, pa); 2177 } else { 2178 printf("%s: hardware does not support DMA", 2179 sc->sc_wdcdev.sc_dev.dv_xname); 2180 sc->sc_dma_ok = 0; 2181 } 2182 printf("\n"); 2183 2184 if (sc->sc_dma_ok) 2185 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2186 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2187 WDC_CAPABILITY_MODE; 2188 sc->sc_wdcdev.PIO_cap = 4; 2189 sc->sc_wdcdev.DMA_cap = 2; 2190 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2191 2192 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2193 sc->sc_wdcdev.nchannels = 1; 2194 2195 /* Only one channel for this chip; if we are here it's enabled */ 2196 cp = &sc->pciide_channels[0]; 2197 sc->wdc_chanarray[0] = &cp->wdc_channel; 2198 cp->name = PCIIDE_CHANNEL_NAME(0); 2199 cp->wdc_channel.channel = 0; 2200 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2201 cp->wdc_channel.ch_queue = 2202 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2203 if (cp->wdc_channel.ch_queue == NULL) { 2204 printf("%s primary channel: " 2205 "can't allocate memory for command queue", 2206 sc->sc_wdcdev.sc_dev.dv_xname); 2207 return; 2208 } 2209 printf("%s: primary channel %s to ", 2210 sc->sc_wdcdev.sc_dev.dv_xname, 2211 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2212 "configured" : "wired"); 2213 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2214 printf("native-PCI"); 2215 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2216 pciide_pci_intr); 2217 } else { 2218 printf("compatibility"); 2219 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2220 &cmdsize, &ctlsize); 2221 } 2222 printf(" mode\n"); 2223 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2224 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2225 wdcattach(&cp->wdc_channel); 2226 if (pciiide_chan_candisable(cp)) { 2227 pci_conf_write(sc->sc_pc, sc->sc_tag, 2228 PCI_COMMAND_STATUS_REG, 0); 2229 } 2230 pciide_map_compat_intr(pa, cp, compatchan, interface); 2231 if (cp->hw_ok == 0) 2232 return; 2233 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2234 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2235 cy693_setup_channel(&cp->wdc_channel); 2236 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2237 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2238 } 2239 2240 void 2241 cy693_setup_channel(chp) 2242 struct channel_softc *chp; 2243 { 2244 struct ata_drive_datas *drvp; 2245 int drive; 2246 u_int32_t cy_cmd_ctrl; 2247 u_int32_t idedma_ctl; 2248 struct pciide_channel *cp = (struct pciide_channel*)chp; 2249 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2250 int dma_mode = -1; 2251 2252 cy_cmd_ctrl = idedma_ctl = 0; 2253 2254 /* setup DMA if needed */ 2255 pciide_channel_dma_setup(cp); 2256 2257 for (drive = 0; drive < 2; drive++) { 2258 drvp = &chp->ch_drive[drive]; 2259 /* If no drive, skip */ 2260 if ((drvp->drive_flags & DRIVE) == 0) 2261 continue; 2262 /* add timing values, setup DMA if needed */ 2263 if (drvp->drive_flags & DRIVE_DMA) { 2264 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2265 /* use Multiword DMA */ 2266 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2267 dma_mode = drvp->DMA_mode; 2268 } 2269 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2270 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2271 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2272 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2273 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2274 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2275 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2276 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2277 } 2278 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2279 chp->ch_drive[0].DMA_mode = dma_mode; 2280 chp->ch_drive[1].DMA_mode = dma_mode; 2281 pciide_print_modes(cp); 2282 if (idedma_ctl != 0) { 2283 /* Add software bits in status register */ 2284 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2285 IDEDMA_CTL, idedma_ctl); 2286 } 2287 } 2288 2289 void 2290 sis_chip_map(sc, pa) 2291 struct pciide_softc *sc; 2292 struct pci_attach_args *pa; 2293 { 2294 struct pciide_channel *cp; 2295 int channel; 2296 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2297 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2298 sc->sc_tag, PCI_CLASS_REG)); 2299 pcireg_t rev = PCI_REVISION(pci_conf_read(sc->sc_pc, 2300 sc->sc_tag, PCI_CLASS_REG)); 2301 bus_size_t cmdsize, ctlsize; 2302 2303 if (pciide_chipen(sc, pa) == 0) 2304 return; 2305 printf("%s: bus-master DMA support present", 2306 sc->sc_wdcdev.sc_dev.dv_xname); 2307 pciide_mapreg_dma(sc, pa); 2308 printf("\n"); 2309 if (sc->sc_dma_ok) { 2310 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2311 if (rev >= 0xd0) 2312 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2313 } 2314 2315 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2316 WDC_CAPABILITY_MODE; 2317 sc->sc_wdcdev.PIO_cap = 4; 2318 sc->sc_wdcdev.DMA_cap = 2; 2319 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2320 sc->sc_wdcdev.UDMA_cap = 2; 2321 sc->sc_wdcdev.set_modes = sis_setup_channel; 2322 2323 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2324 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2325 2326 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2327 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2328 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2329 2330 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2331 cp = &sc->pciide_channels[channel]; 2332 if (pciide_chansetup(sc, channel, interface) == 0) 2333 continue; 2334 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2335 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2336 printf("%s: %s channel ignored (disabled)\n", 2337 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2338 continue; 2339 } 2340 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2341 pciide_pci_intr); 2342 if (cp->hw_ok == 0) 2343 continue; 2344 if (pciiide_chan_candisable(cp)) { 2345 if (channel == 0) 2346 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2347 else 2348 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2349 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2350 sis_ctr0); 2351 } 2352 pciide_map_compat_intr(pa, cp, channel, interface); 2353 if (cp->hw_ok == 0) 2354 continue; 2355 sis_setup_channel(&cp->wdc_channel); 2356 } 2357 } 2358 2359 void 2360 sis_setup_channel(chp) 2361 struct channel_softc *chp; 2362 { 2363 struct ata_drive_datas *drvp; 2364 int drive; 2365 u_int32_t sis_tim; 2366 u_int32_t idedma_ctl; 2367 struct pciide_channel *cp = (struct pciide_channel*)chp; 2368 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2369 2370 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2371 "channel %d 0x%x\n", chp->channel, 2372 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2373 DEBUG_PROBE); 2374 sis_tim = 0; 2375 idedma_ctl = 0; 2376 /* setup DMA if needed */ 2377 pciide_channel_dma_setup(cp); 2378 2379 for (drive = 0; drive < 2; drive++) { 2380 drvp = &chp->ch_drive[drive]; 2381 /* If no drive, skip */ 2382 if ((drvp->drive_flags & DRIVE) == 0) 2383 continue; 2384 /* add timing values, setup DMA if needed */ 2385 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2386 (drvp->drive_flags & DRIVE_UDMA) == 0) 2387 goto pio; 2388 2389 if (drvp->drive_flags & DRIVE_UDMA) { 2390 /* use Ultra/DMA */ 2391 drvp->drive_flags &= ~DRIVE_DMA; 2392 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2393 SIS_TIM_UDMA_TIME_OFF(drive); 2394 sis_tim |= SIS_TIM_UDMA_EN(drive); 2395 } else { 2396 /* 2397 * use Multiword DMA 2398 * Timings will be used for both PIO and DMA, 2399 * so adjust DMA mode if needed 2400 */ 2401 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2402 drvp->PIO_mode = drvp->DMA_mode + 2; 2403 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2404 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2405 drvp->PIO_mode - 2 : 0; 2406 if (drvp->DMA_mode == 0) 2407 drvp->PIO_mode = 0; 2408 } 2409 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2410 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2411 SIS_TIM_ACT_OFF(drive); 2412 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2413 SIS_TIM_REC_OFF(drive); 2414 } 2415 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2416 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2417 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2418 if (idedma_ctl != 0) { 2419 /* Add software bits in status register */ 2420 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2421 IDEDMA_CTL, idedma_ctl); 2422 } 2423 pciide_print_modes(cp); 2424 } 2425 2426 void 2427 acer_chip_map(sc, pa) 2428 struct pciide_softc *sc; 2429 struct pci_attach_args *pa; 2430 { 2431 struct pciide_channel *cp; 2432 int channel; 2433 pcireg_t cr, interface; 2434 bus_size_t cmdsize, ctlsize; 2435 2436 if (pciide_chipen(sc, pa) == 0) 2437 return; 2438 printf("%s: bus-master DMA support present", 2439 sc->sc_wdcdev.sc_dev.dv_xname); 2440 pciide_mapreg_dma(sc, pa); 2441 printf("\n"); 2442 if (sc->sc_dma_ok) 2443 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2444 2445 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2446 WDC_CAPABILITY_MODE; 2447 2448 sc->sc_wdcdev.PIO_cap = 4; 2449 sc->sc_wdcdev.DMA_cap = 2; 2450 sc->sc_wdcdev.UDMA_cap = 2; 2451 sc->sc_wdcdev.set_modes = acer_setup_channel; 2452 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2453 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2454 2455 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2456 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2457 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2458 2459 /* Enable "microsoft register bits" R/W. */ 2460 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2461 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2462 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2463 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2464 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2465 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2466 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2467 ~ACER_CHANSTATUSREGS_RO); 2468 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2469 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2470 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2471 /* Don't use cr, re-read the real register content instead */ 2472 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2473 PCI_CLASS_REG)); 2474 2475 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2476 cp = &sc->pciide_channels[channel]; 2477 if (pciide_chansetup(sc, channel, interface) == 0) 2478 continue; 2479 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2480 printf("%s: %s channel ignored (disabled)\n", 2481 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2482 continue; 2483 } 2484 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2485 acer_pci_intr); 2486 if (cp->hw_ok == 0) 2487 continue; 2488 if (pciiide_chan_candisable(cp)) { 2489 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2490 pci_conf_write(sc->sc_pc, sc->sc_tag, 2491 PCI_CLASS_REG, cr); 2492 } 2493 pciide_map_compat_intr(pa, cp, channel, interface); 2494 acer_setup_channel(&cp->wdc_channel); 2495 } 2496 } 2497 2498 void 2499 acer_setup_channel(chp) 2500 struct channel_softc *chp; 2501 { 2502 struct ata_drive_datas *drvp; 2503 int drive; 2504 u_int32_t acer_fifo_udma; 2505 u_int32_t idedma_ctl; 2506 struct pciide_channel *cp = (struct pciide_channel*)chp; 2507 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2508 2509 idedma_ctl = 0; 2510 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2511 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2512 acer_fifo_udma), DEBUG_PROBE); 2513 /* setup DMA if needed */ 2514 pciide_channel_dma_setup(cp); 2515 2516 for (drive = 0; drive < 2; drive++) { 2517 drvp = &chp->ch_drive[drive]; 2518 /* If no drive, skip */ 2519 if ((drvp->drive_flags & DRIVE) == 0) 2520 continue; 2521 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2522 "channel %d drive %d 0x%x\n", chp->channel, drive, 2523 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2524 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2525 /* clear FIFO/DMA mode */ 2526 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2527 ACER_UDMA_EN(chp->channel, drive) | 2528 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2529 2530 /* add timing values, setup DMA if needed */ 2531 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2532 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2533 acer_fifo_udma |= 2534 ACER_FTH_OPL(chp->channel, drive, 0x1); 2535 goto pio; 2536 } 2537 2538 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2539 if (drvp->drive_flags & DRIVE_UDMA) { 2540 /* use Ultra/DMA */ 2541 drvp->drive_flags &= ~DRIVE_DMA; 2542 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2543 acer_fifo_udma |= 2544 ACER_UDMA_TIM(chp->channel, drive, 2545 acer_udma[drvp->UDMA_mode]); 2546 } else { 2547 /* 2548 * use Multiword DMA 2549 * Timings will be used for both PIO and DMA, 2550 * so adjust DMA mode if needed 2551 */ 2552 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2553 drvp->PIO_mode = drvp->DMA_mode + 2; 2554 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2555 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2556 drvp->PIO_mode - 2 : 0; 2557 if (drvp->DMA_mode == 0) 2558 drvp->PIO_mode = 0; 2559 } 2560 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2561 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2562 ACER_IDETIM(chp->channel, drive), 2563 acer_pio[drvp->PIO_mode]); 2564 } 2565 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2566 acer_fifo_udma), DEBUG_PROBE); 2567 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2568 if (idedma_ctl != 0) { 2569 /* Add software bits in status register */ 2570 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2571 IDEDMA_CTL, idedma_ctl); 2572 } 2573 pciide_print_modes(cp); 2574 } 2575 2576 int 2577 acer_pci_intr(arg) 2578 void *arg; 2579 { 2580 struct pciide_softc *sc = arg; 2581 struct pciide_channel *cp; 2582 struct channel_softc *wdc_cp; 2583 int i, rv, crv; 2584 u_int32_t chids; 2585 2586 rv = 0; 2587 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2588 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2589 cp = &sc->pciide_channels[i]; 2590 wdc_cp = &cp->wdc_channel; 2591 /* If a compat channel skip. */ 2592 if (cp->compat) 2593 continue; 2594 if (chids & ACER_CHIDS_INT(i)) { 2595 crv = wdcintr(wdc_cp); 2596 if (crv == 0) 2597 printf("%s:%d: bogus intr\n", 2598 sc->sc_wdcdev.sc_dev.dv_xname, i); 2599 else 2600 rv = 1; 2601 } 2602 } 2603 return rv; 2604 } 2605 2606 /* A macro to test product */ 2607 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 2608 2609 void 2610 pdc202xx_chip_map(sc, pa) 2611 struct pciide_softc *sc; 2612 struct pci_attach_args *pa; 2613 { 2614 struct pciide_channel *cp; 2615 int channel; 2616 pcireg_t interface, st, mode; 2617 bus_size_t cmdsize, ctlsize; 2618 2619 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2620 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 2621 DEBUG_PROBE); 2622 if (pciide_chipen(sc, pa) == 0) 2623 return; 2624 2625 /* turn off RAID mode */ 2626 st &= ~PDC2xx_STATE_IDERAID; 2627 2628 /* 2629 * can't rely on the PCI_CLASS_REG content if the chip was in raid 2630 * mode. We have to fake interface 2631 */ 2632 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 2633 if (st & PDC2xx_STATE_NATIVE) 2634 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2635 2636 printf("%s: bus-master DMA support present", 2637 sc->sc_wdcdev.sc_dev.dv_xname); 2638 pciide_mapreg_dma(sc, pa); 2639 printf("\n"); 2640 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2641 WDC_CAPABILITY_MODE; 2642 if (sc->sc_dma_ok) 2643 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2644 sc->sc_wdcdev.PIO_cap = 4; 2645 sc->sc_wdcdev.DMA_cap = 2; 2646 if (PDC_IS_262(sc)) 2647 sc->sc_wdcdev.UDMA_cap = 4; 2648 else 2649 sc->sc_wdcdev.UDMA_cap = 2; 2650 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 2651 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2652 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2653 2654 /* setup failsafe defaults */ 2655 mode = 0; 2656 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 2657 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 2658 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 2659 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 2660 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2661 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 2662 "initial timings 0x%x, now 0x%x\n", channel, 2663 pci_conf_read(sc->sc_pc, sc->sc_tag, 2664 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 2665 DEBUG_PROBE); 2666 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 2667 mode | PDC2xx_TIM_IORDYp); 2668 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 2669 "initial timings 0x%x, now 0x%x\n", channel, 2670 pci_conf_read(sc->sc_pc, sc->sc_tag, 2671 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 2672 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 2673 mode); 2674 } 2675 2676 mode = PDC2xx_SCR_DMA; 2677 if (PDC_IS_262(sc)) { 2678 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 2679 } else { 2680 /* the BIOS set it up this way */ 2681 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 2682 } 2683 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 2684 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 2685 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 2686 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 2687 DEBUG_PROBE); 2688 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 2689 2690 /* controller initial state register is OK even without BIOS */ 2691 /* Set DMA mode to IDE DMA compatibility */ 2692 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 2693 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 2694 DEBUG_PROBE); 2695 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 2696 mode | 0x1); 2697 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 2698 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 2699 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 2700 mode | 0x1); 2701 2702 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2703 cp = &sc->pciide_channels[channel]; 2704 if (pciide_chansetup(sc, channel, interface) == 0) 2705 continue; 2706 if ((st & (PDC_IS_262(sc) ? 2707 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 2708 printf("%s: %s channel ignored (disabled)\n", 2709 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2710 continue; 2711 } 2712 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2713 pdc202xx_pci_intr); 2714 if (cp->hw_ok == 0) 2715 continue; 2716 if (pciiide_chan_candisable(cp)) 2717 st &= ~(PDC_IS_262(sc) ? 2718 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 2719 pciide_map_compat_intr(pa, cp, channel, interface); 2720 pdc202xx_setup_channel(&cp->wdc_channel); 2721 } 2722 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 2723 DEBUG_PROBE); 2724 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 2725 return; 2726 } 2727 2728 void 2729 pdc202xx_setup_channel(chp) 2730 struct channel_softc *chp; 2731 { 2732 struct ata_drive_datas *drvp; 2733 int drive; 2734 pcireg_t mode, st; 2735 u_int32_t idedma_ctl, scr, atapi; 2736 struct pciide_channel *cp = (struct pciide_channel*)chp; 2737 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2738 int channel = chp->channel; 2739 2740 /* setup DMA if needed */ 2741 pciide_channel_dma_setup(cp); 2742 2743 idedma_ctl = 0; 2744 2745 /* Per channel settings */ 2746 if (PDC_IS_262(sc)) { 2747 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2748 PDC262_U66); 2749 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2750 /* Trimm UDMA mode */ 2751 if ((st & PDC262_STATE_80P(channel)) == 0 || 2752 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 2753 chp->ch_drive[0].UDMA_mode <= 2) || 2754 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 2755 chp->ch_drive[1].UDMA_mode <= 2)) { 2756 if (chp->ch_drive[0].UDMA_mode > 2) 2757 chp->ch_drive[0].UDMA_mode = 2; 2758 if (chp->ch_drive[1].UDMA_mode > 2) 2759 chp->ch_drive[1].UDMA_mode = 2; 2760 } 2761 /* Set U66 if needed */ 2762 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 2763 chp->ch_drive[0].UDMA_mode > 2) || 2764 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 2765 chp->ch_drive[1].UDMA_mode > 2)) 2766 scr |= PDC262_U66_EN(channel); 2767 else 2768 scr &= ~PDC262_U66_EN(channel); 2769 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2770 PDC262_U66, scr); 2771 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 2772 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 2773 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2774 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 2775 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 2776 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 2777 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2778 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 2779 atapi = 0; 2780 else 2781 atapi = PDC262_ATAPI_UDMA; 2782 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 2783 PDC262_ATAPI(channel), atapi); 2784 } 2785 } 2786 for (drive = 0; drive < 2; drive++) { 2787 drvp = &chp->ch_drive[drive]; 2788 /* If no drive, skip */ 2789 if ((drvp->drive_flags & DRIVE) == 0) 2790 continue; 2791 mode = 0; 2792 if (drvp->drive_flags & DRIVE_UDMA) { 2793 mode = PDC2xx_TIM_SET_MB(mode, 2794 pdc2xx_udma_mb[drvp->UDMA_mode]); 2795 mode = PDC2xx_TIM_SET_MC(mode, 2796 pdc2xx_udma_mc[drvp->UDMA_mode]); 2797 drvp->drive_flags &= ~DRIVE_DMA; 2798 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2799 } else if (drvp->drive_flags & DRIVE_DMA) { 2800 mode = PDC2xx_TIM_SET_MB(mode, 2801 pdc2xx_dma_mb[drvp->DMA_mode]); 2802 mode = PDC2xx_TIM_SET_MC(mode, 2803 pdc2xx_dma_mc[drvp->DMA_mode]); 2804 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2805 } else { 2806 mode = PDC2xx_TIM_SET_MB(mode, 2807 pdc2xx_dma_mb[0]); 2808 mode = PDC2xx_TIM_SET_MC(mode, 2809 pdc2xx_dma_mc[0]); 2810 } 2811 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 2812 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 2813 if (drvp->drive_flags & DRIVE_ATA) 2814 mode |= PDC2xx_TIM_PRE; 2815 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 2816 if (drvp->PIO_mode >= 3) { 2817 mode |= PDC2xx_TIM_IORDY; 2818 if (drive == 0) 2819 mode |= PDC2xx_TIM_IORDYp; 2820 } 2821 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 2822 "timings 0x%x\n", 2823 sc->sc_wdcdev.sc_dev.dv_xname, 2824 chp->channel, drive, mode), DEBUG_PROBE); 2825 pci_conf_write(sc->sc_pc, sc->sc_tag, 2826 PDC2xx_TIM(chp->channel, drive), mode); 2827 } 2828 if (idedma_ctl != 0) { 2829 /* Add software bits in status register */ 2830 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2831 IDEDMA_CTL, idedma_ctl); 2832 } 2833 pciide_print_modes(cp); 2834 } 2835 2836 int 2837 pdc202xx_pci_intr(arg) 2838 void *arg; 2839 { 2840 struct pciide_softc *sc = arg; 2841 struct pciide_channel *cp; 2842 struct channel_softc *wdc_cp; 2843 int i, rv, crv; 2844 u_int32_t scr; 2845 2846 rv = 0; 2847 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 2848 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2849 cp = &sc->pciide_channels[i]; 2850 wdc_cp = &cp->wdc_channel; 2851 /* If a compat channel skip. */ 2852 if (cp->compat) 2853 continue; 2854 if (scr & PDC2xx_SCR_INT(i)) { 2855 crv = wdcintr(wdc_cp); 2856 if (crv == 0) 2857 printf("%s:%d: bogus intr\n", 2858 sc->sc_wdcdev.sc_dev.dv_xname, i); 2859 else 2860 rv = 1; 2861 } 2862 } 2863 return rv; 2864 } 2865
Indexes created Thu Oct 02 10:09:58 GMT 2025