pciide.c revision 1.58
1 /* $NetBSD: pciide.c,v 1.58 2000/05/15 08:46:00 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <vm/vm.h> 102 #include <vm/vm_param.h> 103 #include <vm/vm_kern.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 119 /* inlines for reading/writing 8-bit PCI registers */ 120 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 121 int)); 122 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 123 int, u_int8_t)); 124 125 static __inline u_int8_t 126 pciide_pci_read(pc, pa, reg) 127 pci_chipset_tag_t pc; 128 pcitag_t pa; 129 int reg; 130 { 131 132 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 133 ((reg & 0x03) * 8) & 0xff); 134 } 135 136 static __inline void 137 pciide_pci_write(pc, pa, reg, val) 138 pci_chipset_tag_t pc; 139 pcitag_t pa; 140 int reg; 141 u_int8_t val; 142 { 143 pcireg_t pcival; 144 145 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 146 pcival &= ~(0xff << ((reg & 0x03) * 8)); 147 pcival |= (val << ((reg & 0x03) * 8)); 148 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 149 } 150 151 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 152 153 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 154 void piix_setup_channel __P((struct channel_softc*)); 155 void piix3_4_setup_channel __P((struct channel_softc*)); 156 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 157 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 158 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 159 160 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 161 void amd756_setup_channel __P((struct channel_softc*)); 162 163 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 164 void apollo_setup_channel __P((struct channel_softc*)); 165 166 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 167 void cmd0643_6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void cmd0643_6_setup_channel __P((struct channel_softc*)); 169 void cmd_channel_map __P((struct pci_attach_args *, 170 struct pciide_softc *, int)); 171 int cmd_pci_intr __P((void *)); 172 173 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cy693_setup_channel __P((struct channel_softc*)); 175 176 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 177 void sis_setup_channel __P((struct channel_softc*)); 178 179 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 180 void acer_setup_channel __P((struct channel_softc*)); 181 int acer_pci_intr __P((void *)); 182 183 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 184 void pdc202xx_setup_channel __P((struct channel_softc*)); 185 int pdc202xx_pci_intr __P((void *)); 186 187 void pciide_channel_dma_setup __P((struct pciide_channel *)); 188 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 189 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 190 void pciide_dma_start __P((void*, int, int)); 191 int pciide_dma_finish __P((void*, int, int, int)); 192 void pciide_print_modes __P((struct pciide_channel *)); 193 194 struct pciide_product_desc { 195 u_int32_t ide_product; 196 int ide_flags; 197 const char *ide_name; 198 /* map and setup chip, probe drives */ 199 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 200 }; 201 202 /* Flags for ide_flags */ 203 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 204 205 /* Default product description for devices not known from this controller */ 206 const struct pciide_product_desc default_product_desc = { 207 0, 208 0, 209 "Generic PCI IDE controller", 210 default_chip_map, 211 }; 212 213 const struct pciide_product_desc pciide_intel_products[] = { 214 { PCI_PRODUCT_INTEL_82092AA, 215 0, 216 "Intel 82092AA IDE controller", 217 default_chip_map, 218 }, 219 { PCI_PRODUCT_INTEL_82371FB_IDE, 220 0, 221 "Intel 82371FB IDE controller (PIIX)", 222 piix_chip_map, 223 }, 224 { PCI_PRODUCT_INTEL_82371SB_IDE, 225 0, 226 "Intel 82371SB IDE Interface (PIIX3)", 227 piix_chip_map, 228 }, 229 { PCI_PRODUCT_INTEL_82371AB_IDE, 230 0, 231 "Intel 82371AB IDE controller (PIIX4)", 232 piix_chip_map, 233 }, 234 { PCI_PRODUCT_INTEL_82801AA_IDE, 235 0, 236 "Intel 82801AA IDE Controller (ICH)", 237 piix_chip_map, 238 }, 239 { PCI_PRODUCT_INTEL_82801AB_IDE, 240 0, 241 "Intel 82801AB IDE Controller (ICH0)", 242 piix_chip_map, 243 }, 244 { 0, 245 0, 246 NULL, 247 } 248 }; 249 250 const struct pciide_product_desc pciide_amd_products[] = { 251 { PCI_PRODUCT_AMD_PBC756_IDE, 252 0, 253 "Advanced Micro Devices AMD756 IDE Controller", 254 amd756_chip_map 255 }, 256 { 0, 257 0, 258 NULL, 259 } 260 }; 261 262 const struct pciide_product_desc pciide_cmd_products[] = { 263 { PCI_PRODUCT_CMDTECH_640, 264 0, 265 "CMD Technology PCI0640", 266 cmd_chip_map 267 }, 268 { PCI_PRODUCT_CMDTECH_643, 269 0, 270 "CMD Technology PCI0643", 271 cmd0643_6_chip_map, 272 }, 273 { PCI_PRODUCT_CMDTECH_646, 274 0, 275 "CMD Technology PCI0646", 276 cmd0643_6_chip_map, 277 }, 278 { 0, 279 0, 280 NULL, 281 } 282 }; 283 284 const struct pciide_product_desc pciide_via_products[] = { 285 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 286 0, 287 "VIA Technologies VT82C586 (Apollo VP) IDE Controller", 288 apollo_chip_map, 289 }, 290 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 291 0, 292 "VIA Technologies VT82C586A IDE Controller", 293 apollo_chip_map, 294 }, 295 { 0, 296 0, 297 NULL, 298 } 299 }; 300 301 const struct pciide_product_desc pciide_cypress_products[] = { 302 { PCI_PRODUCT_CONTAQ_82C693, 303 0, 304 "Contaq Microsystems CY82C693 IDE Controller", 305 cy693_chip_map, 306 }, 307 { 0, 308 0, 309 NULL, 310 } 311 }; 312 313 const struct pciide_product_desc pciide_sis_products[] = { 314 { PCI_PRODUCT_SIS_5597_IDE, 315 0, 316 "Silicon Integrated System 5597/5598 IDE controller", 317 sis_chip_map, 318 }, 319 { 0, 320 0, 321 NULL, 322 } 323 }; 324 325 const struct pciide_product_desc pciide_acer_products[] = { 326 { PCI_PRODUCT_ALI_M5229, 327 0, 328 "Acer Labs M5229 UDMA IDE Controller", 329 acer_chip_map, 330 }, 331 { 0, 332 0, 333 NULL, 334 } 335 }; 336 337 const struct pciide_product_desc pciide_promise_products[] = { 338 { PCI_PRODUCT_PROMISE_ULTRA33, 339 IDE_PCI_CLASS_OVERRIDE, 340 "Promise Ultra33/ATA Bus Master IDE Accelerator", 341 pdc202xx_chip_map, 342 }, 343 { PCI_PRODUCT_PROMISE_ULTRA66, 344 IDE_PCI_CLASS_OVERRIDE, 345 "Promise Ultra66/ATA Bus Master IDE Accelerator", 346 pdc202xx_chip_map, 347 }, 348 { 0, 349 0, 350 NULL, 351 } 352 }; 353 354 struct pciide_vendor_desc { 355 u_int32_t ide_vendor; 356 const struct pciide_product_desc *ide_products; 357 }; 358 359 const struct pciide_vendor_desc pciide_vendors[] = { 360 { PCI_VENDOR_INTEL, pciide_intel_products }, 361 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 362 { PCI_VENDOR_VIATECH, pciide_via_products }, 363 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 364 { PCI_VENDOR_SIS, pciide_sis_products }, 365 { PCI_VENDOR_ALI, pciide_acer_products }, 366 { PCI_VENDOR_PROMISE, pciide_promise_products }, 367 { PCI_VENDOR_AMD, pciide_amd_products }, 368 { 0, NULL } 369 }; 370 371 /* options passed via the 'flags' config keyword */ 372 #define PCIIDE_OPTIONS_DMA 0x01 373 374 int pciide_match __P((struct device *, struct cfdata *, void *)); 375 void pciide_attach __P((struct device *, struct device *, void *)); 376 377 struct cfattach pciide_ca = { 378 sizeof(struct pciide_softc), pciide_match, pciide_attach 379 }; 380 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 381 int pciide_mapregs_compat __P(( struct pci_attach_args *, 382 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 383 int pciide_mapregs_native __P((struct pci_attach_args *, 384 struct pciide_channel *, bus_size_t *, bus_size_t *, 385 int (*pci_intr) __P((void *)))); 386 void pciide_mapreg_dma __P((struct pciide_softc *, 387 struct pci_attach_args *)); 388 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 389 void pciide_mapchan __P((struct pci_attach_args *, 390 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 391 int (*pci_intr) __P((void *)))); 392 int pciiide_chan_candisable __P((struct pciide_channel *)); 393 void pciide_map_compat_intr __P(( struct pci_attach_args *, 394 struct pciide_channel *, int, int)); 395 int pciide_print __P((void *, const char *pnp)); 396 int pciide_compat_intr __P((void *)); 397 int pciide_pci_intr __P((void *)); 398 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 399 400 const struct pciide_product_desc * 401 pciide_lookup_product(id) 402 u_int32_t id; 403 { 404 const struct pciide_product_desc *pp; 405 const struct pciide_vendor_desc *vp; 406 407 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 408 if (PCI_VENDOR(id) == vp->ide_vendor) 409 break; 410 411 if ((pp = vp->ide_products) == NULL) 412 return NULL; 413 414 for (; pp->ide_name != NULL; pp++) 415 if (PCI_PRODUCT(id) == pp->ide_product) 416 break; 417 418 if (pp->ide_name == NULL) 419 return NULL; 420 return pp; 421 } 422 423 int 424 pciide_match(parent, match, aux) 425 struct device *parent; 426 struct cfdata *match; 427 void *aux; 428 { 429 struct pci_attach_args *pa = aux; 430 const struct pciide_product_desc *pp; 431 432 /* 433 * Check the ID register to see that it's a PCI IDE controller. 434 * If it is, we assume that we can deal with it; it _should_ 435 * work in a standardized way... 436 */ 437 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 438 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 439 return (1); 440 } 441 442 /* 443 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 444 * controllers. Let see if we can deal with it anyway. 445 */ 446 pp = pciide_lookup_product(pa->pa_id); 447 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 448 return (1); 449 } 450 451 return (0); 452 } 453 454 void 455 pciide_attach(parent, self, aux) 456 struct device *parent, *self; 457 void *aux; 458 { 459 struct pci_attach_args *pa = aux; 460 pci_chipset_tag_t pc = pa->pa_pc; 461 pcitag_t tag = pa->pa_tag; 462 struct pciide_softc *sc = (struct pciide_softc *)self; 463 pcireg_t csr; 464 char devinfo[256]; 465 const char *displaydev; 466 467 sc->sc_pp = pciide_lookup_product(pa->pa_id); 468 if (sc->sc_pp == NULL) { 469 sc->sc_pp = &default_product_desc; 470 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 471 displaydev = devinfo; 472 } else 473 displaydev = sc->sc_pp->ide_name; 474 475 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 476 477 sc->sc_pc = pa->pa_pc; 478 sc->sc_tag = pa->pa_tag; 479 #ifdef WDCDEBUG 480 if (wdcdebug_pciide_mask & DEBUG_PROBE) 481 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 482 #endif 483 484 sc->sc_pp->chip_map(sc, pa); 485 486 if (sc->sc_dma_ok) { 487 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 488 csr |= PCI_COMMAND_MASTER_ENABLE; 489 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 490 } 491 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 492 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 493 } 494 495 /* tell wether the chip is enabled or not */ 496 int 497 pciide_chipen(sc, pa) 498 struct pciide_softc *sc; 499 struct pci_attach_args *pa; 500 { 501 pcireg_t csr; 502 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 503 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 504 PCI_COMMAND_STATUS_REG); 505 printf("%s: device disabled (at %s)\n", 506 sc->sc_wdcdev.sc_dev.dv_xname, 507 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 508 "device" : "bridge"); 509 return 0; 510 } 511 return 1; 512 } 513 514 int 515 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 516 struct pci_attach_args *pa; 517 struct pciide_channel *cp; 518 int compatchan; 519 bus_size_t *cmdsizep, *ctlsizep; 520 { 521 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 522 struct channel_softc *wdc_cp = &cp->wdc_channel; 523 524 cp->compat = 1; 525 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 526 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 527 528 wdc_cp->cmd_iot = pa->pa_iot; 529 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 530 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 531 printf("%s: couldn't map %s channel cmd regs\n", 532 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 533 return (0); 534 } 535 536 wdc_cp->ctl_iot = pa->pa_iot; 537 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 538 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 539 printf("%s: couldn't map %s channel ctl regs\n", 540 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 541 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 542 PCIIDE_COMPAT_CMD_SIZE); 543 return (0); 544 } 545 546 return (1); 547 } 548 549 int 550 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 551 struct pci_attach_args * pa; 552 struct pciide_channel *cp; 553 bus_size_t *cmdsizep, *ctlsizep; 554 int (*pci_intr) __P((void *)); 555 { 556 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 557 struct channel_softc *wdc_cp = &cp->wdc_channel; 558 const char *intrstr; 559 pci_intr_handle_t intrhandle; 560 561 cp->compat = 0; 562 563 if (sc->sc_pci_ih == NULL) { 564 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 565 pa->pa_intrline, &intrhandle) != 0) { 566 printf("%s: couldn't map native-PCI interrupt\n", 567 sc->sc_wdcdev.sc_dev.dv_xname); 568 return 0; 569 } 570 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 571 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 572 intrhandle, IPL_BIO, pci_intr, sc); 573 if (sc->sc_pci_ih != NULL) { 574 printf("%s: using %s for native-PCI interrupt\n", 575 sc->sc_wdcdev.sc_dev.dv_xname, 576 intrstr ? intrstr : "unknown interrupt"); 577 } else { 578 printf("%s: couldn't establish native-PCI interrupt", 579 sc->sc_wdcdev.sc_dev.dv_xname); 580 if (intrstr != NULL) 581 printf(" at %s", intrstr); 582 printf("\n"); 583 return 0; 584 } 585 } 586 cp->ih = sc->sc_pci_ih; 587 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 588 PCI_MAPREG_TYPE_IO, 0, 589 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 590 printf("%s: couldn't map %s channel cmd regs\n", 591 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 592 return 0; 593 } 594 595 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 596 PCI_MAPREG_TYPE_IO, 0, 597 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 598 printf("%s: couldn't map %s channel ctl regs\n", 599 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 600 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 601 return 0; 602 } 603 return (1); 604 } 605 606 void 607 pciide_mapreg_dma(sc, pa) 608 struct pciide_softc *sc; 609 struct pci_attach_args *pa; 610 { 611 /* 612 * Map DMA registers 613 * 614 * Note that sc_dma_ok is the right variable to test to see if 615 * DMA can be done. If the interface doesn't support DMA, 616 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 617 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 618 * non-zero if the interface supports DMA and the registers 619 * could be mapped. 620 * 621 * XXX Note that despite the fact that the Bus Master IDE specs 622 * XXX say that "The bus master IDE function uses 16 bytes of IO 623 * XXX space," some controllers (at least the United 624 * XXX Microelectronics UM8886BF) place it in memory space. 625 * XXX eventually, we should probably read the register and check 626 * XXX which type it is. Either that or 'quirk' certain devices. 627 */ 628 sc->sc_dma_ok = (pci_mapreg_map(pa, 629 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0, 630 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 631 sc->sc_dmat = pa->pa_dmat; 632 if (sc->sc_dma_ok == 0) { 633 printf(", but unused (couldn't map registers)"); 634 } else { 635 sc->sc_wdcdev.dma_arg = sc; 636 sc->sc_wdcdev.dma_init = pciide_dma_init; 637 sc->sc_wdcdev.dma_start = pciide_dma_start; 638 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 639 } 640 } 641 int 642 pciide_compat_intr(arg) 643 void *arg; 644 { 645 struct pciide_channel *cp = arg; 646 647 #ifdef DIAGNOSTIC 648 /* should only be called for a compat channel */ 649 if (cp->compat == 0) 650 panic("pciide compat intr called for non-compat chan %p\n", cp); 651 #endif 652 return (wdcintr(&cp->wdc_channel)); 653 } 654 655 int 656 pciide_pci_intr(arg) 657 void *arg; 658 { 659 struct pciide_softc *sc = arg; 660 struct pciide_channel *cp; 661 struct channel_softc *wdc_cp; 662 int i, rv, crv; 663 664 rv = 0; 665 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 666 cp = &sc->pciide_channels[i]; 667 wdc_cp = &cp->wdc_channel; 668 669 /* If a compat channel skip. */ 670 if (cp->compat) 671 continue; 672 /* if this channel not waiting for intr, skip */ 673 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 674 continue; 675 676 crv = wdcintr(wdc_cp); 677 if (crv == 0) 678 ; /* leave rv alone */ 679 else if (crv == 1) 680 rv = 1; /* claim the intr */ 681 else if (rv == 0) /* crv should be -1 in this case */ 682 rv = crv; /* if we've done no better, take it */ 683 } 684 return (rv); 685 } 686 687 void 688 pciide_channel_dma_setup(cp) 689 struct pciide_channel *cp; 690 { 691 int drive; 692 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 693 struct ata_drive_datas *drvp; 694 695 for (drive = 0; drive < 2; drive++) { 696 drvp = &cp->wdc_channel.ch_drive[drive]; 697 /* If no drive, skip */ 698 if ((drvp->drive_flags & DRIVE) == 0) 699 continue; 700 /* setup DMA if needed */ 701 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 702 (drvp->drive_flags & DRIVE_UDMA) == 0) || 703 sc->sc_dma_ok == 0) { 704 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 705 continue; 706 } 707 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 708 != 0) { 709 /* Abort DMA setup */ 710 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 711 continue; 712 } 713 } 714 } 715 716 int 717 pciide_dma_table_setup(sc, channel, drive) 718 struct pciide_softc *sc; 719 int channel, drive; 720 { 721 bus_dma_segment_t seg; 722 int error, rseg; 723 const bus_size_t dma_table_size = 724 sizeof(struct idedma_table) * NIDEDMA_TABLES; 725 struct pciide_dma_maps *dma_maps = 726 &sc->pciide_channels[channel].dma_maps[drive]; 727 728 /* If table was already allocated, just return */ 729 if (dma_maps->dma_table) 730 return 0; 731 732 /* Allocate memory for the DMA tables and map it */ 733 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 734 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 735 BUS_DMA_NOWAIT)) != 0) { 736 printf("%s:%d: unable to allocate table DMA for " 737 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 738 channel, drive, error); 739 return error; 740 } 741 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 742 dma_table_size, 743 (caddr_t *)&dma_maps->dma_table, 744 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 745 printf("%s:%d: unable to map table DMA for" 746 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 747 channel, drive, error); 748 return error; 749 } 750 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 751 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 752 seg.ds_addr), DEBUG_PROBE); 753 754 /* Create and load table DMA map for this disk */ 755 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 756 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 757 &dma_maps->dmamap_table)) != 0) { 758 printf("%s:%d: unable to create table DMA map for " 759 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 760 channel, drive, error); 761 return error; 762 } 763 if ((error = bus_dmamap_load(sc->sc_dmat, 764 dma_maps->dmamap_table, 765 dma_maps->dma_table, 766 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 767 printf("%s:%d: unable to load table DMA map for " 768 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 769 channel, drive, error); 770 return error; 771 } 772 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 773 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 774 /* Create a xfer DMA map for this drive */ 775 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 776 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 777 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 778 &dma_maps->dmamap_xfer)) != 0) { 779 printf("%s:%d: unable to create xfer DMA map for " 780 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 781 channel, drive, error); 782 return error; 783 } 784 return 0; 785 } 786 787 int 788 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 789 void *v; 790 int channel, drive; 791 void *databuf; 792 size_t datalen; 793 int flags; 794 { 795 struct pciide_softc *sc = v; 796 int error, seg; 797 struct pciide_dma_maps *dma_maps = 798 &sc->pciide_channels[channel].dma_maps[drive]; 799 800 error = bus_dmamap_load(sc->sc_dmat, 801 dma_maps->dmamap_xfer, 802 databuf, datalen, NULL, BUS_DMA_NOWAIT); 803 if (error) { 804 printf("%s:%d: unable to load xfer DMA map for" 805 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 806 channel, drive, error); 807 return error; 808 } 809 810 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 811 dma_maps->dmamap_xfer->dm_mapsize, 812 (flags & WDC_DMA_READ) ? 813 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 814 815 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 816 #ifdef DIAGNOSTIC 817 /* A segment must not cross a 64k boundary */ 818 { 819 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 820 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 821 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 822 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 823 printf("pciide_dma: segment %d physical addr 0x%lx" 824 " len 0x%lx not properly aligned\n", 825 seg, phys, len); 826 panic("pciide_dma: buf align"); 827 } 828 } 829 #endif 830 dma_maps->dma_table[seg].base_addr = 831 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 832 dma_maps->dma_table[seg].byte_count = 833 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 834 IDEDMA_BYTE_COUNT_MASK); 835 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 836 seg, le32toh(dma_maps->dma_table[seg].byte_count), 837 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 838 839 } 840 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 841 htole32(IDEDMA_BYTE_COUNT_EOT); 842 843 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 844 dma_maps->dmamap_table->dm_mapsize, 845 BUS_DMASYNC_PREWRITE); 846 847 /* Maps are ready. Start DMA function */ 848 #ifdef DIAGNOSTIC 849 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 850 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 851 dma_maps->dmamap_table->dm_segs[0].ds_addr); 852 panic("pciide_dma_init: table align"); 853 } 854 #endif 855 856 /* Clear status bits */ 857 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 858 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 859 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 860 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 861 /* Write table addr */ 862 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 863 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 864 dma_maps->dmamap_table->dm_segs[0].ds_addr); 865 /* set read/write */ 866 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 867 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 868 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 869 /* remember flags */ 870 dma_maps->dma_flags = flags; 871 return 0; 872 } 873 874 void 875 pciide_dma_start(v, channel, drive) 876 void *v; 877 int channel, drive; 878 { 879 struct pciide_softc *sc = v; 880 881 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 882 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 883 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 884 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 885 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 886 } 887 888 int 889 pciide_dma_finish(v, channel, drive, force) 890 void *v; 891 int channel, drive; 892 int force; 893 { 894 struct pciide_softc *sc = v; 895 u_int8_t status; 896 int error = 0; 897 struct pciide_dma_maps *dma_maps = 898 &sc->pciide_channels[channel].dma_maps[drive]; 899 900 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 901 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 902 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 903 DEBUG_XFERS); 904 905 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 906 return WDC_DMAST_NOIRQ; 907 908 /* stop DMA channel */ 909 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 910 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 911 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 912 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 913 914 /* Clear status bits */ 915 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 916 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 917 status); 918 919 /* Unload the map of the data buffer */ 920 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 921 dma_maps->dmamap_xfer->dm_mapsize, 922 (dma_maps->dma_flags & WDC_DMA_READ) ? 923 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 924 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 925 926 if ((status & IDEDMA_CTL_ERR) != 0) { 927 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 928 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 929 error |= WDC_DMAST_ERR; 930 } 931 932 if ((status & IDEDMA_CTL_INTR) == 0) { 933 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 934 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 935 drive, status); 936 error |= WDC_DMAST_NOIRQ; 937 } 938 939 if ((status & IDEDMA_CTL_ACT) != 0) { 940 /* data underrun, may be a valid condition for ATAPI */ 941 error |= WDC_DMAST_UNDER; 942 } 943 return error; 944 } 945 946 /* some common code used by several chip_map */ 947 int 948 pciide_chansetup(sc, channel, interface) 949 struct pciide_softc *sc; 950 int channel; 951 pcireg_t interface; 952 { 953 struct pciide_channel *cp = &sc->pciide_channels[channel]; 954 sc->wdc_chanarray[channel] = &cp->wdc_channel; 955 cp->name = PCIIDE_CHANNEL_NAME(channel); 956 cp->wdc_channel.channel = channel; 957 cp->wdc_channel.wdc = &sc->sc_wdcdev; 958 cp->wdc_channel.ch_queue = 959 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 960 if (cp->wdc_channel.ch_queue == NULL) { 961 printf("%s %s channel: " 962 "can't allocate memory for command queue", 963 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 964 return 0; 965 } 966 printf("%s: %s channel %s to %s mode\n", 967 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 968 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 969 "configured" : "wired", 970 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 971 "native-PCI" : "compatibility"); 972 return 1; 973 } 974 975 /* some common code used by several chip channel_map */ 976 void 977 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 978 struct pci_attach_args *pa; 979 struct pciide_channel *cp; 980 pcireg_t interface; 981 bus_size_t *cmdsizep, *ctlsizep; 982 int (*pci_intr) __P((void *)); 983 { 984 struct channel_softc *wdc_cp = &cp->wdc_channel; 985 986 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 987 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 988 pci_intr); 989 else 990 cp->hw_ok = pciide_mapregs_compat(pa, cp, 991 wdc_cp->channel, cmdsizep, ctlsizep); 992 993 if (cp->hw_ok == 0) 994 return; 995 wdc_cp->data32iot = wdc_cp->cmd_iot; 996 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 997 wdcattach(wdc_cp); 998 } 999 1000 /* 1001 * Generic code to call to know if a channel can be disabled. Return 1 1002 * if channel can be disabled, 0 if not 1003 */ 1004 int 1005 pciiide_chan_candisable(cp) 1006 struct pciide_channel *cp; 1007 { 1008 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1009 struct channel_softc *wdc_cp = &cp->wdc_channel; 1010 1011 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1012 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1013 printf("%s: disabling %s channel (no drives)\n", 1014 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1015 cp->hw_ok = 0; 1016 return 1; 1017 } 1018 return 0; 1019 } 1020 1021 /* 1022 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1023 * Set hw_ok=0 on failure 1024 */ 1025 void 1026 pciide_map_compat_intr(pa, cp, compatchan, interface) 1027 struct pci_attach_args *pa; 1028 struct pciide_channel *cp; 1029 int compatchan, interface; 1030 { 1031 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1032 struct channel_softc *wdc_cp = &cp->wdc_channel; 1033 1034 if (cp->hw_ok == 0) 1035 return; 1036 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1037 return; 1038 1039 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1040 pa, compatchan, pciide_compat_intr, cp); 1041 if (cp->ih == NULL) { 1042 printf("%s: no compatibility interrupt for use by %s " 1043 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1044 cp->hw_ok = 0; 1045 } 1046 } 1047 1048 void 1049 pciide_print_modes(cp) 1050 struct pciide_channel *cp; 1051 { 1052 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1053 int drive; 1054 struct channel_softc *chp; 1055 struct ata_drive_datas *drvp; 1056 1057 chp = &cp->wdc_channel; 1058 for (drive = 0; drive < 2; drive++) { 1059 drvp = &chp->ch_drive[drive]; 1060 if ((drvp->drive_flags & DRIVE) == 0) 1061 continue; 1062 printf("%s(%s:%d:%d): using PIO mode %d", 1063 drvp->drv_softc->dv_xname, 1064 sc->sc_wdcdev.sc_dev.dv_xname, 1065 chp->channel, drive, drvp->PIO_mode); 1066 if (drvp->drive_flags & DRIVE_DMA) 1067 printf(", DMA mode %d", drvp->DMA_mode); 1068 if (drvp->drive_flags & DRIVE_UDMA) 1069 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1070 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1071 printf(" (using DMA data transfers)"); 1072 printf("\n"); 1073 } 1074 } 1075 1076 void 1077 default_chip_map(sc, pa) 1078 struct pciide_softc *sc; 1079 struct pci_attach_args *pa; 1080 { 1081 struct pciide_channel *cp; 1082 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1083 sc->sc_tag, PCI_CLASS_REG)); 1084 pcireg_t csr; 1085 int channel, drive; 1086 struct ata_drive_datas *drvp; 1087 u_int8_t idedma_ctl; 1088 bus_size_t cmdsize, ctlsize; 1089 char *failreason; 1090 1091 if (pciide_chipen(sc, pa) == 0) 1092 return; 1093 1094 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1095 printf("%s: bus-master DMA support present", 1096 sc->sc_wdcdev.sc_dev.dv_xname); 1097 if (sc->sc_pp == &default_product_desc && 1098 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1099 PCIIDE_OPTIONS_DMA) == 0) { 1100 printf(", but unused (no driver support)"); 1101 sc->sc_dma_ok = 0; 1102 } else { 1103 pciide_mapreg_dma(sc, pa); 1104 if (sc->sc_dma_ok != 0) 1105 printf(", used without full driver " 1106 "support"); 1107 } 1108 } else { 1109 printf("%s: hardware does not support DMA", 1110 sc->sc_wdcdev.sc_dev.dv_xname); 1111 sc->sc_dma_ok = 0; 1112 } 1113 printf("\n"); 1114 if (sc->sc_dma_ok) 1115 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1116 sc->sc_wdcdev.PIO_cap = 0; 1117 sc->sc_wdcdev.DMA_cap = 0; 1118 1119 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1120 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1121 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1122 1123 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1124 cp = &sc->pciide_channels[channel]; 1125 if (pciide_chansetup(sc, channel, interface) == 0) 1126 continue; 1127 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1128 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1129 &ctlsize, pciide_pci_intr); 1130 } else { 1131 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1132 channel, &cmdsize, &ctlsize); 1133 } 1134 if (cp->hw_ok == 0) 1135 continue; 1136 /* 1137 * Check to see if something appears to be there. 1138 */ 1139 failreason = NULL; 1140 if (!wdcprobe(&cp->wdc_channel)) { 1141 failreason = "not responding; disabled or no drives?"; 1142 goto next; 1143 } 1144 /* 1145 * Now, make sure it's actually attributable to this PCI IDE 1146 * channel by trying to access the channel again while the 1147 * PCI IDE controller's I/O space is disabled. (If the 1148 * channel no longer appears to be there, it belongs to 1149 * this controller.) YUCK! 1150 */ 1151 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1152 PCI_COMMAND_STATUS_REG); 1153 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1154 csr & ~PCI_COMMAND_IO_ENABLE); 1155 if (wdcprobe(&cp->wdc_channel)) 1156 failreason = "other hardware responding at addresses"; 1157 pci_conf_write(sc->sc_pc, sc->sc_tag, 1158 PCI_COMMAND_STATUS_REG, csr); 1159 next: 1160 if (failreason) { 1161 printf("%s: %s channel ignored (%s)\n", 1162 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1163 failreason); 1164 cp->hw_ok = 0; 1165 bus_space_unmap(cp->wdc_channel.cmd_iot, 1166 cp->wdc_channel.cmd_ioh, cmdsize); 1167 bus_space_unmap(cp->wdc_channel.ctl_iot, 1168 cp->wdc_channel.ctl_ioh, ctlsize); 1169 } else { 1170 pciide_map_compat_intr(pa, cp, channel, interface); 1171 } 1172 if (cp->hw_ok) { 1173 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1174 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1175 wdcattach(&cp->wdc_channel); 1176 } 1177 } 1178 1179 if (sc->sc_dma_ok == 0) 1180 return; 1181 1182 /* Allocate DMA maps */ 1183 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1184 idedma_ctl = 0; 1185 cp = &sc->pciide_channels[channel]; 1186 for (drive = 0; drive < 2; drive++) { 1187 drvp = &cp->wdc_channel.ch_drive[drive]; 1188 /* If no drive, skip */ 1189 if ((drvp->drive_flags & DRIVE) == 0) 1190 continue; 1191 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1192 continue; 1193 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1194 /* Abort DMA setup */ 1195 printf("%s:%d:%d: can't allocate DMA maps, " 1196 "using PIO transfers\n", 1197 sc->sc_wdcdev.sc_dev.dv_xname, 1198 channel, drive); 1199 drvp->drive_flags &= ~DRIVE_DMA; 1200 } 1201 printf("%s:%d:%d: using DMA data transfers\n", 1202 sc->sc_wdcdev.sc_dev.dv_xname, 1203 channel, drive); 1204 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1205 } 1206 if (idedma_ctl != 0) { 1207 /* Add software bits in status register */ 1208 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1209 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1210 idedma_ctl); 1211 } 1212 } 1213 } 1214 1215 void 1216 piix_chip_map(sc, pa) 1217 struct pciide_softc *sc; 1218 struct pci_attach_args *pa; 1219 { 1220 struct pciide_channel *cp; 1221 int channel; 1222 u_int32_t idetim; 1223 bus_size_t cmdsize, ctlsize; 1224 1225 if (pciide_chipen(sc, pa) == 0) 1226 return; 1227 1228 printf("%s: bus-master DMA support present", 1229 sc->sc_wdcdev.sc_dev.dv_xname); 1230 pciide_mapreg_dma(sc, pa); 1231 printf("\n"); 1232 if (sc->sc_dma_ok) { 1233 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1234 switch(sc->sc_pp->ide_product) { 1235 case PCI_PRODUCT_INTEL_82371AB_IDE: 1236 case PCI_PRODUCT_INTEL_82801AA_IDE: 1237 case PCI_PRODUCT_INTEL_82801AB_IDE: 1238 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1239 } 1240 } 1241 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1242 WDC_CAPABILITY_MODE; 1243 sc->sc_wdcdev.PIO_cap = 4; 1244 sc->sc_wdcdev.DMA_cap = 2; 1245 sc->sc_wdcdev.UDMA_cap = 1246 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1247 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1248 sc->sc_wdcdev.set_modes = piix_setup_channel; 1249 else 1250 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1251 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1252 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1253 1254 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1255 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1256 DEBUG_PROBE); 1257 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1258 WDCDEBUG_PRINT((", sidetim=0x%x", 1259 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1260 DEBUG_PROBE); 1261 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1262 WDCDEBUG_PRINT((", udamreg 0x%x", 1263 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1264 DEBUG_PROBE); 1265 } 1266 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1267 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1268 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1269 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1270 DEBUG_PROBE); 1271 } 1272 1273 } 1274 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1275 1276 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1277 cp = &sc->pciide_channels[channel]; 1278 /* PIIX is compat-only */ 1279 if (pciide_chansetup(sc, channel, 0) == 0) 1280 continue; 1281 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1282 if ((PIIX_IDETIM_READ(idetim, channel) & 1283 PIIX_IDETIM_IDE) == 0) { 1284 printf("%s: %s channel ignored (disabled)\n", 1285 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1286 continue; 1287 } 1288 /* PIIX are compat-only pciide devices */ 1289 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1290 if (cp->hw_ok == 0) 1291 continue; 1292 if (pciiide_chan_candisable(cp)) { 1293 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1294 channel); 1295 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1296 idetim); 1297 } 1298 pciide_map_compat_intr(pa, cp, channel, 0); 1299 if (cp->hw_ok == 0) 1300 continue; 1301 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1302 } 1303 1304 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1305 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1306 DEBUG_PROBE); 1307 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1308 WDCDEBUG_PRINT((", sidetim=0x%x", 1309 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1310 DEBUG_PROBE); 1311 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1312 WDCDEBUG_PRINT((", udamreg 0x%x", 1313 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1314 DEBUG_PROBE); 1315 } 1316 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1317 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1318 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1319 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1320 DEBUG_PROBE); 1321 } 1322 } 1323 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1324 } 1325 1326 void 1327 piix_setup_channel(chp) 1328 struct channel_softc *chp; 1329 { 1330 u_int8_t mode[2], drive; 1331 u_int32_t oidetim, idetim, idedma_ctl; 1332 struct pciide_channel *cp = (struct pciide_channel*)chp; 1333 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1334 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1335 1336 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1337 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1338 idedma_ctl = 0; 1339 1340 /* set up new idetim: Enable IDE registers decode */ 1341 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1342 chp->channel); 1343 1344 /* setup DMA */ 1345 pciide_channel_dma_setup(cp); 1346 1347 /* 1348 * Here we have to mess up with drives mode: PIIX can't have 1349 * different timings for master and slave drives. 1350 * We need to find the best combination. 1351 */ 1352 1353 /* If both drives supports DMA, take the lower mode */ 1354 if ((drvp[0].drive_flags & DRIVE_DMA) && 1355 (drvp[1].drive_flags & DRIVE_DMA)) { 1356 mode[0] = mode[1] = 1357 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1358 drvp[0].DMA_mode = mode[0]; 1359 drvp[1].DMA_mode = mode[1]; 1360 goto ok; 1361 } 1362 /* 1363 * If only one drive supports DMA, use its mode, and 1364 * put the other one in PIO mode 0 if mode not compatible 1365 */ 1366 if (drvp[0].drive_flags & DRIVE_DMA) { 1367 mode[0] = drvp[0].DMA_mode; 1368 mode[1] = drvp[1].PIO_mode; 1369 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1370 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1371 mode[1] = drvp[1].PIO_mode = 0; 1372 goto ok; 1373 } 1374 if (drvp[1].drive_flags & DRIVE_DMA) { 1375 mode[1] = drvp[1].DMA_mode; 1376 mode[0] = drvp[0].PIO_mode; 1377 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1378 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1379 mode[0] = drvp[0].PIO_mode = 0; 1380 goto ok; 1381 } 1382 /* 1383 * If both drives are not DMA, takes the lower mode, unless 1384 * one of them is PIO mode < 2 1385 */ 1386 if (drvp[0].PIO_mode < 2) { 1387 mode[0] = drvp[0].PIO_mode = 0; 1388 mode[1] = drvp[1].PIO_mode; 1389 } else if (drvp[1].PIO_mode < 2) { 1390 mode[1] = drvp[1].PIO_mode = 0; 1391 mode[0] = drvp[0].PIO_mode; 1392 } else { 1393 mode[0] = mode[1] = 1394 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1395 drvp[0].PIO_mode = mode[0]; 1396 drvp[1].PIO_mode = mode[1]; 1397 } 1398 ok: /* The modes are setup */ 1399 for (drive = 0; drive < 2; drive++) { 1400 if (drvp[drive].drive_flags & DRIVE_DMA) { 1401 idetim |= piix_setup_idetim_timings( 1402 mode[drive], 1, chp->channel); 1403 goto end; 1404 } 1405 } 1406 /* If we are there, none of the drives are DMA */ 1407 if (mode[0] >= 2) 1408 idetim |= piix_setup_idetim_timings( 1409 mode[0], 0, chp->channel); 1410 else 1411 idetim |= piix_setup_idetim_timings( 1412 mode[1], 0, chp->channel); 1413 end: /* 1414 * timing mode is now set up in the controller. Enable 1415 * it per-drive 1416 */ 1417 for (drive = 0; drive < 2; drive++) { 1418 /* If no drive, skip */ 1419 if ((drvp[drive].drive_flags & DRIVE) == 0) 1420 continue; 1421 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1422 if (drvp[drive].drive_flags & DRIVE_DMA) 1423 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1424 } 1425 if (idedma_ctl != 0) { 1426 /* Add software bits in status register */ 1427 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1428 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1429 idedma_ctl); 1430 } 1431 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1432 pciide_print_modes(cp); 1433 } 1434 1435 void 1436 piix3_4_setup_channel(chp) 1437 struct channel_softc *chp; 1438 { 1439 struct ata_drive_datas *drvp; 1440 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1441 struct pciide_channel *cp = (struct pciide_channel*)chp; 1442 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1443 int drive; 1444 int channel = chp->channel; 1445 1446 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1447 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1448 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1449 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1450 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1451 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1452 PIIX_SIDETIM_RTC_MASK(channel)); 1453 1454 idedma_ctl = 0; 1455 /* If channel disabled, no need to go further */ 1456 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1457 return; 1458 /* set up new idetim: Enable IDE registers decode */ 1459 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1460 1461 /* setup DMA if needed */ 1462 pciide_channel_dma_setup(cp); 1463 1464 for (drive = 0; drive < 2; drive++) { 1465 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1466 PIIX_UDMATIM_SET(0x3, channel, drive)); 1467 drvp = &chp->ch_drive[drive]; 1468 /* If no drive, skip */ 1469 if ((drvp->drive_flags & DRIVE) == 0) 1470 continue; 1471 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1472 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1473 goto pio; 1474 1475 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1476 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1477 ideconf |= PIIX_CONFIG_PINGPONG; 1478 } 1479 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1480 /* setup Ultra/66 */ 1481 if (drvp->UDMA_mode > 2 && 1482 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1483 drvp->UDMA_mode = 2; 1484 if (drvp->UDMA_mode > 2) 1485 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1486 else 1487 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1488 } 1489 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1490 (drvp->drive_flags & DRIVE_UDMA)) { 1491 /* use Ultra/DMA */ 1492 drvp->drive_flags &= ~DRIVE_DMA; 1493 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1494 udmareg |= PIIX_UDMATIM_SET( 1495 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1496 } else { 1497 /* use Multiword DMA */ 1498 drvp->drive_flags &= ~DRIVE_UDMA; 1499 if (drive == 0) { 1500 idetim |= piix_setup_idetim_timings( 1501 drvp->DMA_mode, 1, channel); 1502 } else { 1503 sidetim |= piix_setup_sidetim_timings( 1504 drvp->DMA_mode, 1, channel); 1505 idetim =PIIX_IDETIM_SET(idetim, 1506 PIIX_IDETIM_SITRE, channel); 1507 } 1508 } 1509 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1510 1511 pio: /* use PIO mode */ 1512 idetim |= piix_setup_idetim_drvs(drvp); 1513 if (drive == 0) { 1514 idetim |= piix_setup_idetim_timings( 1515 drvp->PIO_mode, 0, channel); 1516 } else { 1517 sidetim |= piix_setup_sidetim_timings( 1518 drvp->PIO_mode, 0, channel); 1519 idetim =PIIX_IDETIM_SET(idetim, 1520 PIIX_IDETIM_SITRE, channel); 1521 } 1522 } 1523 if (idedma_ctl != 0) { 1524 /* Add software bits in status register */ 1525 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1526 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1527 idedma_ctl); 1528 } 1529 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1530 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1531 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1532 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1533 pciide_print_modes(cp); 1534 } 1535 1536 1537 /* setup ISP and RTC fields, based on mode */ 1538 static u_int32_t 1539 piix_setup_idetim_timings(mode, dma, channel) 1540 u_int8_t mode; 1541 u_int8_t dma; 1542 u_int8_t channel; 1543 { 1544 1545 if (dma) 1546 return PIIX_IDETIM_SET(0, 1547 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1548 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1549 channel); 1550 else 1551 return PIIX_IDETIM_SET(0, 1552 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1553 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1554 channel); 1555 } 1556 1557 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1558 static u_int32_t 1559 piix_setup_idetim_drvs(drvp) 1560 struct ata_drive_datas *drvp; 1561 { 1562 u_int32_t ret = 0; 1563 struct channel_softc *chp = drvp->chnl_softc; 1564 u_int8_t channel = chp->channel; 1565 u_int8_t drive = drvp->drive; 1566 1567 /* 1568 * If drive is using UDMA, timings setups are independant 1569 * So just check DMA and PIO here. 1570 */ 1571 if (drvp->drive_flags & DRIVE_DMA) { 1572 /* if mode = DMA mode 0, use compatible timings */ 1573 if ((drvp->drive_flags & DRIVE_DMA) && 1574 drvp->DMA_mode == 0) { 1575 drvp->PIO_mode = 0; 1576 return ret; 1577 } 1578 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1579 /* 1580 * PIO and DMA timings are the same, use fast timings for PIO 1581 * too, else use compat timings. 1582 */ 1583 if ((piix_isp_pio[drvp->PIO_mode] != 1584 piix_isp_dma[drvp->DMA_mode]) || 1585 (piix_rtc_pio[drvp->PIO_mode] != 1586 piix_rtc_dma[drvp->DMA_mode])) 1587 drvp->PIO_mode = 0; 1588 /* if PIO mode <= 2, use compat timings for PIO */ 1589 if (drvp->PIO_mode <= 2) { 1590 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1591 channel); 1592 return ret; 1593 } 1594 } 1595 1596 /* 1597 * Now setup PIO modes. If mode < 2, use compat timings. 1598 * Else enable fast timings. Enable IORDY and prefetch/post 1599 * if PIO mode >= 3. 1600 */ 1601 1602 if (drvp->PIO_mode < 2) 1603 return ret; 1604 1605 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1606 if (drvp->PIO_mode >= 3) { 1607 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1608 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1609 } 1610 return ret; 1611 } 1612 1613 /* setup values in SIDETIM registers, based on mode */ 1614 static u_int32_t 1615 piix_setup_sidetim_timings(mode, dma, channel) 1616 u_int8_t mode; 1617 u_int8_t dma; 1618 u_int8_t channel; 1619 { 1620 if (dma) 1621 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1622 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1623 else 1624 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1625 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1626 } 1627 1628 void 1629 amd756_chip_map(sc, pa) 1630 struct pciide_softc *sc; 1631 struct pci_attach_args *pa; 1632 { 1633 struct pciide_channel *cp; 1634 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1635 sc->sc_tag, PCI_CLASS_REG)); 1636 int channel; 1637 pcireg_t chanenable; 1638 bus_size_t cmdsize, ctlsize; 1639 1640 if (pciide_chipen(sc, pa) == 0) 1641 return; 1642 printf("%s: bus-master DMA support present", 1643 sc->sc_wdcdev.sc_dev.dv_xname); 1644 pciide_mapreg_dma(sc, pa); 1645 printf("\n"); 1646 if (sc->sc_dma_ok) 1647 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1648 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1649 WDC_CAPABILITY_MODE; 1650 sc->sc_wdcdev.PIO_cap = 4; 1651 sc->sc_wdcdev.DMA_cap = 2; 1652 sc->sc_wdcdev.UDMA_cap = 4; 1653 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1654 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1655 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1656 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1657 1658 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1659 DEBUG_PROBE); 1660 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1661 cp = &sc->pciide_channels[channel]; 1662 if (pciide_chansetup(sc, channel, interface) == 0) 1663 continue; 1664 1665 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1666 printf("%s: %s channel ignored (disabled)\n", 1667 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1668 continue; 1669 } 1670 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1671 pciide_pci_intr); 1672 1673 if (pciiide_chan_candisable(cp)) 1674 chanenable &= ~AMD756_CHAN_EN(channel); 1675 pciide_map_compat_intr(pa, cp, channel, interface); 1676 if (cp->hw_ok == 0) 1677 continue; 1678 1679 amd756_setup_channel(&cp->wdc_channel); 1680 } 1681 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1682 chanenable); 1683 return; 1684 } 1685 1686 void 1687 amd756_setup_channel(chp) 1688 struct channel_softc *chp; 1689 { 1690 u_int32_t udmatim_reg, datatim_reg; 1691 u_int8_t idedma_ctl; 1692 int mode, drive; 1693 struct ata_drive_datas *drvp; 1694 struct pciide_channel *cp = (struct pciide_channel*)chp; 1695 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1696 1697 idedma_ctl = 0; 1698 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1699 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1700 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1701 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1702 1703 /* setup DMA if needed */ 1704 pciide_channel_dma_setup(cp); 1705 1706 for (drive = 0; drive < 2; drive++) { 1707 drvp = &chp->ch_drive[drive]; 1708 /* If no drive, skip */ 1709 if ((drvp->drive_flags & DRIVE) == 0) 1710 continue; 1711 /* add timing values, setup DMA if needed */ 1712 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1713 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1714 mode = drvp->PIO_mode; 1715 goto pio; 1716 } 1717 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1718 (drvp->drive_flags & DRIVE_UDMA)) { 1719 /* use Ultra/DMA */ 1720 drvp->drive_flags &= ~DRIVE_DMA; 1721 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1722 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1723 AMD756_UDMA_TIME(chp->channel, drive, 1724 amd756_udma_tim[drvp->UDMA_mode]); 1725 /* can use PIO timings, MW DMA unused */ 1726 mode = drvp->PIO_mode; 1727 } else { 1728 /* use Multiword DMA */ 1729 drvp->drive_flags &= ~DRIVE_UDMA; 1730 /* mode = min(pio, dma+2) */ 1731 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1732 mode = drvp->PIO_mode; 1733 else 1734 mode = drvp->DMA_mode + 2; 1735 } 1736 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1737 1738 pio: /* setup PIO mode */ 1739 if (mode <= 2) { 1740 drvp->DMA_mode = 0; 1741 drvp->PIO_mode = 0; 1742 mode = 0; 1743 } else { 1744 drvp->PIO_mode = mode; 1745 drvp->DMA_mode = mode - 2; 1746 } 1747 datatim_reg |= 1748 AMD756_DATATIM_PULSE(chp->channel, drive, 1749 amd756_pio_set[mode]) | 1750 AMD756_DATATIM_RECOV(chp->channel, drive, 1751 amd756_pio_rec[mode]); 1752 } 1753 if (idedma_ctl != 0) { 1754 /* Add software bits in status register */ 1755 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1756 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1757 idedma_ctl); 1758 } 1759 pciide_print_modes(cp); 1760 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1761 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1762 } 1763 1764 void 1765 apollo_chip_map(sc, pa) 1766 struct pciide_softc *sc; 1767 struct pci_attach_args *pa; 1768 { 1769 struct pciide_channel *cp; 1770 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1771 sc->sc_tag, PCI_CLASS_REG)); 1772 int channel; 1773 u_int32_t ideconf; 1774 bus_size_t cmdsize, ctlsize; 1775 1776 if (pciide_chipen(sc, pa) == 0) 1777 return; 1778 printf("%s: bus-master DMA support present", 1779 sc->sc_wdcdev.sc_dev.dv_xname); 1780 pciide_mapreg_dma(sc, pa); 1781 printf("\n"); 1782 if (sc->sc_dma_ok) { 1783 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1784 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1785 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1786 } 1787 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE; 1788 sc->sc_wdcdev.PIO_cap = 4; 1789 sc->sc_wdcdev.DMA_cap = 2; 1790 sc->sc_wdcdev.UDMA_cap = 2; 1791 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1792 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1793 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1794 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1795 1796 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1797 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1798 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1799 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1800 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1801 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1802 DEBUG_PROBE); 1803 1804 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1805 cp = &sc->pciide_channels[channel]; 1806 if (pciide_chansetup(sc, channel, interface) == 0) 1807 continue; 1808 1809 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1810 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1811 printf("%s: %s channel ignored (disabled)\n", 1812 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1813 continue; 1814 } 1815 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1816 pciide_pci_intr); 1817 if (cp->hw_ok == 0) 1818 continue; 1819 if (pciiide_chan_candisable(cp)) { 1820 ideconf &= ~APO_IDECONF_EN(channel); 1821 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1822 ideconf); 1823 } 1824 pciide_map_compat_intr(pa, cp, channel, interface); 1825 1826 if (cp->hw_ok == 0) 1827 continue; 1828 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1829 } 1830 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1831 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1832 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1833 } 1834 1835 void 1836 apollo_setup_channel(chp) 1837 struct channel_softc *chp; 1838 { 1839 u_int32_t udmatim_reg, datatim_reg; 1840 u_int8_t idedma_ctl; 1841 int mode, drive; 1842 struct ata_drive_datas *drvp; 1843 struct pciide_channel *cp = (struct pciide_channel*)chp; 1844 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1845 1846 idedma_ctl = 0; 1847 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1848 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1849 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1850 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1851 1852 /* setup DMA if needed */ 1853 pciide_channel_dma_setup(cp); 1854 1855 for (drive = 0; drive < 2; drive++) { 1856 drvp = &chp->ch_drive[drive]; 1857 /* If no drive, skip */ 1858 if ((drvp->drive_flags & DRIVE) == 0) 1859 continue; 1860 /* add timing values, setup DMA if needed */ 1861 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1862 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1863 mode = drvp->PIO_mode; 1864 goto pio; 1865 } 1866 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1867 (drvp->drive_flags & DRIVE_UDMA)) { 1868 /* use Ultra/DMA */ 1869 drvp->drive_flags &= ~DRIVE_DMA; 1870 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1871 APO_UDMA_EN_MTH(chp->channel, drive) | 1872 APO_UDMA_TIME(chp->channel, drive, 1873 apollo_udma_tim[drvp->UDMA_mode]); 1874 /* can use PIO timings, MW DMA unused */ 1875 mode = drvp->PIO_mode; 1876 } else { 1877 /* use Multiword DMA */ 1878 drvp->drive_flags &= ~DRIVE_UDMA; 1879 /* mode = min(pio, dma+2) */ 1880 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1881 mode = drvp->PIO_mode; 1882 else 1883 mode = drvp->DMA_mode + 2; 1884 } 1885 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1886 1887 pio: /* setup PIO mode */ 1888 if (mode <= 2) { 1889 drvp->DMA_mode = 0; 1890 drvp->PIO_mode = 0; 1891 mode = 0; 1892 } else { 1893 drvp->PIO_mode = mode; 1894 drvp->DMA_mode = mode - 2; 1895 } 1896 datatim_reg |= 1897 APO_DATATIM_PULSE(chp->channel, drive, 1898 apollo_pio_set[mode]) | 1899 APO_DATATIM_RECOV(chp->channel, drive, 1900 apollo_pio_rec[mode]); 1901 } 1902 if (idedma_ctl != 0) { 1903 /* Add software bits in status register */ 1904 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1905 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1906 idedma_ctl); 1907 } 1908 pciide_print_modes(cp); 1909 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 1910 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 1911 } 1912 1913 void 1914 cmd_channel_map(pa, sc, channel) 1915 struct pci_attach_args *pa; 1916 struct pciide_softc *sc; 1917 int channel; 1918 { 1919 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1920 bus_size_t cmdsize, ctlsize; 1921 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 1922 int interface = 1923 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1924 1925 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1926 cp->name = PCIIDE_CHANNEL_NAME(channel); 1927 cp->wdc_channel.channel = channel; 1928 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1929 1930 if (channel > 0) { 1931 cp->wdc_channel.ch_queue = 1932 sc->pciide_channels[0].wdc_channel.ch_queue; 1933 } else { 1934 cp->wdc_channel.ch_queue = 1935 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1936 } 1937 if (cp->wdc_channel.ch_queue == NULL) { 1938 printf("%s %s channel: " 1939 "can't allocate memory for command queue", 1940 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1941 return; 1942 } 1943 1944 printf("%s: %s channel %s to %s mode\n", 1945 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1946 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1947 "configured" : "wired", 1948 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1949 "native-PCI" : "compatibility"); 1950 1951 /* 1952 * with a CMD PCI64x, if we get here, the first channel is enabled: 1953 * there's no way to disable the first channel without disabling 1954 * the whole device 1955 */ 1956 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 1957 printf("%s: %s channel ignored (disabled)\n", 1958 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1959 return; 1960 } 1961 1962 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 1963 if (cp->hw_ok == 0) 1964 return; 1965 if (channel == 1) { 1966 if (pciiide_chan_candisable(cp)) { 1967 ctrl &= ~CMD_CTRL_2PORT; 1968 pciide_pci_write(pa->pa_pc, pa->pa_tag, 1969 CMD_CTRL, ctrl); 1970 } 1971 } 1972 pciide_map_compat_intr(pa, cp, channel, interface); 1973 } 1974 1975 int 1976 cmd_pci_intr(arg) 1977 void *arg; 1978 { 1979 struct pciide_softc *sc = arg; 1980 struct pciide_channel *cp; 1981 struct channel_softc *wdc_cp; 1982 int i, rv, crv; 1983 u_int32_t priirq, secirq; 1984 1985 rv = 0; 1986 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 1987 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 1988 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 1989 cp = &sc->pciide_channels[i]; 1990 wdc_cp = &cp->wdc_channel; 1991 /* If a compat channel skip. */ 1992 if (cp->compat) 1993 continue; 1994 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 1995 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 1996 crv = wdcintr(wdc_cp); 1997 if (crv == 0) 1998 printf("%s:%d: bogus intr\n", 1999 sc->sc_wdcdev.sc_dev.dv_xname, i); 2000 else 2001 rv = 1; 2002 } 2003 } 2004 return rv; 2005 } 2006 2007 void 2008 cmd_chip_map(sc, pa) 2009 struct pciide_softc *sc; 2010 struct pci_attach_args *pa; 2011 { 2012 int channel; 2013 2014 /* 2015 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2016 * and base adresses registers can be disabled at 2017 * hardware level. In this case, the device is wired 2018 * in compat mode and its first channel is always enabled, 2019 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2020 * In fact, it seems that the first channel of the CMD PCI0640 2021 * can't be disabled. 2022 */ 2023 2024 #ifdef PCIIDE_CMD064x_DISABLE 2025 if (pciide_chipen(sc, pa) == 0) 2026 return; 2027 #endif 2028 2029 printf("%s: hardware does not support DMA\n", 2030 sc->sc_wdcdev.sc_dev.dv_xname); 2031 sc->sc_dma_ok = 0; 2032 2033 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2034 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2035 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 2036 2037 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2038 cmd_channel_map(pa, sc, channel); 2039 } 2040 } 2041 2042 void 2043 cmd0643_6_chip_map(sc, pa) 2044 struct pciide_softc *sc; 2045 struct pci_attach_args *pa; 2046 { 2047 struct pciide_channel *cp; 2048 int channel; 2049 2050 /* 2051 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2052 * and base adresses registers can be disabled at 2053 * hardware level. In this case, the device is wired 2054 * in compat mode and its first channel is always enabled, 2055 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2056 * In fact, it seems that the first channel of the CMD PCI0640 2057 * can't be disabled. 2058 */ 2059 2060 #ifdef PCIIDE_CMD064x_DISABLE 2061 if (pciide_chipen(sc, pa) == 0) 2062 return; 2063 #endif 2064 printf("%s: bus-master DMA support present", 2065 sc->sc_wdcdev.sc_dev.dv_xname); 2066 pciide_mapreg_dma(sc, pa); 2067 printf("\n"); 2068 if (sc->sc_dma_ok) 2069 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2070 2071 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2072 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2073 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2074 WDC_CAPABILITY_MODE; 2075 sc->sc_wdcdev.PIO_cap = 4; 2076 sc->sc_wdcdev.DMA_cap = 2; 2077 sc->sc_wdcdev.set_modes = cmd0643_6_setup_channel; 2078 2079 WDCDEBUG_PRINT(("cmd0643_6_chip_map: old timings reg 0x%x 0x%x\n", 2080 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2081 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2082 DEBUG_PROBE); 2083 2084 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2085 cp = &sc->pciide_channels[channel]; 2086 cmd_channel_map(pa, sc, channel); 2087 if (cp->hw_ok == 0) 2088 continue; 2089 cmd0643_6_setup_channel(&cp->wdc_channel); 2090 } 2091 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2092 WDCDEBUG_PRINT(("cmd0643_6_chip_map: timings reg now 0x%x 0x%x\n", 2093 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2094 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2095 DEBUG_PROBE); 2096 } 2097 2098 void 2099 cmd0643_6_setup_channel(chp) 2100 struct channel_softc *chp; 2101 { 2102 struct ata_drive_datas *drvp; 2103 u_int8_t tim; 2104 u_int32_t idedma_ctl; 2105 int drive; 2106 struct pciide_channel *cp = (struct pciide_channel*)chp; 2107 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2108 2109 idedma_ctl = 0; 2110 /* setup DMA if needed */ 2111 pciide_channel_dma_setup(cp); 2112 2113 for (drive = 0; drive < 2; drive++) { 2114 drvp = &chp->ch_drive[drive]; 2115 /* If no drive, skip */ 2116 if ((drvp->drive_flags & DRIVE) == 0) 2117 continue; 2118 /* add timing values, setup DMA if needed */ 2119 tim = cmd0643_6_data_tim_pio[drvp->PIO_mode]; 2120 if (drvp->drive_flags & DRIVE_DMA) { 2121 /* 2122 * use Multiword DMA. 2123 * Timings will be used for both PIO and DMA, so adjust 2124 * DMA mode if needed 2125 */ 2126 if (drvp->PIO_mode >= 3 && 2127 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2128 drvp->DMA_mode = drvp->PIO_mode - 2; 2129 } 2130 tim = cmd0643_6_data_tim_dma[drvp->DMA_mode]; 2131 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2132 } 2133 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2134 CMD_DATA_TIM(chp->channel, drive), tim); 2135 } 2136 if (idedma_ctl != 0) { 2137 /* Add software bits in status register */ 2138 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2139 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2140 idedma_ctl); 2141 } 2142 pciide_print_modes(cp); 2143 } 2144 2145 void 2146 cy693_chip_map(sc, pa) 2147 struct pciide_softc *sc; 2148 struct pci_attach_args *pa; 2149 { 2150 struct pciide_channel *cp; 2151 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2152 sc->sc_tag, PCI_CLASS_REG)); 2153 int compatchan; 2154 bus_size_t cmdsize, ctlsize; 2155 2156 if (pciide_chipen(sc, pa) == 0) 2157 return; 2158 /* 2159 * this chip has 2 PCI IDE functions, one for primary and one for 2160 * secondary. So we need to call pciide_mapregs_compat() with 2161 * the real channel 2162 */ 2163 if (pa->pa_function == 1) { 2164 compatchan = 0; 2165 } else if (pa->pa_function == 2) { 2166 compatchan = 1; 2167 } else { 2168 printf("%s: unexpected PCI function %d\n", 2169 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2170 return; 2171 } 2172 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2173 printf("%s: bus-master DMA support present", 2174 sc->sc_wdcdev.sc_dev.dv_xname); 2175 pciide_mapreg_dma(sc, pa); 2176 } else { 2177 printf("%s: hardware does not support DMA", 2178 sc->sc_wdcdev.sc_dev.dv_xname); 2179 sc->sc_dma_ok = 0; 2180 } 2181 printf("\n"); 2182 2183 if (sc->sc_dma_ok) 2184 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2185 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2186 WDC_CAPABILITY_MODE; 2187 sc->sc_wdcdev.PIO_cap = 4; 2188 sc->sc_wdcdev.DMA_cap = 2; 2189 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2190 2191 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2192 sc->sc_wdcdev.nchannels = 1; 2193 2194 /* Only one channel for this chip; if we are here it's enabled */ 2195 cp = &sc->pciide_channels[0]; 2196 sc->wdc_chanarray[0] = &cp->wdc_channel; 2197 cp->name = PCIIDE_CHANNEL_NAME(0); 2198 cp->wdc_channel.channel = 0; 2199 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2200 cp->wdc_channel.ch_queue = 2201 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2202 if (cp->wdc_channel.ch_queue == NULL) { 2203 printf("%s primary channel: " 2204 "can't allocate memory for command queue", 2205 sc->sc_wdcdev.sc_dev.dv_xname); 2206 return; 2207 } 2208 printf("%s: primary channel %s to ", 2209 sc->sc_wdcdev.sc_dev.dv_xname, 2210 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2211 "configured" : "wired"); 2212 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2213 printf("native-PCI"); 2214 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2215 pciide_pci_intr); 2216 } else { 2217 printf("compatibility"); 2218 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2219 &cmdsize, &ctlsize); 2220 } 2221 printf(" mode\n"); 2222 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2223 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2224 wdcattach(&cp->wdc_channel); 2225 if (pciiide_chan_candisable(cp)) { 2226 pci_conf_write(sc->sc_pc, sc->sc_tag, 2227 PCI_COMMAND_STATUS_REG, 0); 2228 } 2229 pciide_map_compat_intr(pa, cp, compatchan, interface); 2230 if (cp->hw_ok == 0) 2231 return; 2232 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2233 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2234 cy693_setup_channel(&cp->wdc_channel); 2235 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2236 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2237 } 2238 2239 void 2240 cy693_setup_channel(chp) 2241 struct channel_softc *chp; 2242 { 2243 struct ata_drive_datas *drvp; 2244 int drive; 2245 u_int32_t cy_cmd_ctrl; 2246 u_int32_t idedma_ctl; 2247 struct pciide_channel *cp = (struct pciide_channel*)chp; 2248 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2249 int dma_mode = -1; 2250 2251 cy_cmd_ctrl = idedma_ctl = 0; 2252 2253 /* setup DMA if needed */ 2254 pciide_channel_dma_setup(cp); 2255 2256 for (drive = 0; drive < 2; drive++) { 2257 drvp = &chp->ch_drive[drive]; 2258 /* If no drive, skip */ 2259 if ((drvp->drive_flags & DRIVE) == 0) 2260 continue; 2261 /* add timing values, setup DMA if needed */ 2262 if (drvp->drive_flags & DRIVE_DMA) { 2263 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2264 /* use Multiword DMA */ 2265 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2266 dma_mode = drvp->DMA_mode; 2267 } 2268 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2269 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2270 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2271 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2272 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2273 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2274 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2275 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2276 } 2277 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2278 chp->ch_drive[0].DMA_mode = dma_mode; 2279 chp->ch_drive[1].DMA_mode = dma_mode; 2280 pciide_print_modes(cp); 2281 if (idedma_ctl != 0) { 2282 /* Add software bits in status register */ 2283 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2284 IDEDMA_CTL, idedma_ctl); 2285 } 2286 } 2287 2288 void 2289 sis_chip_map(sc, pa) 2290 struct pciide_softc *sc; 2291 struct pci_attach_args *pa; 2292 { 2293 struct pciide_channel *cp; 2294 int channel; 2295 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2296 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2297 sc->sc_tag, PCI_CLASS_REG)); 2298 pcireg_t rev = PCI_REVISION(pci_conf_read(sc->sc_pc, 2299 sc->sc_tag, PCI_CLASS_REG)); 2300 bus_size_t cmdsize, ctlsize; 2301 2302 if (pciide_chipen(sc, pa) == 0) 2303 return; 2304 printf("%s: bus-master DMA support present", 2305 sc->sc_wdcdev.sc_dev.dv_xname); 2306 pciide_mapreg_dma(sc, pa); 2307 printf("\n"); 2308 if (sc->sc_dma_ok) { 2309 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2310 if (rev >= 0xd0) 2311 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2312 } 2313 2314 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2315 WDC_CAPABILITY_MODE; 2316 sc->sc_wdcdev.PIO_cap = 4; 2317 sc->sc_wdcdev.DMA_cap = 2; 2318 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2319 sc->sc_wdcdev.UDMA_cap = 2; 2320 sc->sc_wdcdev.set_modes = sis_setup_channel; 2321 2322 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2323 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2324 2325 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2326 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2327 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2328 2329 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2330 cp = &sc->pciide_channels[channel]; 2331 if (pciide_chansetup(sc, channel, interface) == 0) 2332 continue; 2333 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2334 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2335 printf("%s: %s channel ignored (disabled)\n", 2336 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2337 continue; 2338 } 2339 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2340 pciide_pci_intr); 2341 if (cp->hw_ok == 0) 2342 continue; 2343 if (pciiide_chan_candisable(cp)) { 2344 if (channel == 0) 2345 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2346 else 2347 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2348 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2349 sis_ctr0); 2350 } 2351 pciide_map_compat_intr(pa, cp, channel, interface); 2352 if (cp->hw_ok == 0) 2353 continue; 2354 sis_setup_channel(&cp->wdc_channel); 2355 } 2356 } 2357 2358 void 2359 sis_setup_channel(chp) 2360 struct channel_softc *chp; 2361 { 2362 struct ata_drive_datas *drvp; 2363 int drive; 2364 u_int32_t sis_tim; 2365 u_int32_t idedma_ctl; 2366 struct pciide_channel *cp = (struct pciide_channel*)chp; 2367 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2368 2369 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2370 "channel %d 0x%x\n", chp->channel, 2371 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2372 DEBUG_PROBE); 2373 sis_tim = 0; 2374 idedma_ctl = 0; 2375 /* setup DMA if needed */ 2376 pciide_channel_dma_setup(cp); 2377 2378 for (drive = 0; drive < 2; drive++) { 2379 drvp = &chp->ch_drive[drive]; 2380 /* If no drive, skip */ 2381 if ((drvp->drive_flags & DRIVE) == 0) 2382 continue; 2383 /* add timing values, setup DMA if needed */ 2384 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2385 (drvp->drive_flags & DRIVE_UDMA) == 0) 2386 goto pio; 2387 2388 if (drvp->drive_flags & DRIVE_UDMA) { 2389 /* use Ultra/DMA */ 2390 drvp->drive_flags &= ~DRIVE_DMA; 2391 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2392 SIS_TIM_UDMA_TIME_OFF(drive); 2393 sis_tim |= SIS_TIM_UDMA_EN(drive); 2394 } else { 2395 /* 2396 * use Multiword DMA 2397 * Timings will be used for both PIO and DMA, 2398 * so adjust DMA mode if needed 2399 */ 2400 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2401 drvp->PIO_mode = drvp->DMA_mode + 2; 2402 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2403 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2404 drvp->PIO_mode - 2 : 0; 2405 if (drvp->DMA_mode == 0) 2406 drvp->PIO_mode = 0; 2407 } 2408 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2409 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2410 SIS_TIM_ACT_OFF(drive); 2411 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2412 SIS_TIM_REC_OFF(drive); 2413 } 2414 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2415 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2416 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2417 if (idedma_ctl != 0) { 2418 /* Add software bits in status register */ 2419 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2420 IDEDMA_CTL, idedma_ctl); 2421 } 2422 pciide_print_modes(cp); 2423 } 2424 2425 void 2426 acer_chip_map(sc, pa) 2427 struct pciide_softc *sc; 2428 struct pci_attach_args *pa; 2429 { 2430 struct pciide_channel *cp; 2431 int channel; 2432 pcireg_t cr, interface; 2433 bus_size_t cmdsize, ctlsize; 2434 2435 if (pciide_chipen(sc, pa) == 0) 2436 return; 2437 printf("%s: bus-master DMA support present", 2438 sc->sc_wdcdev.sc_dev.dv_xname); 2439 pciide_mapreg_dma(sc, pa); 2440 printf("\n"); 2441 if (sc->sc_dma_ok) 2442 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2443 2444 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2445 WDC_CAPABILITY_MODE; 2446 2447 sc->sc_wdcdev.PIO_cap = 4; 2448 sc->sc_wdcdev.DMA_cap = 2; 2449 sc->sc_wdcdev.UDMA_cap = 2; 2450 sc->sc_wdcdev.set_modes = acer_setup_channel; 2451 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2452 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2453 2454 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2455 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2456 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2457 2458 /* Enable "microsoft register bits" R/W. */ 2459 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2460 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2461 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2462 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2463 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2464 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2465 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2466 ~ACER_CHANSTATUSREGS_RO); 2467 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2468 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2469 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2470 /* Don't use cr, re-read the real register content instead */ 2471 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2472 PCI_CLASS_REG)); 2473 2474 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2475 cp = &sc->pciide_channels[channel]; 2476 if (pciide_chansetup(sc, channel, interface) == 0) 2477 continue; 2478 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2479 printf("%s: %s channel ignored (disabled)\n", 2480 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2481 continue; 2482 } 2483 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2484 acer_pci_intr); 2485 if (cp->hw_ok == 0) 2486 continue; 2487 if (pciiide_chan_candisable(cp)) { 2488 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2489 pci_conf_write(sc->sc_pc, sc->sc_tag, 2490 PCI_CLASS_REG, cr); 2491 } 2492 pciide_map_compat_intr(pa, cp, channel, interface); 2493 acer_setup_channel(&cp->wdc_channel); 2494 } 2495 } 2496 2497 void 2498 acer_setup_channel(chp) 2499 struct channel_softc *chp; 2500 { 2501 struct ata_drive_datas *drvp; 2502 int drive; 2503 u_int32_t acer_fifo_udma; 2504 u_int32_t idedma_ctl; 2505 struct pciide_channel *cp = (struct pciide_channel*)chp; 2506 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2507 2508 idedma_ctl = 0; 2509 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2510 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2511 acer_fifo_udma), DEBUG_PROBE); 2512 /* setup DMA if needed */ 2513 pciide_channel_dma_setup(cp); 2514 2515 for (drive = 0; drive < 2; drive++) { 2516 drvp = &chp->ch_drive[drive]; 2517 /* If no drive, skip */ 2518 if ((drvp->drive_flags & DRIVE) == 0) 2519 continue; 2520 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2521 "channel %d drive %d 0x%x\n", chp->channel, drive, 2522 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2523 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2524 /* clear FIFO/DMA mode */ 2525 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2526 ACER_UDMA_EN(chp->channel, drive) | 2527 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2528 2529 /* add timing values, setup DMA if needed */ 2530 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2531 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2532 acer_fifo_udma |= 2533 ACER_FTH_OPL(chp->channel, drive, 0x1); 2534 goto pio; 2535 } 2536 2537 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2538 if (drvp->drive_flags & DRIVE_UDMA) { 2539 /* use Ultra/DMA */ 2540 drvp->drive_flags &= ~DRIVE_DMA; 2541 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2542 acer_fifo_udma |= 2543 ACER_UDMA_TIM(chp->channel, drive, 2544 acer_udma[drvp->UDMA_mode]); 2545 } else { 2546 /* 2547 * use Multiword DMA 2548 * Timings will be used for both PIO and DMA, 2549 * so adjust DMA mode if needed 2550 */ 2551 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2552 drvp->PIO_mode = drvp->DMA_mode + 2; 2553 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2554 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2555 drvp->PIO_mode - 2 : 0; 2556 if (drvp->DMA_mode == 0) 2557 drvp->PIO_mode = 0; 2558 } 2559 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2560 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2561 ACER_IDETIM(chp->channel, drive), 2562 acer_pio[drvp->PIO_mode]); 2563 } 2564 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2565 acer_fifo_udma), DEBUG_PROBE); 2566 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2567 if (idedma_ctl != 0) { 2568 /* Add software bits in status register */ 2569 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2570 IDEDMA_CTL, idedma_ctl); 2571 } 2572 pciide_print_modes(cp); 2573 } 2574 2575 int 2576 acer_pci_intr(arg) 2577 void *arg; 2578 { 2579 struct pciide_softc *sc = arg; 2580 struct pciide_channel *cp; 2581 struct channel_softc *wdc_cp; 2582 int i, rv, crv; 2583 u_int32_t chids; 2584 2585 rv = 0; 2586 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2587 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2588 cp = &sc->pciide_channels[i]; 2589 wdc_cp = &cp->wdc_channel; 2590 /* If a compat channel skip. */ 2591 if (cp->compat) 2592 continue; 2593 if (chids & ACER_CHIDS_INT(i)) { 2594 crv = wdcintr(wdc_cp); 2595 if (crv == 0) 2596 printf("%s:%d: bogus intr\n", 2597 sc->sc_wdcdev.sc_dev.dv_xname, i); 2598 else 2599 rv = 1; 2600 } 2601 } 2602 return rv; 2603 } 2604 2605 /* A macro to test product */ 2606 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 2607 2608 void 2609 pdc202xx_chip_map(sc, pa) 2610 struct pciide_softc *sc; 2611 struct pci_attach_args *pa; 2612 { 2613 struct pciide_channel *cp; 2614 int channel; 2615 pcireg_t interface, st, mode; 2616 bus_size_t cmdsize, ctlsize; 2617 2618 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2619 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 2620 DEBUG_PROBE); 2621 if (pciide_chipen(sc, pa) == 0) 2622 return; 2623 2624 /* turn off RAID mode */ 2625 st &= ~PDC2xx_STATE_IDERAID; 2626 2627 /* 2628 * can't rely on the PCI_CLASS_REG content if the chip was in raid 2629 * mode. We have to fake interface 2630 */ 2631 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 2632 if (st & PDC2xx_STATE_NATIVE) 2633 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2634 2635 printf("%s: bus-master DMA support present", 2636 sc->sc_wdcdev.sc_dev.dv_xname); 2637 pciide_mapreg_dma(sc, pa); 2638 printf("\n"); 2639 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2640 WDC_CAPABILITY_MODE; 2641 if (sc->sc_dma_ok) 2642 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2643 sc->sc_wdcdev.PIO_cap = 4; 2644 sc->sc_wdcdev.DMA_cap = 2; 2645 if (PDC_IS_262(sc)) 2646 sc->sc_wdcdev.UDMA_cap = 4; 2647 else 2648 sc->sc_wdcdev.UDMA_cap = 2; 2649 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 2650 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2651 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2652 2653 /* setup failsafe defaults */ 2654 mode = 0; 2655 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 2656 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 2657 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 2658 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 2659 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2660 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 2661 "initial timings 0x%x, now 0x%x\n", channel, 2662 pci_conf_read(sc->sc_pc, sc->sc_tag, 2663 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 2664 DEBUG_PROBE); 2665 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 2666 mode | PDC2xx_TIM_IORDYp); 2667 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 2668 "initial timings 0x%x, now 0x%x\n", channel, 2669 pci_conf_read(sc->sc_pc, sc->sc_tag, 2670 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 2671 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 2672 mode); 2673 } 2674 2675 mode = PDC2xx_SCR_DMA; 2676 if (PDC_IS_262(sc)) { 2677 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 2678 } else { 2679 /* the BIOS set it up this way */ 2680 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 2681 } 2682 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 2683 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 2684 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 2685 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 2686 DEBUG_PROBE); 2687 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 2688 2689 /* controller initial state register is OK even without BIOS */ 2690 /* Set DMA mode to IDE DMA compatibility */ 2691 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 2692 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 2693 DEBUG_PROBE); 2694 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 2695 mode | 0x1); 2696 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 2697 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 2698 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 2699 mode | 0x1); 2700 2701 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2702 cp = &sc->pciide_channels[channel]; 2703 if (pciide_chansetup(sc, channel, interface) == 0) 2704 continue; 2705 if ((st & (PDC_IS_262(sc) ? 2706 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 2707 printf("%s: %s channel ignored (disabled)\n", 2708 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2709 continue; 2710 } 2711 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2712 pdc202xx_pci_intr); 2713 if (cp->hw_ok == 0) 2714 continue; 2715 if (pciiide_chan_candisable(cp)) 2716 st &= ~(PDC_IS_262(sc) ? 2717 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 2718 pciide_map_compat_intr(pa, cp, channel, interface); 2719 pdc202xx_setup_channel(&cp->wdc_channel); 2720 } 2721 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 2722 DEBUG_PROBE); 2723 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 2724 return; 2725 } 2726 2727 void 2728 pdc202xx_setup_channel(chp) 2729 struct channel_softc *chp; 2730 { 2731 struct ata_drive_datas *drvp; 2732 int drive; 2733 pcireg_t mode, st; 2734 u_int32_t idedma_ctl, scr, atapi; 2735 struct pciide_channel *cp = (struct pciide_channel*)chp; 2736 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2737 int channel = chp->channel; 2738 2739 /* setup DMA if needed */ 2740 pciide_channel_dma_setup(cp); 2741 2742 idedma_ctl = 0; 2743 2744 /* Per channel settings */ 2745 if (PDC_IS_262(sc)) { 2746 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2747 PDC262_U66); 2748 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2749 /* Trimm UDMA mode */ 2750 if ((st & PDC262_STATE_80P(channel)) == 0 || 2751 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 2752 chp->ch_drive[0].UDMA_mode <= 2) || 2753 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 2754 chp->ch_drive[1].UDMA_mode <= 2)) { 2755 if (chp->ch_drive[0].UDMA_mode > 2) 2756 chp->ch_drive[0].UDMA_mode = 2; 2757 if (chp->ch_drive[1].UDMA_mode > 2) 2758 chp->ch_drive[1].UDMA_mode = 2; 2759 } 2760 /* Set U66 if needed */ 2761 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 2762 chp->ch_drive[0].UDMA_mode > 2) || 2763 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 2764 chp->ch_drive[1].UDMA_mode > 2)) 2765 scr |= PDC262_U66_EN(channel); 2766 else 2767 scr &= ~PDC262_U66_EN(channel); 2768 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2769 PDC262_U66, scr); 2770 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 2771 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 2772 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2773 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 2774 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 2775 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 2776 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2777 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 2778 atapi = 0; 2779 else 2780 atapi = PDC262_ATAPI_UDMA; 2781 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 2782 PDC262_ATAPI(channel), atapi); 2783 } 2784 } 2785 for (drive = 0; drive < 2; drive++) { 2786 drvp = &chp->ch_drive[drive]; 2787 /* If no drive, skip */ 2788 if ((drvp->drive_flags & DRIVE) == 0) 2789 continue; 2790 mode = 0; 2791 if (drvp->drive_flags & DRIVE_UDMA) { 2792 mode = PDC2xx_TIM_SET_MB(mode, 2793 pdc2xx_udma_mb[drvp->UDMA_mode]); 2794 mode = PDC2xx_TIM_SET_MC(mode, 2795 pdc2xx_udma_mc[drvp->UDMA_mode]); 2796 drvp->drive_flags &= ~DRIVE_DMA; 2797 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2798 } else if (drvp->drive_flags & DRIVE_DMA) { 2799 mode = PDC2xx_TIM_SET_MB(mode, 2800 pdc2xx_dma_mb[drvp->DMA_mode]); 2801 mode = PDC2xx_TIM_SET_MC(mode, 2802 pdc2xx_dma_mc[drvp->DMA_mode]); 2803 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2804 } else { 2805 mode = PDC2xx_TIM_SET_MB(mode, 2806 pdc2xx_dma_mb[0]); 2807 mode = PDC2xx_TIM_SET_MC(mode, 2808 pdc2xx_dma_mc[0]); 2809 } 2810 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 2811 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 2812 if (drvp->drive_flags & DRIVE_ATA) 2813 mode |= PDC2xx_TIM_PRE; 2814 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 2815 if (drvp->PIO_mode >= 3) { 2816 mode |= PDC2xx_TIM_IORDY; 2817 if (drive == 0) 2818 mode |= PDC2xx_TIM_IORDYp; 2819 } 2820 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 2821 "timings 0x%x\n", 2822 sc->sc_wdcdev.sc_dev.dv_xname, 2823 chp->channel, drive, mode), DEBUG_PROBE); 2824 pci_conf_write(sc->sc_pc, sc->sc_tag, 2825 PDC2xx_TIM(chp->channel, drive), mode); 2826 } 2827 if (idedma_ctl != 0) { 2828 /* Add software bits in status register */ 2829 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2830 IDEDMA_CTL, idedma_ctl); 2831 } 2832 pciide_print_modes(cp); 2833 } 2834 2835 int 2836 pdc202xx_pci_intr(arg) 2837 void *arg; 2838 { 2839 struct pciide_softc *sc = arg; 2840 struct pciide_channel *cp; 2841 struct channel_softc *wdc_cp; 2842 int i, rv, crv; 2843 u_int32_t scr; 2844 2845 rv = 0; 2846 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 2847 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2848 cp = &sc->pciide_channels[i]; 2849 wdc_cp = &cp->wdc_channel; 2850 /* If a compat channel skip. */ 2851 if (cp->compat) 2852 continue; 2853 if (scr & PDC2xx_SCR_INT(i)) { 2854 crv = wdcintr(wdc_cp); 2855 if (crv == 0) 2856 printf("%s:%d: bogus intr\n", 2857 sc->sc_wdcdev.sc_dev.dv_xname, i); 2858 else 2859 rv = 1; 2860 } 2861 } 2862 return rv; 2863 } 2864
Indexes created Tue Sep 23 07:09:52 GMT 2025