pciide.c revision 1.6.2.1
1 /* $NetBSD: pciide.c,v 1.6.2.1 1998/06/04 16:53:17 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI IDE controller driver. 35 * 36 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 37 * sys/dev/pci/ppb.c, revision 1.16). 38 * 39 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 40 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 41 * 5/16/94" from the PCI SIG. 42 * 43 * XXX Does not yet support DMA (but does map the Bus Master DMA regs). 44 * 45 * XXX Does not support serializing the two channels for broken (at least 46 * XXX according to linux and freebsd) controllers, e.g. CMD PCI0640. 47 */ 48 49 #define WDCDEBUG 50 51 #define DEBUG_DMA 0x01 52 #define DEBUG_XFERS 0x02 53 #define DEBUG_FUNCS 0x08 54 #define DEBUG_PROBE 0x10 55 #ifdef WDCDEBUG 56 int wdcdebug_pciide_mask = DEBUG_PROBE; 57 #define WDCDEBUG_PRINT(args, level) \ 58 if (wdcdebug_pciide_mask & (level)) printf args 59 #else 60 #define WDCDEBUG_PRINT(args, level) 61 #endif 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/device.h> 65 #include <sys/malloc.h> 66 67 #include <vm/vm.h> 68 #include <vm/vm_param.h> 69 #include <vm/vm_kern.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcidevs.h> 74 #include <dev/pci/pciidereg.h> 75 #include <dev/pci/pciidevar.h> 76 #include <dev/pci/pciide_pIIx_reg.h> 77 #include <dev/ata/atavar.h> 78 #include <dev/ic/wdcreg.h> 79 #include <dev/ic/wdcvar.h> 80 81 struct pciide_softc { 82 struct wdc_softc sc_wdcdev; /* common wdc definitions */ 83 84 void *sc_pci_ih; /* PCI interrupt handle */ 85 int sc_dma_ok; /* bus-master DMA info */ 86 bus_space_tag_t sc_dma_iot; 87 bus_space_handle_t sc_dma_ioh; 88 bus_dma_tag_t sc_dmat; 89 /* Chip description */ 90 const struct pciide_product_desc *sc_pp; 91 /* common definitions */ 92 struct channel_softc wdc_channels[PCIIDE_NUM_CHANNELS]; 93 /* internal bookkeeping */ 94 struct pciide_channel { /* per-channel data */ 95 int hw_ok; /* hardware mapped & OK? */ 96 int compat; /* is it compat? */ 97 void *ih; /* compat or pci handle */ 98 /* DMA tables and DMA map for xfer, for each drive */ 99 struct pciide_dma_maps { 100 bus_dmamap_t dmamap_table; 101 struct idedma_table *dma_table; 102 bus_dmamap_t dmamap_xfer; 103 } dma_maps[2]; 104 } pciide_channels[PCIIDE_NUM_CHANNELS]; 105 }; 106 107 void default_setup_cap __P((struct pciide_softc*)); 108 void default_setup_chip __P((struct pciide_softc*, 109 pci_chipset_tag_t, pcitag_t)); 110 void piix_setup_cap __P((struct pciide_softc*)); 111 void piix_setup_chip __P((struct pciide_softc*, 112 pci_chipset_tag_t, pcitag_t)); 113 void piix3_4_setup_chip __P((struct pciide_softc*, 114 pci_chipset_tag_t, pcitag_t)); 115 116 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 117 static u_int32_t piix_setup_idetim_drvs __P((u_int8_t, u_int8_t, u_int8_t)); 118 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 119 120 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 121 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 122 void pciide_dma_start __P((void*, int, int, int)); 123 int pciide_dma_finish __P((void*, int, int, int)); 124 125 struct pciide_product_desc { 126 u_int32_t ide_product; 127 int ide_flags; 128 const char *ide_name; 129 /* init controller's capabilities for drives probe */ 130 void (*setup_cap) __P((struct pciide_softc*)); 131 /* init controller after drives probe */ 132 void (*setup_chip) __P((struct pciide_softc*, pci_chipset_tag_t, pcitag_t)); 133 }; 134 135 /* Flags for ide_flags */ 136 #define NO_PCI_INTR 0x01 /* don't try to map the native PCI intr */ 137 #define ONE_QUEUE 0x02 /* device need serialised access */ 138 139 /* Default product description for devices not known from this controller */ 140 const struct pciide_product_desc default_product_desc = { 141 0, 142 0, 143 "Generic PCI IDE controller", 144 default_setup_cap, 145 default_setup_chip 146 }; 147 148 149 const struct pciide_product_desc pciide_intel_products[] = { 150 { PCI_PRODUCT_INTEL_82092AA, 151 0, 152 "Intel 82092AA IDE controller", 153 default_setup_cap, 154 default_setup_chip 155 }, 156 { PCI_PRODUCT_INTEL_82371FB_IDE, 157 0, 158 "Intel 82371FB IDE controller (PIIX)", 159 piix_setup_cap, 160 piix_setup_chip 161 }, 162 { PCI_PRODUCT_INTEL_82371SB_IDE, 163 0, 164 "Intel 82371SB IDE Interface (PIIX3)", 165 piix_setup_cap, 166 piix3_4_setup_chip 167 }, 168 { PCI_PRODUCT_INTEL_82371AB_IDE, 169 0, 170 "Intel 82371AB IDE controller (PIIX4)", 171 piix_setup_cap, 172 piix3_4_setup_chip 173 }, 174 { 0, 175 0, 176 NULL, 177 } 178 }; 179 const struct pciide_product_desc pciide_cmd_products[] = { 180 { PCI_PRODUCT_CMDTECH_640, 181 NO_PCI_INTR | ONE_QUEUE, 182 "CMD Technology PCI0640", 183 default_setup_cap, 184 default_setup_chip 185 }, 186 { 0, 187 0, 188 NULL, 189 } 190 }; 191 192 struct pciide_vendor_desc { 193 u_int32_t ide_vendor; 194 const struct pciide_product_desc *ide_products; 195 }; 196 197 const struct pciide_vendor_desc pciide_vendors[] = { 198 { PCI_VENDOR_INTEL, pciide_intel_products }, 199 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 200 { 0, NULL } 201 }; 202 203 204 #define PCIIDE_CHANNEL_NAME(chan) ((chan) == 0 ? "primary" : "secondary") 205 206 #ifdef __BROKEN_INDIRECT_CONFIG 207 int pciide_match __P((struct device *, void *, void *)); 208 #else 209 int pciide_match __P((struct device *, struct cfdata *, void *)); 210 #endif 211 void pciide_attach __P((struct device *, struct device *, void *)); 212 213 struct cfattach pciide_ca = { 214 sizeof(struct pciide_softc), pciide_match, pciide_attach 215 }; 216 217 int pciide_map_channel_compat __P((struct pciide_softc *, 218 struct pci_attach_args *, int)); 219 const char *pciide_compat_channel_probe __P((struct pciide_softc *, 220 struct pci_attach_args *, int)); 221 int pciide_map_channel_native __P((struct pciide_softc *, 222 struct pci_attach_args *, int)); 223 int pciide_print __P((void *, const char *pnp)); 224 int pciide_compat_intr __P((void *)); 225 int pciide_pci_intr __P((void *)); 226 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 227 228 const struct pciide_product_desc* 229 pciide_lookup_product(id) 230 u_int32_t id; 231 { 232 const struct pciide_product_desc *pp; 233 const struct pciide_vendor_desc *vp; 234 235 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 236 if (PCI_VENDOR(id) == vp->ide_vendor) 237 break; 238 239 if ((pp = vp->ide_products) == NULL) 240 return NULL; 241 242 for (; pp->ide_name != NULL; pp++) 243 if (PCI_PRODUCT(id) == pp->ide_product) 244 break; 245 246 if (pp->ide_name == NULL) 247 return NULL; 248 return pp; 249 } 250 251 int 252 pciide_match(parent, match, aux) 253 struct device *parent; 254 #ifdef __BROKEN_INDIRECT_CONFIG 255 void *match; 256 #else 257 struct cfdata *match; 258 #endif 259 void *aux; 260 { 261 struct pci_attach_args *pa = aux; 262 263 /* 264 * Check the ID register to see that it's a PCI IDE controller. 265 * If it is, we assume that we can deal with it; it _should_ 266 * work in a standardized way... 267 */ 268 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 269 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 270 return (1); 271 } 272 273 return (0); 274 } 275 276 void 277 pciide_attach(parent, self, aux) 278 struct device *parent, *self; 279 void *aux; 280 { 281 struct pci_attach_args *pa = aux; 282 pci_chipset_tag_t pc = pa->pa_pc; 283 pcitag_t tag = pa->pa_tag; 284 struct pciide_softc *sc = (struct pciide_softc *)self; 285 struct pciide_channel *cp; 286 pcireg_t class, interface, csr; 287 pci_intr_handle_t intrhandle; 288 const char *intrstr; 289 char devinfo[256]; 290 int i; 291 292 sc->sc_pp = pciide_lookup_product(pa->pa_id); 293 if (sc->sc_pp == NULL) { 294 sc->sc_pp = &default_product_desc; 295 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 296 printf(": %s (rev. 0x%02x)\n", devinfo, 297 PCI_REVISION(pa->pa_class)); 298 } else { 299 printf(": %s\n", sc->sc_pp->ide_name); 300 } 301 302 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 303 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 304 printf("%s: device disabled (at %s)\n", 305 sc->sc_wdcdev.sc_dev.dv_xname, 306 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? "device" : "bridge"); 307 return; 308 } 309 310 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 311 interface = PCI_INTERFACE(class); 312 313 /* 314 * Set up PCI interrupt. 315 * 316 * If mapping fails, that's (probably) because there's no pin 317 * set to intr, which is (probably) because it's a compat-only 318 * device (or hard-wired in compatibility-only mode). Native-PCI 319 * channels will complain later if the interrupt was needed. 320 * 321 * If establishment fails, that's (probably) some other problem. 322 */ 323 if ((sc->sc_pp->ide_flags & NO_PCI_INTR) == 0) { 324 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 325 pa->pa_intrline, &intrhandle) == 0) { 326 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 327 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, 328 IPL_BIO, pciide_pci_intr, sc); 329 330 if (sc->sc_pci_ih != NULL) { 331 printf("%s: using %s for native-PCI interrupt\n", 332 sc->sc_wdcdev.sc_dev.dv_xname, 333 intrstr ? intrstr : "unknown interrupt"); 334 } else { 335 printf("%s: couldn't establish native-PCI interrupt", 336 sc->sc_wdcdev.sc_dev.dv_xname); 337 if (intrstr != NULL) 338 printf(" at %s", intrstr); 339 printf("\n"); 340 } 341 } 342 } 343 344 /* 345 * Map DMA registers, if DMA is supported. 346 * 347 * Note that sc_dma_ok is the right variable to test to see if 348 * DMA can * be done. If the interface doesn't support DMA, 349 * sc_dma_ok * will never be non-zero. If the DMA regs couldn't 350 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 351 * non-zero if the interface supports DMA and the registers 352 * could be mapped. 353 * 354 * XXX Note that despite the fact that the Bus Master IDE specs 355 * XXX say that "The bus master IDE functoin uses 16 bytes of IO 356 * XXX space," some controllers (at least the United 357 * XXX Microelectronics UM8886BF) place it in memory space. 358 * XXX eventually, we should probably read the register and check 359 * XXX which type it is. Either that or 'quirk' certain devices. 360 */ 361 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 362 sc->sc_dma_ok = (pci_mapreg_map(pa, 363 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0, 364 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 365 sc->sc_dmat = pa->pa_dmat; 366 printf("%s: bus-master DMA support present", 367 sc->sc_wdcdev.sc_dev.dv_xname); 368 if (sc->sc_dma_ok == 0) { 369 printf(", but unused (couldn't map registers)"); 370 } else if (sc->sc_pp == 0) { 371 printf(", but unused (no driver support)"); 372 } else { 373 sc->sc_wdcdev.dma_arg = sc; 374 sc->sc_wdcdev.dma_init = pciide_dma_init; 375 sc->sc_wdcdev.dma_start = pciide_dma_start; 376 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 377 } 378 printf("\n"); 379 } 380 if (sc->sc_pp == NULL) 381 default_setup_cap(sc); 382 else 383 sc->sc_pp->setup_cap(sc); 384 sc->sc_wdcdev.channels = sc->wdc_channels; 385 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 386 387 for (i = 0; i < PCIIDE_NUM_CHANNELS; i++) { 388 cp = &sc->pciide_channels[i]; 389 390 sc->wdc_channels[i].channel = i; 391 sc->wdc_channels[i].wdc = &sc->sc_wdcdev; 392 if (i > 0 && (sc->sc_pp->ide_flags & ONE_QUEUE)) { 393 sc->wdc_channels[i].ch_queue = 394 sc->wdc_channels[0].ch_queue; 395 } else { 396 sc->wdc_channels[i].ch_queue = 397 malloc(sizeof(struct channel_queue), M_DEVBUF, 398 M_NOWAIT); 399 } 400 if (sc->wdc_channels[i].ch_queue == NULL) { 401 printf("%s %s channel: " 402 "can't allocate memory for command queue", 403 sc->sc_wdcdev.sc_dev.dv_xname, 404 PCIIDE_CHANNEL_NAME(i)); 405 continue; 406 } 407 printf("%s: %s channel %s to %s mode\n", 408 sc->sc_wdcdev.sc_dev.dv_xname, 409 PCIIDE_CHANNEL_NAME(i), 410 (interface & PCIIDE_INTERFACE_SETTABLE(i)) ? 411 "configured" : "wired", 412 (interface & PCIIDE_INTERFACE_PCI(i)) ? "native-PCI" : 413 "compatibility"); 414 415 if (interface & PCIIDE_INTERFACE_PCI(i)) 416 cp->hw_ok = pciide_map_channel_native(sc, pa, i); 417 else 418 cp->hw_ok = pciide_map_channel_compat(sc, pa, i); 419 if (!cp->hw_ok) 420 continue; 421 /* Now call common attach routine */ 422 wdcattach(&sc->wdc_channels[i]); 423 } 424 if (sc->sc_pp == NULL) 425 default_setup_chip(sc, pc, tag); 426 else 427 sc->sc_pp->setup_chip(sc, pc, tag); 428 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 429 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 430 } 431 432 int 433 pciide_map_channel_compat(sc, pa, chan) 434 struct pciide_softc *sc; 435 struct pci_attach_args *pa; 436 int chan; 437 { 438 struct pciide_channel *cp = &sc->pciide_channels[chan]; 439 struct channel_softc *wdc_cp = &sc->wdc_channels[chan]; 440 const char *probe_fail_reason; 441 int rv = 1; 442 443 cp->compat = 1; 444 445 wdc_cp->cmd_iot = pa->pa_iot; 446 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(chan), 447 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 448 printf("%s: couldn't map %s channel cmd regs\n", 449 sc->sc_wdcdev.sc_dev.dv_xname, 450 PCIIDE_CHANNEL_NAME(chan)); 451 rv = 0; 452 } 453 454 wdc_cp->ctl_iot = pa->pa_iot; 455 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(chan), 456 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 457 printf("%s: couldn't map %s channel ctl regs\n", 458 sc->sc_wdcdev.sc_dev.dv_xname, 459 PCIIDE_CHANNEL_NAME(chan)); 460 rv = 0; 461 } 462 463 /* 464 * If we weren't able to map the device successfully, 465 * we just give up now. Something else has already 466 * occupied those ports, indicating that the device has 467 * (probably) been completely disabled (by some nonstandard 468 * mechanism). 469 * 470 * XXX If we successfully map some ports, but not others, 471 * XXX it might make sense to unmap the ones that we mapped. 472 */ 473 if (rv == 0) 474 goto out; 475 476 /* 477 * If we were able to map the device successfully, try to 478 * make sure that there's a wdc there and that it's 479 * attributable to us. 480 * 481 * If there's not, then we assume that there's the device 482 * has been disabled and that other devices are free to use 483 * its ports. 484 */ 485 probe_fail_reason = pciide_compat_channel_probe(sc, pa, chan); 486 if (probe_fail_reason != NULL) { 487 printf("%s: %s channel ignored (%s)\n", 488 sc->sc_wdcdev.sc_dev.dv_xname, 489 PCIIDE_CHANNEL_NAME(chan), probe_fail_reason); 490 rv = 0; 491 492 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 493 PCIIDE_COMPAT_CMD_SIZE); 494 bus_space_unmap(wdc_cp->ctl_iot, wdc_cp->ctl_ioh, 495 PCIIDE_COMPAT_CTL_SIZE); 496 497 goto out; 498 } 499 500 /* 501 * If we're here, we were able to map the device successfully 502 * and it really looks like there's a controller there. 503 * 504 * Unless those conditions are true, we don't map the 505 * compatibility interrupt. The spec indicates that if a 506 * channel is configured for compatibility mode and the PCI 507 * device's I/O space is enabled, the channel will be enabled. 508 * Hoewver, some devices seem to be able to disable invididual 509 * compatibility channels (via non-standard mechanisms). If 510 * the channel is disabled, the interrupt line can (probably) 511 * be used by other devices (and may be assigned to other 512 * devices by the BIOS). If we mapped the interrupt we might 513 * conflict with another interrupt assignment. 514 */ 515 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 516 pa, chan, pciide_compat_intr, wdc_cp); 517 if (cp->ih == NULL) { 518 printf("%s: no compatibility interrupt for use by %s channel\n", 519 sc->sc_wdcdev.sc_dev.dv_xname, 520 PCIIDE_CHANNEL_NAME(chan)); 521 rv = 0; 522 } 523 524 out: 525 return (rv); 526 } 527 528 const char * 529 pciide_compat_channel_probe(sc, pa, chan) 530 struct pciide_softc *sc; 531 struct pci_attach_args *pa; 532 { 533 pcireg_t csr; 534 const char *failreason = NULL; 535 536 /* 537 * Check to see if something appears to be there. 538 */ 539 if (!wdcprobe(&sc->wdc_channels[chan])) { 540 failreason = "not responding; disabled or no drives?"; 541 goto out; 542 } 543 544 /* 545 * Now, make sure it's actually attributable to this PCI IDE 546 * channel by trying to access the channel again while the 547 * PCI IDE controller's I/O space is disabled. (If the 548 * channel no longer appears to be there, it belongs to 549 * this controller.) YUCK! 550 */ 551 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 552 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 553 csr & ~PCI_COMMAND_IO_ENABLE); 554 if (wdcprobe(&sc->wdc_channels[chan])) 555 failreason = "other hardware responding at addresses"; 556 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 557 558 out: 559 return (failreason); 560 } 561 562 int 563 pciide_map_channel_native(sc, pa, chan) 564 struct pciide_softc *sc; 565 struct pci_attach_args *pa; 566 int chan; 567 { 568 struct pciide_channel *cp = &sc->pciide_channels[chan]; 569 struct channel_softc *wdc_cp = &sc->wdc_channels[chan]; 570 int rv = 1; 571 572 cp->compat = 0; 573 574 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(chan), PCI_MAPREG_TYPE_IO, 575 0, &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, NULL) != 0) { 576 printf("%s: couldn't map %s channel cmd regs\n", 577 sc->sc_wdcdev.sc_dev.dv_xname, 578 PCIIDE_CHANNEL_NAME(chan)); 579 rv = 0; 580 } 581 582 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(chan), PCI_MAPREG_TYPE_IO, 583 0, &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, NULL) != 0) { 584 printf("%s: couldn't map %s channel ctl regs\n", 585 sc->sc_wdcdev.sc_dev.dv_xname, 586 PCIIDE_CHANNEL_NAME(chan)); 587 rv = 0; 588 } 589 590 if ((cp->ih = sc->sc_pci_ih) == NULL) { 591 printf("%s: no native-PCI interrupt for use by %s channel\n", 592 sc->sc_wdcdev.sc_dev.dv_xname, 593 PCIIDE_CHANNEL_NAME(chan)); 594 rv = 0; 595 } 596 597 return (rv); 598 } 599 600 int 601 pciide_compat_intr(arg) 602 void *arg; 603 { 604 struct channel_softc *wdc_cp = arg; 605 606 #ifdef DIAGNOSTIC 607 struct pciide_softc *sc = (struct pciide_softc*)wdc_cp->wdc; 608 struct pciide_channel *cp = &sc->pciide_channels[wdc_cp->channel]; 609 /* should only be called for a compat channel */ 610 if (cp->compat == 0) 611 panic("pciide compat intr called for non-compat chan %p\n", cp); 612 #endif 613 return (wdcintr(wdc_cp)); 614 } 615 616 int 617 pciide_pci_intr(arg) 618 void *arg; 619 { 620 struct pciide_softc *sc = arg; 621 struct pciide_channel *cp; 622 struct channel_softc *wdc_cp; 623 int i, rv, crv; 624 625 rv = 0; 626 for (i = 0; i < PCIIDE_NUM_CHANNELS; i++) { 627 cp = &sc->pciide_channels[i]; 628 wdc_cp = &sc->wdc_channels[i]; 629 630 /* If a compat channel skip. */ 631 if (cp->compat) 632 continue; 633 /* if this channel not waiting for intr, skip */ 634 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 635 continue; 636 637 crv = wdcintr(wdc_cp); 638 if (crv == 0) 639 ; /* leave rv alone */ 640 else if (crv == 1) 641 rv = 1; /* claim the intr */ 642 else if (rv == 0) /* crv should be -1 in this case */ 643 rv = crv; /* if we've done no better, take it */ 644 } 645 return (rv); 646 } 647 648 void 649 default_setup_cap(sc) 650 struct pciide_softc *sc; 651 { 652 if (sc->sc_dma_ok) 653 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 654 sc->sc_wdcdev.pio_mode = 2; /* I _think_ all PCI controllers are >= 2 */ 655 sc->sc_wdcdev.dma_mode = 0; 656 } 657 658 void 659 default_setup_chip(sc, pc, tag) 660 struct pciide_softc *sc; 661 pci_chipset_tag_t pc; 662 pcitag_t tag; 663 { 664 /* Nothing to do if we don't know what chip we have */ 665 } 666 667 void 668 piix_setup_cap(sc) 669 struct pciide_softc *sc; 670 { 671 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371AB_IDE) 672 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 673 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DMA; 674 sc->sc_wdcdev.pio_mode = 4; 675 sc->sc_wdcdev.dma_mode = 2; 676 } 677 678 void 679 piix_setup_chip(sc, pc, tag) 680 struct pciide_softc *sc; 681 pci_chipset_tag_t pc; 682 pcitag_t tag; 683 { 684 struct channel_softc *chp; 685 u_int8_t mode[2]; 686 u_int8_t channel, drive; 687 u_int32_t idetim, sidetim, idedma_ctl; 688 struct ata_drive_datas *drvp; 689 690 idetim = sidetim = 0; 691 692 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x, sidetim=0x%x\n", 693 pci_conf_read(pc, tag, PIIX_IDETIM), 694 pci_conf_read(pc, tag, PIIX_SIDETIM)), DEBUG_PROBE); 695 696 for (channel = 0; channel < PCIIDE_NUM_CHANNELS; channel++) { 697 chp = &sc->wdc_channels[channel]; 698 drvp = chp->ch_drive; 699 idedma_ctl = 0; 700 /* Enable IDE registers decode */ 701 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 702 channel); 703 704 /* setup DMA if needed */ 705 for (drive = 0; drive < 2; drive++) { 706 if (drvp[drive].drive_flags & DRIVE_DMA && 707 pciide_dma_table_setup(sc, channel, drive) != 0) { 708 drvp[drive].drive_flags &= ~DRIVE_DMA; 709 } 710 } 711 712 /* 713 * Here we have to mess up with drives mode: PIIX can't have 714 * different timings for master and slave drives. 715 * We need to find the best combination. 716 */ 717 718 /* If both drives supports DMA, takes the lower mode */ 719 if ((drvp[0].drive_flags & DRIVE_DMA) && 720 (drvp[1].drive_flags & DRIVE_DMA)) { 721 mode[0] = mode[1] = 722 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 723 goto ok; 724 } 725 /* 726 * If only one drive supports DMA, use its mode, and 727 * put the other one in PIO mode 0 if mode not compatible 728 */ 729 if (drvp[0].drive_flags & DRIVE_DMA) { 730 mode[0] = drvp[0].DMA_mode; 731 mode[1] = drvp[1].PIO_mode; 732 if (piix_isp_pio[mode[1]] < piix_isp_dma[mode[0]] || 733 piix_rtc_pio[mode[1]] < piix_rtc_dma[mode[0]]) 734 mode[1] = 0; 735 goto ok; 736 } 737 if (drvp[1].drive_flags & DRIVE_DMA) { 738 mode[1] = drvp[1].DMA_mode; 739 mode[0] = drvp[0].PIO_mode; 740 if (piix_isp_pio[mode[0]] < piix_isp_dma[mode[1]] || 741 piix_rtc_pio[mode[0]] < piix_rtc_dma[mode[1]]) 742 mode[0] = 0; 743 goto ok; 744 } 745 /* 746 * If both drives are not DMA, takes the lower mode, unless 747 * one of them is PIO mode 0 748 */ 749 if (drvp[0].PIO_mode == 0) { 750 mode[0] = 0; 751 mode[1] = drvp[1].PIO_mode; 752 } else if (drvp[1].PIO_mode == 0) { 753 mode[1] = 0; 754 mode[0] = drvp[0].PIO_mode; 755 } else { 756 mode[0] = mode[1] = 757 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 758 } 759 ok: /* The modes are setup */ 760 for (drive = 0; drive < 2; drive++) { 761 if (drvp[drive].drive_flags & DRIVE_DMA) { 762 idetim |= piix_setup_idetim_timings( 763 mode[drive], 1, channel); 764 goto end; 765 } 766 } 767 /* If we are there, none of the drives are DMA */ 768 if (mode[0] > 0) 769 idetim |= piix_setup_idetim_timings( 770 mode[0], 0, channel); 771 else 772 idetim |= piix_setup_idetim_timings( 773 mode[1], 0, channel); 774 end: /* 775 * timing mode is now set up in the controller. Enable 776 * it per-drive 777 */ 778 for (drive = 0; drive < 2; drive++) { 779 if (drvp[drive].drive_flags & DRIVE_DMA) { 780 idetim = PIIX_IDETIM_SET(idetim, 781 PIIX_IDETIM_DTE(drive), channel); 782 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 783 drvp[drive].DMA_mode = mode[drive]; 784 drvp[drive].PIO_mode = 0; 785 printf("%s:%d:%d: using DMA mode %d\n", 786 sc->sc_wdcdev.sc_dev.dv_xname, 787 channel, drive, mode[drive]); 788 } else { 789 if (mode[drive] > 0) 790 idetim |= piix_setup_idetim_drvs( 791 mode[drive], channel, drive); 792 drvp[drive].PIO_mode = mode[drive]; 793 printf("%s:%d:%d: using PIO mode %d\n", 794 sc->sc_wdcdev.sc_dev.dv_xname, 795 channel, drive, mode[drive]); 796 } 797 } 798 if (idedma_ctl != 0) { 799 /* Add software bits in status register */ 800 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 801 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 802 idedma_ctl); 803 } 804 } 805 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x, sidetim=0x%x\n", 806 idetim, sidetim), DEBUG_PROBE); 807 pci_conf_write(pc, tag, PIIX_IDETIM, idetim); 808 pci_conf_write(pc, tag, PIIX_SIDETIM, sidetim); 809 } 810 811 void 812 piix3_4_setup_chip(sc, pc, tag) 813 struct pciide_softc *sc; 814 pci_chipset_tag_t pc; 815 pcitag_t tag; 816 { 817 int channel, drive; 818 struct channel_softc *chp; 819 struct ata_drive_datas *drvp; 820 u_int32_t idetim, sidetim, udmactl, udmatim, idedma_ctl; 821 822 idetim = sidetim = udmactl = udmatim = 0; 823 824 WDCDEBUG_PRINT(("piix3_4_setup_chip: old idetim=0x%x, sidetim=0x%x\n", 825 pci_conf_read(pc, tag, PIIX_IDETIM), 826 pci_conf_read(pc, tag, PIIX_SIDETIM)), DEBUG_PROBE); 827 for (channel = 0; channel < PCIIDE_NUM_CHANNELS; channel++) { 828 chp = &sc->wdc_channels[channel]; 829 idedma_ctl = 0; 830 /* Enable IDE registers decode */ 831 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 832 channel); 833 for (drive = 0; drive < 2; drive++) { 834 drvp = &chp->ch_drive[drive]; 835 /* If no drive, skip */ 836 if ((drvp->drive_flags & DRIVE) == 0) 837 continue; 838 /* add timing values, setup DMA if needed */ 839 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 840 (drvp->drive_flags & DRIVE_UDMA) == 0) || 841 sc->sc_dma_ok == 0) 842 goto pio; 843 if (pciide_dma_table_setup(sc, channel, drive) != 0) 844 goto pio; /* Abort DMA setup */ 845 drvp->PIO_mode = 0; /* use compatible timings for PIO */ 846 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 847 (drvp->drive_flags & DRIVE_UDMA)) { 848 /* use Ultra/DMA */ 849 drvp->drive_flags &= ~DRIVE_DMA; 850 udmactl |= PIIX_UDMACTL_DRV_EN( 851 channel, drive); 852 udmatim |= PIIX_UDMATIM_SET( 853 piix4_sct_udma[drvp->UDMA_mode], 854 channel, drive); 855 printf("%s:%d:%d: using Ultra DMA/33 mode %d\n", 856 sc->sc_wdcdev.sc_dev.dv_xname, 857 channel, drive, 858 drvp->UDMA_mode); 859 } else { 860 /* use Multiword DMA */ 861 drvp->drive_flags &= ~DRIVE_UDMA; 862 if (drive == 0) { 863 idetim |= piix_setup_idetim_timings( 864 drvp->DMA_mode, 1, channel); 865 } else { 866 sidetim |= piix_setup_sidetim_timings( 867 drvp->DMA_mode, 1, channel); 868 idetim =PIIX_IDETIM_SET(idetim, 869 PIIX_IDETIM_SITRE, channel); 870 } 871 printf("%s:%d:%d: using DMA mode %d\n", 872 sc->sc_wdcdev.sc_dev.dv_xname, 873 channel, drive, 874 drvp->DMA_mode); 875 } 876 /* Enable DMA only PIO modes may be wrong */ 877 idetim = PIIX_IDETIM_SET(idetim, 878 PIIX_IDETIM_DTE(drive), channel); 879 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 880 continue; 881 882 pio: /* use PIO mode */ 883 drvp->drive_flags &= ~DRIVE_DMA | DRIVE_UDMA; 884 if (drive == 0) { 885 idetim |= piix_setup_idetim_timings( 886 drvp->PIO_mode, 0, channel); 887 } else { 888 sidetim |= piix_setup_sidetim_timings( 889 drvp->PIO_mode, 0, channel); 890 idetim =PIIX_IDETIM_SET(idetim, 891 PIIX_IDETIM_SITRE, channel); 892 } 893 idetim |= piix_setup_idetim_drvs(drvp->PIO_mode, 894 channel, drive); 895 printf("%s:%d:%d: using PIO mode %d\n", 896 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, 897 drvp->PIO_mode); 898 } 899 if (idedma_ctl != 0) { 900 /* Add software bits in status register */ 901 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 902 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 903 idedma_ctl); 904 } 905 } 906 907 WDCDEBUG_PRINT(("piix3_4_setup_chip: idetim=0x%x, sidetim=0x%x", 908 idetim, sidetim), DEBUG_PROBE); 909 if (chp->wdc->cap & WDC_CAPABILITY_UDMA) { 910 WDCDEBUG_PRINT((", udmactl=0x%x, udmatim=0x%x", udmactl, 911 udmatim), DEBUG_PROBE); 912 pci_conf_write(pc, tag, PIIX_UDMACTL, udmactl); 913 pci_conf_write(pc, tag, PIIX_UDMATIM, udmatim); 914 } 915 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 916 pci_conf_write(pc, tag, PIIX_IDETIM, idetim); 917 pci_conf_write(pc, tag, PIIX_SIDETIM, sidetim); 918 } 919 920 /* setup ISP and RTC fields, based on mode */ 921 static u_int32_t 922 piix_setup_idetim_timings(mode, dma, channel) 923 u_int8_t mode; 924 u_int8_t dma; 925 u_int8_t channel; 926 { 927 928 if (dma) 929 return PIIX_IDETIM_SET(0, 930 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 931 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 932 channel); 933 else 934 return PIIX_IDETIM_SET(0, 935 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 936 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 937 channel); 938 } 939 940 /* setup PPE, IE and TIME1 field based on PIO mode */ 941 static u_int32_t 942 piix_setup_idetim_drvs(mode, channel, drive) 943 u_int8_t mode; 944 u_int8_t channel; 945 u_int8_t drive; 946 { 947 u_int32_t ret = 0; 948 949 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 950 /* I didn't read anything about this, it's just a guess */ 951 if (mode >= 2) 952 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 953 if (mode >= 3) 954 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 955 return ret; 956 } 957 958 /* setup values in SIDETIM registers, based on mode */ 959 static u_int32_t 960 piix_setup_sidetim_timings(mode, dma, channel) 961 u_int8_t mode; 962 u_int8_t dma; 963 u_int8_t channel; 964 { 965 if (dma) 966 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 967 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 968 else 969 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 970 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 971 } 972 973 974 975 int 976 pciide_dma_table_setup(sc, channel, drive) 977 struct pciide_softc *sc; 978 int channel, drive; 979 { 980 bus_dma_segment_t seg; 981 int error, rseg; 982 const bus_size_t dma_table_size = 983 sizeof(struct idedma_table) * NIDEDMA_TABLES; 984 struct pciide_dma_maps *dma_maps = 985 &sc->pciide_channels[channel].dma_maps[drive]; 986 987 /* Allocate memory for the DMA tables and map it */ 988 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 989 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 990 BUS_DMA_NOWAIT)) != 0) { 991 printf("%s:%d: unable to allocate table DMA for" 992 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 993 channel, drive, error); 994 return error; 995 } 996 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 997 dma_table_size, 998 (caddr_t *)&dma_maps->dma_table, 999 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1000 printf("%s:%d: unable to map table DMA for" 1001 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1002 channel, drive, error); 1003 return error; 1004 } 1005 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 1006 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 1007 seg.ds_addr), DEBUG_PROBE); 1008 1009 /* Create and load table DMA map for this disk */ 1010 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1011 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1012 &dma_maps->dmamap_table)) != 0) { 1013 printf("%s:%d: unable to create table DMA map for" 1014 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1015 channel, drive, error); 1016 return error; 1017 } 1018 if ((error = bus_dmamap_load(sc->sc_dmat, 1019 dma_maps->dmamap_table, 1020 dma_maps->dma_table, 1021 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1022 printf("%s:%d: unable to load table DMA map for" 1023 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1024 channel, drive, error); 1025 return error; 1026 } 1027 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1028 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 1029 /* Create a xfer DMA map for this drive */ 1030 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1031 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1032 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1033 &dma_maps->dmamap_xfer)) != 0) { 1034 printf("%s:%d: unable to create xfer DMA map for" 1035 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1036 channel, drive, error); 1037 return error; 1038 } 1039 return 0; 1040 } 1041 1042 int 1043 pciide_dma_init(v, channel, drive, databuf, datalen, read) 1044 void *v; 1045 int channel, drive; 1046 void *databuf; 1047 size_t datalen; 1048 int read; 1049 { 1050 struct pciide_softc *sc = v; 1051 int error, seg; 1052 struct pciide_dma_maps *dma_maps = 1053 &sc->pciide_channels[channel].dma_maps[drive]; 1054 1055 error = bus_dmamap_load(sc->sc_dmat, 1056 dma_maps->dmamap_xfer, 1057 databuf, datalen, NULL, BUS_DMA_NOWAIT); 1058 if (error) { 1059 printf("%s:%d: unable to load xfer DMA map for" 1060 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1061 channel, drive, error); 1062 return error; 1063 } 1064 1065 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1066 dma_maps->dmamap_xfer->dm_mapsize, 1067 (read) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1068 1069 WDCDEBUG_PRINT(("pciide_dma_init: %d segs for %p len %d (phy 0x%x)\n", 1070 dma_maps->dmamap_xfer->dm_nsegs, databuf, datalen, 1071 vtophys(databuf)), DEBUG_DMA|DEBUG_XFERS); 1072 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1073 #ifdef DIAGNOSTIC 1074 /* A segment must not cross a 64k boundary */ 1075 { 1076 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1077 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1078 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1079 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1080 printf("pciide_dma: segment %d physical addr 0x%lx" 1081 " len 0x%lx not properly aligned\n", 1082 seg, phys, len); 1083 panic("pciide_dma: buf align"); 1084 } 1085 } 1086 #endif 1087 dma_maps->dma_table[seg].base_addr = 1088 dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1089 dma_maps->dma_table[seg].byte_count = 1090 dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1091 IDEDMA_BYTE_COUNT_MASK; 1092 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1093 seg, dma_maps->dma_table[seg].byte_count, 1094 dma_maps->dma_table[seg].base_addr), DEBUG_DMA); 1095 1096 } 1097 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1098 IDEDMA_BYTE_COUNT_EOT; 1099 1100 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1101 dma_maps->dmamap_table->dm_mapsize, 1102 BUS_DMASYNC_PREWRITE); 1103 1104 /* Maps are ready. Start DMA function */ 1105 #ifdef DIAGNOSTIC 1106 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1107 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1108 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1109 panic("pciide_dma_init: table align"); 1110 } 1111 #endif 1112 1113 WDCDEBUG_PRINT(("phy addr of table at %p = 0x%lx len %ld (%d segs, " 1114 "phys 0x%x)\n", 1115 dma_maps->dma_table, 1116 dma_maps->dmamap_table->dm_segs[0].ds_addr, 1117 dma_maps->dmamap_table->dm_segs[0].ds_len, 1118 dma_maps->dmamap_table->dm_nsegs, 1119 vtophys(dma_maps->dma_table)), DEBUG_DMA); 1120 /* Clear status bits */ 1121 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1122 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1123 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1124 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1125 /* Write table addr */ 1126 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1127 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1128 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1129 /* set read/write */ 1130 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1131 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1132 (read) ? IDEDMA_CMD_WRITE: 0); 1133 return 0; 1134 } 1135 1136 void 1137 pciide_dma_start(v, channel, drive, read) 1138 void *v; 1139 int channel, drive; 1140 { 1141 struct pciide_softc *sc = v; 1142 1143 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1144 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1145 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1146 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1147 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1148 } 1149 1150 int 1151 pciide_dma_finish(v, channel, drive, read) 1152 void *v; 1153 int channel, drive; 1154 int read; 1155 { 1156 struct pciide_softc *sc = v; 1157 u_int8_t status; 1158 struct pciide_dma_maps *dma_maps = 1159 &sc->pciide_channels[channel].dma_maps[drive]; 1160 1161 /* Unload the map of the data buffer */ 1162 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1163 dma_maps->dmamap_xfer->dm_mapsize, 1164 (read) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1165 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1166 1167 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1168 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1169 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1170 DEBUG_XFERS); 1171 1172 /* stop DMA channel */ 1173 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1174 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1175 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1176 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1177 1178 /* Clear status bits */ 1179 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1180 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1181 status); 1182 1183 if ((status & (IDEDMA_CTL_INTR | IDEDMA_CTL_ERR | IDEDMA_CTL_ACT)) != 1184 IDEDMA_CTL_INTR) { 1185 printf("%s:%d:%d: Bus-Master DMA error: status=0x%x\n", 1186 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1187 return 1; 1188 } 1189 return 0; 1190 } 1191
Indexes created Thu Oct 02 10:09:58 GMT 2025