pciide.c revision 1.6.2.6
1 /* $NetBSD: pciide.c,v 1.6.2.6 1998/06/10 11:29:25 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Christopher G. Demetriou 17 * for the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * PCI IDE controller driver. 35 * 36 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 37 * sys/dev/pci/ppb.c, revision 1.16). 38 * 39 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 40 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 41 * 5/16/94" from the PCI SIG. 42 * 43 * XXX Does not yet support DMA (but does map the Bus Master DMA regs). 44 * 45 * XXX Does not support serializing the two channels for broken (at least 46 * XXX according to linux and freebsd) controllers, e.g. CMD PCI0640. 47 */ 48 49 #define WDCDEBUG 50 51 #define DEBUG_DMA 0x01 52 #define DEBUG_XFERS 0x02 53 #define DEBUG_FUNCS 0x08 54 #define DEBUG_PROBE 0x10 55 #ifdef WDCDEBUG 56 int wdcdebug_pciide_mask = DEBUG_PROBE; 57 #define WDCDEBUG_PRINT(args, level) \ 58 if (wdcdebug_pciide_mask & (level)) printf args 59 #else 60 #define WDCDEBUG_PRINT(args, level) 61 #endif 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/device.h> 65 #include <sys/malloc.h> 66 67 #include <vm/vm.h> 68 #include <vm/vm_param.h> 69 #include <vm/vm_kern.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcidevs.h> 74 #include <dev/pci/pciidereg.h> 75 #include <dev/pci/pciidevar.h> 76 #include <dev/pci/pciide_piix_reg.h> 77 #include <dev/ata/atavar.h> 78 #include <dev/ic/wdcreg.h> 79 #include <dev/ic/wdcvar.h> 80 81 struct pciide_softc { 82 struct wdc_softc sc_wdcdev; /* common wdc definitions */ 83 84 void *sc_pci_ih; /* PCI interrupt handle */ 85 int sc_dma_ok; /* bus-master DMA info */ 86 bus_space_tag_t sc_dma_iot; 87 bus_space_handle_t sc_dma_ioh; 88 bus_dma_tag_t sc_dmat; 89 /* Chip description */ 90 const struct pciide_product_desc *sc_pp; 91 /* common definitions */ 92 struct channel_softc wdc_channels[PCIIDE_NUM_CHANNELS]; 93 /* internal bookkeeping */ 94 struct pciide_channel { /* per-channel data */ 95 int hw_ok; /* hardware mapped & OK? */ 96 int compat; /* is it compat? */ 97 void *ih; /* compat or pci handle */ 98 /* DMA tables and DMA map for xfer, for each drive */ 99 struct pciide_dma_maps { 100 bus_dmamap_t dmamap_table; 101 struct idedma_table *dma_table; 102 bus_dmamap_t dmamap_xfer; 103 } dma_maps[2]; 104 } pciide_channels[PCIIDE_NUM_CHANNELS]; 105 }; 106 107 void default_setup_cap __P((struct pciide_softc*)); 108 void default_setup_chip __P((struct pciide_softc*, 109 pci_chipset_tag_t, pcitag_t)); 110 void piix_setup_cap __P((struct pciide_softc*)); 111 void piix_setup_chip __P((struct pciide_softc*, 112 pci_chipset_tag_t, pcitag_t)); 113 void piix3_4_setup_chip __P((struct pciide_softc*, 114 pci_chipset_tag_t, pcitag_t)); 115 116 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 117 static u_int32_t piix_setup_idetim_drvs __P((u_int8_t, u_int8_t, u_int8_t)); 118 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 119 120 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 121 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 122 void pciide_dma_start __P((void*, int, int, int)); 123 int pciide_dma_finish __P((void*, int, int, int)); 124 125 struct pciide_product_desc { 126 u_int32_t ide_product; 127 int ide_flags; 128 const char *ide_name; 129 /* init controller's capabilities for drives probe */ 130 void (*setup_cap) __P((struct pciide_softc*)); 131 /* init controller after drives probe */ 132 void (*setup_chip) __P((struct pciide_softc*, pci_chipset_tag_t, pcitag_t)); 133 }; 134 135 /* Flags for ide_flags */ 136 #define NO_PCI_INTR 0x01 /* don't try to map the native PCI intr */ 137 #define ONE_QUEUE 0x02 /* device need serialised access */ 138 139 /* Default product description for devices not known from this controller */ 140 const struct pciide_product_desc default_product_desc = { 141 0, 142 0, 143 "Generic PCI IDE controller", 144 default_setup_cap, 145 default_setup_chip 146 }; 147 148 149 const struct pciide_product_desc pciide_intel_products[] = { 150 { PCI_PRODUCT_INTEL_82092AA, 151 0, 152 "Intel 82092AA IDE controller", 153 default_setup_cap, 154 default_setup_chip 155 }, 156 { PCI_PRODUCT_INTEL_82371FB_IDE, 157 0, 158 "Intel 82371FB IDE controller (PIIX)", 159 piix_setup_cap, 160 piix_setup_chip 161 }, 162 { PCI_PRODUCT_INTEL_82371SB_IDE, 163 0, 164 "Intel 82371SB IDE Interface (PIIX3)", 165 piix_setup_cap, 166 piix3_4_setup_chip 167 }, 168 { PCI_PRODUCT_INTEL_82371AB_IDE, 169 0, 170 "Intel 82371AB IDE controller (PIIX4)", 171 piix_setup_cap, 172 piix3_4_setup_chip 173 }, 174 { 0, 175 0, 176 NULL, 177 } 178 }; 179 const struct pciide_product_desc pciide_cmd_products[] = { 180 { PCI_PRODUCT_CMDTECH_640, 181 NO_PCI_INTR | ONE_QUEUE, 182 "CMD Technology PCI0640", 183 default_setup_cap, 184 default_setup_chip 185 }, 186 { 0, 187 0, 188 NULL, 189 } 190 }; 191 192 struct pciide_vendor_desc { 193 u_int32_t ide_vendor; 194 const struct pciide_product_desc *ide_products; 195 }; 196 197 const struct pciide_vendor_desc pciide_vendors[] = { 198 { PCI_VENDOR_INTEL, pciide_intel_products }, 199 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 200 { 0, NULL } 201 }; 202 203 204 #define PCIIDE_CHANNEL_NAME(chan) ((chan) == 0 ? "primary" : "secondary") 205 206 int pciide_match __P((struct device *, struct cfdata *, void *)); 207 void pciide_attach __P((struct device *, struct device *, void *)); 208 209 struct cfattach pciide_ca = { 210 sizeof(struct pciide_softc), pciide_match, pciide_attach 211 }; 212 213 int pciide_map_channel_compat __P((struct pciide_softc *, 214 struct pci_attach_args *, int)); 215 const char *pciide_compat_channel_probe __P((struct pciide_softc *, 216 struct pci_attach_args *, int)); 217 int pciide_map_channel_native __P((struct pciide_softc *, 218 struct pci_attach_args *, int)); 219 int pciide_print __P((void *, const char *pnp)); 220 int pciide_compat_intr __P((void *)); 221 int pciide_pci_intr __P((void *)); 222 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 223 224 const struct pciide_product_desc* 225 pciide_lookup_product(id) 226 u_int32_t id; 227 { 228 const struct pciide_product_desc *pp; 229 const struct pciide_vendor_desc *vp; 230 231 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 232 if (PCI_VENDOR(id) == vp->ide_vendor) 233 break; 234 235 if ((pp = vp->ide_products) == NULL) 236 return NULL; 237 238 for (; pp->ide_name != NULL; pp++) 239 if (PCI_PRODUCT(id) == pp->ide_product) 240 break; 241 242 if (pp->ide_name == NULL) 243 return NULL; 244 return pp; 245 } 246 247 int 248 pciide_match(parent, match, aux) 249 struct device *parent; 250 struct cfdata *match; 251 void *aux; 252 { 253 struct pci_attach_args *pa = aux; 254 255 /* 256 * Check the ID register to see that it's a PCI IDE controller. 257 * If it is, we assume that we can deal with it; it _should_ 258 * work in a standardized way... 259 */ 260 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 261 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 262 return (1); 263 } 264 265 return (0); 266 } 267 268 void 269 pciide_attach(parent, self, aux) 270 struct device *parent, *self; 271 void *aux; 272 { 273 struct pci_attach_args *pa = aux; 274 pci_chipset_tag_t pc = pa->pa_pc; 275 pcitag_t tag = pa->pa_tag; 276 struct pciide_softc *sc = (struct pciide_softc *)self; 277 struct pciide_channel *cp; 278 pcireg_t class, interface, csr; 279 pci_intr_handle_t intrhandle; 280 const char *intrstr; 281 char devinfo[256]; 282 int i; 283 284 sc->sc_pp = pciide_lookup_product(pa->pa_id); 285 if (sc->sc_pp == NULL) { 286 sc->sc_pp = &default_product_desc; 287 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 288 printf(": %s (rev. 0x%02x)\n", devinfo, 289 PCI_REVISION(pa->pa_class)); 290 } else { 291 printf(": %s\n", sc->sc_pp->ide_name); 292 } 293 294 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 295 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 296 printf("%s: device disabled (at %s)\n", 297 sc->sc_wdcdev.sc_dev.dv_xname, 298 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? "device" : "bridge"); 299 return; 300 } 301 302 class = pci_conf_read(pc, tag, PCI_CLASS_REG); 303 interface = PCI_INTERFACE(class); 304 305 /* 306 * Set up PCI interrupt. 307 * 308 * If mapping fails, that's (probably) because there's no pin 309 * set to intr, which is (probably) because it's a compat-only 310 * device (or hard-wired in compatibility-only mode). Native-PCI 311 * channels will complain later if the interrupt was needed. 312 * 313 * If establishment fails, that's (probably) some other problem. 314 */ 315 if ((sc->sc_pp->ide_flags & NO_PCI_INTR) == 0) { 316 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 317 pa->pa_intrline, &intrhandle) == 0) { 318 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 319 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, 320 IPL_BIO, pciide_pci_intr, sc); 321 322 if (sc->sc_pci_ih != NULL) { 323 printf("%s: using %s for native-PCI interrupt\n", 324 sc->sc_wdcdev.sc_dev.dv_xname, 325 intrstr ? intrstr : "unknown interrupt"); 326 } else { 327 printf("%s: couldn't establish native-PCI interrupt", 328 sc->sc_wdcdev.sc_dev.dv_xname); 329 if (intrstr != NULL) 330 printf(" at %s", intrstr); 331 printf("\n"); 332 } 333 } 334 } 335 336 /* 337 * Map DMA registers, if DMA is supported. 338 * 339 * Note that sc_dma_ok is the right variable to test to see if 340 * DMA can * be done. If the interface doesn't support DMA, 341 * sc_dma_ok * will never be non-zero. If the DMA regs couldn't 342 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 343 * non-zero if the interface supports DMA and the registers 344 * could be mapped. 345 * 346 * XXX Note that despite the fact that the Bus Master IDE specs 347 * XXX say that "The bus master IDE functoin uses 16 bytes of IO 348 * XXX space," some controllers (at least the United 349 * XXX Microelectronics UM8886BF) place it in memory space. 350 * XXX eventually, we should probably read the register and check 351 * XXX which type it is. Either that or 'quirk' certain devices. 352 */ 353 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 354 sc->sc_dma_ok = (pci_mapreg_map(pa, 355 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0, 356 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 357 sc->sc_dmat = pa->pa_dmat; 358 printf("%s: bus-master DMA support present", 359 sc->sc_wdcdev.sc_dev.dv_xname); 360 if (sc->sc_dma_ok == 0) { 361 printf(", but unused (couldn't map registers)"); 362 } else if (sc->sc_pp == 0) { 363 printf(", but unused (no driver support)"); 364 } else { 365 sc->sc_wdcdev.dma_arg = sc; 366 sc->sc_wdcdev.dma_init = pciide_dma_init; 367 sc->sc_wdcdev.dma_start = pciide_dma_start; 368 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 369 } 370 printf("\n"); 371 } 372 if (sc->sc_pp == NULL) 373 default_setup_cap(sc); 374 else 375 sc->sc_pp->setup_cap(sc); 376 sc->sc_wdcdev.channels = sc->wdc_channels; 377 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 378 379 for (i = 0; i < PCIIDE_NUM_CHANNELS; i++) { 380 cp = &sc->pciide_channels[i]; 381 382 sc->wdc_channels[i].channel = i; 383 sc->wdc_channels[i].wdc = &sc->sc_wdcdev; 384 if (i > 0 && (sc->sc_pp->ide_flags & ONE_QUEUE)) { 385 sc->wdc_channels[i].ch_queue = 386 sc->wdc_channels[0].ch_queue; 387 } else { 388 sc->wdc_channels[i].ch_queue = 389 malloc(sizeof(struct channel_queue), M_DEVBUF, 390 M_NOWAIT); 391 } 392 if (sc->wdc_channels[i].ch_queue == NULL) { 393 printf("%s %s channel: " 394 "can't allocate memory for command queue", 395 sc->sc_wdcdev.sc_dev.dv_xname, 396 PCIIDE_CHANNEL_NAME(i)); 397 continue; 398 } 399 printf("%s: %s channel %s to %s mode\n", 400 sc->sc_wdcdev.sc_dev.dv_xname, 401 PCIIDE_CHANNEL_NAME(i), 402 (interface & PCIIDE_INTERFACE_SETTABLE(i)) ? 403 "configured" : "wired", 404 (interface & PCIIDE_INTERFACE_PCI(i)) ? "native-PCI" : 405 "compatibility"); 406 407 if (interface & PCIIDE_INTERFACE_PCI(i)) 408 cp->hw_ok = pciide_map_channel_native(sc, pa, i); 409 else 410 cp->hw_ok = pciide_map_channel_compat(sc, pa, i); 411 if (!cp->hw_ok) 412 continue; 413 /* Now call common attach routine */ 414 wdcattach(&sc->wdc_channels[i]); 415 } 416 if (sc->sc_pp == NULL) 417 default_setup_chip(sc, pc, tag); 418 else 419 sc->sc_pp->setup_chip(sc, pc, tag); 420 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 421 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 422 } 423 424 int 425 pciide_map_channel_compat(sc, pa, chan) 426 struct pciide_softc *sc; 427 struct pci_attach_args *pa; 428 int chan; 429 { 430 struct pciide_channel *cp = &sc->pciide_channels[chan]; 431 struct channel_softc *wdc_cp = &sc->wdc_channels[chan]; 432 const char *probe_fail_reason; 433 int rv = 1; 434 435 cp->compat = 1; 436 437 wdc_cp->cmd_iot = pa->pa_iot; 438 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(chan), 439 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 440 printf("%s: couldn't map %s channel cmd regs\n", 441 sc->sc_wdcdev.sc_dev.dv_xname, 442 PCIIDE_CHANNEL_NAME(chan)); 443 rv = 0; 444 } 445 446 wdc_cp->ctl_iot = pa->pa_iot; 447 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(chan), 448 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 449 printf("%s: couldn't map %s channel ctl regs\n", 450 sc->sc_wdcdev.sc_dev.dv_xname, 451 PCIIDE_CHANNEL_NAME(chan)); 452 rv = 0; 453 } 454 455 /* 456 * If we weren't able to map the device successfully, 457 * we just give up now. Something else has already 458 * occupied those ports, indicating that the device has 459 * (probably) been completely disabled (by some nonstandard 460 * mechanism). 461 * 462 * XXX If we successfully map some ports, but not others, 463 * XXX it might make sense to unmap the ones that we mapped. 464 */ 465 if (rv == 0) 466 goto out; 467 468 /* 469 * If we were able to map the device successfully, try to 470 * make sure that there's a wdc there and that it's 471 * attributable to us. 472 * 473 * If there's not, then we assume that there's the device 474 * has been disabled and that other devices are free to use 475 * its ports. 476 */ 477 probe_fail_reason = pciide_compat_channel_probe(sc, pa, chan); 478 if (probe_fail_reason != NULL) { 479 printf("%s: %s channel ignored (%s)\n", 480 sc->sc_wdcdev.sc_dev.dv_xname, 481 PCIIDE_CHANNEL_NAME(chan), probe_fail_reason); 482 rv = 0; 483 484 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 485 PCIIDE_COMPAT_CMD_SIZE); 486 bus_space_unmap(wdc_cp->ctl_iot, wdc_cp->ctl_ioh, 487 PCIIDE_COMPAT_CTL_SIZE); 488 489 goto out; 490 } 491 492 /* 493 * If we're here, we were able to map the device successfully 494 * and it really looks like there's a controller there. 495 * 496 * Unless those conditions are true, we don't map the 497 * compatibility interrupt. The spec indicates that if a 498 * channel is configured for compatibility mode and the PCI 499 * device's I/O space is enabled, the channel will be enabled. 500 * Hoewver, some devices seem to be able to disable invididual 501 * compatibility channels (via non-standard mechanisms). If 502 * the channel is disabled, the interrupt line can (probably) 503 * be used by other devices (and may be assigned to other 504 * devices by the BIOS). If we mapped the interrupt we might 505 * conflict with another interrupt assignment. 506 */ 507 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 508 pa, chan, pciide_compat_intr, wdc_cp); 509 if (cp->ih == NULL) { 510 printf("%s: no compatibility interrupt for use by %s channel\n", 511 sc->sc_wdcdev.sc_dev.dv_xname, 512 PCIIDE_CHANNEL_NAME(chan)); 513 rv = 0; 514 } 515 516 out: 517 return (rv); 518 } 519 520 const char * 521 pciide_compat_channel_probe(sc, pa, chan) 522 struct pciide_softc *sc; 523 struct pci_attach_args *pa; 524 { 525 pcireg_t csr; 526 const char *failreason = NULL; 527 528 /* 529 * Check to see if something appears to be there. 530 */ 531 if (!wdcprobe(&sc->wdc_channels[chan])) { 532 failreason = "not responding; disabled or no drives?"; 533 goto out; 534 } 535 536 /* 537 * Now, make sure it's actually attributable to this PCI IDE 538 * channel by trying to access the channel again while the 539 * PCI IDE controller's I/O space is disabled. (If the 540 * channel no longer appears to be there, it belongs to 541 * this controller.) YUCK! 542 */ 543 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 544 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 545 csr & ~PCI_COMMAND_IO_ENABLE); 546 if (wdcprobe(&sc->wdc_channels[chan])) 547 failreason = "other hardware responding at addresses"; 548 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 549 550 out: 551 return (failreason); 552 } 553 554 int 555 pciide_map_channel_native(sc, pa, chan) 556 struct pciide_softc *sc; 557 struct pci_attach_args *pa; 558 int chan; 559 { 560 struct pciide_channel *cp = &sc->pciide_channels[chan]; 561 struct channel_softc *wdc_cp = &sc->wdc_channels[chan]; 562 int rv = 1; 563 564 cp->compat = 0; 565 566 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(chan), PCI_MAPREG_TYPE_IO, 567 0, &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, NULL) != 0) { 568 printf("%s: couldn't map %s channel cmd regs\n", 569 sc->sc_wdcdev.sc_dev.dv_xname, 570 PCIIDE_CHANNEL_NAME(chan)); 571 rv = 0; 572 } 573 574 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(chan), PCI_MAPREG_TYPE_IO, 575 0, &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, NULL) != 0) { 576 printf("%s: couldn't map %s channel ctl regs\n", 577 sc->sc_wdcdev.sc_dev.dv_xname, 578 PCIIDE_CHANNEL_NAME(chan)); 579 rv = 0; 580 } 581 582 if ((cp->ih = sc->sc_pci_ih) == NULL) { 583 printf("%s: no native-PCI interrupt for use by %s channel\n", 584 sc->sc_wdcdev.sc_dev.dv_xname, 585 PCIIDE_CHANNEL_NAME(chan)); 586 rv = 0; 587 } 588 589 return (rv); 590 } 591 592 int 593 pciide_compat_intr(arg) 594 void *arg; 595 { 596 struct channel_softc *wdc_cp = arg; 597 598 #ifdef DIAGNOSTIC 599 struct pciide_softc *sc = (struct pciide_softc*)wdc_cp->wdc; 600 struct pciide_channel *cp = &sc->pciide_channels[wdc_cp->channel]; 601 /* should only be called for a compat channel */ 602 if (cp->compat == 0) 603 panic("pciide compat intr called for non-compat chan %p\n", cp); 604 #endif 605 return (wdcintr(wdc_cp)); 606 } 607 608 int 609 pciide_pci_intr(arg) 610 void *arg; 611 { 612 struct pciide_softc *sc = arg; 613 struct pciide_channel *cp; 614 struct channel_softc *wdc_cp; 615 int i, rv, crv; 616 617 rv = 0; 618 for (i = 0; i < PCIIDE_NUM_CHANNELS; i++) { 619 cp = &sc->pciide_channels[i]; 620 wdc_cp = &sc->wdc_channels[i]; 621 622 /* If a compat channel skip. */ 623 if (cp->compat) 624 continue; 625 /* if this channel not waiting for intr, skip */ 626 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 627 continue; 628 629 crv = wdcintr(wdc_cp); 630 if (crv == 0) 631 ; /* leave rv alone */ 632 else if (crv == 1) 633 rv = 1; /* claim the intr */ 634 else if (rv == 0) /* crv should be -1 in this case */ 635 rv = crv; /* if we've done no better, take it */ 636 } 637 return (rv); 638 } 639 640 void 641 default_setup_cap(sc) 642 struct pciide_softc *sc; 643 { 644 if (sc->sc_dma_ok) 645 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 646 sc->sc_wdcdev.pio_mode = 0; 647 sc->sc_wdcdev.dma_mode = 0; 648 } 649 650 void 651 default_setup_chip(sc, pc, tag) 652 struct pciide_softc *sc; 653 pci_chipset_tag_t pc; 654 pcitag_t tag; 655 { 656 int channel, drive, idedma_ctl; 657 struct channel_softc *chp; 658 struct ata_drive_datas *drvp; 659 660 if (sc->sc_dma_ok == 0) 661 return; /* nothing to do */ 662 663 /* Allocate DMA maps */ 664 for (channel = 0; channel < PCIIDE_NUM_CHANNELS; channel++) { 665 idedma_ctl = 0; 666 chp = &sc->wdc_channels[channel]; 667 for (drive = 0; drive < 2; drive++) { 668 drvp = &chp->ch_drive[drive]; 669 /* If no drive, skip */ 670 if ((drvp->drive_flags & DRIVE) == 0) 671 continue; 672 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 673 /* Abort DMA setup */ 674 printf("%s:%d:%d: can't allocate DMA maps, " 675 "using PIO transferts\n", 676 sc->sc_wdcdev.sc_dev.dv_xname, 677 channel, drive); 678 drvp->drive_flags &= ~DRIVE_DMA; 679 } 680 printf("%s:%d:%d: using DMA mode %d\n", 681 sc->sc_wdcdev.sc_dev.dv_xname, 682 channel, drive, 683 drvp->DMA_mode); 684 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 685 } 686 if (idedma_ctl != 0) { 687 /* Add software bits in status register */ 688 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 689 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 690 idedma_ctl); 691 } 692 } 693 694 } 695 696 void 697 piix_setup_cap(sc) 698 struct pciide_softc *sc; 699 { 700 #if 0 701 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371AB_IDE) 702 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 703 #endif 704 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_PIO | 705 WDC_CAPABILITY_DMA; 706 sc->sc_wdcdev.pio_mode = 4; 707 sc->sc_wdcdev.dma_mode = 2; 708 } 709 710 void 711 piix_setup_chip(sc, pc, tag) 712 struct pciide_softc *sc; 713 pci_chipset_tag_t pc; 714 pcitag_t tag; 715 { 716 struct channel_softc *chp; 717 u_int8_t mode[2]; 718 u_int8_t channel, drive; 719 u_int32_t idetim, sidetim, idedma_ctl; 720 struct ata_drive_datas *drvp; 721 722 idetim = sidetim = 0; 723 724 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x, sidetim=0x%x\n", 725 pci_conf_read(pc, tag, PIIX_IDETIM), 726 pci_conf_read(pc, tag, PIIX_SIDETIM)), DEBUG_PROBE); 727 728 for (channel = 0; channel < PCIIDE_NUM_CHANNELS; channel++) { 729 chp = &sc->wdc_channels[channel]; 730 drvp = chp->ch_drive; 731 idedma_ctl = 0; 732 /* Enable IDE registers decode */ 733 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 734 channel); 735 736 /* setup DMA if needed */ 737 for (drive = 0; drive < 2; drive++) { 738 if (drvp[drive].drive_flags & DRIVE_DMA && 739 pciide_dma_table_setup(sc, channel, drive) != 0) { 740 drvp[drive].drive_flags &= ~DRIVE_DMA; 741 } 742 } 743 744 /* 745 * Here we have to mess up with drives mode: PIIX can't have 746 * different timings for master and slave drives. 747 * We need to find the best combination. 748 */ 749 750 /* If both drives supports DMA, takes the lower mode */ 751 if ((drvp[0].drive_flags & DRIVE_DMA) && 752 (drvp[1].drive_flags & DRIVE_DMA)) { 753 mode[0] = mode[1] = 754 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 755 goto ok; 756 } 757 /* 758 * If only one drive supports DMA, use its mode, and 759 * put the other one in PIO mode 0 if mode not compatible 760 */ 761 if (drvp[0].drive_flags & DRIVE_DMA) { 762 mode[0] = drvp[0].DMA_mode; 763 mode[1] = drvp[1].PIO_mode; 764 if (piix_isp_pio[mode[1]] < piix_isp_dma[mode[0]] || 765 piix_rtc_pio[mode[1]] < piix_rtc_dma[mode[0]]) 766 mode[1] = 0; 767 goto ok; 768 } 769 if (drvp[1].drive_flags & DRIVE_DMA) { 770 mode[1] = drvp[1].DMA_mode; 771 mode[0] = drvp[0].PIO_mode; 772 if (piix_isp_pio[mode[0]] < piix_isp_dma[mode[1]] || 773 piix_rtc_pio[mode[0]] < piix_rtc_dma[mode[1]]) 774 mode[0] = 0; 775 goto ok; 776 } 777 /* 778 * If both drives are not DMA, takes the lower mode, unless 779 * one of them is PIO mode 0 780 */ 781 if (drvp[0].PIO_mode == 0) { 782 mode[0] = 0; 783 mode[1] = drvp[1].PIO_mode; 784 } else if (drvp[1].PIO_mode == 0) { 785 mode[1] = 0; 786 mode[0] = drvp[0].PIO_mode; 787 } else { 788 mode[0] = mode[1] = 789 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 790 } 791 ok: /* The modes are setup */ 792 for (drive = 0; drive < 2; drive++) { 793 if (drvp[drive].drive_flags & DRIVE_DMA) { 794 idetim |= piix_setup_idetim_timings( 795 mode[drive], 1, channel); 796 goto end; 797 } 798 } 799 /* If we are there, none of the drives are DMA */ 800 if (mode[0] > 0) 801 idetim |= piix_setup_idetim_timings( 802 mode[0], 0, channel); 803 else 804 idetim |= piix_setup_idetim_timings( 805 mode[1], 0, channel); 806 end: /* 807 * timing mode is now set up in the controller. Enable 808 * it per-drive 809 */ 810 for (drive = 0; drive < 2; drive++) { 811 /* If no drive, skip */ 812 if ((drvp[drive].drive_flags & DRIVE) == 0) 813 continue; 814 if (drvp[drive].drive_flags & DRIVE_DMA) { 815 /* Enable fast timing for mode >= 1 */ 816 if (mode[drive] >= 1) 817 idetim = PIIX_IDETIM_SET(idetim, 818 PIIX_IDETIM_DTE(drive) | 819 PIIX_IDETIM_TIME(drive), channel); 820 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 821 drvp[drive].DMA_mode = mode[drive]; 822 drvp[drive].PIO_mode = 0; 823 printf("%s:%d:%d: using DMA mode %d\n", 824 sc->sc_wdcdev.sc_dev.dv_xname, 825 channel, drive, mode[drive]); 826 } else { 827 if (mode[drive] > 0) 828 idetim |= piix_setup_idetim_drvs( 829 mode[drive], channel, drive); 830 drvp[drive].PIO_mode = mode[drive]; 831 printf("%s:%d:%d: using PIO mode %d\n", 832 sc->sc_wdcdev.sc_dev.dv_xname, 833 channel, drive, mode[drive]); 834 } 835 } 836 if (idedma_ctl != 0) { 837 /* Add software bits in status register */ 838 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 839 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 840 idedma_ctl); 841 } 842 } 843 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x, sidetim=0x%x\n", 844 idetim, sidetim), DEBUG_PROBE); 845 pci_conf_write(pc, tag, PIIX_IDETIM, idetim); 846 pci_conf_write(pc, tag, PIIX_SIDETIM, sidetim); 847 } 848 849 void 850 piix3_4_setup_chip(sc, pc, tag) 851 struct pciide_softc *sc; 852 pci_chipset_tag_t pc; 853 pcitag_t tag; 854 { 855 int channel, drive; 856 struct channel_softc *chp; 857 struct ata_drive_datas *drvp; 858 u_int32_t idetim, sidetim, udmareg, idedma_ctl; 859 860 idetim = sidetim = udmareg = 0; 861 862 WDCDEBUG_PRINT(("piix3_4_setup_chip: old idetim=0x%x, sidetim=0x%x", 863 pci_conf_read(pc, tag, PIIX_IDETIM), 864 pci_conf_read(pc, tag, PIIX_SIDETIM)), DEBUG_PROBE); 865 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 866 WDCDEBUG_PRINT((", udamreg 0x%x", 867 pci_conf_read(pc, tag, PIIX_UDMAREG)), 868 DEBUG_PROBE); 869 } 870 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 871 872 for (channel = 0; channel < PCIIDE_NUM_CHANNELS; channel++) { 873 chp = &sc->wdc_channels[channel]; 874 idedma_ctl = 0; 875 /* Enable IDE registers decode */ 876 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 877 channel); 878 for (drive = 0; drive < 2; drive++) { 879 drvp = &chp->ch_drive[drive]; 880 /* If no drive, skip */ 881 if ((drvp->drive_flags & DRIVE) == 0) 882 continue; 883 /* add timing values, setup DMA if needed */ 884 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 885 (drvp->drive_flags & DRIVE_UDMA) == 0) || 886 sc->sc_dma_ok == 0) 887 goto pio; 888 if (pciide_dma_table_setup(sc, channel, drive) != 0) 889 goto pio; /* Abort DMA setup */ 890 drvp->PIO_mode = 0; /* use compatible timings for PIO */ 891 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 892 (drvp->drive_flags & DRIVE_UDMA)) { 893 /* use Ultra/DMA */ 894 drvp->drive_flags &= ~DRIVE_DMA; 895 udmareg |= PIIX_UDMACTL_DRV_EN( 896 channel, drive); 897 udmareg |= PIIX_UDMATIM_SET( 898 piix4_sct_udma[drvp->UDMA_mode], 899 channel, drive); 900 printf("%s:%d:%d: using Ultra DMA/33 mode %d\n", 901 sc->sc_wdcdev.sc_dev.dv_xname, 902 channel, drive, 903 drvp->UDMA_mode); 904 } else { 905 /* use Multiword DMA */ 906 drvp->drive_flags &= ~DRIVE_UDMA; 907 if (drive == 0) { 908 idetim |= piix_setup_idetim_timings( 909 drvp->DMA_mode, 1, channel); 910 } else { 911 sidetim |= piix_setup_sidetim_timings( 912 drvp->DMA_mode, 1, channel); 913 idetim =PIIX_IDETIM_SET(idetim, 914 PIIX_IDETIM_SITRE, channel); 915 } 916 printf("%s:%d:%d: using DMA mode %d\n", 917 sc->sc_wdcdev.sc_dev.dv_xname, 918 channel, drive, 919 drvp->DMA_mode); 920 } 921 /* enable fast timings only for mode >= 1 */ 922 if (drvp->drive_flags & DRIVE_UDMA || 923 drvp->DMA_mode >= 1) 924 /* Enable DMA only PIO modes may be wrong */ 925 idetim = PIIX_IDETIM_SET(idetim, 926 PIIX_IDETIM_DTE(drive) | 927 PIIX_IDETIM_TIME(drive), 928 channel); 929 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 930 continue; 931 932 pio: /* use PIO mode */ 933 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 934 if (drive == 0) { 935 idetim |= piix_setup_idetim_timings( 936 drvp->PIO_mode, 0, channel); 937 } else { 938 sidetim |= piix_setup_sidetim_timings( 939 drvp->PIO_mode, 0, channel); 940 idetim =PIIX_IDETIM_SET(idetim, 941 PIIX_IDETIM_SITRE, channel); 942 } 943 idetim |= piix_setup_idetim_drvs(drvp->PIO_mode, 944 channel, drive); 945 printf("%s:%d:%d: using PIO mode %d\n", 946 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, 947 drvp->PIO_mode); 948 } 949 if (idedma_ctl != 0) { 950 /* Add software bits in status register */ 951 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 952 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 953 idedma_ctl); 954 } 955 } 956 957 WDCDEBUG_PRINT(("piix3_4_setup_chip: idetim=0x%x, sidetim=0x%x", 958 idetim, sidetim), DEBUG_PROBE); 959 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 960 WDCDEBUG_PRINT((", udmareg=0x%x", udmareg), DEBUG_PROBE); 961 pci_conf_write(pc, tag, PIIX_UDMAREG, udmareg); 962 } 963 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 964 pci_conf_write(pc, tag, PIIX_IDETIM, idetim); 965 pci_conf_write(pc, tag, PIIX_SIDETIM, sidetim); 966 } 967 968 /* setup ISP and RTC fields, based on mode */ 969 static u_int32_t 970 piix_setup_idetim_timings(mode, dma, channel) 971 u_int8_t mode; 972 u_int8_t dma; 973 u_int8_t channel; 974 { 975 976 if (dma) 977 return PIIX_IDETIM_SET(0, 978 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 979 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 980 channel); 981 else 982 return PIIX_IDETIM_SET(0, 983 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 984 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 985 channel); 986 } 987 988 /* setup PPE, IE and TIME field based on PIO mode */ 989 static u_int32_t 990 piix_setup_idetim_drvs(mode, channel, drive) 991 u_int8_t mode; 992 u_int8_t channel; 993 u_int8_t drive; 994 { 995 u_int32_t ret = 0; 996 997 /* if mode <= 1, use compatible timings only */ 998 if (mode <= 1) 999 return 0; 1000 1001 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1002 /* I didn't read anything about this, it's just a guess */ 1003 if (mode >= 3) 1004 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1005 if (mode >= 2) 1006 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1007 return ret; 1008 } 1009 1010 /* setup values in SIDETIM registers, based on mode */ 1011 static u_int32_t 1012 piix_setup_sidetim_timings(mode, dma, channel) 1013 u_int8_t mode; 1014 u_int8_t dma; 1015 u_int8_t channel; 1016 { 1017 if (dma) 1018 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1019 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1020 else 1021 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1022 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1023 } 1024 1025 1026 1027 int 1028 pciide_dma_table_setup(sc, channel, drive) 1029 struct pciide_softc *sc; 1030 int channel, drive; 1031 { 1032 bus_dma_segment_t seg; 1033 int error, rseg; 1034 const bus_size_t dma_table_size = 1035 sizeof(struct idedma_table) * NIDEDMA_TABLES; 1036 struct pciide_dma_maps *dma_maps = 1037 &sc->pciide_channels[channel].dma_maps[drive]; 1038 1039 /* Allocate memory for the DMA tables and map it */ 1040 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 1041 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 1042 BUS_DMA_NOWAIT)) != 0) { 1043 printf("%s:%d: unable to allocate table DMA for" 1044 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1045 channel, drive, error); 1046 return error; 1047 } 1048 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 1049 dma_table_size, 1050 (caddr_t *)&dma_maps->dma_table, 1051 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 1052 printf("%s:%d: unable to map table DMA for" 1053 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1054 channel, drive, error); 1055 return error; 1056 } 1057 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 1058 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 1059 seg.ds_addr), DEBUG_PROBE); 1060 1061 /* Create and load table DMA map for this disk */ 1062 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 1063 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 1064 &dma_maps->dmamap_table)) != 0) { 1065 printf("%s:%d: unable to create table DMA map for" 1066 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1067 channel, drive, error); 1068 return error; 1069 } 1070 if ((error = bus_dmamap_load(sc->sc_dmat, 1071 dma_maps->dmamap_table, 1072 dma_maps->dma_table, 1073 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 1074 printf("%s:%d: unable to load table DMA map for" 1075 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1076 channel, drive, error); 1077 return error; 1078 } 1079 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 1080 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 1081 /* Create a xfer DMA map for this drive */ 1082 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 1083 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 1084 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 1085 &dma_maps->dmamap_xfer)) != 0) { 1086 printf("%s:%d: unable to create xfer DMA map for" 1087 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1088 channel, drive, error); 1089 return error; 1090 } 1091 return 0; 1092 } 1093 1094 int 1095 pciide_dma_init(v, channel, drive, databuf, datalen, read) 1096 void *v; 1097 int channel, drive; 1098 void *databuf; 1099 size_t datalen; 1100 int read; 1101 { 1102 struct pciide_softc *sc = v; 1103 int error, seg; 1104 struct pciide_dma_maps *dma_maps = 1105 &sc->pciide_channels[channel].dma_maps[drive]; 1106 1107 error = bus_dmamap_load(sc->sc_dmat, 1108 dma_maps->dmamap_xfer, 1109 databuf, datalen, NULL, BUS_DMA_NOWAIT); 1110 if (error) { 1111 printf("%s:%d: unable to load xfer DMA map for" 1112 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 1113 channel, drive, error); 1114 return error; 1115 } 1116 1117 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1118 dma_maps->dmamap_xfer->dm_mapsize, 1119 (read) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1120 1121 WDCDEBUG_PRINT(("pciide_dma_init: %d segs for %p len %d (phy 0x%x)\n", 1122 dma_maps->dmamap_xfer->dm_nsegs, databuf, datalen, 1123 vtophys(databuf)), DEBUG_DMA|DEBUG_XFERS); 1124 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 1125 #ifdef DIAGNOSTIC 1126 /* A segment must not cross a 64k boundary */ 1127 { 1128 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1129 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 1130 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 1131 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 1132 printf("pciide_dma: segment %d physical addr 0x%lx" 1133 " len 0x%lx not properly aligned\n", 1134 seg, phys, len); 1135 panic("pciide_dma: buf align"); 1136 } 1137 } 1138 #endif 1139 dma_maps->dma_table[seg].base_addr = 1140 dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 1141 dma_maps->dma_table[seg].byte_count = 1142 dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 1143 IDEDMA_BYTE_COUNT_MASK; 1144 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 1145 seg, dma_maps->dma_table[seg].byte_count, 1146 dma_maps->dma_table[seg].base_addr), DEBUG_DMA); 1147 1148 } 1149 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 1150 IDEDMA_BYTE_COUNT_EOT; 1151 1152 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1153 dma_maps->dmamap_table->dm_mapsize, 1154 BUS_DMASYNC_PREWRITE); 1155 1156 /* Maps are ready. Start DMA function */ 1157 #ifdef DIAGNOSTIC 1158 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1159 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1160 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1161 panic("pciide_dma_init: table align"); 1162 } 1163 #endif 1164 1165 WDCDEBUG_PRINT(("phy addr of table at %p = 0x%lx len %ld (%d segs, " 1166 "phys 0x%x)\n", 1167 dma_maps->dma_table, 1168 dma_maps->dmamap_table->dm_segs[0].ds_addr, 1169 dma_maps->dmamap_table->dm_segs[0].ds_len, 1170 dma_maps->dmamap_table->dm_nsegs, 1171 vtophys(dma_maps->dma_table)), DEBUG_DMA); 1172 /* Clear status bits */ 1173 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1174 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1175 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1176 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1177 /* Write table addr */ 1178 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1179 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1180 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1181 /* set read/write */ 1182 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1183 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1184 (read) ? IDEDMA_CMD_WRITE: 0); 1185 return 0; 1186 } 1187 1188 void 1189 pciide_dma_start(v, channel, drive, read) 1190 void *v; 1191 int channel, drive; 1192 { 1193 struct pciide_softc *sc = v; 1194 1195 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1196 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1197 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1198 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1199 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1200 } 1201 1202 int 1203 pciide_dma_finish(v, channel, drive, read) 1204 void *v; 1205 int channel, drive; 1206 int read; 1207 { 1208 struct pciide_softc *sc = v; 1209 u_int8_t status; 1210 struct pciide_dma_maps *dma_maps = 1211 &sc->pciide_channels[channel].dma_maps[drive]; 1212 1213 /* Unload the map of the data buffer */ 1214 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1215 dma_maps->dmamap_xfer->dm_mapsize, 1216 (read) ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1217 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1218 1219 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1220 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1221 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1222 DEBUG_XFERS); 1223 1224 /* stop DMA channel */ 1225 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1226 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1227 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1228 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1229 1230 /* Clear status bits */ 1231 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1232 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1233 status); 1234 1235 if ((status & (IDEDMA_CTL_INTR | IDEDMA_CTL_ERR | IDEDMA_CTL_ACT)) != 1236 IDEDMA_CTL_INTR) { 1237 printf("%s:%d:%d: Bus-Master DMA error: status=0x%x\n", 1238 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1239 return 1; 1240 } 1241 return 0; 1242 } 1243
Indexes created Thu Oct 02 10:09:58 GMT 2025