pciide.c revision 1.64
1 /* $NetBSD: pciide.c,v 1.64 2000/06/06 22:56:06 thorpej Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <vm/vm.h> 102 #include <vm/vm_param.h> 103 #include <vm/vm_kern.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 120 #include <dev/pci/cy82c693var.h> 121 122 /* inlines for reading/writing 8-bit PCI registers */ 123 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 124 int)); 125 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 126 int, u_int8_t)); 127 128 static __inline u_int8_t 129 pciide_pci_read(pc, pa, reg) 130 pci_chipset_tag_t pc; 131 pcitag_t pa; 132 int reg; 133 { 134 135 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 136 ((reg & 0x03) * 8) & 0xff); 137 } 138 139 static __inline void 140 pciide_pci_write(pc, pa, reg, val) 141 pci_chipset_tag_t pc; 142 pcitag_t pa; 143 int reg; 144 u_int8_t val; 145 { 146 pcireg_t pcival; 147 148 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 149 pcival &= ~(0xff << ((reg & 0x03) * 8)); 150 pcival |= (val << ((reg & 0x03) * 8)); 151 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 152 } 153 154 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 155 156 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 157 void piix_setup_channel __P((struct channel_softc*)); 158 void piix3_4_setup_channel __P((struct channel_softc*)); 159 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 160 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 161 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 162 163 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 164 void amd756_setup_channel __P((struct channel_softc*)); 165 166 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 167 void apollo_setup_channel __P((struct channel_softc*)); 168 169 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 170 void cmd0643_6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void cmd0643_6_setup_channel __P((struct channel_softc*)); 172 void cmd_channel_map __P((struct pci_attach_args *, 173 struct pciide_softc *, int)); 174 int cmd_pci_intr __P((void *)); 175 176 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 177 void cy693_setup_channel __P((struct channel_softc*)); 178 179 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 180 void sis_setup_channel __P((struct channel_softc*)); 181 182 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 183 void acer_setup_channel __P((struct channel_softc*)); 184 int acer_pci_intr __P((void *)); 185 186 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 187 void pdc202xx_setup_channel __P((struct channel_softc*)); 188 int pdc202xx_pci_intr __P((void *)); 189 190 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 191 void opti_setup_channel __P((struct channel_softc*)); 192 193 void pciide_channel_dma_setup __P((struct pciide_channel *)); 194 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 195 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 196 void pciide_dma_start __P((void*, int, int)); 197 int pciide_dma_finish __P((void*, int, int, int)); 198 void pciide_print_modes __P((struct pciide_channel *)); 199 200 struct pciide_product_desc { 201 u_int32_t ide_product; 202 int ide_flags; 203 const char *ide_name; 204 /* map and setup chip, probe drives */ 205 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 206 }; 207 208 /* Flags for ide_flags */ 209 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 210 211 /* Default product description for devices not known from this controller */ 212 const struct pciide_product_desc default_product_desc = { 213 0, 214 0, 215 "Generic PCI IDE controller", 216 default_chip_map, 217 }; 218 219 const struct pciide_product_desc pciide_intel_products[] = { 220 { PCI_PRODUCT_INTEL_82092AA, 221 0, 222 "Intel 82092AA IDE controller", 223 default_chip_map, 224 }, 225 { PCI_PRODUCT_INTEL_82371FB_IDE, 226 0, 227 "Intel 82371FB IDE controller (PIIX)", 228 piix_chip_map, 229 }, 230 { PCI_PRODUCT_INTEL_82371SB_IDE, 231 0, 232 "Intel 82371SB IDE Interface (PIIX3)", 233 piix_chip_map, 234 }, 235 { PCI_PRODUCT_INTEL_82371AB_IDE, 236 0, 237 "Intel 82371AB IDE controller (PIIX4)", 238 piix_chip_map, 239 }, 240 { PCI_PRODUCT_INTEL_82801AA_IDE, 241 0, 242 "Intel 82801AA IDE Controller (ICH)", 243 piix_chip_map, 244 }, 245 { PCI_PRODUCT_INTEL_82801AB_IDE, 246 0, 247 "Intel 82801AB IDE Controller (ICH0)", 248 piix_chip_map, 249 }, 250 { 0, 251 0, 252 NULL, 253 } 254 }; 255 256 const struct pciide_product_desc pciide_amd_products[] = { 257 { PCI_PRODUCT_AMD_PBC756_IDE, 258 0, 259 "Advanced Micro Devices AMD756 IDE Controller", 260 amd756_chip_map 261 }, 262 { 0, 263 0, 264 NULL, 265 } 266 }; 267 268 const struct pciide_product_desc pciide_cmd_products[] = { 269 { PCI_PRODUCT_CMDTECH_640, 270 0, 271 "CMD Technology PCI0640", 272 cmd_chip_map 273 }, 274 { PCI_PRODUCT_CMDTECH_643, 275 0, 276 "CMD Technology PCI0643", 277 cmd0643_6_chip_map, 278 }, 279 { PCI_PRODUCT_CMDTECH_646, 280 0, 281 "CMD Technology PCI0646", 282 cmd0643_6_chip_map, 283 }, 284 { 0, 285 0, 286 NULL, 287 } 288 }; 289 290 const struct pciide_product_desc pciide_via_products[] = { 291 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 292 0, 293 "VIA Tech VT82C586 IDE Controller", 294 apollo_chip_map, 295 }, 296 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 297 0, 298 "VIA Tech VT82C586A IDE Controller", 299 apollo_chip_map, 300 }, 301 { 0, 302 0, 303 NULL, 304 } 305 }; 306 307 const struct pciide_product_desc pciide_cypress_products[] = { 308 { PCI_PRODUCT_CONTAQ_82C693, 309 0, 310 "Cypress 82C693 IDE Controller", 311 cy693_chip_map, 312 }, 313 { 0, 314 0, 315 NULL, 316 } 317 }; 318 319 const struct pciide_product_desc pciide_sis_products[] = { 320 { PCI_PRODUCT_SIS_5597_IDE, 321 0, 322 "Silicon Integrated System 5597/5598 IDE controller", 323 sis_chip_map, 324 }, 325 { 0, 326 0, 327 NULL, 328 } 329 }; 330 331 const struct pciide_product_desc pciide_acer_products[] = { 332 { PCI_PRODUCT_ALI_M5229, 333 0, 334 "Acer Labs M5229 UDMA IDE Controller", 335 acer_chip_map, 336 }, 337 { 0, 338 0, 339 NULL, 340 } 341 }; 342 343 const struct pciide_product_desc pciide_promise_products[] = { 344 { PCI_PRODUCT_PROMISE_ULTRA33, 345 IDE_PCI_CLASS_OVERRIDE, 346 "Promise Ultra33/ATA Bus Master IDE Accelerator", 347 pdc202xx_chip_map, 348 }, 349 { PCI_PRODUCT_PROMISE_ULTRA66, 350 IDE_PCI_CLASS_OVERRIDE, 351 "Promise Ultra66/ATA Bus Master IDE Accelerator", 352 pdc202xx_chip_map, 353 }, 354 { 0, 355 0, 356 NULL, 357 } 358 }; 359 360 const struct pciide_product_desc pciide_opti_products[] = { 361 { PCI_PRODUCT_OPTI_82C621, 362 0, 363 "OPTi 82c621 PCI IDE controller", 364 opti_chip_map, 365 }, 366 { PCI_PRODUCT_OPTI_82C568, 367 0, 368 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 369 opti_chip_map, 370 }, 371 { PCI_PRODUCT_OPTI_82D568, 372 0, 373 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 374 opti_chip_map, 375 }, 376 { 0, 377 0, 378 NULL, 379 } 380 }; 381 382 struct pciide_vendor_desc { 383 u_int32_t ide_vendor; 384 const struct pciide_product_desc *ide_products; 385 }; 386 387 const struct pciide_vendor_desc pciide_vendors[] = { 388 { PCI_VENDOR_INTEL, pciide_intel_products }, 389 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 390 { PCI_VENDOR_VIATECH, pciide_via_products }, 391 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 392 { PCI_VENDOR_SIS, pciide_sis_products }, 393 { PCI_VENDOR_ALI, pciide_acer_products }, 394 { PCI_VENDOR_PROMISE, pciide_promise_products }, 395 { PCI_VENDOR_AMD, pciide_amd_products }, 396 { PCI_VENDOR_OPTI, pciide_opti_products }, 397 { 0, NULL } 398 }; 399 400 /* options passed via the 'flags' config keyword */ 401 #define PCIIDE_OPTIONS_DMA 0x01 402 403 int pciide_match __P((struct device *, struct cfdata *, void *)); 404 void pciide_attach __P((struct device *, struct device *, void *)); 405 406 struct cfattach pciide_ca = { 407 sizeof(struct pciide_softc), pciide_match, pciide_attach 408 }; 409 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 410 int pciide_mapregs_compat __P(( struct pci_attach_args *, 411 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 412 int pciide_mapregs_native __P((struct pci_attach_args *, 413 struct pciide_channel *, bus_size_t *, bus_size_t *, 414 int (*pci_intr) __P((void *)))); 415 void pciide_mapreg_dma __P((struct pciide_softc *, 416 struct pci_attach_args *)); 417 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 418 void pciide_mapchan __P((struct pci_attach_args *, 419 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 420 int (*pci_intr) __P((void *)))); 421 int pciide_chan_candisable __P((struct pciide_channel *)); 422 void pciide_map_compat_intr __P(( struct pci_attach_args *, 423 struct pciide_channel *, int, int)); 424 int pciide_print __P((void *, const char *pnp)); 425 int pciide_compat_intr __P((void *)); 426 int pciide_pci_intr __P((void *)); 427 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 428 429 const struct pciide_product_desc * 430 pciide_lookup_product(id) 431 u_int32_t id; 432 { 433 const struct pciide_product_desc *pp; 434 const struct pciide_vendor_desc *vp; 435 436 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 437 if (PCI_VENDOR(id) == vp->ide_vendor) 438 break; 439 440 if ((pp = vp->ide_products) == NULL) 441 return NULL; 442 443 for (; pp->ide_name != NULL; pp++) 444 if (PCI_PRODUCT(id) == pp->ide_product) 445 break; 446 447 if (pp->ide_name == NULL) 448 return NULL; 449 return pp; 450 } 451 452 int 453 pciide_match(parent, match, aux) 454 struct device *parent; 455 struct cfdata *match; 456 void *aux; 457 { 458 struct pci_attach_args *pa = aux; 459 const struct pciide_product_desc *pp; 460 461 /* 462 * Check the ID register to see that it's a PCI IDE controller. 463 * If it is, we assume that we can deal with it; it _should_ 464 * work in a standardized way... 465 */ 466 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 467 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 468 return (1); 469 } 470 471 /* 472 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 473 * controllers. Let see if we can deal with it anyway. 474 */ 475 pp = pciide_lookup_product(pa->pa_id); 476 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 477 return (1); 478 } 479 480 return (0); 481 } 482 483 void 484 pciide_attach(parent, self, aux) 485 struct device *parent, *self; 486 void *aux; 487 { 488 struct pci_attach_args *pa = aux; 489 pci_chipset_tag_t pc = pa->pa_pc; 490 pcitag_t tag = pa->pa_tag; 491 struct pciide_softc *sc = (struct pciide_softc *)self; 492 pcireg_t csr; 493 char devinfo[256]; 494 const char *displaydev; 495 496 sc->sc_pp = pciide_lookup_product(pa->pa_id); 497 if (sc->sc_pp == NULL) { 498 sc->sc_pp = &default_product_desc; 499 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 500 displaydev = devinfo; 501 } else 502 displaydev = sc->sc_pp->ide_name; 503 504 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 505 506 sc->sc_pc = pa->pa_pc; 507 sc->sc_tag = pa->pa_tag; 508 #ifdef WDCDEBUG 509 if (wdcdebug_pciide_mask & DEBUG_PROBE) 510 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 511 #endif 512 513 sc->sc_pp->chip_map(sc, pa); 514 515 if (sc->sc_dma_ok) { 516 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 517 csr |= PCI_COMMAND_MASTER_ENABLE; 518 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 519 } 520 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 521 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 522 } 523 524 /* tell wether the chip is enabled or not */ 525 int 526 pciide_chipen(sc, pa) 527 struct pciide_softc *sc; 528 struct pci_attach_args *pa; 529 { 530 pcireg_t csr; 531 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 532 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 533 PCI_COMMAND_STATUS_REG); 534 printf("%s: device disabled (at %s)\n", 535 sc->sc_wdcdev.sc_dev.dv_xname, 536 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 537 "device" : "bridge"); 538 return 0; 539 } 540 return 1; 541 } 542 543 int 544 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 545 struct pci_attach_args *pa; 546 struct pciide_channel *cp; 547 int compatchan; 548 bus_size_t *cmdsizep, *ctlsizep; 549 { 550 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 551 struct channel_softc *wdc_cp = &cp->wdc_channel; 552 553 cp->compat = 1; 554 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 555 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 556 557 wdc_cp->cmd_iot = pa->pa_iot; 558 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 559 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 560 printf("%s: couldn't map %s channel cmd regs\n", 561 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 562 return (0); 563 } 564 565 wdc_cp->ctl_iot = pa->pa_iot; 566 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 567 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 568 printf("%s: couldn't map %s channel ctl regs\n", 569 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 570 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 571 PCIIDE_COMPAT_CMD_SIZE); 572 return (0); 573 } 574 575 return (1); 576 } 577 578 int 579 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 580 struct pci_attach_args * pa; 581 struct pciide_channel *cp; 582 bus_size_t *cmdsizep, *ctlsizep; 583 int (*pci_intr) __P((void *)); 584 { 585 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 586 struct channel_softc *wdc_cp = &cp->wdc_channel; 587 const char *intrstr; 588 pci_intr_handle_t intrhandle; 589 590 cp->compat = 0; 591 592 if (sc->sc_pci_ih == NULL) { 593 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 594 pa->pa_intrline, &intrhandle) != 0) { 595 printf("%s: couldn't map native-PCI interrupt\n", 596 sc->sc_wdcdev.sc_dev.dv_xname); 597 return 0; 598 } 599 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 600 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 601 intrhandle, IPL_BIO, pci_intr, sc); 602 if (sc->sc_pci_ih != NULL) { 603 printf("%s: using %s for native-PCI interrupt\n", 604 sc->sc_wdcdev.sc_dev.dv_xname, 605 intrstr ? intrstr : "unknown interrupt"); 606 } else { 607 printf("%s: couldn't establish native-PCI interrupt", 608 sc->sc_wdcdev.sc_dev.dv_xname); 609 if (intrstr != NULL) 610 printf(" at %s", intrstr); 611 printf("\n"); 612 return 0; 613 } 614 } 615 cp->ih = sc->sc_pci_ih; 616 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 617 PCI_MAPREG_TYPE_IO, 0, 618 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 619 printf("%s: couldn't map %s channel cmd regs\n", 620 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 621 return 0; 622 } 623 624 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 625 PCI_MAPREG_TYPE_IO, 0, 626 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 627 printf("%s: couldn't map %s channel ctl regs\n", 628 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 629 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 630 return 0; 631 } 632 return (1); 633 } 634 635 void 636 pciide_mapreg_dma(sc, pa) 637 struct pciide_softc *sc; 638 struct pci_attach_args *pa; 639 { 640 pcireg_t maptype; 641 642 /* 643 * Map DMA registers 644 * 645 * Note that sc_dma_ok is the right variable to test to see if 646 * DMA can be done. If the interface doesn't support DMA, 647 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 648 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 649 * non-zero if the interface supports DMA and the registers 650 * could be mapped. 651 * 652 * XXX Note that despite the fact that the Bus Master IDE specs 653 * XXX say that "The bus master IDE function uses 16 bytes of IO 654 * XXX space," some controllers (at least the United 655 * XXX Microelectronics UM8886BF) place it in memory space. 656 */ 657 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 658 PCIIDE_REG_BUS_MASTER_DMA); 659 660 switch (maptype) { 661 case PCI_MAPREG_TYPE_IO: 662 case PCI_MAPREG_MEM_TYPE_32BIT: 663 sc->sc_dma_ok = (pci_mapreg_map(pa, 664 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 665 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 666 sc->sc_dmat = pa->pa_dmat; 667 if (sc->sc_dma_ok == 0) { 668 printf(", but unused (couldn't map registers)"); 669 } else { 670 sc->sc_wdcdev.dma_arg = sc; 671 sc->sc_wdcdev.dma_init = pciide_dma_init; 672 sc->sc_wdcdev.dma_start = pciide_dma_start; 673 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 674 } 675 676 default: 677 sc->sc_dma_ok = 0; 678 printf(", but unsupported register maptype (0x%x)", maptype); 679 } 680 } 681 682 int 683 pciide_compat_intr(arg) 684 void *arg; 685 { 686 struct pciide_channel *cp = arg; 687 688 #ifdef DIAGNOSTIC 689 /* should only be called for a compat channel */ 690 if (cp->compat == 0) 691 panic("pciide compat intr called for non-compat chan %p\n", cp); 692 #endif 693 return (wdcintr(&cp->wdc_channel)); 694 } 695 696 int 697 pciide_pci_intr(arg) 698 void *arg; 699 { 700 struct pciide_softc *sc = arg; 701 struct pciide_channel *cp; 702 struct channel_softc *wdc_cp; 703 int i, rv, crv; 704 705 rv = 0; 706 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 707 cp = &sc->pciide_channels[i]; 708 wdc_cp = &cp->wdc_channel; 709 710 /* If a compat channel skip. */ 711 if (cp->compat) 712 continue; 713 /* if this channel not waiting for intr, skip */ 714 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 715 continue; 716 717 crv = wdcintr(wdc_cp); 718 if (crv == 0) 719 ; /* leave rv alone */ 720 else if (crv == 1) 721 rv = 1; /* claim the intr */ 722 else if (rv == 0) /* crv should be -1 in this case */ 723 rv = crv; /* if we've done no better, take it */ 724 } 725 return (rv); 726 } 727 728 void 729 pciide_channel_dma_setup(cp) 730 struct pciide_channel *cp; 731 { 732 int drive; 733 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 734 struct ata_drive_datas *drvp; 735 736 for (drive = 0; drive < 2; drive++) { 737 drvp = &cp->wdc_channel.ch_drive[drive]; 738 /* If no drive, skip */ 739 if ((drvp->drive_flags & DRIVE) == 0) 740 continue; 741 /* setup DMA if needed */ 742 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 743 (drvp->drive_flags & DRIVE_UDMA) == 0) || 744 sc->sc_dma_ok == 0) { 745 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 746 continue; 747 } 748 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 749 != 0) { 750 /* Abort DMA setup */ 751 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 752 continue; 753 } 754 } 755 } 756 757 int 758 pciide_dma_table_setup(sc, channel, drive) 759 struct pciide_softc *sc; 760 int channel, drive; 761 { 762 bus_dma_segment_t seg; 763 int error, rseg; 764 const bus_size_t dma_table_size = 765 sizeof(struct idedma_table) * NIDEDMA_TABLES; 766 struct pciide_dma_maps *dma_maps = 767 &sc->pciide_channels[channel].dma_maps[drive]; 768 769 /* If table was already allocated, just return */ 770 if (dma_maps->dma_table) 771 return 0; 772 773 /* Allocate memory for the DMA tables and map it */ 774 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 775 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 776 BUS_DMA_NOWAIT)) != 0) { 777 printf("%s:%d: unable to allocate table DMA for " 778 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 779 channel, drive, error); 780 return error; 781 } 782 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 783 dma_table_size, 784 (caddr_t *)&dma_maps->dma_table, 785 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 786 printf("%s:%d: unable to map table DMA for" 787 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 788 channel, drive, error); 789 return error; 790 } 791 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 792 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 793 seg.ds_addr), DEBUG_PROBE); 794 795 /* Create and load table DMA map for this disk */ 796 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 797 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 798 &dma_maps->dmamap_table)) != 0) { 799 printf("%s:%d: unable to create table DMA map for " 800 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 801 channel, drive, error); 802 return error; 803 } 804 if ((error = bus_dmamap_load(sc->sc_dmat, 805 dma_maps->dmamap_table, 806 dma_maps->dma_table, 807 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 808 printf("%s:%d: unable to load table DMA map for " 809 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 810 channel, drive, error); 811 return error; 812 } 813 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 814 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 815 /* Create a xfer DMA map for this drive */ 816 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 817 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 818 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 819 &dma_maps->dmamap_xfer)) != 0) { 820 printf("%s:%d: unable to create xfer DMA map for " 821 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 822 channel, drive, error); 823 return error; 824 } 825 return 0; 826 } 827 828 int 829 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 830 void *v; 831 int channel, drive; 832 void *databuf; 833 size_t datalen; 834 int flags; 835 { 836 struct pciide_softc *sc = v; 837 int error, seg; 838 struct pciide_dma_maps *dma_maps = 839 &sc->pciide_channels[channel].dma_maps[drive]; 840 841 error = bus_dmamap_load(sc->sc_dmat, 842 dma_maps->dmamap_xfer, 843 databuf, datalen, NULL, BUS_DMA_NOWAIT); 844 if (error) { 845 printf("%s:%d: unable to load xfer DMA map for" 846 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 847 channel, drive, error); 848 return error; 849 } 850 851 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 852 dma_maps->dmamap_xfer->dm_mapsize, 853 (flags & WDC_DMA_READ) ? 854 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 855 856 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 857 #ifdef DIAGNOSTIC 858 /* A segment must not cross a 64k boundary */ 859 { 860 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 861 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 862 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 863 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 864 printf("pciide_dma: segment %d physical addr 0x%lx" 865 " len 0x%lx not properly aligned\n", 866 seg, phys, len); 867 panic("pciide_dma: buf align"); 868 } 869 } 870 #endif 871 dma_maps->dma_table[seg].base_addr = 872 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 873 dma_maps->dma_table[seg].byte_count = 874 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 875 IDEDMA_BYTE_COUNT_MASK); 876 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 877 seg, le32toh(dma_maps->dma_table[seg].byte_count), 878 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 879 880 } 881 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 882 htole32(IDEDMA_BYTE_COUNT_EOT); 883 884 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 885 dma_maps->dmamap_table->dm_mapsize, 886 BUS_DMASYNC_PREWRITE); 887 888 /* Maps are ready. Start DMA function */ 889 #ifdef DIAGNOSTIC 890 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 891 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 892 dma_maps->dmamap_table->dm_segs[0].ds_addr); 893 panic("pciide_dma_init: table align"); 894 } 895 #endif 896 897 /* Clear status bits */ 898 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 899 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 900 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 901 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 902 /* Write table addr */ 903 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 904 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 905 dma_maps->dmamap_table->dm_segs[0].ds_addr); 906 /* set read/write */ 907 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 908 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 909 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 910 /* remember flags */ 911 dma_maps->dma_flags = flags; 912 return 0; 913 } 914 915 void 916 pciide_dma_start(v, channel, drive) 917 void *v; 918 int channel, drive; 919 { 920 struct pciide_softc *sc = v; 921 922 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 923 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 924 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 925 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 926 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 927 } 928 929 int 930 pciide_dma_finish(v, channel, drive, force) 931 void *v; 932 int channel, drive; 933 int force; 934 { 935 struct pciide_softc *sc = v; 936 u_int8_t status; 937 int error = 0; 938 struct pciide_dma_maps *dma_maps = 939 &sc->pciide_channels[channel].dma_maps[drive]; 940 941 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 942 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 943 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 944 DEBUG_XFERS); 945 946 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 947 return WDC_DMAST_NOIRQ; 948 949 /* stop DMA channel */ 950 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 951 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 952 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 953 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 954 955 /* Clear status bits */ 956 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 957 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 958 status); 959 960 /* Unload the map of the data buffer */ 961 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 962 dma_maps->dmamap_xfer->dm_mapsize, 963 (dma_maps->dma_flags & WDC_DMA_READ) ? 964 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 965 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 966 967 if ((status & IDEDMA_CTL_ERR) != 0) { 968 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 969 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 970 error |= WDC_DMAST_ERR; 971 } 972 973 if ((status & IDEDMA_CTL_INTR) == 0) { 974 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 975 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 976 drive, status); 977 error |= WDC_DMAST_NOIRQ; 978 } 979 980 if ((status & IDEDMA_CTL_ACT) != 0) { 981 /* data underrun, may be a valid condition for ATAPI */ 982 error |= WDC_DMAST_UNDER; 983 } 984 return error; 985 } 986 987 /* some common code used by several chip_map */ 988 int 989 pciide_chansetup(sc, channel, interface) 990 struct pciide_softc *sc; 991 int channel; 992 pcireg_t interface; 993 { 994 struct pciide_channel *cp = &sc->pciide_channels[channel]; 995 sc->wdc_chanarray[channel] = &cp->wdc_channel; 996 cp->name = PCIIDE_CHANNEL_NAME(channel); 997 cp->wdc_channel.channel = channel; 998 cp->wdc_channel.wdc = &sc->sc_wdcdev; 999 cp->wdc_channel.ch_queue = 1000 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1001 if (cp->wdc_channel.ch_queue == NULL) { 1002 printf("%s %s channel: " 1003 "can't allocate memory for command queue", 1004 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1005 return 0; 1006 } 1007 printf("%s: %s channel %s to %s mode\n", 1008 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1009 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1010 "configured" : "wired", 1011 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1012 "native-PCI" : "compatibility"); 1013 return 1; 1014 } 1015 1016 /* some common code used by several chip channel_map */ 1017 void 1018 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1019 struct pci_attach_args *pa; 1020 struct pciide_channel *cp; 1021 pcireg_t interface; 1022 bus_size_t *cmdsizep, *ctlsizep; 1023 int (*pci_intr) __P((void *)); 1024 { 1025 struct channel_softc *wdc_cp = &cp->wdc_channel; 1026 1027 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1028 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1029 pci_intr); 1030 else 1031 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1032 wdc_cp->channel, cmdsizep, ctlsizep); 1033 1034 if (cp->hw_ok == 0) 1035 return; 1036 wdc_cp->data32iot = wdc_cp->cmd_iot; 1037 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1038 wdcattach(wdc_cp); 1039 } 1040 1041 /* 1042 * Generic code to call to know if a channel can be disabled. Return 1 1043 * if channel can be disabled, 0 if not 1044 */ 1045 int 1046 pciide_chan_candisable(cp) 1047 struct pciide_channel *cp; 1048 { 1049 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1050 struct channel_softc *wdc_cp = &cp->wdc_channel; 1051 1052 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1053 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1054 printf("%s: disabling %s channel (no drives)\n", 1055 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1056 cp->hw_ok = 0; 1057 return 1; 1058 } 1059 return 0; 1060 } 1061 1062 /* 1063 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1064 * Set hw_ok=0 on failure 1065 */ 1066 void 1067 pciide_map_compat_intr(pa, cp, compatchan, interface) 1068 struct pci_attach_args *pa; 1069 struct pciide_channel *cp; 1070 int compatchan, interface; 1071 { 1072 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1073 struct channel_softc *wdc_cp = &cp->wdc_channel; 1074 1075 if (cp->hw_ok == 0) 1076 return; 1077 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1078 return; 1079 1080 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1081 pa, compatchan, pciide_compat_intr, cp); 1082 if (cp->ih == NULL) { 1083 printf("%s: no compatibility interrupt for use by %s " 1084 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1085 cp->hw_ok = 0; 1086 } 1087 } 1088 1089 void 1090 pciide_print_modes(cp) 1091 struct pciide_channel *cp; 1092 { 1093 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1094 int drive; 1095 struct channel_softc *chp; 1096 struct ata_drive_datas *drvp; 1097 1098 chp = &cp->wdc_channel; 1099 for (drive = 0; drive < 2; drive++) { 1100 drvp = &chp->ch_drive[drive]; 1101 if ((drvp->drive_flags & DRIVE) == 0) 1102 continue; 1103 printf("%s(%s:%d:%d): using PIO mode %d", 1104 drvp->drv_softc->dv_xname, 1105 sc->sc_wdcdev.sc_dev.dv_xname, 1106 chp->channel, drive, drvp->PIO_mode); 1107 if (drvp->drive_flags & DRIVE_DMA) 1108 printf(", DMA mode %d", drvp->DMA_mode); 1109 if (drvp->drive_flags & DRIVE_UDMA) 1110 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1111 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1112 printf(" (using DMA data transfers)"); 1113 printf("\n"); 1114 } 1115 } 1116 1117 void 1118 default_chip_map(sc, pa) 1119 struct pciide_softc *sc; 1120 struct pci_attach_args *pa; 1121 { 1122 struct pciide_channel *cp; 1123 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1124 sc->sc_tag, PCI_CLASS_REG)); 1125 pcireg_t csr; 1126 int channel, drive; 1127 struct ata_drive_datas *drvp; 1128 u_int8_t idedma_ctl; 1129 bus_size_t cmdsize, ctlsize; 1130 char *failreason; 1131 1132 if (pciide_chipen(sc, pa) == 0) 1133 return; 1134 1135 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1136 printf("%s: bus-master DMA support present", 1137 sc->sc_wdcdev.sc_dev.dv_xname); 1138 if (sc->sc_pp == &default_product_desc && 1139 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1140 PCIIDE_OPTIONS_DMA) == 0) { 1141 printf(", but unused (no driver support)"); 1142 sc->sc_dma_ok = 0; 1143 } else { 1144 pciide_mapreg_dma(sc, pa); 1145 if (sc->sc_dma_ok != 0) 1146 printf(", used without full driver " 1147 "support"); 1148 } 1149 } else { 1150 printf("%s: hardware does not support DMA", 1151 sc->sc_wdcdev.sc_dev.dv_xname); 1152 sc->sc_dma_ok = 0; 1153 } 1154 printf("\n"); 1155 if (sc->sc_dma_ok) 1156 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1157 sc->sc_wdcdev.PIO_cap = 0; 1158 sc->sc_wdcdev.DMA_cap = 0; 1159 1160 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1161 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1162 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1163 1164 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1165 cp = &sc->pciide_channels[channel]; 1166 if (pciide_chansetup(sc, channel, interface) == 0) 1167 continue; 1168 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1169 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1170 &ctlsize, pciide_pci_intr); 1171 } else { 1172 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1173 channel, &cmdsize, &ctlsize); 1174 } 1175 if (cp->hw_ok == 0) 1176 continue; 1177 /* 1178 * Check to see if something appears to be there. 1179 */ 1180 failreason = NULL; 1181 if (!wdcprobe(&cp->wdc_channel)) { 1182 failreason = "not responding; disabled or no drives?"; 1183 goto next; 1184 } 1185 /* 1186 * Now, make sure it's actually attributable to this PCI IDE 1187 * channel by trying to access the channel again while the 1188 * PCI IDE controller's I/O space is disabled. (If the 1189 * channel no longer appears to be there, it belongs to 1190 * this controller.) YUCK! 1191 */ 1192 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1193 PCI_COMMAND_STATUS_REG); 1194 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1195 csr & ~PCI_COMMAND_IO_ENABLE); 1196 if (wdcprobe(&cp->wdc_channel)) 1197 failreason = "other hardware responding at addresses"; 1198 pci_conf_write(sc->sc_pc, sc->sc_tag, 1199 PCI_COMMAND_STATUS_REG, csr); 1200 next: 1201 if (failreason) { 1202 printf("%s: %s channel ignored (%s)\n", 1203 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1204 failreason); 1205 cp->hw_ok = 0; 1206 bus_space_unmap(cp->wdc_channel.cmd_iot, 1207 cp->wdc_channel.cmd_ioh, cmdsize); 1208 bus_space_unmap(cp->wdc_channel.ctl_iot, 1209 cp->wdc_channel.ctl_ioh, ctlsize); 1210 } else { 1211 pciide_map_compat_intr(pa, cp, channel, interface); 1212 } 1213 if (cp->hw_ok) { 1214 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1215 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1216 wdcattach(&cp->wdc_channel); 1217 } 1218 } 1219 1220 if (sc->sc_dma_ok == 0) 1221 return; 1222 1223 /* Allocate DMA maps */ 1224 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1225 idedma_ctl = 0; 1226 cp = &sc->pciide_channels[channel]; 1227 for (drive = 0; drive < 2; drive++) { 1228 drvp = &cp->wdc_channel.ch_drive[drive]; 1229 /* If no drive, skip */ 1230 if ((drvp->drive_flags & DRIVE) == 0) 1231 continue; 1232 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1233 continue; 1234 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1235 /* Abort DMA setup */ 1236 printf("%s:%d:%d: can't allocate DMA maps, " 1237 "using PIO transfers\n", 1238 sc->sc_wdcdev.sc_dev.dv_xname, 1239 channel, drive); 1240 drvp->drive_flags &= ~DRIVE_DMA; 1241 } 1242 printf("%s:%d:%d: using DMA data transfers\n", 1243 sc->sc_wdcdev.sc_dev.dv_xname, 1244 channel, drive); 1245 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1246 } 1247 if (idedma_ctl != 0) { 1248 /* Add software bits in status register */ 1249 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1250 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1251 idedma_ctl); 1252 } 1253 } 1254 } 1255 1256 void 1257 piix_chip_map(sc, pa) 1258 struct pciide_softc *sc; 1259 struct pci_attach_args *pa; 1260 { 1261 struct pciide_channel *cp; 1262 int channel; 1263 u_int32_t idetim; 1264 bus_size_t cmdsize, ctlsize; 1265 1266 if (pciide_chipen(sc, pa) == 0) 1267 return; 1268 1269 printf("%s: bus-master DMA support present", 1270 sc->sc_wdcdev.sc_dev.dv_xname); 1271 pciide_mapreg_dma(sc, pa); 1272 printf("\n"); 1273 if (sc->sc_dma_ok) { 1274 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1275 switch(sc->sc_pp->ide_product) { 1276 case PCI_PRODUCT_INTEL_82371AB_IDE: 1277 case PCI_PRODUCT_INTEL_82801AA_IDE: 1278 case PCI_PRODUCT_INTEL_82801AB_IDE: 1279 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1280 } 1281 } 1282 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1283 WDC_CAPABILITY_MODE; 1284 sc->sc_wdcdev.PIO_cap = 4; 1285 sc->sc_wdcdev.DMA_cap = 2; 1286 sc->sc_wdcdev.UDMA_cap = 1287 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1288 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1289 sc->sc_wdcdev.set_modes = piix_setup_channel; 1290 else 1291 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1292 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1293 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1294 1295 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1296 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1297 DEBUG_PROBE); 1298 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1299 WDCDEBUG_PRINT((", sidetim=0x%x", 1300 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1301 DEBUG_PROBE); 1302 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1303 WDCDEBUG_PRINT((", udamreg 0x%x", 1304 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1305 DEBUG_PROBE); 1306 } 1307 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1308 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1309 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1310 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1311 DEBUG_PROBE); 1312 } 1313 1314 } 1315 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1316 1317 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1318 cp = &sc->pciide_channels[channel]; 1319 /* PIIX is compat-only */ 1320 if (pciide_chansetup(sc, channel, 0) == 0) 1321 continue; 1322 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1323 if ((PIIX_IDETIM_READ(idetim, channel) & 1324 PIIX_IDETIM_IDE) == 0) { 1325 printf("%s: %s channel ignored (disabled)\n", 1326 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1327 continue; 1328 } 1329 /* PIIX are compat-only pciide devices */ 1330 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1331 if (cp->hw_ok == 0) 1332 continue; 1333 if (pciide_chan_candisable(cp)) { 1334 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1335 channel); 1336 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1337 idetim); 1338 } 1339 pciide_map_compat_intr(pa, cp, channel, 0); 1340 if (cp->hw_ok == 0) 1341 continue; 1342 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1343 } 1344 1345 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1346 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1347 DEBUG_PROBE); 1348 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1349 WDCDEBUG_PRINT((", sidetim=0x%x", 1350 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1351 DEBUG_PROBE); 1352 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1353 WDCDEBUG_PRINT((", udamreg 0x%x", 1354 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1355 DEBUG_PROBE); 1356 } 1357 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1358 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1359 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1360 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1361 DEBUG_PROBE); 1362 } 1363 } 1364 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1365 } 1366 1367 void 1368 piix_setup_channel(chp) 1369 struct channel_softc *chp; 1370 { 1371 u_int8_t mode[2], drive; 1372 u_int32_t oidetim, idetim, idedma_ctl; 1373 struct pciide_channel *cp = (struct pciide_channel*)chp; 1374 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1375 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1376 1377 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1378 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1379 idedma_ctl = 0; 1380 1381 /* set up new idetim: Enable IDE registers decode */ 1382 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1383 chp->channel); 1384 1385 /* setup DMA */ 1386 pciide_channel_dma_setup(cp); 1387 1388 /* 1389 * Here we have to mess up with drives mode: PIIX can't have 1390 * different timings for master and slave drives. 1391 * We need to find the best combination. 1392 */ 1393 1394 /* If both drives supports DMA, take the lower mode */ 1395 if ((drvp[0].drive_flags & DRIVE_DMA) && 1396 (drvp[1].drive_flags & DRIVE_DMA)) { 1397 mode[0] = mode[1] = 1398 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1399 drvp[0].DMA_mode = mode[0]; 1400 drvp[1].DMA_mode = mode[1]; 1401 goto ok; 1402 } 1403 /* 1404 * If only one drive supports DMA, use its mode, and 1405 * put the other one in PIO mode 0 if mode not compatible 1406 */ 1407 if (drvp[0].drive_flags & DRIVE_DMA) { 1408 mode[0] = drvp[0].DMA_mode; 1409 mode[1] = drvp[1].PIO_mode; 1410 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1411 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1412 mode[1] = drvp[1].PIO_mode = 0; 1413 goto ok; 1414 } 1415 if (drvp[1].drive_flags & DRIVE_DMA) { 1416 mode[1] = drvp[1].DMA_mode; 1417 mode[0] = drvp[0].PIO_mode; 1418 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1419 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1420 mode[0] = drvp[0].PIO_mode = 0; 1421 goto ok; 1422 } 1423 /* 1424 * If both drives are not DMA, takes the lower mode, unless 1425 * one of them is PIO mode < 2 1426 */ 1427 if (drvp[0].PIO_mode < 2) { 1428 mode[0] = drvp[0].PIO_mode = 0; 1429 mode[1] = drvp[1].PIO_mode; 1430 } else if (drvp[1].PIO_mode < 2) { 1431 mode[1] = drvp[1].PIO_mode = 0; 1432 mode[0] = drvp[0].PIO_mode; 1433 } else { 1434 mode[0] = mode[1] = 1435 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1436 drvp[0].PIO_mode = mode[0]; 1437 drvp[1].PIO_mode = mode[1]; 1438 } 1439 ok: /* The modes are setup */ 1440 for (drive = 0; drive < 2; drive++) { 1441 if (drvp[drive].drive_flags & DRIVE_DMA) { 1442 idetim |= piix_setup_idetim_timings( 1443 mode[drive], 1, chp->channel); 1444 goto end; 1445 } 1446 } 1447 /* If we are there, none of the drives are DMA */ 1448 if (mode[0] >= 2) 1449 idetim |= piix_setup_idetim_timings( 1450 mode[0], 0, chp->channel); 1451 else 1452 idetim |= piix_setup_idetim_timings( 1453 mode[1], 0, chp->channel); 1454 end: /* 1455 * timing mode is now set up in the controller. Enable 1456 * it per-drive 1457 */ 1458 for (drive = 0; drive < 2; drive++) { 1459 /* If no drive, skip */ 1460 if ((drvp[drive].drive_flags & DRIVE) == 0) 1461 continue; 1462 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1463 if (drvp[drive].drive_flags & DRIVE_DMA) 1464 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1465 } 1466 if (idedma_ctl != 0) { 1467 /* Add software bits in status register */ 1468 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1469 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1470 idedma_ctl); 1471 } 1472 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1473 pciide_print_modes(cp); 1474 } 1475 1476 void 1477 piix3_4_setup_channel(chp) 1478 struct channel_softc *chp; 1479 { 1480 struct ata_drive_datas *drvp; 1481 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1482 struct pciide_channel *cp = (struct pciide_channel*)chp; 1483 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1484 int drive; 1485 int channel = chp->channel; 1486 1487 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1488 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1489 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1490 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1491 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1492 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1493 PIIX_SIDETIM_RTC_MASK(channel)); 1494 1495 idedma_ctl = 0; 1496 /* If channel disabled, no need to go further */ 1497 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1498 return; 1499 /* set up new idetim: Enable IDE registers decode */ 1500 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1501 1502 /* setup DMA if needed */ 1503 pciide_channel_dma_setup(cp); 1504 1505 for (drive = 0; drive < 2; drive++) { 1506 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1507 PIIX_UDMATIM_SET(0x3, channel, drive)); 1508 drvp = &chp->ch_drive[drive]; 1509 /* If no drive, skip */ 1510 if ((drvp->drive_flags & DRIVE) == 0) 1511 continue; 1512 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1513 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1514 goto pio; 1515 1516 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1517 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1518 ideconf |= PIIX_CONFIG_PINGPONG; 1519 } 1520 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1521 /* setup Ultra/66 */ 1522 if (drvp->UDMA_mode > 2 && 1523 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1524 drvp->UDMA_mode = 2; 1525 if (drvp->UDMA_mode > 2) 1526 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1527 else 1528 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1529 } 1530 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1531 (drvp->drive_flags & DRIVE_UDMA)) { 1532 /* use Ultra/DMA */ 1533 drvp->drive_flags &= ~DRIVE_DMA; 1534 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1535 udmareg |= PIIX_UDMATIM_SET( 1536 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1537 } else { 1538 /* use Multiword DMA */ 1539 drvp->drive_flags &= ~DRIVE_UDMA; 1540 if (drive == 0) { 1541 idetim |= piix_setup_idetim_timings( 1542 drvp->DMA_mode, 1, channel); 1543 } else { 1544 sidetim |= piix_setup_sidetim_timings( 1545 drvp->DMA_mode, 1, channel); 1546 idetim =PIIX_IDETIM_SET(idetim, 1547 PIIX_IDETIM_SITRE, channel); 1548 } 1549 } 1550 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1551 1552 pio: /* use PIO mode */ 1553 idetim |= piix_setup_idetim_drvs(drvp); 1554 if (drive == 0) { 1555 idetim |= piix_setup_idetim_timings( 1556 drvp->PIO_mode, 0, channel); 1557 } else { 1558 sidetim |= piix_setup_sidetim_timings( 1559 drvp->PIO_mode, 0, channel); 1560 idetim =PIIX_IDETIM_SET(idetim, 1561 PIIX_IDETIM_SITRE, channel); 1562 } 1563 } 1564 if (idedma_ctl != 0) { 1565 /* Add software bits in status register */ 1566 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1567 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1568 idedma_ctl); 1569 } 1570 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1571 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1572 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1573 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1574 pciide_print_modes(cp); 1575 } 1576 1577 1578 /* setup ISP and RTC fields, based on mode */ 1579 static u_int32_t 1580 piix_setup_idetim_timings(mode, dma, channel) 1581 u_int8_t mode; 1582 u_int8_t dma; 1583 u_int8_t channel; 1584 { 1585 1586 if (dma) 1587 return PIIX_IDETIM_SET(0, 1588 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1589 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1590 channel); 1591 else 1592 return PIIX_IDETIM_SET(0, 1593 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1594 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1595 channel); 1596 } 1597 1598 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1599 static u_int32_t 1600 piix_setup_idetim_drvs(drvp) 1601 struct ata_drive_datas *drvp; 1602 { 1603 u_int32_t ret = 0; 1604 struct channel_softc *chp = drvp->chnl_softc; 1605 u_int8_t channel = chp->channel; 1606 u_int8_t drive = drvp->drive; 1607 1608 /* 1609 * If drive is using UDMA, timings setups are independant 1610 * So just check DMA and PIO here. 1611 */ 1612 if (drvp->drive_flags & DRIVE_DMA) { 1613 /* if mode = DMA mode 0, use compatible timings */ 1614 if ((drvp->drive_flags & DRIVE_DMA) && 1615 drvp->DMA_mode == 0) { 1616 drvp->PIO_mode = 0; 1617 return ret; 1618 } 1619 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1620 /* 1621 * PIO and DMA timings are the same, use fast timings for PIO 1622 * too, else use compat timings. 1623 */ 1624 if ((piix_isp_pio[drvp->PIO_mode] != 1625 piix_isp_dma[drvp->DMA_mode]) || 1626 (piix_rtc_pio[drvp->PIO_mode] != 1627 piix_rtc_dma[drvp->DMA_mode])) 1628 drvp->PIO_mode = 0; 1629 /* if PIO mode <= 2, use compat timings for PIO */ 1630 if (drvp->PIO_mode <= 2) { 1631 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1632 channel); 1633 return ret; 1634 } 1635 } 1636 1637 /* 1638 * Now setup PIO modes. If mode < 2, use compat timings. 1639 * Else enable fast timings. Enable IORDY and prefetch/post 1640 * if PIO mode >= 3. 1641 */ 1642 1643 if (drvp->PIO_mode < 2) 1644 return ret; 1645 1646 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1647 if (drvp->PIO_mode >= 3) { 1648 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1649 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1650 } 1651 return ret; 1652 } 1653 1654 /* setup values in SIDETIM registers, based on mode */ 1655 static u_int32_t 1656 piix_setup_sidetim_timings(mode, dma, channel) 1657 u_int8_t mode; 1658 u_int8_t dma; 1659 u_int8_t channel; 1660 { 1661 if (dma) 1662 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1663 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1664 else 1665 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1666 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1667 } 1668 1669 void 1670 amd756_chip_map(sc, pa) 1671 struct pciide_softc *sc; 1672 struct pci_attach_args *pa; 1673 { 1674 struct pciide_channel *cp; 1675 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1676 sc->sc_tag, PCI_CLASS_REG)); 1677 int channel; 1678 pcireg_t chanenable; 1679 bus_size_t cmdsize, ctlsize; 1680 1681 if (pciide_chipen(sc, pa) == 0) 1682 return; 1683 printf("%s: bus-master DMA support present", 1684 sc->sc_wdcdev.sc_dev.dv_xname); 1685 pciide_mapreg_dma(sc, pa); 1686 printf("\n"); 1687 if (sc->sc_dma_ok) 1688 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1689 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1690 WDC_CAPABILITY_MODE; 1691 sc->sc_wdcdev.PIO_cap = 4; 1692 sc->sc_wdcdev.DMA_cap = 2; 1693 sc->sc_wdcdev.UDMA_cap = 4; 1694 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1695 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1696 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1697 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1698 1699 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1700 DEBUG_PROBE); 1701 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1702 cp = &sc->pciide_channels[channel]; 1703 if (pciide_chansetup(sc, channel, interface) == 0) 1704 continue; 1705 1706 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1707 printf("%s: %s channel ignored (disabled)\n", 1708 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1709 continue; 1710 } 1711 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1712 pciide_pci_intr); 1713 1714 if (pciide_chan_candisable(cp)) 1715 chanenable &= ~AMD756_CHAN_EN(channel); 1716 pciide_map_compat_intr(pa, cp, channel, interface); 1717 if (cp->hw_ok == 0) 1718 continue; 1719 1720 amd756_setup_channel(&cp->wdc_channel); 1721 } 1722 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1723 chanenable); 1724 return; 1725 } 1726 1727 void 1728 amd756_setup_channel(chp) 1729 struct channel_softc *chp; 1730 { 1731 u_int32_t udmatim_reg, datatim_reg; 1732 u_int8_t idedma_ctl; 1733 int mode, drive; 1734 struct ata_drive_datas *drvp; 1735 struct pciide_channel *cp = (struct pciide_channel*)chp; 1736 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1737 1738 idedma_ctl = 0; 1739 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1740 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1741 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1742 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1743 1744 /* setup DMA if needed */ 1745 pciide_channel_dma_setup(cp); 1746 1747 for (drive = 0; drive < 2; drive++) { 1748 drvp = &chp->ch_drive[drive]; 1749 /* If no drive, skip */ 1750 if ((drvp->drive_flags & DRIVE) == 0) 1751 continue; 1752 /* add timing values, setup DMA if needed */ 1753 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1754 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1755 mode = drvp->PIO_mode; 1756 goto pio; 1757 } 1758 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1759 (drvp->drive_flags & DRIVE_UDMA)) { 1760 /* use Ultra/DMA */ 1761 drvp->drive_flags &= ~DRIVE_DMA; 1762 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1763 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1764 AMD756_UDMA_TIME(chp->channel, drive, 1765 amd756_udma_tim[drvp->UDMA_mode]); 1766 /* can use PIO timings, MW DMA unused */ 1767 mode = drvp->PIO_mode; 1768 } else { 1769 /* use Multiword DMA */ 1770 drvp->drive_flags &= ~DRIVE_UDMA; 1771 /* mode = min(pio, dma+2) */ 1772 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1773 mode = drvp->PIO_mode; 1774 else 1775 mode = drvp->DMA_mode + 2; 1776 } 1777 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1778 1779 pio: /* setup PIO mode */ 1780 if (mode <= 2) { 1781 drvp->DMA_mode = 0; 1782 drvp->PIO_mode = 0; 1783 mode = 0; 1784 } else { 1785 drvp->PIO_mode = mode; 1786 drvp->DMA_mode = mode - 2; 1787 } 1788 datatim_reg |= 1789 AMD756_DATATIM_PULSE(chp->channel, drive, 1790 amd756_pio_set[mode]) | 1791 AMD756_DATATIM_RECOV(chp->channel, drive, 1792 amd756_pio_rec[mode]); 1793 } 1794 if (idedma_ctl != 0) { 1795 /* Add software bits in status register */ 1796 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1797 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1798 idedma_ctl); 1799 } 1800 pciide_print_modes(cp); 1801 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1802 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1803 } 1804 1805 void 1806 apollo_chip_map(sc, pa) 1807 struct pciide_softc *sc; 1808 struct pci_attach_args *pa; 1809 { 1810 struct pciide_channel *cp; 1811 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 1812 sc->sc_tag, PCI_CLASS_REG)); 1813 int channel; 1814 u_int32_t ideconf; 1815 bus_size_t cmdsize, ctlsize; 1816 1817 if (pciide_chipen(sc, pa) == 0) 1818 return; 1819 printf("%s: bus-master DMA support present", 1820 sc->sc_wdcdev.sc_dev.dv_xname); 1821 pciide_mapreg_dma(sc, pa); 1822 printf("\n"); 1823 if (sc->sc_dma_ok) { 1824 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 1825 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1826 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1827 } 1828 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_MODE; 1829 sc->sc_wdcdev.PIO_cap = 4; 1830 sc->sc_wdcdev.DMA_cap = 2; 1831 sc->sc_wdcdev.UDMA_cap = 2; 1832 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1833 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1834 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1835 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1836 1837 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1838 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1839 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1840 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1841 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1842 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1843 DEBUG_PROBE); 1844 1845 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1846 cp = &sc->pciide_channels[channel]; 1847 if (pciide_chansetup(sc, channel, interface) == 0) 1848 continue; 1849 1850 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1851 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1852 printf("%s: %s channel ignored (disabled)\n", 1853 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1854 continue; 1855 } 1856 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1857 pciide_pci_intr); 1858 if (cp->hw_ok == 0) 1859 continue; 1860 if (pciide_chan_candisable(cp)) { 1861 ideconf &= ~APO_IDECONF_EN(channel); 1862 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1863 ideconf); 1864 } 1865 pciide_map_compat_intr(pa, cp, channel, interface); 1866 1867 if (cp->hw_ok == 0) 1868 continue; 1869 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1870 } 1871 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1872 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1873 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1874 } 1875 1876 void 1877 apollo_setup_channel(chp) 1878 struct channel_softc *chp; 1879 { 1880 u_int32_t udmatim_reg, datatim_reg; 1881 u_int8_t idedma_ctl; 1882 int mode, drive; 1883 struct ata_drive_datas *drvp; 1884 struct pciide_channel *cp = (struct pciide_channel*)chp; 1885 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1886 1887 idedma_ctl = 0; 1888 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1889 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1890 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1891 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1892 1893 /* setup DMA if needed */ 1894 pciide_channel_dma_setup(cp); 1895 1896 for (drive = 0; drive < 2; drive++) { 1897 drvp = &chp->ch_drive[drive]; 1898 /* If no drive, skip */ 1899 if ((drvp->drive_flags & DRIVE) == 0) 1900 continue; 1901 /* add timing values, setup DMA if needed */ 1902 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1903 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1904 mode = drvp->PIO_mode; 1905 goto pio; 1906 } 1907 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1908 (drvp->drive_flags & DRIVE_UDMA)) { 1909 /* use Ultra/DMA */ 1910 drvp->drive_flags &= ~DRIVE_DMA; 1911 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1912 APO_UDMA_EN_MTH(chp->channel, drive) | 1913 APO_UDMA_TIME(chp->channel, drive, 1914 apollo_udma_tim[drvp->UDMA_mode]); 1915 /* can use PIO timings, MW DMA unused */ 1916 mode = drvp->PIO_mode; 1917 } else { 1918 /* use Multiword DMA */ 1919 drvp->drive_flags &= ~DRIVE_UDMA; 1920 /* mode = min(pio, dma+2) */ 1921 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1922 mode = drvp->PIO_mode; 1923 else 1924 mode = drvp->DMA_mode + 2; 1925 } 1926 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1927 1928 pio: /* setup PIO mode */ 1929 if (mode <= 2) { 1930 drvp->DMA_mode = 0; 1931 drvp->PIO_mode = 0; 1932 mode = 0; 1933 } else { 1934 drvp->PIO_mode = mode; 1935 drvp->DMA_mode = mode - 2; 1936 } 1937 datatim_reg |= 1938 APO_DATATIM_PULSE(chp->channel, drive, 1939 apollo_pio_set[mode]) | 1940 APO_DATATIM_RECOV(chp->channel, drive, 1941 apollo_pio_rec[mode]); 1942 } 1943 if (idedma_ctl != 0) { 1944 /* Add software bits in status register */ 1945 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1946 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1947 idedma_ctl); 1948 } 1949 pciide_print_modes(cp); 1950 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 1951 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 1952 } 1953 1954 void 1955 cmd_channel_map(pa, sc, channel) 1956 struct pci_attach_args *pa; 1957 struct pciide_softc *sc; 1958 int channel; 1959 { 1960 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1961 bus_size_t cmdsize, ctlsize; 1962 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 1963 int interface = 1964 PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1965 1966 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1967 cp->name = PCIIDE_CHANNEL_NAME(channel); 1968 cp->wdc_channel.channel = channel; 1969 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1970 1971 if (channel > 0) { 1972 cp->wdc_channel.ch_queue = 1973 sc->pciide_channels[0].wdc_channel.ch_queue; 1974 } else { 1975 cp->wdc_channel.ch_queue = 1976 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1977 } 1978 if (cp->wdc_channel.ch_queue == NULL) { 1979 printf("%s %s channel: " 1980 "can't allocate memory for command queue", 1981 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1982 return; 1983 } 1984 1985 printf("%s: %s channel %s to %s mode\n", 1986 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1987 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1988 "configured" : "wired", 1989 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1990 "native-PCI" : "compatibility"); 1991 1992 /* 1993 * with a CMD PCI64x, if we get here, the first channel is enabled: 1994 * there's no way to disable the first channel without disabling 1995 * the whole device 1996 */ 1997 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 1998 printf("%s: %s channel ignored (disabled)\n", 1999 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2000 return; 2001 } 2002 2003 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2004 if (cp->hw_ok == 0) 2005 return; 2006 if (channel == 1) { 2007 if (pciide_chan_candisable(cp)) { 2008 ctrl &= ~CMD_CTRL_2PORT; 2009 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2010 CMD_CTRL, ctrl); 2011 } 2012 } 2013 pciide_map_compat_intr(pa, cp, channel, interface); 2014 } 2015 2016 int 2017 cmd_pci_intr(arg) 2018 void *arg; 2019 { 2020 struct pciide_softc *sc = arg; 2021 struct pciide_channel *cp; 2022 struct channel_softc *wdc_cp; 2023 int i, rv, crv; 2024 u_int32_t priirq, secirq; 2025 2026 rv = 0; 2027 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2028 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2029 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2030 cp = &sc->pciide_channels[i]; 2031 wdc_cp = &cp->wdc_channel; 2032 /* If a compat channel skip. */ 2033 if (cp->compat) 2034 continue; 2035 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2036 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2037 crv = wdcintr(wdc_cp); 2038 if (crv == 0) 2039 printf("%s:%d: bogus intr\n", 2040 sc->sc_wdcdev.sc_dev.dv_xname, i); 2041 else 2042 rv = 1; 2043 } 2044 } 2045 return rv; 2046 } 2047 2048 void 2049 cmd_chip_map(sc, pa) 2050 struct pciide_softc *sc; 2051 struct pci_attach_args *pa; 2052 { 2053 int channel; 2054 2055 /* 2056 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2057 * and base adresses registers can be disabled at 2058 * hardware level. In this case, the device is wired 2059 * in compat mode and its first channel is always enabled, 2060 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2061 * In fact, it seems that the first channel of the CMD PCI0640 2062 * can't be disabled. 2063 */ 2064 2065 #ifdef PCIIDE_CMD064x_DISABLE 2066 if (pciide_chipen(sc, pa) == 0) 2067 return; 2068 #endif 2069 2070 printf("%s: hardware does not support DMA\n", 2071 sc->sc_wdcdev.sc_dev.dv_xname); 2072 sc->sc_dma_ok = 0; 2073 2074 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2075 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2076 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 2077 2078 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2079 cmd_channel_map(pa, sc, channel); 2080 } 2081 } 2082 2083 void 2084 cmd0643_6_chip_map(sc, pa) 2085 struct pciide_softc *sc; 2086 struct pci_attach_args *pa; 2087 { 2088 struct pciide_channel *cp; 2089 int channel; 2090 2091 /* 2092 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2093 * and base adresses registers can be disabled at 2094 * hardware level. In this case, the device is wired 2095 * in compat mode and its first channel is always enabled, 2096 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2097 * In fact, it seems that the first channel of the CMD PCI0640 2098 * can't be disabled. 2099 */ 2100 2101 #ifdef PCIIDE_CMD064x_DISABLE 2102 if (pciide_chipen(sc, pa) == 0) 2103 return; 2104 #endif 2105 printf("%s: bus-master DMA support present", 2106 sc->sc_wdcdev.sc_dev.dv_xname); 2107 pciide_mapreg_dma(sc, pa); 2108 printf("\n"); 2109 if (sc->sc_dma_ok) 2110 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2111 2112 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2113 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2114 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2115 WDC_CAPABILITY_MODE; 2116 sc->sc_wdcdev.PIO_cap = 4; 2117 sc->sc_wdcdev.DMA_cap = 2; 2118 sc->sc_wdcdev.set_modes = cmd0643_6_setup_channel; 2119 2120 WDCDEBUG_PRINT(("cmd0643_6_chip_map: old timings reg 0x%x 0x%x\n", 2121 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2122 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2123 DEBUG_PROBE); 2124 2125 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2126 cp = &sc->pciide_channels[channel]; 2127 cmd_channel_map(pa, sc, channel); 2128 if (cp->hw_ok == 0) 2129 continue; 2130 cmd0643_6_setup_channel(&cp->wdc_channel); 2131 } 2132 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2133 WDCDEBUG_PRINT(("cmd0643_6_chip_map: timings reg now 0x%x 0x%x\n", 2134 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2135 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2136 DEBUG_PROBE); 2137 } 2138 2139 void 2140 cmd0643_6_setup_channel(chp) 2141 struct channel_softc *chp; 2142 { 2143 struct ata_drive_datas *drvp; 2144 u_int8_t tim; 2145 u_int32_t idedma_ctl; 2146 int drive; 2147 struct pciide_channel *cp = (struct pciide_channel*)chp; 2148 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2149 2150 idedma_ctl = 0; 2151 /* setup DMA if needed */ 2152 pciide_channel_dma_setup(cp); 2153 2154 for (drive = 0; drive < 2; drive++) { 2155 drvp = &chp->ch_drive[drive]; 2156 /* If no drive, skip */ 2157 if ((drvp->drive_flags & DRIVE) == 0) 2158 continue; 2159 /* add timing values, setup DMA if needed */ 2160 tim = cmd0643_6_data_tim_pio[drvp->PIO_mode]; 2161 if (drvp->drive_flags & DRIVE_DMA) { 2162 /* 2163 * use Multiword DMA. 2164 * Timings will be used for both PIO and DMA, so adjust 2165 * DMA mode if needed 2166 */ 2167 if (drvp->PIO_mode >= 3 && 2168 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2169 drvp->DMA_mode = drvp->PIO_mode - 2; 2170 } 2171 tim = cmd0643_6_data_tim_dma[drvp->DMA_mode]; 2172 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2173 } 2174 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2175 CMD_DATA_TIM(chp->channel, drive), tim); 2176 } 2177 if (idedma_ctl != 0) { 2178 /* Add software bits in status register */ 2179 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2180 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2181 idedma_ctl); 2182 } 2183 pciide_print_modes(cp); 2184 } 2185 2186 void 2187 cy693_chip_map(sc, pa) 2188 struct pciide_softc *sc; 2189 struct pci_attach_args *pa; 2190 { 2191 struct pciide_channel *cp; 2192 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2193 sc->sc_tag, PCI_CLASS_REG)); 2194 bus_size_t cmdsize, ctlsize; 2195 2196 if (pciide_chipen(sc, pa) == 0) 2197 return; 2198 /* 2199 * this chip has 2 PCI IDE functions, one for primary and one for 2200 * secondary. So we need to call pciide_mapregs_compat() with 2201 * the real channel 2202 */ 2203 if (pa->pa_function == 1) { 2204 sc->sc_cy_compatchan = 0; 2205 } else if (pa->pa_function == 2) { 2206 sc->sc_cy_compatchan = 1; 2207 } else { 2208 printf("%s: unexpected PCI function %d\n", 2209 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2210 return; 2211 } 2212 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2213 printf("%s: bus-master DMA support present", 2214 sc->sc_wdcdev.sc_dev.dv_xname); 2215 pciide_mapreg_dma(sc, pa); 2216 } else { 2217 printf("%s: hardware does not support DMA", 2218 sc->sc_wdcdev.sc_dev.dv_xname); 2219 sc->sc_dma_ok = 0; 2220 } 2221 printf("\n"); 2222 2223 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2224 if (sc->sc_cy_handle == NULL) { 2225 printf("%s: unable to map hyperCache control registers\n", 2226 sc->sc_wdcdev.sc_dev.dv_xname); 2227 sc->sc_dma_ok = 0; 2228 } 2229 2230 if (sc->sc_dma_ok) 2231 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2232 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2233 WDC_CAPABILITY_MODE; 2234 sc->sc_wdcdev.PIO_cap = 4; 2235 sc->sc_wdcdev.DMA_cap = 2; 2236 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2237 2238 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2239 sc->sc_wdcdev.nchannels = 1; 2240 2241 /* Only one channel for this chip; if we are here it's enabled */ 2242 cp = &sc->pciide_channels[0]; 2243 sc->wdc_chanarray[0] = &cp->wdc_channel; 2244 cp->name = PCIIDE_CHANNEL_NAME(0); 2245 cp->wdc_channel.channel = 0; 2246 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2247 cp->wdc_channel.ch_queue = 2248 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2249 if (cp->wdc_channel.ch_queue == NULL) { 2250 printf("%s primary channel: " 2251 "can't allocate memory for command queue", 2252 sc->sc_wdcdev.sc_dev.dv_xname); 2253 return; 2254 } 2255 printf("%s: primary channel %s to ", 2256 sc->sc_wdcdev.sc_dev.dv_xname, 2257 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2258 "configured" : "wired"); 2259 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2260 printf("native-PCI"); 2261 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2262 pciide_pci_intr); 2263 } else { 2264 printf("compatibility"); 2265 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2266 &cmdsize, &ctlsize); 2267 } 2268 printf(" mode\n"); 2269 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2270 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2271 wdcattach(&cp->wdc_channel); 2272 if (pciide_chan_candisable(cp)) { 2273 pci_conf_write(sc->sc_pc, sc->sc_tag, 2274 PCI_COMMAND_STATUS_REG, 0); 2275 } 2276 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2277 if (cp->hw_ok == 0) 2278 return; 2279 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2280 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2281 cy693_setup_channel(&cp->wdc_channel); 2282 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2283 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2284 } 2285 2286 void 2287 cy693_setup_channel(chp) 2288 struct channel_softc *chp; 2289 { 2290 struct ata_drive_datas *drvp; 2291 int drive; 2292 u_int32_t cy_cmd_ctrl; 2293 u_int32_t idedma_ctl; 2294 struct pciide_channel *cp = (struct pciide_channel*)chp; 2295 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2296 int dma_mode = -1; 2297 2298 cy_cmd_ctrl = idedma_ctl = 0; 2299 2300 /* setup DMA if needed */ 2301 pciide_channel_dma_setup(cp); 2302 2303 for (drive = 0; drive < 2; drive++) { 2304 drvp = &chp->ch_drive[drive]; 2305 /* If no drive, skip */ 2306 if ((drvp->drive_flags & DRIVE) == 0) 2307 continue; 2308 /* add timing values, setup DMA if needed */ 2309 if (drvp->drive_flags & DRIVE_DMA) { 2310 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2311 /* use Multiword DMA */ 2312 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2313 dma_mode = drvp->DMA_mode; 2314 } 2315 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2316 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2317 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2318 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2319 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2320 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2321 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2322 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2323 } 2324 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2325 chp->ch_drive[0].DMA_mode = dma_mode; 2326 chp->ch_drive[1].DMA_mode = dma_mode; 2327 2328 if (dma_mode == -1) 2329 dma_mode = 0; 2330 2331 if (sc->sc_cy_handle != NULL) { 2332 /* Note: `multiple' is implied. */ 2333 cy82c693_write(sc->sc_cy_handle, 2334 (sc->sc_cy_compatchan == 0) ? 2335 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2336 } 2337 2338 pciide_print_modes(cp); 2339 2340 if (idedma_ctl != 0) { 2341 /* Add software bits in status register */ 2342 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2343 IDEDMA_CTL, idedma_ctl); 2344 } 2345 } 2346 2347 void 2348 sis_chip_map(sc, pa) 2349 struct pciide_softc *sc; 2350 struct pci_attach_args *pa; 2351 { 2352 struct pciide_channel *cp; 2353 int channel; 2354 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2355 pcireg_t interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2356 sc->sc_tag, PCI_CLASS_REG)); 2357 pcireg_t rev = PCI_REVISION(pci_conf_read(sc->sc_pc, 2358 sc->sc_tag, PCI_CLASS_REG)); 2359 bus_size_t cmdsize, ctlsize; 2360 2361 if (pciide_chipen(sc, pa) == 0) 2362 return; 2363 printf("%s: bus-master DMA support present", 2364 sc->sc_wdcdev.sc_dev.dv_xname); 2365 pciide_mapreg_dma(sc, pa); 2366 printf("\n"); 2367 if (sc->sc_dma_ok) { 2368 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2369 if (rev >= 0xd0) 2370 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2371 } 2372 2373 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2374 WDC_CAPABILITY_MODE; 2375 sc->sc_wdcdev.PIO_cap = 4; 2376 sc->sc_wdcdev.DMA_cap = 2; 2377 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2378 sc->sc_wdcdev.UDMA_cap = 2; 2379 sc->sc_wdcdev.set_modes = sis_setup_channel; 2380 2381 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2382 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2383 2384 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2385 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2386 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2387 2388 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2389 cp = &sc->pciide_channels[channel]; 2390 if (pciide_chansetup(sc, channel, interface) == 0) 2391 continue; 2392 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2393 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2394 printf("%s: %s channel ignored (disabled)\n", 2395 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2396 continue; 2397 } 2398 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2399 pciide_pci_intr); 2400 if (cp->hw_ok == 0) 2401 continue; 2402 if (pciide_chan_candisable(cp)) { 2403 if (channel == 0) 2404 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2405 else 2406 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2407 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2408 sis_ctr0); 2409 } 2410 pciide_map_compat_intr(pa, cp, channel, interface); 2411 if (cp->hw_ok == 0) 2412 continue; 2413 sis_setup_channel(&cp->wdc_channel); 2414 } 2415 } 2416 2417 void 2418 sis_setup_channel(chp) 2419 struct channel_softc *chp; 2420 { 2421 struct ata_drive_datas *drvp; 2422 int drive; 2423 u_int32_t sis_tim; 2424 u_int32_t idedma_ctl; 2425 struct pciide_channel *cp = (struct pciide_channel*)chp; 2426 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2427 2428 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2429 "channel %d 0x%x\n", chp->channel, 2430 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2431 DEBUG_PROBE); 2432 sis_tim = 0; 2433 idedma_ctl = 0; 2434 /* setup DMA if needed */ 2435 pciide_channel_dma_setup(cp); 2436 2437 for (drive = 0; drive < 2; drive++) { 2438 drvp = &chp->ch_drive[drive]; 2439 /* If no drive, skip */ 2440 if ((drvp->drive_flags & DRIVE) == 0) 2441 continue; 2442 /* add timing values, setup DMA if needed */ 2443 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2444 (drvp->drive_flags & DRIVE_UDMA) == 0) 2445 goto pio; 2446 2447 if (drvp->drive_flags & DRIVE_UDMA) { 2448 /* use Ultra/DMA */ 2449 drvp->drive_flags &= ~DRIVE_DMA; 2450 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2451 SIS_TIM_UDMA_TIME_OFF(drive); 2452 sis_tim |= SIS_TIM_UDMA_EN(drive); 2453 } else { 2454 /* 2455 * use Multiword DMA 2456 * Timings will be used for both PIO and DMA, 2457 * so adjust DMA mode if needed 2458 */ 2459 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2460 drvp->PIO_mode = drvp->DMA_mode + 2; 2461 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2462 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2463 drvp->PIO_mode - 2 : 0; 2464 if (drvp->DMA_mode == 0) 2465 drvp->PIO_mode = 0; 2466 } 2467 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2468 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2469 SIS_TIM_ACT_OFF(drive); 2470 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2471 SIS_TIM_REC_OFF(drive); 2472 } 2473 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2474 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2475 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2476 if (idedma_ctl != 0) { 2477 /* Add software bits in status register */ 2478 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2479 IDEDMA_CTL, idedma_ctl); 2480 } 2481 pciide_print_modes(cp); 2482 } 2483 2484 void 2485 acer_chip_map(sc, pa) 2486 struct pciide_softc *sc; 2487 struct pci_attach_args *pa; 2488 { 2489 struct pciide_channel *cp; 2490 int channel; 2491 pcireg_t cr, interface; 2492 bus_size_t cmdsize, ctlsize; 2493 2494 if (pciide_chipen(sc, pa) == 0) 2495 return; 2496 printf("%s: bus-master DMA support present", 2497 sc->sc_wdcdev.sc_dev.dv_xname); 2498 pciide_mapreg_dma(sc, pa); 2499 printf("\n"); 2500 if (sc->sc_dma_ok) 2501 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2502 2503 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2504 WDC_CAPABILITY_MODE; 2505 2506 sc->sc_wdcdev.PIO_cap = 4; 2507 sc->sc_wdcdev.DMA_cap = 2; 2508 sc->sc_wdcdev.UDMA_cap = 2; 2509 sc->sc_wdcdev.set_modes = acer_setup_channel; 2510 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2511 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2512 2513 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2514 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2515 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2516 2517 /* Enable "microsoft register bits" R/W. */ 2518 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2519 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2520 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2521 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2522 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2523 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2524 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2525 ~ACER_CHANSTATUSREGS_RO); 2526 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2527 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2528 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2529 /* Don't use cr, re-read the real register content instead */ 2530 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2531 PCI_CLASS_REG)); 2532 2533 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2534 cp = &sc->pciide_channels[channel]; 2535 if (pciide_chansetup(sc, channel, interface) == 0) 2536 continue; 2537 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2538 printf("%s: %s channel ignored (disabled)\n", 2539 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2540 continue; 2541 } 2542 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2543 acer_pci_intr); 2544 if (cp->hw_ok == 0) 2545 continue; 2546 if (pciide_chan_candisable(cp)) { 2547 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2548 pci_conf_write(sc->sc_pc, sc->sc_tag, 2549 PCI_CLASS_REG, cr); 2550 } 2551 pciide_map_compat_intr(pa, cp, channel, interface); 2552 acer_setup_channel(&cp->wdc_channel); 2553 } 2554 } 2555 2556 void 2557 acer_setup_channel(chp) 2558 struct channel_softc *chp; 2559 { 2560 struct ata_drive_datas *drvp; 2561 int drive; 2562 u_int32_t acer_fifo_udma; 2563 u_int32_t idedma_ctl; 2564 struct pciide_channel *cp = (struct pciide_channel*)chp; 2565 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2566 2567 idedma_ctl = 0; 2568 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2569 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2570 acer_fifo_udma), DEBUG_PROBE); 2571 /* setup DMA if needed */ 2572 pciide_channel_dma_setup(cp); 2573 2574 for (drive = 0; drive < 2; drive++) { 2575 drvp = &chp->ch_drive[drive]; 2576 /* If no drive, skip */ 2577 if ((drvp->drive_flags & DRIVE) == 0) 2578 continue; 2579 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2580 "channel %d drive %d 0x%x\n", chp->channel, drive, 2581 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2582 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2583 /* clear FIFO/DMA mode */ 2584 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2585 ACER_UDMA_EN(chp->channel, drive) | 2586 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2587 2588 /* add timing values, setup DMA if needed */ 2589 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2590 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2591 acer_fifo_udma |= 2592 ACER_FTH_OPL(chp->channel, drive, 0x1); 2593 goto pio; 2594 } 2595 2596 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2597 if (drvp->drive_flags & DRIVE_UDMA) { 2598 /* use Ultra/DMA */ 2599 drvp->drive_flags &= ~DRIVE_DMA; 2600 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2601 acer_fifo_udma |= 2602 ACER_UDMA_TIM(chp->channel, drive, 2603 acer_udma[drvp->UDMA_mode]); 2604 } else { 2605 /* 2606 * use Multiword DMA 2607 * Timings will be used for both PIO and DMA, 2608 * so adjust DMA mode if needed 2609 */ 2610 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2611 drvp->PIO_mode = drvp->DMA_mode + 2; 2612 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2613 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2614 drvp->PIO_mode - 2 : 0; 2615 if (drvp->DMA_mode == 0) 2616 drvp->PIO_mode = 0; 2617 } 2618 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2619 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2620 ACER_IDETIM(chp->channel, drive), 2621 acer_pio[drvp->PIO_mode]); 2622 } 2623 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2624 acer_fifo_udma), DEBUG_PROBE); 2625 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2626 if (idedma_ctl != 0) { 2627 /* Add software bits in status register */ 2628 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2629 IDEDMA_CTL, idedma_ctl); 2630 } 2631 pciide_print_modes(cp); 2632 } 2633 2634 int 2635 acer_pci_intr(arg) 2636 void *arg; 2637 { 2638 struct pciide_softc *sc = arg; 2639 struct pciide_channel *cp; 2640 struct channel_softc *wdc_cp; 2641 int i, rv, crv; 2642 u_int32_t chids; 2643 2644 rv = 0; 2645 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2646 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2647 cp = &sc->pciide_channels[i]; 2648 wdc_cp = &cp->wdc_channel; 2649 /* If a compat channel skip. */ 2650 if (cp->compat) 2651 continue; 2652 if (chids & ACER_CHIDS_INT(i)) { 2653 crv = wdcintr(wdc_cp); 2654 if (crv == 0) 2655 printf("%s:%d: bogus intr\n", 2656 sc->sc_wdcdev.sc_dev.dv_xname, i); 2657 else 2658 rv = 1; 2659 } 2660 } 2661 return rv; 2662 } 2663 2664 /* A macro to test product */ 2665 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 2666 2667 void 2668 pdc202xx_chip_map(sc, pa) 2669 struct pciide_softc *sc; 2670 struct pci_attach_args *pa; 2671 { 2672 struct pciide_channel *cp; 2673 int channel; 2674 pcireg_t interface, st, mode; 2675 bus_size_t cmdsize, ctlsize; 2676 2677 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2678 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 2679 DEBUG_PROBE); 2680 if (pciide_chipen(sc, pa) == 0) 2681 return; 2682 2683 /* turn off RAID mode */ 2684 st &= ~PDC2xx_STATE_IDERAID; 2685 2686 /* 2687 * can't rely on the PCI_CLASS_REG content if the chip was in raid 2688 * mode. We have to fake interface 2689 */ 2690 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 2691 if (st & PDC2xx_STATE_NATIVE) 2692 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 2693 2694 printf("%s: bus-master DMA support present", 2695 sc->sc_wdcdev.sc_dev.dv_xname); 2696 pciide_mapreg_dma(sc, pa); 2697 printf("\n"); 2698 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2699 WDC_CAPABILITY_MODE; 2700 if (sc->sc_dma_ok) 2701 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2702 sc->sc_wdcdev.PIO_cap = 4; 2703 sc->sc_wdcdev.DMA_cap = 2; 2704 if (PDC_IS_262(sc)) 2705 sc->sc_wdcdev.UDMA_cap = 4; 2706 else 2707 sc->sc_wdcdev.UDMA_cap = 2; 2708 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 2709 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2710 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2711 2712 /* setup failsafe defaults */ 2713 mode = 0; 2714 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 2715 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 2716 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 2717 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 2718 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2719 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 2720 "initial timings 0x%x, now 0x%x\n", channel, 2721 pci_conf_read(sc->sc_pc, sc->sc_tag, 2722 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 2723 DEBUG_PROBE); 2724 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 2725 mode | PDC2xx_TIM_IORDYp); 2726 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 2727 "initial timings 0x%x, now 0x%x\n", channel, 2728 pci_conf_read(sc->sc_pc, sc->sc_tag, 2729 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 2730 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 2731 mode); 2732 } 2733 2734 mode = PDC2xx_SCR_DMA; 2735 if (PDC_IS_262(sc)) { 2736 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 2737 } else { 2738 /* the BIOS set it up this way */ 2739 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 2740 } 2741 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 2742 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 2743 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 2744 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 2745 DEBUG_PROBE); 2746 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 2747 2748 /* controller initial state register is OK even without BIOS */ 2749 /* Set DMA mode to IDE DMA compatibility */ 2750 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 2751 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 2752 DEBUG_PROBE); 2753 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 2754 mode | 0x1); 2755 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 2756 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 2757 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 2758 mode | 0x1); 2759 2760 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2761 cp = &sc->pciide_channels[channel]; 2762 if (pciide_chansetup(sc, channel, interface) == 0) 2763 continue; 2764 if ((st & (PDC_IS_262(sc) ? 2765 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 2766 printf("%s: %s channel ignored (disabled)\n", 2767 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2768 continue; 2769 } 2770 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2771 pdc202xx_pci_intr); 2772 if (cp->hw_ok == 0) 2773 continue; 2774 if (pciide_chan_candisable(cp)) 2775 st &= ~(PDC_IS_262(sc) ? 2776 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 2777 pciide_map_compat_intr(pa, cp, channel, interface); 2778 pdc202xx_setup_channel(&cp->wdc_channel); 2779 } 2780 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 2781 DEBUG_PROBE); 2782 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 2783 return; 2784 } 2785 2786 void 2787 pdc202xx_setup_channel(chp) 2788 struct channel_softc *chp; 2789 { 2790 struct ata_drive_datas *drvp; 2791 int drive; 2792 pcireg_t mode, st; 2793 u_int32_t idedma_ctl, scr, atapi; 2794 struct pciide_channel *cp = (struct pciide_channel*)chp; 2795 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2796 int channel = chp->channel; 2797 2798 /* setup DMA if needed */ 2799 pciide_channel_dma_setup(cp); 2800 2801 idedma_ctl = 0; 2802 2803 /* Per channel settings */ 2804 if (PDC_IS_262(sc)) { 2805 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2806 PDC262_U66); 2807 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2808 /* Trimm UDMA mode */ 2809 if ((st & PDC262_STATE_80P(channel)) == 0 || 2810 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 2811 chp->ch_drive[0].UDMA_mode <= 2) || 2812 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 2813 chp->ch_drive[1].UDMA_mode <= 2)) { 2814 if (chp->ch_drive[0].UDMA_mode > 2) 2815 chp->ch_drive[0].UDMA_mode = 2; 2816 if (chp->ch_drive[1].UDMA_mode > 2) 2817 chp->ch_drive[1].UDMA_mode = 2; 2818 } 2819 /* Set U66 if needed */ 2820 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 2821 chp->ch_drive[0].UDMA_mode > 2) || 2822 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 2823 chp->ch_drive[1].UDMA_mode > 2)) 2824 scr |= PDC262_U66_EN(channel); 2825 else 2826 scr &= ~PDC262_U66_EN(channel); 2827 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2828 PDC262_U66, scr); 2829 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 2830 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 2831 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2832 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 2833 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 2834 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 2835 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2836 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 2837 atapi = 0; 2838 else 2839 atapi = PDC262_ATAPI_UDMA; 2840 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 2841 PDC262_ATAPI(channel), atapi); 2842 } 2843 } 2844 for (drive = 0; drive < 2; drive++) { 2845 drvp = &chp->ch_drive[drive]; 2846 /* If no drive, skip */ 2847 if ((drvp->drive_flags & DRIVE) == 0) 2848 continue; 2849 mode = 0; 2850 if (drvp->drive_flags & DRIVE_UDMA) { 2851 mode = PDC2xx_TIM_SET_MB(mode, 2852 pdc2xx_udma_mb[drvp->UDMA_mode]); 2853 mode = PDC2xx_TIM_SET_MC(mode, 2854 pdc2xx_udma_mc[drvp->UDMA_mode]); 2855 drvp->drive_flags &= ~DRIVE_DMA; 2856 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2857 } else if (drvp->drive_flags & DRIVE_DMA) { 2858 mode = PDC2xx_TIM_SET_MB(mode, 2859 pdc2xx_dma_mb[drvp->DMA_mode]); 2860 mode = PDC2xx_TIM_SET_MC(mode, 2861 pdc2xx_dma_mc[drvp->DMA_mode]); 2862 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2863 } else { 2864 mode = PDC2xx_TIM_SET_MB(mode, 2865 pdc2xx_dma_mb[0]); 2866 mode = PDC2xx_TIM_SET_MC(mode, 2867 pdc2xx_dma_mc[0]); 2868 } 2869 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 2870 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 2871 if (drvp->drive_flags & DRIVE_ATA) 2872 mode |= PDC2xx_TIM_PRE; 2873 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 2874 if (drvp->PIO_mode >= 3) { 2875 mode |= PDC2xx_TIM_IORDY; 2876 if (drive == 0) 2877 mode |= PDC2xx_TIM_IORDYp; 2878 } 2879 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 2880 "timings 0x%x\n", 2881 sc->sc_wdcdev.sc_dev.dv_xname, 2882 chp->channel, drive, mode), DEBUG_PROBE); 2883 pci_conf_write(sc->sc_pc, sc->sc_tag, 2884 PDC2xx_TIM(chp->channel, drive), mode); 2885 } 2886 if (idedma_ctl != 0) { 2887 /* Add software bits in status register */ 2888 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2889 IDEDMA_CTL, idedma_ctl); 2890 } 2891 pciide_print_modes(cp); 2892 } 2893 2894 int 2895 pdc202xx_pci_intr(arg) 2896 void *arg; 2897 { 2898 struct pciide_softc *sc = arg; 2899 struct pciide_channel *cp; 2900 struct channel_softc *wdc_cp; 2901 int i, rv, crv; 2902 u_int32_t scr; 2903 2904 rv = 0; 2905 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 2906 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2907 cp = &sc->pciide_channels[i]; 2908 wdc_cp = &cp->wdc_channel; 2909 /* If a compat channel skip. */ 2910 if (cp->compat) 2911 continue; 2912 if (scr & PDC2xx_SCR_INT(i)) { 2913 crv = wdcintr(wdc_cp); 2914 if (crv == 0) 2915 printf("%s:%d: bogus intr\n", 2916 sc->sc_wdcdev.sc_dev.dv_xname, i); 2917 else 2918 rv = 1; 2919 } 2920 } 2921 return rv; 2922 } 2923 2924 void 2925 opti_chip_map(sc, pa) 2926 struct pciide_softc *sc; 2927 struct pci_attach_args *pa; 2928 { 2929 struct pciide_channel *cp; 2930 bus_size_t cmdsize, ctlsize; 2931 pcireg_t interface; 2932 u_int8_t init_ctrl; 2933 int channel; 2934 2935 if (pciide_chipen(sc, pa) == 0) 2936 return; 2937 printf("%s: bus-master DMA support present", 2938 sc->sc_wdcdev.sc_dev.dv_xname); 2939 pciide_mapreg_dma(sc, pa); 2940 printf("\n"); 2941 2942 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 2943 sc->sc_wdcdev.PIO_cap = 4; 2944 if (sc->sc_dma_ok) { 2945 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2946 sc->sc_wdcdev.DMA_cap = 2; 2947 } 2948 sc->sc_wdcdev.set_modes = opti_setup_channel; 2949 2950 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2951 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2952 2953 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 2954 OPTI_REG_INIT_CONTROL); 2955 2956 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, 2957 sc->sc_tag, PCI_CLASS_REG)); 2958 2959 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2960 cp = &sc->pciide_channels[channel]; 2961 if (pciide_chansetup(sc, channel, interface) == 0) 2962 continue; 2963 if (channel == 1 && 2964 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 2965 printf("%s: %s channel ignored (disabled)\n", 2966 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2967 continue; 2968 } 2969 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2970 pciide_pci_intr); 2971 if (cp->hw_ok == 0) 2972 continue; 2973 pciide_map_compat_intr(pa, cp, channel, interface); 2974 if (cp->hw_ok == 0) 2975 continue; 2976 opti_setup_channel(&cp->wdc_channel); 2977 } 2978 } 2979 2980 void 2981 opti_setup_channel(chp) 2982 struct channel_softc *chp; 2983 { 2984 struct ata_drive_datas *drvp; 2985 struct pciide_channel *cp = (struct pciide_channel*)chp; 2986 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2987 int drive; 2988 int mode[2]; 2989 u_int8_t rv, mr; 2990 2991 /* 2992 * The `Delay' and `Address Setup Time' fields of the 2993 * Miscellaneous Register are always zero initially. 2994 */ 2995 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 2996 mr &= ~(OPTI_MISC_DELAY_MASK | 2997 OPTI_MISC_ADDR_SETUP_MASK | 2998 OPTI_MISC_INDEX_MASK); 2999 3000 /* Prime the control register before setting timing values */ 3001 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3002 3003 /* setup DMA if needed */ 3004 pciide_channel_dma_setup(cp); 3005 3006 for (drive = 0; drive < 2; drive++) { 3007 drvp = &chp->ch_drive[drive]; 3008 /* If no drive, skip */ 3009 if ((drvp->drive_flags & DRIVE) == 0) { 3010 mode[drive] = -1; 3011 continue; 3012 } 3013 3014 if ((drvp->drive_flags & DRIVE_DMA)) { 3015 /* 3016 * Timings will be used for both PIO and DMA, 3017 * so adjust DMA mode if needed 3018 */ 3019 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3020 drvp->PIO_mode = drvp->DMA_mode + 2; 3021 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3022 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3023 drvp->PIO_mode - 2 : 0; 3024 if (drvp->DMA_mode == 0) 3025 drvp->PIO_mode = 0; 3026 3027 mode[drive] = drvp->DMA_mode + 5; 3028 } else 3029 mode[drive] = drvp->PIO_mode; 3030 3031 if (drive && mode[0] >= 0 && 3032 (opti_tim_as[mode[0]] != opti_tim_as[mode[1]])) { 3033 /* 3034 * Can't have two drives using different values 3035 * for `Address Setup Time'. 3036 * Slow down the faster drive to compensate. 3037 */ 3038 int d; 3039 d = (opti_tim_as[mode[0]] > opti_tim_as[mode[1]])?0:1; 3040 3041 mode[d] = mode[1-d]; 3042 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3043 chp->ch_drive[d].DMA_mode = 0; 3044 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3045 } 3046 } 3047 3048 for (drive = 0; drive < 2; drive++) { 3049 int m; 3050 if ((m = mode[drive]) < 0) 3051 continue; 3052 3053 /* Set the Address Setup Time and select appropriate index */ 3054 rv = opti_tim_as[m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3055 rv |= OPTI_MISC_INDEX(drive); 3056 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3057 3058 /* Set the pulse width and recovery timing parameters */ 3059 rv = opti_tim_cp[m] << OPTI_PULSE_WIDTH_SHIFT; 3060 rv |= opti_tim_rt[m] << OPTI_RECOVERY_TIME_SHIFT; 3061 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3062 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3063 3064 /* Set the Enhanced Mode register appropriately */ 3065 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3066 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3067 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3068 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3069 } 3070 3071 /* Finally, enable the timings */ 3072 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3073 3074 pciide_print_modes(cp); 3075 } 3076
Indexes created Thu Oct 02 10:09:58 GMT 2025