pciide.c revision 1.68.2.10
1 /* $NetBSD: pciide.c,v 1.68.2.10 2000/08/02 17:06:17 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <vm/vm.h> 102 #include <vm/vm_param.h> 103 #include <vm/vm_kern.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/cy82c693var.h> 121 122 /* inlines for reading/writing 8-bit PCI registers */ 123 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 124 int)); 125 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 126 int, u_int8_t)); 127 128 static __inline u_int8_t 129 pciide_pci_read(pc, pa, reg) 130 pci_chipset_tag_t pc; 131 pcitag_t pa; 132 int reg; 133 { 134 135 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 136 ((reg & 0x03) * 8) & 0xff); 137 } 138 139 static __inline void 140 pciide_pci_write(pc, pa, reg, val) 141 pci_chipset_tag_t pc; 142 pcitag_t pa; 143 int reg; 144 u_int8_t val; 145 { 146 pcireg_t pcival; 147 148 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 149 pcival &= ~(0xff << ((reg & 0x03) * 8)); 150 pcival |= (val << ((reg & 0x03) * 8)); 151 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 152 } 153 154 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 155 156 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 157 void piix_setup_channel __P((struct channel_softc*)); 158 void piix3_4_setup_channel __P((struct channel_softc*)); 159 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 160 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 161 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 162 163 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 164 void amd756_setup_channel __P((struct channel_softc*)); 165 166 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 167 void apollo_setup_channel __P((struct channel_softc*)); 168 169 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 170 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void cmd0643_9_setup_channel __P((struct channel_softc*)); 172 void cmd_channel_map __P((struct pci_attach_args *, 173 struct pciide_softc *, int)); 174 int cmd_pci_intr __P((void *)); 175 void cmd646_9_irqack __P((struct channel_softc *)); 176 177 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void cy693_setup_channel __P((struct channel_softc*)); 179 180 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void sis_setup_channel __P((struct channel_softc*)); 182 183 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 184 void acer_setup_channel __P((struct channel_softc*)); 185 int acer_pci_intr __P((void *)); 186 187 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 188 void pdc202xx_setup_channel __P((struct channel_softc*)); 189 int pdc202xx_pci_intr __P((void *)); 190 191 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 192 void opti_setup_channel __P((struct channel_softc*)); 193 194 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 195 void hpt_setup_channel __P((struct channel_softc*)); 196 int hpt_pci_intr __P((void *)); 197 198 void pciide_channel_dma_setup __P((struct pciide_channel *)); 199 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 200 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 201 void pciide_dma_start __P((void*, int, int)); 202 int pciide_dma_finish __P((void*, int, int, int)); 203 void pciide_irqack __P((struct channel_softc *)); 204 void pciide_print_modes __P((struct pciide_channel *)); 205 206 struct pciide_product_desc { 207 u_int32_t ide_product; 208 int ide_flags; 209 const char *ide_name; 210 /* map and setup chip, probe drives */ 211 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 212 }; 213 214 /* Flags for ide_flags */ 215 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 216 217 /* Default product description for devices not known from this controller */ 218 const struct pciide_product_desc default_product_desc = { 219 0, 220 0, 221 "Generic PCI IDE controller", 222 default_chip_map, 223 }; 224 225 const struct pciide_product_desc pciide_intel_products[] = { 226 { PCI_PRODUCT_INTEL_82092AA, 227 0, 228 "Intel 82092AA IDE controller", 229 default_chip_map, 230 }, 231 { PCI_PRODUCT_INTEL_82371FB_IDE, 232 0, 233 "Intel 82371FB IDE controller (PIIX)", 234 piix_chip_map, 235 }, 236 { PCI_PRODUCT_INTEL_82371SB_IDE, 237 0, 238 "Intel 82371SB IDE Interface (PIIX3)", 239 piix_chip_map, 240 }, 241 { PCI_PRODUCT_INTEL_82371AB_IDE, 242 0, 243 "Intel 82371AB IDE controller (PIIX4)", 244 piix_chip_map, 245 }, 246 { PCI_PRODUCT_INTEL_82801AA_IDE, 247 0, 248 "Intel 82801AA IDE Controller (ICH)", 249 piix_chip_map, 250 }, 251 { PCI_PRODUCT_INTEL_82801AB_IDE, 252 0, 253 "Intel 82801AB IDE Controller (ICH0)", 254 piix_chip_map, 255 }, 256 { 0, 257 0, 258 NULL, 259 } 260 }; 261 262 const struct pciide_product_desc pciide_amd_products[] = { 263 { PCI_PRODUCT_AMD_PBC756_IDE, 264 0, 265 "Advanced Micro Devices AMD756 IDE Controller", 266 amd756_chip_map 267 }, 268 { 0, 269 0, 270 NULL, 271 } 272 }; 273 274 const struct pciide_product_desc pciide_cmd_products[] = { 275 { PCI_PRODUCT_CMDTECH_640, 276 0, 277 "CMD Technology PCI0640", 278 cmd_chip_map 279 }, 280 { PCI_PRODUCT_CMDTECH_643, 281 0, 282 "CMD Technology PCI0643", 283 cmd0643_9_chip_map, 284 }, 285 { PCI_PRODUCT_CMDTECH_646, 286 0, 287 "CMD Technology PCI0646", 288 cmd0643_9_chip_map, 289 }, 290 { PCI_PRODUCT_CMDTECH_648, 291 IDE_PCI_CLASS_OVERRIDE, 292 "CMD Technology PCI0648", 293 cmd0643_9_chip_map, 294 }, 295 { PCI_PRODUCT_CMDTECH_649, 296 IDE_PCI_CLASS_OVERRIDE, 297 "CMD Technology PCI0649", 298 cmd0643_9_chip_map, 299 }, 300 { 0, 301 0, 302 NULL, 303 } 304 }; 305 306 const struct pciide_product_desc pciide_via_products[] = { 307 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 308 0, 309 "VIA Tech VT82C586 IDE Controller", 310 apollo_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 313 0, 314 "VIA Tech VT82C586A IDE Controller", 315 apollo_chip_map, 316 }, 317 { 0, 318 0, 319 NULL, 320 } 321 }; 322 323 const struct pciide_product_desc pciide_cypress_products[] = { 324 { PCI_PRODUCT_CONTAQ_82C693, 325 0, 326 "Cypress 82C693 IDE Controller", 327 cy693_chip_map, 328 }, 329 { 0, 330 0, 331 NULL, 332 } 333 }; 334 335 const struct pciide_product_desc pciide_sis_products[] = { 336 { PCI_PRODUCT_SIS_5597_IDE, 337 0, 338 "Silicon Integrated System 5597/5598 IDE controller", 339 sis_chip_map, 340 }, 341 { 0, 342 0, 343 NULL, 344 } 345 }; 346 347 const struct pciide_product_desc pciide_acer_products[] = { 348 { PCI_PRODUCT_ALI_M5229, 349 0, 350 "Acer Labs M5229 UDMA IDE Controller", 351 acer_chip_map, 352 }, 353 { 0, 354 0, 355 NULL, 356 } 357 }; 358 359 const struct pciide_product_desc pciide_promise_products[] = { 360 { PCI_PRODUCT_PROMISE_ULTRA33, 361 IDE_PCI_CLASS_OVERRIDE, 362 "Promise Ultra33/ATA Bus Master IDE Accelerator", 363 pdc202xx_chip_map, 364 }, 365 { PCI_PRODUCT_PROMISE_ULTRA66, 366 IDE_PCI_CLASS_OVERRIDE, 367 "Promise Ultra66/ATA Bus Master IDE Accelerator", 368 pdc202xx_chip_map, 369 }, 370 { PCI_PRODUCT_PROMISE_ULTRA100, 371 IDE_PCI_CLASS_OVERRIDE, 372 "Promise Ultra100/ATA Bus Master IDE Accelerator", 373 pdc202xx_chip_map, 374 }, 375 { 0, 376 0, 377 NULL, 378 } 379 }; 380 381 const struct pciide_product_desc pciide_opti_products[] = { 382 { PCI_PRODUCT_OPTI_82C621, 383 0, 384 "OPTi 82c621 PCI IDE controller", 385 opti_chip_map, 386 }, 387 { PCI_PRODUCT_OPTI_82C568, 388 0, 389 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 390 opti_chip_map, 391 }, 392 { PCI_PRODUCT_OPTI_82D568, 393 0, 394 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 395 opti_chip_map, 396 }, 397 { 0, 398 0, 399 NULL, 400 } 401 }; 402 403 const struct pciide_product_desc pciide_triones_products[] = { 404 { PCI_PRODUCT_TRIONES_HPT366, 405 IDE_PCI_CLASS_OVERRIDE, 406 "Triones/Highpoint HPT366/370 IDE Controller", 407 hpt_chip_map, 408 }, 409 { 0, 410 0, 411 NULL, 412 } 413 }; 414 415 struct pciide_vendor_desc { 416 u_int32_t ide_vendor; 417 const struct pciide_product_desc *ide_products; 418 }; 419 420 const struct pciide_vendor_desc pciide_vendors[] = { 421 { PCI_VENDOR_INTEL, pciide_intel_products }, 422 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 423 { PCI_VENDOR_VIATECH, pciide_via_products }, 424 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 425 { PCI_VENDOR_SIS, pciide_sis_products }, 426 { PCI_VENDOR_ALI, pciide_acer_products }, 427 { PCI_VENDOR_PROMISE, pciide_promise_products }, 428 { PCI_VENDOR_AMD, pciide_amd_products }, 429 { PCI_VENDOR_OPTI, pciide_opti_products }, 430 { PCI_VENDOR_TRIONES, pciide_triones_products }, 431 { 0, NULL } 432 }; 433 434 /* options passed via the 'flags' config keyword */ 435 #define PCIIDE_OPTIONS_DMA 0x01 436 437 int pciide_match __P((struct device *, struct cfdata *, void *)); 438 void pciide_attach __P((struct device *, struct device *, void *)); 439 440 struct cfattach pciide_ca = { 441 sizeof(struct pciide_softc), pciide_match, pciide_attach 442 }; 443 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 444 int pciide_mapregs_compat __P(( struct pci_attach_args *, 445 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 446 int pciide_mapregs_native __P((struct pci_attach_args *, 447 struct pciide_channel *, bus_size_t *, bus_size_t *, 448 int (*pci_intr) __P((void *)))); 449 void pciide_mapreg_dma __P((struct pciide_softc *, 450 struct pci_attach_args *)); 451 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 452 void pciide_mapchan __P((struct pci_attach_args *, 453 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 454 int (*pci_intr) __P((void *)))); 455 int pciide_chan_candisable __P((struct pciide_channel *)); 456 void pciide_map_compat_intr __P(( struct pci_attach_args *, 457 struct pciide_channel *, int, int)); 458 int pciide_print __P((void *, const char *pnp)); 459 int pciide_compat_intr __P((void *)); 460 int pciide_pci_intr __P((void *)); 461 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 462 463 const struct pciide_product_desc * 464 pciide_lookup_product(id) 465 u_int32_t id; 466 { 467 const struct pciide_product_desc *pp; 468 const struct pciide_vendor_desc *vp; 469 470 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 471 if (PCI_VENDOR(id) == vp->ide_vendor) 472 break; 473 474 if ((pp = vp->ide_products) == NULL) 475 return NULL; 476 477 for (; pp->ide_name != NULL; pp++) 478 if (PCI_PRODUCT(id) == pp->ide_product) 479 break; 480 481 if (pp->ide_name == NULL) 482 return NULL; 483 return pp; 484 } 485 486 int 487 pciide_match(parent, match, aux) 488 struct device *parent; 489 struct cfdata *match; 490 void *aux; 491 { 492 struct pci_attach_args *pa = aux; 493 const struct pciide_product_desc *pp; 494 495 /* 496 * Check the ID register to see that it's a PCI IDE controller. 497 * If it is, we assume that we can deal with it; it _should_ 498 * work in a standardized way... 499 */ 500 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 501 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 502 return (1); 503 } 504 505 /* 506 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 507 * controllers. Let see if we can deal with it anyway. 508 */ 509 pp = pciide_lookup_product(pa->pa_id); 510 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 511 return (1); 512 } 513 514 return (0); 515 } 516 517 void 518 pciide_attach(parent, self, aux) 519 struct device *parent, *self; 520 void *aux; 521 { 522 struct pci_attach_args *pa = aux; 523 pci_chipset_tag_t pc = pa->pa_pc; 524 pcitag_t tag = pa->pa_tag; 525 struct pciide_softc *sc = (struct pciide_softc *)self; 526 pcireg_t csr; 527 char devinfo[256]; 528 const char *displaydev; 529 530 sc->sc_pp = pciide_lookup_product(pa->pa_id); 531 if (sc->sc_pp == NULL) { 532 sc->sc_pp = &default_product_desc; 533 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 534 displaydev = devinfo; 535 } else 536 displaydev = sc->sc_pp->ide_name; 537 538 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 539 540 sc->sc_pc = pa->pa_pc; 541 sc->sc_tag = pa->pa_tag; 542 #ifdef WDCDEBUG 543 if (wdcdebug_pciide_mask & DEBUG_PROBE) 544 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 545 #endif 546 sc->sc_pp->chip_map(sc, pa); 547 548 if (sc->sc_dma_ok) { 549 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 550 csr |= PCI_COMMAND_MASTER_ENABLE; 551 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 552 } 553 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 554 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 555 } 556 557 /* tell wether the chip is enabled or not */ 558 int 559 pciide_chipen(sc, pa) 560 struct pciide_softc *sc; 561 struct pci_attach_args *pa; 562 { 563 pcireg_t csr; 564 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 565 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 566 PCI_COMMAND_STATUS_REG); 567 printf("%s: device disabled (at %s)\n", 568 sc->sc_wdcdev.sc_dev.dv_xname, 569 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 570 "device" : "bridge"); 571 return 0; 572 } 573 return 1; 574 } 575 576 int 577 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 578 struct pci_attach_args *pa; 579 struct pciide_channel *cp; 580 int compatchan; 581 bus_size_t *cmdsizep, *ctlsizep; 582 { 583 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 584 struct channel_softc *wdc_cp = &cp->wdc_channel; 585 586 cp->compat = 1; 587 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 588 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 589 590 wdc_cp->cmd_iot = pa->pa_iot; 591 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 592 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 593 printf("%s: couldn't map %s channel cmd regs\n", 594 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 595 return (0); 596 } 597 598 wdc_cp->ctl_iot = pa->pa_iot; 599 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 600 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 601 printf("%s: couldn't map %s channel ctl regs\n", 602 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 603 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 604 PCIIDE_COMPAT_CMD_SIZE); 605 return (0); 606 } 607 608 return (1); 609 } 610 611 int 612 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 613 struct pci_attach_args * pa; 614 struct pciide_channel *cp; 615 bus_size_t *cmdsizep, *ctlsizep; 616 int (*pci_intr) __P((void *)); 617 { 618 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 619 struct channel_softc *wdc_cp = &cp->wdc_channel; 620 const char *intrstr; 621 pci_intr_handle_t intrhandle; 622 623 cp->compat = 0; 624 625 if (sc->sc_pci_ih == NULL) { 626 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 627 pa->pa_intrline, &intrhandle) != 0) { 628 printf("%s: couldn't map native-PCI interrupt\n", 629 sc->sc_wdcdev.sc_dev.dv_xname); 630 return 0; 631 } 632 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 633 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 634 intrhandle, IPL_BIO, pci_intr, sc); 635 if (sc->sc_pci_ih != NULL) { 636 printf("%s: using %s for native-PCI interrupt\n", 637 sc->sc_wdcdev.sc_dev.dv_xname, 638 intrstr ? intrstr : "unknown interrupt"); 639 } else { 640 printf("%s: couldn't establish native-PCI interrupt", 641 sc->sc_wdcdev.sc_dev.dv_xname); 642 if (intrstr != NULL) 643 printf(" at %s", intrstr); 644 printf("\n"); 645 return 0; 646 } 647 } 648 cp->ih = sc->sc_pci_ih; 649 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 650 PCI_MAPREG_TYPE_IO, 0, 651 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 652 printf("%s: couldn't map %s channel cmd regs\n", 653 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 654 return 0; 655 } 656 657 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 658 PCI_MAPREG_TYPE_IO, 0, 659 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 660 printf("%s: couldn't map %s channel ctl regs\n", 661 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 662 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 663 return 0; 664 } 665 return (1); 666 } 667 668 void 669 pciide_mapreg_dma(sc, pa) 670 struct pciide_softc *sc; 671 struct pci_attach_args *pa; 672 { 673 pcireg_t maptype; 674 675 /* 676 * Map DMA registers 677 * 678 * Note that sc_dma_ok is the right variable to test to see if 679 * DMA can be done. If the interface doesn't support DMA, 680 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 681 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 682 * non-zero if the interface supports DMA and the registers 683 * could be mapped. 684 * 685 * XXX Note that despite the fact that the Bus Master IDE specs 686 * XXX say that "The bus master IDE function uses 16 bytes of IO 687 * XXX space," some controllers (at least the United 688 * XXX Microelectronics UM8886BF) place it in memory space. 689 */ 690 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 691 PCIIDE_REG_BUS_MASTER_DMA); 692 693 switch (maptype) { 694 case PCI_MAPREG_TYPE_IO: 695 case PCI_MAPREG_MEM_TYPE_32BIT: 696 sc->sc_dma_ok = (pci_mapreg_map(pa, 697 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 698 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 699 sc->sc_dmat = pa->pa_dmat; 700 if (sc->sc_dma_ok == 0) { 701 printf(", but unused (couldn't map registers)"); 702 } else { 703 sc->sc_wdcdev.dma_arg = sc; 704 sc->sc_wdcdev.dma_init = pciide_dma_init; 705 sc->sc_wdcdev.dma_start = pciide_dma_start; 706 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 707 } 708 break; 709 710 default: 711 sc->sc_dma_ok = 0; 712 printf(", but unsupported register maptype (0x%x)", maptype); 713 } 714 } 715 716 int 717 pciide_compat_intr(arg) 718 void *arg; 719 { 720 struct pciide_channel *cp = arg; 721 722 #ifdef DIAGNOSTIC 723 /* should only be called for a compat channel */ 724 if (cp->compat == 0) 725 panic("pciide compat intr called for non-compat chan %p\n", cp); 726 #endif 727 return (wdcintr(&cp->wdc_channel)); 728 } 729 730 int 731 pciide_pci_intr(arg) 732 void *arg; 733 { 734 struct pciide_softc *sc = arg; 735 struct pciide_channel *cp; 736 struct channel_softc *wdc_cp; 737 int i, rv, crv; 738 739 rv = 0; 740 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 741 cp = &sc->pciide_channels[i]; 742 wdc_cp = &cp->wdc_channel; 743 744 /* If a compat channel skip. */ 745 if (cp->compat) 746 continue; 747 /* if this channel not waiting for intr, skip */ 748 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 749 continue; 750 751 crv = wdcintr(wdc_cp); 752 if (crv == 0) 753 ; /* leave rv alone */ 754 else if (crv == 1) 755 rv = 1; /* claim the intr */ 756 else if (rv == 0) /* crv should be -1 in this case */ 757 rv = crv; /* if we've done no better, take it */ 758 } 759 return (rv); 760 } 761 762 void 763 pciide_channel_dma_setup(cp) 764 struct pciide_channel *cp; 765 { 766 int drive; 767 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 768 struct ata_drive_datas *drvp; 769 770 for (drive = 0; drive < 2; drive++) { 771 drvp = &cp->wdc_channel.ch_drive[drive]; 772 /* If no drive, skip */ 773 if ((drvp->drive_flags & DRIVE) == 0) 774 continue; 775 /* setup DMA if needed */ 776 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 777 (drvp->drive_flags & DRIVE_UDMA) == 0) || 778 sc->sc_dma_ok == 0) { 779 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 780 continue; 781 } 782 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 783 != 0) { 784 /* Abort DMA setup */ 785 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 786 continue; 787 } 788 } 789 } 790 791 int 792 pciide_dma_table_setup(sc, channel, drive) 793 struct pciide_softc *sc; 794 int channel, drive; 795 { 796 bus_dma_segment_t seg; 797 int error, rseg; 798 const bus_size_t dma_table_size = 799 sizeof(struct idedma_table) * NIDEDMA_TABLES; 800 struct pciide_dma_maps *dma_maps = 801 &sc->pciide_channels[channel].dma_maps[drive]; 802 803 /* If table was already allocated, just return */ 804 if (dma_maps->dma_table) 805 return 0; 806 807 /* Allocate memory for the DMA tables and map it */ 808 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 809 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 810 BUS_DMA_NOWAIT)) != 0) { 811 printf("%s:%d: unable to allocate table DMA for " 812 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 813 channel, drive, error); 814 return error; 815 } 816 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 817 dma_table_size, 818 (caddr_t *)&dma_maps->dma_table, 819 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 820 printf("%s:%d: unable to map table DMA for" 821 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 822 channel, drive, error); 823 return error; 824 } 825 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 826 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 827 seg.ds_addr), DEBUG_PROBE); 828 829 /* Create and load table DMA map for this disk */ 830 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 831 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 832 &dma_maps->dmamap_table)) != 0) { 833 printf("%s:%d: unable to create table DMA map for " 834 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 835 channel, drive, error); 836 return error; 837 } 838 if ((error = bus_dmamap_load(sc->sc_dmat, 839 dma_maps->dmamap_table, 840 dma_maps->dma_table, 841 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 842 printf("%s:%d: unable to load table DMA map for " 843 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 844 channel, drive, error); 845 return error; 846 } 847 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 848 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 849 /* Create a xfer DMA map for this drive */ 850 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 851 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 852 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 853 &dma_maps->dmamap_xfer)) != 0) { 854 printf("%s:%d: unable to create xfer DMA map for " 855 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 856 channel, drive, error); 857 return error; 858 } 859 return 0; 860 } 861 862 int 863 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 864 void *v; 865 int channel, drive; 866 void *databuf; 867 size_t datalen; 868 int flags; 869 { 870 struct pciide_softc *sc = v; 871 int error, seg; 872 struct pciide_dma_maps *dma_maps = 873 &sc->pciide_channels[channel].dma_maps[drive]; 874 875 error = bus_dmamap_load(sc->sc_dmat, 876 dma_maps->dmamap_xfer, 877 databuf, datalen, NULL, BUS_DMA_NOWAIT); 878 if (error) { 879 printf("%s:%d: unable to load xfer DMA map for" 880 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 881 channel, drive, error); 882 return error; 883 } 884 885 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 886 dma_maps->dmamap_xfer->dm_mapsize, 887 (flags & WDC_DMA_READ) ? 888 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 889 890 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 891 #ifdef DIAGNOSTIC 892 /* A segment must not cross a 64k boundary */ 893 { 894 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 895 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 896 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 897 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 898 printf("pciide_dma: segment %d physical addr 0x%lx" 899 " len 0x%lx not properly aligned\n", 900 seg, phys, len); 901 panic("pciide_dma: buf align"); 902 } 903 } 904 #endif 905 dma_maps->dma_table[seg].base_addr = 906 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 907 dma_maps->dma_table[seg].byte_count = 908 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 909 IDEDMA_BYTE_COUNT_MASK); 910 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 911 seg, le32toh(dma_maps->dma_table[seg].byte_count), 912 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 913 914 } 915 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 916 htole32(IDEDMA_BYTE_COUNT_EOT); 917 918 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 919 dma_maps->dmamap_table->dm_mapsize, 920 BUS_DMASYNC_PREWRITE); 921 922 /* Maps are ready. Start DMA function */ 923 #ifdef DIAGNOSTIC 924 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 925 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 926 dma_maps->dmamap_table->dm_segs[0].ds_addr); 927 panic("pciide_dma_init: table align"); 928 } 929 #endif 930 931 /* Clear status bits */ 932 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 933 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 934 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 935 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 936 /* Write table addr */ 937 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 938 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 939 dma_maps->dmamap_table->dm_segs[0].ds_addr); 940 /* set read/write */ 941 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 942 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 943 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 944 /* remember flags */ 945 dma_maps->dma_flags = flags; 946 return 0; 947 } 948 949 void 950 pciide_dma_start(v, channel, drive) 951 void *v; 952 int channel, drive; 953 { 954 struct pciide_softc *sc = v; 955 956 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 957 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 958 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 959 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 960 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 961 } 962 963 int 964 pciide_dma_finish(v, channel, drive, force) 965 void *v; 966 int channel, drive; 967 int force; 968 { 969 struct pciide_softc *sc = v; 970 u_int8_t status; 971 int error = 0; 972 struct pciide_dma_maps *dma_maps = 973 &sc->pciide_channels[channel].dma_maps[drive]; 974 975 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 976 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 977 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 978 DEBUG_XFERS); 979 980 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 981 return WDC_DMAST_NOIRQ; 982 983 /* stop DMA channel */ 984 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 985 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 986 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 987 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 988 989 /* Unload the map of the data buffer */ 990 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 991 dma_maps->dmamap_xfer->dm_mapsize, 992 (dma_maps->dma_flags & WDC_DMA_READ) ? 993 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 994 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 995 996 if ((status & IDEDMA_CTL_ERR) != 0) { 997 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 998 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 999 error |= WDC_DMAST_ERR; 1000 } 1001 1002 if ((status & IDEDMA_CTL_INTR) == 0) { 1003 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1004 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1005 drive, status); 1006 error |= WDC_DMAST_NOIRQ; 1007 } 1008 1009 if ((status & IDEDMA_CTL_ACT) != 0) { 1010 /* data underrun, may be a valid condition for ATAPI */ 1011 error |= WDC_DMAST_UNDER; 1012 } 1013 return error; 1014 } 1015 1016 void 1017 pciide_irqack(chp) 1018 struct channel_softc *chp; 1019 { 1020 struct pciide_channel *cp = (struct pciide_channel*)chp; 1021 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1022 1023 /* clear status bits in IDE DMA registers */ 1024 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1025 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1026 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1027 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1028 } 1029 1030 /* some common code used by several chip_map */ 1031 int 1032 pciide_chansetup(sc, channel, interface) 1033 struct pciide_softc *sc; 1034 int channel; 1035 pcireg_t interface; 1036 { 1037 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1038 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1039 cp->name = PCIIDE_CHANNEL_NAME(channel); 1040 cp->wdc_channel.channel = channel; 1041 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1042 cp->wdc_channel.ch_queue = 1043 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1044 if (cp->wdc_channel.ch_queue == NULL) { 1045 printf("%s %s channel: " 1046 "can't allocate memory for command queue", 1047 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1048 return 0; 1049 } 1050 printf("%s: %s channel %s to %s mode\n", 1051 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1052 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1053 "configured" : "wired", 1054 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1055 "native-PCI" : "compatibility"); 1056 return 1; 1057 } 1058 1059 /* some common code used by several chip channel_map */ 1060 void 1061 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1062 struct pci_attach_args *pa; 1063 struct pciide_channel *cp; 1064 pcireg_t interface; 1065 bus_size_t *cmdsizep, *ctlsizep; 1066 int (*pci_intr) __P((void *)); 1067 { 1068 struct channel_softc *wdc_cp = &cp->wdc_channel; 1069 1070 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1071 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1072 pci_intr); 1073 else 1074 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1075 wdc_cp->channel, cmdsizep, ctlsizep); 1076 1077 if (cp->hw_ok == 0) 1078 return; 1079 wdc_cp->data32iot = wdc_cp->cmd_iot; 1080 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1081 wdcattach(wdc_cp); 1082 } 1083 1084 /* 1085 * Generic code to call to know if a channel can be disabled. Return 1 1086 * if channel can be disabled, 0 if not 1087 */ 1088 int 1089 pciide_chan_candisable(cp) 1090 struct pciide_channel *cp; 1091 { 1092 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1093 struct channel_softc *wdc_cp = &cp->wdc_channel; 1094 1095 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1096 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1097 printf("%s: disabling %s channel (no drives)\n", 1098 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1099 cp->hw_ok = 0; 1100 return 1; 1101 } 1102 return 0; 1103 } 1104 1105 /* 1106 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1107 * Set hw_ok=0 on failure 1108 */ 1109 void 1110 pciide_map_compat_intr(pa, cp, compatchan, interface) 1111 struct pci_attach_args *pa; 1112 struct pciide_channel *cp; 1113 int compatchan, interface; 1114 { 1115 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1116 struct channel_softc *wdc_cp = &cp->wdc_channel; 1117 1118 if (cp->hw_ok == 0) 1119 return; 1120 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1121 return; 1122 1123 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1124 pa, compatchan, pciide_compat_intr, cp); 1125 if (cp->ih == NULL) { 1126 printf("%s: no compatibility interrupt for use by %s " 1127 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1128 cp->hw_ok = 0; 1129 } 1130 } 1131 1132 void 1133 pciide_print_modes(cp) 1134 struct pciide_channel *cp; 1135 { 1136 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1137 int drive; 1138 struct channel_softc *chp; 1139 struct ata_drive_datas *drvp; 1140 1141 chp = &cp->wdc_channel; 1142 for (drive = 0; drive < 2; drive++) { 1143 drvp = &chp->ch_drive[drive]; 1144 if ((drvp->drive_flags & DRIVE) == 0) 1145 continue; 1146 printf("%s(%s:%d:%d): using PIO mode %d", 1147 drvp->drv_softc->dv_xname, 1148 sc->sc_wdcdev.sc_dev.dv_xname, 1149 chp->channel, drive, drvp->PIO_mode); 1150 if (drvp->drive_flags & DRIVE_DMA) 1151 printf(", DMA mode %d", drvp->DMA_mode); 1152 if (drvp->drive_flags & DRIVE_UDMA) 1153 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1154 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1155 printf(" (using DMA data transfers)"); 1156 printf("\n"); 1157 } 1158 } 1159 1160 void 1161 default_chip_map(sc, pa) 1162 struct pciide_softc *sc; 1163 struct pci_attach_args *pa; 1164 { 1165 struct pciide_channel *cp; 1166 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1167 pcireg_t csr; 1168 int channel, drive; 1169 struct ata_drive_datas *drvp; 1170 u_int8_t idedma_ctl; 1171 bus_size_t cmdsize, ctlsize; 1172 char *failreason; 1173 1174 if (pciide_chipen(sc, pa) == 0) 1175 return; 1176 1177 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1178 printf("%s: bus-master DMA support present", 1179 sc->sc_wdcdev.sc_dev.dv_xname); 1180 if (sc->sc_pp == &default_product_desc && 1181 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1182 PCIIDE_OPTIONS_DMA) == 0) { 1183 printf(", but unused (no driver support)"); 1184 sc->sc_dma_ok = 0; 1185 } else { 1186 pciide_mapreg_dma(sc, pa); 1187 if (sc->sc_dma_ok != 0) 1188 printf(", used without full driver " 1189 "support"); 1190 } 1191 } else { 1192 printf("%s: hardware does not support DMA", 1193 sc->sc_wdcdev.sc_dev.dv_xname); 1194 sc->sc_dma_ok = 0; 1195 } 1196 printf("\n"); 1197 if (sc->sc_dma_ok) { 1198 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1199 sc->sc_wdcdev.irqack = pciide_irqack; 1200 } 1201 sc->sc_wdcdev.PIO_cap = 0; 1202 sc->sc_wdcdev.DMA_cap = 0; 1203 1204 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1205 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1206 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1207 1208 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1209 cp = &sc->pciide_channels[channel]; 1210 if (pciide_chansetup(sc, channel, interface) == 0) 1211 continue; 1212 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1213 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1214 &ctlsize, pciide_pci_intr); 1215 } else { 1216 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1217 channel, &cmdsize, &ctlsize); 1218 } 1219 if (cp->hw_ok == 0) 1220 continue; 1221 /* 1222 * Check to see if something appears to be there. 1223 */ 1224 failreason = NULL; 1225 if (!wdcprobe(&cp->wdc_channel)) { 1226 failreason = "not responding; disabled or no drives?"; 1227 goto next; 1228 } 1229 /* 1230 * Now, make sure it's actually attributable to this PCI IDE 1231 * channel by trying to access the channel again while the 1232 * PCI IDE controller's I/O space is disabled. (If the 1233 * channel no longer appears to be there, it belongs to 1234 * this controller.) YUCK! 1235 */ 1236 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1237 PCI_COMMAND_STATUS_REG); 1238 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1239 csr & ~PCI_COMMAND_IO_ENABLE); 1240 if (wdcprobe(&cp->wdc_channel)) 1241 failreason = "other hardware responding at addresses"; 1242 pci_conf_write(sc->sc_pc, sc->sc_tag, 1243 PCI_COMMAND_STATUS_REG, csr); 1244 next: 1245 if (failreason) { 1246 printf("%s: %s channel ignored (%s)\n", 1247 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1248 failreason); 1249 cp->hw_ok = 0; 1250 bus_space_unmap(cp->wdc_channel.cmd_iot, 1251 cp->wdc_channel.cmd_ioh, cmdsize); 1252 bus_space_unmap(cp->wdc_channel.ctl_iot, 1253 cp->wdc_channel.ctl_ioh, ctlsize); 1254 } else { 1255 pciide_map_compat_intr(pa, cp, channel, interface); 1256 } 1257 if (cp->hw_ok) { 1258 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1259 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1260 wdcattach(&cp->wdc_channel); 1261 } 1262 } 1263 1264 if (sc->sc_dma_ok == 0) 1265 return; 1266 1267 /* Allocate DMA maps */ 1268 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1269 idedma_ctl = 0; 1270 cp = &sc->pciide_channels[channel]; 1271 for (drive = 0; drive < 2; drive++) { 1272 drvp = &cp->wdc_channel.ch_drive[drive]; 1273 /* If no drive, skip */ 1274 if ((drvp->drive_flags & DRIVE) == 0) 1275 continue; 1276 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1277 continue; 1278 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1279 /* Abort DMA setup */ 1280 printf("%s:%d:%d: can't allocate DMA maps, " 1281 "using PIO transfers\n", 1282 sc->sc_wdcdev.sc_dev.dv_xname, 1283 channel, drive); 1284 drvp->drive_flags &= ~DRIVE_DMA; 1285 } 1286 printf("%s:%d:%d: using DMA data transfers\n", 1287 sc->sc_wdcdev.sc_dev.dv_xname, 1288 channel, drive); 1289 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1290 } 1291 if (idedma_ctl != 0) { 1292 /* Add software bits in status register */ 1293 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1294 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1295 idedma_ctl); 1296 } 1297 } 1298 } 1299 1300 void 1301 piix_chip_map(sc, pa) 1302 struct pciide_softc *sc; 1303 struct pci_attach_args *pa; 1304 { 1305 struct pciide_channel *cp; 1306 int channel; 1307 u_int32_t idetim; 1308 bus_size_t cmdsize, ctlsize; 1309 1310 if (pciide_chipen(sc, pa) == 0) 1311 return; 1312 1313 printf("%s: bus-master DMA support present", 1314 sc->sc_wdcdev.sc_dev.dv_xname); 1315 pciide_mapreg_dma(sc, pa); 1316 printf("\n"); 1317 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1318 WDC_CAPABILITY_MODE; 1319 if (sc->sc_dma_ok) { 1320 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1321 sc->sc_wdcdev.irqack = pciide_irqack; 1322 switch(sc->sc_pp->ide_product) { 1323 case PCI_PRODUCT_INTEL_82371AB_IDE: 1324 case PCI_PRODUCT_INTEL_82801AA_IDE: 1325 case PCI_PRODUCT_INTEL_82801AB_IDE: 1326 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1327 } 1328 } 1329 sc->sc_wdcdev.PIO_cap = 4; 1330 sc->sc_wdcdev.DMA_cap = 2; 1331 sc->sc_wdcdev.UDMA_cap = 1332 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1333 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1334 sc->sc_wdcdev.set_modes = piix_setup_channel; 1335 else 1336 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1337 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1338 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1339 1340 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1341 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1342 DEBUG_PROBE); 1343 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1344 WDCDEBUG_PRINT((", sidetim=0x%x", 1345 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1346 DEBUG_PROBE); 1347 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1348 WDCDEBUG_PRINT((", udamreg 0x%x", 1349 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1350 DEBUG_PROBE); 1351 } 1352 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1353 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1354 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1355 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1356 DEBUG_PROBE); 1357 } 1358 1359 } 1360 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1361 1362 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1363 cp = &sc->pciide_channels[channel]; 1364 /* PIIX is compat-only */ 1365 if (pciide_chansetup(sc, channel, 0) == 0) 1366 continue; 1367 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1368 if ((PIIX_IDETIM_READ(idetim, channel) & 1369 PIIX_IDETIM_IDE) == 0) { 1370 printf("%s: %s channel ignored (disabled)\n", 1371 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1372 continue; 1373 } 1374 /* PIIX are compat-only pciide devices */ 1375 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1376 if (cp->hw_ok == 0) 1377 continue; 1378 if (pciide_chan_candisable(cp)) { 1379 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1380 channel); 1381 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1382 idetim); 1383 } 1384 pciide_map_compat_intr(pa, cp, channel, 0); 1385 if (cp->hw_ok == 0) 1386 continue; 1387 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1388 } 1389 1390 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1391 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1392 DEBUG_PROBE); 1393 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1394 WDCDEBUG_PRINT((", sidetim=0x%x", 1395 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1396 DEBUG_PROBE); 1397 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1398 WDCDEBUG_PRINT((", udamreg 0x%x", 1399 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1400 DEBUG_PROBE); 1401 } 1402 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1403 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1404 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1405 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1406 DEBUG_PROBE); 1407 } 1408 } 1409 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1410 } 1411 1412 void 1413 piix_setup_channel(chp) 1414 struct channel_softc *chp; 1415 { 1416 u_int8_t mode[2], drive; 1417 u_int32_t oidetim, idetim, idedma_ctl; 1418 struct pciide_channel *cp = (struct pciide_channel*)chp; 1419 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1420 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1421 1422 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1423 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1424 idedma_ctl = 0; 1425 1426 /* set up new idetim: Enable IDE registers decode */ 1427 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1428 chp->channel); 1429 1430 /* setup DMA */ 1431 pciide_channel_dma_setup(cp); 1432 1433 /* 1434 * Here we have to mess up with drives mode: PIIX can't have 1435 * different timings for master and slave drives. 1436 * We need to find the best combination. 1437 */ 1438 1439 /* If both drives supports DMA, take the lower mode */ 1440 if ((drvp[0].drive_flags & DRIVE_DMA) && 1441 (drvp[1].drive_flags & DRIVE_DMA)) { 1442 mode[0] = mode[1] = 1443 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1444 drvp[0].DMA_mode = mode[0]; 1445 drvp[1].DMA_mode = mode[1]; 1446 goto ok; 1447 } 1448 /* 1449 * If only one drive supports DMA, use its mode, and 1450 * put the other one in PIO mode 0 if mode not compatible 1451 */ 1452 if (drvp[0].drive_flags & DRIVE_DMA) { 1453 mode[0] = drvp[0].DMA_mode; 1454 mode[1] = drvp[1].PIO_mode; 1455 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1456 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1457 mode[1] = drvp[1].PIO_mode = 0; 1458 goto ok; 1459 } 1460 if (drvp[1].drive_flags & DRIVE_DMA) { 1461 mode[1] = drvp[1].DMA_mode; 1462 mode[0] = drvp[0].PIO_mode; 1463 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1464 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1465 mode[0] = drvp[0].PIO_mode = 0; 1466 goto ok; 1467 } 1468 /* 1469 * If both drives are not DMA, takes the lower mode, unless 1470 * one of them is PIO mode < 2 1471 */ 1472 if (drvp[0].PIO_mode < 2) { 1473 mode[0] = drvp[0].PIO_mode = 0; 1474 mode[1] = drvp[1].PIO_mode; 1475 } else if (drvp[1].PIO_mode < 2) { 1476 mode[1] = drvp[1].PIO_mode = 0; 1477 mode[0] = drvp[0].PIO_mode; 1478 } else { 1479 mode[0] = mode[1] = 1480 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1481 drvp[0].PIO_mode = mode[0]; 1482 drvp[1].PIO_mode = mode[1]; 1483 } 1484 ok: /* The modes are setup */ 1485 for (drive = 0; drive < 2; drive++) { 1486 if (drvp[drive].drive_flags & DRIVE_DMA) { 1487 idetim |= piix_setup_idetim_timings( 1488 mode[drive], 1, chp->channel); 1489 goto end; 1490 } 1491 } 1492 /* If we are there, none of the drives are DMA */ 1493 if (mode[0] >= 2) 1494 idetim |= piix_setup_idetim_timings( 1495 mode[0], 0, chp->channel); 1496 else 1497 idetim |= piix_setup_idetim_timings( 1498 mode[1], 0, chp->channel); 1499 end: /* 1500 * timing mode is now set up in the controller. Enable 1501 * it per-drive 1502 */ 1503 for (drive = 0; drive < 2; drive++) { 1504 /* If no drive, skip */ 1505 if ((drvp[drive].drive_flags & DRIVE) == 0) 1506 continue; 1507 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1508 if (drvp[drive].drive_flags & DRIVE_DMA) 1509 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1510 } 1511 if (idedma_ctl != 0) { 1512 /* Add software bits in status register */ 1513 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1514 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1515 idedma_ctl); 1516 } 1517 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1518 pciide_print_modes(cp); 1519 } 1520 1521 void 1522 piix3_4_setup_channel(chp) 1523 struct channel_softc *chp; 1524 { 1525 struct ata_drive_datas *drvp; 1526 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1527 struct pciide_channel *cp = (struct pciide_channel*)chp; 1528 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1529 int drive; 1530 int channel = chp->channel; 1531 1532 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1533 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1534 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1535 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1536 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1537 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1538 PIIX_SIDETIM_RTC_MASK(channel)); 1539 1540 idedma_ctl = 0; 1541 /* If channel disabled, no need to go further */ 1542 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1543 return; 1544 /* set up new idetim: Enable IDE registers decode */ 1545 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1546 1547 /* setup DMA if needed */ 1548 pciide_channel_dma_setup(cp); 1549 1550 for (drive = 0; drive < 2; drive++) { 1551 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1552 PIIX_UDMATIM_SET(0x3, channel, drive)); 1553 drvp = &chp->ch_drive[drive]; 1554 /* If no drive, skip */ 1555 if ((drvp->drive_flags & DRIVE) == 0) 1556 continue; 1557 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1558 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1559 goto pio; 1560 1561 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1562 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1563 ideconf |= PIIX_CONFIG_PINGPONG; 1564 } 1565 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1566 /* setup Ultra/66 */ 1567 if (drvp->UDMA_mode > 2 && 1568 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1569 drvp->UDMA_mode = 2; 1570 if (drvp->UDMA_mode > 2) 1571 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1572 else 1573 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1574 } 1575 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1576 (drvp->drive_flags & DRIVE_UDMA)) { 1577 /* use Ultra/DMA */ 1578 drvp->drive_flags &= ~DRIVE_DMA; 1579 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1580 udmareg |= PIIX_UDMATIM_SET( 1581 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1582 } else { 1583 /* use Multiword DMA */ 1584 drvp->drive_flags &= ~DRIVE_UDMA; 1585 if (drive == 0) { 1586 idetim |= piix_setup_idetim_timings( 1587 drvp->DMA_mode, 1, channel); 1588 } else { 1589 sidetim |= piix_setup_sidetim_timings( 1590 drvp->DMA_mode, 1, channel); 1591 idetim =PIIX_IDETIM_SET(idetim, 1592 PIIX_IDETIM_SITRE, channel); 1593 } 1594 } 1595 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1596 1597 pio: /* use PIO mode */ 1598 idetim |= piix_setup_idetim_drvs(drvp); 1599 if (drive == 0) { 1600 idetim |= piix_setup_idetim_timings( 1601 drvp->PIO_mode, 0, channel); 1602 } else { 1603 sidetim |= piix_setup_sidetim_timings( 1604 drvp->PIO_mode, 0, channel); 1605 idetim =PIIX_IDETIM_SET(idetim, 1606 PIIX_IDETIM_SITRE, channel); 1607 } 1608 } 1609 if (idedma_ctl != 0) { 1610 /* Add software bits in status register */ 1611 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1612 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1613 idedma_ctl); 1614 } 1615 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1616 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1617 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1618 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1619 pciide_print_modes(cp); 1620 } 1621 1622 1623 /* setup ISP and RTC fields, based on mode */ 1624 static u_int32_t 1625 piix_setup_idetim_timings(mode, dma, channel) 1626 u_int8_t mode; 1627 u_int8_t dma; 1628 u_int8_t channel; 1629 { 1630 1631 if (dma) 1632 return PIIX_IDETIM_SET(0, 1633 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1634 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1635 channel); 1636 else 1637 return PIIX_IDETIM_SET(0, 1638 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1639 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1640 channel); 1641 } 1642 1643 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1644 static u_int32_t 1645 piix_setup_idetim_drvs(drvp) 1646 struct ata_drive_datas *drvp; 1647 { 1648 u_int32_t ret = 0; 1649 struct channel_softc *chp = drvp->chnl_softc; 1650 u_int8_t channel = chp->channel; 1651 u_int8_t drive = drvp->drive; 1652 1653 /* 1654 * If drive is using UDMA, timings setups are independant 1655 * So just check DMA and PIO here. 1656 */ 1657 if (drvp->drive_flags & DRIVE_DMA) { 1658 /* if mode = DMA mode 0, use compatible timings */ 1659 if ((drvp->drive_flags & DRIVE_DMA) && 1660 drvp->DMA_mode == 0) { 1661 drvp->PIO_mode = 0; 1662 return ret; 1663 } 1664 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1665 /* 1666 * PIO and DMA timings are the same, use fast timings for PIO 1667 * too, else use compat timings. 1668 */ 1669 if ((piix_isp_pio[drvp->PIO_mode] != 1670 piix_isp_dma[drvp->DMA_mode]) || 1671 (piix_rtc_pio[drvp->PIO_mode] != 1672 piix_rtc_dma[drvp->DMA_mode])) 1673 drvp->PIO_mode = 0; 1674 /* if PIO mode <= 2, use compat timings for PIO */ 1675 if (drvp->PIO_mode <= 2) { 1676 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1677 channel); 1678 return ret; 1679 } 1680 } 1681 1682 /* 1683 * Now setup PIO modes. If mode < 2, use compat timings. 1684 * Else enable fast timings. Enable IORDY and prefetch/post 1685 * if PIO mode >= 3. 1686 */ 1687 1688 if (drvp->PIO_mode < 2) 1689 return ret; 1690 1691 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1692 if (drvp->PIO_mode >= 3) { 1693 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1694 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1695 } 1696 return ret; 1697 } 1698 1699 /* setup values in SIDETIM registers, based on mode */ 1700 static u_int32_t 1701 piix_setup_sidetim_timings(mode, dma, channel) 1702 u_int8_t mode; 1703 u_int8_t dma; 1704 u_int8_t channel; 1705 { 1706 if (dma) 1707 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1708 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1709 else 1710 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1711 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1712 } 1713 1714 void 1715 amd756_chip_map(sc, pa) 1716 struct pciide_softc *sc; 1717 struct pci_attach_args *pa; 1718 { 1719 struct pciide_channel *cp; 1720 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1721 int channel; 1722 pcireg_t chanenable; 1723 bus_size_t cmdsize, ctlsize; 1724 1725 if (pciide_chipen(sc, pa) == 0) 1726 return; 1727 printf("%s: bus-master DMA support present", 1728 sc->sc_wdcdev.sc_dev.dv_xname); 1729 pciide_mapreg_dma(sc, pa); 1730 printf("\n"); 1731 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1732 WDC_CAPABILITY_MODE; 1733 if (sc->sc_dma_ok) { 1734 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1735 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1736 sc->sc_wdcdev.irqack = pciide_irqack; 1737 } 1738 sc->sc_wdcdev.PIO_cap = 4; 1739 sc->sc_wdcdev.DMA_cap = 2; 1740 sc->sc_wdcdev.UDMA_cap = 4; 1741 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1742 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1743 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1744 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1745 1746 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1747 DEBUG_PROBE); 1748 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1749 cp = &sc->pciide_channels[channel]; 1750 if (pciide_chansetup(sc, channel, interface) == 0) 1751 continue; 1752 1753 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1754 printf("%s: %s channel ignored (disabled)\n", 1755 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1756 continue; 1757 } 1758 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1759 pciide_pci_intr); 1760 1761 if (pciide_chan_candisable(cp)) 1762 chanenable &= ~AMD756_CHAN_EN(channel); 1763 pciide_map_compat_intr(pa, cp, channel, interface); 1764 if (cp->hw_ok == 0) 1765 continue; 1766 1767 amd756_setup_channel(&cp->wdc_channel); 1768 } 1769 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1770 chanenable); 1771 return; 1772 } 1773 1774 void 1775 amd756_setup_channel(chp) 1776 struct channel_softc *chp; 1777 { 1778 u_int32_t udmatim_reg, datatim_reg; 1779 u_int8_t idedma_ctl; 1780 int mode, drive; 1781 struct ata_drive_datas *drvp; 1782 struct pciide_channel *cp = (struct pciide_channel*)chp; 1783 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1784 #ifndef PCIIDE_AMD756_ENABLEDMA 1785 int rev = PCI_REVISION( 1786 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1787 #endif 1788 1789 idedma_ctl = 0; 1790 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1791 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1792 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1793 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1794 1795 /* setup DMA if needed */ 1796 pciide_channel_dma_setup(cp); 1797 1798 for (drive = 0; drive < 2; drive++) { 1799 drvp = &chp->ch_drive[drive]; 1800 /* If no drive, skip */ 1801 if ((drvp->drive_flags & DRIVE) == 0) 1802 continue; 1803 /* add timing values, setup DMA if needed */ 1804 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1805 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1806 mode = drvp->PIO_mode; 1807 goto pio; 1808 } 1809 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1810 (drvp->drive_flags & DRIVE_UDMA)) { 1811 /* use Ultra/DMA */ 1812 drvp->drive_flags &= ~DRIVE_DMA; 1813 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1814 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1815 AMD756_UDMA_TIME(chp->channel, drive, 1816 amd756_udma_tim[drvp->UDMA_mode]); 1817 /* can use PIO timings, MW DMA unused */ 1818 mode = drvp->PIO_mode; 1819 } else { 1820 /* use Multiword DMA, but only if revision is OK */ 1821 drvp->drive_flags &= ~DRIVE_UDMA; 1822 #ifndef PCIIDE_AMD756_ENABLEDMA 1823 /* 1824 * The workaround doesn't seem to be necessary 1825 * with all drives, so it can be disabled by 1826 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1827 * triggered. 1828 */ 1829 if (AMD756_CHIPREV_DISABLEDMA(rev)) { 1830 printf("%s:%d:%d: multi-word DMA disabled due " 1831 "to chip revision\n", 1832 sc->sc_wdcdev.sc_dev.dv_xname, 1833 chp->channel, drive); 1834 mode = drvp->PIO_mode; 1835 drvp->drive_flags &= ~DRIVE_DMA; 1836 goto pio; 1837 } 1838 #endif 1839 /* mode = min(pio, dma+2) */ 1840 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1841 mode = drvp->PIO_mode; 1842 else 1843 mode = drvp->DMA_mode + 2; 1844 } 1845 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1846 1847 pio: /* setup PIO mode */ 1848 if (mode <= 2) { 1849 drvp->DMA_mode = 0; 1850 drvp->PIO_mode = 0; 1851 mode = 0; 1852 } else { 1853 drvp->PIO_mode = mode; 1854 drvp->DMA_mode = mode - 2; 1855 } 1856 datatim_reg |= 1857 AMD756_DATATIM_PULSE(chp->channel, drive, 1858 amd756_pio_set[mode]) | 1859 AMD756_DATATIM_RECOV(chp->channel, drive, 1860 amd756_pio_rec[mode]); 1861 } 1862 if (idedma_ctl != 0) { 1863 /* Add software bits in status register */ 1864 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1865 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1866 idedma_ctl); 1867 } 1868 pciide_print_modes(cp); 1869 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1870 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1871 } 1872 1873 void 1874 apollo_chip_map(sc, pa) 1875 struct pciide_softc *sc; 1876 struct pci_attach_args *pa; 1877 { 1878 struct pciide_channel *cp; 1879 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1880 int channel; 1881 u_int32_t ideconf; 1882 bus_size_t cmdsize, ctlsize; 1883 1884 if (pciide_chipen(sc, pa) == 0) 1885 return; 1886 printf("%s: bus-master DMA support present", 1887 sc->sc_wdcdev.sc_dev.dv_xname); 1888 pciide_mapreg_dma(sc, pa); 1889 printf("\n"); 1890 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1891 WDC_CAPABILITY_MODE; 1892 if (sc->sc_dma_ok) { 1893 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1894 sc->sc_wdcdev.irqack = pciide_irqack; 1895 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1896 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1897 } 1898 sc->sc_wdcdev.PIO_cap = 4; 1899 sc->sc_wdcdev.DMA_cap = 2; 1900 sc->sc_wdcdev.UDMA_cap = 2; 1901 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1902 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1903 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1904 1905 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1906 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1907 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1908 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1909 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1910 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1911 DEBUG_PROBE); 1912 1913 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1914 cp = &sc->pciide_channels[channel]; 1915 if (pciide_chansetup(sc, channel, interface) == 0) 1916 continue; 1917 1918 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1919 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1920 printf("%s: %s channel ignored (disabled)\n", 1921 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1922 continue; 1923 } 1924 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1925 pciide_pci_intr); 1926 if (cp->hw_ok == 0) 1927 continue; 1928 if (pciide_chan_candisable(cp)) { 1929 ideconf &= ~APO_IDECONF_EN(channel); 1930 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1931 ideconf); 1932 } 1933 pciide_map_compat_intr(pa, cp, channel, interface); 1934 1935 if (cp->hw_ok == 0) 1936 continue; 1937 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1938 } 1939 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1940 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1941 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1942 } 1943 1944 void 1945 apollo_setup_channel(chp) 1946 struct channel_softc *chp; 1947 { 1948 u_int32_t udmatim_reg, datatim_reg; 1949 u_int8_t idedma_ctl; 1950 int mode, drive; 1951 struct ata_drive_datas *drvp; 1952 struct pciide_channel *cp = (struct pciide_channel*)chp; 1953 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1954 1955 idedma_ctl = 0; 1956 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1957 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1958 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1959 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1960 1961 /* setup DMA if needed */ 1962 pciide_channel_dma_setup(cp); 1963 1964 for (drive = 0; drive < 2; drive++) { 1965 drvp = &chp->ch_drive[drive]; 1966 /* If no drive, skip */ 1967 if ((drvp->drive_flags & DRIVE) == 0) 1968 continue; 1969 /* add timing values, setup DMA if needed */ 1970 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1971 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1972 mode = drvp->PIO_mode; 1973 goto pio; 1974 } 1975 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1976 (drvp->drive_flags & DRIVE_UDMA)) { 1977 /* use Ultra/DMA */ 1978 drvp->drive_flags &= ~DRIVE_DMA; 1979 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1980 APO_UDMA_EN_MTH(chp->channel, drive) | 1981 APO_UDMA_TIME(chp->channel, drive, 1982 apollo_udma_tim[drvp->UDMA_mode]); 1983 /* can use PIO timings, MW DMA unused */ 1984 mode = drvp->PIO_mode; 1985 } else { 1986 /* use Multiword DMA */ 1987 drvp->drive_flags &= ~DRIVE_UDMA; 1988 /* mode = min(pio, dma+2) */ 1989 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1990 mode = drvp->PIO_mode; 1991 else 1992 mode = drvp->DMA_mode + 2; 1993 } 1994 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1995 1996 pio: /* setup PIO mode */ 1997 if (mode <= 2) { 1998 drvp->DMA_mode = 0; 1999 drvp->PIO_mode = 0; 2000 mode = 0; 2001 } else { 2002 drvp->PIO_mode = mode; 2003 drvp->DMA_mode = mode - 2; 2004 } 2005 datatim_reg |= 2006 APO_DATATIM_PULSE(chp->channel, drive, 2007 apollo_pio_set[mode]) | 2008 APO_DATATIM_RECOV(chp->channel, drive, 2009 apollo_pio_rec[mode]); 2010 } 2011 if (idedma_ctl != 0) { 2012 /* Add software bits in status register */ 2013 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2014 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2015 idedma_ctl); 2016 } 2017 pciide_print_modes(cp); 2018 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2019 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2020 } 2021 2022 void 2023 cmd_channel_map(pa, sc, channel) 2024 struct pci_attach_args *pa; 2025 struct pciide_softc *sc; 2026 int channel; 2027 { 2028 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2029 bus_size_t cmdsize, ctlsize; 2030 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2031 int interface; 2032 2033 /* 2034 * The 0648/0649 can be told to identify as a RAID controller. 2035 * In this case, we have to fake interface 2036 */ 2037 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2038 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2039 PCIIDE_INTERFACE_SETTABLE(1); 2040 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2041 CMD_CONF_DSA1) 2042 interface |= PCIIDE_INTERFACE_PCI(0) | 2043 PCIIDE_INTERFACE_PCI(1); 2044 } else { 2045 interface = PCI_INTERFACE(pa->pa_class); 2046 } 2047 2048 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2049 cp->name = PCIIDE_CHANNEL_NAME(channel); 2050 cp->wdc_channel.channel = channel; 2051 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2052 2053 if (channel > 0) { 2054 cp->wdc_channel.ch_queue = 2055 sc->pciide_channels[0].wdc_channel.ch_queue; 2056 } else { 2057 cp->wdc_channel.ch_queue = 2058 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2059 } 2060 if (cp->wdc_channel.ch_queue == NULL) { 2061 printf("%s %s channel: " 2062 "can't allocate memory for command queue", 2063 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2064 return; 2065 } 2066 2067 printf("%s: %s channel %s to %s mode\n", 2068 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2069 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2070 "configured" : "wired", 2071 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2072 "native-PCI" : "compatibility"); 2073 2074 /* 2075 * with a CMD PCI64x, if we get here, the first channel is enabled: 2076 * there's no way to disable the first channel without disabling 2077 * the whole device 2078 */ 2079 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2080 printf("%s: %s channel ignored (disabled)\n", 2081 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2082 return; 2083 } 2084 2085 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2086 if (cp->hw_ok == 0) 2087 return; 2088 if (channel == 1) { 2089 if (pciide_chan_candisable(cp)) { 2090 ctrl &= ~CMD_CTRL_2PORT; 2091 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2092 CMD_CTRL, ctrl); 2093 } 2094 } 2095 pciide_map_compat_intr(pa, cp, channel, interface); 2096 } 2097 2098 int 2099 cmd_pci_intr(arg) 2100 void *arg; 2101 { 2102 struct pciide_softc *sc = arg; 2103 struct pciide_channel *cp; 2104 struct channel_softc *wdc_cp; 2105 int i, rv, crv; 2106 u_int32_t priirq, secirq; 2107 2108 rv = 0; 2109 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2110 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2111 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2112 cp = &sc->pciide_channels[i]; 2113 wdc_cp = &cp->wdc_channel; 2114 /* If a compat channel skip. */ 2115 if (cp->compat) 2116 continue; 2117 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2118 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2119 crv = wdcintr(wdc_cp); 2120 if (crv == 0) 2121 printf("%s:%d: bogus intr\n", 2122 sc->sc_wdcdev.sc_dev.dv_xname, i); 2123 else 2124 rv = 1; 2125 } 2126 } 2127 return rv; 2128 } 2129 2130 void 2131 cmd_chip_map(sc, pa) 2132 struct pciide_softc *sc; 2133 struct pci_attach_args *pa; 2134 { 2135 int channel; 2136 2137 /* 2138 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2139 * and base adresses registers can be disabled at 2140 * hardware level. In this case, the device is wired 2141 * in compat mode and its first channel is always enabled, 2142 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2143 * In fact, it seems that the first channel of the CMD PCI0640 2144 * can't be disabled. 2145 */ 2146 2147 #ifdef PCIIDE_CMD064x_DISABLE 2148 if (pciide_chipen(sc, pa) == 0) 2149 return; 2150 #endif 2151 2152 printf("%s: hardware does not support DMA\n", 2153 sc->sc_wdcdev.sc_dev.dv_xname); 2154 sc->sc_dma_ok = 0; 2155 2156 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2157 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2158 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2159 2160 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2161 cmd_channel_map(pa, sc, channel); 2162 } 2163 } 2164 2165 void 2166 cmd0643_9_chip_map(sc, pa) 2167 struct pciide_softc *sc; 2168 struct pci_attach_args *pa; 2169 { 2170 struct pciide_channel *cp; 2171 int channel; 2172 int rev = PCI_REVISION( 2173 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2174 2175 /* 2176 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2177 * and base adresses registers can be disabled at 2178 * hardware level. In this case, the device is wired 2179 * in compat mode and its first channel is always enabled, 2180 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2181 * In fact, it seems that the first channel of the CMD PCI0640 2182 * can't be disabled. 2183 */ 2184 2185 #ifdef PCIIDE_CMD064x_DISABLE 2186 if (pciide_chipen(sc, pa) == 0) 2187 return; 2188 #endif 2189 printf("%s: bus-master DMA support present", 2190 sc->sc_wdcdev.sc_dev.dv_xname); 2191 pciide_mapreg_dma(sc, pa); 2192 printf("\n"); 2193 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2194 WDC_CAPABILITY_MODE; 2195 if (sc->sc_dma_ok) { 2196 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2197 switch (sc->sc_pp->ide_product) { 2198 case PCI_PRODUCT_CMDTECH_649: 2199 case PCI_PRODUCT_CMDTECH_648: 2200 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2201 sc->sc_wdcdev.UDMA_cap = 4; 2202 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2203 break; 2204 case PCI_PRODUCT_CMDTECH_646: 2205 if (rev >= CMD0646U2_REV) { 2206 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2207 sc->sc_wdcdev.UDMA_cap = 2; 2208 } 2209 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2210 break; 2211 default: 2212 sc->sc_wdcdev.irqack = pciide_irqack; 2213 } 2214 } 2215 2216 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2217 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2218 sc->sc_wdcdev.PIO_cap = 4; 2219 sc->sc_wdcdev.DMA_cap = 2; 2220 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2221 2222 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2223 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2224 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2225 DEBUG_PROBE); 2226 2227 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2228 cp = &sc->pciide_channels[channel]; 2229 cmd_channel_map(pa, sc, channel); 2230 if (cp->hw_ok == 0) 2231 continue; 2232 cmd0643_9_setup_channel(&cp->wdc_channel); 2233 } 2234 /* note - this also make sure we clear the irq disable and reset bits */ 2235 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2236 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2237 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2238 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2239 DEBUG_PROBE); 2240 } 2241 2242 void 2243 cmd0643_9_setup_channel(chp) 2244 struct channel_softc *chp; 2245 { 2246 struct ata_drive_datas *drvp; 2247 u_int8_t tim; 2248 u_int32_t idedma_ctl, udma_reg; 2249 int drive; 2250 struct pciide_channel *cp = (struct pciide_channel*)chp; 2251 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2252 2253 idedma_ctl = 0; 2254 /* setup DMA if needed */ 2255 pciide_channel_dma_setup(cp); 2256 2257 for (drive = 0; drive < 2; drive++) { 2258 drvp = &chp->ch_drive[drive]; 2259 /* If no drive, skip */ 2260 if ((drvp->drive_flags & DRIVE) == 0) 2261 continue; 2262 /* add timing values, setup DMA if needed */ 2263 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2264 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2265 if (drvp->drive_flags & DRIVE_UDMA) { 2266 /* UltraDMA on a 646U2, 0648 or 0649 */ 2267 udma_reg = pciide_pci_read(sc->sc_pc, 2268 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2269 if (drvp->UDMA_mode > 2 && 2270 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2271 CMD_BICSR) & 2272 CMD_BICSR_80(chp->channel)) == 0) 2273 drvp->UDMA_mode = 2; 2274 if (drvp->UDMA_mode > 2) 2275 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2276 else if (sc->sc_wdcdev.UDMA_cap > 2) 2277 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2278 udma_reg |= CMD_UDMATIM_UDMA(drive); 2279 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2280 CMD_UDMATIM_TIM_OFF(drive)); 2281 udma_reg |= 2282 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2283 CMD_UDMATIM_TIM_OFF(drive)); 2284 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2285 CMD_UDMATIM(chp->channel), udma_reg); 2286 } else { 2287 /* 2288 * use Multiword DMA. 2289 * Timings will be used for both PIO and DMA, 2290 * so adjust DMA mode if needed 2291 * if we have a 0646U2/8/9, turn off UDMA 2292 */ 2293 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2294 udma_reg = pciide_pci_read(sc->sc_pc, 2295 sc->sc_tag, 2296 CMD_UDMATIM(chp->channel)); 2297 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2298 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2299 CMD_UDMATIM(chp->channel), 2300 udma_reg); 2301 } 2302 if (drvp->PIO_mode >= 3 && 2303 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2304 drvp->DMA_mode = drvp->PIO_mode - 2; 2305 } 2306 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2307 } 2308 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2309 } 2310 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2311 CMD_DATA_TIM(chp->channel, drive), tim); 2312 } 2313 if (idedma_ctl != 0) { 2314 /* Add software bits in status register */ 2315 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2316 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2317 idedma_ctl); 2318 } 2319 pciide_print_modes(cp); 2320 } 2321 2322 void 2323 cmd646_9_irqack(chp) 2324 struct channel_softc *chp; 2325 { 2326 u_int32_t priirq, secirq; 2327 struct pciide_channel *cp = (struct pciide_channel*)chp; 2328 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2329 2330 if (chp->channel == 0) { 2331 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2332 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2333 } else { 2334 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2335 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2336 } 2337 pciide_irqack(chp); 2338 } 2339 2340 void 2341 cy693_chip_map(sc, pa) 2342 struct pciide_softc *sc; 2343 struct pci_attach_args *pa; 2344 { 2345 struct pciide_channel *cp; 2346 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2347 bus_size_t cmdsize, ctlsize; 2348 2349 if (pciide_chipen(sc, pa) == 0) 2350 return; 2351 /* 2352 * this chip has 2 PCI IDE functions, one for primary and one for 2353 * secondary. So we need to call pciide_mapregs_compat() with 2354 * the real channel 2355 */ 2356 if (pa->pa_function == 1) { 2357 sc->sc_cy_compatchan = 0; 2358 } else if (pa->pa_function == 2) { 2359 sc->sc_cy_compatchan = 1; 2360 } else { 2361 printf("%s: unexpected PCI function %d\n", 2362 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2363 return; 2364 } 2365 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2366 printf("%s: bus-master DMA support present", 2367 sc->sc_wdcdev.sc_dev.dv_xname); 2368 pciide_mapreg_dma(sc, pa); 2369 } else { 2370 printf("%s: hardware does not support DMA", 2371 sc->sc_wdcdev.sc_dev.dv_xname); 2372 sc->sc_dma_ok = 0; 2373 } 2374 printf("\n"); 2375 2376 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2377 if (sc->sc_cy_handle == NULL) { 2378 printf("%s: unable to map hyperCache control registers\n", 2379 sc->sc_wdcdev.sc_dev.dv_xname); 2380 sc->sc_dma_ok = 0; 2381 } 2382 2383 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2384 WDC_CAPABILITY_MODE; 2385 if (sc->sc_dma_ok) { 2386 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2387 sc->sc_wdcdev.irqack = pciide_irqack; 2388 } 2389 sc->sc_wdcdev.PIO_cap = 4; 2390 sc->sc_wdcdev.DMA_cap = 2; 2391 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2392 2393 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2394 sc->sc_wdcdev.nchannels = 1; 2395 2396 /* Only one channel for this chip; if we are here it's enabled */ 2397 cp = &sc->pciide_channels[0]; 2398 sc->wdc_chanarray[0] = &cp->wdc_channel; 2399 cp->name = PCIIDE_CHANNEL_NAME(0); 2400 cp->wdc_channel.channel = 0; 2401 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2402 cp->wdc_channel.ch_queue = 2403 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2404 if (cp->wdc_channel.ch_queue == NULL) { 2405 printf("%s primary channel: " 2406 "can't allocate memory for command queue", 2407 sc->sc_wdcdev.sc_dev.dv_xname); 2408 return; 2409 } 2410 printf("%s: primary channel %s to ", 2411 sc->sc_wdcdev.sc_dev.dv_xname, 2412 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2413 "configured" : "wired"); 2414 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2415 printf("native-PCI"); 2416 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2417 pciide_pci_intr); 2418 } else { 2419 printf("compatibility"); 2420 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2421 &cmdsize, &ctlsize); 2422 } 2423 printf(" mode\n"); 2424 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2425 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2426 wdcattach(&cp->wdc_channel); 2427 if (pciide_chan_candisable(cp)) { 2428 pci_conf_write(sc->sc_pc, sc->sc_tag, 2429 PCI_COMMAND_STATUS_REG, 0); 2430 } 2431 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2432 if (cp->hw_ok == 0) 2433 return; 2434 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2435 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2436 cy693_setup_channel(&cp->wdc_channel); 2437 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2438 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2439 } 2440 2441 void 2442 cy693_setup_channel(chp) 2443 struct channel_softc *chp; 2444 { 2445 struct ata_drive_datas *drvp; 2446 int drive; 2447 u_int32_t cy_cmd_ctrl; 2448 u_int32_t idedma_ctl; 2449 struct pciide_channel *cp = (struct pciide_channel*)chp; 2450 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2451 int dma_mode = -1; 2452 2453 cy_cmd_ctrl = idedma_ctl = 0; 2454 2455 /* setup DMA if needed */ 2456 pciide_channel_dma_setup(cp); 2457 2458 for (drive = 0; drive < 2; drive++) { 2459 drvp = &chp->ch_drive[drive]; 2460 /* If no drive, skip */ 2461 if ((drvp->drive_flags & DRIVE) == 0) 2462 continue; 2463 /* add timing values, setup DMA if needed */ 2464 if (drvp->drive_flags & DRIVE_DMA) { 2465 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2466 /* use Multiword DMA */ 2467 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2468 dma_mode = drvp->DMA_mode; 2469 } 2470 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2471 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2472 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2473 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2474 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2475 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2476 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2477 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2478 } 2479 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2480 chp->ch_drive[0].DMA_mode = dma_mode; 2481 chp->ch_drive[1].DMA_mode = dma_mode; 2482 2483 if (dma_mode == -1) 2484 dma_mode = 0; 2485 2486 if (sc->sc_cy_handle != NULL) { 2487 /* Note: `multiple' is implied. */ 2488 cy82c693_write(sc->sc_cy_handle, 2489 (sc->sc_cy_compatchan == 0) ? 2490 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2491 } 2492 2493 pciide_print_modes(cp); 2494 2495 if (idedma_ctl != 0) { 2496 /* Add software bits in status register */ 2497 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2498 IDEDMA_CTL, idedma_ctl); 2499 } 2500 } 2501 2502 void 2503 sis_chip_map(sc, pa) 2504 struct pciide_softc *sc; 2505 struct pci_attach_args *pa; 2506 { 2507 struct pciide_channel *cp; 2508 int channel; 2509 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2510 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2511 pcireg_t rev = PCI_REVISION(pa->pa_class); 2512 bus_size_t cmdsize, ctlsize; 2513 2514 if (pciide_chipen(sc, pa) == 0) 2515 return; 2516 printf("%s: bus-master DMA support present", 2517 sc->sc_wdcdev.sc_dev.dv_xname); 2518 pciide_mapreg_dma(sc, pa); 2519 printf("\n"); 2520 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2521 WDC_CAPABILITY_MODE; 2522 if (sc->sc_dma_ok) { 2523 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2524 sc->sc_wdcdev.irqack = pciide_irqack; 2525 if (rev >= 0xd0) 2526 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2527 } 2528 2529 sc->sc_wdcdev.PIO_cap = 4; 2530 sc->sc_wdcdev.DMA_cap = 2; 2531 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2532 sc->sc_wdcdev.UDMA_cap = 2; 2533 sc->sc_wdcdev.set_modes = sis_setup_channel; 2534 2535 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2536 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2537 2538 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2539 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2540 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2541 2542 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2543 cp = &sc->pciide_channels[channel]; 2544 if (pciide_chansetup(sc, channel, interface) == 0) 2545 continue; 2546 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2547 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2548 printf("%s: %s channel ignored (disabled)\n", 2549 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2550 continue; 2551 } 2552 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2553 pciide_pci_intr); 2554 if (cp->hw_ok == 0) 2555 continue; 2556 if (pciide_chan_candisable(cp)) { 2557 if (channel == 0) 2558 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2559 else 2560 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2561 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2562 sis_ctr0); 2563 } 2564 pciide_map_compat_intr(pa, cp, channel, interface); 2565 if (cp->hw_ok == 0) 2566 continue; 2567 sis_setup_channel(&cp->wdc_channel); 2568 } 2569 } 2570 2571 void 2572 sis_setup_channel(chp) 2573 struct channel_softc *chp; 2574 { 2575 struct ata_drive_datas *drvp; 2576 int drive; 2577 u_int32_t sis_tim; 2578 u_int32_t idedma_ctl; 2579 struct pciide_channel *cp = (struct pciide_channel*)chp; 2580 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2581 2582 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2583 "channel %d 0x%x\n", chp->channel, 2584 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2585 DEBUG_PROBE); 2586 sis_tim = 0; 2587 idedma_ctl = 0; 2588 /* setup DMA if needed */ 2589 pciide_channel_dma_setup(cp); 2590 2591 for (drive = 0; drive < 2; drive++) { 2592 drvp = &chp->ch_drive[drive]; 2593 /* If no drive, skip */ 2594 if ((drvp->drive_flags & DRIVE) == 0) 2595 continue; 2596 /* add timing values, setup DMA if needed */ 2597 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2598 (drvp->drive_flags & DRIVE_UDMA) == 0) 2599 goto pio; 2600 2601 if (drvp->drive_flags & DRIVE_UDMA) { 2602 /* use Ultra/DMA */ 2603 drvp->drive_flags &= ~DRIVE_DMA; 2604 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2605 SIS_TIM_UDMA_TIME_OFF(drive); 2606 sis_tim |= SIS_TIM_UDMA_EN(drive); 2607 } else { 2608 /* 2609 * use Multiword DMA 2610 * Timings will be used for both PIO and DMA, 2611 * so adjust DMA mode if needed 2612 */ 2613 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2614 drvp->PIO_mode = drvp->DMA_mode + 2; 2615 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2616 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2617 drvp->PIO_mode - 2 : 0; 2618 if (drvp->DMA_mode == 0) 2619 drvp->PIO_mode = 0; 2620 } 2621 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2622 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2623 SIS_TIM_ACT_OFF(drive); 2624 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2625 SIS_TIM_REC_OFF(drive); 2626 } 2627 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2628 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2629 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2630 if (idedma_ctl != 0) { 2631 /* Add software bits in status register */ 2632 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2633 IDEDMA_CTL, idedma_ctl); 2634 } 2635 pciide_print_modes(cp); 2636 } 2637 2638 void 2639 acer_chip_map(sc, pa) 2640 struct pciide_softc *sc; 2641 struct pci_attach_args *pa; 2642 { 2643 struct pciide_channel *cp; 2644 int channel; 2645 pcireg_t cr, interface; 2646 bus_size_t cmdsize, ctlsize; 2647 2648 if (pciide_chipen(sc, pa) == 0) 2649 return; 2650 printf("%s: bus-master DMA support present", 2651 sc->sc_wdcdev.sc_dev.dv_xname); 2652 pciide_mapreg_dma(sc, pa); 2653 printf("\n"); 2654 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2655 WDC_CAPABILITY_MODE; 2656 if (sc->sc_dma_ok) { 2657 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2658 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2659 sc->sc_wdcdev.irqack = pciide_irqack; 2660 } 2661 2662 sc->sc_wdcdev.PIO_cap = 4; 2663 sc->sc_wdcdev.DMA_cap = 2; 2664 sc->sc_wdcdev.UDMA_cap = 2; 2665 sc->sc_wdcdev.set_modes = acer_setup_channel; 2666 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2667 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2668 2669 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2670 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2671 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2672 2673 /* Enable "microsoft register bits" R/W. */ 2674 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2675 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2676 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2677 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2678 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2679 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2680 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2681 ~ACER_CHANSTATUSREGS_RO); 2682 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2683 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2684 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2685 /* Don't use cr, re-read the real register content instead */ 2686 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2687 PCI_CLASS_REG)); 2688 2689 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2690 cp = &sc->pciide_channels[channel]; 2691 if (pciide_chansetup(sc, channel, interface) == 0) 2692 continue; 2693 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2694 printf("%s: %s channel ignored (disabled)\n", 2695 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2696 continue; 2697 } 2698 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2699 acer_pci_intr); 2700 if (cp->hw_ok == 0) 2701 continue; 2702 if (pciide_chan_candisable(cp)) { 2703 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2704 pci_conf_write(sc->sc_pc, sc->sc_tag, 2705 PCI_CLASS_REG, cr); 2706 } 2707 pciide_map_compat_intr(pa, cp, channel, interface); 2708 acer_setup_channel(&cp->wdc_channel); 2709 } 2710 } 2711 2712 void 2713 acer_setup_channel(chp) 2714 struct channel_softc *chp; 2715 { 2716 struct ata_drive_datas *drvp; 2717 int drive; 2718 u_int32_t acer_fifo_udma; 2719 u_int32_t idedma_ctl; 2720 struct pciide_channel *cp = (struct pciide_channel*)chp; 2721 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2722 2723 idedma_ctl = 0; 2724 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2725 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2726 acer_fifo_udma), DEBUG_PROBE); 2727 /* setup DMA if needed */ 2728 pciide_channel_dma_setup(cp); 2729 2730 for (drive = 0; drive < 2; drive++) { 2731 drvp = &chp->ch_drive[drive]; 2732 /* If no drive, skip */ 2733 if ((drvp->drive_flags & DRIVE) == 0) 2734 continue; 2735 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2736 "channel %d drive %d 0x%x\n", chp->channel, drive, 2737 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2738 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2739 /* clear FIFO/DMA mode */ 2740 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2741 ACER_UDMA_EN(chp->channel, drive) | 2742 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2743 2744 /* add timing values, setup DMA if needed */ 2745 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2746 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2747 acer_fifo_udma |= 2748 ACER_FTH_OPL(chp->channel, drive, 0x1); 2749 goto pio; 2750 } 2751 2752 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2753 if (drvp->drive_flags & DRIVE_UDMA) { 2754 /* use Ultra/DMA */ 2755 drvp->drive_flags &= ~DRIVE_DMA; 2756 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2757 acer_fifo_udma |= 2758 ACER_UDMA_TIM(chp->channel, drive, 2759 acer_udma[drvp->UDMA_mode]); 2760 } else { 2761 /* 2762 * use Multiword DMA 2763 * Timings will be used for both PIO and DMA, 2764 * so adjust DMA mode if needed 2765 */ 2766 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2767 drvp->PIO_mode = drvp->DMA_mode + 2; 2768 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2769 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2770 drvp->PIO_mode - 2 : 0; 2771 if (drvp->DMA_mode == 0) 2772 drvp->PIO_mode = 0; 2773 } 2774 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2775 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2776 ACER_IDETIM(chp->channel, drive), 2777 acer_pio[drvp->PIO_mode]); 2778 } 2779 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2780 acer_fifo_udma), DEBUG_PROBE); 2781 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2782 if (idedma_ctl != 0) { 2783 /* Add software bits in status register */ 2784 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2785 IDEDMA_CTL, idedma_ctl); 2786 } 2787 pciide_print_modes(cp); 2788 } 2789 2790 int 2791 acer_pci_intr(arg) 2792 void *arg; 2793 { 2794 struct pciide_softc *sc = arg; 2795 struct pciide_channel *cp; 2796 struct channel_softc *wdc_cp; 2797 int i, rv, crv; 2798 u_int32_t chids; 2799 2800 rv = 0; 2801 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2802 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2803 cp = &sc->pciide_channels[i]; 2804 wdc_cp = &cp->wdc_channel; 2805 /* If a compat channel skip. */ 2806 if (cp->compat) 2807 continue; 2808 if (chids & ACER_CHIDS_INT(i)) { 2809 crv = wdcintr(wdc_cp); 2810 if (crv == 0) 2811 printf("%s:%d: bogus intr\n", 2812 sc->sc_wdcdev.sc_dev.dv_xname, i); 2813 else 2814 rv = 1; 2815 } 2816 } 2817 return rv; 2818 } 2819 2820 void 2821 hpt_chip_map(sc, pa) 2822 struct pciide_softc *sc; 2823 struct pci_attach_args *pa; 2824 { 2825 struct pciide_channel *cp; 2826 int i, compatchan, revision; 2827 pcireg_t interface; 2828 bus_size_t cmdsize, ctlsize; 2829 2830 if (pciide_chipen(sc, pa) == 0) 2831 return; 2832 revision = PCI_REVISION(pa->pa_class); 2833 2834 /* 2835 * when the chip is in native mode it identifies itself as a 2836 * 'misc mass storage'. Fake interface in this case. 2837 */ 2838 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2839 interface = PCI_INTERFACE(pa->pa_class); 2840 } else { 2841 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2842 PCIIDE_INTERFACE_PCI(0); 2843 if (revision == HPT370_REV) 2844 interface |= PCIIDE_INTERFACE_PCI(1); 2845 } 2846 2847 printf("%s: bus-master DMA support present", 2848 sc->sc_wdcdev.sc_dev.dv_xname); 2849 pciide_mapreg_dma(sc, pa); 2850 printf("\n"); 2851 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2852 WDC_CAPABILITY_MODE; 2853 if (sc->sc_dma_ok) { 2854 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2855 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2856 sc->sc_wdcdev.irqack = pciide_irqack; 2857 } 2858 sc->sc_wdcdev.PIO_cap = 4; 2859 sc->sc_wdcdev.DMA_cap = 2; 2860 sc->sc_wdcdev.UDMA_cap = 4; 2861 2862 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2863 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2864 if (revision == HPT366_REV) { 2865 /* 2866 * The 366 has 2 PCI IDE functions, one for primary and one 2867 * for secondary. So we need to call pciide_mapregs_compat() 2868 * with the real channel 2869 */ 2870 if (pa->pa_function == 0) { 2871 compatchan = 0; 2872 } else if (pa->pa_function == 1) { 2873 compatchan = 1; 2874 } else { 2875 printf("%s: unexpected PCI function %d\n", 2876 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2877 return; 2878 } 2879 sc->sc_wdcdev.nchannels = 1; 2880 } else { 2881 sc->sc_wdcdev.nchannels = 2; 2882 } 2883 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2884 cp = &sc->pciide_channels[i]; 2885 if (sc->sc_wdcdev.nchannels > 1) { 2886 compatchan = i; 2887 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2888 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2889 printf("%s: %s channel ignored (disabled)\n", 2890 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2891 continue; 2892 } 2893 } 2894 if (pciide_chansetup(sc, i, interface) == 0) 2895 continue; 2896 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2897 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2898 &ctlsize, hpt_pci_intr); 2899 } else { 2900 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2901 &cmdsize, &ctlsize); 2902 } 2903 if (cp->hw_ok == 0) 2904 return; 2905 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2906 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2907 wdcattach(&cp->wdc_channel); 2908 hpt_setup_channel(&cp->wdc_channel); 2909 } 2910 if (revision == HPT370_REV) { 2911 /* 2912 * HPT370_REV has a bit to disable interrupts, make sure 2913 * to clear it 2914 */ 2915 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 2916 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 2917 ~HPT_CSEL_IRQDIS); 2918 } 2919 return; 2920 } 2921 2922 2923 void 2924 hpt_setup_channel(chp) 2925 struct channel_softc *chp; 2926 { 2927 struct ata_drive_datas *drvp; 2928 int drive; 2929 int cable; 2930 u_int32_t before, after; 2931 u_int32_t idedma_ctl; 2932 struct pciide_channel *cp = (struct pciide_channel*)chp; 2933 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2934 2935 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 2936 2937 /* setup DMA if needed */ 2938 pciide_channel_dma_setup(cp); 2939 2940 idedma_ctl = 0; 2941 2942 /* Per drive settings */ 2943 for (drive = 0; drive < 2; drive++) { 2944 drvp = &chp->ch_drive[drive]; 2945 /* If no drive, skip */ 2946 if ((drvp->drive_flags & DRIVE) == 0) 2947 continue; 2948 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 2949 HPT_IDETIM(chp->channel, drive)); 2950 2951 /* add timing values, setup DMA if needed */ 2952 if (drvp->drive_flags & DRIVE_UDMA) { 2953 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 2954 drvp->UDMA_mode > 2) 2955 drvp->UDMA_mode = 2; 2956 after = (sc->sc_wdcdev.nchannels == 2) ? 2957 hpt370_udma[drvp->UDMA_mode] : 2958 hpt366_udma[drvp->UDMA_mode]; 2959 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2960 } else if (drvp->drive_flags & DRIVE_DMA) { 2961 /* 2962 * use Multiword DMA. 2963 * Timings will be used for both PIO and DMA, so adjust 2964 * DMA mode if needed 2965 */ 2966 if (drvp->PIO_mode >= 3 && 2967 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2968 drvp->DMA_mode = drvp->PIO_mode - 2; 2969 } 2970 after = (sc->sc_wdcdev.nchannels == 2) ? 2971 hpt370_dma[drvp->DMA_mode] : 2972 hpt366_dma[drvp->DMA_mode]; 2973 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2974 } else { 2975 /* PIO only */ 2976 after = (sc->sc_wdcdev.nchannels == 2) ? 2977 hpt370_pio[drvp->PIO_mode] : 2978 hpt366_pio[drvp->PIO_mode]; 2979 } 2980 pci_conf_write(sc->sc_pc, sc->sc_tag, 2981 HPT_IDETIM(chp->channel, drive), after); 2982 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 2983 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 2984 after, before), DEBUG_PROBE); 2985 } 2986 if (idedma_ctl != 0) { 2987 /* Add software bits in status register */ 2988 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2989 IDEDMA_CTL, idedma_ctl); 2990 } 2991 pciide_print_modes(cp); 2992 } 2993 2994 int 2995 hpt_pci_intr(arg) 2996 void *arg; 2997 { 2998 struct pciide_softc *sc = arg; 2999 struct pciide_channel *cp; 3000 struct channel_softc *wdc_cp; 3001 int rv = 0; 3002 int dmastat, i, crv; 3003 3004 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3005 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3006 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3007 if((dmastat & IDEDMA_CTL_INTR) == 0) 3008 continue; 3009 cp = &sc->pciide_channels[i]; 3010 wdc_cp = &cp->wdc_channel; 3011 crv = wdcintr(wdc_cp); 3012 if (crv == 0) { 3013 printf("%s:%d: bogus intr\n", 3014 sc->sc_wdcdev.sc_dev.dv_xname, i); 3015 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3016 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3017 } else 3018 rv = 1; 3019 } 3020 return rv; 3021 } 3022 3023 3024 /* A macro to test product */ 3025 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 3026 3027 void 3028 pdc202xx_chip_map(sc, pa) 3029 struct pciide_softc *sc; 3030 struct pci_attach_args *pa; 3031 { 3032 struct pciide_channel *cp; 3033 int channel; 3034 pcireg_t interface, st, mode; 3035 bus_size_t cmdsize, ctlsize; 3036 3037 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3038 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3039 DEBUG_PROBE); 3040 if (pciide_chipen(sc, pa) == 0) 3041 return; 3042 3043 /* turn off RAID mode */ 3044 st &= ~PDC2xx_STATE_IDERAID; 3045 3046 /* 3047 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3048 * mode. We have to fake interface 3049 */ 3050 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3051 if (st & PDC2xx_STATE_NATIVE) 3052 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3053 3054 printf("%s: bus-master DMA support present", 3055 sc->sc_wdcdev.sc_dev.dv_xname); 3056 pciide_mapreg_dma(sc, pa); 3057 printf("\n"); 3058 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3059 WDC_CAPABILITY_MODE; 3060 if (sc->sc_dma_ok) { 3061 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3062 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3063 sc->sc_wdcdev.irqack = pciide_irqack; 3064 } 3065 sc->sc_wdcdev.PIO_cap = 4; 3066 sc->sc_wdcdev.DMA_cap = 2; 3067 if (PDC_IS_262(sc)) 3068 sc->sc_wdcdev.UDMA_cap = 4; 3069 else 3070 sc->sc_wdcdev.UDMA_cap = 2; 3071 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3072 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3073 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3074 3075 /* setup failsafe defaults */ 3076 mode = 0; 3077 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3078 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3079 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3080 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3081 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3082 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3083 "initial timings 0x%x, now 0x%x\n", channel, 3084 pci_conf_read(sc->sc_pc, sc->sc_tag, 3085 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3086 DEBUG_PROBE); 3087 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3088 mode | PDC2xx_TIM_IORDYp); 3089 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3090 "initial timings 0x%x, now 0x%x\n", channel, 3091 pci_conf_read(sc->sc_pc, sc->sc_tag, 3092 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3093 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3094 mode); 3095 } 3096 3097 mode = PDC2xx_SCR_DMA; 3098 if (PDC_IS_262(sc)) { 3099 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3100 } else { 3101 /* the BIOS set it up this way */ 3102 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3103 } 3104 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3105 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3106 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3107 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3108 DEBUG_PROBE); 3109 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3110 3111 /* controller initial state register is OK even without BIOS */ 3112 /* Set DMA mode to IDE DMA compatibility */ 3113 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3114 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3115 DEBUG_PROBE); 3116 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3117 mode | 0x1); 3118 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3119 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3120 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3121 mode | 0x1); 3122 3123 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3124 cp = &sc->pciide_channels[channel]; 3125 if (pciide_chansetup(sc, channel, interface) == 0) 3126 continue; 3127 if ((st & (PDC_IS_262(sc) ? 3128 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3129 printf("%s: %s channel ignored (disabled)\n", 3130 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3131 continue; 3132 } 3133 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3134 pdc202xx_pci_intr); 3135 if (cp->hw_ok == 0) 3136 continue; 3137 if (pciide_chan_candisable(cp)) 3138 st &= ~(PDC_IS_262(sc) ? 3139 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3140 pciide_map_compat_intr(pa, cp, channel, interface); 3141 pdc202xx_setup_channel(&cp->wdc_channel); 3142 } 3143 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3144 DEBUG_PROBE); 3145 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3146 return; 3147 } 3148 3149 void 3150 pdc202xx_setup_channel(chp) 3151 struct channel_softc *chp; 3152 { 3153 struct ata_drive_datas *drvp; 3154 int drive; 3155 pcireg_t mode, st; 3156 u_int32_t idedma_ctl, scr, atapi; 3157 struct pciide_channel *cp = (struct pciide_channel*)chp; 3158 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3159 int channel = chp->channel; 3160 3161 /* setup DMA if needed */ 3162 pciide_channel_dma_setup(cp); 3163 3164 idedma_ctl = 0; 3165 3166 /* Per channel settings */ 3167 if (PDC_IS_262(sc)) { 3168 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3169 PDC262_U66); 3170 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3171 /* Trimm UDMA mode */ 3172 if ((st & PDC262_STATE_80P(channel)) != 0 || 3173 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3174 chp->ch_drive[0].UDMA_mode <= 2) || 3175 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3176 chp->ch_drive[1].UDMA_mode <= 2)) { 3177 if (chp->ch_drive[0].UDMA_mode > 2) 3178 chp->ch_drive[0].UDMA_mode = 2; 3179 if (chp->ch_drive[1].UDMA_mode > 2) 3180 chp->ch_drive[1].UDMA_mode = 2; 3181 } 3182 /* Set U66 if needed */ 3183 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3184 chp->ch_drive[0].UDMA_mode > 2) || 3185 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3186 chp->ch_drive[1].UDMA_mode > 2)) 3187 scr |= PDC262_U66_EN(channel); 3188 else 3189 scr &= ~PDC262_U66_EN(channel); 3190 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3191 PDC262_U66, scr); 3192 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3193 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3194 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3195 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3196 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3197 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3198 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3199 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3200 atapi = 0; 3201 else 3202 atapi = PDC262_ATAPI_UDMA; 3203 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3204 PDC262_ATAPI(channel), atapi); 3205 } 3206 } 3207 for (drive = 0; drive < 2; drive++) { 3208 drvp = &chp->ch_drive[drive]; 3209 /* If no drive, skip */ 3210 if ((drvp->drive_flags & DRIVE) == 0) 3211 continue; 3212 mode = 0; 3213 if (drvp->drive_flags & DRIVE_UDMA) { 3214 mode = PDC2xx_TIM_SET_MB(mode, 3215 pdc2xx_udma_mb[drvp->UDMA_mode]); 3216 mode = PDC2xx_TIM_SET_MC(mode, 3217 pdc2xx_udma_mc[drvp->UDMA_mode]); 3218 drvp->drive_flags &= ~DRIVE_DMA; 3219 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3220 } else if (drvp->drive_flags & DRIVE_DMA) { 3221 mode = PDC2xx_TIM_SET_MB(mode, 3222 pdc2xx_dma_mb[drvp->DMA_mode]); 3223 mode = PDC2xx_TIM_SET_MC(mode, 3224 pdc2xx_dma_mc[drvp->DMA_mode]); 3225 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3226 } else { 3227 mode = PDC2xx_TIM_SET_MB(mode, 3228 pdc2xx_dma_mb[0]); 3229 mode = PDC2xx_TIM_SET_MC(mode, 3230 pdc2xx_dma_mc[0]); 3231 } 3232 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3233 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3234 if (drvp->drive_flags & DRIVE_ATA) 3235 mode |= PDC2xx_TIM_PRE; 3236 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3237 if (drvp->PIO_mode >= 3) { 3238 mode |= PDC2xx_TIM_IORDY; 3239 if (drive == 0) 3240 mode |= PDC2xx_TIM_IORDYp; 3241 } 3242 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3243 "timings 0x%x\n", 3244 sc->sc_wdcdev.sc_dev.dv_xname, 3245 chp->channel, drive, mode), DEBUG_PROBE); 3246 pci_conf_write(sc->sc_pc, sc->sc_tag, 3247 PDC2xx_TIM(chp->channel, drive), mode); 3248 } 3249 if (idedma_ctl != 0) { 3250 /* Add software bits in status register */ 3251 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3252 IDEDMA_CTL, idedma_ctl); 3253 } 3254 pciide_print_modes(cp); 3255 } 3256 3257 int 3258 pdc202xx_pci_intr(arg) 3259 void *arg; 3260 { 3261 struct pciide_softc *sc = arg; 3262 struct pciide_channel *cp; 3263 struct channel_softc *wdc_cp; 3264 int i, rv, crv; 3265 u_int32_t scr; 3266 3267 rv = 0; 3268 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3269 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3270 cp = &sc->pciide_channels[i]; 3271 wdc_cp = &cp->wdc_channel; 3272 /* If a compat channel skip. */ 3273 if (cp->compat) 3274 continue; 3275 if (scr & PDC2xx_SCR_INT(i)) { 3276 crv = wdcintr(wdc_cp); 3277 if (crv == 0) 3278 printf("%s:%d: bogus intr\n", 3279 sc->sc_wdcdev.sc_dev.dv_xname, i); 3280 else 3281 rv = 1; 3282 } 3283 } 3284 return rv; 3285 } 3286 3287 void 3288 opti_chip_map(sc, pa) 3289 struct pciide_softc *sc; 3290 struct pci_attach_args *pa; 3291 { 3292 struct pciide_channel *cp; 3293 bus_size_t cmdsize, ctlsize; 3294 pcireg_t interface; 3295 u_int8_t init_ctrl; 3296 int channel; 3297 3298 if (pciide_chipen(sc, pa) == 0) 3299 return; 3300 printf("%s: bus-master DMA support present", 3301 sc->sc_wdcdev.sc_dev.dv_xname); 3302 pciide_mapreg_dma(sc, pa); 3303 printf("\n"); 3304 3305 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3306 WDC_CAPABILITY_MODE; 3307 sc->sc_wdcdev.PIO_cap = 4; 3308 if (sc->sc_dma_ok) { 3309 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3310 sc->sc_wdcdev.irqack = pciide_irqack; 3311 sc->sc_wdcdev.DMA_cap = 2; 3312 } 3313 sc->sc_wdcdev.set_modes = opti_setup_channel; 3314 3315 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3316 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3317 3318 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3319 OPTI_REG_INIT_CONTROL); 3320 3321 interface = PCI_INTERFACE(pa->pa_class); 3322 3323 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3324 cp = &sc->pciide_channels[channel]; 3325 if (pciide_chansetup(sc, channel, interface) == 0) 3326 continue; 3327 if (channel == 1 && 3328 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3329 printf("%s: %s channel ignored (disabled)\n", 3330 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3331 continue; 3332 } 3333 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3334 pciide_pci_intr); 3335 if (cp->hw_ok == 0) 3336 continue; 3337 pciide_map_compat_intr(pa, cp, channel, interface); 3338 if (cp->hw_ok == 0) 3339 continue; 3340 opti_setup_channel(&cp->wdc_channel); 3341 } 3342 } 3343 3344 void 3345 opti_setup_channel(chp) 3346 struct channel_softc *chp; 3347 { 3348 struct ata_drive_datas *drvp; 3349 struct pciide_channel *cp = (struct pciide_channel*)chp; 3350 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3351 int drive, spd; 3352 int mode[2]; 3353 u_int8_t rv, mr; 3354 3355 /* 3356 * The `Delay' and `Address Setup Time' fields of the 3357 * Miscellaneous Register are always zero initially. 3358 */ 3359 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3360 mr &= ~(OPTI_MISC_DELAY_MASK | 3361 OPTI_MISC_ADDR_SETUP_MASK | 3362 OPTI_MISC_INDEX_MASK); 3363 3364 /* Prime the control register before setting timing values */ 3365 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3366 3367 /* Determine the clockrate of the PCIbus the chip is attached to */ 3368 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3369 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3370 3371 /* setup DMA if needed */ 3372 pciide_channel_dma_setup(cp); 3373 3374 for (drive = 0; drive < 2; drive++) { 3375 drvp = &chp->ch_drive[drive]; 3376 /* If no drive, skip */ 3377 if ((drvp->drive_flags & DRIVE) == 0) { 3378 mode[drive] = -1; 3379 continue; 3380 } 3381 3382 if ((drvp->drive_flags & DRIVE_DMA)) { 3383 /* 3384 * Timings will be used for both PIO and DMA, 3385 * so adjust DMA mode if needed 3386 */ 3387 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3388 drvp->PIO_mode = drvp->DMA_mode + 2; 3389 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3390 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3391 drvp->PIO_mode - 2 : 0; 3392 if (drvp->DMA_mode == 0) 3393 drvp->PIO_mode = 0; 3394 3395 mode[drive] = drvp->DMA_mode + 5; 3396 } else 3397 mode[drive] = drvp->PIO_mode; 3398 3399 if (drive && mode[0] >= 0 && 3400 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3401 /* 3402 * Can't have two drives using different values 3403 * for `Address Setup Time'. 3404 * Slow down the faster drive to compensate. 3405 */ 3406 int d = (opti_tim_as[spd][mode[0]] > 3407 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3408 3409 mode[d] = mode[1-d]; 3410 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3411 chp->ch_drive[d].DMA_mode = 0; 3412 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3413 } 3414 } 3415 3416 for (drive = 0; drive < 2; drive++) { 3417 int m; 3418 if ((m = mode[drive]) < 0) 3419 continue; 3420 3421 /* Set the Address Setup Time and select appropriate index */ 3422 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3423 rv |= OPTI_MISC_INDEX(drive); 3424 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3425 3426 /* Set the pulse width and recovery timing parameters */ 3427 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3428 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3429 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3430 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3431 3432 /* Set the Enhanced Mode register appropriately */ 3433 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3434 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3435 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3436 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3437 } 3438 3439 /* Finally, enable the timings */ 3440 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3441 3442 pciide_print_modes(cp); 3443 } 3444
Indexes created Thu Oct 02 10:09:58 GMT 2025