pciide.c revision 1.68.2.11
1 /* $NetBSD: pciide.c,v 1.68.2.11 2000/08/03 17:15:40 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <vm/vm.h> 102 #include <vm/vm_param.h> 103 #include <vm/vm_kern.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/cy82c693var.h> 121 122 #include "opt_pciide.h" 123 124 /* inlines for reading/writing 8-bit PCI registers */ 125 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 126 int)); 127 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 128 int, u_int8_t)); 129 130 static __inline u_int8_t 131 pciide_pci_read(pc, pa, reg) 132 pci_chipset_tag_t pc; 133 pcitag_t pa; 134 int reg; 135 { 136 137 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 138 ((reg & 0x03) * 8) & 0xff); 139 } 140 141 static __inline void 142 pciide_pci_write(pc, pa, reg, val) 143 pci_chipset_tag_t pc; 144 pcitag_t pa; 145 int reg; 146 u_int8_t val; 147 { 148 pcireg_t pcival; 149 150 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 151 pcival &= ~(0xff << ((reg & 0x03) * 8)); 152 pcival |= (val << ((reg & 0x03) * 8)); 153 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 154 } 155 156 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 157 158 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 void piix_setup_channel __P((struct channel_softc*)); 160 void piix3_4_setup_channel __P((struct channel_softc*)); 161 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 162 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 163 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 165 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 166 void amd756_setup_channel __P((struct channel_softc*)); 167 168 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 169 void apollo_setup_channel __P((struct channel_softc*)); 170 171 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 172 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 173 void cmd0643_9_setup_channel __P((struct channel_softc*)); 174 void cmd_channel_map __P((struct pci_attach_args *, 175 struct pciide_softc *, int)); 176 int cmd_pci_intr __P((void *)); 177 void cmd646_9_irqack __P((struct channel_softc *)); 178 179 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 180 void cy693_setup_channel __P((struct channel_softc*)); 181 182 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 183 void sis_setup_channel __P((struct channel_softc*)); 184 185 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 186 void acer_setup_channel __P((struct channel_softc*)); 187 int acer_pci_intr __P((void *)); 188 189 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 190 void pdc202xx_setup_channel __P((struct channel_softc*)); 191 int pdc202xx_pci_intr __P((void *)); 192 193 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 194 void opti_setup_channel __P((struct channel_softc*)); 195 196 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 197 void hpt_setup_channel __P((struct channel_softc*)); 198 int hpt_pci_intr __P((void *)); 199 200 void pciide_channel_dma_setup __P((struct pciide_channel *)); 201 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 202 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 203 void pciide_dma_start __P((void*, int, int)); 204 int pciide_dma_finish __P((void*, int, int, int)); 205 void pciide_irqack __P((struct channel_softc *)); 206 void pciide_print_modes __P((struct pciide_channel *)); 207 208 struct pciide_product_desc { 209 u_int32_t ide_product; 210 int ide_flags; 211 const char *ide_name; 212 /* map and setup chip, probe drives */ 213 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 214 }; 215 216 /* Flags for ide_flags */ 217 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 218 219 /* Default product description for devices not known from this controller */ 220 const struct pciide_product_desc default_product_desc = { 221 0, 222 0, 223 "Generic PCI IDE controller", 224 default_chip_map, 225 }; 226 227 const struct pciide_product_desc pciide_intel_products[] = { 228 { PCI_PRODUCT_INTEL_82092AA, 229 0, 230 "Intel 82092AA IDE controller", 231 default_chip_map, 232 }, 233 { PCI_PRODUCT_INTEL_82371FB_IDE, 234 0, 235 "Intel 82371FB IDE controller (PIIX)", 236 piix_chip_map, 237 }, 238 { PCI_PRODUCT_INTEL_82371SB_IDE, 239 0, 240 "Intel 82371SB IDE Interface (PIIX3)", 241 piix_chip_map, 242 }, 243 { PCI_PRODUCT_INTEL_82371AB_IDE, 244 0, 245 "Intel 82371AB IDE controller (PIIX4)", 246 piix_chip_map, 247 }, 248 { PCI_PRODUCT_INTEL_82801AA_IDE, 249 0, 250 "Intel 82801AA IDE Controller (ICH)", 251 piix_chip_map, 252 }, 253 { PCI_PRODUCT_INTEL_82801AB_IDE, 254 0, 255 "Intel 82801AB IDE Controller (ICH0)", 256 piix_chip_map, 257 }, 258 { 0, 259 0, 260 NULL, 261 } 262 }; 263 264 const struct pciide_product_desc pciide_amd_products[] = { 265 { PCI_PRODUCT_AMD_PBC756_IDE, 266 0, 267 "Advanced Micro Devices AMD756 IDE Controller", 268 amd756_chip_map 269 }, 270 { 0, 271 0, 272 NULL, 273 } 274 }; 275 276 const struct pciide_product_desc pciide_cmd_products[] = { 277 { PCI_PRODUCT_CMDTECH_640, 278 0, 279 "CMD Technology PCI0640", 280 cmd_chip_map 281 }, 282 { PCI_PRODUCT_CMDTECH_643, 283 0, 284 "CMD Technology PCI0643", 285 cmd0643_9_chip_map, 286 }, 287 { PCI_PRODUCT_CMDTECH_646, 288 0, 289 "CMD Technology PCI0646", 290 cmd0643_9_chip_map, 291 }, 292 { PCI_PRODUCT_CMDTECH_648, 293 IDE_PCI_CLASS_OVERRIDE, 294 "CMD Technology PCI0648", 295 cmd0643_9_chip_map, 296 }, 297 { PCI_PRODUCT_CMDTECH_649, 298 IDE_PCI_CLASS_OVERRIDE, 299 "CMD Technology PCI0649", 300 cmd0643_9_chip_map, 301 }, 302 { 0, 303 0, 304 NULL, 305 } 306 }; 307 308 const struct pciide_product_desc pciide_via_products[] = { 309 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 310 0, 311 "VIA Tech VT82C586 IDE Controller", 312 apollo_chip_map, 313 }, 314 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 315 0, 316 "VIA Tech VT82C586A IDE Controller", 317 apollo_chip_map, 318 }, 319 { 0, 320 0, 321 NULL, 322 } 323 }; 324 325 const struct pciide_product_desc pciide_cypress_products[] = { 326 { PCI_PRODUCT_CONTAQ_82C693, 327 0, 328 "Cypress 82C693 IDE Controller", 329 cy693_chip_map, 330 }, 331 { 0, 332 0, 333 NULL, 334 } 335 }; 336 337 const struct pciide_product_desc pciide_sis_products[] = { 338 { PCI_PRODUCT_SIS_5597_IDE, 339 0, 340 "Silicon Integrated System 5597/5598 IDE controller", 341 sis_chip_map, 342 }, 343 { 0, 344 0, 345 NULL, 346 } 347 }; 348 349 const struct pciide_product_desc pciide_acer_products[] = { 350 { PCI_PRODUCT_ALI_M5229, 351 0, 352 "Acer Labs M5229 UDMA IDE Controller", 353 acer_chip_map, 354 }, 355 { 0, 356 0, 357 NULL, 358 } 359 }; 360 361 const struct pciide_product_desc pciide_promise_products[] = { 362 { PCI_PRODUCT_PROMISE_ULTRA33, 363 IDE_PCI_CLASS_OVERRIDE, 364 "Promise Ultra33/ATA Bus Master IDE Accelerator", 365 pdc202xx_chip_map, 366 }, 367 { PCI_PRODUCT_PROMISE_ULTRA66, 368 IDE_PCI_CLASS_OVERRIDE, 369 "Promise Ultra66/ATA Bus Master IDE Accelerator", 370 pdc202xx_chip_map, 371 }, 372 { PCI_PRODUCT_PROMISE_ULTRA100, 373 IDE_PCI_CLASS_OVERRIDE, 374 "Promise Ultra100/ATA Bus Master IDE Accelerator", 375 pdc202xx_chip_map, 376 }, 377 { 0, 378 0, 379 NULL, 380 } 381 }; 382 383 const struct pciide_product_desc pciide_opti_products[] = { 384 { PCI_PRODUCT_OPTI_82C621, 385 0, 386 "OPTi 82c621 PCI IDE controller", 387 opti_chip_map, 388 }, 389 { PCI_PRODUCT_OPTI_82C568, 390 0, 391 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 392 opti_chip_map, 393 }, 394 { PCI_PRODUCT_OPTI_82D568, 395 0, 396 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 397 opti_chip_map, 398 }, 399 { 0, 400 0, 401 NULL, 402 } 403 }; 404 405 const struct pciide_product_desc pciide_triones_products[] = { 406 { PCI_PRODUCT_TRIONES_HPT366, 407 IDE_PCI_CLASS_OVERRIDE, 408 "Triones/Highpoint HPT366/370 IDE Controller", 409 hpt_chip_map, 410 }, 411 { 0, 412 0, 413 NULL, 414 } 415 }; 416 417 struct pciide_vendor_desc { 418 u_int32_t ide_vendor; 419 const struct pciide_product_desc *ide_products; 420 }; 421 422 const struct pciide_vendor_desc pciide_vendors[] = { 423 { PCI_VENDOR_INTEL, pciide_intel_products }, 424 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 425 { PCI_VENDOR_VIATECH, pciide_via_products }, 426 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 427 { PCI_VENDOR_SIS, pciide_sis_products }, 428 { PCI_VENDOR_ALI, pciide_acer_products }, 429 { PCI_VENDOR_PROMISE, pciide_promise_products }, 430 { PCI_VENDOR_AMD, pciide_amd_products }, 431 { PCI_VENDOR_OPTI, pciide_opti_products }, 432 { PCI_VENDOR_TRIONES, pciide_triones_products }, 433 { 0, NULL } 434 }; 435 436 /* options passed via the 'flags' config keyword */ 437 #define PCIIDE_OPTIONS_DMA 0x01 438 439 int pciide_match __P((struct device *, struct cfdata *, void *)); 440 void pciide_attach __P((struct device *, struct device *, void *)); 441 442 struct cfattach pciide_ca = { 443 sizeof(struct pciide_softc), pciide_match, pciide_attach 444 }; 445 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 446 int pciide_mapregs_compat __P(( struct pci_attach_args *, 447 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 448 int pciide_mapregs_native __P((struct pci_attach_args *, 449 struct pciide_channel *, bus_size_t *, bus_size_t *, 450 int (*pci_intr) __P((void *)))); 451 void pciide_mapreg_dma __P((struct pciide_softc *, 452 struct pci_attach_args *)); 453 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 454 void pciide_mapchan __P((struct pci_attach_args *, 455 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 456 int (*pci_intr) __P((void *)))); 457 int pciide_chan_candisable __P((struct pciide_channel *)); 458 void pciide_map_compat_intr __P(( struct pci_attach_args *, 459 struct pciide_channel *, int, int)); 460 int pciide_print __P((void *, const char *pnp)); 461 int pciide_compat_intr __P((void *)); 462 int pciide_pci_intr __P((void *)); 463 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 464 465 const struct pciide_product_desc * 466 pciide_lookup_product(id) 467 u_int32_t id; 468 { 469 const struct pciide_product_desc *pp; 470 const struct pciide_vendor_desc *vp; 471 472 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 473 if (PCI_VENDOR(id) == vp->ide_vendor) 474 break; 475 476 if ((pp = vp->ide_products) == NULL) 477 return NULL; 478 479 for (; pp->ide_name != NULL; pp++) 480 if (PCI_PRODUCT(id) == pp->ide_product) 481 break; 482 483 if (pp->ide_name == NULL) 484 return NULL; 485 return pp; 486 } 487 488 int 489 pciide_match(parent, match, aux) 490 struct device *parent; 491 struct cfdata *match; 492 void *aux; 493 { 494 struct pci_attach_args *pa = aux; 495 const struct pciide_product_desc *pp; 496 497 /* 498 * Check the ID register to see that it's a PCI IDE controller. 499 * If it is, we assume that we can deal with it; it _should_ 500 * work in a standardized way... 501 */ 502 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 503 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 504 return (1); 505 } 506 507 /* 508 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 509 * controllers. Let see if we can deal with it anyway. 510 */ 511 pp = pciide_lookup_product(pa->pa_id); 512 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 513 return (1); 514 } 515 516 return (0); 517 } 518 519 void 520 pciide_attach(parent, self, aux) 521 struct device *parent, *self; 522 void *aux; 523 { 524 struct pci_attach_args *pa = aux; 525 pci_chipset_tag_t pc = pa->pa_pc; 526 pcitag_t tag = pa->pa_tag; 527 struct pciide_softc *sc = (struct pciide_softc *)self; 528 pcireg_t csr; 529 char devinfo[256]; 530 const char *displaydev; 531 532 sc->sc_pp = pciide_lookup_product(pa->pa_id); 533 if (sc->sc_pp == NULL) { 534 sc->sc_pp = &default_product_desc; 535 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 536 displaydev = devinfo; 537 } else 538 displaydev = sc->sc_pp->ide_name; 539 540 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 541 542 sc->sc_pc = pa->pa_pc; 543 sc->sc_tag = pa->pa_tag; 544 #ifdef WDCDEBUG 545 if (wdcdebug_pciide_mask & DEBUG_PROBE) 546 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 547 #endif 548 sc->sc_pp->chip_map(sc, pa); 549 550 if (sc->sc_dma_ok) { 551 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 552 csr |= PCI_COMMAND_MASTER_ENABLE; 553 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 554 } 555 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 556 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 557 } 558 559 /* tell wether the chip is enabled or not */ 560 int 561 pciide_chipen(sc, pa) 562 struct pciide_softc *sc; 563 struct pci_attach_args *pa; 564 { 565 pcireg_t csr; 566 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 567 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 568 PCI_COMMAND_STATUS_REG); 569 printf("%s: device disabled (at %s)\n", 570 sc->sc_wdcdev.sc_dev.dv_xname, 571 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 572 "device" : "bridge"); 573 return 0; 574 } 575 return 1; 576 } 577 578 int 579 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 580 struct pci_attach_args *pa; 581 struct pciide_channel *cp; 582 int compatchan; 583 bus_size_t *cmdsizep, *ctlsizep; 584 { 585 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 586 struct channel_softc *wdc_cp = &cp->wdc_channel; 587 588 cp->compat = 1; 589 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 590 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 591 592 wdc_cp->cmd_iot = pa->pa_iot; 593 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 594 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 595 printf("%s: couldn't map %s channel cmd regs\n", 596 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 597 return (0); 598 } 599 600 wdc_cp->ctl_iot = pa->pa_iot; 601 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 602 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 603 printf("%s: couldn't map %s channel ctl regs\n", 604 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 605 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 606 PCIIDE_COMPAT_CMD_SIZE); 607 return (0); 608 } 609 610 return (1); 611 } 612 613 int 614 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 615 struct pci_attach_args * pa; 616 struct pciide_channel *cp; 617 bus_size_t *cmdsizep, *ctlsizep; 618 int (*pci_intr) __P((void *)); 619 { 620 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 621 struct channel_softc *wdc_cp = &cp->wdc_channel; 622 const char *intrstr; 623 pci_intr_handle_t intrhandle; 624 625 cp->compat = 0; 626 627 if (sc->sc_pci_ih == NULL) { 628 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 629 pa->pa_intrline, &intrhandle) != 0) { 630 printf("%s: couldn't map native-PCI interrupt\n", 631 sc->sc_wdcdev.sc_dev.dv_xname); 632 return 0; 633 } 634 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 635 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 636 intrhandle, IPL_BIO, pci_intr, sc); 637 if (sc->sc_pci_ih != NULL) { 638 printf("%s: using %s for native-PCI interrupt\n", 639 sc->sc_wdcdev.sc_dev.dv_xname, 640 intrstr ? intrstr : "unknown interrupt"); 641 } else { 642 printf("%s: couldn't establish native-PCI interrupt", 643 sc->sc_wdcdev.sc_dev.dv_xname); 644 if (intrstr != NULL) 645 printf(" at %s", intrstr); 646 printf("\n"); 647 return 0; 648 } 649 } 650 cp->ih = sc->sc_pci_ih; 651 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 652 PCI_MAPREG_TYPE_IO, 0, 653 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 654 printf("%s: couldn't map %s channel cmd regs\n", 655 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 656 return 0; 657 } 658 659 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 660 PCI_MAPREG_TYPE_IO, 0, 661 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 662 printf("%s: couldn't map %s channel ctl regs\n", 663 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 664 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 665 return 0; 666 } 667 return (1); 668 } 669 670 void 671 pciide_mapreg_dma(sc, pa) 672 struct pciide_softc *sc; 673 struct pci_attach_args *pa; 674 { 675 pcireg_t maptype; 676 677 /* 678 * Map DMA registers 679 * 680 * Note that sc_dma_ok is the right variable to test to see if 681 * DMA can be done. If the interface doesn't support DMA, 682 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 683 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 684 * non-zero if the interface supports DMA and the registers 685 * could be mapped. 686 * 687 * XXX Note that despite the fact that the Bus Master IDE specs 688 * XXX say that "The bus master IDE function uses 16 bytes of IO 689 * XXX space," some controllers (at least the United 690 * XXX Microelectronics UM8886BF) place it in memory space. 691 */ 692 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 693 PCIIDE_REG_BUS_MASTER_DMA); 694 695 switch (maptype) { 696 case PCI_MAPREG_TYPE_IO: 697 case PCI_MAPREG_MEM_TYPE_32BIT: 698 sc->sc_dma_ok = (pci_mapreg_map(pa, 699 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 700 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 701 sc->sc_dmat = pa->pa_dmat; 702 if (sc->sc_dma_ok == 0) { 703 printf(", but unused (couldn't map registers)"); 704 } else { 705 sc->sc_wdcdev.dma_arg = sc; 706 sc->sc_wdcdev.dma_init = pciide_dma_init; 707 sc->sc_wdcdev.dma_start = pciide_dma_start; 708 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 709 } 710 break; 711 712 default: 713 sc->sc_dma_ok = 0; 714 printf(", but unsupported register maptype (0x%x)", maptype); 715 } 716 } 717 718 int 719 pciide_compat_intr(arg) 720 void *arg; 721 { 722 struct pciide_channel *cp = arg; 723 724 #ifdef DIAGNOSTIC 725 /* should only be called for a compat channel */ 726 if (cp->compat == 0) 727 panic("pciide compat intr called for non-compat chan %p\n", cp); 728 #endif 729 return (wdcintr(&cp->wdc_channel)); 730 } 731 732 int 733 pciide_pci_intr(arg) 734 void *arg; 735 { 736 struct pciide_softc *sc = arg; 737 struct pciide_channel *cp; 738 struct channel_softc *wdc_cp; 739 int i, rv, crv; 740 741 rv = 0; 742 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 743 cp = &sc->pciide_channels[i]; 744 wdc_cp = &cp->wdc_channel; 745 746 /* If a compat channel skip. */ 747 if (cp->compat) 748 continue; 749 /* if this channel not waiting for intr, skip */ 750 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 751 continue; 752 753 crv = wdcintr(wdc_cp); 754 if (crv == 0) 755 ; /* leave rv alone */ 756 else if (crv == 1) 757 rv = 1; /* claim the intr */ 758 else if (rv == 0) /* crv should be -1 in this case */ 759 rv = crv; /* if we've done no better, take it */ 760 } 761 return (rv); 762 } 763 764 void 765 pciide_channel_dma_setup(cp) 766 struct pciide_channel *cp; 767 { 768 int drive; 769 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 770 struct ata_drive_datas *drvp; 771 772 for (drive = 0; drive < 2; drive++) { 773 drvp = &cp->wdc_channel.ch_drive[drive]; 774 /* If no drive, skip */ 775 if ((drvp->drive_flags & DRIVE) == 0) 776 continue; 777 /* setup DMA if needed */ 778 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 779 (drvp->drive_flags & DRIVE_UDMA) == 0) || 780 sc->sc_dma_ok == 0) { 781 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 782 continue; 783 } 784 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 785 != 0) { 786 /* Abort DMA setup */ 787 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 788 continue; 789 } 790 } 791 } 792 793 int 794 pciide_dma_table_setup(sc, channel, drive) 795 struct pciide_softc *sc; 796 int channel, drive; 797 { 798 bus_dma_segment_t seg; 799 int error, rseg; 800 const bus_size_t dma_table_size = 801 sizeof(struct idedma_table) * NIDEDMA_TABLES; 802 struct pciide_dma_maps *dma_maps = 803 &sc->pciide_channels[channel].dma_maps[drive]; 804 805 /* If table was already allocated, just return */ 806 if (dma_maps->dma_table) 807 return 0; 808 809 /* Allocate memory for the DMA tables and map it */ 810 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 811 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 812 BUS_DMA_NOWAIT)) != 0) { 813 printf("%s:%d: unable to allocate table DMA for " 814 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 815 channel, drive, error); 816 return error; 817 } 818 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 819 dma_table_size, 820 (caddr_t *)&dma_maps->dma_table, 821 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 822 printf("%s:%d: unable to map table DMA for" 823 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 824 channel, drive, error); 825 return error; 826 } 827 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 828 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 829 seg.ds_addr), DEBUG_PROBE); 830 831 /* Create and load table DMA map for this disk */ 832 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 833 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 834 &dma_maps->dmamap_table)) != 0) { 835 printf("%s:%d: unable to create table DMA map for " 836 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 837 channel, drive, error); 838 return error; 839 } 840 if ((error = bus_dmamap_load(sc->sc_dmat, 841 dma_maps->dmamap_table, 842 dma_maps->dma_table, 843 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 844 printf("%s:%d: unable to load table DMA map for " 845 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 846 channel, drive, error); 847 return error; 848 } 849 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 850 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 851 /* Create a xfer DMA map for this drive */ 852 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 853 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 854 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 855 &dma_maps->dmamap_xfer)) != 0) { 856 printf("%s:%d: unable to create xfer DMA map for " 857 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 858 channel, drive, error); 859 return error; 860 } 861 return 0; 862 } 863 864 int 865 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 866 void *v; 867 int channel, drive; 868 void *databuf; 869 size_t datalen; 870 int flags; 871 { 872 struct pciide_softc *sc = v; 873 int error, seg; 874 struct pciide_dma_maps *dma_maps = 875 &sc->pciide_channels[channel].dma_maps[drive]; 876 877 error = bus_dmamap_load(sc->sc_dmat, 878 dma_maps->dmamap_xfer, 879 databuf, datalen, NULL, BUS_DMA_NOWAIT); 880 if (error) { 881 printf("%s:%d: unable to load xfer DMA map for" 882 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 883 channel, drive, error); 884 return error; 885 } 886 887 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 888 dma_maps->dmamap_xfer->dm_mapsize, 889 (flags & WDC_DMA_READ) ? 890 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 891 892 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 893 #ifdef DIAGNOSTIC 894 /* A segment must not cross a 64k boundary */ 895 { 896 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 897 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 898 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 899 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 900 printf("pciide_dma: segment %d physical addr 0x%lx" 901 " len 0x%lx not properly aligned\n", 902 seg, phys, len); 903 panic("pciide_dma: buf align"); 904 } 905 } 906 #endif 907 dma_maps->dma_table[seg].base_addr = 908 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 909 dma_maps->dma_table[seg].byte_count = 910 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 911 IDEDMA_BYTE_COUNT_MASK); 912 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 913 seg, le32toh(dma_maps->dma_table[seg].byte_count), 914 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 915 916 } 917 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 918 htole32(IDEDMA_BYTE_COUNT_EOT); 919 920 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 921 dma_maps->dmamap_table->dm_mapsize, 922 BUS_DMASYNC_PREWRITE); 923 924 /* Maps are ready. Start DMA function */ 925 #ifdef DIAGNOSTIC 926 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 927 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 928 dma_maps->dmamap_table->dm_segs[0].ds_addr); 929 panic("pciide_dma_init: table align"); 930 } 931 #endif 932 933 /* Clear status bits */ 934 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 935 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 936 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 937 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 938 /* Write table addr */ 939 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 940 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 941 dma_maps->dmamap_table->dm_segs[0].ds_addr); 942 /* set read/write */ 943 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 944 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 945 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 946 /* remember flags */ 947 dma_maps->dma_flags = flags; 948 return 0; 949 } 950 951 void 952 pciide_dma_start(v, channel, drive) 953 void *v; 954 int channel, drive; 955 { 956 struct pciide_softc *sc = v; 957 958 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 959 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 960 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 961 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 962 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 963 } 964 965 int 966 pciide_dma_finish(v, channel, drive, force) 967 void *v; 968 int channel, drive; 969 int force; 970 { 971 struct pciide_softc *sc = v; 972 u_int8_t status; 973 int error = 0; 974 struct pciide_dma_maps *dma_maps = 975 &sc->pciide_channels[channel].dma_maps[drive]; 976 977 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 978 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 979 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 980 DEBUG_XFERS); 981 982 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 983 return WDC_DMAST_NOIRQ; 984 985 /* stop DMA channel */ 986 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 987 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 988 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 989 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 990 991 /* Unload the map of the data buffer */ 992 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 993 dma_maps->dmamap_xfer->dm_mapsize, 994 (dma_maps->dma_flags & WDC_DMA_READ) ? 995 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 996 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 997 998 if ((status & IDEDMA_CTL_ERR) != 0) { 999 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1000 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1001 error |= WDC_DMAST_ERR; 1002 } 1003 1004 if ((status & IDEDMA_CTL_INTR) == 0) { 1005 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1006 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1007 drive, status); 1008 error |= WDC_DMAST_NOIRQ; 1009 } 1010 1011 if ((status & IDEDMA_CTL_ACT) != 0) { 1012 /* data underrun, may be a valid condition for ATAPI */ 1013 error |= WDC_DMAST_UNDER; 1014 } 1015 return error; 1016 } 1017 1018 void 1019 pciide_irqack(chp) 1020 struct channel_softc *chp; 1021 { 1022 struct pciide_channel *cp = (struct pciide_channel*)chp; 1023 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1024 1025 /* clear status bits in IDE DMA registers */ 1026 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1027 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1028 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1029 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1030 } 1031 1032 /* some common code used by several chip_map */ 1033 int 1034 pciide_chansetup(sc, channel, interface) 1035 struct pciide_softc *sc; 1036 int channel; 1037 pcireg_t interface; 1038 { 1039 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1040 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1041 cp->name = PCIIDE_CHANNEL_NAME(channel); 1042 cp->wdc_channel.channel = channel; 1043 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1044 cp->wdc_channel.ch_queue = 1045 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1046 if (cp->wdc_channel.ch_queue == NULL) { 1047 printf("%s %s channel: " 1048 "can't allocate memory for command queue", 1049 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1050 return 0; 1051 } 1052 printf("%s: %s channel %s to %s mode\n", 1053 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1054 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1055 "configured" : "wired", 1056 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1057 "native-PCI" : "compatibility"); 1058 return 1; 1059 } 1060 1061 /* some common code used by several chip channel_map */ 1062 void 1063 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1064 struct pci_attach_args *pa; 1065 struct pciide_channel *cp; 1066 pcireg_t interface; 1067 bus_size_t *cmdsizep, *ctlsizep; 1068 int (*pci_intr) __P((void *)); 1069 { 1070 struct channel_softc *wdc_cp = &cp->wdc_channel; 1071 1072 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1073 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1074 pci_intr); 1075 else 1076 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1077 wdc_cp->channel, cmdsizep, ctlsizep); 1078 1079 if (cp->hw_ok == 0) 1080 return; 1081 wdc_cp->data32iot = wdc_cp->cmd_iot; 1082 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1083 wdcattach(wdc_cp); 1084 } 1085 1086 /* 1087 * Generic code to call to know if a channel can be disabled. Return 1 1088 * if channel can be disabled, 0 if not 1089 */ 1090 int 1091 pciide_chan_candisable(cp) 1092 struct pciide_channel *cp; 1093 { 1094 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1095 struct channel_softc *wdc_cp = &cp->wdc_channel; 1096 1097 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1098 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1099 printf("%s: disabling %s channel (no drives)\n", 1100 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1101 cp->hw_ok = 0; 1102 return 1; 1103 } 1104 return 0; 1105 } 1106 1107 /* 1108 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1109 * Set hw_ok=0 on failure 1110 */ 1111 void 1112 pciide_map_compat_intr(pa, cp, compatchan, interface) 1113 struct pci_attach_args *pa; 1114 struct pciide_channel *cp; 1115 int compatchan, interface; 1116 { 1117 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1118 struct channel_softc *wdc_cp = &cp->wdc_channel; 1119 1120 if (cp->hw_ok == 0) 1121 return; 1122 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1123 return; 1124 1125 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1126 pa, compatchan, pciide_compat_intr, cp); 1127 if (cp->ih == NULL) { 1128 printf("%s: no compatibility interrupt for use by %s " 1129 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1130 cp->hw_ok = 0; 1131 } 1132 } 1133 1134 void 1135 pciide_print_modes(cp) 1136 struct pciide_channel *cp; 1137 { 1138 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1139 int drive; 1140 struct channel_softc *chp; 1141 struct ata_drive_datas *drvp; 1142 1143 chp = &cp->wdc_channel; 1144 for (drive = 0; drive < 2; drive++) { 1145 drvp = &chp->ch_drive[drive]; 1146 if ((drvp->drive_flags & DRIVE) == 0) 1147 continue; 1148 printf("%s(%s:%d:%d): using PIO mode %d", 1149 drvp->drv_softc->dv_xname, 1150 sc->sc_wdcdev.sc_dev.dv_xname, 1151 chp->channel, drive, drvp->PIO_mode); 1152 if (drvp->drive_flags & DRIVE_DMA) 1153 printf(", DMA mode %d", drvp->DMA_mode); 1154 if (drvp->drive_flags & DRIVE_UDMA) 1155 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1156 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1157 printf(" (using DMA data transfers)"); 1158 printf("\n"); 1159 } 1160 } 1161 1162 void 1163 default_chip_map(sc, pa) 1164 struct pciide_softc *sc; 1165 struct pci_attach_args *pa; 1166 { 1167 struct pciide_channel *cp; 1168 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1169 pcireg_t csr; 1170 int channel, drive; 1171 struct ata_drive_datas *drvp; 1172 u_int8_t idedma_ctl; 1173 bus_size_t cmdsize, ctlsize; 1174 char *failreason; 1175 1176 if (pciide_chipen(sc, pa) == 0) 1177 return; 1178 1179 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1180 printf("%s: bus-master DMA support present", 1181 sc->sc_wdcdev.sc_dev.dv_xname); 1182 if (sc->sc_pp == &default_product_desc && 1183 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1184 PCIIDE_OPTIONS_DMA) == 0) { 1185 printf(", but unused (no driver support)"); 1186 sc->sc_dma_ok = 0; 1187 } else { 1188 pciide_mapreg_dma(sc, pa); 1189 if (sc->sc_dma_ok != 0) 1190 printf(", used without full driver " 1191 "support"); 1192 } 1193 } else { 1194 printf("%s: hardware does not support DMA", 1195 sc->sc_wdcdev.sc_dev.dv_xname); 1196 sc->sc_dma_ok = 0; 1197 } 1198 printf("\n"); 1199 if (sc->sc_dma_ok) { 1200 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1201 sc->sc_wdcdev.irqack = pciide_irqack; 1202 } 1203 sc->sc_wdcdev.PIO_cap = 0; 1204 sc->sc_wdcdev.DMA_cap = 0; 1205 1206 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1207 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1208 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1209 1210 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1211 cp = &sc->pciide_channels[channel]; 1212 if (pciide_chansetup(sc, channel, interface) == 0) 1213 continue; 1214 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1215 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1216 &ctlsize, pciide_pci_intr); 1217 } else { 1218 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1219 channel, &cmdsize, &ctlsize); 1220 } 1221 if (cp->hw_ok == 0) 1222 continue; 1223 /* 1224 * Check to see if something appears to be there. 1225 */ 1226 failreason = NULL; 1227 if (!wdcprobe(&cp->wdc_channel)) { 1228 failreason = "not responding; disabled or no drives?"; 1229 goto next; 1230 } 1231 /* 1232 * Now, make sure it's actually attributable to this PCI IDE 1233 * channel by trying to access the channel again while the 1234 * PCI IDE controller's I/O space is disabled. (If the 1235 * channel no longer appears to be there, it belongs to 1236 * this controller.) YUCK! 1237 */ 1238 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1239 PCI_COMMAND_STATUS_REG); 1240 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1241 csr & ~PCI_COMMAND_IO_ENABLE); 1242 if (wdcprobe(&cp->wdc_channel)) 1243 failreason = "other hardware responding at addresses"; 1244 pci_conf_write(sc->sc_pc, sc->sc_tag, 1245 PCI_COMMAND_STATUS_REG, csr); 1246 next: 1247 if (failreason) { 1248 printf("%s: %s channel ignored (%s)\n", 1249 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1250 failreason); 1251 cp->hw_ok = 0; 1252 bus_space_unmap(cp->wdc_channel.cmd_iot, 1253 cp->wdc_channel.cmd_ioh, cmdsize); 1254 bus_space_unmap(cp->wdc_channel.ctl_iot, 1255 cp->wdc_channel.ctl_ioh, ctlsize); 1256 } else { 1257 pciide_map_compat_intr(pa, cp, channel, interface); 1258 } 1259 if (cp->hw_ok) { 1260 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1261 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1262 wdcattach(&cp->wdc_channel); 1263 } 1264 } 1265 1266 if (sc->sc_dma_ok == 0) 1267 return; 1268 1269 /* Allocate DMA maps */ 1270 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1271 idedma_ctl = 0; 1272 cp = &sc->pciide_channels[channel]; 1273 for (drive = 0; drive < 2; drive++) { 1274 drvp = &cp->wdc_channel.ch_drive[drive]; 1275 /* If no drive, skip */ 1276 if ((drvp->drive_flags & DRIVE) == 0) 1277 continue; 1278 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1279 continue; 1280 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1281 /* Abort DMA setup */ 1282 printf("%s:%d:%d: can't allocate DMA maps, " 1283 "using PIO transfers\n", 1284 sc->sc_wdcdev.sc_dev.dv_xname, 1285 channel, drive); 1286 drvp->drive_flags &= ~DRIVE_DMA; 1287 } 1288 printf("%s:%d:%d: using DMA data transfers\n", 1289 sc->sc_wdcdev.sc_dev.dv_xname, 1290 channel, drive); 1291 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1292 } 1293 if (idedma_ctl != 0) { 1294 /* Add software bits in status register */ 1295 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1296 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1297 idedma_ctl); 1298 } 1299 } 1300 } 1301 1302 void 1303 piix_chip_map(sc, pa) 1304 struct pciide_softc *sc; 1305 struct pci_attach_args *pa; 1306 { 1307 struct pciide_channel *cp; 1308 int channel; 1309 u_int32_t idetim; 1310 bus_size_t cmdsize, ctlsize; 1311 1312 if (pciide_chipen(sc, pa) == 0) 1313 return; 1314 1315 printf("%s: bus-master DMA support present", 1316 sc->sc_wdcdev.sc_dev.dv_xname); 1317 pciide_mapreg_dma(sc, pa); 1318 printf("\n"); 1319 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1320 WDC_CAPABILITY_MODE; 1321 if (sc->sc_dma_ok) { 1322 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1323 sc->sc_wdcdev.irqack = pciide_irqack; 1324 switch(sc->sc_pp->ide_product) { 1325 case PCI_PRODUCT_INTEL_82371AB_IDE: 1326 case PCI_PRODUCT_INTEL_82801AA_IDE: 1327 case PCI_PRODUCT_INTEL_82801AB_IDE: 1328 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1329 } 1330 } 1331 sc->sc_wdcdev.PIO_cap = 4; 1332 sc->sc_wdcdev.DMA_cap = 2; 1333 sc->sc_wdcdev.UDMA_cap = 1334 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1335 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1336 sc->sc_wdcdev.set_modes = piix_setup_channel; 1337 else 1338 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1339 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1340 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1341 1342 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1343 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1344 DEBUG_PROBE); 1345 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1346 WDCDEBUG_PRINT((", sidetim=0x%x", 1347 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1348 DEBUG_PROBE); 1349 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1350 WDCDEBUG_PRINT((", udamreg 0x%x", 1351 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1352 DEBUG_PROBE); 1353 } 1354 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1355 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1356 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1357 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1358 DEBUG_PROBE); 1359 } 1360 1361 } 1362 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1363 1364 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1365 cp = &sc->pciide_channels[channel]; 1366 /* PIIX is compat-only */ 1367 if (pciide_chansetup(sc, channel, 0) == 0) 1368 continue; 1369 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1370 if ((PIIX_IDETIM_READ(idetim, channel) & 1371 PIIX_IDETIM_IDE) == 0) { 1372 printf("%s: %s channel ignored (disabled)\n", 1373 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1374 continue; 1375 } 1376 /* PIIX are compat-only pciide devices */ 1377 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1378 if (cp->hw_ok == 0) 1379 continue; 1380 if (pciide_chan_candisable(cp)) { 1381 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1382 channel); 1383 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1384 idetim); 1385 } 1386 pciide_map_compat_intr(pa, cp, channel, 0); 1387 if (cp->hw_ok == 0) 1388 continue; 1389 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1390 } 1391 1392 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1393 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1394 DEBUG_PROBE); 1395 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1396 WDCDEBUG_PRINT((", sidetim=0x%x", 1397 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1398 DEBUG_PROBE); 1399 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1400 WDCDEBUG_PRINT((", udamreg 0x%x", 1401 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1402 DEBUG_PROBE); 1403 } 1404 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1405 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1406 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1407 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1408 DEBUG_PROBE); 1409 } 1410 } 1411 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1412 } 1413 1414 void 1415 piix_setup_channel(chp) 1416 struct channel_softc *chp; 1417 { 1418 u_int8_t mode[2], drive; 1419 u_int32_t oidetim, idetim, idedma_ctl; 1420 struct pciide_channel *cp = (struct pciide_channel*)chp; 1421 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1422 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1423 1424 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1425 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1426 idedma_ctl = 0; 1427 1428 /* set up new idetim: Enable IDE registers decode */ 1429 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1430 chp->channel); 1431 1432 /* setup DMA */ 1433 pciide_channel_dma_setup(cp); 1434 1435 /* 1436 * Here we have to mess up with drives mode: PIIX can't have 1437 * different timings for master and slave drives. 1438 * We need to find the best combination. 1439 */ 1440 1441 /* If both drives supports DMA, take the lower mode */ 1442 if ((drvp[0].drive_flags & DRIVE_DMA) && 1443 (drvp[1].drive_flags & DRIVE_DMA)) { 1444 mode[0] = mode[1] = 1445 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1446 drvp[0].DMA_mode = mode[0]; 1447 drvp[1].DMA_mode = mode[1]; 1448 goto ok; 1449 } 1450 /* 1451 * If only one drive supports DMA, use its mode, and 1452 * put the other one in PIO mode 0 if mode not compatible 1453 */ 1454 if (drvp[0].drive_flags & DRIVE_DMA) { 1455 mode[0] = drvp[0].DMA_mode; 1456 mode[1] = drvp[1].PIO_mode; 1457 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1458 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1459 mode[1] = drvp[1].PIO_mode = 0; 1460 goto ok; 1461 } 1462 if (drvp[1].drive_flags & DRIVE_DMA) { 1463 mode[1] = drvp[1].DMA_mode; 1464 mode[0] = drvp[0].PIO_mode; 1465 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1466 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1467 mode[0] = drvp[0].PIO_mode = 0; 1468 goto ok; 1469 } 1470 /* 1471 * If both drives are not DMA, takes the lower mode, unless 1472 * one of them is PIO mode < 2 1473 */ 1474 if (drvp[0].PIO_mode < 2) { 1475 mode[0] = drvp[0].PIO_mode = 0; 1476 mode[1] = drvp[1].PIO_mode; 1477 } else if (drvp[1].PIO_mode < 2) { 1478 mode[1] = drvp[1].PIO_mode = 0; 1479 mode[0] = drvp[0].PIO_mode; 1480 } else { 1481 mode[0] = mode[1] = 1482 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1483 drvp[0].PIO_mode = mode[0]; 1484 drvp[1].PIO_mode = mode[1]; 1485 } 1486 ok: /* The modes are setup */ 1487 for (drive = 0; drive < 2; drive++) { 1488 if (drvp[drive].drive_flags & DRIVE_DMA) { 1489 idetim |= piix_setup_idetim_timings( 1490 mode[drive], 1, chp->channel); 1491 goto end; 1492 } 1493 } 1494 /* If we are there, none of the drives are DMA */ 1495 if (mode[0] >= 2) 1496 idetim |= piix_setup_idetim_timings( 1497 mode[0], 0, chp->channel); 1498 else 1499 idetim |= piix_setup_idetim_timings( 1500 mode[1], 0, chp->channel); 1501 end: /* 1502 * timing mode is now set up in the controller. Enable 1503 * it per-drive 1504 */ 1505 for (drive = 0; drive < 2; drive++) { 1506 /* If no drive, skip */ 1507 if ((drvp[drive].drive_flags & DRIVE) == 0) 1508 continue; 1509 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1510 if (drvp[drive].drive_flags & DRIVE_DMA) 1511 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1512 } 1513 if (idedma_ctl != 0) { 1514 /* Add software bits in status register */ 1515 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1516 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1517 idedma_ctl); 1518 } 1519 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1520 pciide_print_modes(cp); 1521 } 1522 1523 void 1524 piix3_4_setup_channel(chp) 1525 struct channel_softc *chp; 1526 { 1527 struct ata_drive_datas *drvp; 1528 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1529 struct pciide_channel *cp = (struct pciide_channel*)chp; 1530 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1531 int drive; 1532 int channel = chp->channel; 1533 1534 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1535 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1536 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1537 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1538 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1539 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1540 PIIX_SIDETIM_RTC_MASK(channel)); 1541 1542 idedma_ctl = 0; 1543 /* If channel disabled, no need to go further */ 1544 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1545 return; 1546 /* set up new idetim: Enable IDE registers decode */ 1547 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1548 1549 /* setup DMA if needed */ 1550 pciide_channel_dma_setup(cp); 1551 1552 for (drive = 0; drive < 2; drive++) { 1553 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1554 PIIX_UDMATIM_SET(0x3, channel, drive)); 1555 drvp = &chp->ch_drive[drive]; 1556 /* If no drive, skip */ 1557 if ((drvp->drive_flags & DRIVE) == 0) 1558 continue; 1559 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1560 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1561 goto pio; 1562 1563 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1564 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1565 ideconf |= PIIX_CONFIG_PINGPONG; 1566 } 1567 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1568 /* setup Ultra/66 */ 1569 if (drvp->UDMA_mode > 2 && 1570 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1571 drvp->UDMA_mode = 2; 1572 if (drvp->UDMA_mode > 2) 1573 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1574 else 1575 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1576 } 1577 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1578 (drvp->drive_flags & DRIVE_UDMA)) { 1579 /* use Ultra/DMA */ 1580 drvp->drive_flags &= ~DRIVE_DMA; 1581 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1582 udmareg |= PIIX_UDMATIM_SET( 1583 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1584 } else { 1585 /* use Multiword DMA */ 1586 drvp->drive_flags &= ~DRIVE_UDMA; 1587 if (drive == 0) { 1588 idetim |= piix_setup_idetim_timings( 1589 drvp->DMA_mode, 1, channel); 1590 } else { 1591 sidetim |= piix_setup_sidetim_timings( 1592 drvp->DMA_mode, 1, channel); 1593 idetim =PIIX_IDETIM_SET(idetim, 1594 PIIX_IDETIM_SITRE, channel); 1595 } 1596 } 1597 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1598 1599 pio: /* use PIO mode */ 1600 idetim |= piix_setup_idetim_drvs(drvp); 1601 if (drive == 0) { 1602 idetim |= piix_setup_idetim_timings( 1603 drvp->PIO_mode, 0, channel); 1604 } else { 1605 sidetim |= piix_setup_sidetim_timings( 1606 drvp->PIO_mode, 0, channel); 1607 idetim =PIIX_IDETIM_SET(idetim, 1608 PIIX_IDETIM_SITRE, channel); 1609 } 1610 } 1611 if (idedma_ctl != 0) { 1612 /* Add software bits in status register */ 1613 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1614 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1615 idedma_ctl); 1616 } 1617 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1618 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1619 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1620 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1621 pciide_print_modes(cp); 1622 } 1623 1624 1625 /* setup ISP and RTC fields, based on mode */ 1626 static u_int32_t 1627 piix_setup_idetim_timings(mode, dma, channel) 1628 u_int8_t mode; 1629 u_int8_t dma; 1630 u_int8_t channel; 1631 { 1632 1633 if (dma) 1634 return PIIX_IDETIM_SET(0, 1635 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1636 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1637 channel); 1638 else 1639 return PIIX_IDETIM_SET(0, 1640 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1641 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1642 channel); 1643 } 1644 1645 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1646 static u_int32_t 1647 piix_setup_idetim_drvs(drvp) 1648 struct ata_drive_datas *drvp; 1649 { 1650 u_int32_t ret = 0; 1651 struct channel_softc *chp = drvp->chnl_softc; 1652 u_int8_t channel = chp->channel; 1653 u_int8_t drive = drvp->drive; 1654 1655 /* 1656 * If drive is using UDMA, timings setups are independant 1657 * So just check DMA and PIO here. 1658 */ 1659 if (drvp->drive_flags & DRIVE_DMA) { 1660 /* if mode = DMA mode 0, use compatible timings */ 1661 if ((drvp->drive_flags & DRIVE_DMA) && 1662 drvp->DMA_mode == 0) { 1663 drvp->PIO_mode = 0; 1664 return ret; 1665 } 1666 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1667 /* 1668 * PIO and DMA timings are the same, use fast timings for PIO 1669 * too, else use compat timings. 1670 */ 1671 if ((piix_isp_pio[drvp->PIO_mode] != 1672 piix_isp_dma[drvp->DMA_mode]) || 1673 (piix_rtc_pio[drvp->PIO_mode] != 1674 piix_rtc_dma[drvp->DMA_mode])) 1675 drvp->PIO_mode = 0; 1676 /* if PIO mode <= 2, use compat timings for PIO */ 1677 if (drvp->PIO_mode <= 2) { 1678 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1679 channel); 1680 return ret; 1681 } 1682 } 1683 1684 /* 1685 * Now setup PIO modes. If mode < 2, use compat timings. 1686 * Else enable fast timings. Enable IORDY and prefetch/post 1687 * if PIO mode >= 3. 1688 */ 1689 1690 if (drvp->PIO_mode < 2) 1691 return ret; 1692 1693 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1694 if (drvp->PIO_mode >= 3) { 1695 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1696 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1697 } 1698 return ret; 1699 } 1700 1701 /* setup values in SIDETIM registers, based on mode */ 1702 static u_int32_t 1703 piix_setup_sidetim_timings(mode, dma, channel) 1704 u_int8_t mode; 1705 u_int8_t dma; 1706 u_int8_t channel; 1707 { 1708 if (dma) 1709 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1710 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1711 else 1712 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1713 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1714 } 1715 1716 void 1717 amd756_chip_map(sc, pa) 1718 struct pciide_softc *sc; 1719 struct pci_attach_args *pa; 1720 { 1721 struct pciide_channel *cp; 1722 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1723 int channel; 1724 pcireg_t chanenable; 1725 bus_size_t cmdsize, ctlsize; 1726 1727 if (pciide_chipen(sc, pa) == 0) 1728 return; 1729 printf("%s: bus-master DMA support present", 1730 sc->sc_wdcdev.sc_dev.dv_xname); 1731 pciide_mapreg_dma(sc, pa); 1732 printf("\n"); 1733 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1734 WDC_CAPABILITY_MODE; 1735 if (sc->sc_dma_ok) { 1736 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1737 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1738 sc->sc_wdcdev.irqack = pciide_irqack; 1739 } 1740 sc->sc_wdcdev.PIO_cap = 4; 1741 sc->sc_wdcdev.DMA_cap = 2; 1742 sc->sc_wdcdev.UDMA_cap = 4; 1743 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1744 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1745 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1746 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1747 1748 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1749 DEBUG_PROBE); 1750 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1751 cp = &sc->pciide_channels[channel]; 1752 if (pciide_chansetup(sc, channel, interface) == 0) 1753 continue; 1754 1755 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1756 printf("%s: %s channel ignored (disabled)\n", 1757 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1758 continue; 1759 } 1760 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1761 pciide_pci_intr); 1762 1763 if (pciide_chan_candisable(cp)) 1764 chanenable &= ~AMD756_CHAN_EN(channel); 1765 pciide_map_compat_intr(pa, cp, channel, interface); 1766 if (cp->hw_ok == 0) 1767 continue; 1768 1769 amd756_setup_channel(&cp->wdc_channel); 1770 } 1771 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1772 chanenable); 1773 return; 1774 } 1775 1776 void 1777 amd756_setup_channel(chp) 1778 struct channel_softc *chp; 1779 { 1780 u_int32_t udmatim_reg, datatim_reg; 1781 u_int8_t idedma_ctl; 1782 int mode, drive; 1783 struct ata_drive_datas *drvp; 1784 struct pciide_channel *cp = (struct pciide_channel*)chp; 1785 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1786 #ifndef PCIIDE_AMD756_ENABLEDMA 1787 int rev = PCI_REVISION( 1788 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1789 #endif 1790 1791 idedma_ctl = 0; 1792 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1793 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1794 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1795 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1796 1797 /* setup DMA if needed */ 1798 pciide_channel_dma_setup(cp); 1799 1800 for (drive = 0; drive < 2; drive++) { 1801 drvp = &chp->ch_drive[drive]; 1802 /* If no drive, skip */ 1803 if ((drvp->drive_flags & DRIVE) == 0) 1804 continue; 1805 /* add timing values, setup DMA if needed */ 1806 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1807 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1808 mode = drvp->PIO_mode; 1809 goto pio; 1810 } 1811 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1812 (drvp->drive_flags & DRIVE_UDMA)) { 1813 /* use Ultra/DMA */ 1814 drvp->drive_flags &= ~DRIVE_DMA; 1815 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1816 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1817 AMD756_UDMA_TIME(chp->channel, drive, 1818 amd756_udma_tim[drvp->UDMA_mode]); 1819 /* can use PIO timings, MW DMA unused */ 1820 mode = drvp->PIO_mode; 1821 } else { 1822 /* use Multiword DMA, but only if revision is OK */ 1823 drvp->drive_flags &= ~DRIVE_UDMA; 1824 #ifndef PCIIDE_AMD756_ENABLEDMA 1825 /* 1826 * The workaround doesn't seem to be necessary 1827 * with all drives, so it can be disabled by 1828 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1829 * triggered. 1830 */ 1831 if (AMD756_CHIPREV_DISABLEDMA(rev)) { 1832 printf("%s:%d:%d: multi-word DMA disabled due " 1833 "to chip revision\n", 1834 sc->sc_wdcdev.sc_dev.dv_xname, 1835 chp->channel, drive); 1836 mode = drvp->PIO_mode; 1837 drvp->drive_flags &= ~DRIVE_DMA; 1838 goto pio; 1839 } 1840 #endif 1841 /* mode = min(pio, dma+2) */ 1842 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1843 mode = drvp->PIO_mode; 1844 else 1845 mode = drvp->DMA_mode + 2; 1846 } 1847 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1848 1849 pio: /* setup PIO mode */ 1850 if (mode <= 2) { 1851 drvp->DMA_mode = 0; 1852 drvp->PIO_mode = 0; 1853 mode = 0; 1854 } else { 1855 drvp->PIO_mode = mode; 1856 drvp->DMA_mode = mode - 2; 1857 } 1858 datatim_reg |= 1859 AMD756_DATATIM_PULSE(chp->channel, drive, 1860 amd756_pio_set[mode]) | 1861 AMD756_DATATIM_RECOV(chp->channel, drive, 1862 amd756_pio_rec[mode]); 1863 } 1864 if (idedma_ctl != 0) { 1865 /* Add software bits in status register */ 1866 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1867 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1868 idedma_ctl); 1869 } 1870 pciide_print_modes(cp); 1871 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1872 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1873 } 1874 1875 void 1876 apollo_chip_map(sc, pa) 1877 struct pciide_softc *sc; 1878 struct pci_attach_args *pa; 1879 { 1880 struct pciide_channel *cp; 1881 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1882 int channel; 1883 u_int32_t ideconf; 1884 bus_size_t cmdsize, ctlsize; 1885 1886 if (pciide_chipen(sc, pa) == 0) 1887 return; 1888 printf("%s: bus-master DMA support present", 1889 sc->sc_wdcdev.sc_dev.dv_xname); 1890 pciide_mapreg_dma(sc, pa); 1891 printf("\n"); 1892 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1893 WDC_CAPABILITY_MODE; 1894 if (sc->sc_dma_ok) { 1895 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1896 sc->sc_wdcdev.irqack = pciide_irqack; 1897 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1898 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1899 } 1900 sc->sc_wdcdev.PIO_cap = 4; 1901 sc->sc_wdcdev.DMA_cap = 2; 1902 sc->sc_wdcdev.UDMA_cap = 2; 1903 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1904 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1905 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1906 1907 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1908 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1909 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1910 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1911 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1912 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1913 DEBUG_PROBE); 1914 1915 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1916 cp = &sc->pciide_channels[channel]; 1917 if (pciide_chansetup(sc, channel, interface) == 0) 1918 continue; 1919 1920 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1921 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1922 printf("%s: %s channel ignored (disabled)\n", 1923 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1924 continue; 1925 } 1926 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1927 pciide_pci_intr); 1928 if (cp->hw_ok == 0) 1929 continue; 1930 if (pciide_chan_candisable(cp)) { 1931 ideconf &= ~APO_IDECONF_EN(channel); 1932 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1933 ideconf); 1934 } 1935 pciide_map_compat_intr(pa, cp, channel, interface); 1936 1937 if (cp->hw_ok == 0) 1938 continue; 1939 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1940 } 1941 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1942 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1943 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1944 } 1945 1946 void 1947 apollo_setup_channel(chp) 1948 struct channel_softc *chp; 1949 { 1950 u_int32_t udmatim_reg, datatim_reg; 1951 u_int8_t idedma_ctl; 1952 int mode, drive; 1953 struct ata_drive_datas *drvp; 1954 struct pciide_channel *cp = (struct pciide_channel*)chp; 1955 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1956 1957 idedma_ctl = 0; 1958 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1959 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1960 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1961 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1962 1963 /* setup DMA if needed */ 1964 pciide_channel_dma_setup(cp); 1965 1966 for (drive = 0; drive < 2; drive++) { 1967 drvp = &chp->ch_drive[drive]; 1968 /* If no drive, skip */ 1969 if ((drvp->drive_flags & DRIVE) == 0) 1970 continue; 1971 /* add timing values, setup DMA if needed */ 1972 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1973 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1974 mode = drvp->PIO_mode; 1975 goto pio; 1976 } 1977 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1978 (drvp->drive_flags & DRIVE_UDMA)) { 1979 /* use Ultra/DMA */ 1980 drvp->drive_flags &= ~DRIVE_DMA; 1981 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1982 APO_UDMA_EN_MTH(chp->channel, drive) | 1983 APO_UDMA_TIME(chp->channel, drive, 1984 apollo_udma_tim[drvp->UDMA_mode]); 1985 /* can use PIO timings, MW DMA unused */ 1986 mode = drvp->PIO_mode; 1987 } else { 1988 /* use Multiword DMA */ 1989 drvp->drive_flags &= ~DRIVE_UDMA; 1990 /* mode = min(pio, dma+2) */ 1991 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1992 mode = drvp->PIO_mode; 1993 else 1994 mode = drvp->DMA_mode + 2; 1995 } 1996 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1997 1998 pio: /* setup PIO mode */ 1999 if (mode <= 2) { 2000 drvp->DMA_mode = 0; 2001 drvp->PIO_mode = 0; 2002 mode = 0; 2003 } else { 2004 drvp->PIO_mode = mode; 2005 drvp->DMA_mode = mode - 2; 2006 } 2007 datatim_reg |= 2008 APO_DATATIM_PULSE(chp->channel, drive, 2009 apollo_pio_set[mode]) | 2010 APO_DATATIM_RECOV(chp->channel, drive, 2011 apollo_pio_rec[mode]); 2012 } 2013 if (idedma_ctl != 0) { 2014 /* Add software bits in status register */ 2015 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2016 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2017 idedma_ctl); 2018 } 2019 pciide_print_modes(cp); 2020 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2021 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2022 } 2023 2024 void 2025 cmd_channel_map(pa, sc, channel) 2026 struct pci_attach_args *pa; 2027 struct pciide_softc *sc; 2028 int channel; 2029 { 2030 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2031 bus_size_t cmdsize, ctlsize; 2032 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2033 int interface; 2034 2035 /* 2036 * The 0648/0649 can be told to identify as a RAID controller. 2037 * In this case, we have to fake interface 2038 */ 2039 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2040 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2041 PCIIDE_INTERFACE_SETTABLE(1); 2042 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2043 CMD_CONF_DSA1) 2044 interface |= PCIIDE_INTERFACE_PCI(0) | 2045 PCIIDE_INTERFACE_PCI(1); 2046 } else { 2047 interface = PCI_INTERFACE(pa->pa_class); 2048 } 2049 2050 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2051 cp->name = PCIIDE_CHANNEL_NAME(channel); 2052 cp->wdc_channel.channel = channel; 2053 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2054 2055 if (channel > 0) { 2056 cp->wdc_channel.ch_queue = 2057 sc->pciide_channels[0].wdc_channel.ch_queue; 2058 } else { 2059 cp->wdc_channel.ch_queue = 2060 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2061 } 2062 if (cp->wdc_channel.ch_queue == NULL) { 2063 printf("%s %s channel: " 2064 "can't allocate memory for command queue", 2065 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2066 return; 2067 } 2068 2069 printf("%s: %s channel %s to %s mode\n", 2070 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2071 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2072 "configured" : "wired", 2073 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2074 "native-PCI" : "compatibility"); 2075 2076 /* 2077 * with a CMD PCI64x, if we get here, the first channel is enabled: 2078 * there's no way to disable the first channel without disabling 2079 * the whole device 2080 */ 2081 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2082 printf("%s: %s channel ignored (disabled)\n", 2083 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2084 return; 2085 } 2086 2087 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2088 if (cp->hw_ok == 0) 2089 return; 2090 if (channel == 1) { 2091 if (pciide_chan_candisable(cp)) { 2092 ctrl &= ~CMD_CTRL_2PORT; 2093 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2094 CMD_CTRL, ctrl); 2095 } 2096 } 2097 pciide_map_compat_intr(pa, cp, channel, interface); 2098 } 2099 2100 int 2101 cmd_pci_intr(arg) 2102 void *arg; 2103 { 2104 struct pciide_softc *sc = arg; 2105 struct pciide_channel *cp; 2106 struct channel_softc *wdc_cp; 2107 int i, rv, crv; 2108 u_int32_t priirq, secirq; 2109 2110 rv = 0; 2111 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2112 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2113 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2114 cp = &sc->pciide_channels[i]; 2115 wdc_cp = &cp->wdc_channel; 2116 /* If a compat channel skip. */ 2117 if (cp->compat) 2118 continue; 2119 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2120 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2121 crv = wdcintr(wdc_cp); 2122 if (crv == 0) 2123 printf("%s:%d: bogus intr\n", 2124 sc->sc_wdcdev.sc_dev.dv_xname, i); 2125 else 2126 rv = 1; 2127 } 2128 } 2129 return rv; 2130 } 2131 2132 void 2133 cmd_chip_map(sc, pa) 2134 struct pciide_softc *sc; 2135 struct pci_attach_args *pa; 2136 { 2137 int channel; 2138 2139 /* 2140 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2141 * and base adresses registers can be disabled at 2142 * hardware level. In this case, the device is wired 2143 * in compat mode and its first channel is always enabled, 2144 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2145 * In fact, it seems that the first channel of the CMD PCI0640 2146 * can't be disabled. 2147 */ 2148 2149 #ifdef PCIIDE_CMD064x_DISABLE 2150 if (pciide_chipen(sc, pa) == 0) 2151 return; 2152 #endif 2153 2154 printf("%s: hardware does not support DMA\n", 2155 sc->sc_wdcdev.sc_dev.dv_xname); 2156 sc->sc_dma_ok = 0; 2157 2158 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2159 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2160 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2161 2162 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2163 cmd_channel_map(pa, sc, channel); 2164 } 2165 } 2166 2167 void 2168 cmd0643_9_chip_map(sc, pa) 2169 struct pciide_softc *sc; 2170 struct pci_attach_args *pa; 2171 { 2172 struct pciide_channel *cp; 2173 int channel; 2174 int rev = PCI_REVISION( 2175 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2176 2177 /* 2178 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2179 * and base adresses registers can be disabled at 2180 * hardware level. In this case, the device is wired 2181 * in compat mode and its first channel is always enabled, 2182 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2183 * In fact, it seems that the first channel of the CMD PCI0640 2184 * can't be disabled. 2185 */ 2186 2187 #ifdef PCIIDE_CMD064x_DISABLE 2188 if (pciide_chipen(sc, pa) == 0) 2189 return; 2190 #endif 2191 printf("%s: bus-master DMA support present", 2192 sc->sc_wdcdev.sc_dev.dv_xname); 2193 pciide_mapreg_dma(sc, pa); 2194 printf("\n"); 2195 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2196 WDC_CAPABILITY_MODE; 2197 if (sc->sc_dma_ok) { 2198 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2199 switch (sc->sc_pp->ide_product) { 2200 case PCI_PRODUCT_CMDTECH_649: 2201 case PCI_PRODUCT_CMDTECH_648: 2202 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2203 sc->sc_wdcdev.UDMA_cap = 4; 2204 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2205 break; 2206 case PCI_PRODUCT_CMDTECH_646: 2207 if (rev >= CMD0646U2_REV) { 2208 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2209 sc->sc_wdcdev.UDMA_cap = 2; 2210 } else if (rev >= CMD0646U_REV) { 2211 /* 2212 * Linux's driver claims that the 646U is broken 2213 * with UDMA. Only enable it if we know what we're 2214 * doing 2215 */ 2216 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2217 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2218 sc->sc_wdcdev.UDMA_cap = 2; 2219 #endif 2220 /* explicitely disable UDMA */ 2221 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2222 CMD_UDMATIM(0), 0); 2223 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2224 CMD_UDMATIM(1), 0); 2225 } 2226 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2227 break; 2228 default: 2229 sc->sc_wdcdev.irqack = pciide_irqack; 2230 } 2231 } 2232 2233 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2234 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2235 sc->sc_wdcdev.PIO_cap = 4; 2236 sc->sc_wdcdev.DMA_cap = 2; 2237 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2238 2239 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2240 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2241 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2242 DEBUG_PROBE); 2243 2244 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2245 cp = &sc->pciide_channels[channel]; 2246 cmd_channel_map(pa, sc, channel); 2247 if (cp->hw_ok == 0) 2248 continue; 2249 cmd0643_9_setup_channel(&cp->wdc_channel); 2250 } 2251 /* 2252 * note - this also makes sure we clear the irq disable and reset 2253 * bits 2254 */ 2255 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2256 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2257 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2258 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2259 DEBUG_PROBE); 2260 } 2261 2262 void 2263 cmd0643_9_setup_channel(chp) 2264 struct channel_softc *chp; 2265 { 2266 struct ata_drive_datas *drvp; 2267 u_int8_t tim; 2268 u_int32_t idedma_ctl, udma_reg; 2269 int drive; 2270 struct pciide_channel *cp = (struct pciide_channel*)chp; 2271 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2272 2273 idedma_ctl = 0; 2274 /* setup DMA if needed */ 2275 pciide_channel_dma_setup(cp); 2276 2277 for (drive = 0; drive < 2; drive++) { 2278 drvp = &chp->ch_drive[drive]; 2279 /* If no drive, skip */ 2280 if ((drvp->drive_flags & DRIVE) == 0) 2281 continue; 2282 /* add timing values, setup DMA if needed */ 2283 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2284 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2285 if (drvp->drive_flags & DRIVE_UDMA) { 2286 /* UltraDMA on a 646U2, 0648 or 0649 */ 2287 udma_reg = pciide_pci_read(sc->sc_pc, 2288 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2289 if (drvp->UDMA_mode > 2 && 2290 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2291 CMD_BICSR) & 2292 CMD_BICSR_80(chp->channel)) == 0) 2293 drvp->UDMA_mode = 2; 2294 if (drvp->UDMA_mode > 2) 2295 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2296 else if (sc->sc_wdcdev.UDMA_cap > 2) 2297 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2298 udma_reg |= CMD_UDMATIM_UDMA(drive); 2299 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2300 CMD_UDMATIM_TIM_OFF(drive)); 2301 udma_reg |= 2302 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2303 CMD_UDMATIM_TIM_OFF(drive)); 2304 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2305 CMD_UDMATIM(chp->channel), udma_reg); 2306 } else { 2307 /* 2308 * use Multiword DMA. 2309 * Timings will be used for both PIO and DMA, 2310 * so adjust DMA mode if needed 2311 * if we have a 0646U2/8/9, turn off UDMA 2312 */ 2313 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2314 udma_reg = pciide_pci_read(sc->sc_pc, 2315 sc->sc_tag, 2316 CMD_UDMATIM(chp->channel)); 2317 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2318 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2319 CMD_UDMATIM(chp->channel), 2320 udma_reg); 2321 } 2322 if (drvp->PIO_mode >= 3 && 2323 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2324 drvp->DMA_mode = drvp->PIO_mode - 2; 2325 } 2326 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2327 } 2328 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2329 } 2330 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2331 CMD_DATA_TIM(chp->channel, drive), tim); 2332 } 2333 if (idedma_ctl != 0) { 2334 /* Add software bits in status register */ 2335 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2336 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2337 idedma_ctl); 2338 } 2339 pciide_print_modes(cp); 2340 } 2341 2342 void 2343 cmd646_9_irqack(chp) 2344 struct channel_softc *chp; 2345 { 2346 u_int32_t priirq, secirq; 2347 struct pciide_channel *cp = (struct pciide_channel*)chp; 2348 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2349 2350 if (chp->channel == 0) { 2351 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2352 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2353 } else { 2354 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2355 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2356 } 2357 pciide_irqack(chp); 2358 } 2359 2360 void 2361 cy693_chip_map(sc, pa) 2362 struct pciide_softc *sc; 2363 struct pci_attach_args *pa; 2364 { 2365 struct pciide_channel *cp; 2366 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2367 bus_size_t cmdsize, ctlsize; 2368 2369 if (pciide_chipen(sc, pa) == 0) 2370 return; 2371 /* 2372 * this chip has 2 PCI IDE functions, one for primary and one for 2373 * secondary. So we need to call pciide_mapregs_compat() with 2374 * the real channel 2375 */ 2376 if (pa->pa_function == 1) { 2377 sc->sc_cy_compatchan = 0; 2378 } else if (pa->pa_function == 2) { 2379 sc->sc_cy_compatchan = 1; 2380 } else { 2381 printf("%s: unexpected PCI function %d\n", 2382 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2383 return; 2384 } 2385 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2386 printf("%s: bus-master DMA support present", 2387 sc->sc_wdcdev.sc_dev.dv_xname); 2388 pciide_mapreg_dma(sc, pa); 2389 } else { 2390 printf("%s: hardware does not support DMA", 2391 sc->sc_wdcdev.sc_dev.dv_xname); 2392 sc->sc_dma_ok = 0; 2393 } 2394 printf("\n"); 2395 2396 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2397 if (sc->sc_cy_handle == NULL) { 2398 printf("%s: unable to map hyperCache control registers\n", 2399 sc->sc_wdcdev.sc_dev.dv_xname); 2400 sc->sc_dma_ok = 0; 2401 } 2402 2403 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2404 WDC_CAPABILITY_MODE; 2405 if (sc->sc_dma_ok) { 2406 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2407 sc->sc_wdcdev.irqack = pciide_irqack; 2408 } 2409 sc->sc_wdcdev.PIO_cap = 4; 2410 sc->sc_wdcdev.DMA_cap = 2; 2411 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2412 2413 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2414 sc->sc_wdcdev.nchannels = 1; 2415 2416 /* Only one channel for this chip; if we are here it's enabled */ 2417 cp = &sc->pciide_channels[0]; 2418 sc->wdc_chanarray[0] = &cp->wdc_channel; 2419 cp->name = PCIIDE_CHANNEL_NAME(0); 2420 cp->wdc_channel.channel = 0; 2421 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2422 cp->wdc_channel.ch_queue = 2423 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2424 if (cp->wdc_channel.ch_queue == NULL) { 2425 printf("%s primary channel: " 2426 "can't allocate memory for command queue", 2427 sc->sc_wdcdev.sc_dev.dv_xname); 2428 return; 2429 } 2430 printf("%s: primary channel %s to ", 2431 sc->sc_wdcdev.sc_dev.dv_xname, 2432 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2433 "configured" : "wired"); 2434 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2435 printf("native-PCI"); 2436 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2437 pciide_pci_intr); 2438 } else { 2439 printf("compatibility"); 2440 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2441 &cmdsize, &ctlsize); 2442 } 2443 printf(" mode\n"); 2444 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2445 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2446 wdcattach(&cp->wdc_channel); 2447 if (pciide_chan_candisable(cp)) { 2448 pci_conf_write(sc->sc_pc, sc->sc_tag, 2449 PCI_COMMAND_STATUS_REG, 0); 2450 } 2451 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2452 if (cp->hw_ok == 0) 2453 return; 2454 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2455 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2456 cy693_setup_channel(&cp->wdc_channel); 2457 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2458 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2459 } 2460 2461 void 2462 cy693_setup_channel(chp) 2463 struct channel_softc *chp; 2464 { 2465 struct ata_drive_datas *drvp; 2466 int drive; 2467 u_int32_t cy_cmd_ctrl; 2468 u_int32_t idedma_ctl; 2469 struct pciide_channel *cp = (struct pciide_channel*)chp; 2470 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2471 int dma_mode = -1; 2472 2473 cy_cmd_ctrl = idedma_ctl = 0; 2474 2475 /* setup DMA if needed */ 2476 pciide_channel_dma_setup(cp); 2477 2478 for (drive = 0; drive < 2; drive++) { 2479 drvp = &chp->ch_drive[drive]; 2480 /* If no drive, skip */ 2481 if ((drvp->drive_flags & DRIVE) == 0) 2482 continue; 2483 /* add timing values, setup DMA if needed */ 2484 if (drvp->drive_flags & DRIVE_DMA) { 2485 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2486 /* use Multiword DMA */ 2487 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2488 dma_mode = drvp->DMA_mode; 2489 } 2490 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2491 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2492 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2493 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2494 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2495 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2496 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2497 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2498 } 2499 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2500 chp->ch_drive[0].DMA_mode = dma_mode; 2501 chp->ch_drive[1].DMA_mode = dma_mode; 2502 2503 if (dma_mode == -1) 2504 dma_mode = 0; 2505 2506 if (sc->sc_cy_handle != NULL) { 2507 /* Note: `multiple' is implied. */ 2508 cy82c693_write(sc->sc_cy_handle, 2509 (sc->sc_cy_compatchan == 0) ? 2510 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2511 } 2512 2513 pciide_print_modes(cp); 2514 2515 if (idedma_ctl != 0) { 2516 /* Add software bits in status register */ 2517 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2518 IDEDMA_CTL, idedma_ctl); 2519 } 2520 } 2521 2522 void 2523 sis_chip_map(sc, pa) 2524 struct pciide_softc *sc; 2525 struct pci_attach_args *pa; 2526 { 2527 struct pciide_channel *cp; 2528 int channel; 2529 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2530 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2531 pcireg_t rev = PCI_REVISION(pa->pa_class); 2532 bus_size_t cmdsize, ctlsize; 2533 2534 if (pciide_chipen(sc, pa) == 0) 2535 return; 2536 printf("%s: bus-master DMA support present", 2537 sc->sc_wdcdev.sc_dev.dv_xname); 2538 pciide_mapreg_dma(sc, pa); 2539 printf("\n"); 2540 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2541 WDC_CAPABILITY_MODE; 2542 if (sc->sc_dma_ok) { 2543 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2544 sc->sc_wdcdev.irqack = pciide_irqack; 2545 if (rev >= 0xd0) 2546 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2547 } 2548 2549 sc->sc_wdcdev.PIO_cap = 4; 2550 sc->sc_wdcdev.DMA_cap = 2; 2551 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2552 sc->sc_wdcdev.UDMA_cap = 2; 2553 sc->sc_wdcdev.set_modes = sis_setup_channel; 2554 2555 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2556 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2557 2558 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2559 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2560 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2561 2562 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2563 cp = &sc->pciide_channels[channel]; 2564 if (pciide_chansetup(sc, channel, interface) == 0) 2565 continue; 2566 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2567 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2568 printf("%s: %s channel ignored (disabled)\n", 2569 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2570 continue; 2571 } 2572 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2573 pciide_pci_intr); 2574 if (cp->hw_ok == 0) 2575 continue; 2576 if (pciide_chan_candisable(cp)) { 2577 if (channel == 0) 2578 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2579 else 2580 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2581 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2582 sis_ctr0); 2583 } 2584 pciide_map_compat_intr(pa, cp, channel, interface); 2585 if (cp->hw_ok == 0) 2586 continue; 2587 sis_setup_channel(&cp->wdc_channel); 2588 } 2589 } 2590 2591 void 2592 sis_setup_channel(chp) 2593 struct channel_softc *chp; 2594 { 2595 struct ata_drive_datas *drvp; 2596 int drive; 2597 u_int32_t sis_tim; 2598 u_int32_t idedma_ctl; 2599 struct pciide_channel *cp = (struct pciide_channel*)chp; 2600 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2601 2602 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2603 "channel %d 0x%x\n", chp->channel, 2604 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2605 DEBUG_PROBE); 2606 sis_tim = 0; 2607 idedma_ctl = 0; 2608 /* setup DMA if needed */ 2609 pciide_channel_dma_setup(cp); 2610 2611 for (drive = 0; drive < 2; drive++) { 2612 drvp = &chp->ch_drive[drive]; 2613 /* If no drive, skip */ 2614 if ((drvp->drive_flags & DRIVE) == 0) 2615 continue; 2616 /* add timing values, setup DMA if needed */ 2617 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2618 (drvp->drive_flags & DRIVE_UDMA) == 0) 2619 goto pio; 2620 2621 if (drvp->drive_flags & DRIVE_UDMA) { 2622 /* use Ultra/DMA */ 2623 drvp->drive_flags &= ~DRIVE_DMA; 2624 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2625 SIS_TIM_UDMA_TIME_OFF(drive); 2626 sis_tim |= SIS_TIM_UDMA_EN(drive); 2627 } else { 2628 /* 2629 * use Multiword DMA 2630 * Timings will be used for both PIO and DMA, 2631 * so adjust DMA mode if needed 2632 */ 2633 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2634 drvp->PIO_mode = drvp->DMA_mode + 2; 2635 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2636 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2637 drvp->PIO_mode - 2 : 0; 2638 if (drvp->DMA_mode == 0) 2639 drvp->PIO_mode = 0; 2640 } 2641 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2642 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2643 SIS_TIM_ACT_OFF(drive); 2644 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2645 SIS_TIM_REC_OFF(drive); 2646 } 2647 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2648 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2649 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2650 if (idedma_ctl != 0) { 2651 /* Add software bits in status register */ 2652 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2653 IDEDMA_CTL, idedma_ctl); 2654 } 2655 pciide_print_modes(cp); 2656 } 2657 2658 void 2659 acer_chip_map(sc, pa) 2660 struct pciide_softc *sc; 2661 struct pci_attach_args *pa; 2662 { 2663 struct pciide_channel *cp; 2664 int channel; 2665 pcireg_t cr, interface; 2666 bus_size_t cmdsize, ctlsize; 2667 2668 if (pciide_chipen(sc, pa) == 0) 2669 return; 2670 printf("%s: bus-master DMA support present", 2671 sc->sc_wdcdev.sc_dev.dv_xname); 2672 pciide_mapreg_dma(sc, pa); 2673 printf("\n"); 2674 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2675 WDC_CAPABILITY_MODE; 2676 if (sc->sc_dma_ok) { 2677 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2678 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2679 sc->sc_wdcdev.irqack = pciide_irqack; 2680 } 2681 2682 sc->sc_wdcdev.PIO_cap = 4; 2683 sc->sc_wdcdev.DMA_cap = 2; 2684 sc->sc_wdcdev.UDMA_cap = 2; 2685 sc->sc_wdcdev.set_modes = acer_setup_channel; 2686 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2687 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2688 2689 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2690 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2691 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2692 2693 /* Enable "microsoft register bits" R/W. */ 2694 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2695 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2696 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2697 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2698 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2699 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2700 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2701 ~ACER_CHANSTATUSREGS_RO); 2702 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2703 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2704 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2705 /* Don't use cr, re-read the real register content instead */ 2706 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2707 PCI_CLASS_REG)); 2708 2709 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2710 cp = &sc->pciide_channels[channel]; 2711 if (pciide_chansetup(sc, channel, interface) == 0) 2712 continue; 2713 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2714 printf("%s: %s channel ignored (disabled)\n", 2715 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2716 continue; 2717 } 2718 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2719 acer_pci_intr); 2720 if (cp->hw_ok == 0) 2721 continue; 2722 if (pciide_chan_candisable(cp)) { 2723 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2724 pci_conf_write(sc->sc_pc, sc->sc_tag, 2725 PCI_CLASS_REG, cr); 2726 } 2727 pciide_map_compat_intr(pa, cp, channel, interface); 2728 acer_setup_channel(&cp->wdc_channel); 2729 } 2730 } 2731 2732 void 2733 acer_setup_channel(chp) 2734 struct channel_softc *chp; 2735 { 2736 struct ata_drive_datas *drvp; 2737 int drive; 2738 u_int32_t acer_fifo_udma; 2739 u_int32_t idedma_ctl; 2740 struct pciide_channel *cp = (struct pciide_channel*)chp; 2741 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2742 2743 idedma_ctl = 0; 2744 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2745 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2746 acer_fifo_udma), DEBUG_PROBE); 2747 /* setup DMA if needed */ 2748 pciide_channel_dma_setup(cp); 2749 2750 for (drive = 0; drive < 2; drive++) { 2751 drvp = &chp->ch_drive[drive]; 2752 /* If no drive, skip */ 2753 if ((drvp->drive_flags & DRIVE) == 0) 2754 continue; 2755 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2756 "channel %d drive %d 0x%x\n", chp->channel, drive, 2757 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2758 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2759 /* clear FIFO/DMA mode */ 2760 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2761 ACER_UDMA_EN(chp->channel, drive) | 2762 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2763 2764 /* add timing values, setup DMA if needed */ 2765 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2766 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2767 acer_fifo_udma |= 2768 ACER_FTH_OPL(chp->channel, drive, 0x1); 2769 goto pio; 2770 } 2771 2772 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2773 if (drvp->drive_flags & DRIVE_UDMA) { 2774 /* use Ultra/DMA */ 2775 drvp->drive_flags &= ~DRIVE_DMA; 2776 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2777 acer_fifo_udma |= 2778 ACER_UDMA_TIM(chp->channel, drive, 2779 acer_udma[drvp->UDMA_mode]); 2780 } else { 2781 /* 2782 * use Multiword DMA 2783 * Timings will be used for both PIO and DMA, 2784 * so adjust DMA mode if needed 2785 */ 2786 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2787 drvp->PIO_mode = drvp->DMA_mode + 2; 2788 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2789 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2790 drvp->PIO_mode - 2 : 0; 2791 if (drvp->DMA_mode == 0) 2792 drvp->PIO_mode = 0; 2793 } 2794 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2795 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2796 ACER_IDETIM(chp->channel, drive), 2797 acer_pio[drvp->PIO_mode]); 2798 } 2799 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2800 acer_fifo_udma), DEBUG_PROBE); 2801 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2802 if (idedma_ctl != 0) { 2803 /* Add software bits in status register */ 2804 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2805 IDEDMA_CTL, idedma_ctl); 2806 } 2807 pciide_print_modes(cp); 2808 } 2809 2810 int 2811 acer_pci_intr(arg) 2812 void *arg; 2813 { 2814 struct pciide_softc *sc = arg; 2815 struct pciide_channel *cp; 2816 struct channel_softc *wdc_cp; 2817 int i, rv, crv; 2818 u_int32_t chids; 2819 2820 rv = 0; 2821 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2822 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2823 cp = &sc->pciide_channels[i]; 2824 wdc_cp = &cp->wdc_channel; 2825 /* If a compat channel skip. */ 2826 if (cp->compat) 2827 continue; 2828 if (chids & ACER_CHIDS_INT(i)) { 2829 crv = wdcintr(wdc_cp); 2830 if (crv == 0) 2831 printf("%s:%d: bogus intr\n", 2832 sc->sc_wdcdev.sc_dev.dv_xname, i); 2833 else 2834 rv = 1; 2835 } 2836 } 2837 return rv; 2838 } 2839 2840 void 2841 hpt_chip_map(sc, pa) 2842 struct pciide_softc *sc; 2843 struct pci_attach_args *pa; 2844 { 2845 struct pciide_channel *cp; 2846 int i, compatchan, revision; 2847 pcireg_t interface; 2848 bus_size_t cmdsize, ctlsize; 2849 2850 if (pciide_chipen(sc, pa) == 0) 2851 return; 2852 revision = PCI_REVISION(pa->pa_class); 2853 2854 /* 2855 * when the chip is in native mode it identifies itself as a 2856 * 'misc mass storage'. Fake interface in this case. 2857 */ 2858 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2859 interface = PCI_INTERFACE(pa->pa_class); 2860 } else { 2861 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2862 PCIIDE_INTERFACE_PCI(0); 2863 if (revision == HPT370_REV) 2864 interface |= PCIIDE_INTERFACE_PCI(1); 2865 } 2866 2867 printf("%s: bus-master DMA support present", 2868 sc->sc_wdcdev.sc_dev.dv_xname); 2869 pciide_mapreg_dma(sc, pa); 2870 printf("\n"); 2871 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2872 WDC_CAPABILITY_MODE; 2873 if (sc->sc_dma_ok) { 2874 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2875 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2876 sc->sc_wdcdev.irqack = pciide_irqack; 2877 } 2878 sc->sc_wdcdev.PIO_cap = 4; 2879 sc->sc_wdcdev.DMA_cap = 2; 2880 sc->sc_wdcdev.UDMA_cap = 4; 2881 2882 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2883 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2884 if (revision == HPT366_REV) { 2885 /* 2886 * The 366 has 2 PCI IDE functions, one for primary and one 2887 * for secondary. So we need to call pciide_mapregs_compat() 2888 * with the real channel 2889 */ 2890 if (pa->pa_function == 0) { 2891 compatchan = 0; 2892 } else if (pa->pa_function == 1) { 2893 compatchan = 1; 2894 } else { 2895 printf("%s: unexpected PCI function %d\n", 2896 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2897 return; 2898 } 2899 sc->sc_wdcdev.nchannels = 1; 2900 } else { 2901 sc->sc_wdcdev.nchannels = 2; 2902 } 2903 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2904 cp = &sc->pciide_channels[i]; 2905 if (sc->sc_wdcdev.nchannels > 1) { 2906 compatchan = i; 2907 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2908 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2909 printf("%s: %s channel ignored (disabled)\n", 2910 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2911 continue; 2912 } 2913 } 2914 if (pciide_chansetup(sc, i, interface) == 0) 2915 continue; 2916 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2917 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2918 &ctlsize, hpt_pci_intr); 2919 } else { 2920 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2921 &cmdsize, &ctlsize); 2922 } 2923 if (cp->hw_ok == 0) 2924 return; 2925 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2926 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2927 wdcattach(&cp->wdc_channel); 2928 hpt_setup_channel(&cp->wdc_channel); 2929 } 2930 if (revision == HPT370_REV) { 2931 /* 2932 * HPT370_REV has a bit to disable interrupts, make sure 2933 * to clear it 2934 */ 2935 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 2936 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 2937 ~HPT_CSEL_IRQDIS); 2938 } 2939 return; 2940 } 2941 2942 2943 void 2944 hpt_setup_channel(chp) 2945 struct channel_softc *chp; 2946 { 2947 struct ata_drive_datas *drvp; 2948 int drive; 2949 int cable; 2950 u_int32_t before, after; 2951 u_int32_t idedma_ctl; 2952 struct pciide_channel *cp = (struct pciide_channel*)chp; 2953 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2954 2955 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 2956 2957 /* setup DMA if needed */ 2958 pciide_channel_dma_setup(cp); 2959 2960 idedma_ctl = 0; 2961 2962 /* Per drive settings */ 2963 for (drive = 0; drive < 2; drive++) { 2964 drvp = &chp->ch_drive[drive]; 2965 /* If no drive, skip */ 2966 if ((drvp->drive_flags & DRIVE) == 0) 2967 continue; 2968 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 2969 HPT_IDETIM(chp->channel, drive)); 2970 2971 /* add timing values, setup DMA if needed */ 2972 if (drvp->drive_flags & DRIVE_UDMA) { 2973 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 2974 drvp->UDMA_mode > 2) 2975 drvp->UDMA_mode = 2; 2976 after = (sc->sc_wdcdev.nchannels == 2) ? 2977 hpt370_udma[drvp->UDMA_mode] : 2978 hpt366_udma[drvp->UDMA_mode]; 2979 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2980 } else if (drvp->drive_flags & DRIVE_DMA) { 2981 /* 2982 * use Multiword DMA. 2983 * Timings will be used for both PIO and DMA, so adjust 2984 * DMA mode if needed 2985 */ 2986 if (drvp->PIO_mode >= 3 && 2987 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2988 drvp->DMA_mode = drvp->PIO_mode - 2; 2989 } 2990 after = (sc->sc_wdcdev.nchannels == 2) ? 2991 hpt370_dma[drvp->DMA_mode] : 2992 hpt366_dma[drvp->DMA_mode]; 2993 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2994 } else { 2995 /* PIO only */ 2996 after = (sc->sc_wdcdev.nchannels == 2) ? 2997 hpt370_pio[drvp->PIO_mode] : 2998 hpt366_pio[drvp->PIO_mode]; 2999 } 3000 pci_conf_write(sc->sc_pc, sc->sc_tag, 3001 HPT_IDETIM(chp->channel, drive), after); 3002 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3003 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3004 after, before), DEBUG_PROBE); 3005 } 3006 if (idedma_ctl != 0) { 3007 /* Add software bits in status register */ 3008 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3009 IDEDMA_CTL, idedma_ctl); 3010 } 3011 pciide_print_modes(cp); 3012 } 3013 3014 int 3015 hpt_pci_intr(arg) 3016 void *arg; 3017 { 3018 struct pciide_softc *sc = arg; 3019 struct pciide_channel *cp; 3020 struct channel_softc *wdc_cp; 3021 int rv = 0; 3022 int dmastat, i, crv; 3023 3024 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3025 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3026 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3027 if((dmastat & IDEDMA_CTL_INTR) == 0) 3028 continue; 3029 cp = &sc->pciide_channels[i]; 3030 wdc_cp = &cp->wdc_channel; 3031 crv = wdcintr(wdc_cp); 3032 if (crv == 0) { 3033 printf("%s:%d: bogus intr\n", 3034 sc->sc_wdcdev.sc_dev.dv_xname, i); 3035 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3036 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3037 } else 3038 rv = 1; 3039 } 3040 return rv; 3041 } 3042 3043 3044 /* A macro to test product */ 3045 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 3046 3047 void 3048 pdc202xx_chip_map(sc, pa) 3049 struct pciide_softc *sc; 3050 struct pci_attach_args *pa; 3051 { 3052 struct pciide_channel *cp; 3053 int channel; 3054 pcireg_t interface, st, mode; 3055 bus_size_t cmdsize, ctlsize; 3056 3057 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3058 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3059 DEBUG_PROBE); 3060 if (pciide_chipen(sc, pa) == 0) 3061 return; 3062 3063 /* turn off RAID mode */ 3064 st &= ~PDC2xx_STATE_IDERAID; 3065 3066 /* 3067 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3068 * mode. We have to fake interface 3069 */ 3070 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3071 if (st & PDC2xx_STATE_NATIVE) 3072 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3073 3074 printf("%s: bus-master DMA support present", 3075 sc->sc_wdcdev.sc_dev.dv_xname); 3076 pciide_mapreg_dma(sc, pa); 3077 printf("\n"); 3078 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3079 WDC_CAPABILITY_MODE; 3080 if (sc->sc_dma_ok) { 3081 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3082 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3083 sc->sc_wdcdev.irqack = pciide_irqack; 3084 } 3085 sc->sc_wdcdev.PIO_cap = 4; 3086 sc->sc_wdcdev.DMA_cap = 2; 3087 if (PDC_IS_262(sc)) 3088 sc->sc_wdcdev.UDMA_cap = 4; 3089 else 3090 sc->sc_wdcdev.UDMA_cap = 2; 3091 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3092 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3093 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3094 3095 /* setup failsafe defaults */ 3096 mode = 0; 3097 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3098 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3099 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3100 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3101 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3102 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3103 "initial timings 0x%x, now 0x%x\n", channel, 3104 pci_conf_read(sc->sc_pc, sc->sc_tag, 3105 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3106 DEBUG_PROBE); 3107 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3108 mode | PDC2xx_TIM_IORDYp); 3109 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3110 "initial timings 0x%x, now 0x%x\n", channel, 3111 pci_conf_read(sc->sc_pc, sc->sc_tag, 3112 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3113 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3114 mode); 3115 } 3116 3117 mode = PDC2xx_SCR_DMA; 3118 if (PDC_IS_262(sc)) { 3119 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3120 } else { 3121 /* the BIOS set it up this way */ 3122 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3123 } 3124 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3125 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3126 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3127 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3128 DEBUG_PROBE); 3129 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3130 3131 /* controller initial state register is OK even without BIOS */ 3132 /* Set DMA mode to IDE DMA compatibility */ 3133 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3134 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3135 DEBUG_PROBE); 3136 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3137 mode | 0x1); 3138 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3139 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3140 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3141 mode | 0x1); 3142 3143 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3144 cp = &sc->pciide_channels[channel]; 3145 if (pciide_chansetup(sc, channel, interface) == 0) 3146 continue; 3147 if ((st & (PDC_IS_262(sc) ? 3148 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3149 printf("%s: %s channel ignored (disabled)\n", 3150 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3151 continue; 3152 } 3153 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3154 pdc202xx_pci_intr); 3155 if (cp->hw_ok == 0) 3156 continue; 3157 if (pciide_chan_candisable(cp)) 3158 st &= ~(PDC_IS_262(sc) ? 3159 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3160 pciide_map_compat_intr(pa, cp, channel, interface); 3161 pdc202xx_setup_channel(&cp->wdc_channel); 3162 } 3163 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3164 DEBUG_PROBE); 3165 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3166 return; 3167 } 3168 3169 void 3170 pdc202xx_setup_channel(chp) 3171 struct channel_softc *chp; 3172 { 3173 struct ata_drive_datas *drvp; 3174 int drive; 3175 pcireg_t mode, st; 3176 u_int32_t idedma_ctl, scr, atapi; 3177 struct pciide_channel *cp = (struct pciide_channel*)chp; 3178 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3179 int channel = chp->channel; 3180 3181 /* setup DMA if needed */ 3182 pciide_channel_dma_setup(cp); 3183 3184 idedma_ctl = 0; 3185 3186 /* Per channel settings */ 3187 if (PDC_IS_262(sc)) { 3188 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3189 PDC262_U66); 3190 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3191 /* Trimm UDMA mode */ 3192 if ((st & PDC262_STATE_80P(channel)) != 0 || 3193 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3194 chp->ch_drive[0].UDMA_mode <= 2) || 3195 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3196 chp->ch_drive[1].UDMA_mode <= 2)) { 3197 if (chp->ch_drive[0].UDMA_mode > 2) 3198 chp->ch_drive[0].UDMA_mode = 2; 3199 if (chp->ch_drive[1].UDMA_mode > 2) 3200 chp->ch_drive[1].UDMA_mode = 2; 3201 } 3202 /* Set U66 if needed */ 3203 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3204 chp->ch_drive[0].UDMA_mode > 2) || 3205 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3206 chp->ch_drive[1].UDMA_mode > 2)) 3207 scr |= PDC262_U66_EN(channel); 3208 else 3209 scr &= ~PDC262_U66_EN(channel); 3210 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3211 PDC262_U66, scr); 3212 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3213 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3214 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3215 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3216 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3217 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3218 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3219 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3220 atapi = 0; 3221 else 3222 atapi = PDC262_ATAPI_UDMA; 3223 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3224 PDC262_ATAPI(channel), atapi); 3225 } 3226 } 3227 for (drive = 0; drive < 2; drive++) { 3228 drvp = &chp->ch_drive[drive]; 3229 /* If no drive, skip */ 3230 if ((drvp->drive_flags & DRIVE) == 0) 3231 continue; 3232 mode = 0; 3233 if (drvp->drive_flags & DRIVE_UDMA) { 3234 mode = PDC2xx_TIM_SET_MB(mode, 3235 pdc2xx_udma_mb[drvp->UDMA_mode]); 3236 mode = PDC2xx_TIM_SET_MC(mode, 3237 pdc2xx_udma_mc[drvp->UDMA_mode]); 3238 drvp->drive_flags &= ~DRIVE_DMA; 3239 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3240 } else if (drvp->drive_flags & DRIVE_DMA) { 3241 mode = PDC2xx_TIM_SET_MB(mode, 3242 pdc2xx_dma_mb[drvp->DMA_mode]); 3243 mode = PDC2xx_TIM_SET_MC(mode, 3244 pdc2xx_dma_mc[drvp->DMA_mode]); 3245 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3246 } else { 3247 mode = PDC2xx_TIM_SET_MB(mode, 3248 pdc2xx_dma_mb[0]); 3249 mode = PDC2xx_TIM_SET_MC(mode, 3250 pdc2xx_dma_mc[0]); 3251 } 3252 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3253 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3254 if (drvp->drive_flags & DRIVE_ATA) 3255 mode |= PDC2xx_TIM_PRE; 3256 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3257 if (drvp->PIO_mode >= 3) { 3258 mode |= PDC2xx_TIM_IORDY; 3259 if (drive == 0) 3260 mode |= PDC2xx_TIM_IORDYp; 3261 } 3262 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3263 "timings 0x%x\n", 3264 sc->sc_wdcdev.sc_dev.dv_xname, 3265 chp->channel, drive, mode), DEBUG_PROBE); 3266 pci_conf_write(sc->sc_pc, sc->sc_tag, 3267 PDC2xx_TIM(chp->channel, drive), mode); 3268 } 3269 if (idedma_ctl != 0) { 3270 /* Add software bits in status register */ 3271 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3272 IDEDMA_CTL, idedma_ctl); 3273 } 3274 pciide_print_modes(cp); 3275 } 3276 3277 int 3278 pdc202xx_pci_intr(arg) 3279 void *arg; 3280 { 3281 struct pciide_softc *sc = arg; 3282 struct pciide_channel *cp; 3283 struct channel_softc *wdc_cp; 3284 int i, rv, crv; 3285 u_int32_t scr; 3286 3287 rv = 0; 3288 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3289 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3290 cp = &sc->pciide_channels[i]; 3291 wdc_cp = &cp->wdc_channel; 3292 /* If a compat channel skip. */ 3293 if (cp->compat) 3294 continue; 3295 if (scr & PDC2xx_SCR_INT(i)) { 3296 crv = wdcintr(wdc_cp); 3297 if (crv == 0) 3298 printf("%s:%d: bogus intr\n", 3299 sc->sc_wdcdev.sc_dev.dv_xname, i); 3300 else 3301 rv = 1; 3302 } 3303 } 3304 return rv; 3305 } 3306 3307 void 3308 opti_chip_map(sc, pa) 3309 struct pciide_softc *sc; 3310 struct pci_attach_args *pa; 3311 { 3312 struct pciide_channel *cp; 3313 bus_size_t cmdsize, ctlsize; 3314 pcireg_t interface; 3315 u_int8_t init_ctrl; 3316 int channel; 3317 3318 if (pciide_chipen(sc, pa) == 0) 3319 return; 3320 printf("%s: bus-master DMA support present", 3321 sc->sc_wdcdev.sc_dev.dv_xname); 3322 pciide_mapreg_dma(sc, pa); 3323 printf("\n"); 3324 3325 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3326 WDC_CAPABILITY_MODE; 3327 sc->sc_wdcdev.PIO_cap = 4; 3328 if (sc->sc_dma_ok) { 3329 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3330 sc->sc_wdcdev.irqack = pciide_irqack; 3331 sc->sc_wdcdev.DMA_cap = 2; 3332 } 3333 sc->sc_wdcdev.set_modes = opti_setup_channel; 3334 3335 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3336 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3337 3338 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3339 OPTI_REG_INIT_CONTROL); 3340 3341 interface = PCI_INTERFACE(pa->pa_class); 3342 3343 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3344 cp = &sc->pciide_channels[channel]; 3345 if (pciide_chansetup(sc, channel, interface) == 0) 3346 continue; 3347 if (channel == 1 && 3348 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3349 printf("%s: %s channel ignored (disabled)\n", 3350 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3351 continue; 3352 } 3353 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3354 pciide_pci_intr); 3355 if (cp->hw_ok == 0) 3356 continue; 3357 pciide_map_compat_intr(pa, cp, channel, interface); 3358 if (cp->hw_ok == 0) 3359 continue; 3360 opti_setup_channel(&cp->wdc_channel); 3361 } 3362 } 3363 3364 void 3365 opti_setup_channel(chp) 3366 struct channel_softc *chp; 3367 { 3368 struct ata_drive_datas *drvp; 3369 struct pciide_channel *cp = (struct pciide_channel*)chp; 3370 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3371 int drive, spd; 3372 int mode[2]; 3373 u_int8_t rv, mr; 3374 3375 /* 3376 * The `Delay' and `Address Setup Time' fields of the 3377 * Miscellaneous Register are always zero initially. 3378 */ 3379 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3380 mr &= ~(OPTI_MISC_DELAY_MASK | 3381 OPTI_MISC_ADDR_SETUP_MASK | 3382 OPTI_MISC_INDEX_MASK); 3383 3384 /* Prime the control register before setting timing values */ 3385 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3386 3387 /* Determine the clockrate of the PCIbus the chip is attached to */ 3388 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3389 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3390 3391 /* setup DMA if needed */ 3392 pciide_channel_dma_setup(cp); 3393 3394 for (drive = 0; drive < 2; drive++) { 3395 drvp = &chp->ch_drive[drive]; 3396 /* If no drive, skip */ 3397 if ((drvp->drive_flags & DRIVE) == 0) { 3398 mode[drive] = -1; 3399 continue; 3400 } 3401 3402 if ((drvp->drive_flags & DRIVE_DMA)) { 3403 /* 3404 * Timings will be used for both PIO and DMA, 3405 * so adjust DMA mode if needed 3406 */ 3407 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3408 drvp->PIO_mode = drvp->DMA_mode + 2; 3409 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3410 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3411 drvp->PIO_mode - 2 : 0; 3412 if (drvp->DMA_mode == 0) 3413 drvp->PIO_mode = 0; 3414 3415 mode[drive] = drvp->DMA_mode + 5; 3416 } else 3417 mode[drive] = drvp->PIO_mode; 3418 3419 if (drive && mode[0] >= 0 && 3420 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3421 /* 3422 * Can't have two drives using different values 3423 * for `Address Setup Time'. 3424 * Slow down the faster drive to compensate. 3425 */ 3426 int d = (opti_tim_as[spd][mode[0]] > 3427 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3428 3429 mode[d] = mode[1-d]; 3430 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3431 chp->ch_drive[d].DMA_mode = 0; 3432 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3433 } 3434 } 3435 3436 for (drive = 0; drive < 2; drive++) { 3437 int m; 3438 if ((m = mode[drive]) < 0) 3439 continue; 3440 3441 /* Set the Address Setup Time and select appropriate index */ 3442 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3443 rv |= OPTI_MISC_INDEX(drive); 3444 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3445 3446 /* Set the pulse width and recovery timing parameters */ 3447 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3448 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3449 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3450 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3451 3452 /* Set the Enhanced Mode register appropriately */ 3453 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3454 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3455 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3456 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3457 } 3458 3459 /* Finally, enable the timings */ 3460 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3461 3462 pciide_print_modes(cp); 3463 } 3464
Indexes created Thu Oct 02 14:10:14 GMT 2025