pciide.c revision 1.68.2.13
1 /* $NetBSD: pciide.c,v 1.68.2.13 2000/08/22 02:19:32 enami Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <vm/vm.h> 102 #include <vm/vm_param.h> 103 #include <vm/vm_kern.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/cy82c693var.h> 121 122 #include "opt_pciide.h" 123 124 /* inlines for reading/writing 8-bit PCI registers */ 125 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 126 int)); 127 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 128 int, u_int8_t)); 129 130 static __inline u_int8_t 131 pciide_pci_read(pc, pa, reg) 132 pci_chipset_tag_t pc; 133 pcitag_t pa; 134 int reg; 135 { 136 137 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 138 ((reg & 0x03) * 8) & 0xff); 139 } 140 141 static __inline void 142 pciide_pci_write(pc, pa, reg, val) 143 pci_chipset_tag_t pc; 144 pcitag_t pa; 145 int reg; 146 u_int8_t val; 147 { 148 pcireg_t pcival; 149 150 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 151 pcival &= ~(0xff << ((reg & 0x03) * 8)); 152 pcival |= (val << ((reg & 0x03) * 8)); 153 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 154 } 155 156 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 157 158 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 void piix_setup_channel __P((struct channel_softc*)); 160 void piix3_4_setup_channel __P((struct channel_softc*)); 161 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 162 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 163 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 165 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 166 void amd756_setup_channel __P((struct channel_softc*)); 167 168 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 169 void apollo_setup_channel __P((struct channel_softc*)); 170 171 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 172 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 173 void cmd0643_9_setup_channel __P((struct channel_softc*)); 174 void cmd_channel_map __P((struct pci_attach_args *, 175 struct pciide_softc *, int)); 176 int cmd_pci_intr __P((void *)); 177 void cmd646_9_irqack __P((struct channel_softc *)); 178 179 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 180 void cy693_setup_channel __P((struct channel_softc*)); 181 182 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 183 void sis_setup_channel __P((struct channel_softc*)); 184 185 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 186 void acer_setup_channel __P((struct channel_softc*)); 187 int acer_pci_intr __P((void *)); 188 189 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 190 void pdc202xx_setup_channel __P((struct channel_softc*)); 191 int pdc202xx_pci_intr __P((void *)); 192 193 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 194 void opti_setup_channel __P((struct channel_softc*)); 195 196 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 197 void hpt_setup_channel __P((struct channel_softc*)); 198 int hpt_pci_intr __P((void *)); 199 200 void pciide_channel_dma_setup __P((struct pciide_channel *)); 201 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 202 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 203 void pciide_dma_start __P((void*, int, int)); 204 int pciide_dma_finish __P((void*, int, int, int)); 205 void pciide_irqack __P((struct channel_softc *)); 206 void pciide_print_modes __P((struct pciide_channel *)); 207 208 struct pciide_product_desc { 209 u_int32_t ide_product; 210 int ide_flags; 211 const char *ide_name; 212 /* map and setup chip, probe drives */ 213 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 214 }; 215 216 /* Flags for ide_flags */ 217 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 218 219 /* Default product description for devices not known from this controller */ 220 const struct pciide_product_desc default_product_desc = { 221 0, 222 0, 223 "Generic PCI IDE controller", 224 default_chip_map, 225 }; 226 227 const struct pciide_product_desc pciide_intel_products[] = { 228 { PCI_PRODUCT_INTEL_82092AA, 229 0, 230 "Intel 82092AA IDE controller", 231 default_chip_map, 232 }, 233 { PCI_PRODUCT_INTEL_82371FB_IDE, 234 0, 235 "Intel 82371FB IDE controller (PIIX)", 236 piix_chip_map, 237 }, 238 { PCI_PRODUCT_INTEL_82371SB_IDE, 239 0, 240 "Intel 82371SB IDE Interface (PIIX3)", 241 piix_chip_map, 242 }, 243 { PCI_PRODUCT_INTEL_82371AB_IDE, 244 0, 245 "Intel 82371AB IDE controller (PIIX4)", 246 piix_chip_map, 247 }, 248 { PCI_PRODUCT_INTEL_82801AA_IDE, 249 0, 250 "Intel 82801AA IDE Controller (ICH)", 251 piix_chip_map, 252 }, 253 { PCI_PRODUCT_INTEL_82801AB_IDE, 254 0, 255 "Intel 82801AB IDE Controller (ICH0)", 256 piix_chip_map, 257 }, 258 { 0, 259 0, 260 NULL, 261 } 262 }; 263 264 const struct pciide_product_desc pciide_amd_products[] = { 265 { PCI_PRODUCT_AMD_PBC756_IDE, 266 0, 267 "Advanced Micro Devices AMD756 IDE Controller", 268 amd756_chip_map 269 }, 270 { 0, 271 0, 272 NULL, 273 } 274 }; 275 276 const struct pciide_product_desc pciide_cmd_products[] = { 277 { PCI_PRODUCT_CMDTECH_640, 278 0, 279 "CMD Technology PCI0640", 280 cmd_chip_map 281 }, 282 { PCI_PRODUCT_CMDTECH_643, 283 0, 284 "CMD Technology PCI0643", 285 cmd0643_9_chip_map, 286 }, 287 { PCI_PRODUCT_CMDTECH_646, 288 0, 289 "CMD Technology PCI0646", 290 cmd0643_9_chip_map, 291 }, 292 { PCI_PRODUCT_CMDTECH_648, 293 IDE_PCI_CLASS_OVERRIDE, 294 "CMD Technology PCI0648", 295 cmd0643_9_chip_map, 296 }, 297 { PCI_PRODUCT_CMDTECH_649, 298 IDE_PCI_CLASS_OVERRIDE, 299 "CMD Technology PCI0649", 300 cmd0643_9_chip_map, 301 }, 302 { 0, 303 0, 304 NULL, 305 } 306 }; 307 308 const struct pciide_product_desc pciide_via_products[] = { 309 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 310 0, 311 "VIA Tech VT82C586 IDE Controller", 312 apollo_chip_map, 313 }, 314 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 315 0, 316 "VIA Tech VT82C586A IDE Controller", 317 apollo_chip_map, 318 }, 319 { 0, 320 0, 321 NULL, 322 } 323 }; 324 325 const struct pciide_product_desc pciide_cypress_products[] = { 326 { PCI_PRODUCT_CONTAQ_82C693, 327 0, 328 "Cypress 82C693 IDE Controller", 329 cy693_chip_map, 330 }, 331 { 0, 332 0, 333 NULL, 334 } 335 }; 336 337 const struct pciide_product_desc pciide_sis_products[] = { 338 { PCI_PRODUCT_SIS_5597_IDE, 339 0, 340 "Silicon Integrated System 5597/5598 IDE controller", 341 sis_chip_map, 342 }, 343 { 0, 344 0, 345 NULL, 346 } 347 }; 348 349 const struct pciide_product_desc pciide_acer_products[] = { 350 { PCI_PRODUCT_ALI_M5229, 351 0, 352 "Acer Labs M5229 UDMA IDE Controller", 353 acer_chip_map, 354 }, 355 { 0, 356 0, 357 NULL, 358 } 359 }; 360 361 const struct pciide_product_desc pciide_promise_products[] = { 362 { PCI_PRODUCT_PROMISE_ULTRA33, 363 IDE_PCI_CLASS_OVERRIDE, 364 "Promise Ultra33/ATA Bus Master IDE Accelerator", 365 pdc202xx_chip_map, 366 }, 367 { PCI_PRODUCT_PROMISE_ULTRA66, 368 IDE_PCI_CLASS_OVERRIDE, 369 "Promise Ultra66/ATA Bus Master IDE Accelerator", 370 pdc202xx_chip_map, 371 }, 372 { PCI_PRODUCT_PROMISE_ULTRA100, 373 IDE_PCI_CLASS_OVERRIDE, 374 "Promise Ultra100/ATA Bus Master IDE Accelerator", 375 pdc202xx_chip_map, 376 }, 377 { PCI_PRODUCT_PROMISE_ULTRA100X, 378 IDE_PCI_CLASS_OVERRIDE, 379 "Promise Ultra100/ATA Bus Master IDE Accelerator", 380 pdc202xx_chip_map, 381 }, 382 { 0, 383 0, 384 NULL, 385 } 386 }; 387 388 const struct pciide_product_desc pciide_opti_products[] = { 389 { PCI_PRODUCT_OPTI_82C621, 390 0, 391 "OPTi 82c621 PCI IDE controller", 392 opti_chip_map, 393 }, 394 { PCI_PRODUCT_OPTI_82C568, 395 0, 396 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 397 opti_chip_map, 398 }, 399 { PCI_PRODUCT_OPTI_82D568, 400 0, 401 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 402 opti_chip_map, 403 }, 404 { 0, 405 0, 406 NULL, 407 } 408 }; 409 410 const struct pciide_product_desc pciide_triones_products[] = { 411 { PCI_PRODUCT_TRIONES_HPT366, 412 IDE_PCI_CLASS_OVERRIDE, 413 "Triones/Highpoint HPT366/370 IDE Controller", 414 hpt_chip_map, 415 }, 416 { 0, 417 0, 418 NULL, 419 } 420 }; 421 422 struct pciide_vendor_desc { 423 u_int32_t ide_vendor; 424 const struct pciide_product_desc *ide_products; 425 }; 426 427 const struct pciide_vendor_desc pciide_vendors[] = { 428 { PCI_VENDOR_INTEL, pciide_intel_products }, 429 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 430 { PCI_VENDOR_VIATECH, pciide_via_products }, 431 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 432 { PCI_VENDOR_SIS, pciide_sis_products }, 433 { PCI_VENDOR_ALI, pciide_acer_products }, 434 { PCI_VENDOR_PROMISE, pciide_promise_products }, 435 { PCI_VENDOR_AMD, pciide_amd_products }, 436 { PCI_VENDOR_OPTI, pciide_opti_products }, 437 { PCI_VENDOR_TRIONES, pciide_triones_products }, 438 { 0, NULL } 439 }; 440 441 /* options passed via the 'flags' config keyword */ 442 #define PCIIDE_OPTIONS_DMA 0x01 443 444 int pciide_match __P((struct device *, struct cfdata *, void *)); 445 void pciide_attach __P((struct device *, struct device *, void *)); 446 447 struct cfattach pciide_ca = { 448 sizeof(struct pciide_softc), pciide_match, pciide_attach 449 }; 450 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 451 int pciide_mapregs_compat __P(( struct pci_attach_args *, 452 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 453 int pciide_mapregs_native __P((struct pci_attach_args *, 454 struct pciide_channel *, bus_size_t *, bus_size_t *, 455 int (*pci_intr) __P((void *)))); 456 void pciide_mapreg_dma __P((struct pciide_softc *, 457 struct pci_attach_args *)); 458 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 459 void pciide_mapchan __P((struct pci_attach_args *, 460 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 461 int (*pci_intr) __P((void *)))); 462 int pciide_chan_candisable __P((struct pciide_channel *)); 463 void pciide_map_compat_intr __P(( struct pci_attach_args *, 464 struct pciide_channel *, int, int)); 465 int pciide_print __P((void *, const char *pnp)); 466 int pciide_compat_intr __P((void *)); 467 int pciide_pci_intr __P((void *)); 468 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 469 470 const struct pciide_product_desc * 471 pciide_lookup_product(id) 472 u_int32_t id; 473 { 474 const struct pciide_product_desc *pp; 475 const struct pciide_vendor_desc *vp; 476 477 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 478 if (PCI_VENDOR(id) == vp->ide_vendor) 479 break; 480 481 if ((pp = vp->ide_products) == NULL) 482 return NULL; 483 484 for (; pp->ide_name != NULL; pp++) 485 if (PCI_PRODUCT(id) == pp->ide_product) 486 break; 487 488 if (pp->ide_name == NULL) 489 return NULL; 490 return pp; 491 } 492 493 int 494 pciide_match(parent, match, aux) 495 struct device *parent; 496 struct cfdata *match; 497 void *aux; 498 { 499 struct pci_attach_args *pa = aux; 500 const struct pciide_product_desc *pp; 501 502 /* 503 * Check the ID register to see that it's a PCI IDE controller. 504 * If it is, we assume that we can deal with it; it _should_ 505 * work in a standardized way... 506 */ 507 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 508 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 509 return (1); 510 } 511 512 /* 513 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 514 * controllers. Let see if we can deal with it anyway. 515 */ 516 pp = pciide_lookup_product(pa->pa_id); 517 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 518 return (1); 519 } 520 521 return (0); 522 } 523 524 void 525 pciide_attach(parent, self, aux) 526 struct device *parent, *self; 527 void *aux; 528 { 529 struct pci_attach_args *pa = aux; 530 pci_chipset_tag_t pc = pa->pa_pc; 531 pcitag_t tag = pa->pa_tag; 532 struct pciide_softc *sc = (struct pciide_softc *)self; 533 pcireg_t csr; 534 char devinfo[256]; 535 const char *displaydev; 536 537 sc->sc_pp = pciide_lookup_product(pa->pa_id); 538 if (sc->sc_pp == NULL) { 539 sc->sc_pp = &default_product_desc; 540 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 541 displaydev = devinfo; 542 } else 543 displaydev = sc->sc_pp->ide_name; 544 545 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 546 547 sc->sc_pc = pa->pa_pc; 548 sc->sc_tag = pa->pa_tag; 549 #ifdef WDCDEBUG 550 if (wdcdebug_pciide_mask & DEBUG_PROBE) 551 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 552 #endif 553 sc->sc_pp->chip_map(sc, pa); 554 555 if (sc->sc_dma_ok) { 556 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 557 csr |= PCI_COMMAND_MASTER_ENABLE; 558 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 559 } 560 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 561 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 562 } 563 564 /* tell wether the chip is enabled or not */ 565 int 566 pciide_chipen(sc, pa) 567 struct pciide_softc *sc; 568 struct pci_attach_args *pa; 569 { 570 pcireg_t csr; 571 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 572 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 573 PCI_COMMAND_STATUS_REG); 574 printf("%s: device disabled (at %s)\n", 575 sc->sc_wdcdev.sc_dev.dv_xname, 576 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 577 "device" : "bridge"); 578 return 0; 579 } 580 return 1; 581 } 582 583 int 584 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 585 struct pci_attach_args *pa; 586 struct pciide_channel *cp; 587 int compatchan; 588 bus_size_t *cmdsizep, *ctlsizep; 589 { 590 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 591 struct channel_softc *wdc_cp = &cp->wdc_channel; 592 593 cp->compat = 1; 594 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 595 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 596 597 wdc_cp->cmd_iot = pa->pa_iot; 598 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 599 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 600 printf("%s: couldn't map %s channel cmd regs\n", 601 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 602 return (0); 603 } 604 605 wdc_cp->ctl_iot = pa->pa_iot; 606 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 607 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 608 printf("%s: couldn't map %s channel ctl regs\n", 609 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 610 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 611 PCIIDE_COMPAT_CMD_SIZE); 612 return (0); 613 } 614 615 return (1); 616 } 617 618 int 619 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 620 struct pci_attach_args * pa; 621 struct pciide_channel *cp; 622 bus_size_t *cmdsizep, *ctlsizep; 623 int (*pci_intr) __P((void *)); 624 { 625 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 626 struct channel_softc *wdc_cp = &cp->wdc_channel; 627 const char *intrstr; 628 pci_intr_handle_t intrhandle; 629 630 cp->compat = 0; 631 632 if (sc->sc_pci_ih == NULL) { 633 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 634 pa->pa_intrline, &intrhandle) != 0) { 635 printf("%s: couldn't map native-PCI interrupt\n", 636 sc->sc_wdcdev.sc_dev.dv_xname); 637 return 0; 638 } 639 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 640 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 641 intrhandle, IPL_BIO, pci_intr, sc); 642 if (sc->sc_pci_ih != NULL) { 643 printf("%s: using %s for native-PCI interrupt\n", 644 sc->sc_wdcdev.sc_dev.dv_xname, 645 intrstr ? intrstr : "unknown interrupt"); 646 } else { 647 printf("%s: couldn't establish native-PCI interrupt", 648 sc->sc_wdcdev.sc_dev.dv_xname); 649 if (intrstr != NULL) 650 printf(" at %s", intrstr); 651 printf("\n"); 652 return 0; 653 } 654 } 655 cp->ih = sc->sc_pci_ih; 656 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 657 PCI_MAPREG_TYPE_IO, 0, 658 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 659 printf("%s: couldn't map %s channel cmd regs\n", 660 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 661 return 0; 662 } 663 664 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 665 PCI_MAPREG_TYPE_IO, 0, 666 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 667 printf("%s: couldn't map %s channel ctl regs\n", 668 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 669 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 670 return 0; 671 } 672 return (1); 673 } 674 675 void 676 pciide_mapreg_dma(sc, pa) 677 struct pciide_softc *sc; 678 struct pci_attach_args *pa; 679 { 680 pcireg_t maptype; 681 682 /* 683 * Map DMA registers 684 * 685 * Note that sc_dma_ok is the right variable to test to see if 686 * DMA can be done. If the interface doesn't support DMA, 687 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 688 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 689 * non-zero if the interface supports DMA and the registers 690 * could be mapped. 691 * 692 * XXX Note that despite the fact that the Bus Master IDE specs 693 * XXX say that "The bus master IDE function uses 16 bytes of IO 694 * XXX space," some controllers (at least the United 695 * XXX Microelectronics UM8886BF) place it in memory space. 696 */ 697 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 698 PCIIDE_REG_BUS_MASTER_DMA); 699 700 switch (maptype) { 701 case PCI_MAPREG_TYPE_IO: 702 case PCI_MAPREG_MEM_TYPE_32BIT: 703 sc->sc_dma_ok = (pci_mapreg_map(pa, 704 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 705 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 706 sc->sc_dmat = pa->pa_dmat; 707 if (sc->sc_dma_ok == 0) { 708 printf(", but unused (couldn't map registers)"); 709 } else { 710 sc->sc_wdcdev.dma_arg = sc; 711 sc->sc_wdcdev.dma_init = pciide_dma_init; 712 sc->sc_wdcdev.dma_start = pciide_dma_start; 713 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 714 } 715 break; 716 717 default: 718 sc->sc_dma_ok = 0; 719 printf(", but unsupported register maptype (0x%x)", maptype); 720 } 721 } 722 723 int 724 pciide_compat_intr(arg) 725 void *arg; 726 { 727 struct pciide_channel *cp = arg; 728 729 #ifdef DIAGNOSTIC 730 /* should only be called for a compat channel */ 731 if (cp->compat == 0) 732 panic("pciide compat intr called for non-compat chan %p\n", cp); 733 #endif 734 return (wdcintr(&cp->wdc_channel)); 735 } 736 737 int 738 pciide_pci_intr(arg) 739 void *arg; 740 { 741 struct pciide_softc *sc = arg; 742 struct pciide_channel *cp; 743 struct channel_softc *wdc_cp; 744 int i, rv, crv; 745 746 rv = 0; 747 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 748 cp = &sc->pciide_channels[i]; 749 wdc_cp = &cp->wdc_channel; 750 751 /* If a compat channel skip. */ 752 if (cp->compat) 753 continue; 754 /* if this channel not waiting for intr, skip */ 755 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 756 continue; 757 758 crv = wdcintr(wdc_cp); 759 if (crv == 0) 760 ; /* leave rv alone */ 761 else if (crv == 1) 762 rv = 1; /* claim the intr */ 763 else if (rv == 0) /* crv should be -1 in this case */ 764 rv = crv; /* if we've done no better, take it */ 765 } 766 return (rv); 767 } 768 769 void 770 pciide_channel_dma_setup(cp) 771 struct pciide_channel *cp; 772 { 773 int drive; 774 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 775 struct ata_drive_datas *drvp; 776 777 for (drive = 0; drive < 2; drive++) { 778 drvp = &cp->wdc_channel.ch_drive[drive]; 779 /* If no drive, skip */ 780 if ((drvp->drive_flags & DRIVE) == 0) 781 continue; 782 /* setup DMA if needed */ 783 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 784 (drvp->drive_flags & DRIVE_UDMA) == 0) || 785 sc->sc_dma_ok == 0) { 786 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 787 continue; 788 } 789 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 790 != 0) { 791 /* Abort DMA setup */ 792 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 793 continue; 794 } 795 } 796 } 797 798 int 799 pciide_dma_table_setup(sc, channel, drive) 800 struct pciide_softc *sc; 801 int channel, drive; 802 { 803 bus_dma_segment_t seg; 804 int error, rseg; 805 const bus_size_t dma_table_size = 806 sizeof(struct idedma_table) * NIDEDMA_TABLES; 807 struct pciide_dma_maps *dma_maps = 808 &sc->pciide_channels[channel].dma_maps[drive]; 809 810 /* If table was already allocated, just return */ 811 if (dma_maps->dma_table) 812 return 0; 813 814 /* Allocate memory for the DMA tables and map it */ 815 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 816 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 817 BUS_DMA_NOWAIT)) != 0) { 818 printf("%s:%d: unable to allocate table DMA for " 819 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 820 channel, drive, error); 821 return error; 822 } 823 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 824 dma_table_size, 825 (caddr_t *)&dma_maps->dma_table, 826 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 827 printf("%s:%d: unable to map table DMA for" 828 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 829 channel, drive, error); 830 return error; 831 } 832 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 833 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 834 seg.ds_addr), DEBUG_PROBE); 835 836 /* Create and load table DMA map for this disk */ 837 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 838 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 839 &dma_maps->dmamap_table)) != 0) { 840 printf("%s:%d: unable to create table DMA map for " 841 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 842 channel, drive, error); 843 return error; 844 } 845 if ((error = bus_dmamap_load(sc->sc_dmat, 846 dma_maps->dmamap_table, 847 dma_maps->dma_table, 848 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 849 printf("%s:%d: unable to load table DMA map for " 850 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 851 channel, drive, error); 852 return error; 853 } 854 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 855 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 856 /* Create a xfer DMA map for this drive */ 857 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 858 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 859 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 860 &dma_maps->dmamap_xfer)) != 0) { 861 printf("%s:%d: unable to create xfer DMA map for " 862 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 863 channel, drive, error); 864 return error; 865 } 866 return 0; 867 } 868 869 int 870 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 871 void *v; 872 int channel, drive; 873 void *databuf; 874 size_t datalen; 875 int flags; 876 { 877 struct pciide_softc *sc = v; 878 int error, seg; 879 struct pciide_dma_maps *dma_maps = 880 &sc->pciide_channels[channel].dma_maps[drive]; 881 882 error = bus_dmamap_load(sc->sc_dmat, 883 dma_maps->dmamap_xfer, 884 databuf, datalen, NULL, BUS_DMA_NOWAIT); 885 if (error) { 886 printf("%s:%d: unable to load xfer DMA map for" 887 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 888 channel, drive, error); 889 return error; 890 } 891 892 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 893 dma_maps->dmamap_xfer->dm_mapsize, 894 (flags & WDC_DMA_READ) ? 895 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 896 897 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 898 #ifdef DIAGNOSTIC 899 /* A segment must not cross a 64k boundary */ 900 { 901 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 902 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 903 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 904 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 905 printf("pciide_dma: segment %d physical addr 0x%lx" 906 " len 0x%lx not properly aligned\n", 907 seg, phys, len); 908 panic("pciide_dma: buf align"); 909 } 910 } 911 #endif 912 dma_maps->dma_table[seg].base_addr = 913 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 914 dma_maps->dma_table[seg].byte_count = 915 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 916 IDEDMA_BYTE_COUNT_MASK); 917 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 918 seg, le32toh(dma_maps->dma_table[seg].byte_count), 919 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 920 921 } 922 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 923 htole32(IDEDMA_BYTE_COUNT_EOT); 924 925 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 926 dma_maps->dmamap_table->dm_mapsize, 927 BUS_DMASYNC_PREWRITE); 928 929 /* Maps are ready. Start DMA function */ 930 #ifdef DIAGNOSTIC 931 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 932 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 933 dma_maps->dmamap_table->dm_segs[0].ds_addr); 934 panic("pciide_dma_init: table align"); 935 } 936 #endif 937 938 /* Clear status bits */ 939 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 940 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 941 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 942 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 943 /* Write table addr */ 944 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 945 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 946 dma_maps->dmamap_table->dm_segs[0].ds_addr); 947 /* set read/write */ 948 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 949 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 950 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 951 /* remember flags */ 952 dma_maps->dma_flags = flags; 953 return 0; 954 } 955 956 void 957 pciide_dma_start(v, channel, drive) 958 void *v; 959 int channel, drive; 960 { 961 struct pciide_softc *sc = v; 962 963 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 964 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 965 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 966 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 967 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 968 } 969 970 int 971 pciide_dma_finish(v, channel, drive, force) 972 void *v; 973 int channel, drive; 974 int force; 975 { 976 struct pciide_softc *sc = v; 977 u_int8_t status; 978 int error = 0; 979 struct pciide_dma_maps *dma_maps = 980 &sc->pciide_channels[channel].dma_maps[drive]; 981 982 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 983 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 984 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 985 DEBUG_XFERS); 986 987 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 988 return WDC_DMAST_NOIRQ; 989 990 /* stop DMA channel */ 991 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 992 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 993 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 994 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 995 996 /* Unload the map of the data buffer */ 997 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 998 dma_maps->dmamap_xfer->dm_mapsize, 999 (dma_maps->dma_flags & WDC_DMA_READ) ? 1000 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1001 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1002 1003 if ((status & IDEDMA_CTL_ERR) != 0) { 1004 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1005 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1006 error |= WDC_DMAST_ERR; 1007 } 1008 1009 if ((status & IDEDMA_CTL_INTR) == 0) { 1010 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1011 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1012 drive, status); 1013 error |= WDC_DMAST_NOIRQ; 1014 } 1015 1016 if ((status & IDEDMA_CTL_ACT) != 0) { 1017 /* data underrun, may be a valid condition for ATAPI */ 1018 error |= WDC_DMAST_UNDER; 1019 } 1020 return error; 1021 } 1022 1023 void 1024 pciide_irqack(chp) 1025 struct channel_softc *chp; 1026 { 1027 struct pciide_channel *cp = (struct pciide_channel*)chp; 1028 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1029 1030 /* clear status bits in IDE DMA registers */ 1031 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1032 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1033 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1034 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1035 } 1036 1037 /* some common code used by several chip_map */ 1038 int 1039 pciide_chansetup(sc, channel, interface) 1040 struct pciide_softc *sc; 1041 int channel; 1042 pcireg_t interface; 1043 { 1044 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1045 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1046 cp->name = PCIIDE_CHANNEL_NAME(channel); 1047 cp->wdc_channel.channel = channel; 1048 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1049 cp->wdc_channel.ch_queue = 1050 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1051 if (cp->wdc_channel.ch_queue == NULL) { 1052 printf("%s %s channel: " 1053 "can't allocate memory for command queue", 1054 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1055 return 0; 1056 } 1057 printf("%s: %s channel %s to %s mode\n", 1058 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1059 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1060 "configured" : "wired", 1061 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1062 "native-PCI" : "compatibility"); 1063 return 1; 1064 } 1065 1066 /* some common code used by several chip channel_map */ 1067 void 1068 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1069 struct pci_attach_args *pa; 1070 struct pciide_channel *cp; 1071 pcireg_t interface; 1072 bus_size_t *cmdsizep, *ctlsizep; 1073 int (*pci_intr) __P((void *)); 1074 { 1075 struct channel_softc *wdc_cp = &cp->wdc_channel; 1076 1077 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1078 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1079 pci_intr); 1080 else 1081 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1082 wdc_cp->channel, cmdsizep, ctlsizep); 1083 1084 if (cp->hw_ok == 0) 1085 return; 1086 wdc_cp->data32iot = wdc_cp->cmd_iot; 1087 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1088 wdcattach(wdc_cp); 1089 } 1090 1091 /* 1092 * Generic code to call to know if a channel can be disabled. Return 1 1093 * if channel can be disabled, 0 if not 1094 */ 1095 int 1096 pciide_chan_candisable(cp) 1097 struct pciide_channel *cp; 1098 { 1099 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1100 struct channel_softc *wdc_cp = &cp->wdc_channel; 1101 1102 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1103 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1104 printf("%s: disabling %s channel (no drives)\n", 1105 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1106 cp->hw_ok = 0; 1107 return 1; 1108 } 1109 return 0; 1110 } 1111 1112 /* 1113 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1114 * Set hw_ok=0 on failure 1115 */ 1116 void 1117 pciide_map_compat_intr(pa, cp, compatchan, interface) 1118 struct pci_attach_args *pa; 1119 struct pciide_channel *cp; 1120 int compatchan, interface; 1121 { 1122 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1123 struct channel_softc *wdc_cp = &cp->wdc_channel; 1124 1125 if (cp->hw_ok == 0) 1126 return; 1127 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1128 return; 1129 1130 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1131 pa, compatchan, pciide_compat_intr, cp); 1132 if (cp->ih == NULL) { 1133 printf("%s: no compatibility interrupt for use by %s " 1134 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1135 cp->hw_ok = 0; 1136 } 1137 } 1138 1139 void 1140 pciide_print_modes(cp) 1141 struct pciide_channel *cp; 1142 { 1143 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1144 int drive; 1145 struct channel_softc *chp; 1146 struct ata_drive_datas *drvp; 1147 1148 chp = &cp->wdc_channel; 1149 for (drive = 0; drive < 2; drive++) { 1150 drvp = &chp->ch_drive[drive]; 1151 if ((drvp->drive_flags & DRIVE) == 0) 1152 continue; 1153 printf("%s(%s:%d:%d): using PIO mode %d", 1154 drvp->drv_softc->dv_xname, 1155 sc->sc_wdcdev.sc_dev.dv_xname, 1156 chp->channel, drive, drvp->PIO_mode); 1157 if (drvp->drive_flags & DRIVE_DMA) 1158 printf(", DMA mode %d", drvp->DMA_mode); 1159 if (drvp->drive_flags & DRIVE_UDMA) 1160 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1161 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1162 printf(" (using DMA data transfers)"); 1163 printf("\n"); 1164 } 1165 } 1166 1167 void 1168 default_chip_map(sc, pa) 1169 struct pciide_softc *sc; 1170 struct pci_attach_args *pa; 1171 { 1172 struct pciide_channel *cp; 1173 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1174 pcireg_t csr; 1175 int channel, drive; 1176 struct ata_drive_datas *drvp; 1177 u_int8_t idedma_ctl; 1178 bus_size_t cmdsize, ctlsize; 1179 char *failreason; 1180 1181 if (pciide_chipen(sc, pa) == 0) 1182 return; 1183 1184 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1185 printf("%s: bus-master DMA support present", 1186 sc->sc_wdcdev.sc_dev.dv_xname); 1187 if (sc->sc_pp == &default_product_desc && 1188 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1189 PCIIDE_OPTIONS_DMA) == 0) { 1190 printf(", but unused (no driver support)"); 1191 sc->sc_dma_ok = 0; 1192 } else { 1193 pciide_mapreg_dma(sc, pa); 1194 if (sc->sc_dma_ok != 0) 1195 printf(", used without full driver " 1196 "support"); 1197 } 1198 } else { 1199 printf("%s: hardware does not support DMA", 1200 sc->sc_wdcdev.sc_dev.dv_xname); 1201 sc->sc_dma_ok = 0; 1202 } 1203 printf("\n"); 1204 if (sc->sc_dma_ok) { 1205 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1206 sc->sc_wdcdev.irqack = pciide_irqack; 1207 } 1208 sc->sc_wdcdev.PIO_cap = 0; 1209 sc->sc_wdcdev.DMA_cap = 0; 1210 1211 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1212 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1213 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1214 1215 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1216 cp = &sc->pciide_channels[channel]; 1217 if (pciide_chansetup(sc, channel, interface) == 0) 1218 continue; 1219 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1220 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1221 &ctlsize, pciide_pci_intr); 1222 } else { 1223 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1224 channel, &cmdsize, &ctlsize); 1225 } 1226 if (cp->hw_ok == 0) 1227 continue; 1228 /* 1229 * Check to see if something appears to be there. 1230 */ 1231 failreason = NULL; 1232 if (!wdcprobe(&cp->wdc_channel)) { 1233 failreason = "not responding; disabled or no drives?"; 1234 goto next; 1235 } 1236 /* 1237 * Now, make sure it's actually attributable to this PCI IDE 1238 * channel by trying to access the channel again while the 1239 * PCI IDE controller's I/O space is disabled. (If the 1240 * channel no longer appears to be there, it belongs to 1241 * this controller.) YUCK! 1242 */ 1243 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1244 PCI_COMMAND_STATUS_REG); 1245 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1246 csr & ~PCI_COMMAND_IO_ENABLE); 1247 if (wdcprobe(&cp->wdc_channel)) 1248 failreason = "other hardware responding at addresses"; 1249 pci_conf_write(sc->sc_pc, sc->sc_tag, 1250 PCI_COMMAND_STATUS_REG, csr); 1251 next: 1252 if (failreason) { 1253 printf("%s: %s channel ignored (%s)\n", 1254 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1255 failreason); 1256 cp->hw_ok = 0; 1257 bus_space_unmap(cp->wdc_channel.cmd_iot, 1258 cp->wdc_channel.cmd_ioh, cmdsize); 1259 bus_space_unmap(cp->wdc_channel.ctl_iot, 1260 cp->wdc_channel.ctl_ioh, ctlsize); 1261 } else { 1262 pciide_map_compat_intr(pa, cp, channel, interface); 1263 } 1264 if (cp->hw_ok) { 1265 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1266 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1267 wdcattach(&cp->wdc_channel); 1268 } 1269 } 1270 1271 if (sc->sc_dma_ok == 0) 1272 return; 1273 1274 /* Allocate DMA maps */ 1275 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1276 idedma_ctl = 0; 1277 cp = &sc->pciide_channels[channel]; 1278 for (drive = 0; drive < 2; drive++) { 1279 drvp = &cp->wdc_channel.ch_drive[drive]; 1280 /* If no drive, skip */ 1281 if ((drvp->drive_flags & DRIVE) == 0) 1282 continue; 1283 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1284 continue; 1285 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1286 /* Abort DMA setup */ 1287 printf("%s:%d:%d: can't allocate DMA maps, " 1288 "using PIO transfers\n", 1289 sc->sc_wdcdev.sc_dev.dv_xname, 1290 channel, drive); 1291 drvp->drive_flags &= ~DRIVE_DMA; 1292 } 1293 printf("%s:%d:%d: using DMA data transfers\n", 1294 sc->sc_wdcdev.sc_dev.dv_xname, 1295 channel, drive); 1296 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1297 } 1298 if (idedma_ctl != 0) { 1299 /* Add software bits in status register */ 1300 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1301 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1302 idedma_ctl); 1303 } 1304 } 1305 } 1306 1307 void 1308 piix_chip_map(sc, pa) 1309 struct pciide_softc *sc; 1310 struct pci_attach_args *pa; 1311 { 1312 struct pciide_channel *cp; 1313 int channel; 1314 u_int32_t idetim; 1315 bus_size_t cmdsize, ctlsize; 1316 1317 if (pciide_chipen(sc, pa) == 0) 1318 return; 1319 1320 printf("%s: bus-master DMA support present", 1321 sc->sc_wdcdev.sc_dev.dv_xname); 1322 pciide_mapreg_dma(sc, pa); 1323 printf("\n"); 1324 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1325 WDC_CAPABILITY_MODE; 1326 if (sc->sc_dma_ok) { 1327 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1328 sc->sc_wdcdev.irqack = pciide_irqack; 1329 switch(sc->sc_pp->ide_product) { 1330 case PCI_PRODUCT_INTEL_82371AB_IDE: 1331 case PCI_PRODUCT_INTEL_82801AA_IDE: 1332 case PCI_PRODUCT_INTEL_82801AB_IDE: 1333 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1334 } 1335 } 1336 sc->sc_wdcdev.PIO_cap = 4; 1337 sc->sc_wdcdev.DMA_cap = 2; 1338 sc->sc_wdcdev.UDMA_cap = 1339 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1340 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1341 sc->sc_wdcdev.set_modes = piix_setup_channel; 1342 else 1343 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1344 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1345 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1346 1347 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1348 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1349 DEBUG_PROBE); 1350 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1351 WDCDEBUG_PRINT((", sidetim=0x%x", 1352 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1353 DEBUG_PROBE); 1354 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1355 WDCDEBUG_PRINT((", udamreg 0x%x", 1356 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1357 DEBUG_PROBE); 1358 } 1359 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1360 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1361 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1362 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1363 DEBUG_PROBE); 1364 } 1365 1366 } 1367 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1368 1369 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1370 cp = &sc->pciide_channels[channel]; 1371 /* PIIX is compat-only */ 1372 if (pciide_chansetup(sc, channel, 0) == 0) 1373 continue; 1374 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1375 if ((PIIX_IDETIM_READ(idetim, channel) & 1376 PIIX_IDETIM_IDE) == 0) { 1377 printf("%s: %s channel ignored (disabled)\n", 1378 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1379 continue; 1380 } 1381 /* PIIX are compat-only pciide devices */ 1382 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1383 if (cp->hw_ok == 0) 1384 continue; 1385 if (pciide_chan_candisable(cp)) { 1386 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1387 channel); 1388 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1389 idetim); 1390 } 1391 pciide_map_compat_intr(pa, cp, channel, 0); 1392 if (cp->hw_ok == 0) 1393 continue; 1394 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1395 } 1396 1397 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1398 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1399 DEBUG_PROBE); 1400 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1401 WDCDEBUG_PRINT((", sidetim=0x%x", 1402 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1403 DEBUG_PROBE); 1404 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1405 WDCDEBUG_PRINT((", udamreg 0x%x", 1406 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1407 DEBUG_PROBE); 1408 } 1409 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1410 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1411 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1412 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1413 DEBUG_PROBE); 1414 } 1415 } 1416 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1417 } 1418 1419 void 1420 piix_setup_channel(chp) 1421 struct channel_softc *chp; 1422 { 1423 u_int8_t mode[2], drive; 1424 u_int32_t oidetim, idetim, idedma_ctl; 1425 struct pciide_channel *cp = (struct pciide_channel*)chp; 1426 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1427 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1428 1429 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1430 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1431 idedma_ctl = 0; 1432 1433 /* set up new idetim: Enable IDE registers decode */ 1434 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1435 chp->channel); 1436 1437 /* setup DMA */ 1438 pciide_channel_dma_setup(cp); 1439 1440 /* 1441 * Here we have to mess up with drives mode: PIIX can't have 1442 * different timings for master and slave drives. 1443 * We need to find the best combination. 1444 */ 1445 1446 /* If both drives supports DMA, take the lower mode */ 1447 if ((drvp[0].drive_flags & DRIVE_DMA) && 1448 (drvp[1].drive_flags & DRIVE_DMA)) { 1449 mode[0] = mode[1] = 1450 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1451 drvp[0].DMA_mode = mode[0]; 1452 drvp[1].DMA_mode = mode[1]; 1453 goto ok; 1454 } 1455 /* 1456 * If only one drive supports DMA, use its mode, and 1457 * put the other one in PIO mode 0 if mode not compatible 1458 */ 1459 if (drvp[0].drive_flags & DRIVE_DMA) { 1460 mode[0] = drvp[0].DMA_mode; 1461 mode[1] = drvp[1].PIO_mode; 1462 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1463 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1464 mode[1] = drvp[1].PIO_mode = 0; 1465 goto ok; 1466 } 1467 if (drvp[1].drive_flags & DRIVE_DMA) { 1468 mode[1] = drvp[1].DMA_mode; 1469 mode[0] = drvp[0].PIO_mode; 1470 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1471 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1472 mode[0] = drvp[0].PIO_mode = 0; 1473 goto ok; 1474 } 1475 /* 1476 * If both drives are not DMA, takes the lower mode, unless 1477 * one of them is PIO mode < 2 1478 */ 1479 if (drvp[0].PIO_mode < 2) { 1480 mode[0] = drvp[0].PIO_mode = 0; 1481 mode[1] = drvp[1].PIO_mode; 1482 } else if (drvp[1].PIO_mode < 2) { 1483 mode[1] = drvp[1].PIO_mode = 0; 1484 mode[0] = drvp[0].PIO_mode; 1485 } else { 1486 mode[0] = mode[1] = 1487 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1488 drvp[0].PIO_mode = mode[0]; 1489 drvp[1].PIO_mode = mode[1]; 1490 } 1491 ok: /* The modes are setup */ 1492 for (drive = 0; drive < 2; drive++) { 1493 if (drvp[drive].drive_flags & DRIVE_DMA) { 1494 idetim |= piix_setup_idetim_timings( 1495 mode[drive], 1, chp->channel); 1496 goto end; 1497 } 1498 } 1499 /* If we are there, none of the drives are DMA */ 1500 if (mode[0] >= 2) 1501 idetim |= piix_setup_idetim_timings( 1502 mode[0], 0, chp->channel); 1503 else 1504 idetim |= piix_setup_idetim_timings( 1505 mode[1], 0, chp->channel); 1506 end: /* 1507 * timing mode is now set up in the controller. Enable 1508 * it per-drive 1509 */ 1510 for (drive = 0; drive < 2; drive++) { 1511 /* If no drive, skip */ 1512 if ((drvp[drive].drive_flags & DRIVE) == 0) 1513 continue; 1514 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1515 if (drvp[drive].drive_flags & DRIVE_DMA) 1516 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1517 } 1518 if (idedma_ctl != 0) { 1519 /* Add software bits in status register */ 1520 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1521 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1522 idedma_ctl); 1523 } 1524 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1525 pciide_print_modes(cp); 1526 } 1527 1528 void 1529 piix3_4_setup_channel(chp) 1530 struct channel_softc *chp; 1531 { 1532 struct ata_drive_datas *drvp; 1533 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1534 struct pciide_channel *cp = (struct pciide_channel*)chp; 1535 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1536 int drive; 1537 int channel = chp->channel; 1538 1539 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1540 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1541 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1542 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1543 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1544 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1545 PIIX_SIDETIM_RTC_MASK(channel)); 1546 1547 idedma_ctl = 0; 1548 /* If channel disabled, no need to go further */ 1549 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1550 return; 1551 /* set up new idetim: Enable IDE registers decode */ 1552 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1553 1554 /* setup DMA if needed */ 1555 pciide_channel_dma_setup(cp); 1556 1557 for (drive = 0; drive < 2; drive++) { 1558 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1559 PIIX_UDMATIM_SET(0x3, channel, drive)); 1560 drvp = &chp->ch_drive[drive]; 1561 /* If no drive, skip */ 1562 if ((drvp->drive_flags & DRIVE) == 0) 1563 continue; 1564 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1565 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1566 goto pio; 1567 1568 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1569 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1570 ideconf |= PIIX_CONFIG_PINGPONG; 1571 } 1572 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1573 /* setup Ultra/66 */ 1574 if (drvp->UDMA_mode > 2 && 1575 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1576 drvp->UDMA_mode = 2; 1577 if (drvp->UDMA_mode > 2) 1578 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1579 else 1580 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1581 } 1582 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1583 (drvp->drive_flags & DRIVE_UDMA)) { 1584 /* use Ultra/DMA */ 1585 drvp->drive_flags &= ~DRIVE_DMA; 1586 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1587 udmareg |= PIIX_UDMATIM_SET( 1588 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1589 } else { 1590 /* use Multiword DMA */ 1591 drvp->drive_flags &= ~DRIVE_UDMA; 1592 if (drive == 0) { 1593 idetim |= piix_setup_idetim_timings( 1594 drvp->DMA_mode, 1, channel); 1595 } else { 1596 sidetim |= piix_setup_sidetim_timings( 1597 drvp->DMA_mode, 1, channel); 1598 idetim =PIIX_IDETIM_SET(idetim, 1599 PIIX_IDETIM_SITRE, channel); 1600 } 1601 } 1602 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1603 1604 pio: /* use PIO mode */ 1605 idetim |= piix_setup_idetim_drvs(drvp); 1606 if (drive == 0) { 1607 idetim |= piix_setup_idetim_timings( 1608 drvp->PIO_mode, 0, channel); 1609 } else { 1610 sidetim |= piix_setup_sidetim_timings( 1611 drvp->PIO_mode, 0, channel); 1612 idetim =PIIX_IDETIM_SET(idetim, 1613 PIIX_IDETIM_SITRE, channel); 1614 } 1615 } 1616 if (idedma_ctl != 0) { 1617 /* Add software bits in status register */ 1618 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1619 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1620 idedma_ctl); 1621 } 1622 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1623 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1624 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1625 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1626 pciide_print_modes(cp); 1627 } 1628 1629 1630 /* setup ISP and RTC fields, based on mode */ 1631 static u_int32_t 1632 piix_setup_idetim_timings(mode, dma, channel) 1633 u_int8_t mode; 1634 u_int8_t dma; 1635 u_int8_t channel; 1636 { 1637 1638 if (dma) 1639 return PIIX_IDETIM_SET(0, 1640 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1641 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1642 channel); 1643 else 1644 return PIIX_IDETIM_SET(0, 1645 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1646 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1647 channel); 1648 } 1649 1650 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1651 static u_int32_t 1652 piix_setup_idetim_drvs(drvp) 1653 struct ata_drive_datas *drvp; 1654 { 1655 u_int32_t ret = 0; 1656 struct channel_softc *chp = drvp->chnl_softc; 1657 u_int8_t channel = chp->channel; 1658 u_int8_t drive = drvp->drive; 1659 1660 /* 1661 * If drive is using UDMA, timings setups are independant 1662 * So just check DMA and PIO here. 1663 */ 1664 if (drvp->drive_flags & DRIVE_DMA) { 1665 /* if mode = DMA mode 0, use compatible timings */ 1666 if ((drvp->drive_flags & DRIVE_DMA) && 1667 drvp->DMA_mode == 0) { 1668 drvp->PIO_mode = 0; 1669 return ret; 1670 } 1671 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1672 /* 1673 * PIO and DMA timings are the same, use fast timings for PIO 1674 * too, else use compat timings. 1675 */ 1676 if ((piix_isp_pio[drvp->PIO_mode] != 1677 piix_isp_dma[drvp->DMA_mode]) || 1678 (piix_rtc_pio[drvp->PIO_mode] != 1679 piix_rtc_dma[drvp->DMA_mode])) 1680 drvp->PIO_mode = 0; 1681 /* if PIO mode <= 2, use compat timings for PIO */ 1682 if (drvp->PIO_mode <= 2) { 1683 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1684 channel); 1685 return ret; 1686 } 1687 } 1688 1689 /* 1690 * Now setup PIO modes. If mode < 2, use compat timings. 1691 * Else enable fast timings. Enable IORDY and prefetch/post 1692 * if PIO mode >= 3. 1693 */ 1694 1695 if (drvp->PIO_mode < 2) 1696 return ret; 1697 1698 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1699 if (drvp->PIO_mode >= 3) { 1700 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1701 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1702 } 1703 return ret; 1704 } 1705 1706 /* setup values in SIDETIM registers, based on mode */ 1707 static u_int32_t 1708 piix_setup_sidetim_timings(mode, dma, channel) 1709 u_int8_t mode; 1710 u_int8_t dma; 1711 u_int8_t channel; 1712 { 1713 if (dma) 1714 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1715 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1716 else 1717 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1718 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1719 } 1720 1721 void 1722 amd756_chip_map(sc, pa) 1723 struct pciide_softc *sc; 1724 struct pci_attach_args *pa; 1725 { 1726 struct pciide_channel *cp; 1727 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1728 int channel; 1729 pcireg_t chanenable; 1730 bus_size_t cmdsize, ctlsize; 1731 1732 if (pciide_chipen(sc, pa) == 0) 1733 return; 1734 printf("%s: bus-master DMA support present", 1735 sc->sc_wdcdev.sc_dev.dv_xname); 1736 pciide_mapreg_dma(sc, pa); 1737 printf("\n"); 1738 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1739 WDC_CAPABILITY_MODE; 1740 if (sc->sc_dma_ok) { 1741 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1742 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1743 sc->sc_wdcdev.irqack = pciide_irqack; 1744 } 1745 sc->sc_wdcdev.PIO_cap = 4; 1746 sc->sc_wdcdev.DMA_cap = 2; 1747 sc->sc_wdcdev.UDMA_cap = 4; 1748 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1749 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1750 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1751 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1752 1753 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1754 DEBUG_PROBE); 1755 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1756 cp = &sc->pciide_channels[channel]; 1757 if (pciide_chansetup(sc, channel, interface) == 0) 1758 continue; 1759 1760 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1761 printf("%s: %s channel ignored (disabled)\n", 1762 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1763 continue; 1764 } 1765 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1766 pciide_pci_intr); 1767 1768 if (pciide_chan_candisable(cp)) 1769 chanenable &= ~AMD756_CHAN_EN(channel); 1770 pciide_map_compat_intr(pa, cp, channel, interface); 1771 if (cp->hw_ok == 0) 1772 continue; 1773 1774 amd756_setup_channel(&cp->wdc_channel); 1775 } 1776 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1777 chanenable); 1778 return; 1779 } 1780 1781 void 1782 amd756_setup_channel(chp) 1783 struct channel_softc *chp; 1784 { 1785 u_int32_t udmatim_reg, datatim_reg; 1786 u_int8_t idedma_ctl; 1787 int mode, drive; 1788 struct ata_drive_datas *drvp; 1789 struct pciide_channel *cp = (struct pciide_channel*)chp; 1790 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1791 #ifndef PCIIDE_AMD756_ENABLEDMA 1792 int rev = PCI_REVISION( 1793 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1794 #endif 1795 1796 idedma_ctl = 0; 1797 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1798 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1799 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1800 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1801 1802 /* setup DMA if needed */ 1803 pciide_channel_dma_setup(cp); 1804 1805 for (drive = 0; drive < 2; drive++) { 1806 drvp = &chp->ch_drive[drive]; 1807 /* If no drive, skip */ 1808 if ((drvp->drive_flags & DRIVE) == 0) 1809 continue; 1810 /* add timing values, setup DMA if needed */ 1811 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1812 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1813 mode = drvp->PIO_mode; 1814 goto pio; 1815 } 1816 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1817 (drvp->drive_flags & DRIVE_UDMA)) { 1818 /* use Ultra/DMA */ 1819 drvp->drive_flags &= ~DRIVE_DMA; 1820 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1821 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1822 AMD756_UDMA_TIME(chp->channel, drive, 1823 amd756_udma_tim[drvp->UDMA_mode]); 1824 /* can use PIO timings, MW DMA unused */ 1825 mode = drvp->PIO_mode; 1826 } else { 1827 /* use Multiword DMA, but only if revision is OK */ 1828 drvp->drive_flags &= ~DRIVE_UDMA; 1829 #ifndef PCIIDE_AMD756_ENABLEDMA 1830 /* 1831 * The workaround doesn't seem to be necessary 1832 * with all drives, so it can be disabled by 1833 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1834 * triggered. 1835 */ 1836 if (AMD756_CHIPREV_DISABLEDMA(rev)) { 1837 printf("%s:%d:%d: multi-word DMA disabled due " 1838 "to chip revision\n", 1839 sc->sc_wdcdev.sc_dev.dv_xname, 1840 chp->channel, drive); 1841 mode = drvp->PIO_mode; 1842 drvp->drive_flags &= ~DRIVE_DMA; 1843 goto pio; 1844 } 1845 #endif 1846 /* mode = min(pio, dma+2) */ 1847 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1848 mode = drvp->PIO_mode; 1849 else 1850 mode = drvp->DMA_mode + 2; 1851 } 1852 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1853 1854 pio: /* setup PIO mode */ 1855 if (mode <= 2) { 1856 drvp->DMA_mode = 0; 1857 drvp->PIO_mode = 0; 1858 mode = 0; 1859 } else { 1860 drvp->PIO_mode = mode; 1861 drvp->DMA_mode = mode - 2; 1862 } 1863 datatim_reg |= 1864 AMD756_DATATIM_PULSE(chp->channel, drive, 1865 amd756_pio_set[mode]) | 1866 AMD756_DATATIM_RECOV(chp->channel, drive, 1867 amd756_pio_rec[mode]); 1868 } 1869 if (idedma_ctl != 0) { 1870 /* Add software bits in status register */ 1871 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1872 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1873 idedma_ctl); 1874 } 1875 pciide_print_modes(cp); 1876 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1877 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1878 } 1879 1880 void 1881 apollo_chip_map(sc, pa) 1882 struct pciide_softc *sc; 1883 struct pci_attach_args *pa; 1884 { 1885 struct pciide_channel *cp; 1886 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1887 int channel; 1888 u_int32_t ideconf; 1889 bus_size_t cmdsize, ctlsize; 1890 1891 if (pciide_chipen(sc, pa) == 0) 1892 return; 1893 printf("%s: bus-master DMA support present", 1894 sc->sc_wdcdev.sc_dev.dv_xname); 1895 pciide_mapreg_dma(sc, pa); 1896 printf("\n"); 1897 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1898 WDC_CAPABILITY_MODE; 1899 if (sc->sc_dma_ok) { 1900 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1901 sc->sc_wdcdev.irqack = pciide_irqack; 1902 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1903 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1904 } 1905 sc->sc_wdcdev.PIO_cap = 4; 1906 sc->sc_wdcdev.DMA_cap = 2; 1907 sc->sc_wdcdev.UDMA_cap = 2; 1908 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1909 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1910 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1911 1912 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1913 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1914 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1915 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1916 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1917 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1918 DEBUG_PROBE); 1919 1920 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1921 cp = &sc->pciide_channels[channel]; 1922 if (pciide_chansetup(sc, channel, interface) == 0) 1923 continue; 1924 1925 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1926 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1927 printf("%s: %s channel ignored (disabled)\n", 1928 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1929 continue; 1930 } 1931 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1932 pciide_pci_intr); 1933 if (cp->hw_ok == 0) 1934 continue; 1935 if (pciide_chan_candisable(cp)) { 1936 ideconf &= ~APO_IDECONF_EN(channel); 1937 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1938 ideconf); 1939 } 1940 pciide_map_compat_intr(pa, cp, channel, interface); 1941 1942 if (cp->hw_ok == 0) 1943 continue; 1944 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1945 } 1946 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1947 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1948 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1949 } 1950 1951 void 1952 apollo_setup_channel(chp) 1953 struct channel_softc *chp; 1954 { 1955 u_int32_t udmatim_reg, datatim_reg; 1956 u_int8_t idedma_ctl; 1957 int mode, drive; 1958 struct ata_drive_datas *drvp; 1959 struct pciide_channel *cp = (struct pciide_channel*)chp; 1960 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1961 1962 idedma_ctl = 0; 1963 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1964 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1965 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1966 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1967 1968 /* setup DMA if needed */ 1969 pciide_channel_dma_setup(cp); 1970 1971 for (drive = 0; drive < 2; drive++) { 1972 drvp = &chp->ch_drive[drive]; 1973 /* If no drive, skip */ 1974 if ((drvp->drive_flags & DRIVE) == 0) 1975 continue; 1976 /* add timing values, setup DMA if needed */ 1977 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1978 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1979 mode = drvp->PIO_mode; 1980 goto pio; 1981 } 1982 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1983 (drvp->drive_flags & DRIVE_UDMA)) { 1984 /* use Ultra/DMA */ 1985 drvp->drive_flags &= ~DRIVE_DMA; 1986 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1987 APO_UDMA_EN_MTH(chp->channel, drive) | 1988 APO_UDMA_TIME(chp->channel, drive, 1989 apollo_udma_tim[drvp->UDMA_mode]); 1990 /* can use PIO timings, MW DMA unused */ 1991 mode = drvp->PIO_mode; 1992 } else { 1993 /* use Multiword DMA */ 1994 drvp->drive_flags &= ~DRIVE_UDMA; 1995 /* mode = min(pio, dma+2) */ 1996 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1997 mode = drvp->PIO_mode; 1998 else 1999 mode = drvp->DMA_mode + 2; 2000 } 2001 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2002 2003 pio: /* setup PIO mode */ 2004 if (mode <= 2) { 2005 drvp->DMA_mode = 0; 2006 drvp->PIO_mode = 0; 2007 mode = 0; 2008 } else { 2009 drvp->PIO_mode = mode; 2010 drvp->DMA_mode = mode - 2; 2011 } 2012 datatim_reg |= 2013 APO_DATATIM_PULSE(chp->channel, drive, 2014 apollo_pio_set[mode]) | 2015 APO_DATATIM_RECOV(chp->channel, drive, 2016 apollo_pio_rec[mode]); 2017 } 2018 if (idedma_ctl != 0) { 2019 /* Add software bits in status register */ 2020 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2021 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2022 idedma_ctl); 2023 } 2024 pciide_print_modes(cp); 2025 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2026 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2027 } 2028 2029 void 2030 cmd_channel_map(pa, sc, channel) 2031 struct pci_attach_args *pa; 2032 struct pciide_softc *sc; 2033 int channel; 2034 { 2035 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2036 bus_size_t cmdsize, ctlsize; 2037 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2038 int interface; 2039 2040 /* 2041 * The 0648/0649 can be told to identify as a RAID controller. 2042 * In this case, we have to fake interface 2043 */ 2044 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2045 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2046 PCIIDE_INTERFACE_SETTABLE(1); 2047 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2048 CMD_CONF_DSA1) 2049 interface |= PCIIDE_INTERFACE_PCI(0) | 2050 PCIIDE_INTERFACE_PCI(1); 2051 } else { 2052 interface = PCI_INTERFACE(pa->pa_class); 2053 } 2054 2055 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2056 cp->name = PCIIDE_CHANNEL_NAME(channel); 2057 cp->wdc_channel.channel = channel; 2058 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2059 2060 if (channel > 0) { 2061 cp->wdc_channel.ch_queue = 2062 sc->pciide_channels[0].wdc_channel.ch_queue; 2063 } else { 2064 cp->wdc_channel.ch_queue = 2065 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2066 } 2067 if (cp->wdc_channel.ch_queue == NULL) { 2068 printf("%s %s channel: " 2069 "can't allocate memory for command queue", 2070 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2071 return; 2072 } 2073 2074 printf("%s: %s channel %s to %s mode\n", 2075 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2076 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2077 "configured" : "wired", 2078 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2079 "native-PCI" : "compatibility"); 2080 2081 /* 2082 * with a CMD PCI64x, if we get here, the first channel is enabled: 2083 * there's no way to disable the first channel without disabling 2084 * the whole device 2085 */ 2086 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2087 printf("%s: %s channel ignored (disabled)\n", 2088 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2089 return; 2090 } 2091 2092 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2093 if (cp->hw_ok == 0) 2094 return; 2095 if (channel == 1) { 2096 if (pciide_chan_candisable(cp)) { 2097 ctrl &= ~CMD_CTRL_2PORT; 2098 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2099 CMD_CTRL, ctrl); 2100 } 2101 } 2102 pciide_map_compat_intr(pa, cp, channel, interface); 2103 } 2104 2105 int 2106 cmd_pci_intr(arg) 2107 void *arg; 2108 { 2109 struct pciide_softc *sc = arg; 2110 struct pciide_channel *cp; 2111 struct channel_softc *wdc_cp; 2112 int i, rv, crv; 2113 u_int32_t priirq, secirq; 2114 2115 rv = 0; 2116 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2117 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2118 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2119 cp = &sc->pciide_channels[i]; 2120 wdc_cp = &cp->wdc_channel; 2121 /* If a compat channel skip. */ 2122 if (cp->compat) 2123 continue; 2124 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2125 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2126 crv = wdcintr(wdc_cp); 2127 if (crv == 0) 2128 printf("%s:%d: bogus intr\n", 2129 sc->sc_wdcdev.sc_dev.dv_xname, i); 2130 else 2131 rv = 1; 2132 } 2133 } 2134 return rv; 2135 } 2136 2137 void 2138 cmd_chip_map(sc, pa) 2139 struct pciide_softc *sc; 2140 struct pci_attach_args *pa; 2141 { 2142 int channel; 2143 2144 /* 2145 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2146 * and base adresses registers can be disabled at 2147 * hardware level. In this case, the device is wired 2148 * in compat mode and its first channel is always enabled, 2149 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2150 * In fact, it seems that the first channel of the CMD PCI0640 2151 * can't be disabled. 2152 */ 2153 2154 #ifdef PCIIDE_CMD064x_DISABLE 2155 if (pciide_chipen(sc, pa) == 0) 2156 return; 2157 #endif 2158 2159 printf("%s: hardware does not support DMA\n", 2160 sc->sc_wdcdev.sc_dev.dv_xname); 2161 sc->sc_dma_ok = 0; 2162 2163 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2164 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2165 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2166 2167 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2168 cmd_channel_map(pa, sc, channel); 2169 } 2170 } 2171 2172 void 2173 cmd0643_9_chip_map(sc, pa) 2174 struct pciide_softc *sc; 2175 struct pci_attach_args *pa; 2176 { 2177 struct pciide_channel *cp; 2178 int channel; 2179 int rev = PCI_REVISION( 2180 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2181 2182 /* 2183 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2184 * and base adresses registers can be disabled at 2185 * hardware level. In this case, the device is wired 2186 * in compat mode and its first channel is always enabled, 2187 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2188 * In fact, it seems that the first channel of the CMD PCI0640 2189 * can't be disabled. 2190 */ 2191 2192 #ifdef PCIIDE_CMD064x_DISABLE 2193 if (pciide_chipen(sc, pa) == 0) 2194 return; 2195 #endif 2196 printf("%s: bus-master DMA support present", 2197 sc->sc_wdcdev.sc_dev.dv_xname); 2198 pciide_mapreg_dma(sc, pa); 2199 printf("\n"); 2200 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2201 WDC_CAPABILITY_MODE; 2202 if (sc->sc_dma_ok) { 2203 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2204 switch (sc->sc_pp->ide_product) { 2205 case PCI_PRODUCT_CMDTECH_649: 2206 case PCI_PRODUCT_CMDTECH_648: 2207 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2208 sc->sc_wdcdev.UDMA_cap = 4; 2209 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2210 break; 2211 case PCI_PRODUCT_CMDTECH_646: 2212 if (rev >= CMD0646U2_REV) { 2213 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2214 sc->sc_wdcdev.UDMA_cap = 2; 2215 } else if (rev >= CMD0646U_REV) { 2216 /* 2217 * Linux's driver claims that the 646U is broken 2218 * with UDMA. Only enable it if we know what we're 2219 * doing 2220 */ 2221 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2222 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2223 sc->sc_wdcdev.UDMA_cap = 2; 2224 #endif 2225 /* explicitely disable UDMA */ 2226 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2227 CMD_UDMATIM(0), 0); 2228 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2229 CMD_UDMATIM(1), 0); 2230 } 2231 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2232 break; 2233 default: 2234 sc->sc_wdcdev.irqack = pciide_irqack; 2235 } 2236 } 2237 2238 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2239 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2240 sc->sc_wdcdev.PIO_cap = 4; 2241 sc->sc_wdcdev.DMA_cap = 2; 2242 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2243 2244 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2245 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2246 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2247 DEBUG_PROBE); 2248 2249 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2250 cp = &sc->pciide_channels[channel]; 2251 cmd_channel_map(pa, sc, channel); 2252 if (cp->hw_ok == 0) 2253 continue; 2254 cmd0643_9_setup_channel(&cp->wdc_channel); 2255 } 2256 /* 2257 * note - this also makes sure we clear the irq disable and reset 2258 * bits 2259 */ 2260 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2261 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2262 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2263 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2264 DEBUG_PROBE); 2265 } 2266 2267 void 2268 cmd0643_9_setup_channel(chp) 2269 struct channel_softc *chp; 2270 { 2271 struct ata_drive_datas *drvp; 2272 u_int8_t tim; 2273 u_int32_t idedma_ctl, udma_reg; 2274 int drive; 2275 struct pciide_channel *cp = (struct pciide_channel*)chp; 2276 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2277 2278 idedma_ctl = 0; 2279 /* setup DMA if needed */ 2280 pciide_channel_dma_setup(cp); 2281 2282 for (drive = 0; drive < 2; drive++) { 2283 drvp = &chp->ch_drive[drive]; 2284 /* If no drive, skip */ 2285 if ((drvp->drive_flags & DRIVE) == 0) 2286 continue; 2287 /* add timing values, setup DMA if needed */ 2288 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2289 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2290 if (drvp->drive_flags & DRIVE_UDMA) { 2291 /* UltraDMA on a 646U2, 0648 or 0649 */ 2292 udma_reg = pciide_pci_read(sc->sc_pc, 2293 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2294 if (drvp->UDMA_mode > 2 && 2295 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2296 CMD_BICSR) & 2297 CMD_BICSR_80(chp->channel)) == 0) 2298 drvp->UDMA_mode = 2; 2299 if (drvp->UDMA_mode > 2) 2300 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2301 else if (sc->sc_wdcdev.UDMA_cap > 2) 2302 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2303 udma_reg |= CMD_UDMATIM_UDMA(drive); 2304 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2305 CMD_UDMATIM_TIM_OFF(drive)); 2306 udma_reg |= 2307 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2308 CMD_UDMATIM_TIM_OFF(drive)); 2309 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2310 CMD_UDMATIM(chp->channel), udma_reg); 2311 } else { 2312 /* 2313 * use Multiword DMA. 2314 * Timings will be used for both PIO and DMA, 2315 * so adjust DMA mode if needed 2316 * if we have a 0646U2/8/9, turn off UDMA 2317 */ 2318 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2319 udma_reg = pciide_pci_read(sc->sc_pc, 2320 sc->sc_tag, 2321 CMD_UDMATIM(chp->channel)); 2322 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2323 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2324 CMD_UDMATIM(chp->channel), 2325 udma_reg); 2326 } 2327 if (drvp->PIO_mode >= 3 && 2328 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2329 drvp->DMA_mode = drvp->PIO_mode - 2; 2330 } 2331 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2332 } 2333 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2334 } 2335 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2336 CMD_DATA_TIM(chp->channel, drive), tim); 2337 } 2338 if (idedma_ctl != 0) { 2339 /* Add software bits in status register */ 2340 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2341 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2342 idedma_ctl); 2343 } 2344 pciide_print_modes(cp); 2345 } 2346 2347 void 2348 cmd646_9_irqack(chp) 2349 struct channel_softc *chp; 2350 { 2351 u_int32_t priirq, secirq; 2352 struct pciide_channel *cp = (struct pciide_channel*)chp; 2353 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2354 2355 if (chp->channel == 0) { 2356 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2357 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2358 } else { 2359 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2360 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2361 } 2362 pciide_irqack(chp); 2363 } 2364 2365 void 2366 cy693_chip_map(sc, pa) 2367 struct pciide_softc *sc; 2368 struct pci_attach_args *pa; 2369 { 2370 struct pciide_channel *cp; 2371 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2372 bus_size_t cmdsize, ctlsize; 2373 2374 if (pciide_chipen(sc, pa) == 0) 2375 return; 2376 /* 2377 * this chip has 2 PCI IDE functions, one for primary and one for 2378 * secondary. So we need to call pciide_mapregs_compat() with 2379 * the real channel 2380 */ 2381 if (pa->pa_function == 1) { 2382 sc->sc_cy_compatchan = 0; 2383 } else if (pa->pa_function == 2) { 2384 sc->sc_cy_compatchan = 1; 2385 } else { 2386 printf("%s: unexpected PCI function %d\n", 2387 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2388 return; 2389 } 2390 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2391 printf("%s: bus-master DMA support present", 2392 sc->sc_wdcdev.sc_dev.dv_xname); 2393 pciide_mapreg_dma(sc, pa); 2394 } else { 2395 printf("%s: hardware does not support DMA", 2396 sc->sc_wdcdev.sc_dev.dv_xname); 2397 sc->sc_dma_ok = 0; 2398 } 2399 printf("\n"); 2400 2401 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2402 if (sc->sc_cy_handle == NULL) { 2403 printf("%s: unable to map hyperCache control registers\n", 2404 sc->sc_wdcdev.sc_dev.dv_xname); 2405 sc->sc_dma_ok = 0; 2406 } 2407 2408 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2409 WDC_CAPABILITY_MODE; 2410 if (sc->sc_dma_ok) { 2411 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2412 sc->sc_wdcdev.irqack = pciide_irqack; 2413 } 2414 sc->sc_wdcdev.PIO_cap = 4; 2415 sc->sc_wdcdev.DMA_cap = 2; 2416 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2417 2418 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2419 sc->sc_wdcdev.nchannels = 1; 2420 2421 /* Only one channel for this chip; if we are here it's enabled */ 2422 cp = &sc->pciide_channels[0]; 2423 sc->wdc_chanarray[0] = &cp->wdc_channel; 2424 cp->name = PCIIDE_CHANNEL_NAME(0); 2425 cp->wdc_channel.channel = 0; 2426 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2427 cp->wdc_channel.ch_queue = 2428 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2429 if (cp->wdc_channel.ch_queue == NULL) { 2430 printf("%s primary channel: " 2431 "can't allocate memory for command queue", 2432 sc->sc_wdcdev.sc_dev.dv_xname); 2433 return; 2434 } 2435 printf("%s: primary channel %s to ", 2436 sc->sc_wdcdev.sc_dev.dv_xname, 2437 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2438 "configured" : "wired"); 2439 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2440 printf("native-PCI"); 2441 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2442 pciide_pci_intr); 2443 } else { 2444 printf("compatibility"); 2445 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2446 &cmdsize, &ctlsize); 2447 } 2448 printf(" mode\n"); 2449 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2450 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2451 wdcattach(&cp->wdc_channel); 2452 if (pciide_chan_candisable(cp)) { 2453 pci_conf_write(sc->sc_pc, sc->sc_tag, 2454 PCI_COMMAND_STATUS_REG, 0); 2455 } 2456 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2457 if (cp->hw_ok == 0) 2458 return; 2459 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2460 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2461 cy693_setup_channel(&cp->wdc_channel); 2462 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2463 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2464 } 2465 2466 void 2467 cy693_setup_channel(chp) 2468 struct channel_softc *chp; 2469 { 2470 struct ata_drive_datas *drvp; 2471 int drive; 2472 u_int32_t cy_cmd_ctrl; 2473 u_int32_t idedma_ctl; 2474 struct pciide_channel *cp = (struct pciide_channel*)chp; 2475 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2476 int dma_mode = -1; 2477 2478 cy_cmd_ctrl = idedma_ctl = 0; 2479 2480 /* setup DMA if needed */ 2481 pciide_channel_dma_setup(cp); 2482 2483 for (drive = 0; drive < 2; drive++) { 2484 drvp = &chp->ch_drive[drive]; 2485 /* If no drive, skip */ 2486 if ((drvp->drive_flags & DRIVE) == 0) 2487 continue; 2488 /* add timing values, setup DMA if needed */ 2489 if (drvp->drive_flags & DRIVE_DMA) { 2490 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2491 /* use Multiword DMA */ 2492 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2493 dma_mode = drvp->DMA_mode; 2494 } 2495 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2496 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2497 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2498 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2499 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2500 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2501 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2502 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2503 } 2504 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2505 chp->ch_drive[0].DMA_mode = dma_mode; 2506 chp->ch_drive[1].DMA_mode = dma_mode; 2507 2508 if (dma_mode == -1) 2509 dma_mode = 0; 2510 2511 if (sc->sc_cy_handle != NULL) { 2512 /* Note: `multiple' is implied. */ 2513 cy82c693_write(sc->sc_cy_handle, 2514 (sc->sc_cy_compatchan == 0) ? 2515 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2516 } 2517 2518 pciide_print_modes(cp); 2519 2520 if (idedma_ctl != 0) { 2521 /* Add software bits in status register */ 2522 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2523 IDEDMA_CTL, idedma_ctl); 2524 } 2525 } 2526 2527 void 2528 sis_chip_map(sc, pa) 2529 struct pciide_softc *sc; 2530 struct pci_attach_args *pa; 2531 { 2532 struct pciide_channel *cp; 2533 int channel; 2534 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2535 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2536 pcireg_t rev = PCI_REVISION(pa->pa_class); 2537 bus_size_t cmdsize, ctlsize; 2538 2539 if (pciide_chipen(sc, pa) == 0) 2540 return; 2541 printf("%s: bus-master DMA support present", 2542 sc->sc_wdcdev.sc_dev.dv_xname); 2543 pciide_mapreg_dma(sc, pa); 2544 printf("\n"); 2545 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2546 WDC_CAPABILITY_MODE; 2547 if (sc->sc_dma_ok) { 2548 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2549 sc->sc_wdcdev.irqack = pciide_irqack; 2550 if (rev >= 0xd0) 2551 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2552 } 2553 2554 sc->sc_wdcdev.PIO_cap = 4; 2555 sc->sc_wdcdev.DMA_cap = 2; 2556 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2557 sc->sc_wdcdev.UDMA_cap = 2; 2558 sc->sc_wdcdev.set_modes = sis_setup_channel; 2559 2560 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2561 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2562 2563 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2564 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2565 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2566 2567 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2568 cp = &sc->pciide_channels[channel]; 2569 if (pciide_chansetup(sc, channel, interface) == 0) 2570 continue; 2571 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2572 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2573 printf("%s: %s channel ignored (disabled)\n", 2574 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2575 continue; 2576 } 2577 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2578 pciide_pci_intr); 2579 if (cp->hw_ok == 0) 2580 continue; 2581 if (pciide_chan_candisable(cp)) { 2582 if (channel == 0) 2583 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2584 else 2585 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2586 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2587 sis_ctr0); 2588 } 2589 pciide_map_compat_intr(pa, cp, channel, interface); 2590 if (cp->hw_ok == 0) 2591 continue; 2592 sis_setup_channel(&cp->wdc_channel); 2593 } 2594 } 2595 2596 void 2597 sis_setup_channel(chp) 2598 struct channel_softc *chp; 2599 { 2600 struct ata_drive_datas *drvp; 2601 int drive; 2602 u_int32_t sis_tim; 2603 u_int32_t idedma_ctl; 2604 struct pciide_channel *cp = (struct pciide_channel*)chp; 2605 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2606 2607 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2608 "channel %d 0x%x\n", chp->channel, 2609 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2610 DEBUG_PROBE); 2611 sis_tim = 0; 2612 idedma_ctl = 0; 2613 /* setup DMA if needed */ 2614 pciide_channel_dma_setup(cp); 2615 2616 for (drive = 0; drive < 2; drive++) { 2617 drvp = &chp->ch_drive[drive]; 2618 /* If no drive, skip */ 2619 if ((drvp->drive_flags & DRIVE) == 0) 2620 continue; 2621 /* add timing values, setup DMA if needed */ 2622 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2623 (drvp->drive_flags & DRIVE_UDMA) == 0) 2624 goto pio; 2625 2626 if (drvp->drive_flags & DRIVE_UDMA) { 2627 /* use Ultra/DMA */ 2628 drvp->drive_flags &= ~DRIVE_DMA; 2629 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2630 SIS_TIM_UDMA_TIME_OFF(drive); 2631 sis_tim |= SIS_TIM_UDMA_EN(drive); 2632 } else { 2633 /* 2634 * use Multiword DMA 2635 * Timings will be used for both PIO and DMA, 2636 * so adjust DMA mode if needed 2637 */ 2638 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2639 drvp->PIO_mode = drvp->DMA_mode + 2; 2640 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2641 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2642 drvp->PIO_mode - 2 : 0; 2643 if (drvp->DMA_mode == 0) 2644 drvp->PIO_mode = 0; 2645 } 2646 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2647 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2648 SIS_TIM_ACT_OFF(drive); 2649 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2650 SIS_TIM_REC_OFF(drive); 2651 } 2652 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2653 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2654 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2655 if (idedma_ctl != 0) { 2656 /* Add software bits in status register */ 2657 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2658 IDEDMA_CTL, idedma_ctl); 2659 } 2660 pciide_print_modes(cp); 2661 } 2662 2663 void 2664 acer_chip_map(sc, pa) 2665 struct pciide_softc *sc; 2666 struct pci_attach_args *pa; 2667 { 2668 struct pciide_channel *cp; 2669 int channel; 2670 pcireg_t cr, interface; 2671 bus_size_t cmdsize, ctlsize; 2672 2673 if (pciide_chipen(sc, pa) == 0) 2674 return; 2675 printf("%s: bus-master DMA support present", 2676 sc->sc_wdcdev.sc_dev.dv_xname); 2677 pciide_mapreg_dma(sc, pa); 2678 printf("\n"); 2679 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2680 WDC_CAPABILITY_MODE; 2681 if (sc->sc_dma_ok) { 2682 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2683 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2684 sc->sc_wdcdev.irqack = pciide_irqack; 2685 } 2686 2687 sc->sc_wdcdev.PIO_cap = 4; 2688 sc->sc_wdcdev.DMA_cap = 2; 2689 sc->sc_wdcdev.UDMA_cap = 2; 2690 sc->sc_wdcdev.set_modes = acer_setup_channel; 2691 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2692 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2693 2694 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2695 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2696 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2697 2698 /* Enable "microsoft register bits" R/W. */ 2699 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2700 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2701 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2702 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2703 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2704 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2705 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2706 ~ACER_CHANSTATUSREGS_RO); 2707 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2708 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2709 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2710 /* Don't use cr, re-read the real register content instead */ 2711 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2712 PCI_CLASS_REG)); 2713 2714 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2715 cp = &sc->pciide_channels[channel]; 2716 if (pciide_chansetup(sc, channel, interface) == 0) 2717 continue; 2718 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2719 printf("%s: %s channel ignored (disabled)\n", 2720 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2721 continue; 2722 } 2723 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2724 acer_pci_intr); 2725 if (cp->hw_ok == 0) 2726 continue; 2727 if (pciide_chan_candisable(cp)) { 2728 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2729 pci_conf_write(sc->sc_pc, sc->sc_tag, 2730 PCI_CLASS_REG, cr); 2731 } 2732 pciide_map_compat_intr(pa, cp, channel, interface); 2733 acer_setup_channel(&cp->wdc_channel); 2734 } 2735 } 2736 2737 void 2738 acer_setup_channel(chp) 2739 struct channel_softc *chp; 2740 { 2741 struct ata_drive_datas *drvp; 2742 int drive; 2743 u_int32_t acer_fifo_udma; 2744 u_int32_t idedma_ctl; 2745 struct pciide_channel *cp = (struct pciide_channel*)chp; 2746 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2747 2748 idedma_ctl = 0; 2749 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2750 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2751 acer_fifo_udma), DEBUG_PROBE); 2752 /* setup DMA if needed */ 2753 pciide_channel_dma_setup(cp); 2754 2755 for (drive = 0; drive < 2; drive++) { 2756 drvp = &chp->ch_drive[drive]; 2757 /* If no drive, skip */ 2758 if ((drvp->drive_flags & DRIVE) == 0) 2759 continue; 2760 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2761 "channel %d drive %d 0x%x\n", chp->channel, drive, 2762 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2763 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2764 /* clear FIFO/DMA mode */ 2765 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2766 ACER_UDMA_EN(chp->channel, drive) | 2767 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2768 2769 /* add timing values, setup DMA if needed */ 2770 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2771 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2772 acer_fifo_udma |= 2773 ACER_FTH_OPL(chp->channel, drive, 0x1); 2774 goto pio; 2775 } 2776 2777 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2778 if (drvp->drive_flags & DRIVE_UDMA) { 2779 /* use Ultra/DMA */ 2780 drvp->drive_flags &= ~DRIVE_DMA; 2781 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2782 acer_fifo_udma |= 2783 ACER_UDMA_TIM(chp->channel, drive, 2784 acer_udma[drvp->UDMA_mode]); 2785 } else { 2786 /* 2787 * use Multiword DMA 2788 * Timings will be used for both PIO and DMA, 2789 * so adjust DMA mode if needed 2790 */ 2791 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2792 drvp->PIO_mode = drvp->DMA_mode + 2; 2793 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2794 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2795 drvp->PIO_mode - 2 : 0; 2796 if (drvp->DMA_mode == 0) 2797 drvp->PIO_mode = 0; 2798 } 2799 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2800 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2801 ACER_IDETIM(chp->channel, drive), 2802 acer_pio[drvp->PIO_mode]); 2803 } 2804 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2805 acer_fifo_udma), DEBUG_PROBE); 2806 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2807 if (idedma_ctl != 0) { 2808 /* Add software bits in status register */ 2809 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2810 IDEDMA_CTL, idedma_ctl); 2811 } 2812 pciide_print_modes(cp); 2813 } 2814 2815 int 2816 acer_pci_intr(arg) 2817 void *arg; 2818 { 2819 struct pciide_softc *sc = arg; 2820 struct pciide_channel *cp; 2821 struct channel_softc *wdc_cp; 2822 int i, rv, crv; 2823 u_int32_t chids; 2824 2825 rv = 0; 2826 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2827 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2828 cp = &sc->pciide_channels[i]; 2829 wdc_cp = &cp->wdc_channel; 2830 /* If a compat channel skip. */ 2831 if (cp->compat) 2832 continue; 2833 if (chids & ACER_CHIDS_INT(i)) { 2834 crv = wdcintr(wdc_cp); 2835 if (crv == 0) 2836 printf("%s:%d: bogus intr\n", 2837 sc->sc_wdcdev.sc_dev.dv_xname, i); 2838 else 2839 rv = 1; 2840 } 2841 } 2842 return rv; 2843 } 2844 2845 void 2846 hpt_chip_map(sc, pa) 2847 struct pciide_softc *sc; 2848 struct pci_attach_args *pa; 2849 { 2850 struct pciide_channel *cp; 2851 int i, compatchan, revision; 2852 pcireg_t interface; 2853 bus_size_t cmdsize, ctlsize; 2854 2855 if (pciide_chipen(sc, pa) == 0) 2856 return; 2857 revision = PCI_REVISION(pa->pa_class); 2858 2859 /* 2860 * when the chip is in native mode it identifies itself as a 2861 * 'misc mass storage'. Fake interface in this case. 2862 */ 2863 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2864 interface = PCI_INTERFACE(pa->pa_class); 2865 } else { 2866 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2867 PCIIDE_INTERFACE_PCI(0); 2868 if (revision == HPT370_REV) 2869 interface |= PCIIDE_INTERFACE_PCI(1); 2870 } 2871 2872 printf("%s: bus-master DMA support present", 2873 sc->sc_wdcdev.sc_dev.dv_xname); 2874 pciide_mapreg_dma(sc, pa); 2875 printf("\n"); 2876 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2877 WDC_CAPABILITY_MODE; 2878 if (sc->sc_dma_ok) { 2879 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2880 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2881 sc->sc_wdcdev.irqack = pciide_irqack; 2882 } 2883 sc->sc_wdcdev.PIO_cap = 4; 2884 sc->sc_wdcdev.DMA_cap = 2; 2885 sc->sc_wdcdev.UDMA_cap = 4; 2886 2887 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2888 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2889 if (revision == HPT366_REV) { 2890 /* 2891 * The 366 has 2 PCI IDE functions, one for primary and one 2892 * for secondary. So we need to call pciide_mapregs_compat() 2893 * with the real channel 2894 */ 2895 if (pa->pa_function == 0) { 2896 compatchan = 0; 2897 } else if (pa->pa_function == 1) { 2898 compatchan = 1; 2899 } else { 2900 printf("%s: unexpected PCI function %d\n", 2901 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2902 return; 2903 } 2904 sc->sc_wdcdev.nchannels = 1; 2905 } else { 2906 sc->sc_wdcdev.nchannels = 2; 2907 } 2908 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2909 cp = &sc->pciide_channels[i]; 2910 if (sc->sc_wdcdev.nchannels > 1) { 2911 compatchan = i; 2912 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2913 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2914 printf("%s: %s channel ignored (disabled)\n", 2915 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2916 continue; 2917 } 2918 } 2919 if (pciide_chansetup(sc, i, interface) == 0) 2920 continue; 2921 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2922 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2923 &ctlsize, hpt_pci_intr); 2924 } else { 2925 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2926 &cmdsize, &ctlsize); 2927 } 2928 if (cp->hw_ok == 0) 2929 return; 2930 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2931 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2932 wdcattach(&cp->wdc_channel); 2933 hpt_setup_channel(&cp->wdc_channel); 2934 } 2935 if (revision == HPT370_REV) { 2936 /* 2937 * HPT370_REV has a bit to disable interrupts, make sure 2938 * to clear it 2939 */ 2940 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 2941 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 2942 ~HPT_CSEL_IRQDIS); 2943 } 2944 return; 2945 } 2946 2947 2948 void 2949 hpt_setup_channel(chp) 2950 struct channel_softc *chp; 2951 { 2952 struct ata_drive_datas *drvp; 2953 int drive; 2954 int cable; 2955 u_int32_t before, after; 2956 u_int32_t idedma_ctl; 2957 struct pciide_channel *cp = (struct pciide_channel*)chp; 2958 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2959 2960 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 2961 2962 /* setup DMA if needed */ 2963 pciide_channel_dma_setup(cp); 2964 2965 idedma_ctl = 0; 2966 2967 /* Per drive settings */ 2968 for (drive = 0; drive < 2; drive++) { 2969 drvp = &chp->ch_drive[drive]; 2970 /* If no drive, skip */ 2971 if ((drvp->drive_flags & DRIVE) == 0) 2972 continue; 2973 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 2974 HPT_IDETIM(chp->channel, drive)); 2975 2976 /* add timing values, setup DMA if needed */ 2977 if (drvp->drive_flags & DRIVE_UDMA) { 2978 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 2979 drvp->UDMA_mode > 2) 2980 drvp->UDMA_mode = 2; 2981 after = (sc->sc_wdcdev.nchannels == 2) ? 2982 hpt370_udma[drvp->UDMA_mode] : 2983 hpt366_udma[drvp->UDMA_mode]; 2984 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2985 } else if (drvp->drive_flags & DRIVE_DMA) { 2986 /* 2987 * use Multiword DMA. 2988 * Timings will be used for both PIO and DMA, so adjust 2989 * DMA mode if needed 2990 */ 2991 if (drvp->PIO_mode >= 3 && 2992 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2993 drvp->DMA_mode = drvp->PIO_mode - 2; 2994 } 2995 after = (sc->sc_wdcdev.nchannels == 2) ? 2996 hpt370_dma[drvp->DMA_mode] : 2997 hpt366_dma[drvp->DMA_mode]; 2998 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2999 } else { 3000 /* PIO only */ 3001 after = (sc->sc_wdcdev.nchannels == 2) ? 3002 hpt370_pio[drvp->PIO_mode] : 3003 hpt366_pio[drvp->PIO_mode]; 3004 } 3005 pci_conf_write(sc->sc_pc, sc->sc_tag, 3006 HPT_IDETIM(chp->channel, drive), after); 3007 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3008 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3009 after, before), DEBUG_PROBE); 3010 } 3011 if (idedma_ctl != 0) { 3012 /* Add software bits in status register */ 3013 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3014 IDEDMA_CTL, idedma_ctl); 3015 } 3016 pciide_print_modes(cp); 3017 } 3018 3019 int 3020 hpt_pci_intr(arg) 3021 void *arg; 3022 { 3023 struct pciide_softc *sc = arg; 3024 struct pciide_channel *cp; 3025 struct channel_softc *wdc_cp; 3026 int rv = 0; 3027 int dmastat, i, crv; 3028 3029 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3030 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3031 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3032 if((dmastat & IDEDMA_CTL_INTR) == 0) 3033 continue; 3034 cp = &sc->pciide_channels[i]; 3035 wdc_cp = &cp->wdc_channel; 3036 crv = wdcintr(wdc_cp); 3037 if (crv == 0) { 3038 printf("%s:%d: bogus intr\n", 3039 sc->sc_wdcdev.sc_dev.dv_xname, i); 3040 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3041 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3042 } else 3043 rv = 1; 3044 } 3045 return rv; 3046 } 3047 3048 3049 /* A macro to test product */ 3050 #define PDC_IS_262(sc) \ 3051 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3052 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3053 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3054 3055 void 3056 pdc202xx_chip_map(sc, pa) 3057 struct pciide_softc *sc; 3058 struct pci_attach_args *pa; 3059 { 3060 struct pciide_channel *cp; 3061 int channel; 3062 pcireg_t interface, st, mode; 3063 bus_size_t cmdsize, ctlsize; 3064 3065 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3066 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3067 DEBUG_PROBE); 3068 if (pciide_chipen(sc, pa) == 0) 3069 return; 3070 3071 /* turn off RAID mode */ 3072 st &= ~PDC2xx_STATE_IDERAID; 3073 3074 /* 3075 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3076 * mode. We have to fake interface 3077 */ 3078 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3079 if (st & PDC2xx_STATE_NATIVE) 3080 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3081 3082 printf("%s: bus-master DMA support present", 3083 sc->sc_wdcdev.sc_dev.dv_xname); 3084 pciide_mapreg_dma(sc, pa); 3085 printf("\n"); 3086 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3087 WDC_CAPABILITY_MODE; 3088 if (sc->sc_dma_ok) { 3089 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3090 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3091 sc->sc_wdcdev.irqack = pciide_irqack; 3092 } 3093 sc->sc_wdcdev.PIO_cap = 4; 3094 sc->sc_wdcdev.DMA_cap = 2; 3095 if (PDC_IS_262(sc)) 3096 sc->sc_wdcdev.UDMA_cap = 4; 3097 else 3098 sc->sc_wdcdev.UDMA_cap = 2; 3099 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3100 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3101 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3102 3103 /* setup failsafe defaults */ 3104 mode = 0; 3105 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3106 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3107 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3108 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3109 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3110 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3111 "initial timings 0x%x, now 0x%x\n", channel, 3112 pci_conf_read(sc->sc_pc, sc->sc_tag, 3113 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3114 DEBUG_PROBE); 3115 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3116 mode | PDC2xx_TIM_IORDYp); 3117 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3118 "initial timings 0x%x, now 0x%x\n", channel, 3119 pci_conf_read(sc->sc_pc, sc->sc_tag, 3120 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3121 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3122 mode); 3123 } 3124 3125 mode = PDC2xx_SCR_DMA; 3126 if (PDC_IS_262(sc)) { 3127 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3128 } else { 3129 /* the BIOS set it up this way */ 3130 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3131 } 3132 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3133 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3134 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3135 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3136 DEBUG_PROBE); 3137 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3138 3139 /* controller initial state register is OK even without BIOS */ 3140 /* Set DMA mode to IDE DMA compatibility */ 3141 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3142 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3143 DEBUG_PROBE); 3144 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3145 mode | 0x1); 3146 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3147 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3148 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3149 mode | 0x1); 3150 3151 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3152 cp = &sc->pciide_channels[channel]; 3153 if (pciide_chansetup(sc, channel, interface) == 0) 3154 continue; 3155 if ((st & (PDC_IS_262(sc) ? 3156 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3157 printf("%s: %s channel ignored (disabled)\n", 3158 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3159 continue; 3160 } 3161 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3162 pdc202xx_pci_intr); 3163 if (cp->hw_ok == 0) 3164 continue; 3165 if (pciide_chan_candisable(cp)) 3166 st &= ~(PDC_IS_262(sc) ? 3167 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3168 pciide_map_compat_intr(pa, cp, channel, interface); 3169 pdc202xx_setup_channel(&cp->wdc_channel); 3170 } 3171 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3172 DEBUG_PROBE); 3173 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3174 return; 3175 } 3176 3177 void 3178 pdc202xx_setup_channel(chp) 3179 struct channel_softc *chp; 3180 { 3181 struct ata_drive_datas *drvp; 3182 int drive; 3183 pcireg_t mode, st; 3184 u_int32_t idedma_ctl, scr, atapi; 3185 struct pciide_channel *cp = (struct pciide_channel*)chp; 3186 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3187 int channel = chp->channel; 3188 3189 /* setup DMA if needed */ 3190 pciide_channel_dma_setup(cp); 3191 3192 idedma_ctl = 0; 3193 3194 /* Per channel settings */ 3195 if (PDC_IS_262(sc)) { 3196 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3197 PDC262_U66); 3198 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3199 /* Trimm UDMA mode */ 3200 if ((st & PDC262_STATE_80P(channel)) != 0 || 3201 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3202 chp->ch_drive[0].UDMA_mode <= 2) || 3203 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3204 chp->ch_drive[1].UDMA_mode <= 2)) { 3205 if (chp->ch_drive[0].UDMA_mode > 2) 3206 chp->ch_drive[0].UDMA_mode = 2; 3207 if (chp->ch_drive[1].UDMA_mode > 2) 3208 chp->ch_drive[1].UDMA_mode = 2; 3209 } 3210 /* Set U66 if needed */ 3211 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3212 chp->ch_drive[0].UDMA_mode > 2) || 3213 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3214 chp->ch_drive[1].UDMA_mode > 2)) 3215 scr |= PDC262_U66_EN(channel); 3216 else 3217 scr &= ~PDC262_U66_EN(channel); 3218 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3219 PDC262_U66, scr); 3220 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3221 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3222 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3223 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3224 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3225 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3226 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3227 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3228 atapi = 0; 3229 else 3230 atapi = PDC262_ATAPI_UDMA; 3231 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3232 PDC262_ATAPI(channel), atapi); 3233 } 3234 } 3235 for (drive = 0; drive < 2; drive++) { 3236 drvp = &chp->ch_drive[drive]; 3237 /* If no drive, skip */ 3238 if ((drvp->drive_flags & DRIVE) == 0) 3239 continue; 3240 mode = 0; 3241 if (drvp->drive_flags & DRIVE_UDMA) { 3242 mode = PDC2xx_TIM_SET_MB(mode, 3243 pdc2xx_udma_mb[drvp->UDMA_mode]); 3244 mode = PDC2xx_TIM_SET_MC(mode, 3245 pdc2xx_udma_mc[drvp->UDMA_mode]); 3246 drvp->drive_flags &= ~DRIVE_DMA; 3247 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3248 } else if (drvp->drive_flags & DRIVE_DMA) { 3249 mode = PDC2xx_TIM_SET_MB(mode, 3250 pdc2xx_dma_mb[drvp->DMA_mode]); 3251 mode = PDC2xx_TIM_SET_MC(mode, 3252 pdc2xx_dma_mc[drvp->DMA_mode]); 3253 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3254 } else { 3255 mode = PDC2xx_TIM_SET_MB(mode, 3256 pdc2xx_dma_mb[0]); 3257 mode = PDC2xx_TIM_SET_MC(mode, 3258 pdc2xx_dma_mc[0]); 3259 } 3260 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3261 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3262 if (drvp->drive_flags & DRIVE_ATA) 3263 mode |= PDC2xx_TIM_PRE; 3264 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3265 if (drvp->PIO_mode >= 3) { 3266 mode |= PDC2xx_TIM_IORDY; 3267 if (drive == 0) 3268 mode |= PDC2xx_TIM_IORDYp; 3269 } 3270 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3271 "timings 0x%x\n", 3272 sc->sc_wdcdev.sc_dev.dv_xname, 3273 chp->channel, drive, mode), DEBUG_PROBE); 3274 pci_conf_write(sc->sc_pc, sc->sc_tag, 3275 PDC2xx_TIM(chp->channel, drive), mode); 3276 } 3277 if (idedma_ctl != 0) { 3278 /* Add software bits in status register */ 3279 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3280 IDEDMA_CTL, idedma_ctl); 3281 } 3282 pciide_print_modes(cp); 3283 } 3284 3285 int 3286 pdc202xx_pci_intr(arg) 3287 void *arg; 3288 { 3289 struct pciide_softc *sc = arg; 3290 struct pciide_channel *cp; 3291 struct channel_softc *wdc_cp; 3292 int i, rv, crv; 3293 u_int32_t scr; 3294 3295 rv = 0; 3296 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3297 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3298 cp = &sc->pciide_channels[i]; 3299 wdc_cp = &cp->wdc_channel; 3300 /* If a compat channel skip. */ 3301 if (cp->compat) 3302 continue; 3303 if (scr & PDC2xx_SCR_INT(i)) { 3304 crv = wdcintr(wdc_cp); 3305 if (crv == 0) 3306 printf("%s:%d: bogus intr\n", 3307 sc->sc_wdcdev.sc_dev.dv_xname, i); 3308 else 3309 rv = 1; 3310 } 3311 } 3312 return rv; 3313 } 3314 3315 void 3316 opti_chip_map(sc, pa) 3317 struct pciide_softc *sc; 3318 struct pci_attach_args *pa; 3319 { 3320 struct pciide_channel *cp; 3321 bus_size_t cmdsize, ctlsize; 3322 pcireg_t interface; 3323 u_int8_t init_ctrl; 3324 int channel; 3325 3326 if (pciide_chipen(sc, pa) == 0) 3327 return; 3328 printf("%s: bus-master DMA support present", 3329 sc->sc_wdcdev.sc_dev.dv_xname); 3330 pciide_mapreg_dma(sc, pa); 3331 printf("\n"); 3332 3333 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3334 WDC_CAPABILITY_MODE; 3335 sc->sc_wdcdev.PIO_cap = 4; 3336 if (sc->sc_dma_ok) { 3337 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3338 sc->sc_wdcdev.irqack = pciide_irqack; 3339 sc->sc_wdcdev.DMA_cap = 2; 3340 } 3341 sc->sc_wdcdev.set_modes = opti_setup_channel; 3342 3343 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3344 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3345 3346 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3347 OPTI_REG_INIT_CONTROL); 3348 3349 interface = PCI_INTERFACE(pa->pa_class); 3350 3351 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3352 cp = &sc->pciide_channels[channel]; 3353 if (pciide_chansetup(sc, channel, interface) == 0) 3354 continue; 3355 if (channel == 1 && 3356 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3357 printf("%s: %s channel ignored (disabled)\n", 3358 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3359 continue; 3360 } 3361 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3362 pciide_pci_intr); 3363 if (cp->hw_ok == 0) 3364 continue; 3365 pciide_map_compat_intr(pa, cp, channel, interface); 3366 if (cp->hw_ok == 0) 3367 continue; 3368 opti_setup_channel(&cp->wdc_channel); 3369 } 3370 } 3371 3372 void 3373 opti_setup_channel(chp) 3374 struct channel_softc *chp; 3375 { 3376 struct ata_drive_datas *drvp; 3377 struct pciide_channel *cp = (struct pciide_channel*)chp; 3378 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3379 int drive, spd; 3380 int mode[2]; 3381 u_int8_t rv, mr; 3382 3383 /* 3384 * The `Delay' and `Address Setup Time' fields of the 3385 * Miscellaneous Register are always zero initially. 3386 */ 3387 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3388 mr &= ~(OPTI_MISC_DELAY_MASK | 3389 OPTI_MISC_ADDR_SETUP_MASK | 3390 OPTI_MISC_INDEX_MASK); 3391 3392 /* Prime the control register before setting timing values */ 3393 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3394 3395 /* Determine the clockrate of the PCIbus the chip is attached to */ 3396 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3397 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3398 3399 /* setup DMA if needed */ 3400 pciide_channel_dma_setup(cp); 3401 3402 for (drive = 0; drive < 2; drive++) { 3403 drvp = &chp->ch_drive[drive]; 3404 /* If no drive, skip */ 3405 if ((drvp->drive_flags & DRIVE) == 0) { 3406 mode[drive] = -1; 3407 continue; 3408 } 3409 3410 if ((drvp->drive_flags & DRIVE_DMA)) { 3411 /* 3412 * Timings will be used for both PIO and DMA, 3413 * so adjust DMA mode if needed 3414 */ 3415 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3416 drvp->PIO_mode = drvp->DMA_mode + 2; 3417 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3418 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3419 drvp->PIO_mode - 2 : 0; 3420 if (drvp->DMA_mode == 0) 3421 drvp->PIO_mode = 0; 3422 3423 mode[drive] = drvp->DMA_mode + 5; 3424 } else 3425 mode[drive] = drvp->PIO_mode; 3426 3427 if (drive && mode[0] >= 0 && 3428 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3429 /* 3430 * Can't have two drives using different values 3431 * for `Address Setup Time'. 3432 * Slow down the faster drive to compensate. 3433 */ 3434 int d = (opti_tim_as[spd][mode[0]] > 3435 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3436 3437 mode[d] = mode[1-d]; 3438 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3439 chp->ch_drive[d].DMA_mode = 0; 3440 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3441 } 3442 } 3443 3444 for (drive = 0; drive < 2; drive++) { 3445 int m; 3446 if ((m = mode[drive]) < 0) 3447 continue; 3448 3449 /* Set the Address Setup Time and select appropriate index */ 3450 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3451 rv |= OPTI_MISC_INDEX(drive); 3452 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3453 3454 /* Set the pulse width and recovery timing parameters */ 3455 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3456 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3457 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3458 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3459 3460 /* Set the Enhanced Mode register appropriately */ 3461 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3462 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3463 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3464 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3465 } 3466 3467 /* Finally, enable the timings */ 3468 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3469 3470 pciide_print_modes(cp); 3471 } 3472
Indexes created Thu Oct 02 10:09:58 GMT 2025