pciide.c revision 1.68.2.17
1 /* $NetBSD: pciide.c,v 1.68.2.17 2001/02/04 18:44:41 he Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <vm/vm.h> 102 #include <vm/vm_param.h> 103 #include <vm/vm_kern.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/cy82c693var.h> 121 122 #include "opt_pciide.h" 123 124 /* inlines for reading/writing 8-bit PCI registers */ 125 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 126 int)); 127 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 128 int, u_int8_t)); 129 130 static __inline u_int8_t 131 pciide_pci_read(pc, pa, reg) 132 pci_chipset_tag_t pc; 133 pcitag_t pa; 134 int reg; 135 { 136 137 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 138 ((reg & 0x03) * 8) & 0xff); 139 } 140 141 static __inline void 142 pciide_pci_write(pc, pa, reg, val) 143 pci_chipset_tag_t pc; 144 pcitag_t pa; 145 int reg; 146 u_int8_t val; 147 { 148 pcireg_t pcival; 149 150 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 151 pcival &= ~(0xff << ((reg & 0x03) * 8)); 152 pcival |= (val << ((reg & 0x03) * 8)); 153 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 154 } 155 156 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 157 158 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 159 void piix_setup_channel __P((struct channel_softc*)); 160 void piix3_4_setup_channel __P((struct channel_softc*)); 161 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 162 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 163 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 164 165 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 166 void amd756_setup_channel __P((struct channel_softc*)); 167 168 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 169 void apollo_setup_channel __P((struct channel_softc*)); 170 171 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 172 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 173 void cmd0643_9_setup_channel __P((struct channel_softc*)); 174 void cmd_channel_map __P((struct pci_attach_args *, 175 struct pciide_softc *, int)); 176 int cmd_pci_intr __P((void *)); 177 void cmd646_9_irqack __P((struct channel_softc *)); 178 179 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 180 void cy693_setup_channel __P((struct channel_softc*)); 181 182 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 183 void sis_setup_channel __P((struct channel_softc*)); 184 185 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 186 void acer_setup_channel __P((struct channel_softc*)); 187 int acer_pci_intr __P((void *)); 188 189 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 190 void pdc202xx_setup_channel __P((struct channel_softc*)); 191 int pdc202xx_pci_intr __P((void *)); 192 193 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 194 void opti_setup_channel __P((struct channel_softc*)); 195 196 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 197 void hpt_setup_channel __P((struct channel_softc*)); 198 int hpt_pci_intr __P((void *)); 199 200 void pciide_channel_dma_setup __P((struct pciide_channel *)); 201 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 202 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 203 void pciide_dma_start __P((void*, int, int)); 204 int pciide_dma_finish __P((void*, int, int, int)); 205 void pciide_irqack __P((struct channel_softc *)); 206 void pciide_print_modes __P((struct pciide_channel *)); 207 208 struct pciide_product_desc { 209 u_int32_t ide_product; 210 int ide_flags; 211 const char *ide_name; 212 /* map and setup chip, probe drives */ 213 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 214 }; 215 216 /* Flags for ide_flags */ 217 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 218 219 /* Default product description for devices not known from this controller */ 220 const struct pciide_product_desc default_product_desc = { 221 0, 222 0, 223 "Generic PCI IDE controller", 224 default_chip_map, 225 }; 226 227 const struct pciide_product_desc pciide_intel_products[] = { 228 { PCI_PRODUCT_INTEL_82092AA, 229 0, 230 "Intel 82092AA IDE controller", 231 default_chip_map, 232 }, 233 { PCI_PRODUCT_INTEL_82371FB_IDE, 234 0, 235 "Intel 82371FB IDE controller (PIIX)", 236 piix_chip_map, 237 }, 238 { PCI_PRODUCT_INTEL_82371SB_IDE, 239 0, 240 "Intel 82371SB IDE Interface (PIIX3)", 241 piix_chip_map, 242 }, 243 { PCI_PRODUCT_INTEL_82371AB_IDE, 244 0, 245 "Intel 82371AB IDE controller (PIIX4)", 246 piix_chip_map, 247 }, 248 { PCI_PRODUCT_INTEL_82801AA_IDE, 249 0, 250 "Intel 82801AA IDE Controller (ICH)", 251 piix_chip_map, 252 }, 253 { PCI_PRODUCT_INTEL_82801AB_IDE, 254 0, 255 "Intel 82801AB IDE Controller (ICH0)", 256 piix_chip_map, 257 }, 258 { PCI_PRODUCT_INTEL_82801BA_IDE, 259 0, 260 "Intel 82801BA IDE Controller (ICH2)", 261 piix_chip_map, 262 }, 263 { 0, 264 0, 265 NULL, 266 } 267 }; 268 269 const struct pciide_product_desc pciide_amd_products[] = { 270 { PCI_PRODUCT_AMD_PBC756_IDE, 271 0, 272 "Advanced Micro Devices AMD756 IDE Controller", 273 amd756_chip_map 274 }, 275 { 0, 276 0, 277 NULL, 278 } 279 }; 280 281 const struct pciide_product_desc pciide_cmd_products[] = { 282 { PCI_PRODUCT_CMDTECH_640, 283 0, 284 "CMD Technology PCI0640", 285 cmd_chip_map 286 }, 287 { PCI_PRODUCT_CMDTECH_643, 288 0, 289 "CMD Technology PCI0643", 290 cmd0643_9_chip_map, 291 }, 292 { PCI_PRODUCT_CMDTECH_646, 293 0, 294 "CMD Technology PCI0646", 295 cmd0643_9_chip_map, 296 }, 297 { PCI_PRODUCT_CMDTECH_648, 298 IDE_PCI_CLASS_OVERRIDE, 299 "CMD Technology PCI0648", 300 cmd0643_9_chip_map, 301 }, 302 { PCI_PRODUCT_CMDTECH_649, 303 IDE_PCI_CLASS_OVERRIDE, 304 "CMD Technology PCI0649", 305 cmd0643_9_chip_map, 306 }, 307 { 0, 308 0, 309 NULL, 310 } 311 }; 312 313 const struct pciide_product_desc pciide_via_products[] = { 314 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 315 0, 316 "VIA Tech VT82C586 IDE Controller", 317 apollo_chip_map, 318 }, 319 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 320 0, 321 "VIA Tech VT82C586A IDE Controller", 322 apollo_chip_map, 323 }, 324 { 0, 325 0, 326 NULL, 327 } 328 }; 329 330 const struct pciide_product_desc pciide_cypress_products[] = { 331 { PCI_PRODUCT_CONTAQ_82C693, 332 0, 333 "Cypress 82C693 IDE Controller", 334 cy693_chip_map, 335 }, 336 { 0, 337 0, 338 NULL, 339 } 340 }; 341 342 const struct pciide_product_desc pciide_sis_products[] = { 343 { PCI_PRODUCT_SIS_5597_IDE, 344 0, 345 "Silicon Integrated System 5597/5598 IDE controller", 346 sis_chip_map, 347 }, 348 { 0, 349 0, 350 NULL, 351 } 352 }; 353 354 const struct pciide_product_desc pciide_acer_products[] = { 355 { PCI_PRODUCT_ALI_M5229, 356 0, 357 "Acer Labs M5229 UDMA IDE Controller", 358 acer_chip_map, 359 }, 360 { 0, 361 0, 362 NULL, 363 } 364 }; 365 366 const struct pciide_product_desc pciide_promise_products[] = { 367 { PCI_PRODUCT_PROMISE_ULTRA33, 368 IDE_PCI_CLASS_OVERRIDE, 369 "Promise Ultra33/ATA Bus Master IDE Accelerator", 370 pdc202xx_chip_map, 371 }, 372 { PCI_PRODUCT_PROMISE_ULTRA66, 373 IDE_PCI_CLASS_OVERRIDE, 374 "Promise Ultra66/ATA Bus Master IDE Accelerator", 375 pdc202xx_chip_map, 376 }, 377 { PCI_PRODUCT_PROMISE_ULTRA100, 378 IDE_PCI_CLASS_OVERRIDE, 379 "Promise Ultra100/ATA Bus Master IDE Accelerator", 380 pdc202xx_chip_map, 381 }, 382 { PCI_PRODUCT_PROMISE_ULTRA100X, 383 IDE_PCI_CLASS_OVERRIDE, 384 "Promise Ultra100/ATA Bus Master IDE Accelerator", 385 pdc202xx_chip_map, 386 }, 387 { 0, 388 0, 389 NULL, 390 } 391 }; 392 393 const struct pciide_product_desc pciide_opti_products[] = { 394 { PCI_PRODUCT_OPTI_82C621, 395 0, 396 "OPTi 82c621 PCI IDE controller", 397 opti_chip_map, 398 }, 399 { PCI_PRODUCT_OPTI_82C568, 400 0, 401 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 402 opti_chip_map, 403 }, 404 { PCI_PRODUCT_OPTI_82D568, 405 0, 406 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 407 opti_chip_map, 408 }, 409 { 0, 410 0, 411 NULL, 412 } 413 }; 414 415 const struct pciide_product_desc pciide_triones_products[] = { 416 { PCI_PRODUCT_TRIONES_HPT366, 417 IDE_PCI_CLASS_OVERRIDE, 418 "Triones/Highpoint HPT366/370 IDE Controller", 419 hpt_chip_map, 420 }, 421 { 0, 422 0, 423 NULL, 424 } 425 }; 426 427 struct pciide_vendor_desc { 428 u_int32_t ide_vendor; 429 const struct pciide_product_desc *ide_products; 430 }; 431 432 const struct pciide_vendor_desc pciide_vendors[] = { 433 { PCI_VENDOR_INTEL, pciide_intel_products }, 434 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 435 { PCI_VENDOR_VIATECH, pciide_via_products }, 436 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 437 { PCI_VENDOR_SIS, pciide_sis_products }, 438 { PCI_VENDOR_ALI, pciide_acer_products }, 439 { PCI_VENDOR_PROMISE, pciide_promise_products }, 440 { PCI_VENDOR_AMD, pciide_amd_products }, 441 { PCI_VENDOR_OPTI, pciide_opti_products }, 442 { PCI_VENDOR_TRIONES, pciide_triones_products }, 443 { 0, NULL } 444 }; 445 446 /* options passed via the 'flags' config keyword */ 447 #define PCIIDE_OPTIONS_DMA 0x01 448 449 int pciide_match __P((struct device *, struct cfdata *, void *)); 450 void pciide_attach __P((struct device *, struct device *, void *)); 451 452 struct cfattach pciide_ca = { 453 sizeof(struct pciide_softc), pciide_match, pciide_attach 454 }; 455 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 456 int pciide_mapregs_compat __P(( struct pci_attach_args *, 457 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 458 int pciide_mapregs_native __P((struct pci_attach_args *, 459 struct pciide_channel *, bus_size_t *, bus_size_t *, 460 int (*pci_intr) __P((void *)))); 461 void pciide_mapreg_dma __P((struct pciide_softc *, 462 struct pci_attach_args *)); 463 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 464 void pciide_mapchan __P((struct pci_attach_args *, 465 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 466 int (*pci_intr) __P((void *)))); 467 int pciide_chan_candisable __P((struct pciide_channel *)); 468 void pciide_map_compat_intr __P(( struct pci_attach_args *, 469 struct pciide_channel *, int, int)); 470 int pciide_print __P((void *, const char *pnp)); 471 int pciide_compat_intr __P((void *)); 472 int pciide_pci_intr __P((void *)); 473 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 474 475 const struct pciide_product_desc * 476 pciide_lookup_product(id) 477 u_int32_t id; 478 { 479 const struct pciide_product_desc *pp; 480 const struct pciide_vendor_desc *vp; 481 482 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 483 if (PCI_VENDOR(id) == vp->ide_vendor) 484 break; 485 486 if ((pp = vp->ide_products) == NULL) 487 return NULL; 488 489 for (; pp->ide_name != NULL; pp++) 490 if (PCI_PRODUCT(id) == pp->ide_product) 491 break; 492 493 if (pp->ide_name == NULL) 494 return NULL; 495 return pp; 496 } 497 498 int 499 pciide_match(parent, match, aux) 500 struct device *parent; 501 struct cfdata *match; 502 void *aux; 503 { 504 struct pci_attach_args *pa = aux; 505 const struct pciide_product_desc *pp; 506 507 /* 508 * Check the ID register to see that it's a PCI IDE controller. 509 * If it is, we assume that we can deal with it; it _should_ 510 * work in a standardized way... 511 */ 512 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 513 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 514 return (1); 515 } 516 517 /* 518 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 519 * controllers. Let see if we can deal with it anyway. 520 */ 521 pp = pciide_lookup_product(pa->pa_id); 522 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 523 return (1); 524 } 525 526 return (0); 527 } 528 529 void 530 pciide_attach(parent, self, aux) 531 struct device *parent, *self; 532 void *aux; 533 { 534 struct pci_attach_args *pa = aux; 535 pci_chipset_tag_t pc = pa->pa_pc; 536 pcitag_t tag = pa->pa_tag; 537 struct pciide_softc *sc = (struct pciide_softc *)self; 538 pcireg_t csr; 539 char devinfo[256]; 540 const char *displaydev; 541 542 sc->sc_pp = pciide_lookup_product(pa->pa_id); 543 if (sc->sc_pp == NULL) { 544 sc->sc_pp = &default_product_desc; 545 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 546 displaydev = devinfo; 547 } else 548 displaydev = sc->sc_pp->ide_name; 549 550 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 551 552 sc->sc_pc = pa->pa_pc; 553 sc->sc_tag = pa->pa_tag; 554 #ifdef WDCDEBUG 555 if (wdcdebug_pciide_mask & DEBUG_PROBE) 556 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 557 #endif 558 sc->sc_pp->chip_map(sc, pa); 559 560 if (sc->sc_dma_ok) { 561 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 562 csr |= PCI_COMMAND_MASTER_ENABLE; 563 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 564 } 565 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 566 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 567 } 568 569 /* tell wether the chip is enabled or not */ 570 int 571 pciide_chipen(sc, pa) 572 struct pciide_softc *sc; 573 struct pci_attach_args *pa; 574 { 575 pcireg_t csr; 576 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 577 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 578 PCI_COMMAND_STATUS_REG); 579 printf("%s: device disabled (at %s)\n", 580 sc->sc_wdcdev.sc_dev.dv_xname, 581 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 582 "device" : "bridge"); 583 return 0; 584 } 585 return 1; 586 } 587 588 int 589 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 590 struct pci_attach_args *pa; 591 struct pciide_channel *cp; 592 int compatchan; 593 bus_size_t *cmdsizep, *ctlsizep; 594 { 595 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 596 struct channel_softc *wdc_cp = &cp->wdc_channel; 597 598 cp->compat = 1; 599 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 600 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 601 602 wdc_cp->cmd_iot = pa->pa_iot; 603 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 604 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 605 printf("%s: couldn't map %s channel cmd regs\n", 606 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 607 return (0); 608 } 609 610 wdc_cp->ctl_iot = pa->pa_iot; 611 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 612 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 613 printf("%s: couldn't map %s channel ctl regs\n", 614 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 615 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 616 PCIIDE_COMPAT_CMD_SIZE); 617 return (0); 618 } 619 620 return (1); 621 } 622 623 int 624 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 625 struct pci_attach_args * pa; 626 struct pciide_channel *cp; 627 bus_size_t *cmdsizep, *ctlsizep; 628 int (*pci_intr) __P((void *)); 629 { 630 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 631 struct channel_softc *wdc_cp = &cp->wdc_channel; 632 const char *intrstr; 633 pci_intr_handle_t intrhandle; 634 635 cp->compat = 0; 636 637 if (sc->sc_pci_ih == NULL) { 638 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 639 pa->pa_intrline, &intrhandle) != 0) { 640 printf("%s: couldn't map native-PCI interrupt\n", 641 sc->sc_wdcdev.sc_dev.dv_xname); 642 return 0; 643 } 644 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 645 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 646 intrhandle, IPL_BIO, pci_intr, sc); 647 if (sc->sc_pci_ih != NULL) { 648 printf("%s: using %s for native-PCI interrupt\n", 649 sc->sc_wdcdev.sc_dev.dv_xname, 650 intrstr ? intrstr : "unknown interrupt"); 651 } else { 652 printf("%s: couldn't establish native-PCI interrupt", 653 sc->sc_wdcdev.sc_dev.dv_xname); 654 if (intrstr != NULL) 655 printf(" at %s", intrstr); 656 printf("\n"); 657 return 0; 658 } 659 } 660 cp->ih = sc->sc_pci_ih; 661 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 662 PCI_MAPREG_TYPE_IO, 0, 663 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 664 printf("%s: couldn't map %s channel cmd regs\n", 665 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 666 return 0; 667 } 668 669 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 670 PCI_MAPREG_TYPE_IO, 0, 671 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 672 printf("%s: couldn't map %s channel ctl regs\n", 673 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 674 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 675 return 0; 676 } 677 return (1); 678 } 679 680 void 681 pciide_mapreg_dma(sc, pa) 682 struct pciide_softc *sc; 683 struct pci_attach_args *pa; 684 { 685 pcireg_t maptype; 686 687 /* 688 * Map DMA registers 689 * 690 * Note that sc_dma_ok is the right variable to test to see if 691 * DMA can be done. If the interface doesn't support DMA, 692 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 693 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 694 * non-zero if the interface supports DMA and the registers 695 * could be mapped. 696 * 697 * XXX Note that despite the fact that the Bus Master IDE specs 698 * XXX say that "The bus master IDE function uses 16 bytes of IO 699 * XXX space," some controllers (at least the United 700 * XXX Microelectronics UM8886BF) place it in memory space. 701 */ 702 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 703 PCIIDE_REG_BUS_MASTER_DMA); 704 705 switch (maptype) { 706 case PCI_MAPREG_TYPE_IO: 707 case PCI_MAPREG_MEM_TYPE_32BIT: 708 sc->sc_dma_ok = (pci_mapreg_map(pa, 709 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 710 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 711 sc->sc_dmat = pa->pa_dmat; 712 if (sc->sc_dma_ok == 0) { 713 printf(", but unused (couldn't map registers)"); 714 } else { 715 sc->sc_wdcdev.dma_arg = sc; 716 sc->sc_wdcdev.dma_init = pciide_dma_init; 717 sc->sc_wdcdev.dma_start = pciide_dma_start; 718 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 719 } 720 break; 721 722 default: 723 sc->sc_dma_ok = 0; 724 printf(", but unsupported register maptype (0x%x)", maptype); 725 } 726 } 727 728 int 729 pciide_compat_intr(arg) 730 void *arg; 731 { 732 struct pciide_channel *cp = arg; 733 734 #ifdef DIAGNOSTIC 735 /* should only be called for a compat channel */ 736 if (cp->compat == 0) 737 panic("pciide compat intr called for non-compat chan %p\n", cp); 738 #endif 739 return (wdcintr(&cp->wdc_channel)); 740 } 741 742 int 743 pciide_pci_intr(arg) 744 void *arg; 745 { 746 struct pciide_softc *sc = arg; 747 struct pciide_channel *cp; 748 struct channel_softc *wdc_cp; 749 int i, rv, crv; 750 751 rv = 0; 752 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 753 cp = &sc->pciide_channels[i]; 754 wdc_cp = &cp->wdc_channel; 755 756 /* If a compat channel skip. */ 757 if (cp->compat) 758 continue; 759 /* if this channel not waiting for intr, skip */ 760 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 761 continue; 762 763 crv = wdcintr(wdc_cp); 764 if (crv == 0) 765 ; /* leave rv alone */ 766 else if (crv == 1) 767 rv = 1; /* claim the intr */ 768 else if (rv == 0) /* crv should be -1 in this case */ 769 rv = crv; /* if we've done no better, take it */ 770 } 771 return (rv); 772 } 773 774 void 775 pciide_channel_dma_setup(cp) 776 struct pciide_channel *cp; 777 { 778 int drive; 779 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 780 struct ata_drive_datas *drvp; 781 782 for (drive = 0; drive < 2; drive++) { 783 drvp = &cp->wdc_channel.ch_drive[drive]; 784 /* If no drive, skip */ 785 if ((drvp->drive_flags & DRIVE) == 0) 786 continue; 787 /* setup DMA if needed */ 788 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 789 (drvp->drive_flags & DRIVE_UDMA) == 0) || 790 sc->sc_dma_ok == 0) { 791 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 792 continue; 793 } 794 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 795 != 0) { 796 /* Abort DMA setup */ 797 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 798 continue; 799 } 800 } 801 } 802 803 int 804 pciide_dma_table_setup(sc, channel, drive) 805 struct pciide_softc *sc; 806 int channel, drive; 807 { 808 bus_dma_segment_t seg; 809 int error, rseg; 810 const bus_size_t dma_table_size = 811 sizeof(struct idedma_table) * NIDEDMA_TABLES; 812 struct pciide_dma_maps *dma_maps = 813 &sc->pciide_channels[channel].dma_maps[drive]; 814 815 /* If table was already allocated, just return */ 816 if (dma_maps->dma_table) 817 return 0; 818 819 /* Allocate memory for the DMA tables and map it */ 820 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 821 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 822 BUS_DMA_NOWAIT)) != 0) { 823 printf("%s:%d: unable to allocate table DMA for " 824 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 825 channel, drive, error); 826 return error; 827 } 828 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 829 dma_table_size, 830 (caddr_t *)&dma_maps->dma_table, 831 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 832 printf("%s:%d: unable to map table DMA for" 833 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 834 channel, drive, error); 835 return error; 836 } 837 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 838 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 839 seg.ds_addr), DEBUG_PROBE); 840 841 /* Create and load table DMA map for this disk */ 842 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 843 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 844 &dma_maps->dmamap_table)) != 0) { 845 printf("%s:%d: unable to create table DMA map for " 846 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 847 channel, drive, error); 848 return error; 849 } 850 if ((error = bus_dmamap_load(sc->sc_dmat, 851 dma_maps->dmamap_table, 852 dma_maps->dma_table, 853 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 854 printf("%s:%d: unable to load table DMA map for " 855 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 856 channel, drive, error); 857 return error; 858 } 859 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 860 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 861 /* Create a xfer DMA map for this drive */ 862 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 863 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 864 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 865 &dma_maps->dmamap_xfer)) != 0) { 866 printf("%s:%d: unable to create xfer DMA map for " 867 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 868 channel, drive, error); 869 return error; 870 } 871 return 0; 872 } 873 874 int 875 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 876 void *v; 877 int channel, drive; 878 void *databuf; 879 size_t datalen; 880 int flags; 881 { 882 struct pciide_softc *sc = v; 883 int error, seg; 884 struct pciide_dma_maps *dma_maps = 885 &sc->pciide_channels[channel].dma_maps[drive]; 886 887 error = bus_dmamap_load(sc->sc_dmat, 888 dma_maps->dmamap_xfer, 889 databuf, datalen, NULL, BUS_DMA_NOWAIT); 890 if (error) { 891 printf("%s:%d: unable to load xfer DMA map for" 892 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 893 channel, drive, error); 894 return error; 895 } 896 897 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 898 dma_maps->dmamap_xfer->dm_mapsize, 899 (flags & WDC_DMA_READ) ? 900 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 901 902 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 903 #ifdef DIAGNOSTIC 904 /* A segment must not cross a 64k boundary */ 905 { 906 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 907 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 908 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 909 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 910 printf("pciide_dma: segment %d physical addr 0x%lx" 911 " len 0x%lx not properly aligned\n", 912 seg, phys, len); 913 panic("pciide_dma: buf align"); 914 } 915 } 916 #endif 917 dma_maps->dma_table[seg].base_addr = 918 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 919 dma_maps->dma_table[seg].byte_count = 920 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 921 IDEDMA_BYTE_COUNT_MASK); 922 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 923 seg, le32toh(dma_maps->dma_table[seg].byte_count), 924 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 925 926 } 927 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 928 htole32(IDEDMA_BYTE_COUNT_EOT); 929 930 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 931 dma_maps->dmamap_table->dm_mapsize, 932 BUS_DMASYNC_PREWRITE); 933 934 /* Maps are ready. Start DMA function */ 935 #ifdef DIAGNOSTIC 936 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 937 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 938 dma_maps->dmamap_table->dm_segs[0].ds_addr); 939 panic("pciide_dma_init: table align"); 940 } 941 #endif 942 943 /* Clear status bits */ 944 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 945 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 946 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 947 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 948 /* Write table addr */ 949 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 950 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 951 dma_maps->dmamap_table->dm_segs[0].ds_addr); 952 /* set read/write */ 953 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 954 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 955 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 956 /* remember flags */ 957 dma_maps->dma_flags = flags; 958 return 0; 959 } 960 961 void 962 pciide_dma_start(v, channel, drive) 963 void *v; 964 int channel, drive; 965 { 966 struct pciide_softc *sc = v; 967 968 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 969 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 970 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 971 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 972 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 973 } 974 975 int 976 pciide_dma_finish(v, channel, drive, force) 977 void *v; 978 int channel, drive; 979 int force; 980 { 981 struct pciide_softc *sc = v; 982 u_int8_t status; 983 int error = 0; 984 struct pciide_dma_maps *dma_maps = 985 &sc->pciide_channels[channel].dma_maps[drive]; 986 987 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 988 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 989 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 990 DEBUG_XFERS); 991 992 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 993 return WDC_DMAST_NOIRQ; 994 995 /* stop DMA channel */ 996 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 997 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 998 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 999 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1000 1001 /* Unload the map of the data buffer */ 1002 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1003 dma_maps->dmamap_xfer->dm_mapsize, 1004 (dma_maps->dma_flags & WDC_DMA_READ) ? 1005 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1006 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1007 1008 if ((status & IDEDMA_CTL_ERR) != 0) { 1009 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1010 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1011 error |= WDC_DMAST_ERR; 1012 } 1013 1014 if ((status & IDEDMA_CTL_INTR) == 0) { 1015 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1016 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1017 drive, status); 1018 error |= WDC_DMAST_NOIRQ; 1019 } 1020 1021 if ((status & IDEDMA_CTL_ACT) != 0) { 1022 /* data underrun, may be a valid condition for ATAPI */ 1023 error |= WDC_DMAST_UNDER; 1024 } 1025 return error; 1026 } 1027 1028 void 1029 pciide_irqack(chp) 1030 struct channel_softc *chp; 1031 { 1032 struct pciide_channel *cp = (struct pciide_channel*)chp; 1033 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1034 1035 /* clear status bits in IDE DMA registers */ 1036 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1037 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1038 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1039 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1040 } 1041 1042 /* some common code used by several chip_map */ 1043 int 1044 pciide_chansetup(sc, channel, interface) 1045 struct pciide_softc *sc; 1046 int channel; 1047 pcireg_t interface; 1048 { 1049 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1050 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1051 cp->name = PCIIDE_CHANNEL_NAME(channel); 1052 cp->wdc_channel.channel = channel; 1053 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1054 cp->wdc_channel.ch_queue = 1055 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1056 if (cp->wdc_channel.ch_queue == NULL) { 1057 printf("%s %s channel: " 1058 "can't allocate memory for command queue", 1059 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1060 return 0; 1061 } 1062 printf("%s: %s channel %s to %s mode\n", 1063 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1064 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1065 "configured" : "wired", 1066 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1067 "native-PCI" : "compatibility"); 1068 return 1; 1069 } 1070 1071 /* some common code used by several chip channel_map */ 1072 void 1073 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1074 struct pci_attach_args *pa; 1075 struct pciide_channel *cp; 1076 pcireg_t interface; 1077 bus_size_t *cmdsizep, *ctlsizep; 1078 int (*pci_intr) __P((void *)); 1079 { 1080 struct channel_softc *wdc_cp = &cp->wdc_channel; 1081 1082 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1083 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1084 pci_intr); 1085 else 1086 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1087 wdc_cp->channel, cmdsizep, ctlsizep); 1088 1089 if (cp->hw_ok == 0) 1090 return; 1091 wdc_cp->data32iot = wdc_cp->cmd_iot; 1092 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1093 wdcattach(wdc_cp); 1094 } 1095 1096 /* 1097 * Generic code to call to know if a channel can be disabled. Return 1 1098 * if channel can be disabled, 0 if not 1099 */ 1100 int 1101 pciide_chan_candisable(cp) 1102 struct pciide_channel *cp; 1103 { 1104 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1105 struct channel_softc *wdc_cp = &cp->wdc_channel; 1106 1107 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1108 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1109 printf("%s: disabling %s channel (no drives)\n", 1110 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1111 cp->hw_ok = 0; 1112 return 1; 1113 } 1114 return 0; 1115 } 1116 1117 /* 1118 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1119 * Set hw_ok=0 on failure 1120 */ 1121 void 1122 pciide_map_compat_intr(pa, cp, compatchan, interface) 1123 struct pci_attach_args *pa; 1124 struct pciide_channel *cp; 1125 int compatchan, interface; 1126 { 1127 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1128 struct channel_softc *wdc_cp = &cp->wdc_channel; 1129 1130 if (cp->hw_ok == 0) 1131 return; 1132 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1133 return; 1134 1135 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1136 pa, compatchan, pciide_compat_intr, cp); 1137 if (cp->ih == NULL) { 1138 printf("%s: no compatibility interrupt for use by %s " 1139 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1140 cp->hw_ok = 0; 1141 } 1142 } 1143 1144 void 1145 pciide_print_modes(cp) 1146 struct pciide_channel *cp; 1147 { 1148 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1149 int drive; 1150 struct channel_softc *chp; 1151 struct ata_drive_datas *drvp; 1152 1153 chp = &cp->wdc_channel; 1154 for (drive = 0; drive < 2; drive++) { 1155 drvp = &chp->ch_drive[drive]; 1156 if ((drvp->drive_flags & DRIVE) == 0) 1157 continue; 1158 printf("%s(%s:%d:%d): using PIO mode %d", 1159 drvp->drv_softc->dv_xname, 1160 sc->sc_wdcdev.sc_dev.dv_xname, 1161 chp->channel, drive, drvp->PIO_mode); 1162 if (drvp->drive_flags & DRIVE_DMA) 1163 printf(", DMA mode %d", drvp->DMA_mode); 1164 if (drvp->drive_flags & DRIVE_UDMA) 1165 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1166 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1167 printf(" (using DMA data transfers)"); 1168 printf("\n"); 1169 } 1170 } 1171 1172 void 1173 default_chip_map(sc, pa) 1174 struct pciide_softc *sc; 1175 struct pci_attach_args *pa; 1176 { 1177 struct pciide_channel *cp; 1178 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1179 pcireg_t csr; 1180 int channel, drive; 1181 struct ata_drive_datas *drvp; 1182 u_int8_t idedma_ctl; 1183 bus_size_t cmdsize, ctlsize; 1184 char *failreason; 1185 1186 if (pciide_chipen(sc, pa) == 0) 1187 return; 1188 1189 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1190 printf("%s: bus-master DMA support present", 1191 sc->sc_wdcdev.sc_dev.dv_xname); 1192 if (sc->sc_pp == &default_product_desc && 1193 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1194 PCIIDE_OPTIONS_DMA) == 0) { 1195 printf(", but unused (no driver support)"); 1196 sc->sc_dma_ok = 0; 1197 } else { 1198 pciide_mapreg_dma(sc, pa); 1199 if (sc->sc_dma_ok != 0) 1200 printf(", used without full driver " 1201 "support"); 1202 } 1203 } else { 1204 printf("%s: hardware does not support DMA", 1205 sc->sc_wdcdev.sc_dev.dv_xname); 1206 sc->sc_dma_ok = 0; 1207 } 1208 printf("\n"); 1209 if (sc->sc_dma_ok) { 1210 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1211 sc->sc_wdcdev.irqack = pciide_irqack; 1212 } 1213 sc->sc_wdcdev.PIO_cap = 0; 1214 sc->sc_wdcdev.DMA_cap = 0; 1215 1216 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1217 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1218 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1219 1220 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1221 cp = &sc->pciide_channels[channel]; 1222 if (pciide_chansetup(sc, channel, interface) == 0) 1223 continue; 1224 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1225 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1226 &ctlsize, pciide_pci_intr); 1227 } else { 1228 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1229 channel, &cmdsize, &ctlsize); 1230 } 1231 if (cp->hw_ok == 0) 1232 continue; 1233 /* 1234 * Check to see if something appears to be there. 1235 */ 1236 failreason = NULL; 1237 if (!wdcprobe(&cp->wdc_channel)) { 1238 failreason = "not responding; disabled or no drives?"; 1239 goto next; 1240 } 1241 /* 1242 * Now, make sure it's actually attributable to this PCI IDE 1243 * channel by trying to access the channel again while the 1244 * PCI IDE controller's I/O space is disabled. (If the 1245 * channel no longer appears to be there, it belongs to 1246 * this controller.) YUCK! 1247 */ 1248 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1249 PCI_COMMAND_STATUS_REG); 1250 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1251 csr & ~PCI_COMMAND_IO_ENABLE); 1252 if (wdcprobe(&cp->wdc_channel)) 1253 failreason = "other hardware responding at addresses"; 1254 pci_conf_write(sc->sc_pc, sc->sc_tag, 1255 PCI_COMMAND_STATUS_REG, csr); 1256 next: 1257 if (failreason) { 1258 printf("%s: %s channel ignored (%s)\n", 1259 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1260 failreason); 1261 cp->hw_ok = 0; 1262 bus_space_unmap(cp->wdc_channel.cmd_iot, 1263 cp->wdc_channel.cmd_ioh, cmdsize); 1264 bus_space_unmap(cp->wdc_channel.ctl_iot, 1265 cp->wdc_channel.ctl_ioh, ctlsize); 1266 } else { 1267 pciide_map_compat_intr(pa, cp, channel, interface); 1268 } 1269 if (cp->hw_ok) { 1270 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1271 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1272 wdcattach(&cp->wdc_channel); 1273 } 1274 } 1275 1276 if (sc->sc_dma_ok == 0) 1277 return; 1278 1279 /* Allocate DMA maps */ 1280 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1281 idedma_ctl = 0; 1282 cp = &sc->pciide_channels[channel]; 1283 for (drive = 0; drive < 2; drive++) { 1284 drvp = &cp->wdc_channel.ch_drive[drive]; 1285 /* If no drive, skip */ 1286 if ((drvp->drive_flags & DRIVE) == 0) 1287 continue; 1288 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1289 continue; 1290 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1291 /* Abort DMA setup */ 1292 printf("%s:%d:%d: can't allocate DMA maps, " 1293 "using PIO transfers\n", 1294 sc->sc_wdcdev.sc_dev.dv_xname, 1295 channel, drive); 1296 drvp->drive_flags &= ~DRIVE_DMA; 1297 } 1298 printf("%s:%d:%d: using DMA data transfers\n", 1299 sc->sc_wdcdev.sc_dev.dv_xname, 1300 channel, drive); 1301 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1302 } 1303 if (idedma_ctl != 0) { 1304 /* Add software bits in status register */ 1305 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1306 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1307 idedma_ctl); 1308 } 1309 } 1310 } 1311 1312 void 1313 piix_chip_map(sc, pa) 1314 struct pciide_softc *sc; 1315 struct pci_attach_args *pa; 1316 { 1317 struct pciide_channel *cp; 1318 int channel; 1319 u_int32_t idetim; 1320 bus_size_t cmdsize, ctlsize; 1321 1322 if (pciide_chipen(sc, pa) == 0) 1323 return; 1324 1325 printf("%s: bus-master DMA support present", 1326 sc->sc_wdcdev.sc_dev.dv_xname); 1327 pciide_mapreg_dma(sc, pa); 1328 printf("\n"); 1329 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1330 WDC_CAPABILITY_MODE; 1331 if (sc->sc_dma_ok) { 1332 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1333 sc->sc_wdcdev.irqack = pciide_irqack; 1334 switch(sc->sc_pp->ide_product) { 1335 case PCI_PRODUCT_INTEL_82371AB_IDE: 1336 case PCI_PRODUCT_INTEL_82801AA_IDE: 1337 case PCI_PRODUCT_INTEL_82801AB_IDE: 1338 case PCI_PRODUCT_INTEL_82801BA_IDE: 1339 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1340 } 1341 } 1342 sc->sc_wdcdev.PIO_cap = 4; 1343 sc->sc_wdcdev.DMA_cap = 2; 1344 switch(sc->sc_pp->ide_product) { 1345 case PCI_PRODUCT_INTEL_82801AA_IDE: 1346 case PCI_PRODUCT_INTEL_82801BA_IDE: 1347 sc->sc_wdcdev.UDMA_cap = 4; 1348 break; 1349 default: 1350 sc->sc_wdcdev.UDMA_cap = 2; 1351 } 1352 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1353 sc->sc_wdcdev.set_modes = piix_setup_channel; 1354 else 1355 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1356 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1357 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1358 1359 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1360 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1361 DEBUG_PROBE); 1362 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1363 WDCDEBUG_PRINT((", sidetim=0x%x", 1364 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1365 DEBUG_PROBE); 1366 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1367 WDCDEBUG_PRINT((", udamreg 0x%x", 1368 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1369 DEBUG_PROBE); 1370 } 1371 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1372 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1373 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1374 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1375 DEBUG_PROBE); 1376 } 1377 1378 } 1379 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1380 1381 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1382 cp = &sc->pciide_channels[channel]; 1383 /* PIIX is compat-only */ 1384 if (pciide_chansetup(sc, channel, 0) == 0) 1385 continue; 1386 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1387 if ((PIIX_IDETIM_READ(idetim, channel) & 1388 PIIX_IDETIM_IDE) == 0) { 1389 printf("%s: %s channel ignored (disabled)\n", 1390 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1391 continue; 1392 } 1393 /* PIIX are compat-only pciide devices */ 1394 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1395 if (cp->hw_ok == 0) 1396 continue; 1397 if (pciide_chan_candisable(cp)) { 1398 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1399 channel); 1400 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1401 idetim); 1402 } 1403 pciide_map_compat_intr(pa, cp, channel, 0); 1404 if (cp->hw_ok == 0) 1405 continue; 1406 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1407 } 1408 1409 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1410 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1411 DEBUG_PROBE); 1412 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1413 WDCDEBUG_PRINT((", sidetim=0x%x", 1414 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1415 DEBUG_PROBE); 1416 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1417 WDCDEBUG_PRINT((", udamreg 0x%x", 1418 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1419 DEBUG_PROBE); 1420 } 1421 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1422 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1423 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1424 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1425 DEBUG_PROBE); 1426 } 1427 } 1428 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1429 } 1430 1431 void 1432 piix_setup_channel(chp) 1433 struct channel_softc *chp; 1434 { 1435 u_int8_t mode[2], drive; 1436 u_int32_t oidetim, idetim, idedma_ctl; 1437 struct pciide_channel *cp = (struct pciide_channel*)chp; 1438 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1439 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1440 1441 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1442 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1443 idedma_ctl = 0; 1444 1445 /* set up new idetim: Enable IDE registers decode */ 1446 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1447 chp->channel); 1448 1449 /* setup DMA */ 1450 pciide_channel_dma_setup(cp); 1451 1452 /* 1453 * Here we have to mess up with drives mode: PIIX can't have 1454 * different timings for master and slave drives. 1455 * We need to find the best combination. 1456 */ 1457 1458 /* If both drives supports DMA, take the lower mode */ 1459 if ((drvp[0].drive_flags & DRIVE_DMA) && 1460 (drvp[1].drive_flags & DRIVE_DMA)) { 1461 mode[0] = mode[1] = 1462 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1463 drvp[0].DMA_mode = mode[0]; 1464 drvp[1].DMA_mode = mode[1]; 1465 goto ok; 1466 } 1467 /* 1468 * If only one drive supports DMA, use its mode, and 1469 * put the other one in PIO mode 0 if mode not compatible 1470 */ 1471 if (drvp[0].drive_flags & DRIVE_DMA) { 1472 mode[0] = drvp[0].DMA_mode; 1473 mode[1] = drvp[1].PIO_mode; 1474 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1475 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1476 mode[1] = drvp[1].PIO_mode = 0; 1477 goto ok; 1478 } 1479 if (drvp[1].drive_flags & DRIVE_DMA) { 1480 mode[1] = drvp[1].DMA_mode; 1481 mode[0] = drvp[0].PIO_mode; 1482 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1483 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1484 mode[0] = drvp[0].PIO_mode = 0; 1485 goto ok; 1486 } 1487 /* 1488 * If both drives are not DMA, takes the lower mode, unless 1489 * one of them is PIO mode < 2 1490 */ 1491 if (drvp[0].PIO_mode < 2) { 1492 mode[0] = drvp[0].PIO_mode = 0; 1493 mode[1] = drvp[1].PIO_mode; 1494 } else if (drvp[1].PIO_mode < 2) { 1495 mode[1] = drvp[1].PIO_mode = 0; 1496 mode[0] = drvp[0].PIO_mode; 1497 } else { 1498 mode[0] = mode[1] = 1499 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1500 drvp[0].PIO_mode = mode[0]; 1501 drvp[1].PIO_mode = mode[1]; 1502 } 1503 ok: /* The modes are setup */ 1504 for (drive = 0; drive < 2; drive++) { 1505 if (drvp[drive].drive_flags & DRIVE_DMA) { 1506 idetim |= piix_setup_idetim_timings( 1507 mode[drive], 1, chp->channel); 1508 goto end; 1509 } 1510 } 1511 /* If we are there, none of the drives are DMA */ 1512 if (mode[0] >= 2) 1513 idetim |= piix_setup_idetim_timings( 1514 mode[0], 0, chp->channel); 1515 else 1516 idetim |= piix_setup_idetim_timings( 1517 mode[1], 0, chp->channel); 1518 end: /* 1519 * timing mode is now set up in the controller. Enable 1520 * it per-drive 1521 */ 1522 for (drive = 0; drive < 2; drive++) { 1523 /* If no drive, skip */ 1524 if ((drvp[drive].drive_flags & DRIVE) == 0) 1525 continue; 1526 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1527 if (drvp[drive].drive_flags & DRIVE_DMA) 1528 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1529 } 1530 if (idedma_ctl != 0) { 1531 /* Add software bits in status register */ 1532 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1533 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1534 idedma_ctl); 1535 } 1536 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1537 pciide_print_modes(cp); 1538 } 1539 1540 void 1541 piix3_4_setup_channel(chp) 1542 struct channel_softc *chp; 1543 { 1544 struct ata_drive_datas *drvp; 1545 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1546 struct pciide_channel *cp = (struct pciide_channel*)chp; 1547 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1548 int drive; 1549 int channel = chp->channel; 1550 1551 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1552 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1553 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1554 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1555 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1556 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1557 PIIX_SIDETIM_RTC_MASK(channel)); 1558 1559 idedma_ctl = 0; 1560 /* If channel disabled, no need to go further */ 1561 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1562 return; 1563 /* set up new idetim: Enable IDE registers decode */ 1564 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1565 1566 /* setup DMA if needed */ 1567 pciide_channel_dma_setup(cp); 1568 1569 for (drive = 0; drive < 2; drive++) { 1570 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1571 PIIX_UDMATIM_SET(0x3, channel, drive)); 1572 drvp = &chp->ch_drive[drive]; 1573 /* If no drive, skip */ 1574 if ((drvp->drive_flags & DRIVE) == 0) 1575 continue; 1576 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1577 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1578 goto pio; 1579 1580 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1581 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1582 ideconf |= PIIX_CONFIG_PINGPONG; 1583 } 1584 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1585 /* setup Ultra/66 */ 1586 if (drvp->UDMA_mode > 2 && 1587 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1588 drvp->UDMA_mode = 2; 1589 if (drvp->UDMA_mode > 2) 1590 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1591 else 1592 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1593 } 1594 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1595 (drvp->drive_flags & DRIVE_UDMA)) { 1596 /* use Ultra/DMA */ 1597 drvp->drive_flags &= ~DRIVE_DMA; 1598 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1599 udmareg |= PIIX_UDMATIM_SET( 1600 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1601 } else { 1602 /* use Multiword DMA */ 1603 drvp->drive_flags &= ~DRIVE_UDMA; 1604 if (drive == 0) { 1605 idetim |= piix_setup_idetim_timings( 1606 drvp->DMA_mode, 1, channel); 1607 } else { 1608 sidetim |= piix_setup_sidetim_timings( 1609 drvp->DMA_mode, 1, channel); 1610 idetim =PIIX_IDETIM_SET(idetim, 1611 PIIX_IDETIM_SITRE, channel); 1612 } 1613 } 1614 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1615 1616 pio: /* use PIO mode */ 1617 idetim |= piix_setup_idetim_drvs(drvp); 1618 if (drive == 0) { 1619 idetim |= piix_setup_idetim_timings( 1620 drvp->PIO_mode, 0, channel); 1621 } else { 1622 sidetim |= piix_setup_sidetim_timings( 1623 drvp->PIO_mode, 0, channel); 1624 idetim =PIIX_IDETIM_SET(idetim, 1625 PIIX_IDETIM_SITRE, channel); 1626 } 1627 } 1628 if (idedma_ctl != 0) { 1629 /* Add software bits in status register */ 1630 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1631 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1632 idedma_ctl); 1633 } 1634 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1635 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1636 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1637 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1638 pciide_print_modes(cp); 1639 } 1640 1641 1642 /* setup ISP and RTC fields, based on mode */ 1643 static u_int32_t 1644 piix_setup_idetim_timings(mode, dma, channel) 1645 u_int8_t mode; 1646 u_int8_t dma; 1647 u_int8_t channel; 1648 { 1649 1650 if (dma) 1651 return PIIX_IDETIM_SET(0, 1652 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1653 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1654 channel); 1655 else 1656 return PIIX_IDETIM_SET(0, 1657 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1658 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1659 channel); 1660 } 1661 1662 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1663 static u_int32_t 1664 piix_setup_idetim_drvs(drvp) 1665 struct ata_drive_datas *drvp; 1666 { 1667 u_int32_t ret = 0; 1668 struct channel_softc *chp = drvp->chnl_softc; 1669 u_int8_t channel = chp->channel; 1670 u_int8_t drive = drvp->drive; 1671 1672 /* 1673 * If drive is using UDMA, timings setups are independant 1674 * So just check DMA and PIO here. 1675 */ 1676 if (drvp->drive_flags & DRIVE_DMA) { 1677 /* if mode = DMA mode 0, use compatible timings */ 1678 if ((drvp->drive_flags & DRIVE_DMA) && 1679 drvp->DMA_mode == 0) { 1680 drvp->PIO_mode = 0; 1681 return ret; 1682 } 1683 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1684 /* 1685 * PIO and DMA timings are the same, use fast timings for PIO 1686 * too, else use compat timings. 1687 */ 1688 if ((piix_isp_pio[drvp->PIO_mode] != 1689 piix_isp_dma[drvp->DMA_mode]) || 1690 (piix_rtc_pio[drvp->PIO_mode] != 1691 piix_rtc_dma[drvp->DMA_mode])) 1692 drvp->PIO_mode = 0; 1693 /* if PIO mode <= 2, use compat timings for PIO */ 1694 if (drvp->PIO_mode <= 2) { 1695 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1696 channel); 1697 return ret; 1698 } 1699 } 1700 1701 /* 1702 * Now setup PIO modes. If mode < 2, use compat timings. 1703 * Else enable fast timings. Enable IORDY and prefetch/post 1704 * if PIO mode >= 3. 1705 */ 1706 1707 if (drvp->PIO_mode < 2) 1708 return ret; 1709 1710 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1711 if (drvp->PIO_mode >= 3) { 1712 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1713 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1714 } 1715 return ret; 1716 } 1717 1718 /* setup values in SIDETIM registers, based on mode */ 1719 static u_int32_t 1720 piix_setup_sidetim_timings(mode, dma, channel) 1721 u_int8_t mode; 1722 u_int8_t dma; 1723 u_int8_t channel; 1724 { 1725 if (dma) 1726 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1727 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1728 else 1729 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1730 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1731 } 1732 1733 void 1734 amd756_chip_map(sc, pa) 1735 struct pciide_softc *sc; 1736 struct pci_attach_args *pa; 1737 { 1738 struct pciide_channel *cp; 1739 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1740 int channel; 1741 pcireg_t chanenable; 1742 bus_size_t cmdsize, ctlsize; 1743 1744 if (pciide_chipen(sc, pa) == 0) 1745 return; 1746 printf("%s: bus-master DMA support present", 1747 sc->sc_wdcdev.sc_dev.dv_xname); 1748 pciide_mapreg_dma(sc, pa); 1749 printf("\n"); 1750 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1751 WDC_CAPABILITY_MODE; 1752 if (sc->sc_dma_ok) { 1753 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1754 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1755 sc->sc_wdcdev.irqack = pciide_irqack; 1756 } 1757 sc->sc_wdcdev.PIO_cap = 4; 1758 sc->sc_wdcdev.DMA_cap = 2; 1759 sc->sc_wdcdev.UDMA_cap = 4; 1760 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1761 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1762 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1763 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1764 1765 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1766 DEBUG_PROBE); 1767 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1768 cp = &sc->pciide_channels[channel]; 1769 if (pciide_chansetup(sc, channel, interface) == 0) 1770 continue; 1771 1772 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1773 printf("%s: %s channel ignored (disabled)\n", 1774 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1775 continue; 1776 } 1777 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1778 pciide_pci_intr); 1779 1780 if (pciide_chan_candisable(cp)) 1781 chanenable &= ~AMD756_CHAN_EN(channel); 1782 pciide_map_compat_intr(pa, cp, channel, interface); 1783 if (cp->hw_ok == 0) 1784 continue; 1785 1786 amd756_setup_channel(&cp->wdc_channel); 1787 } 1788 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1789 chanenable); 1790 return; 1791 } 1792 1793 void 1794 amd756_setup_channel(chp) 1795 struct channel_softc *chp; 1796 { 1797 u_int32_t udmatim_reg, datatim_reg; 1798 u_int8_t idedma_ctl; 1799 int mode, drive; 1800 struct ata_drive_datas *drvp; 1801 struct pciide_channel *cp = (struct pciide_channel*)chp; 1802 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1803 #ifndef PCIIDE_AMD756_ENABLEDMA 1804 int rev = PCI_REVISION( 1805 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1806 #endif 1807 1808 idedma_ctl = 0; 1809 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1810 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1811 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1812 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1813 1814 /* setup DMA if needed */ 1815 pciide_channel_dma_setup(cp); 1816 1817 for (drive = 0; drive < 2; drive++) { 1818 drvp = &chp->ch_drive[drive]; 1819 /* If no drive, skip */ 1820 if ((drvp->drive_flags & DRIVE) == 0) 1821 continue; 1822 /* add timing values, setup DMA if needed */ 1823 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1824 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1825 mode = drvp->PIO_mode; 1826 goto pio; 1827 } 1828 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1829 (drvp->drive_flags & DRIVE_UDMA)) { 1830 /* use Ultra/DMA */ 1831 drvp->drive_flags &= ~DRIVE_DMA; 1832 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1833 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1834 AMD756_UDMA_TIME(chp->channel, drive, 1835 amd756_udma_tim[drvp->UDMA_mode]); 1836 /* can use PIO timings, MW DMA unused */ 1837 mode = drvp->PIO_mode; 1838 } else { 1839 /* use Multiword DMA, but only if revision is OK */ 1840 drvp->drive_flags &= ~DRIVE_UDMA; 1841 #ifndef PCIIDE_AMD756_ENABLEDMA 1842 /* 1843 * The workaround doesn't seem to be necessary 1844 * with all drives, so it can be disabled by 1845 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1846 * triggered. 1847 */ 1848 if (AMD756_CHIPREV_DISABLEDMA(rev)) { 1849 printf("%s:%d:%d: multi-word DMA disabled due " 1850 "to chip revision\n", 1851 sc->sc_wdcdev.sc_dev.dv_xname, 1852 chp->channel, drive); 1853 mode = drvp->PIO_mode; 1854 drvp->drive_flags &= ~DRIVE_DMA; 1855 goto pio; 1856 } 1857 #endif 1858 /* mode = min(pio, dma+2) */ 1859 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1860 mode = drvp->PIO_mode; 1861 else 1862 mode = drvp->DMA_mode + 2; 1863 } 1864 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1865 1866 pio: /* setup PIO mode */ 1867 if (mode <= 2) { 1868 drvp->DMA_mode = 0; 1869 drvp->PIO_mode = 0; 1870 mode = 0; 1871 } else { 1872 drvp->PIO_mode = mode; 1873 drvp->DMA_mode = mode - 2; 1874 } 1875 datatim_reg |= 1876 AMD756_DATATIM_PULSE(chp->channel, drive, 1877 amd756_pio_set[mode]) | 1878 AMD756_DATATIM_RECOV(chp->channel, drive, 1879 amd756_pio_rec[mode]); 1880 } 1881 if (idedma_ctl != 0) { 1882 /* Add software bits in status register */ 1883 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1884 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1885 idedma_ctl); 1886 } 1887 pciide_print_modes(cp); 1888 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1889 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1890 } 1891 1892 void 1893 apollo_chip_map(sc, pa) 1894 struct pciide_softc *sc; 1895 struct pci_attach_args *pa; 1896 { 1897 struct pciide_channel *cp; 1898 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1899 int rev = PCI_REVISION(pa->pa_class); 1900 int channel; 1901 u_int32_t ideconf, udma_conf, old_udma_conf; 1902 bus_size_t cmdsize, ctlsize; 1903 1904 if (pciide_chipen(sc, pa) == 0) 1905 return; 1906 printf("%s: bus-master DMA support present", 1907 sc->sc_wdcdev.sc_dev.dv_xname); 1908 pciide_mapreg_dma(sc, pa); 1909 printf("\n"); 1910 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1911 WDC_CAPABILITY_MODE; 1912 if (sc->sc_dma_ok) { 1913 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1914 sc->sc_wdcdev.irqack = pciide_irqack; 1915 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE 1916 && rev >= 6) 1917 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1918 } 1919 sc->sc_wdcdev.PIO_cap = 4; 1920 sc->sc_wdcdev.DMA_cap = 2; 1921 sc->sc_wdcdev.UDMA_cap = 2; 1922 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1923 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1924 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1925 1926 old_udma_conf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1927 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1928 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1929 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1930 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1931 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1932 old_udma_conf), 1933 DEBUG_PROBE); 1934 pci_conf_write(sc->sc_pc, sc->sc_tag, 1935 old_udma_conf | (APO_UDMA_PIO_MODE(0, 0) | APO_UDMA_EN(0, 0) | 1936 APO_UDMA_EN_MTH(0, 0) | APO_UDMA_CLK66(0)), 1937 APO_UDMA); 1938 udma_conf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1939 WDCDEBUG_PRINT(("apollo_chip_map: APO_UDMA now 0x%x\n", udma_conf), 1940 DEBUG_PROBE); 1941 if ((udma_conf & (APO_UDMA_PIO_MODE(0, 0) | APO_UDMA_EN(0, 0) | 1942 APO_UDMA_EN_MTH(0, 0))) == 1943 (APO_UDMA_PIO_MODE(0, 0) | APO_UDMA_EN(0, 0) | 1944 APO_UDMA_EN_MTH(0, 0))) { 1945 if ((udma_conf & APO_UDMA_CLK66(0)) == 1946 APO_UDMA_CLK66(0)) { 1947 printf("%s: Ultra/66 capable\n", 1948 sc->sc_wdcdev.sc_dev.dv_xname); 1949 sc->sc_wdcdev.UDMA_cap = 4; 1950 } else { 1951 printf("%s: Ultra/33 capable\n", 1952 sc->sc_wdcdev.sc_dev.dv_xname); 1953 sc->sc_wdcdev.UDMA_cap = 2; 1954 } 1955 } else { 1956 sc->sc_wdcdev.cap &= ~WDC_CAPABILITY_UDMA; 1957 } 1958 pci_conf_write(sc->sc_pc, sc->sc_tag, old_udma_conf, APO_UDMA); 1959 1960 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1961 cp = &sc->pciide_channels[channel]; 1962 if (pciide_chansetup(sc, channel, interface) == 0) 1963 continue; 1964 1965 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1966 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1967 printf("%s: %s channel ignored (disabled)\n", 1968 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1969 continue; 1970 } 1971 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1972 pciide_pci_intr); 1973 if (cp->hw_ok == 0) 1974 continue; 1975 if (pciide_chan_candisable(cp)) { 1976 ideconf &= ~APO_IDECONF_EN(channel); 1977 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1978 ideconf); 1979 } 1980 pciide_map_compat_intr(pa, cp, channel, interface); 1981 1982 if (cp->hw_ok == 0) 1983 continue; 1984 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1985 } 1986 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1987 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1988 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1989 } 1990 1991 void 1992 apollo_setup_channel(chp) 1993 struct channel_softc *chp; 1994 { 1995 u_int32_t udmatim_reg, datatim_reg; 1996 u_int8_t idedma_ctl; 1997 int mode, drive; 1998 struct ata_drive_datas *drvp; 1999 struct pciide_channel *cp = (struct pciide_channel*)chp; 2000 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2001 2002 idedma_ctl = 0; 2003 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2004 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2005 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2006 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 2007 2008 /* setup DMA if needed */ 2009 pciide_channel_dma_setup(cp); 2010 2011 /* 2012 * We can't mix Ultra/33 and Ultra/66 on the same channel, so 2013 * downgrade to Ultra/33 if needed 2014 */ 2015 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 2016 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 2017 /* both drives UDMA */ 2018 if (chp->ch_drive[0].UDMA_mode > 2 && 2019 chp->ch_drive[1].UDMA_mode <= 2) { 2020 /* drive 0 Ultra/66, drive 1 Ultra/33 */ 2021 chp->ch_drive[0].UDMA_mode = 2; 2022 } else if (chp->ch_drive[1].UDMA_mode > 2 && 2023 chp->ch_drive[0].UDMA_mode <= 2) { 2024 /* drive 1 Ultra/66, drive 0 Ultra/33 */ 2025 chp->ch_drive[1].UDMA_mode = 2; 2026 } 2027 } 2028 2029 for (drive = 0; drive < 2; drive++) { 2030 drvp = &chp->ch_drive[drive]; 2031 /* If no drive, skip */ 2032 if ((drvp->drive_flags & DRIVE) == 0) 2033 continue; 2034 /* add timing values, setup DMA if needed */ 2035 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2036 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2037 mode = drvp->PIO_mode; 2038 goto pio; 2039 } 2040 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2041 (drvp->drive_flags & DRIVE_UDMA)) { 2042 /* use Ultra/DMA */ 2043 drvp->drive_flags &= ~DRIVE_DMA; 2044 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2045 APO_UDMA_EN_MTH(chp->channel, drive) | 2046 APO_UDMA_TIME(chp->channel, drive, 2047 apollo_udma_tim[drvp->UDMA_mode]); 2048 if (drvp->UDMA_mode > 2) 2049 udmatim_reg |= 2050 APO_UDMA_CLK66(chp->channel); 2051 /* can use PIO timings, MW DMA unused */ 2052 mode = drvp->PIO_mode; 2053 } else { 2054 /* use Multiword DMA */ 2055 drvp->drive_flags &= ~DRIVE_UDMA; 2056 /* mode = min(pio, dma+2) */ 2057 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2058 mode = drvp->PIO_mode; 2059 else 2060 mode = drvp->DMA_mode + 2; 2061 } 2062 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2063 2064 pio: /* setup PIO mode */ 2065 if (mode <= 2) { 2066 drvp->DMA_mode = 0; 2067 drvp->PIO_mode = 0; 2068 mode = 0; 2069 } else { 2070 drvp->PIO_mode = mode; 2071 drvp->DMA_mode = mode - 2; 2072 } 2073 datatim_reg |= 2074 APO_DATATIM_PULSE(chp->channel, drive, 2075 apollo_pio_set[mode]) | 2076 APO_DATATIM_RECOV(chp->channel, drive, 2077 apollo_pio_rec[mode]); 2078 } 2079 if (idedma_ctl != 0) { 2080 /* Add software bits in status register */ 2081 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2082 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2083 idedma_ctl); 2084 } 2085 pciide_print_modes(cp); 2086 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2087 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2088 } 2089 2090 void 2091 cmd_channel_map(pa, sc, channel) 2092 struct pci_attach_args *pa; 2093 struct pciide_softc *sc; 2094 int channel; 2095 { 2096 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2097 bus_size_t cmdsize, ctlsize; 2098 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2099 int interface; 2100 2101 /* 2102 * The 0648/0649 can be told to identify as a RAID controller. 2103 * In this case, we have to fake interface 2104 */ 2105 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2106 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2107 PCIIDE_INTERFACE_SETTABLE(1); 2108 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2109 CMD_CONF_DSA1) 2110 interface |= PCIIDE_INTERFACE_PCI(0) | 2111 PCIIDE_INTERFACE_PCI(1); 2112 } else { 2113 interface = PCI_INTERFACE(pa->pa_class); 2114 } 2115 2116 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2117 cp->name = PCIIDE_CHANNEL_NAME(channel); 2118 cp->wdc_channel.channel = channel; 2119 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2120 2121 if (channel > 0) { 2122 cp->wdc_channel.ch_queue = 2123 sc->pciide_channels[0].wdc_channel.ch_queue; 2124 } else { 2125 cp->wdc_channel.ch_queue = 2126 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2127 } 2128 if (cp->wdc_channel.ch_queue == NULL) { 2129 printf("%s %s channel: " 2130 "can't allocate memory for command queue", 2131 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2132 return; 2133 } 2134 2135 printf("%s: %s channel %s to %s mode\n", 2136 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2137 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2138 "configured" : "wired", 2139 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2140 "native-PCI" : "compatibility"); 2141 2142 /* 2143 * with a CMD PCI64x, if we get here, the first channel is enabled: 2144 * there's no way to disable the first channel without disabling 2145 * the whole device 2146 */ 2147 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2148 printf("%s: %s channel ignored (disabled)\n", 2149 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2150 return; 2151 } 2152 2153 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2154 if (cp->hw_ok == 0) 2155 return; 2156 if (channel == 1) { 2157 if (pciide_chan_candisable(cp)) { 2158 ctrl &= ~CMD_CTRL_2PORT; 2159 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2160 CMD_CTRL, ctrl); 2161 } 2162 } 2163 pciide_map_compat_intr(pa, cp, channel, interface); 2164 } 2165 2166 int 2167 cmd_pci_intr(arg) 2168 void *arg; 2169 { 2170 struct pciide_softc *sc = arg; 2171 struct pciide_channel *cp; 2172 struct channel_softc *wdc_cp; 2173 int i, rv, crv; 2174 u_int32_t priirq, secirq; 2175 2176 rv = 0; 2177 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2178 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2179 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2180 cp = &sc->pciide_channels[i]; 2181 wdc_cp = &cp->wdc_channel; 2182 /* If a compat channel skip. */ 2183 if (cp->compat) 2184 continue; 2185 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2186 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2187 crv = wdcintr(wdc_cp); 2188 if (crv == 0) 2189 printf("%s:%d: bogus intr\n", 2190 sc->sc_wdcdev.sc_dev.dv_xname, i); 2191 else 2192 rv = 1; 2193 } 2194 } 2195 return rv; 2196 } 2197 2198 void 2199 cmd_chip_map(sc, pa) 2200 struct pciide_softc *sc; 2201 struct pci_attach_args *pa; 2202 { 2203 int channel; 2204 2205 /* 2206 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2207 * and base adresses registers can be disabled at 2208 * hardware level. In this case, the device is wired 2209 * in compat mode and its first channel is always enabled, 2210 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2211 * In fact, it seems that the first channel of the CMD PCI0640 2212 * can't be disabled. 2213 */ 2214 2215 #ifdef PCIIDE_CMD064x_DISABLE 2216 if (pciide_chipen(sc, pa) == 0) 2217 return; 2218 #endif 2219 2220 printf("%s: hardware does not support DMA\n", 2221 sc->sc_wdcdev.sc_dev.dv_xname); 2222 sc->sc_dma_ok = 0; 2223 2224 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2225 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2226 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2227 2228 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2229 cmd_channel_map(pa, sc, channel); 2230 } 2231 } 2232 2233 void 2234 cmd0643_9_chip_map(sc, pa) 2235 struct pciide_softc *sc; 2236 struct pci_attach_args *pa; 2237 { 2238 struct pciide_channel *cp; 2239 int channel; 2240 int rev = PCI_REVISION( 2241 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2242 2243 /* 2244 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2245 * and base adresses registers can be disabled at 2246 * hardware level. In this case, the device is wired 2247 * in compat mode and its first channel is always enabled, 2248 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2249 * In fact, it seems that the first channel of the CMD PCI0640 2250 * can't be disabled. 2251 */ 2252 2253 #ifdef PCIIDE_CMD064x_DISABLE 2254 if (pciide_chipen(sc, pa) == 0) 2255 return; 2256 #endif 2257 printf("%s: bus-master DMA support present", 2258 sc->sc_wdcdev.sc_dev.dv_xname); 2259 pciide_mapreg_dma(sc, pa); 2260 printf("\n"); 2261 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2262 WDC_CAPABILITY_MODE; 2263 if (sc->sc_dma_ok) { 2264 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2265 switch (sc->sc_pp->ide_product) { 2266 case PCI_PRODUCT_CMDTECH_649: 2267 case PCI_PRODUCT_CMDTECH_648: 2268 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2269 sc->sc_wdcdev.UDMA_cap = 4; 2270 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2271 break; 2272 case PCI_PRODUCT_CMDTECH_646: 2273 if (rev >= CMD0646U2_REV) { 2274 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2275 sc->sc_wdcdev.UDMA_cap = 2; 2276 } else if (rev >= CMD0646U_REV) { 2277 /* 2278 * Linux's driver claims that the 646U is broken 2279 * with UDMA. Only enable it if we know what we're 2280 * doing 2281 */ 2282 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2283 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2284 sc->sc_wdcdev.UDMA_cap = 2; 2285 #endif 2286 /* explicitely disable UDMA */ 2287 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2288 CMD_UDMATIM(0), 0); 2289 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2290 CMD_UDMATIM(1), 0); 2291 } 2292 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2293 break; 2294 default: 2295 sc->sc_wdcdev.irqack = pciide_irqack; 2296 } 2297 } 2298 2299 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2300 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2301 sc->sc_wdcdev.PIO_cap = 4; 2302 sc->sc_wdcdev.DMA_cap = 2; 2303 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2304 2305 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2306 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2307 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2308 DEBUG_PROBE); 2309 2310 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2311 cp = &sc->pciide_channels[channel]; 2312 cmd_channel_map(pa, sc, channel); 2313 if (cp->hw_ok == 0) 2314 continue; 2315 cmd0643_9_setup_channel(&cp->wdc_channel); 2316 } 2317 /* 2318 * note - this also makes sure we clear the irq disable and reset 2319 * bits 2320 */ 2321 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2322 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2323 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2324 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2325 DEBUG_PROBE); 2326 } 2327 2328 void 2329 cmd0643_9_setup_channel(chp) 2330 struct channel_softc *chp; 2331 { 2332 struct ata_drive_datas *drvp; 2333 u_int8_t tim; 2334 u_int32_t idedma_ctl, udma_reg; 2335 int drive; 2336 struct pciide_channel *cp = (struct pciide_channel*)chp; 2337 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2338 2339 idedma_ctl = 0; 2340 /* setup DMA if needed */ 2341 pciide_channel_dma_setup(cp); 2342 2343 for (drive = 0; drive < 2; drive++) { 2344 drvp = &chp->ch_drive[drive]; 2345 /* If no drive, skip */ 2346 if ((drvp->drive_flags & DRIVE) == 0) 2347 continue; 2348 /* add timing values, setup DMA if needed */ 2349 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2350 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2351 if (drvp->drive_flags & DRIVE_UDMA) { 2352 /* UltraDMA on a 646U2, 0648 or 0649 */ 2353 drvp->drive_flags &= ~DRIVE_DMA; 2354 udma_reg = pciide_pci_read(sc->sc_pc, 2355 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2356 if (drvp->UDMA_mode > 2 && 2357 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2358 CMD_BICSR) & 2359 CMD_BICSR_80(chp->channel)) == 0) 2360 drvp->UDMA_mode = 2; 2361 if (drvp->UDMA_mode > 2) 2362 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2363 else if (sc->sc_wdcdev.UDMA_cap > 2) 2364 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2365 udma_reg |= CMD_UDMATIM_UDMA(drive); 2366 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2367 CMD_UDMATIM_TIM_OFF(drive)); 2368 udma_reg |= 2369 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2370 CMD_UDMATIM_TIM_OFF(drive)); 2371 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2372 CMD_UDMATIM(chp->channel), udma_reg); 2373 } else { 2374 /* 2375 * use Multiword DMA. 2376 * Timings will be used for both PIO and DMA, 2377 * so adjust DMA mode if needed 2378 * if we have a 0646U2/8/9, turn off UDMA 2379 */ 2380 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2381 udma_reg = pciide_pci_read(sc->sc_pc, 2382 sc->sc_tag, 2383 CMD_UDMATIM(chp->channel)); 2384 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2385 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2386 CMD_UDMATIM(chp->channel), 2387 udma_reg); 2388 } 2389 if (drvp->PIO_mode >= 3 && 2390 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2391 drvp->DMA_mode = drvp->PIO_mode - 2; 2392 } 2393 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2394 } 2395 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2396 } 2397 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2398 CMD_DATA_TIM(chp->channel, drive), tim); 2399 } 2400 if (idedma_ctl != 0) { 2401 /* Add software bits in status register */ 2402 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2403 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2404 idedma_ctl); 2405 } 2406 pciide_print_modes(cp); 2407 } 2408 2409 void 2410 cmd646_9_irqack(chp) 2411 struct channel_softc *chp; 2412 { 2413 u_int32_t priirq, secirq; 2414 struct pciide_channel *cp = (struct pciide_channel*)chp; 2415 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2416 2417 if (chp->channel == 0) { 2418 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2419 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2420 } else { 2421 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2422 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2423 } 2424 pciide_irqack(chp); 2425 } 2426 2427 void 2428 cy693_chip_map(sc, pa) 2429 struct pciide_softc *sc; 2430 struct pci_attach_args *pa; 2431 { 2432 struct pciide_channel *cp; 2433 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2434 bus_size_t cmdsize, ctlsize; 2435 2436 if (pciide_chipen(sc, pa) == 0) 2437 return; 2438 /* 2439 * this chip has 2 PCI IDE functions, one for primary and one for 2440 * secondary. So we need to call pciide_mapregs_compat() with 2441 * the real channel 2442 */ 2443 if (pa->pa_function == 1) { 2444 sc->sc_cy_compatchan = 0; 2445 } else if (pa->pa_function == 2) { 2446 sc->sc_cy_compatchan = 1; 2447 } else { 2448 printf("%s: unexpected PCI function %d\n", 2449 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2450 return; 2451 } 2452 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2453 printf("%s: bus-master DMA support present", 2454 sc->sc_wdcdev.sc_dev.dv_xname); 2455 pciide_mapreg_dma(sc, pa); 2456 } else { 2457 printf("%s: hardware does not support DMA", 2458 sc->sc_wdcdev.sc_dev.dv_xname); 2459 sc->sc_dma_ok = 0; 2460 } 2461 printf("\n"); 2462 2463 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2464 if (sc->sc_cy_handle == NULL) { 2465 printf("%s: unable to map hyperCache control registers\n", 2466 sc->sc_wdcdev.sc_dev.dv_xname); 2467 sc->sc_dma_ok = 0; 2468 } 2469 2470 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2471 WDC_CAPABILITY_MODE; 2472 if (sc->sc_dma_ok) { 2473 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2474 sc->sc_wdcdev.irqack = pciide_irqack; 2475 } 2476 sc->sc_wdcdev.PIO_cap = 4; 2477 sc->sc_wdcdev.DMA_cap = 2; 2478 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2479 2480 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2481 sc->sc_wdcdev.nchannels = 1; 2482 2483 /* Only one channel for this chip; if we are here it's enabled */ 2484 cp = &sc->pciide_channels[0]; 2485 sc->wdc_chanarray[0] = &cp->wdc_channel; 2486 cp->name = PCIIDE_CHANNEL_NAME(0); 2487 cp->wdc_channel.channel = 0; 2488 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2489 cp->wdc_channel.ch_queue = 2490 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2491 if (cp->wdc_channel.ch_queue == NULL) { 2492 printf("%s primary channel: " 2493 "can't allocate memory for command queue", 2494 sc->sc_wdcdev.sc_dev.dv_xname); 2495 return; 2496 } 2497 printf("%s: primary channel %s to ", 2498 sc->sc_wdcdev.sc_dev.dv_xname, 2499 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2500 "configured" : "wired"); 2501 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2502 printf("native-PCI"); 2503 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2504 pciide_pci_intr); 2505 } else { 2506 printf("compatibility"); 2507 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2508 &cmdsize, &ctlsize); 2509 } 2510 printf(" mode\n"); 2511 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2512 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2513 wdcattach(&cp->wdc_channel); 2514 if (pciide_chan_candisable(cp)) { 2515 pci_conf_write(sc->sc_pc, sc->sc_tag, 2516 PCI_COMMAND_STATUS_REG, 0); 2517 } 2518 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2519 if (cp->hw_ok == 0) 2520 return; 2521 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2522 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2523 cy693_setup_channel(&cp->wdc_channel); 2524 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2525 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2526 } 2527 2528 void 2529 cy693_setup_channel(chp) 2530 struct channel_softc *chp; 2531 { 2532 struct ata_drive_datas *drvp; 2533 int drive; 2534 u_int32_t cy_cmd_ctrl; 2535 u_int32_t idedma_ctl; 2536 struct pciide_channel *cp = (struct pciide_channel*)chp; 2537 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2538 int dma_mode = -1; 2539 2540 cy_cmd_ctrl = idedma_ctl = 0; 2541 2542 /* setup DMA if needed */ 2543 pciide_channel_dma_setup(cp); 2544 2545 for (drive = 0; drive < 2; drive++) { 2546 drvp = &chp->ch_drive[drive]; 2547 /* If no drive, skip */ 2548 if ((drvp->drive_flags & DRIVE) == 0) 2549 continue; 2550 /* add timing values, setup DMA if needed */ 2551 if (drvp->drive_flags & DRIVE_DMA) { 2552 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2553 /* use Multiword DMA */ 2554 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2555 dma_mode = drvp->DMA_mode; 2556 } 2557 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2558 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2559 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2560 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2561 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2562 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2563 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2564 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2565 } 2566 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2567 chp->ch_drive[0].DMA_mode = dma_mode; 2568 chp->ch_drive[1].DMA_mode = dma_mode; 2569 2570 if (dma_mode == -1) 2571 dma_mode = 0; 2572 2573 if (sc->sc_cy_handle != NULL) { 2574 /* Note: `multiple' is implied. */ 2575 cy82c693_write(sc->sc_cy_handle, 2576 (sc->sc_cy_compatchan == 0) ? 2577 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2578 } 2579 2580 pciide_print_modes(cp); 2581 2582 if (idedma_ctl != 0) { 2583 /* Add software bits in status register */ 2584 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2585 IDEDMA_CTL, idedma_ctl); 2586 } 2587 } 2588 2589 void 2590 sis_chip_map(sc, pa) 2591 struct pciide_softc *sc; 2592 struct pci_attach_args *pa; 2593 { 2594 struct pciide_channel *cp; 2595 int channel; 2596 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2597 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2598 pcireg_t rev = PCI_REVISION(pa->pa_class); 2599 bus_size_t cmdsize, ctlsize; 2600 2601 if (pciide_chipen(sc, pa) == 0) 2602 return; 2603 printf("%s: bus-master DMA support present", 2604 sc->sc_wdcdev.sc_dev.dv_xname); 2605 pciide_mapreg_dma(sc, pa); 2606 printf("\n"); 2607 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2608 WDC_CAPABILITY_MODE; 2609 if (sc->sc_dma_ok) { 2610 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2611 sc->sc_wdcdev.irqack = pciide_irqack; 2612 if (rev >= 0xd0) 2613 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2614 } 2615 2616 sc->sc_wdcdev.PIO_cap = 4; 2617 sc->sc_wdcdev.DMA_cap = 2; 2618 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2619 sc->sc_wdcdev.UDMA_cap = 2; 2620 sc->sc_wdcdev.set_modes = sis_setup_channel; 2621 2622 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2623 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2624 2625 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2626 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2627 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2628 2629 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2630 cp = &sc->pciide_channels[channel]; 2631 if (pciide_chansetup(sc, channel, interface) == 0) 2632 continue; 2633 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2634 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2635 printf("%s: %s channel ignored (disabled)\n", 2636 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2637 continue; 2638 } 2639 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2640 pciide_pci_intr); 2641 if (cp->hw_ok == 0) 2642 continue; 2643 if (pciide_chan_candisable(cp)) { 2644 if (channel == 0) 2645 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2646 else 2647 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2648 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2649 sis_ctr0); 2650 } 2651 pciide_map_compat_intr(pa, cp, channel, interface); 2652 if (cp->hw_ok == 0) 2653 continue; 2654 sis_setup_channel(&cp->wdc_channel); 2655 } 2656 } 2657 2658 void 2659 sis_setup_channel(chp) 2660 struct channel_softc *chp; 2661 { 2662 struct ata_drive_datas *drvp; 2663 int drive; 2664 u_int32_t sis_tim; 2665 u_int32_t idedma_ctl; 2666 struct pciide_channel *cp = (struct pciide_channel*)chp; 2667 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2668 2669 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2670 "channel %d 0x%x\n", chp->channel, 2671 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2672 DEBUG_PROBE); 2673 sis_tim = 0; 2674 idedma_ctl = 0; 2675 /* setup DMA if needed */ 2676 pciide_channel_dma_setup(cp); 2677 2678 for (drive = 0; drive < 2; drive++) { 2679 drvp = &chp->ch_drive[drive]; 2680 /* If no drive, skip */ 2681 if ((drvp->drive_flags & DRIVE) == 0) 2682 continue; 2683 /* add timing values, setup DMA if needed */ 2684 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2685 (drvp->drive_flags & DRIVE_UDMA) == 0) 2686 goto pio; 2687 2688 if (drvp->drive_flags & DRIVE_UDMA) { 2689 /* use Ultra/DMA */ 2690 drvp->drive_flags &= ~DRIVE_DMA; 2691 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2692 SIS_TIM_UDMA_TIME_OFF(drive); 2693 sis_tim |= SIS_TIM_UDMA_EN(drive); 2694 } else { 2695 /* 2696 * use Multiword DMA 2697 * Timings will be used for both PIO and DMA, 2698 * so adjust DMA mode if needed 2699 */ 2700 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2701 drvp->PIO_mode = drvp->DMA_mode + 2; 2702 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2703 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2704 drvp->PIO_mode - 2 : 0; 2705 if (drvp->DMA_mode == 0) 2706 drvp->PIO_mode = 0; 2707 } 2708 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2709 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2710 SIS_TIM_ACT_OFF(drive); 2711 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2712 SIS_TIM_REC_OFF(drive); 2713 } 2714 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2715 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2716 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2717 if (idedma_ctl != 0) { 2718 /* Add software bits in status register */ 2719 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2720 IDEDMA_CTL, idedma_ctl); 2721 } 2722 pciide_print_modes(cp); 2723 } 2724 2725 void 2726 acer_chip_map(sc, pa) 2727 struct pciide_softc *sc; 2728 struct pci_attach_args *pa; 2729 { 2730 struct pciide_channel *cp; 2731 int channel; 2732 pcireg_t cr, interface; 2733 bus_size_t cmdsize, ctlsize; 2734 2735 if (pciide_chipen(sc, pa) == 0) 2736 return; 2737 printf("%s: bus-master DMA support present", 2738 sc->sc_wdcdev.sc_dev.dv_xname); 2739 pciide_mapreg_dma(sc, pa); 2740 printf("\n"); 2741 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2742 WDC_CAPABILITY_MODE; 2743 if (sc->sc_dma_ok) { 2744 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2745 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2746 sc->sc_wdcdev.irqack = pciide_irqack; 2747 } 2748 2749 sc->sc_wdcdev.PIO_cap = 4; 2750 sc->sc_wdcdev.DMA_cap = 2; 2751 sc->sc_wdcdev.UDMA_cap = 2; 2752 sc->sc_wdcdev.set_modes = acer_setup_channel; 2753 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2754 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2755 2756 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2757 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2758 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2759 2760 /* Enable "microsoft register bits" R/W. */ 2761 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2762 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2763 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2764 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2765 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2766 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2767 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2768 ~ACER_CHANSTATUSREGS_RO); 2769 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2770 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2771 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2772 /* Don't use cr, re-read the real register content instead */ 2773 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2774 PCI_CLASS_REG)); 2775 2776 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2777 cp = &sc->pciide_channels[channel]; 2778 if (pciide_chansetup(sc, channel, interface) == 0) 2779 continue; 2780 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2781 printf("%s: %s channel ignored (disabled)\n", 2782 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2783 continue; 2784 } 2785 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2786 acer_pci_intr); 2787 if (cp->hw_ok == 0) 2788 continue; 2789 if (pciide_chan_candisable(cp)) { 2790 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2791 pci_conf_write(sc->sc_pc, sc->sc_tag, 2792 PCI_CLASS_REG, cr); 2793 } 2794 pciide_map_compat_intr(pa, cp, channel, interface); 2795 acer_setup_channel(&cp->wdc_channel); 2796 } 2797 } 2798 2799 void 2800 acer_setup_channel(chp) 2801 struct channel_softc *chp; 2802 { 2803 struct ata_drive_datas *drvp; 2804 int drive; 2805 u_int32_t acer_fifo_udma; 2806 u_int32_t idedma_ctl; 2807 struct pciide_channel *cp = (struct pciide_channel*)chp; 2808 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2809 2810 idedma_ctl = 0; 2811 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2812 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2813 acer_fifo_udma), DEBUG_PROBE); 2814 /* setup DMA if needed */ 2815 pciide_channel_dma_setup(cp); 2816 2817 for (drive = 0; drive < 2; drive++) { 2818 drvp = &chp->ch_drive[drive]; 2819 /* If no drive, skip */ 2820 if ((drvp->drive_flags & DRIVE) == 0) 2821 continue; 2822 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2823 "channel %d drive %d 0x%x\n", chp->channel, drive, 2824 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2825 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2826 /* clear FIFO/DMA mode */ 2827 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2828 ACER_UDMA_EN(chp->channel, drive) | 2829 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2830 2831 /* add timing values, setup DMA if needed */ 2832 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2833 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2834 acer_fifo_udma |= 2835 ACER_FTH_OPL(chp->channel, drive, 0x1); 2836 goto pio; 2837 } 2838 2839 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2840 if (drvp->drive_flags & DRIVE_UDMA) { 2841 /* use Ultra/DMA */ 2842 drvp->drive_flags &= ~DRIVE_DMA; 2843 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2844 acer_fifo_udma |= 2845 ACER_UDMA_TIM(chp->channel, drive, 2846 acer_udma[drvp->UDMA_mode]); 2847 } else { 2848 /* 2849 * use Multiword DMA 2850 * Timings will be used for both PIO and DMA, 2851 * so adjust DMA mode if needed 2852 */ 2853 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2854 drvp->PIO_mode = drvp->DMA_mode + 2; 2855 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2856 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2857 drvp->PIO_mode - 2 : 0; 2858 if (drvp->DMA_mode == 0) 2859 drvp->PIO_mode = 0; 2860 } 2861 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2862 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2863 ACER_IDETIM(chp->channel, drive), 2864 acer_pio[drvp->PIO_mode]); 2865 } 2866 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2867 acer_fifo_udma), DEBUG_PROBE); 2868 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2869 if (idedma_ctl != 0) { 2870 /* Add software bits in status register */ 2871 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2872 IDEDMA_CTL, idedma_ctl); 2873 } 2874 pciide_print_modes(cp); 2875 } 2876 2877 int 2878 acer_pci_intr(arg) 2879 void *arg; 2880 { 2881 struct pciide_softc *sc = arg; 2882 struct pciide_channel *cp; 2883 struct channel_softc *wdc_cp; 2884 int i, rv, crv; 2885 u_int32_t chids; 2886 2887 rv = 0; 2888 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2889 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2890 cp = &sc->pciide_channels[i]; 2891 wdc_cp = &cp->wdc_channel; 2892 /* If a compat channel skip. */ 2893 if (cp->compat) 2894 continue; 2895 if (chids & ACER_CHIDS_INT(i)) { 2896 crv = wdcintr(wdc_cp); 2897 if (crv == 0) 2898 printf("%s:%d: bogus intr\n", 2899 sc->sc_wdcdev.sc_dev.dv_xname, i); 2900 else 2901 rv = 1; 2902 } 2903 } 2904 return rv; 2905 } 2906 2907 void 2908 hpt_chip_map(sc, pa) 2909 struct pciide_softc *sc; 2910 struct pci_attach_args *pa; 2911 { 2912 struct pciide_channel *cp; 2913 int i, compatchan, revision; 2914 pcireg_t interface; 2915 bus_size_t cmdsize, ctlsize; 2916 2917 if (pciide_chipen(sc, pa) == 0) 2918 return; 2919 revision = PCI_REVISION(pa->pa_class); 2920 2921 /* 2922 * when the chip is in native mode it identifies itself as a 2923 * 'misc mass storage'. Fake interface in this case. 2924 */ 2925 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2926 interface = PCI_INTERFACE(pa->pa_class); 2927 } else { 2928 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2929 PCIIDE_INTERFACE_PCI(0); 2930 if (revision == HPT370_REV) 2931 interface |= PCIIDE_INTERFACE_PCI(1); 2932 } 2933 2934 printf("%s: bus-master DMA support present", 2935 sc->sc_wdcdev.sc_dev.dv_xname); 2936 pciide_mapreg_dma(sc, pa); 2937 printf("\n"); 2938 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2939 WDC_CAPABILITY_MODE; 2940 if (sc->sc_dma_ok) { 2941 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2942 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2943 sc->sc_wdcdev.irqack = pciide_irqack; 2944 } 2945 sc->sc_wdcdev.PIO_cap = 4; 2946 sc->sc_wdcdev.DMA_cap = 2; 2947 2948 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2949 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2950 if (revision == HPT366_REV) { 2951 sc->sc_wdcdev.UDMA_cap = 4; 2952 /* 2953 * The 366 has 2 PCI IDE functions, one for primary and one 2954 * for secondary. So we need to call pciide_mapregs_compat() 2955 * with the real channel 2956 */ 2957 if (pa->pa_function == 0) { 2958 compatchan = 0; 2959 } else if (pa->pa_function == 1) { 2960 compatchan = 1; 2961 } else { 2962 printf("%s: unexpected PCI function %d\n", 2963 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2964 return; 2965 } 2966 sc->sc_wdcdev.nchannels = 1; 2967 } else { 2968 sc->sc_wdcdev.nchannels = 2; 2969 sc->sc_wdcdev.UDMA_cap = 5; 2970 } 2971 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2972 cp = &sc->pciide_channels[i]; 2973 if (sc->sc_wdcdev.nchannels > 1) { 2974 compatchan = i; 2975 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2976 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2977 printf("%s: %s channel ignored (disabled)\n", 2978 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2979 continue; 2980 } 2981 } 2982 if (pciide_chansetup(sc, i, interface) == 0) 2983 continue; 2984 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2985 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2986 &ctlsize, hpt_pci_intr); 2987 } else { 2988 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2989 &cmdsize, &ctlsize); 2990 } 2991 if (cp->hw_ok == 0) 2992 return; 2993 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2994 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2995 wdcattach(&cp->wdc_channel); 2996 hpt_setup_channel(&cp->wdc_channel); 2997 } 2998 if (revision == HPT370_REV) { 2999 /* 3000 * HPT370_REV has a bit to disable interrupts, make sure 3001 * to clear it 3002 */ 3003 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3004 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3005 ~HPT_CSEL_IRQDIS); 3006 } 3007 return; 3008 } 3009 3010 void 3011 hpt_setup_channel(chp) 3012 struct channel_softc *chp; 3013 { 3014 struct ata_drive_datas *drvp; 3015 int drive; 3016 int cable; 3017 u_int32_t before, after; 3018 u_int32_t idedma_ctl; 3019 struct pciide_channel *cp = (struct pciide_channel*)chp; 3020 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3021 3022 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3023 3024 /* setup DMA if needed */ 3025 pciide_channel_dma_setup(cp); 3026 3027 idedma_ctl = 0; 3028 3029 /* Per drive settings */ 3030 for (drive = 0; drive < 2; drive++) { 3031 drvp = &chp->ch_drive[drive]; 3032 /* If no drive, skip */ 3033 if ((drvp->drive_flags & DRIVE) == 0) 3034 continue; 3035 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3036 HPT_IDETIM(chp->channel, drive)); 3037 3038 /* add timing values, setup DMA if needed */ 3039 if (drvp->drive_flags & DRIVE_UDMA) { 3040 /* use Ultra/DMA */ 3041 drvp->drive_flags &= ~DRIVE_DMA; 3042 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3043 drvp->UDMA_mode > 2) 3044 drvp->UDMA_mode = 2; 3045 after = (sc->sc_wdcdev.nchannels == 2) ? 3046 hpt370_udma[drvp->UDMA_mode] : 3047 hpt366_udma[drvp->UDMA_mode]; 3048 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3049 } else if (drvp->drive_flags & DRIVE_DMA) { 3050 /* 3051 * use Multiword DMA. 3052 * Timings will be used for both PIO and DMA, so adjust 3053 * DMA mode if needed 3054 */ 3055 if (drvp->PIO_mode >= 3 && 3056 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3057 drvp->DMA_mode = drvp->PIO_mode - 2; 3058 } 3059 after = (sc->sc_wdcdev.nchannels == 2) ? 3060 hpt370_dma[drvp->DMA_mode] : 3061 hpt366_dma[drvp->DMA_mode]; 3062 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3063 } else { 3064 /* PIO only */ 3065 after = (sc->sc_wdcdev.nchannels == 2) ? 3066 hpt370_pio[drvp->PIO_mode] : 3067 hpt366_pio[drvp->PIO_mode]; 3068 } 3069 pci_conf_write(sc->sc_pc, sc->sc_tag, 3070 HPT_IDETIM(chp->channel, drive), after); 3071 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3072 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3073 after, before), DEBUG_PROBE); 3074 } 3075 if (idedma_ctl != 0) { 3076 /* Add software bits in status register */ 3077 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3078 IDEDMA_CTL, idedma_ctl); 3079 } 3080 pciide_print_modes(cp); 3081 } 3082 3083 int 3084 hpt_pci_intr(arg) 3085 void *arg; 3086 { 3087 struct pciide_softc *sc = arg; 3088 struct pciide_channel *cp; 3089 struct channel_softc *wdc_cp; 3090 int rv = 0; 3091 int dmastat, i, crv; 3092 3093 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3094 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3095 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3096 if((dmastat & IDEDMA_CTL_INTR) == 0) 3097 continue; 3098 cp = &sc->pciide_channels[i]; 3099 wdc_cp = &cp->wdc_channel; 3100 crv = wdcintr(wdc_cp); 3101 if (crv == 0) { 3102 printf("%s:%d: bogus intr\n", 3103 sc->sc_wdcdev.sc_dev.dv_xname, i); 3104 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3105 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3106 } else 3107 rv = 1; 3108 } 3109 return rv; 3110 } 3111 3112 3113 /* A macro to test product */ 3114 #define PDC_IS_262(sc) \ 3115 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3116 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3117 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3118 3119 void 3120 pdc202xx_chip_map(sc, pa) 3121 struct pciide_softc *sc; 3122 struct pci_attach_args *pa; 3123 { 3124 struct pciide_channel *cp; 3125 int channel; 3126 pcireg_t interface, st, mode; 3127 bus_size_t cmdsize, ctlsize; 3128 3129 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3130 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3131 DEBUG_PROBE); 3132 if (pciide_chipen(sc, pa) == 0) 3133 return; 3134 3135 /* turn off RAID mode */ 3136 st &= ~PDC2xx_STATE_IDERAID; 3137 3138 /* 3139 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3140 * mode. We have to fake interface 3141 */ 3142 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3143 if (st & PDC2xx_STATE_NATIVE) 3144 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3145 3146 printf("%s: bus-master DMA support present", 3147 sc->sc_wdcdev.sc_dev.dv_xname); 3148 pciide_mapreg_dma(sc, pa); 3149 printf("\n"); 3150 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3151 WDC_CAPABILITY_MODE; 3152 if (sc->sc_dma_ok) { 3153 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3154 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3155 sc->sc_wdcdev.irqack = pciide_irqack; 3156 } 3157 sc->sc_wdcdev.PIO_cap = 4; 3158 sc->sc_wdcdev.DMA_cap = 2; 3159 if (PDC_IS_262(sc)) 3160 sc->sc_wdcdev.UDMA_cap = 4; 3161 else 3162 sc->sc_wdcdev.UDMA_cap = 2; 3163 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3164 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3165 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3166 3167 /* setup failsafe defaults */ 3168 mode = 0; 3169 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3170 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3171 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3172 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3173 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3174 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3175 "initial timings 0x%x, now 0x%x\n", channel, 3176 pci_conf_read(sc->sc_pc, sc->sc_tag, 3177 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3178 DEBUG_PROBE); 3179 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3180 mode | PDC2xx_TIM_IORDYp); 3181 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3182 "initial timings 0x%x, now 0x%x\n", channel, 3183 pci_conf_read(sc->sc_pc, sc->sc_tag, 3184 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3185 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3186 mode); 3187 } 3188 3189 mode = PDC2xx_SCR_DMA; 3190 if (PDC_IS_262(sc)) { 3191 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3192 } else { 3193 /* the BIOS set it up this way */ 3194 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3195 } 3196 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3197 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3198 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3199 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3200 DEBUG_PROBE); 3201 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3202 3203 /* controller initial state register is OK even without BIOS */ 3204 /* Set DMA mode to IDE DMA compatibility */ 3205 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3206 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3207 DEBUG_PROBE); 3208 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3209 mode | 0x1); 3210 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3211 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3212 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3213 mode | 0x1); 3214 3215 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3216 cp = &sc->pciide_channels[channel]; 3217 if (pciide_chansetup(sc, channel, interface) == 0) 3218 continue; 3219 if ((st & (PDC_IS_262(sc) ? 3220 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3221 printf("%s: %s channel ignored (disabled)\n", 3222 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3223 continue; 3224 } 3225 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3226 pdc202xx_pci_intr); 3227 if (cp->hw_ok == 0) 3228 continue; 3229 if (pciide_chan_candisable(cp)) 3230 st &= ~(PDC_IS_262(sc) ? 3231 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3232 pciide_map_compat_intr(pa, cp, channel, interface); 3233 pdc202xx_setup_channel(&cp->wdc_channel); 3234 } 3235 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3236 DEBUG_PROBE); 3237 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3238 return; 3239 } 3240 3241 void 3242 pdc202xx_setup_channel(chp) 3243 struct channel_softc *chp; 3244 { 3245 struct ata_drive_datas *drvp; 3246 int drive; 3247 pcireg_t mode, st; 3248 u_int32_t idedma_ctl, scr, atapi; 3249 struct pciide_channel *cp = (struct pciide_channel*)chp; 3250 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3251 int channel = chp->channel; 3252 3253 /* setup DMA if needed */ 3254 pciide_channel_dma_setup(cp); 3255 3256 idedma_ctl = 0; 3257 3258 /* Per channel settings */ 3259 if (PDC_IS_262(sc)) { 3260 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3261 PDC262_U66); 3262 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3263 /* Trimm UDMA mode */ 3264 if ((st & PDC262_STATE_80P(channel)) != 0 || 3265 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3266 chp->ch_drive[0].UDMA_mode <= 2) || 3267 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3268 chp->ch_drive[1].UDMA_mode <= 2)) { 3269 if (chp->ch_drive[0].UDMA_mode > 2) 3270 chp->ch_drive[0].UDMA_mode = 2; 3271 if (chp->ch_drive[1].UDMA_mode > 2) 3272 chp->ch_drive[1].UDMA_mode = 2; 3273 } 3274 /* Set U66 if needed */ 3275 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3276 chp->ch_drive[0].UDMA_mode > 2) || 3277 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3278 chp->ch_drive[1].UDMA_mode > 2)) 3279 scr |= PDC262_U66_EN(channel); 3280 else 3281 scr &= ~PDC262_U66_EN(channel); 3282 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3283 PDC262_U66, scr); 3284 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3285 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3286 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3287 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3288 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3289 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3290 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3291 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3292 atapi = 0; 3293 else 3294 atapi = PDC262_ATAPI_UDMA; 3295 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3296 PDC262_ATAPI(channel), atapi); 3297 } 3298 } 3299 for (drive = 0; drive < 2; drive++) { 3300 drvp = &chp->ch_drive[drive]; 3301 /* If no drive, skip */ 3302 if ((drvp->drive_flags & DRIVE) == 0) 3303 continue; 3304 mode = 0; 3305 if (drvp->drive_flags & DRIVE_UDMA) { 3306 /* use Ultra/DMA */ 3307 drvp->drive_flags &= ~DRIVE_DMA; 3308 mode = PDC2xx_TIM_SET_MB(mode, 3309 pdc2xx_udma_mb[drvp->UDMA_mode]); 3310 mode = PDC2xx_TIM_SET_MC(mode, 3311 pdc2xx_udma_mc[drvp->UDMA_mode]); 3312 drvp->drive_flags &= ~DRIVE_DMA; 3313 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3314 } else if (drvp->drive_flags & DRIVE_DMA) { 3315 mode = PDC2xx_TIM_SET_MB(mode, 3316 pdc2xx_dma_mb[drvp->DMA_mode]); 3317 mode = PDC2xx_TIM_SET_MC(mode, 3318 pdc2xx_dma_mc[drvp->DMA_mode]); 3319 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3320 } else { 3321 mode = PDC2xx_TIM_SET_MB(mode, 3322 pdc2xx_dma_mb[0]); 3323 mode = PDC2xx_TIM_SET_MC(mode, 3324 pdc2xx_dma_mc[0]); 3325 } 3326 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3327 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3328 if (drvp->drive_flags & DRIVE_ATA) 3329 mode |= PDC2xx_TIM_PRE; 3330 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3331 if (drvp->PIO_mode >= 3) { 3332 mode |= PDC2xx_TIM_IORDY; 3333 if (drive == 0) 3334 mode |= PDC2xx_TIM_IORDYp; 3335 } 3336 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3337 "timings 0x%x\n", 3338 sc->sc_wdcdev.sc_dev.dv_xname, 3339 chp->channel, drive, mode), DEBUG_PROBE); 3340 pci_conf_write(sc->sc_pc, sc->sc_tag, 3341 PDC2xx_TIM(chp->channel, drive), mode); 3342 } 3343 if (idedma_ctl != 0) { 3344 /* Add software bits in status register */ 3345 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3346 IDEDMA_CTL, idedma_ctl); 3347 } 3348 pciide_print_modes(cp); 3349 } 3350 3351 int 3352 pdc202xx_pci_intr(arg) 3353 void *arg; 3354 { 3355 struct pciide_softc *sc = arg; 3356 struct pciide_channel *cp; 3357 struct channel_softc *wdc_cp; 3358 int i, rv, crv; 3359 u_int32_t scr; 3360 3361 rv = 0; 3362 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3363 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3364 cp = &sc->pciide_channels[i]; 3365 wdc_cp = &cp->wdc_channel; 3366 /* If a compat channel skip. */ 3367 if (cp->compat) 3368 continue; 3369 if (scr & PDC2xx_SCR_INT(i)) { 3370 crv = wdcintr(wdc_cp); 3371 if (crv == 0) 3372 printf("%s:%d: bogus intr\n", 3373 sc->sc_wdcdev.sc_dev.dv_xname, i); 3374 else 3375 rv = 1; 3376 } 3377 } 3378 return rv; 3379 } 3380 3381 void 3382 opti_chip_map(sc, pa) 3383 struct pciide_softc *sc; 3384 struct pci_attach_args *pa; 3385 { 3386 struct pciide_channel *cp; 3387 bus_size_t cmdsize, ctlsize; 3388 pcireg_t interface; 3389 u_int8_t init_ctrl; 3390 int channel; 3391 3392 if (pciide_chipen(sc, pa) == 0) 3393 return; 3394 printf("%s: bus-master DMA support present", 3395 sc->sc_wdcdev.sc_dev.dv_xname); 3396 pciide_mapreg_dma(sc, pa); 3397 printf("\n"); 3398 3399 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3400 WDC_CAPABILITY_MODE; 3401 sc->sc_wdcdev.PIO_cap = 4; 3402 if (sc->sc_dma_ok) { 3403 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3404 sc->sc_wdcdev.irqack = pciide_irqack; 3405 sc->sc_wdcdev.DMA_cap = 2; 3406 } 3407 sc->sc_wdcdev.set_modes = opti_setup_channel; 3408 3409 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3410 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3411 3412 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3413 OPTI_REG_INIT_CONTROL); 3414 3415 interface = PCI_INTERFACE(pa->pa_class); 3416 3417 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3418 cp = &sc->pciide_channels[channel]; 3419 if (pciide_chansetup(sc, channel, interface) == 0) 3420 continue; 3421 if (channel == 1 && 3422 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3423 printf("%s: %s channel ignored (disabled)\n", 3424 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3425 continue; 3426 } 3427 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3428 pciide_pci_intr); 3429 if (cp->hw_ok == 0) 3430 continue; 3431 pciide_map_compat_intr(pa, cp, channel, interface); 3432 if (cp->hw_ok == 0) 3433 continue; 3434 opti_setup_channel(&cp->wdc_channel); 3435 } 3436 } 3437 3438 void 3439 opti_setup_channel(chp) 3440 struct channel_softc *chp; 3441 { 3442 struct ata_drive_datas *drvp; 3443 struct pciide_channel *cp = (struct pciide_channel*)chp; 3444 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3445 int drive, spd; 3446 int mode[2]; 3447 u_int8_t rv, mr; 3448 3449 /* 3450 * The `Delay' and `Address Setup Time' fields of the 3451 * Miscellaneous Register are always zero initially. 3452 */ 3453 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3454 mr &= ~(OPTI_MISC_DELAY_MASK | 3455 OPTI_MISC_ADDR_SETUP_MASK | 3456 OPTI_MISC_INDEX_MASK); 3457 3458 /* Prime the control register before setting timing values */ 3459 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3460 3461 /* Determine the clockrate of the PCIbus the chip is attached to */ 3462 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3463 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3464 3465 /* setup DMA if needed */ 3466 pciide_channel_dma_setup(cp); 3467 3468 for (drive = 0; drive < 2; drive++) { 3469 drvp = &chp->ch_drive[drive]; 3470 /* If no drive, skip */ 3471 if ((drvp->drive_flags & DRIVE) == 0) { 3472 mode[drive] = -1; 3473 continue; 3474 } 3475 3476 if ((drvp->drive_flags & DRIVE_DMA)) { 3477 /* 3478 * Timings will be used for both PIO and DMA, 3479 * so adjust DMA mode if needed 3480 */ 3481 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3482 drvp->PIO_mode = drvp->DMA_mode + 2; 3483 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3484 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3485 drvp->PIO_mode - 2 : 0; 3486 if (drvp->DMA_mode == 0) 3487 drvp->PIO_mode = 0; 3488 3489 mode[drive] = drvp->DMA_mode + 5; 3490 } else 3491 mode[drive] = drvp->PIO_mode; 3492 3493 if (drive && mode[0] >= 0 && 3494 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3495 /* 3496 * Can't have two drives using different values 3497 * for `Address Setup Time'. 3498 * Slow down the faster drive to compensate. 3499 */ 3500 int d = (opti_tim_as[spd][mode[0]] > 3501 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3502 3503 mode[d] = mode[1-d]; 3504 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3505 chp->ch_drive[d].DMA_mode = 0; 3506 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3507 } 3508 } 3509 3510 for (drive = 0; drive < 2; drive++) { 3511 int m; 3512 if ((m = mode[drive]) < 0) 3513 continue; 3514 3515 /* Set the Address Setup Time and select appropriate index */ 3516 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3517 rv |= OPTI_MISC_INDEX(drive); 3518 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3519 3520 /* Set the pulse width and recovery timing parameters */ 3521 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3522 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3523 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3524 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3525 3526 /* Set the Enhanced Mode register appropriately */ 3527 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3528 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3529 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3530 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3531 } 3532 3533 /* Finally, enable the timings */ 3534 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3535 3536 pciide_print_modes(cp); 3537 } 3538
Indexes created Thu Oct 02 14:10:14 GMT 2025