pciide.c revision 1.68.2.33
1 /* $NetBSD: pciide.c,v 1.68.2.33 2002/04/22 22:07:16 he Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <vm/vm.h> 102 #include <vm/vm_param.h> 103 #include <vm/vm_kern.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/pciide_acard_reg.h> 121 #include <dev/pci/cy82c693var.h> 122 123 #include "opt_pciide.h" 124 125 /* inlines for reading/writing 8-bit PCI registers */ 126 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 127 int)); 128 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 129 int, u_int8_t)); 130 131 static __inline u_int8_t 132 pciide_pci_read(pc, pa, reg) 133 pci_chipset_tag_t pc; 134 pcitag_t pa; 135 int reg; 136 { 137 138 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 139 ((reg & 0x03) * 8) & 0xff); 140 } 141 142 static __inline void 143 pciide_pci_write(pc, pa, reg, val) 144 pci_chipset_tag_t pc; 145 pcitag_t pa; 146 int reg; 147 u_int8_t val; 148 { 149 pcireg_t pcival; 150 151 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 152 pcival &= ~(0xff << ((reg & 0x03) * 8)); 153 pcival |= (val << ((reg & 0x03) * 8)); 154 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 155 } 156 157 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 158 159 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 160 void piix_setup_channel __P((struct channel_softc*)); 161 void piix3_4_setup_channel __P((struct channel_softc*)); 162 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 163 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 164 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 165 166 void amd7x6_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 167 void amd7x6_setup_channel __P((struct channel_softc*)); 168 169 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 170 void apollo_setup_channel __P((struct channel_softc*)); 171 172 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 173 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cmd0643_9_setup_channel __P((struct channel_softc*)); 175 void cmd_channel_map __P((struct pci_attach_args *, 176 struct pciide_softc *, int)); 177 int cmd_pci_intr __P((void *)); 178 void cmd646_9_irqack __P((struct channel_softc *)); 179 180 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void cy693_setup_channel __P((struct channel_softc*)); 182 183 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 184 void sis_setup_channel __P((struct channel_softc*)); 185 186 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 187 void acer_setup_channel __P((struct channel_softc*)); 188 int acer_pci_intr __P((void *)); 189 190 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 191 void pdc202xx_setup_channel __P((struct channel_softc*)); 192 int pdc202xx_pci_intr __P((void *)); 193 int pdc20265_pci_intr __P((void *)); 194 195 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 196 void opti_setup_channel __P((struct channel_softc*)); 197 198 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 199 void hpt_setup_channel __P((struct channel_softc*)); 200 int hpt_pci_intr __P((void *)); 201 202 void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 203 void acard_setup_channel __P((struct channel_softc*)); 204 int acard_pci_intr __P((void *)); 205 206 void pciide_channel_dma_setup __P((struct pciide_channel *)); 207 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 208 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 209 void pciide_dma_start __P((void*, int, int)); 210 int pciide_dma_finish __P((void*, int, int, int)); 211 void pciide_irqack __P((struct channel_softc *)); 212 void pciide_print_modes __P((struct pciide_channel *)); 213 214 struct pciide_product_desc { 215 u_int32_t ide_product; 216 int ide_flags; 217 const char *ide_name; 218 /* map and setup chip, probe drives */ 219 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 220 }; 221 222 /* Flags for ide_flags */ 223 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 224 225 /* Default product description for devices not known from this controller */ 226 const struct pciide_product_desc default_product_desc = { 227 0, 228 0, 229 "Generic PCI IDE controller", 230 default_chip_map, 231 }; 232 233 const struct pciide_product_desc pciide_intel_products[] = { 234 { PCI_PRODUCT_INTEL_82092AA, 235 0, 236 "Intel 82092AA IDE controller", 237 default_chip_map, 238 }, 239 { PCI_PRODUCT_INTEL_82371FB_IDE, 240 0, 241 "Intel 82371FB IDE controller (PIIX)", 242 piix_chip_map, 243 }, 244 { PCI_PRODUCT_INTEL_82371SB_IDE, 245 0, 246 "Intel 82371SB IDE Interface (PIIX3)", 247 piix_chip_map, 248 }, 249 { PCI_PRODUCT_INTEL_82371AB_IDE, 250 0, 251 "Intel 82371AB IDE controller (PIIX4)", 252 piix_chip_map, 253 }, 254 { PCI_PRODUCT_INTEL_82801AA_IDE, 255 0, 256 "Intel 82801AA IDE Controller (ICH)", 257 piix_chip_map, 258 }, 259 { PCI_PRODUCT_INTEL_82801AB_IDE, 260 0, 261 "Intel 82801AB IDE Controller (ICH0)", 262 piix_chip_map, 263 }, 264 { PCI_PRODUCT_INTEL_82801BA_IDE, 265 0, 266 "Intel 82801BA IDE Controller (ICH2)", 267 piix_chip_map, 268 }, 269 { PCI_PRODUCT_INTEL_82801BAM_IDE, 270 0, 271 "Intel 82801BAM IDE Controller (ICH2)", 272 piix_chip_map, 273 }, 274 { 0, 275 0, 276 NULL, 277 NULL 278 } 279 }; 280 281 const struct pciide_product_desc pciide_amd_products[] = { 282 { PCI_PRODUCT_AMD_PBC756_IDE, 283 0, 284 "Advanced Micro Devices AMD756 IDE Controller", 285 amd7x6_chip_map 286 }, 287 { PCI_PRODUCT_AMD_PBC766_IDE, 288 0, 289 "Advanced Micro Devices AMD766 IDE Controller", 290 amd7x6_chip_map 291 }, 292 { PCI_PRODUCT_AMD_PBC768_IDE, 293 0, 294 "Advanced Micro Devices AMD768 IDE Controller", 295 amd7x6_chip_map 296 }, 297 { 0, 298 0, 299 NULL, 300 NULL 301 } 302 }; 303 304 const struct pciide_product_desc pciide_cmd_products[] = { 305 { PCI_PRODUCT_CMDTECH_640, 306 0, 307 "CMD Technology PCI0640", 308 cmd_chip_map 309 }, 310 { PCI_PRODUCT_CMDTECH_643, 311 0, 312 "CMD Technology PCI0643", 313 cmd0643_9_chip_map, 314 }, 315 { PCI_PRODUCT_CMDTECH_646, 316 0, 317 "CMD Technology PCI0646", 318 cmd0643_9_chip_map, 319 }, 320 { PCI_PRODUCT_CMDTECH_648, 321 IDE_PCI_CLASS_OVERRIDE, 322 "CMD Technology PCI0648", 323 cmd0643_9_chip_map, 324 }, 325 { PCI_PRODUCT_CMDTECH_649, 326 IDE_PCI_CLASS_OVERRIDE, 327 "CMD Technology PCI0649", 328 cmd0643_9_chip_map, 329 }, 330 { 0, 331 0, 332 NULL, 333 NULL 334 } 335 }; 336 337 const struct pciide_product_desc pciide_via_products[] = { 338 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 339 0, 340 NULL, 341 apollo_chip_map, 342 }, 343 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 344 0, 345 NULL, 346 apollo_chip_map, 347 }, 348 { 0, 349 0, 350 NULL, 351 NULL 352 } 353 }; 354 355 const struct pciide_product_desc pciide_cypress_products[] = { 356 { PCI_PRODUCT_CONTAQ_82C693, 357 0, 358 "Cypress 82C693 IDE Controller", 359 cy693_chip_map, 360 }, 361 { 0, 362 0, 363 NULL, 364 NULL 365 } 366 }; 367 368 const struct pciide_product_desc pciide_sis_products[] = { 369 { PCI_PRODUCT_SIS_5597_IDE, 370 0, 371 "Silicon Integrated System 5597/5598 IDE controller", 372 sis_chip_map, 373 }, 374 { 0, 375 0, 376 NULL, 377 NULL 378 } 379 }; 380 381 const struct pciide_product_desc pciide_acer_products[] = { 382 { PCI_PRODUCT_ALI_M5229, 383 0, 384 "Acer Labs M5229 UDMA IDE Controller", 385 acer_chip_map, 386 }, 387 { 0, 388 0, 389 NULL, 390 NULL 391 } 392 }; 393 394 const struct pciide_product_desc pciide_promise_products[] = { 395 { PCI_PRODUCT_PROMISE_ULTRA33, 396 IDE_PCI_CLASS_OVERRIDE, 397 "Promise Ultra33/ATA Bus Master IDE Accelerator", 398 pdc202xx_chip_map, 399 }, 400 { PCI_PRODUCT_PROMISE_ULTRA66, 401 IDE_PCI_CLASS_OVERRIDE, 402 "Promise Ultra66/ATA Bus Master IDE Accelerator", 403 pdc202xx_chip_map, 404 }, 405 { PCI_PRODUCT_PROMISE_ULTRA100, 406 IDE_PCI_CLASS_OVERRIDE, 407 "Promise Ultra100/ATA Bus Master IDE Accelerator", 408 pdc202xx_chip_map, 409 }, 410 { PCI_PRODUCT_PROMISE_ULTRA100X, 411 IDE_PCI_CLASS_OVERRIDE, 412 "Promise Ultra100/ATA Bus Master IDE Accelerator", 413 pdc202xx_chip_map, 414 }, 415 { 0, 416 0, 417 NULL, 418 NULL 419 } 420 }; 421 422 const struct pciide_product_desc pciide_opti_products[] = { 423 { PCI_PRODUCT_OPTI_82C621, 424 0, 425 "OPTi 82c621 PCI IDE controller", 426 opti_chip_map, 427 }, 428 { PCI_PRODUCT_OPTI_82C568, 429 0, 430 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 431 opti_chip_map, 432 }, 433 { PCI_PRODUCT_OPTI_82D568, 434 0, 435 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 436 opti_chip_map, 437 }, 438 { 0, 439 0, 440 NULL, 441 NULL 442 } 443 }; 444 445 const struct pciide_product_desc pciide_triones_products[] = { 446 { PCI_PRODUCT_TRIONES_HPT366, 447 IDE_PCI_CLASS_OVERRIDE, 448 NULL, 449 hpt_chip_map, 450 }, 451 { 0, 452 0, 453 NULL, 454 NULL 455 } 456 }; 457 458 const struct pciide_product_desc pciide_acard_products[] = { 459 { PCI_PRODUCT_ACARD_ATP850U, 460 IDE_PCI_CLASS_OVERRIDE, 461 "Acard ATP850U Ultra33 IDE Controller", 462 acard_chip_map, 463 }, 464 { PCI_PRODUCT_ACARD_ATP860, 465 IDE_PCI_CLASS_OVERRIDE, 466 "Acard ATP860 Ultra66 IDE Controller", 467 acard_chip_map, 468 }, 469 { PCI_PRODUCT_ACARD_ATP860A, 470 IDE_PCI_CLASS_OVERRIDE, 471 "Acard ATP860-A Ultra66 IDE Controller", 472 acard_chip_map, 473 }, 474 { 0, 475 0, 476 NULL, 477 } 478 }; 479 480 struct pciide_vendor_desc { 481 u_int32_t ide_vendor; 482 const struct pciide_product_desc *ide_products; 483 }; 484 485 const struct pciide_vendor_desc pciide_vendors[] = { 486 { PCI_VENDOR_INTEL, pciide_intel_products }, 487 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 488 { PCI_VENDOR_VIATECH, pciide_via_products }, 489 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 490 { PCI_VENDOR_SIS, pciide_sis_products }, 491 { PCI_VENDOR_ALI, pciide_acer_products }, 492 { PCI_VENDOR_PROMISE, pciide_promise_products }, 493 { PCI_VENDOR_AMD, pciide_amd_products }, 494 { PCI_VENDOR_OPTI, pciide_opti_products }, 495 { PCI_VENDOR_TRIONES, pciide_triones_products }, 496 { PCI_VENDOR_ACARD, pciide_acard_products }, 497 { 0, NULL } 498 }; 499 500 /* options passed via the 'flags' config keyword */ 501 #define PCIIDE_OPTIONS_DMA 0x01 502 503 int pciide_match __P((struct device *, struct cfdata *, void *)); 504 void pciide_attach __P((struct device *, struct device *, void *)); 505 506 struct cfattach pciide_ca = { 507 sizeof(struct pciide_softc), pciide_match, pciide_attach 508 }; 509 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 510 int pciide_mapregs_compat __P(( struct pci_attach_args *, 511 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 512 int pciide_mapregs_native __P((struct pci_attach_args *, 513 struct pciide_channel *, bus_size_t *, bus_size_t *, 514 int (*pci_intr) __P((void *)))); 515 void pciide_mapreg_dma __P((struct pciide_softc *, 516 struct pci_attach_args *)); 517 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 518 void pciide_mapchan __P((struct pci_attach_args *, 519 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 520 int (*pci_intr) __P((void *)))); 521 int pciide_chan_candisable __P((struct pciide_channel *)); 522 void pciide_map_compat_intr __P(( struct pci_attach_args *, 523 struct pciide_channel *, int, int)); 524 int pciide_print __P((void *, const char *pnp)); 525 int pciide_compat_intr __P((void *)); 526 int pciide_pci_intr __P((void *)); 527 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 528 529 const struct pciide_product_desc * 530 pciide_lookup_product(id) 531 u_int32_t id; 532 { 533 const struct pciide_product_desc *pp; 534 const struct pciide_vendor_desc *vp; 535 536 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 537 if (PCI_VENDOR(id) == vp->ide_vendor) 538 break; 539 540 if ((pp = vp->ide_products) == NULL) 541 return NULL; 542 543 for (; pp->chip_map != NULL; pp++) 544 if (PCI_PRODUCT(id) == pp->ide_product) 545 break; 546 547 if (pp->chip_map == NULL) 548 return NULL; 549 return pp; 550 } 551 552 int 553 pciide_match(parent, match, aux) 554 struct device *parent; 555 struct cfdata *match; 556 void *aux; 557 { 558 struct pci_attach_args *pa = aux; 559 const struct pciide_product_desc *pp; 560 561 /* 562 * Check the ID register to see that it's a PCI IDE controller. 563 * If it is, we assume that we can deal with it; it _should_ 564 * work in a standardized way... 565 */ 566 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 567 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 568 return (1); 569 } 570 571 /* 572 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 573 * controllers. Let see if we can deal with it anyway. 574 */ 575 pp = pciide_lookup_product(pa->pa_id); 576 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 577 return (1); 578 } 579 580 return (0); 581 } 582 583 void 584 pciide_attach(parent, self, aux) 585 struct device *parent, *self; 586 void *aux; 587 { 588 struct pci_attach_args *pa = aux; 589 pci_chipset_tag_t pc = pa->pa_pc; 590 pcitag_t tag = pa->pa_tag; 591 struct pciide_softc *sc = (struct pciide_softc *)self; 592 pcireg_t csr; 593 char devinfo[256]; 594 const char *displaydev; 595 596 sc->sc_pp = pciide_lookup_product(pa->pa_id); 597 if (sc->sc_pp == NULL) { 598 sc->sc_pp = &default_product_desc; 599 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 600 displaydev = devinfo; 601 } else 602 displaydev = sc->sc_pp->ide_name; 603 604 /* if displaydev == NULL, printf is done in chip-specific map */ 605 if (displaydev) 606 printf(": %s (rev. 0x%02x)\n", displaydev, 607 PCI_REVISION(pa->pa_class)); 608 609 sc->sc_pc = pa->pa_pc; 610 sc->sc_tag = pa->pa_tag; 611 #ifdef WDCDEBUG 612 if (wdcdebug_pciide_mask & DEBUG_PROBE) 613 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 614 #endif 615 sc->sc_pp->chip_map(sc, pa); 616 617 if (sc->sc_dma_ok) { 618 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 619 csr |= PCI_COMMAND_MASTER_ENABLE; 620 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 621 } 622 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 623 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 624 } 625 626 /* tell wether the chip is enabled or not */ 627 int 628 pciide_chipen(sc, pa) 629 struct pciide_softc *sc; 630 struct pci_attach_args *pa; 631 { 632 pcireg_t csr; 633 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 634 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 635 PCI_COMMAND_STATUS_REG); 636 printf("%s: device disabled (at %s)\n", 637 sc->sc_wdcdev.sc_dev.dv_xname, 638 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 639 "device" : "bridge"); 640 return 0; 641 } 642 return 1; 643 } 644 645 int 646 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 647 struct pci_attach_args *pa; 648 struct pciide_channel *cp; 649 int compatchan; 650 bus_size_t *cmdsizep, *ctlsizep; 651 { 652 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 653 struct channel_softc *wdc_cp = &cp->wdc_channel; 654 655 cp->compat = 1; 656 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 657 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 658 659 wdc_cp->cmd_iot = pa->pa_iot; 660 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 661 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 662 printf("%s: couldn't map %s channel cmd regs\n", 663 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 664 return (0); 665 } 666 667 wdc_cp->ctl_iot = pa->pa_iot; 668 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 669 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 670 printf("%s: couldn't map %s channel ctl regs\n", 671 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 672 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 673 PCIIDE_COMPAT_CMD_SIZE); 674 return (0); 675 } 676 677 return (1); 678 } 679 680 int 681 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 682 struct pci_attach_args * pa; 683 struct pciide_channel *cp; 684 bus_size_t *cmdsizep, *ctlsizep; 685 int (*pci_intr) __P((void *)); 686 { 687 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 688 struct channel_softc *wdc_cp = &cp->wdc_channel; 689 const char *intrstr; 690 pci_intr_handle_t intrhandle; 691 692 cp->compat = 0; 693 694 if (sc->sc_pci_ih == NULL) { 695 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 696 pa->pa_intrline, &intrhandle) != 0) { 697 printf("%s: couldn't map native-PCI interrupt\n", 698 sc->sc_wdcdev.sc_dev.dv_xname); 699 return 0; 700 } 701 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 702 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 703 intrhandle, IPL_BIO, pci_intr, sc); 704 if (sc->sc_pci_ih != NULL) { 705 printf("%s: using %s for native-PCI interrupt\n", 706 sc->sc_wdcdev.sc_dev.dv_xname, 707 intrstr ? intrstr : "unknown interrupt"); 708 } else { 709 printf("%s: couldn't establish native-PCI interrupt", 710 sc->sc_wdcdev.sc_dev.dv_xname); 711 if (intrstr != NULL) 712 printf(" at %s", intrstr); 713 printf("\n"); 714 return 0; 715 } 716 } 717 cp->ih = sc->sc_pci_ih; 718 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 719 PCI_MAPREG_TYPE_IO, 0, 720 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 721 printf("%s: couldn't map %s channel cmd regs\n", 722 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 723 return 0; 724 } 725 726 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 727 PCI_MAPREG_TYPE_IO, 0, 728 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 729 printf("%s: couldn't map %s channel ctl regs\n", 730 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 731 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 732 return 0; 733 } 734 /* 735 * In native mode, 4 bytes of I/O space are mapped for the control 736 * register, the control register is at offset 2. Pass the generic 737 * code a handle for only one byte at the rigth offset. 738 */ 739 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 740 &wdc_cp->ctl_ioh) != 0) { 741 printf("%s: unable to subregion %s channel ctl regs\n", 742 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 743 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 744 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 745 return 0; 746 } 747 return (1); 748 } 749 750 void 751 pciide_mapreg_dma(sc, pa) 752 struct pciide_softc *sc; 753 struct pci_attach_args *pa; 754 { 755 pcireg_t maptype; 756 757 /* 758 * Map DMA registers 759 * 760 * Note that sc_dma_ok is the right variable to test to see if 761 * DMA can be done. If the interface doesn't support DMA, 762 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 763 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 764 * non-zero if the interface supports DMA and the registers 765 * could be mapped. 766 * 767 * XXX Note that despite the fact that the Bus Master IDE specs 768 * XXX say that "The bus master IDE function uses 16 bytes of IO 769 * XXX space," some controllers (at least the United 770 * XXX Microelectronics UM8886BF) place it in memory space. 771 */ 772 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 773 PCIIDE_REG_BUS_MASTER_DMA); 774 775 switch (maptype) { 776 case PCI_MAPREG_TYPE_IO: 777 case PCI_MAPREG_MEM_TYPE_32BIT: 778 sc->sc_dma_ok = (pci_mapreg_map(pa, 779 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 780 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 781 sc->sc_dmat = pa->pa_dmat; 782 if (sc->sc_dma_ok == 0) { 783 printf(", but unused (couldn't map registers)"); 784 } else { 785 sc->sc_wdcdev.dma_arg = sc; 786 sc->sc_wdcdev.dma_init = pciide_dma_init; 787 sc->sc_wdcdev.dma_start = pciide_dma_start; 788 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 789 } 790 break; 791 792 default: 793 sc->sc_dma_ok = 0; 794 printf(", but unsupported register maptype (0x%x)", maptype); 795 } 796 } 797 798 int 799 pciide_compat_intr(arg) 800 void *arg; 801 { 802 struct pciide_channel *cp = arg; 803 804 #ifdef DIAGNOSTIC 805 /* should only be called for a compat channel */ 806 if (cp->compat == 0) 807 panic("pciide compat intr called for non-compat chan %p\n", cp); 808 #endif 809 return (wdcintr(&cp->wdc_channel)); 810 } 811 812 int 813 pciide_pci_intr(arg) 814 void *arg; 815 { 816 struct pciide_softc *sc = arg; 817 struct pciide_channel *cp; 818 struct channel_softc *wdc_cp; 819 int i, rv, crv; 820 821 rv = 0; 822 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 823 cp = &sc->pciide_channels[i]; 824 wdc_cp = &cp->wdc_channel; 825 826 /* If a compat channel skip. */ 827 if (cp->compat) 828 continue; 829 /* if this channel not waiting for intr, skip */ 830 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 831 continue; 832 833 crv = wdcintr(wdc_cp); 834 if (crv == 0) 835 ; /* leave rv alone */ 836 else if (crv == 1) 837 rv = 1; /* claim the intr */ 838 else if (rv == 0) /* crv should be -1 in this case */ 839 rv = crv; /* if we've done no better, take it */ 840 } 841 return (rv); 842 } 843 844 void 845 pciide_channel_dma_setup(cp) 846 struct pciide_channel *cp; 847 { 848 int drive; 849 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 850 struct ata_drive_datas *drvp; 851 852 for (drive = 0; drive < 2; drive++) { 853 drvp = &cp->wdc_channel.ch_drive[drive]; 854 /* If no drive, skip */ 855 if ((drvp->drive_flags & DRIVE) == 0) 856 continue; 857 /* setup DMA if needed */ 858 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 859 (drvp->drive_flags & DRIVE_UDMA) == 0) || 860 sc->sc_dma_ok == 0) { 861 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 862 continue; 863 } 864 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 865 != 0) { 866 /* Abort DMA setup */ 867 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 868 continue; 869 } 870 } 871 } 872 873 int 874 pciide_dma_table_setup(sc, channel, drive) 875 struct pciide_softc *sc; 876 int channel, drive; 877 { 878 bus_dma_segment_t seg; 879 int error, rseg; 880 const bus_size_t dma_table_size = 881 sizeof(struct idedma_table) * NIDEDMA_TABLES; 882 struct pciide_dma_maps *dma_maps = 883 &sc->pciide_channels[channel].dma_maps[drive]; 884 885 /* If table was already allocated, just return */ 886 if (dma_maps->dma_table) 887 return 0; 888 889 /* Allocate memory for the DMA tables and map it */ 890 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 891 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 892 BUS_DMA_NOWAIT)) != 0) { 893 printf("%s:%d: unable to allocate table DMA for " 894 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 895 channel, drive, error); 896 return error; 897 } 898 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 899 dma_table_size, 900 (caddr_t *)&dma_maps->dma_table, 901 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 902 printf("%s:%d: unable to map table DMA for" 903 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 904 channel, drive, error); 905 return error; 906 } 907 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 908 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 909 seg.ds_addr), DEBUG_PROBE); 910 911 /* Create and load table DMA map for this disk */ 912 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 913 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 914 &dma_maps->dmamap_table)) != 0) { 915 printf("%s:%d: unable to create table DMA map for " 916 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 917 channel, drive, error); 918 return error; 919 } 920 if ((error = bus_dmamap_load(sc->sc_dmat, 921 dma_maps->dmamap_table, 922 dma_maps->dma_table, 923 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 924 printf("%s:%d: unable to load table DMA map for " 925 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 926 channel, drive, error); 927 return error; 928 } 929 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 930 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 931 /* Create a xfer DMA map for this drive */ 932 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 933 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 934 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 935 &dma_maps->dmamap_xfer)) != 0) { 936 printf("%s:%d: unable to create xfer DMA map for " 937 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 938 channel, drive, error); 939 return error; 940 } 941 return 0; 942 } 943 944 int 945 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 946 void *v; 947 int channel, drive; 948 void *databuf; 949 size_t datalen; 950 int flags; 951 { 952 struct pciide_softc *sc = v; 953 int error, seg; 954 struct pciide_dma_maps *dma_maps = 955 &sc->pciide_channels[channel].dma_maps[drive]; 956 957 error = bus_dmamap_load(sc->sc_dmat, 958 dma_maps->dmamap_xfer, 959 databuf, datalen, NULL, BUS_DMA_NOWAIT); 960 if (error) { 961 printf("%s:%d: unable to load xfer DMA map for" 962 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 963 channel, drive, error); 964 return error; 965 } 966 967 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 968 dma_maps->dmamap_xfer->dm_mapsize, 969 (flags & WDC_DMA_READ) ? 970 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 971 972 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 973 #ifdef DIAGNOSTIC 974 /* A segment must not cross a 64k boundary */ 975 { 976 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 977 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 978 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 979 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 980 printf("pciide_dma: segment %d physical addr 0x%lx" 981 " len 0x%lx not properly aligned\n", 982 seg, phys, len); 983 panic("pciide_dma: buf align"); 984 } 985 } 986 #endif 987 dma_maps->dma_table[seg].base_addr = 988 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 989 dma_maps->dma_table[seg].byte_count = 990 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 991 IDEDMA_BYTE_COUNT_MASK); 992 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 993 seg, le32toh(dma_maps->dma_table[seg].byte_count), 994 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 995 996 } 997 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 998 htole32(IDEDMA_BYTE_COUNT_EOT); 999 1000 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 1001 dma_maps->dmamap_table->dm_mapsize, 1002 BUS_DMASYNC_PREWRITE); 1003 1004 /* Maps are ready. Start DMA function */ 1005 #ifdef DIAGNOSTIC 1006 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 1007 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 1008 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1009 panic("pciide_dma_init: table align"); 1010 } 1011 #endif 1012 1013 /* Clear status bits */ 1014 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1015 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 1016 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1017 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 1018 /* Write table addr */ 1019 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 1020 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 1021 dma_maps->dmamap_table->dm_segs[0].ds_addr); 1022 /* set read/write */ 1023 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1024 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1025 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 1026 /* remember flags */ 1027 dma_maps->dma_flags = flags; 1028 return 0; 1029 } 1030 1031 void 1032 pciide_dma_start(v, channel, drive) 1033 void *v; 1034 int channel, drive; 1035 { 1036 struct pciide_softc *sc = v; 1037 1038 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 1039 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1040 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1041 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1042 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 1043 } 1044 1045 int 1046 pciide_dma_finish(v, channel, drive, force) 1047 void *v; 1048 int channel, drive; 1049 int force; 1050 { 1051 struct pciide_softc *sc = v; 1052 u_int8_t status; 1053 int error = 0; 1054 struct pciide_dma_maps *dma_maps = 1055 &sc->pciide_channels[channel].dma_maps[drive]; 1056 1057 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1058 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1059 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1060 DEBUG_XFERS); 1061 1062 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1063 return WDC_DMAST_NOIRQ; 1064 1065 /* stop DMA channel */ 1066 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1067 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1068 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1069 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1070 1071 /* Unload the map of the data buffer */ 1072 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1073 dma_maps->dmamap_xfer->dm_mapsize, 1074 (dma_maps->dma_flags & WDC_DMA_READ) ? 1075 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1076 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1077 1078 if ((status & IDEDMA_CTL_ERR) != 0) { 1079 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1080 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1081 error |= WDC_DMAST_ERR; 1082 } 1083 1084 if ((status & IDEDMA_CTL_INTR) == 0) { 1085 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1086 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1087 drive, status); 1088 error |= WDC_DMAST_NOIRQ; 1089 } 1090 1091 if ((status & IDEDMA_CTL_ACT) != 0) { 1092 /* data underrun, may be a valid condition for ATAPI */ 1093 error |= WDC_DMAST_UNDER; 1094 } 1095 return error; 1096 } 1097 1098 void 1099 pciide_irqack(chp) 1100 struct channel_softc *chp; 1101 { 1102 struct pciide_channel *cp = (struct pciide_channel*)chp; 1103 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1104 1105 /* clear status bits in IDE DMA registers */ 1106 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1107 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1108 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1109 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1110 } 1111 1112 /* some common code used by several chip_map */ 1113 int 1114 pciide_chansetup(sc, channel, interface) 1115 struct pciide_softc *sc; 1116 int channel; 1117 pcireg_t interface; 1118 { 1119 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1120 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1121 cp->name = PCIIDE_CHANNEL_NAME(channel); 1122 cp->wdc_channel.channel = channel; 1123 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1124 cp->wdc_channel.ch_queue = 1125 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1126 if (cp->wdc_channel.ch_queue == NULL) { 1127 printf("%s %s channel: " 1128 "can't allocate memory for command queue", 1129 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1130 return 0; 1131 } 1132 printf("%s: %s channel %s to %s mode\n", 1133 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1134 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1135 "configured" : "wired", 1136 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1137 "native-PCI" : "compatibility"); 1138 return 1; 1139 } 1140 1141 /* some common code used by several chip channel_map */ 1142 void 1143 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1144 struct pci_attach_args *pa; 1145 struct pciide_channel *cp; 1146 pcireg_t interface; 1147 bus_size_t *cmdsizep, *ctlsizep; 1148 int (*pci_intr) __P((void *)); 1149 { 1150 struct channel_softc *wdc_cp = &cp->wdc_channel; 1151 1152 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1153 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1154 pci_intr); 1155 else 1156 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1157 wdc_cp->channel, cmdsizep, ctlsizep); 1158 1159 if (cp->hw_ok == 0) 1160 return; 1161 wdc_cp->data32iot = wdc_cp->cmd_iot; 1162 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1163 wdcattach(wdc_cp); 1164 } 1165 1166 /* 1167 * Generic code to call to know if a channel can be disabled. Return 1 1168 * if channel can be disabled, 0 if not 1169 */ 1170 int 1171 pciide_chan_candisable(cp) 1172 struct pciide_channel *cp; 1173 { 1174 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1175 struct channel_softc *wdc_cp = &cp->wdc_channel; 1176 1177 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1178 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1179 printf("%s: disabling %s channel (no drives)\n", 1180 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1181 cp->hw_ok = 0; 1182 return 1; 1183 } 1184 return 0; 1185 } 1186 1187 /* 1188 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1189 * Set hw_ok=0 on failure 1190 */ 1191 void 1192 pciide_map_compat_intr(pa, cp, compatchan, interface) 1193 struct pci_attach_args *pa; 1194 struct pciide_channel *cp; 1195 int compatchan, interface; 1196 { 1197 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1198 struct channel_softc *wdc_cp = &cp->wdc_channel; 1199 1200 if (cp->hw_ok == 0) 1201 return; 1202 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1203 return; 1204 1205 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1206 pa, compatchan, pciide_compat_intr, cp); 1207 if (cp->ih == NULL) { 1208 printf("%s: no compatibility interrupt for use by %s " 1209 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1210 cp->hw_ok = 0; 1211 } 1212 } 1213 1214 void 1215 pciide_print_modes(cp) 1216 struct pciide_channel *cp; 1217 { 1218 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1219 int drive; 1220 struct channel_softc *chp; 1221 struct ata_drive_datas *drvp; 1222 1223 chp = &cp->wdc_channel; 1224 for (drive = 0; drive < 2; drive++) { 1225 drvp = &chp->ch_drive[drive]; 1226 if ((drvp->drive_flags & DRIVE) == 0) 1227 continue; 1228 printf("%s(%s:%d:%d): using PIO mode %d", 1229 drvp->drv_softc->dv_xname, 1230 sc->sc_wdcdev.sc_dev.dv_xname, 1231 chp->channel, drive, drvp->PIO_mode); 1232 if (drvp->drive_flags & DRIVE_DMA) 1233 printf(", DMA mode %d", drvp->DMA_mode); 1234 if (drvp->drive_flags & DRIVE_UDMA) 1235 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1236 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1237 printf(" (using DMA data transfers)"); 1238 printf("\n"); 1239 } 1240 } 1241 1242 void 1243 default_chip_map(sc, pa) 1244 struct pciide_softc *sc; 1245 struct pci_attach_args *pa; 1246 { 1247 struct pciide_channel *cp; 1248 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1249 pcireg_t csr; 1250 int channel, drive; 1251 struct ata_drive_datas *drvp; 1252 u_int8_t idedma_ctl; 1253 bus_size_t cmdsize, ctlsize; 1254 char *failreason; 1255 1256 if (pciide_chipen(sc, pa) == 0) 1257 return; 1258 1259 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1260 printf("%s: bus-master DMA support present", 1261 sc->sc_wdcdev.sc_dev.dv_xname); 1262 if (sc->sc_pp == &default_product_desc && 1263 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1264 PCIIDE_OPTIONS_DMA) == 0) { 1265 printf(", but unused (no driver support)"); 1266 sc->sc_dma_ok = 0; 1267 } else { 1268 pciide_mapreg_dma(sc, pa); 1269 if (sc->sc_dma_ok != 0) 1270 printf(", used without full driver " 1271 "support"); 1272 } 1273 } else { 1274 printf("%s: hardware does not support DMA", 1275 sc->sc_wdcdev.sc_dev.dv_xname); 1276 sc->sc_dma_ok = 0; 1277 } 1278 printf("\n"); 1279 if (sc->sc_dma_ok) { 1280 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1281 sc->sc_wdcdev.irqack = pciide_irqack; 1282 } 1283 sc->sc_wdcdev.PIO_cap = 0; 1284 sc->sc_wdcdev.DMA_cap = 0; 1285 1286 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1287 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1288 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1289 1290 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1291 cp = &sc->pciide_channels[channel]; 1292 if (pciide_chansetup(sc, channel, interface) == 0) 1293 continue; 1294 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1295 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1296 &ctlsize, pciide_pci_intr); 1297 } else { 1298 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1299 channel, &cmdsize, &ctlsize); 1300 } 1301 if (cp->hw_ok == 0) 1302 continue; 1303 /* 1304 * Check to see if something appears to be there. 1305 */ 1306 failreason = NULL; 1307 if (!wdcprobe(&cp->wdc_channel)) { 1308 failreason = "not responding; disabled or no drives?"; 1309 goto next; 1310 } 1311 /* 1312 * Now, make sure it's actually attributable to this PCI IDE 1313 * channel by trying to access the channel again while the 1314 * PCI IDE controller's I/O space is disabled. (If the 1315 * channel no longer appears to be there, it belongs to 1316 * this controller.) YUCK! 1317 */ 1318 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1319 PCI_COMMAND_STATUS_REG); 1320 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1321 csr & ~PCI_COMMAND_IO_ENABLE); 1322 if (wdcprobe(&cp->wdc_channel)) 1323 failreason = "other hardware responding at addresses"; 1324 pci_conf_write(sc->sc_pc, sc->sc_tag, 1325 PCI_COMMAND_STATUS_REG, csr); 1326 next: 1327 if (failreason) { 1328 printf("%s: %s channel ignored (%s)\n", 1329 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1330 failreason); 1331 cp->hw_ok = 0; 1332 bus_space_unmap(cp->wdc_channel.cmd_iot, 1333 cp->wdc_channel.cmd_ioh, cmdsize); 1334 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1335 bus_space_unmap(cp->wdc_channel.ctl_iot, 1336 cp->ctl_baseioh, ctlsize); 1337 else 1338 bus_space_unmap(cp->wdc_channel.ctl_iot, 1339 cp->wdc_channel.ctl_ioh, ctlsize); 1340 } else { 1341 pciide_map_compat_intr(pa, cp, channel, interface); 1342 } 1343 if (cp->hw_ok) { 1344 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1345 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1346 wdcattach(&cp->wdc_channel); 1347 } 1348 } 1349 1350 if (sc->sc_dma_ok == 0) 1351 return; 1352 1353 /* Allocate DMA maps */ 1354 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1355 idedma_ctl = 0; 1356 cp = &sc->pciide_channels[channel]; 1357 for (drive = 0; drive < 2; drive++) { 1358 drvp = &cp->wdc_channel.ch_drive[drive]; 1359 /* If no drive, skip */ 1360 if ((drvp->drive_flags & DRIVE) == 0) 1361 continue; 1362 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1363 continue; 1364 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1365 /* Abort DMA setup */ 1366 printf("%s:%d:%d: can't allocate DMA maps, " 1367 "using PIO transfers\n", 1368 sc->sc_wdcdev.sc_dev.dv_xname, 1369 channel, drive); 1370 drvp->drive_flags &= ~DRIVE_DMA; 1371 } 1372 printf("%s:%d:%d: using DMA data transfers\n", 1373 sc->sc_wdcdev.sc_dev.dv_xname, 1374 channel, drive); 1375 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1376 } 1377 if (idedma_ctl != 0) { 1378 /* Add software bits in status register */ 1379 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1380 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1381 idedma_ctl); 1382 } 1383 } 1384 } 1385 1386 void 1387 piix_chip_map(sc, pa) 1388 struct pciide_softc *sc; 1389 struct pci_attach_args *pa; 1390 { 1391 struct pciide_channel *cp; 1392 int channel; 1393 u_int32_t idetim; 1394 bus_size_t cmdsize, ctlsize; 1395 1396 if (pciide_chipen(sc, pa) == 0) 1397 return; 1398 1399 printf("%s: bus-master DMA support present", 1400 sc->sc_wdcdev.sc_dev.dv_xname); 1401 pciide_mapreg_dma(sc, pa); 1402 printf("\n"); 1403 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1404 WDC_CAPABILITY_MODE; 1405 if (sc->sc_dma_ok) { 1406 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1407 sc->sc_wdcdev.irqack = pciide_irqack; 1408 switch(sc->sc_pp->ide_product) { 1409 case PCI_PRODUCT_INTEL_82371AB_IDE: 1410 case PCI_PRODUCT_INTEL_82801AA_IDE: 1411 case PCI_PRODUCT_INTEL_82801AB_IDE: 1412 case PCI_PRODUCT_INTEL_82801BA_IDE: 1413 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1414 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1415 } 1416 } 1417 sc->sc_wdcdev.PIO_cap = 4; 1418 sc->sc_wdcdev.DMA_cap = 2; 1419 switch(sc->sc_pp->ide_product) { 1420 case PCI_PRODUCT_INTEL_82801AA_IDE: 1421 sc->sc_wdcdev.UDMA_cap = 4; 1422 break; 1423 case PCI_PRODUCT_INTEL_82801BA_IDE: 1424 case PCI_PRODUCT_INTEL_82801BAM_IDE: 1425 sc->sc_wdcdev.UDMA_cap = 5; 1426 break; 1427 default: 1428 sc->sc_wdcdev.UDMA_cap = 2; 1429 } 1430 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1431 sc->sc_wdcdev.set_modes = piix_setup_channel; 1432 else 1433 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1434 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1435 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1436 1437 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1438 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1439 DEBUG_PROBE); 1440 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1441 WDCDEBUG_PRINT((", sidetim=0x%x", 1442 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1443 DEBUG_PROBE); 1444 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1445 WDCDEBUG_PRINT((", udamreg 0x%x", 1446 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1447 DEBUG_PROBE); 1448 } 1449 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1450 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1451 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1452 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1453 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1454 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1455 DEBUG_PROBE); 1456 } 1457 1458 } 1459 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1460 1461 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1462 cp = &sc->pciide_channels[channel]; 1463 /* PIIX is compat-only */ 1464 if (pciide_chansetup(sc, channel, 0) == 0) 1465 continue; 1466 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1467 if ((PIIX_IDETIM_READ(idetim, channel) & 1468 PIIX_IDETIM_IDE) == 0) { 1469 printf("%s: %s channel ignored (disabled)\n", 1470 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1471 continue; 1472 } 1473 /* PIIX are compat-only pciide devices */ 1474 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1475 if (cp->hw_ok == 0) 1476 continue; 1477 if (pciide_chan_candisable(cp)) { 1478 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1479 channel); 1480 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1481 idetim); 1482 } 1483 pciide_map_compat_intr(pa, cp, channel, 0); 1484 if (cp->hw_ok == 0) 1485 continue; 1486 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1487 } 1488 1489 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1490 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1491 DEBUG_PROBE); 1492 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1493 WDCDEBUG_PRINT((", sidetim=0x%x", 1494 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1495 DEBUG_PROBE); 1496 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1497 WDCDEBUG_PRINT((", udamreg 0x%x", 1498 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1499 DEBUG_PROBE); 1500 } 1501 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1502 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1503 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1504 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1505 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1506 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1507 DEBUG_PROBE); 1508 } 1509 } 1510 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1511 } 1512 1513 void 1514 piix_setup_channel(chp) 1515 struct channel_softc *chp; 1516 { 1517 u_int8_t mode[2], drive; 1518 u_int32_t oidetim, idetim, idedma_ctl; 1519 struct pciide_channel *cp = (struct pciide_channel*)chp; 1520 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1521 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1522 1523 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1524 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1525 idedma_ctl = 0; 1526 1527 /* set up new idetim: Enable IDE registers decode */ 1528 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1529 chp->channel); 1530 1531 /* setup DMA */ 1532 pciide_channel_dma_setup(cp); 1533 1534 /* 1535 * Here we have to mess up with drives mode: PIIX can't have 1536 * different timings for master and slave drives. 1537 * We need to find the best combination. 1538 */ 1539 1540 /* If both drives supports DMA, take the lower mode */ 1541 if ((drvp[0].drive_flags & DRIVE_DMA) && 1542 (drvp[1].drive_flags & DRIVE_DMA)) { 1543 mode[0] = mode[1] = 1544 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1545 drvp[0].DMA_mode = mode[0]; 1546 drvp[1].DMA_mode = mode[1]; 1547 goto ok; 1548 } 1549 /* 1550 * If only one drive supports DMA, use its mode, and 1551 * put the other one in PIO mode 0 if mode not compatible 1552 */ 1553 if (drvp[0].drive_flags & DRIVE_DMA) { 1554 mode[0] = drvp[0].DMA_mode; 1555 mode[1] = drvp[1].PIO_mode; 1556 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1557 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1558 mode[1] = drvp[1].PIO_mode = 0; 1559 goto ok; 1560 } 1561 if (drvp[1].drive_flags & DRIVE_DMA) { 1562 mode[1] = drvp[1].DMA_mode; 1563 mode[0] = drvp[0].PIO_mode; 1564 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1565 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1566 mode[0] = drvp[0].PIO_mode = 0; 1567 goto ok; 1568 } 1569 /* 1570 * If both drives are not DMA, takes the lower mode, unless 1571 * one of them is PIO mode < 2 1572 */ 1573 if (drvp[0].PIO_mode < 2) { 1574 mode[0] = drvp[0].PIO_mode = 0; 1575 mode[1] = drvp[1].PIO_mode; 1576 } else if (drvp[1].PIO_mode < 2) { 1577 mode[1] = drvp[1].PIO_mode = 0; 1578 mode[0] = drvp[0].PIO_mode; 1579 } else { 1580 mode[0] = mode[1] = 1581 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1582 drvp[0].PIO_mode = mode[0]; 1583 drvp[1].PIO_mode = mode[1]; 1584 } 1585 ok: /* The modes are setup */ 1586 for (drive = 0; drive < 2; drive++) { 1587 if (drvp[drive].drive_flags & DRIVE_DMA) { 1588 idetim |= piix_setup_idetim_timings( 1589 mode[drive], 1, chp->channel); 1590 goto end; 1591 } 1592 } 1593 /* If we are there, none of the drives are DMA */ 1594 if (mode[0] >= 2) 1595 idetim |= piix_setup_idetim_timings( 1596 mode[0], 0, chp->channel); 1597 else 1598 idetim |= piix_setup_idetim_timings( 1599 mode[1], 0, chp->channel); 1600 end: /* 1601 * timing mode is now set up in the controller. Enable 1602 * it per-drive 1603 */ 1604 for (drive = 0; drive < 2; drive++) { 1605 /* If no drive, skip */ 1606 if ((drvp[drive].drive_flags & DRIVE) == 0) 1607 continue; 1608 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1609 if (drvp[drive].drive_flags & DRIVE_DMA) 1610 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1611 } 1612 if (idedma_ctl != 0) { 1613 /* Add software bits in status register */ 1614 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1615 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1616 idedma_ctl); 1617 } 1618 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1619 pciide_print_modes(cp); 1620 } 1621 1622 void 1623 piix3_4_setup_channel(chp) 1624 struct channel_softc *chp; 1625 { 1626 struct ata_drive_datas *drvp; 1627 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1628 struct pciide_channel *cp = (struct pciide_channel*)chp; 1629 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1630 int drive; 1631 int channel = chp->channel; 1632 1633 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1634 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1635 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1636 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1637 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1638 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1639 PIIX_SIDETIM_RTC_MASK(channel)); 1640 1641 idedma_ctl = 0; 1642 /* If channel disabled, no need to go further */ 1643 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1644 return; 1645 /* set up new idetim: Enable IDE registers decode */ 1646 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1647 1648 /* setup DMA if needed */ 1649 pciide_channel_dma_setup(cp); 1650 1651 for (drive = 0; drive < 2; drive++) { 1652 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1653 PIIX_UDMATIM_SET(0x3, channel, drive)); 1654 drvp = &chp->ch_drive[drive]; 1655 /* If no drive, skip */ 1656 if ((drvp->drive_flags & DRIVE) == 0) 1657 continue; 1658 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1659 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1660 goto pio; 1661 1662 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1663 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE || 1664 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1665 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1666 ideconf |= PIIX_CONFIG_PINGPONG; 1667 } 1668 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BA_IDE || 1669 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801BAM_IDE) { 1670 /* setup Ultra/100 */ 1671 if (drvp->UDMA_mode > 2 && 1672 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1673 drvp->UDMA_mode = 2; 1674 if (drvp->UDMA_mode > 4) { 1675 ideconf |= PIIX_CONFIG_UDMA100(channel, drive); 1676 } else { 1677 ideconf &= ~PIIX_CONFIG_UDMA100(channel, drive); 1678 if (drvp->UDMA_mode > 2) { 1679 ideconf |= PIIX_CONFIG_UDMA66(channel, 1680 drive); 1681 } else { 1682 ideconf &= ~PIIX_CONFIG_UDMA66(channel, 1683 drive); 1684 } 1685 } 1686 } 1687 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1688 /* setup Ultra/66 */ 1689 if (drvp->UDMA_mode > 2 && 1690 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1691 drvp->UDMA_mode = 2; 1692 if (drvp->UDMA_mode > 2) 1693 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1694 else 1695 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1696 } 1697 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1698 (drvp->drive_flags & DRIVE_UDMA)) { 1699 /* use Ultra/DMA */ 1700 drvp->drive_flags &= ~DRIVE_DMA; 1701 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1702 udmareg |= PIIX_UDMATIM_SET( 1703 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1704 } else { 1705 /* use Multiword DMA */ 1706 drvp->drive_flags &= ~DRIVE_UDMA; 1707 if (drive == 0) { 1708 idetim |= piix_setup_idetim_timings( 1709 drvp->DMA_mode, 1, channel); 1710 } else { 1711 sidetim |= piix_setup_sidetim_timings( 1712 drvp->DMA_mode, 1, channel); 1713 idetim =PIIX_IDETIM_SET(idetim, 1714 PIIX_IDETIM_SITRE, channel); 1715 } 1716 } 1717 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1718 1719 pio: /* use PIO mode */ 1720 idetim |= piix_setup_idetim_drvs(drvp); 1721 if (drive == 0) { 1722 idetim |= piix_setup_idetim_timings( 1723 drvp->PIO_mode, 0, channel); 1724 } else { 1725 sidetim |= piix_setup_sidetim_timings( 1726 drvp->PIO_mode, 0, channel); 1727 idetim =PIIX_IDETIM_SET(idetim, 1728 PIIX_IDETIM_SITRE, channel); 1729 } 1730 } 1731 if (idedma_ctl != 0) { 1732 /* Add software bits in status register */ 1733 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1734 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1735 idedma_ctl); 1736 } 1737 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1738 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1739 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1740 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1741 pciide_print_modes(cp); 1742 } 1743 1744 1745 /* setup ISP and RTC fields, based on mode */ 1746 static u_int32_t 1747 piix_setup_idetim_timings(mode, dma, channel) 1748 u_int8_t mode; 1749 u_int8_t dma; 1750 u_int8_t channel; 1751 { 1752 1753 if (dma) 1754 return PIIX_IDETIM_SET(0, 1755 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1756 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1757 channel); 1758 else 1759 return PIIX_IDETIM_SET(0, 1760 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1761 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1762 channel); 1763 } 1764 1765 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1766 static u_int32_t 1767 piix_setup_idetim_drvs(drvp) 1768 struct ata_drive_datas *drvp; 1769 { 1770 u_int32_t ret = 0; 1771 struct channel_softc *chp = drvp->chnl_softc; 1772 u_int8_t channel = chp->channel; 1773 u_int8_t drive = drvp->drive; 1774 1775 /* 1776 * If drive is using UDMA, timings setups are independant 1777 * So just check DMA and PIO here. 1778 */ 1779 if (drvp->drive_flags & DRIVE_DMA) { 1780 /* if mode = DMA mode 0, use compatible timings */ 1781 if ((drvp->drive_flags & DRIVE_DMA) && 1782 drvp->DMA_mode == 0) { 1783 drvp->PIO_mode = 0; 1784 return ret; 1785 } 1786 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1787 /* 1788 * PIO and DMA timings are the same, use fast timings for PIO 1789 * too, else use compat timings. 1790 */ 1791 if ((piix_isp_pio[drvp->PIO_mode] != 1792 piix_isp_dma[drvp->DMA_mode]) || 1793 (piix_rtc_pio[drvp->PIO_mode] != 1794 piix_rtc_dma[drvp->DMA_mode])) 1795 drvp->PIO_mode = 0; 1796 /* if PIO mode <= 2, use compat timings for PIO */ 1797 if (drvp->PIO_mode <= 2) { 1798 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1799 channel); 1800 return ret; 1801 } 1802 } 1803 1804 /* 1805 * Now setup PIO modes. If mode < 2, use compat timings. 1806 * Else enable fast timings. Enable IORDY and prefetch/post 1807 * if PIO mode >= 3. 1808 */ 1809 1810 if (drvp->PIO_mode < 2) 1811 return ret; 1812 1813 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1814 if (drvp->PIO_mode >= 3) { 1815 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1816 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1817 } 1818 return ret; 1819 } 1820 1821 /* setup values in SIDETIM registers, based on mode */ 1822 static u_int32_t 1823 piix_setup_sidetim_timings(mode, dma, channel) 1824 u_int8_t mode; 1825 u_int8_t dma; 1826 u_int8_t channel; 1827 { 1828 if (dma) 1829 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1830 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1831 else 1832 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1833 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1834 } 1835 1836 void 1837 amd7x6_chip_map(sc, pa) 1838 struct pciide_softc *sc; 1839 struct pci_attach_args *pa; 1840 { 1841 struct pciide_channel *cp; 1842 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1843 int channel; 1844 pcireg_t chanenable; 1845 bus_size_t cmdsize, ctlsize; 1846 1847 if (pciide_chipen(sc, pa) == 0) 1848 return; 1849 printf("%s: bus-master DMA support present", 1850 sc->sc_wdcdev.sc_dev.dv_xname); 1851 pciide_mapreg_dma(sc, pa); 1852 printf("\n"); 1853 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1854 WDC_CAPABILITY_MODE; 1855 if (sc->sc_dma_ok) { 1856 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1857 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1858 sc->sc_wdcdev.irqack = pciide_irqack; 1859 } 1860 sc->sc_wdcdev.PIO_cap = 4; 1861 sc->sc_wdcdev.DMA_cap = 2; 1862 1863 switch (sc->sc_pp->ide_product) { 1864 case PCI_PRODUCT_AMD_PBC766_IDE: 1865 case PCI_PRODUCT_AMD_PBC768_IDE: 1866 sc->sc_wdcdev.UDMA_cap = 5; 1867 break; 1868 default: 1869 sc->sc_wdcdev.UDMA_cap = 4; 1870 } 1871 sc->sc_wdcdev.set_modes = amd7x6_setup_channel; 1872 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1873 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1874 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN); 1875 1876 WDCDEBUG_PRINT(("amd7x6_chip_map: Channel enable=0x%x\n", chanenable), 1877 DEBUG_PROBE); 1878 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1879 cp = &sc->pciide_channels[channel]; 1880 if (pciide_chansetup(sc, channel, interface) == 0) 1881 continue; 1882 1883 if ((chanenable & AMD7X6_CHAN_EN(channel)) == 0) { 1884 printf("%s: %s channel ignored (disabled)\n", 1885 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1886 continue; 1887 } 1888 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1889 pciide_pci_intr); 1890 1891 if (pciide_chan_candisable(cp)) 1892 chanenable &= ~AMD7X6_CHAN_EN(channel); 1893 pciide_map_compat_intr(pa, cp, channel, interface); 1894 if (cp->hw_ok == 0) 1895 continue; 1896 1897 amd7x6_setup_channel(&cp->wdc_channel); 1898 } 1899 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_CHANSTATUS_EN, 1900 chanenable); 1901 return; 1902 } 1903 1904 void 1905 amd7x6_setup_channel(chp) 1906 struct channel_softc *chp; 1907 { 1908 u_int32_t udmatim_reg, datatim_reg; 1909 u_int8_t idedma_ctl; 1910 int mode, drive; 1911 struct ata_drive_datas *drvp; 1912 struct pciide_channel *cp = (struct pciide_channel*)chp; 1913 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1914 #ifndef PCIIDE_AMD756_ENABLEDMA 1915 int rev = PCI_REVISION( 1916 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1917 #endif 1918 1919 idedma_ctl = 0; 1920 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM); 1921 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA); 1922 datatim_reg &= ~AMD7X6_DATATIM_MASK(chp->channel); 1923 udmatim_reg &= ~AMD7X6_UDMA_MASK(chp->channel); 1924 1925 /* setup DMA if needed */ 1926 pciide_channel_dma_setup(cp); 1927 1928 for (drive = 0; drive < 2; drive++) { 1929 drvp = &chp->ch_drive[drive]; 1930 /* If no drive, skip */ 1931 if ((drvp->drive_flags & DRIVE) == 0) 1932 continue; 1933 /* add timing values, setup DMA if needed */ 1934 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1935 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1936 mode = drvp->PIO_mode; 1937 goto pio; 1938 } 1939 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1940 (drvp->drive_flags & DRIVE_UDMA)) { 1941 /* use Ultra/DMA */ 1942 drvp->drive_flags &= ~DRIVE_DMA; 1943 udmatim_reg |= AMD7X6_UDMA_EN(chp->channel, drive) | 1944 AMD7X6_UDMA_EN_MTH(chp->channel, drive) | 1945 AMD7X6_UDMA_TIME(chp->channel, drive, 1946 amd7x6_udma_tim[drvp->UDMA_mode]); 1947 /* can use PIO timings, MW DMA unused */ 1948 mode = drvp->PIO_mode; 1949 } else { 1950 /* use Multiword DMA, but only if revision is OK */ 1951 drvp->drive_flags &= ~DRIVE_UDMA; 1952 #ifndef PCIIDE_AMD756_ENABLEDMA 1953 /* 1954 * The workaround doesn't seem to be necessary 1955 * with all drives, so it can be disabled by 1956 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1957 * triggered. 1958 */ 1959 if (sc->sc_pp->ide_product == 1960 PCI_PRODUCT_AMD_PBC756_IDE && 1961 AMD756_CHIPREV_DISABLEDMA(rev)) { 1962 printf("%s:%d:%d: multi-word DMA disabled due " 1963 "to chip revision\n", 1964 sc->sc_wdcdev.sc_dev.dv_xname, 1965 chp->channel, drive); 1966 mode = drvp->PIO_mode; 1967 drvp->drive_flags &= ~DRIVE_DMA; 1968 goto pio; 1969 } 1970 #endif 1971 /* mode = min(pio, dma+2) */ 1972 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1973 mode = drvp->PIO_mode; 1974 else 1975 mode = drvp->DMA_mode + 2; 1976 } 1977 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1978 1979 pio: /* setup PIO mode */ 1980 if (mode <= 2) { 1981 drvp->DMA_mode = 0; 1982 drvp->PIO_mode = 0; 1983 mode = 0; 1984 } else { 1985 drvp->PIO_mode = mode; 1986 drvp->DMA_mode = mode - 2; 1987 } 1988 datatim_reg |= 1989 AMD7X6_DATATIM_PULSE(chp->channel, drive, 1990 amd7x6_pio_set[mode]) | 1991 AMD7X6_DATATIM_RECOV(chp->channel, drive, 1992 amd7x6_pio_rec[mode]); 1993 } 1994 if (idedma_ctl != 0) { 1995 /* Add software bits in status register */ 1996 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1997 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1998 idedma_ctl); 1999 } 2000 pciide_print_modes(cp); 2001 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_DATATIM, datatim_reg); 2002 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD7X6_UDMA, udmatim_reg); 2003 } 2004 2005 void 2006 apollo_chip_map(sc, pa) 2007 struct pciide_softc *sc; 2008 struct pci_attach_args *pa; 2009 { 2010 struct pciide_channel *cp; 2011 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2012 int channel; 2013 u_int32_t ideconf; 2014 bus_size_t cmdsize, ctlsize; 2015 pcitag_t pcib_tag; 2016 pcireg_t pcib_id, pcib_class; 2017 2018 if (pciide_chipen(sc, pa) == 0) 2019 return; 2020 /* get a PCI tag for the ISA bridge (function 0 of the same device) */ 2021 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2022 /* and read ID and rev of the ISA bridge */ 2023 pcib_id = pci_conf_read(sc->sc_pc, pcib_tag, PCI_ID_REG); 2024 pcib_class = pci_conf_read(sc->sc_pc, pcib_tag, PCI_CLASS_REG); 2025 printf(": VIA Technologies "); 2026 switch (PCI_PRODUCT(pcib_id)) { 2027 case PCI_PRODUCT_VIATECH_VT82C586_ISA: 2028 printf("VT82C586 (Apollo VP) "); 2029 if(PCI_REVISION(pcib_class) >= 0x02) { 2030 printf("ATA33 controller\n"); 2031 sc->sc_wdcdev.UDMA_cap = 2; 2032 } else { 2033 printf("controller\n"); 2034 sc->sc_wdcdev.UDMA_cap = 0; 2035 } 2036 break; 2037 case PCI_PRODUCT_VIATECH_VT82C596A: 2038 printf("VT82C596A (Apollo Pro) "); 2039 if (PCI_REVISION(pcib_class) >= 0x12) { 2040 printf("ATA66 controller\n"); 2041 sc->sc_wdcdev.UDMA_cap = 4; 2042 } else { 2043 printf("ATA33 controller\n"); 2044 sc->sc_wdcdev.UDMA_cap = 2; 2045 } 2046 break; 2047 case PCI_PRODUCT_VIATECH_VT82C686A_ISA: 2048 printf("VT82C686A (Apollo KX133) "); 2049 if (PCI_REVISION(pcib_class) >= 0x40) { 2050 printf("ATA100 controller\n"); 2051 sc->sc_wdcdev.UDMA_cap = 5; 2052 } else { 2053 printf("ATA66 controller\n"); 2054 sc->sc_wdcdev.UDMA_cap = 4; 2055 } 2056 break; 2057 default: 2058 printf("unknown ATA controller\n"); 2059 sc->sc_wdcdev.UDMA_cap = 0; 2060 } 2061 2062 printf("%s: bus-master DMA support present", 2063 sc->sc_wdcdev.sc_dev.dv_xname); 2064 pciide_mapreg_dma(sc, pa); 2065 printf("\n"); 2066 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2067 WDC_CAPABILITY_MODE; 2068 if (sc->sc_dma_ok) { 2069 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2070 sc->sc_wdcdev.irqack = pciide_irqack; 2071 if (sc->sc_wdcdev.UDMA_cap > 0) 2072 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2073 } 2074 sc->sc_wdcdev.PIO_cap = 4; 2075 sc->sc_wdcdev.DMA_cap = 2; 2076 sc->sc_wdcdev.set_modes = apollo_setup_channel; 2077 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2078 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2079 2080 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 2081 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2082 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 2083 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 2084 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2085 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 2086 DEBUG_PROBE); 2087 2088 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2089 cp = &sc->pciide_channels[channel]; 2090 if (pciide_chansetup(sc, channel, interface) == 0) 2091 continue; 2092 2093 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 2094 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 2095 printf("%s: %s channel ignored (disabled)\n", 2096 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2097 continue; 2098 } 2099 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2100 pciide_pci_intr); 2101 if (cp->hw_ok == 0) 2102 continue; 2103 if (pciide_chan_candisable(cp)) { 2104 ideconf &= ~APO_IDECONF_EN(channel); 2105 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 2106 ideconf); 2107 } 2108 pciide_map_compat_intr(pa, cp, channel, interface); 2109 2110 if (cp->hw_ok == 0) 2111 continue; 2112 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 2113 } 2114 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 2115 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 2116 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 2117 } 2118 2119 void 2120 apollo_setup_channel(chp) 2121 struct channel_softc *chp; 2122 { 2123 u_int32_t udmatim_reg, datatim_reg; 2124 u_int8_t idedma_ctl; 2125 int mode, drive; 2126 struct ata_drive_datas *drvp; 2127 struct pciide_channel *cp = (struct pciide_channel*)chp; 2128 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2129 2130 idedma_ctl = 0; 2131 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 2132 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 2133 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 2134 udmatim_reg &= ~APO_UDMA_MASK(chp->channel); 2135 2136 /* setup DMA if needed */ 2137 pciide_channel_dma_setup(cp); 2138 2139 for (drive = 0; drive < 2; drive++) { 2140 drvp = &chp->ch_drive[drive]; 2141 /* If no drive, skip */ 2142 if ((drvp->drive_flags & DRIVE) == 0) 2143 continue; 2144 /* add timing values, setup DMA if needed */ 2145 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 2146 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 2147 mode = drvp->PIO_mode; 2148 goto pio; 2149 } 2150 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2151 (drvp->drive_flags & DRIVE_UDMA)) { 2152 /* use Ultra/DMA */ 2153 drvp->drive_flags &= ~DRIVE_DMA; 2154 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2155 APO_UDMA_EN_MTH(chp->channel, drive); 2156 if (sc->sc_wdcdev.UDMA_cap == 5) { 2157 /* 686b */ 2158 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2159 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2160 drive, apollo_udma100_tim[drvp->UDMA_mode]); 2161 } else if (sc->sc_wdcdev.UDMA_cap == 4) { 2162 /* 596b or 686a */ 2163 udmatim_reg |= APO_UDMA_CLK66(chp->channel); 2164 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2165 drive, apollo_udma66_tim[drvp->UDMA_mode]); 2166 } else { 2167 /* 596a or 586b */ 2168 udmatim_reg |= APO_UDMA_TIME(chp->channel, 2169 drive, apollo_udma33_tim[drvp->UDMA_mode]); 2170 } 2171 /* can use PIO timings, MW DMA unused */ 2172 mode = drvp->PIO_mode; 2173 } else { 2174 /* use Multiword DMA */ 2175 drvp->drive_flags &= ~DRIVE_UDMA; 2176 /* mode = min(pio, dma+2) */ 2177 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2178 mode = drvp->PIO_mode; 2179 else 2180 mode = drvp->DMA_mode + 2; 2181 } 2182 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2183 2184 pio: /* setup PIO mode */ 2185 if (mode <= 2) { 2186 drvp->DMA_mode = 0; 2187 drvp->PIO_mode = 0; 2188 mode = 0; 2189 } else { 2190 drvp->PIO_mode = mode; 2191 drvp->DMA_mode = mode - 2; 2192 } 2193 datatim_reg |= 2194 APO_DATATIM_PULSE(chp->channel, drive, 2195 apollo_pio_set[mode]) | 2196 APO_DATATIM_RECOV(chp->channel, drive, 2197 apollo_pio_rec[mode]); 2198 } 2199 if (idedma_ctl != 0) { 2200 /* Add software bits in status register */ 2201 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2202 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2203 idedma_ctl); 2204 } 2205 pciide_print_modes(cp); 2206 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2207 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2208 } 2209 2210 void 2211 cmd_channel_map(pa, sc, channel) 2212 struct pci_attach_args *pa; 2213 struct pciide_softc *sc; 2214 int channel; 2215 { 2216 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2217 bus_size_t cmdsize, ctlsize; 2218 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2219 int interface; 2220 2221 /* 2222 * The 0648/0649 can be told to identify as a RAID controller. 2223 * In this case, we have to fake interface 2224 */ 2225 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2226 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2227 PCIIDE_INTERFACE_SETTABLE(1); 2228 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2229 CMD_CONF_DSA1) 2230 interface |= PCIIDE_INTERFACE_PCI(0) | 2231 PCIIDE_INTERFACE_PCI(1); 2232 } else { 2233 interface = PCI_INTERFACE(pa->pa_class); 2234 } 2235 2236 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2237 cp->name = PCIIDE_CHANNEL_NAME(channel); 2238 cp->wdc_channel.channel = channel; 2239 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2240 2241 if (channel > 0) { 2242 cp->wdc_channel.ch_queue = 2243 sc->pciide_channels[0].wdc_channel.ch_queue; 2244 } else { 2245 cp->wdc_channel.ch_queue = 2246 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2247 } 2248 if (cp->wdc_channel.ch_queue == NULL) { 2249 printf("%s %s channel: " 2250 "can't allocate memory for command queue", 2251 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2252 return; 2253 } 2254 2255 printf("%s: %s channel %s to %s mode\n", 2256 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2257 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2258 "configured" : "wired", 2259 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2260 "native-PCI" : "compatibility"); 2261 2262 /* 2263 * with a CMD PCI64x, if we get here, the first channel is enabled: 2264 * there's no way to disable the first channel without disabling 2265 * the whole device 2266 */ 2267 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2268 printf("%s: %s channel ignored (disabled)\n", 2269 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2270 return; 2271 } 2272 2273 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2274 if (cp->hw_ok == 0) 2275 return; 2276 if (channel == 1) { 2277 if (pciide_chan_candisable(cp)) { 2278 ctrl &= ~CMD_CTRL_2PORT; 2279 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2280 CMD_CTRL, ctrl); 2281 } 2282 } 2283 pciide_map_compat_intr(pa, cp, channel, interface); 2284 } 2285 2286 int 2287 cmd_pci_intr(arg) 2288 void *arg; 2289 { 2290 struct pciide_softc *sc = arg; 2291 struct pciide_channel *cp; 2292 struct channel_softc *wdc_cp; 2293 int i, rv, crv; 2294 u_int32_t priirq, secirq; 2295 2296 rv = 0; 2297 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2298 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2299 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2300 cp = &sc->pciide_channels[i]; 2301 wdc_cp = &cp->wdc_channel; 2302 /* If a compat channel skip. */ 2303 if (cp->compat) 2304 continue; 2305 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2306 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2307 crv = wdcintr(wdc_cp); 2308 if (crv == 0) 2309 printf("%s:%d: bogus intr\n", 2310 sc->sc_wdcdev.sc_dev.dv_xname, i); 2311 else 2312 rv = 1; 2313 } 2314 } 2315 return rv; 2316 } 2317 2318 void 2319 cmd_chip_map(sc, pa) 2320 struct pciide_softc *sc; 2321 struct pci_attach_args *pa; 2322 { 2323 int channel; 2324 2325 /* 2326 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2327 * and base adresses registers can be disabled at 2328 * hardware level. In this case, the device is wired 2329 * in compat mode and its first channel is always enabled, 2330 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2331 * In fact, it seems that the first channel of the CMD PCI0640 2332 * can't be disabled. 2333 */ 2334 2335 #ifdef PCIIDE_CMD064x_DISABLE 2336 if (pciide_chipen(sc, pa) == 0) 2337 return; 2338 #endif 2339 2340 printf("%s: hardware does not support DMA\n", 2341 sc->sc_wdcdev.sc_dev.dv_xname); 2342 sc->sc_dma_ok = 0; 2343 2344 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2345 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2346 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2347 2348 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2349 cmd_channel_map(pa, sc, channel); 2350 } 2351 } 2352 2353 void 2354 cmd0643_9_chip_map(sc, pa) 2355 struct pciide_softc *sc; 2356 struct pci_attach_args *pa; 2357 { 2358 struct pciide_channel *cp; 2359 int channel; 2360 int rev = PCI_REVISION( 2361 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2362 2363 /* 2364 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2365 * and base adresses registers can be disabled at 2366 * hardware level. In this case, the device is wired 2367 * in compat mode and its first channel is always enabled, 2368 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2369 * In fact, it seems that the first channel of the CMD PCI0640 2370 * can't be disabled. 2371 */ 2372 2373 #ifdef PCIIDE_CMD064x_DISABLE 2374 if (pciide_chipen(sc, pa) == 0) 2375 return; 2376 #endif 2377 printf("%s: bus-master DMA support present", 2378 sc->sc_wdcdev.sc_dev.dv_xname); 2379 pciide_mapreg_dma(sc, pa); 2380 printf("\n"); 2381 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2382 WDC_CAPABILITY_MODE; 2383 if (sc->sc_dma_ok) { 2384 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2385 switch (sc->sc_pp->ide_product) { 2386 case PCI_PRODUCT_CMDTECH_649: 2387 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2388 sc->sc_wdcdev.UDMA_cap = 5; 2389 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2390 break; 2391 case PCI_PRODUCT_CMDTECH_648: 2392 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2393 sc->sc_wdcdev.UDMA_cap = 4; 2394 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2395 break; 2396 case PCI_PRODUCT_CMDTECH_646: 2397 if (rev >= CMD0646U2_REV) { 2398 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2399 sc->sc_wdcdev.UDMA_cap = 2; 2400 } else if (rev >= CMD0646U_REV) { 2401 /* 2402 * Linux's driver claims that the 646U is broken 2403 * with UDMA. Only enable it if we know what we're 2404 * doing 2405 */ 2406 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2407 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2408 sc->sc_wdcdev.UDMA_cap = 2; 2409 #endif 2410 /* explicitely disable UDMA */ 2411 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2412 CMD_UDMATIM(0), 0); 2413 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2414 CMD_UDMATIM(1), 0); 2415 } 2416 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2417 break; 2418 default: 2419 sc->sc_wdcdev.irqack = pciide_irqack; 2420 } 2421 } 2422 2423 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2424 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2425 sc->sc_wdcdev.PIO_cap = 4; 2426 sc->sc_wdcdev.DMA_cap = 2; 2427 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2428 2429 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2430 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2431 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2432 DEBUG_PROBE); 2433 2434 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2435 cp = &sc->pciide_channels[channel]; 2436 cmd_channel_map(pa, sc, channel); 2437 if (cp->hw_ok == 0) 2438 continue; 2439 cmd0643_9_setup_channel(&cp->wdc_channel); 2440 } 2441 /* 2442 * note - this also makes sure we clear the irq disable and reset 2443 * bits 2444 */ 2445 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2446 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2447 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2448 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2449 DEBUG_PROBE); 2450 } 2451 2452 void 2453 cmd0643_9_setup_channel(chp) 2454 struct channel_softc *chp; 2455 { 2456 struct ata_drive_datas *drvp; 2457 u_int8_t tim; 2458 u_int32_t idedma_ctl, udma_reg; 2459 int drive; 2460 struct pciide_channel *cp = (struct pciide_channel*)chp; 2461 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2462 2463 idedma_ctl = 0; 2464 /* setup DMA if needed */ 2465 pciide_channel_dma_setup(cp); 2466 2467 for (drive = 0; drive < 2; drive++) { 2468 drvp = &chp->ch_drive[drive]; 2469 /* If no drive, skip */ 2470 if ((drvp->drive_flags & DRIVE) == 0) 2471 continue; 2472 /* add timing values, setup DMA if needed */ 2473 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2474 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2475 if (drvp->drive_flags & DRIVE_UDMA) { 2476 /* UltraDMA on a 646U2, 0648 or 0649 */ 2477 drvp->drive_flags &= ~DRIVE_DMA; 2478 udma_reg = pciide_pci_read(sc->sc_pc, 2479 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2480 if (drvp->UDMA_mode > 2 && 2481 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2482 CMD_BICSR) & 2483 CMD_BICSR_80(chp->channel)) == 0) 2484 drvp->UDMA_mode = 2; 2485 if (drvp->UDMA_mode > 2) 2486 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2487 else if (sc->sc_wdcdev.UDMA_cap > 2) 2488 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2489 udma_reg |= CMD_UDMATIM_UDMA(drive); 2490 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2491 CMD_UDMATIM_TIM_OFF(drive)); 2492 udma_reg |= 2493 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2494 CMD_UDMATIM_TIM_OFF(drive)); 2495 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2496 CMD_UDMATIM(chp->channel), udma_reg); 2497 } else { 2498 /* 2499 * use Multiword DMA. 2500 * Timings will be used for both PIO and DMA, 2501 * so adjust DMA mode if needed 2502 * if we have a 0646U2/8/9, turn off UDMA 2503 */ 2504 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2505 udma_reg = pciide_pci_read(sc->sc_pc, 2506 sc->sc_tag, 2507 CMD_UDMATIM(chp->channel)); 2508 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2509 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2510 CMD_UDMATIM(chp->channel), 2511 udma_reg); 2512 } 2513 if (drvp->PIO_mode >= 3 && 2514 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2515 drvp->DMA_mode = drvp->PIO_mode - 2; 2516 } 2517 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2518 } 2519 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2520 } 2521 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2522 CMD_DATA_TIM(chp->channel, drive), tim); 2523 } 2524 if (idedma_ctl != 0) { 2525 /* Add software bits in status register */ 2526 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2527 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2528 idedma_ctl); 2529 } 2530 pciide_print_modes(cp); 2531 } 2532 2533 void 2534 cmd646_9_irqack(chp) 2535 struct channel_softc *chp; 2536 { 2537 u_int32_t priirq, secirq; 2538 struct pciide_channel *cp = (struct pciide_channel*)chp; 2539 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2540 2541 if (chp->channel == 0) { 2542 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2543 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2544 } else { 2545 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2546 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2547 } 2548 pciide_irqack(chp); 2549 } 2550 2551 void 2552 cy693_chip_map(sc, pa) 2553 struct pciide_softc *sc; 2554 struct pci_attach_args *pa; 2555 { 2556 struct pciide_channel *cp; 2557 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2558 bus_size_t cmdsize, ctlsize; 2559 2560 if (pciide_chipen(sc, pa) == 0) 2561 return; 2562 /* 2563 * this chip has 2 PCI IDE functions, one for primary and one for 2564 * secondary. So we need to call pciide_mapregs_compat() with 2565 * the real channel 2566 */ 2567 if (pa->pa_function == 1) { 2568 sc->sc_cy_compatchan = 0; 2569 } else if (pa->pa_function == 2) { 2570 sc->sc_cy_compatchan = 1; 2571 } else { 2572 printf("%s: unexpected PCI function %d\n", 2573 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2574 return; 2575 } 2576 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2577 printf("%s: bus-master DMA support present", 2578 sc->sc_wdcdev.sc_dev.dv_xname); 2579 pciide_mapreg_dma(sc, pa); 2580 } else { 2581 printf("%s: hardware does not support DMA", 2582 sc->sc_wdcdev.sc_dev.dv_xname); 2583 sc->sc_dma_ok = 0; 2584 } 2585 printf("\n"); 2586 2587 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2588 if (sc->sc_cy_handle == NULL) { 2589 printf("%s: unable to map hyperCache control registers\n", 2590 sc->sc_wdcdev.sc_dev.dv_xname); 2591 sc->sc_dma_ok = 0; 2592 } 2593 2594 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2595 WDC_CAPABILITY_MODE; 2596 if (sc->sc_dma_ok) { 2597 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2598 sc->sc_wdcdev.irqack = pciide_irqack; 2599 } 2600 sc->sc_wdcdev.PIO_cap = 4; 2601 sc->sc_wdcdev.DMA_cap = 2; 2602 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2603 2604 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2605 sc->sc_wdcdev.nchannels = 1; 2606 2607 /* Only one channel for this chip; if we are here it's enabled */ 2608 cp = &sc->pciide_channels[0]; 2609 sc->wdc_chanarray[0] = &cp->wdc_channel; 2610 cp->name = PCIIDE_CHANNEL_NAME(0); 2611 cp->wdc_channel.channel = 0; 2612 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2613 cp->wdc_channel.ch_queue = 2614 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2615 if (cp->wdc_channel.ch_queue == NULL) { 2616 printf("%s primary channel: " 2617 "can't allocate memory for command queue", 2618 sc->sc_wdcdev.sc_dev.dv_xname); 2619 return; 2620 } 2621 printf("%s: primary channel %s to ", 2622 sc->sc_wdcdev.sc_dev.dv_xname, 2623 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2624 "configured" : "wired"); 2625 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2626 printf("native-PCI"); 2627 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2628 pciide_pci_intr); 2629 } else { 2630 printf("compatibility"); 2631 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2632 &cmdsize, &ctlsize); 2633 } 2634 printf(" mode\n"); 2635 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2636 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2637 wdcattach(&cp->wdc_channel); 2638 if (pciide_chan_candisable(cp)) { 2639 pci_conf_write(sc->sc_pc, sc->sc_tag, 2640 PCI_COMMAND_STATUS_REG, 0); 2641 } 2642 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2643 if (cp->hw_ok == 0) 2644 return; 2645 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2646 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2647 cy693_setup_channel(&cp->wdc_channel); 2648 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2649 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2650 } 2651 2652 void 2653 cy693_setup_channel(chp) 2654 struct channel_softc *chp; 2655 { 2656 struct ata_drive_datas *drvp; 2657 int drive; 2658 u_int32_t cy_cmd_ctrl; 2659 u_int32_t idedma_ctl; 2660 struct pciide_channel *cp = (struct pciide_channel*)chp; 2661 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2662 int dma_mode = -1; 2663 2664 cy_cmd_ctrl = idedma_ctl = 0; 2665 2666 /* setup DMA if needed */ 2667 pciide_channel_dma_setup(cp); 2668 2669 for (drive = 0; drive < 2; drive++) { 2670 drvp = &chp->ch_drive[drive]; 2671 /* If no drive, skip */ 2672 if ((drvp->drive_flags & DRIVE) == 0) 2673 continue; 2674 /* add timing values, setup DMA if needed */ 2675 if (drvp->drive_flags & DRIVE_DMA) { 2676 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2677 /* use Multiword DMA */ 2678 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2679 dma_mode = drvp->DMA_mode; 2680 } 2681 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2682 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2683 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2684 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2685 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2686 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2687 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2688 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2689 } 2690 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2691 chp->ch_drive[0].DMA_mode = dma_mode; 2692 chp->ch_drive[1].DMA_mode = dma_mode; 2693 2694 if (dma_mode == -1) 2695 dma_mode = 0; 2696 2697 if (sc->sc_cy_handle != NULL) { 2698 /* Note: `multiple' is implied. */ 2699 cy82c693_write(sc->sc_cy_handle, 2700 (sc->sc_cy_compatchan == 0) ? 2701 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2702 } 2703 2704 pciide_print_modes(cp); 2705 2706 if (idedma_ctl != 0) { 2707 /* Add software bits in status register */ 2708 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2709 IDEDMA_CTL, idedma_ctl); 2710 } 2711 } 2712 2713 void 2714 sis_chip_map(sc, pa) 2715 struct pciide_softc *sc; 2716 struct pci_attach_args *pa; 2717 { 2718 struct pciide_channel *cp; 2719 int channel; 2720 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2721 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2722 pcireg_t rev = PCI_REVISION(pa->pa_class); 2723 bus_size_t cmdsize, ctlsize; 2724 pcitag_t pchb_tag; 2725 pcireg_t pchb_id, pchb_class; 2726 2727 if (pciide_chipen(sc, pa) == 0) 2728 return; 2729 printf("%s: bus-master DMA support present", 2730 sc->sc_wdcdev.sc_dev.dv_xname); 2731 pciide_mapreg_dma(sc, pa); 2732 printf("\n"); 2733 2734 /* get a PCI tag for the host bridge (function 0 of the same device) */ 2735 pchb_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 2736 /* and read ID and rev of the ISA bridge */ 2737 pchb_id = pci_conf_read(sc->sc_pc, pchb_tag, PCI_ID_REG); 2738 pchb_class = pci_conf_read(sc->sc_pc, pchb_tag, PCI_CLASS_REG); 2739 2740 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2741 WDC_CAPABILITY_MODE; 2742 if (sc->sc_dma_ok) { 2743 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2744 sc->sc_wdcdev.irqack = pciide_irqack; 2745 /* 2746 * controllers associated to a rev 0x2 530 Host to PCI Bridge 2747 * have problems with UDMA (info provided by Christos) 2748 */ 2749 if (rev >= 0xd0 && 2750 (PCI_PRODUCT(pchb_id) != PCI_PRODUCT_SIS_530HB || 2751 PCI_REVISION(pchb_class) >= 0x03)) 2752 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2753 } 2754 2755 sc->sc_wdcdev.PIO_cap = 4; 2756 sc->sc_wdcdev.DMA_cap = 2; 2757 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2758 sc->sc_wdcdev.UDMA_cap = 2; 2759 sc->sc_wdcdev.set_modes = sis_setup_channel; 2760 2761 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2762 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2763 2764 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2765 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2766 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2767 2768 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2769 cp = &sc->pciide_channels[channel]; 2770 if (pciide_chansetup(sc, channel, interface) == 0) 2771 continue; 2772 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2773 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2774 printf("%s: %s channel ignored (disabled)\n", 2775 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2776 continue; 2777 } 2778 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2779 pciide_pci_intr); 2780 if (cp->hw_ok == 0) 2781 continue; 2782 if (pciide_chan_candisable(cp)) { 2783 if (channel == 0) 2784 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2785 else 2786 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2787 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2788 sis_ctr0); 2789 } 2790 pciide_map_compat_intr(pa, cp, channel, interface); 2791 if (cp->hw_ok == 0) 2792 continue; 2793 sis_setup_channel(&cp->wdc_channel); 2794 } 2795 } 2796 2797 void 2798 sis_setup_channel(chp) 2799 struct channel_softc *chp; 2800 { 2801 struct ata_drive_datas *drvp; 2802 int drive; 2803 u_int32_t sis_tim; 2804 u_int32_t idedma_ctl; 2805 struct pciide_channel *cp = (struct pciide_channel*)chp; 2806 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2807 2808 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2809 "channel %d 0x%x\n", chp->channel, 2810 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2811 DEBUG_PROBE); 2812 sis_tim = 0; 2813 idedma_ctl = 0; 2814 /* setup DMA if needed */ 2815 pciide_channel_dma_setup(cp); 2816 2817 for (drive = 0; drive < 2; drive++) { 2818 drvp = &chp->ch_drive[drive]; 2819 /* If no drive, skip */ 2820 if ((drvp->drive_flags & DRIVE) == 0) 2821 continue; 2822 /* add timing values, setup DMA if needed */ 2823 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2824 (drvp->drive_flags & DRIVE_UDMA) == 0) 2825 goto pio; 2826 2827 if (drvp->drive_flags & DRIVE_UDMA) { 2828 /* use Ultra/DMA */ 2829 drvp->drive_flags &= ~DRIVE_DMA; 2830 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2831 SIS_TIM_UDMA_TIME_OFF(drive); 2832 sis_tim |= SIS_TIM_UDMA_EN(drive); 2833 } else { 2834 /* 2835 * use Multiword DMA 2836 * Timings will be used for both PIO and DMA, 2837 * so adjust DMA mode if needed 2838 */ 2839 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2840 drvp->PIO_mode = drvp->DMA_mode + 2; 2841 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2842 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2843 drvp->PIO_mode - 2 : 0; 2844 if (drvp->DMA_mode == 0) 2845 drvp->PIO_mode = 0; 2846 } 2847 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2848 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2849 SIS_TIM_ACT_OFF(drive); 2850 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2851 SIS_TIM_REC_OFF(drive); 2852 } 2853 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2854 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2855 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2856 if (idedma_ctl != 0) { 2857 /* Add software bits in status register */ 2858 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2859 IDEDMA_CTL, idedma_ctl); 2860 } 2861 pciide_print_modes(cp); 2862 } 2863 2864 void 2865 acer_chip_map(sc, pa) 2866 struct pciide_softc *sc; 2867 struct pci_attach_args *pa; 2868 { 2869 struct pciide_channel *cp; 2870 int channel; 2871 pcireg_t cr, interface; 2872 bus_size_t cmdsize, ctlsize; 2873 pcireg_t rev = PCI_REVISION(pa->pa_class); 2874 2875 if (pciide_chipen(sc, pa) == 0) 2876 return; 2877 printf("%s: bus-master DMA support present", 2878 sc->sc_wdcdev.sc_dev.dv_xname); 2879 pciide_mapreg_dma(sc, pa); 2880 printf("\n"); 2881 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2882 WDC_CAPABILITY_MODE; 2883 if (sc->sc_dma_ok) { 2884 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 2885 if (rev >= 0x20) 2886 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2887 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2888 sc->sc_wdcdev.irqack = pciide_irqack; 2889 } 2890 2891 sc->sc_wdcdev.PIO_cap = 4; 2892 sc->sc_wdcdev.DMA_cap = 2; 2893 sc->sc_wdcdev.UDMA_cap = 2; 2894 sc->sc_wdcdev.set_modes = acer_setup_channel; 2895 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2896 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2897 2898 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2899 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2900 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2901 2902 /* Enable "microsoft register bits" R/W. */ 2903 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2904 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2905 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2906 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2907 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2908 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2909 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2910 ~ACER_CHANSTATUSREGS_RO); 2911 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2912 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2913 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2914 /* Don't use cr, re-read the real register content instead */ 2915 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2916 PCI_CLASS_REG)); 2917 2918 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2919 cp = &sc->pciide_channels[channel]; 2920 if (pciide_chansetup(sc, channel, interface) == 0) 2921 continue; 2922 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2923 printf("%s: %s channel ignored (disabled)\n", 2924 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2925 continue; 2926 } 2927 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2928 acer_pci_intr); 2929 if (cp->hw_ok == 0) 2930 continue; 2931 if (pciide_chan_candisable(cp)) { 2932 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2933 pci_conf_write(sc->sc_pc, sc->sc_tag, 2934 PCI_CLASS_REG, cr); 2935 } 2936 pciide_map_compat_intr(pa, cp, channel, interface); 2937 acer_setup_channel(&cp->wdc_channel); 2938 } 2939 } 2940 2941 void 2942 acer_setup_channel(chp) 2943 struct channel_softc *chp; 2944 { 2945 struct ata_drive_datas *drvp; 2946 int drive; 2947 u_int32_t acer_fifo_udma; 2948 u_int32_t idedma_ctl; 2949 struct pciide_channel *cp = (struct pciide_channel*)chp; 2950 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2951 2952 idedma_ctl = 0; 2953 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2954 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2955 acer_fifo_udma), DEBUG_PROBE); 2956 /* setup DMA if needed */ 2957 pciide_channel_dma_setup(cp); 2958 2959 for (drive = 0; drive < 2; drive++) { 2960 drvp = &chp->ch_drive[drive]; 2961 /* If no drive, skip */ 2962 if ((drvp->drive_flags & DRIVE) == 0) 2963 continue; 2964 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2965 "channel %d drive %d 0x%x\n", chp->channel, drive, 2966 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2967 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2968 /* clear FIFO/DMA mode */ 2969 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2970 ACER_UDMA_EN(chp->channel, drive) | 2971 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2972 2973 /* add timing values, setup DMA if needed */ 2974 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2975 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2976 acer_fifo_udma |= 2977 ACER_FTH_OPL(chp->channel, drive, 0x1); 2978 goto pio; 2979 } 2980 2981 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2982 if (drvp->drive_flags & DRIVE_UDMA) { 2983 /* use Ultra/DMA */ 2984 drvp->drive_flags &= ~DRIVE_DMA; 2985 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2986 acer_fifo_udma |= 2987 ACER_UDMA_TIM(chp->channel, drive, 2988 acer_udma[drvp->UDMA_mode]); 2989 } else { 2990 /* 2991 * use Multiword DMA 2992 * Timings will be used for both PIO and DMA, 2993 * so adjust DMA mode if needed 2994 */ 2995 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2996 drvp->PIO_mode = drvp->DMA_mode + 2; 2997 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2998 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2999 drvp->PIO_mode - 2 : 0; 3000 if (drvp->DMA_mode == 0) 3001 drvp->PIO_mode = 0; 3002 } 3003 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3004 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 3005 ACER_IDETIM(chp->channel, drive), 3006 acer_pio[drvp->PIO_mode]); 3007 } 3008 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 3009 acer_fifo_udma), DEBUG_PROBE); 3010 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 3011 if (idedma_ctl != 0) { 3012 /* Add software bits in status register */ 3013 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3014 IDEDMA_CTL, idedma_ctl); 3015 } 3016 pciide_print_modes(cp); 3017 } 3018 3019 int 3020 acer_pci_intr(arg) 3021 void *arg; 3022 { 3023 struct pciide_softc *sc = arg; 3024 struct pciide_channel *cp; 3025 struct channel_softc *wdc_cp; 3026 int i, rv, crv; 3027 u_int32_t chids; 3028 3029 rv = 0; 3030 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 3031 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3032 cp = &sc->pciide_channels[i]; 3033 wdc_cp = &cp->wdc_channel; 3034 /* If a compat channel skip. */ 3035 if (cp->compat) 3036 continue; 3037 if (chids & ACER_CHIDS_INT(i)) { 3038 crv = wdcintr(wdc_cp); 3039 if (crv == 0) 3040 printf("%s:%d: bogus intr\n", 3041 sc->sc_wdcdev.sc_dev.dv_xname, i); 3042 else 3043 rv = 1; 3044 } 3045 } 3046 return rv; 3047 } 3048 3049 void 3050 hpt_chip_map(sc, pa) 3051 struct pciide_softc *sc; 3052 struct pci_attach_args *pa; 3053 { 3054 struct pciide_channel *cp; 3055 int i, compatchan, revision; 3056 pcireg_t interface; 3057 bus_size_t cmdsize, ctlsize; 3058 3059 if (pciide_chipen(sc, pa) == 0) 3060 return; 3061 revision = PCI_REVISION(pa->pa_class); 3062 printf(": Triones/Highpoint "); 3063 if (revision == HPT370_REV) 3064 printf("HPT370 IDE Controller\n"); 3065 else if (revision == HPT370A_REV) 3066 printf("HPT370A IDE Controller\n"); 3067 else if (revision == HPT366_REV) 3068 printf("HPT366 IDE Controller\n"); 3069 else 3070 printf("unknown HPT IDE controller rev %d\n", revision); 3071 3072 /* 3073 * when the chip is in native mode it identifies itself as a 3074 * 'misc mass storage'. Fake interface in this case. 3075 */ 3076 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3077 interface = PCI_INTERFACE(pa->pa_class); 3078 } else { 3079 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3080 PCIIDE_INTERFACE_PCI(0); 3081 if (revision == HPT370_REV || revision == HPT370A_REV) 3082 interface |= PCIIDE_INTERFACE_PCI(1); 3083 } 3084 3085 printf("%s: bus-master DMA support present", 3086 sc->sc_wdcdev.sc_dev.dv_xname); 3087 pciide_mapreg_dma(sc, pa); 3088 printf("\n"); 3089 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3090 WDC_CAPABILITY_MODE; 3091 if (sc->sc_dma_ok) { 3092 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3093 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3094 sc->sc_wdcdev.irqack = pciide_irqack; 3095 } 3096 sc->sc_wdcdev.PIO_cap = 4; 3097 sc->sc_wdcdev.DMA_cap = 2; 3098 3099 sc->sc_wdcdev.set_modes = hpt_setup_channel; 3100 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3101 if (revision == HPT366_REV) { 3102 sc->sc_wdcdev.UDMA_cap = 4; 3103 /* 3104 * The 366 has 2 PCI IDE functions, one for primary and one 3105 * for secondary. So we need to call pciide_mapregs_compat() 3106 * with the real channel 3107 */ 3108 if (pa->pa_function == 0) { 3109 compatchan = 0; 3110 } else if (pa->pa_function == 1) { 3111 compatchan = 1; 3112 } else { 3113 printf("%s: unexpected PCI function %d\n", 3114 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 3115 return; 3116 } 3117 sc->sc_wdcdev.nchannels = 1; 3118 } else { 3119 sc->sc_wdcdev.nchannels = 2; 3120 sc->sc_wdcdev.UDMA_cap = 5; 3121 } 3122 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3123 cp = &sc->pciide_channels[i]; 3124 if (sc->sc_wdcdev.nchannels > 1) { 3125 compatchan = i; 3126 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 3127 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 3128 printf("%s: %s channel ignored (disabled)\n", 3129 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3130 continue; 3131 } 3132 } 3133 if (pciide_chansetup(sc, i, interface) == 0) 3134 continue; 3135 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3136 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3137 &ctlsize, hpt_pci_intr); 3138 } else { 3139 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 3140 &cmdsize, &ctlsize); 3141 } 3142 if (cp->hw_ok == 0) 3143 return; 3144 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3145 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3146 wdcattach(&cp->wdc_channel); 3147 hpt_setup_channel(&cp->wdc_channel); 3148 } 3149 if (revision == HPT370_REV || revision == HPT370A_REV) { 3150 /* 3151 * HPT370_REV has a bit to disable interrupts, make sure 3152 * to clear it 3153 */ 3154 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 3155 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 3156 ~HPT_CSEL_IRQDIS); 3157 } 3158 return; 3159 } 3160 3161 void 3162 hpt_setup_channel(chp) 3163 struct channel_softc *chp; 3164 { 3165 struct ata_drive_datas *drvp; 3166 int drive; 3167 int cable; 3168 u_int32_t before, after; 3169 u_int32_t idedma_ctl; 3170 struct pciide_channel *cp = (struct pciide_channel*)chp; 3171 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3172 3173 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 3174 3175 /* setup DMA if needed */ 3176 pciide_channel_dma_setup(cp); 3177 3178 idedma_ctl = 0; 3179 3180 /* Per drive settings */ 3181 for (drive = 0; drive < 2; drive++) { 3182 drvp = &chp->ch_drive[drive]; 3183 /* If no drive, skip */ 3184 if ((drvp->drive_flags & DRIVE) == 0) 3185 continue; 3186 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 3187 HPT_IDETIM(chp->channel, drive)); 3188 3189 /* add timing values, setup DMA if needed */ 3190 if (drvp->drive_flags & DRIVE_UDMA) { 3191 /* use Ultra/DMA */ 3192 drvp->drive_flags &= ~DRIVE_DMA; 3193 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 3194 drvp->UDMA_mode > 2) 3195 drvp->UDMA_mode = 2; 3196 after = (sc->sc_wdcdev.nchannels == 2) ? 3197 hpt370_udma[drvp->UDMA_mode] : 3198 hpt366_udma[drvp->UDMA_mode]; 3199 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3200 } else if (drvp->drive_flags & DRIVE_DMA) { 3201 /* 3202 * use Multiword DMA. 3203 * Timings will be used for both PIO and DMA, so adjust 3204 * DMA mode if needed 3205 */ 3206 if (drvp->PIO_mode >= 3 && 3207 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3208 drvp->DMA_mode = drvp->PIO_mode - 2; 3209 } 3210 after = (sc->sc_wdcdev.nchannels == 2) ? 3211 hpt370_dma[drvp->DMA_mode] : 3212 hpt366_dma[drvp->DMA_mode]; 3213 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3214 } else { 3215 /* PIO only */ 3216 after = (sc->sc_wdcdev.nchannels == 2) ? 3217 hpt370_pio[drvp->PIO_mode] : 3218 hpt366_pio[drvp->PIO_mode]; 3219 } 3220 pci_conf_write(sc->sc_pc, sc->sc_tag, 3221 HPT_IDETIM(chp->channel, drive), after); 3222 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3223 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3224 after, before), DEBUG_PROBE); 3225 } 3226 if (idedma_ctl != 0) { 3227 /* Add software bits in status register */ 3228 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3229 IDEDMA_CTL, idedma_ctl); 3230 } 3231 pciide_print_modes(cp); 3232 } 3233 3234 int 3235 hpt_pci_intr(arg) 3236 void *arg; 3237 { 3238 struct pciide_softc *sc = arg; 3239 struct pciide_channel *cp; 3240 struct channel_softc *wdc_cp; 3241 int rv = 0; 3242 int dmastat, i, crv; 3243 3244 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3245 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3246 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3247 if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 3248 IDEDMA_CTL_INTR) 3249 continue; 3250 cp = &sc->pciide_channels[i]; 3251 wdc_cp = &cp->wdc_channel; 3252 crv = wdcintr(wdc_cp); 3253 if (crv == 0) { 3254 printf("%s:%d: bogus intr\n", 3255 sc->sc_wdcdev.sc_dev.dv_xname, i); 3256 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3257 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3258 } else 3259 rv = 1; 3260 } 3261 return rv; 3262 } 3263 3264 3265 /* Macros to test product */ 3266 #define PDC_IS_262(sc) \ 3267 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3268 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3269 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3270 #define PDC_IS_265(sc) \ 3271 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3272 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3273 3274 void 3275 pdc202xx_chip_map(sc, pa) 3276 struct pciide_softc *sc; 3277 struct pci_attach_args *pa; 3278 { 3279 struct pciide_channel *cp; 3280 int channel; 3281 pcireg_t interface, st, mode; 3282 bus_size_t cmdsize, ctlsize; 3283 3284 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3285 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3286 DEBUG_PROBE); 3287 if (pciide_chipen(sc, pa) == 0) 3288 return; 3289 3290 /* turn off RAID mode */ 3291 st &= ~PDC2xx_STATE_IDERAID; 3292 3293 /* 3294 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3295 * mode. We have to fake interface 3296 */ 3297 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3298 if (st & PDC2xx_STATE_NATIVE) 3299 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3300 3301 printf("%s: bus-master DMA support present", 3302 sc->sc_wdcdev.sc_dev.dv_xname); 3303 pciide_mapreg_dma(sc, pa); 3304 printf("\n"); 3305 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3306 WDC_CAPABILITY_MODE; 3307 if (sc->sc_dma_ok) { 3308 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3309 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3310 sc->sc_wdcdev.irqack = pciide_irqack; 3311 } 3312 sc->sc_wdcdev.PIO_cap = 4; 3313 sc->sc_wdcdev.DMA_cap = 2; 3314 if (PDC_IS_265(sc)) 3315 sc->sc_wdcdev.UDMA_cap = 5; 3316 else if (PDC_IS_262(sc)) 3317 sc->sc_wdcdev.UDMA_cap = 4; 3318 else 3319 sc->sc_wdcdev.UDMA_cap = 2; 3320 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3321 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3322 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3323 3324 /* setup failsafe defaults */ 3325 mode = 0; 3326 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3327 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3328 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3329 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3330 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3331 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3332 "initial timings 0x%x, now 0x%x\n", channel, 3333 pci_conf_read(sc->sc_pc, sc->sc_tag, 3334 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3335 DEBUG_PROBE); 3336 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3337 mode | PDC2xx_TIM_IORDYp); 3338 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3339 "initial timings 0x%x, now 0x%x\n", channel, 3340 pci_conf_read(sc->sc_pc, sc->sc_tag, 3341 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3342 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3343 mode); 3344 } 3345 3346 mode = PDC2xx_SCR_DMA; 3347 if (PDC_IS_262(sc)) { 3348 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3349 } else { 3350 /* the BIOS set it up this way */ 3351 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3352 } 3353 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3354 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3355 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3356 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3357 DEBUG_PROBE); 3358 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3359 3360 /* controller initial state register is OK even without BIOS */ 3361 /* Set DMA mode to IDE DMA compatibility */ 3362 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3363 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3364 DEBUG_PROBE); 3365 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3366 mode | 0x1); 3367 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3368 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3369 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3370 mode | 0x1); 3371 3372 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3373 cp = &sc->pciide_channels[channel]; 3374 if (pciide_chansetup(sc, channel, interface) == 0) 3375 continue; 3376 if ((st & (PDC_IS_262(sc) ? 3377 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3378 printf("%s: %s channel ignored (disabled)\n", 3379 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3380 continue; 3381 } 3382 if (PDC_IS_265(sc)) 3383 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3384 pdc20265_pci_intr); 3385 else 3386 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3387 pdc202xx_pci_intr); 3388 if (cp->hw_ok == 0) 3389 continue; 3390 if (pciide_chan_candisable(cp)) 3391 st &= ~(PDC_IS_262(sc) ? 3392 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3393 pciide_map_compat_intr(pa, cp, channel, interface); 3394 pdc202xx_setup_channel(&cp->wdc_channel); 3395 } 3396 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3397 DEBUG_PROBE); 3398 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3399 return; 3400 } 3401 3402 void 3403 pdc202xx_setup_channel(chp) 3404 struct channel_softc *chp; 3405 { 3406 struct ata_drive_datas *drvp; 3407 int drive; 3408 pcireg_t mode, st; 3409 u_int32_t idedma_ctl, scr, atapi; 3410 struct pciide_channel *cp = (struct pciide_channel*)chp; 3411 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3412 int channel = chp->channel; 3413 3414 /* setup DMA if needed */ 3415 pciide_channel_dma_setup(cp); 3416 3417 idedma_ctl = 0; 3418 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s: scr 0x%x\n", 3419 sc->sc_wdcdev.sc_dev.dv_xname, 3420 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC262_U66)), 3421 DEBUG_PROBE); 3422 3423 /* Per channel settings */ 3424 if (PDC_IS_262(sc)) { 3425 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3426 PDC262_U66); 3427 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3428 /* Trimm UDMA mode */ 3429 if ((st & PDC262_STATE_80P(channel)) != 0 || 3430 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3431 chp->ch_drive[0].UDMA_mode <= 2) || 3432 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3433 chp->ch_drive[1].UDMA_mode <= 2)) { 3434 if (chp->ch_drive[0].UDMA_mode > 2) 3435 chp->ch_drive[0].UDMA_mode = 2; 3436 if (chp->ch_drive[1].UDMA_mode > 2) 3437 chp->ch_drive[1].UDMA_mode = 2; 3438 } 3439 /* Set U66 if needed */ 3440 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3441 chp->ch_drive[0].UDMA_mode > 2) || 3442 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3443 chp->ch_drive[1].UDMA_mode > 2)) 3444 scr |= PDC262_U66_EN(channel); 3445 else 3446 scr &= ~PDC262_U66_EN(channel); 3447 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3448 PDC262_U66, scr); 3449 WDCDEBUG_PRINT(("pdc202xx_setup_channel %s:%d: ATAPI 0x%x\n", 3450 sc->sc_wdcdev.sc_dev.dv_xname, channel, 3451 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3452 PDC262_ATAPI(channel))), DEBUG_PROBE); 3453 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3454 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3455 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3456 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3457 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3458 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3459 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3460 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3461 atapi = 0; 3462 else 3463 atapi = PDC262_ATAPI_UDMA; 3464 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3465 PDC262_ATAPI(channel), atapi); 3466 } 3467 } 3468 for (drive = 0; drive < 2; drive++) { 3469 drvp = &chp->ch_drive[drive]; 3470 /* If no drive, skip */ 3471 if ((drvp->drive_flags & DRIVE) == 0) 3472 continue; 3473 mode = 0; 3474 if (drvp->drive_flags & DRIVE_UDMA) { 3475 /* use Ultra/DMA */ 3476 drvp->drive_flags &= ~DRIVE_DMA; 3477 mode = PDC2xx_TIM_SET_MB(mode, 3478 pdc2xx_udma_mb[drvp->UDMA_mode]); 3479 mode = PDC2xx_TIM_SET_MC(mode, 3480 pdc2xx_udma_mc[drvp->UDMA_mode]); 3481 drvp->drive_flags &= ~DRIVE_DMA; 3482 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3483 } else if (drvp->drive_flags & DRIVE_DMA) { 3484 mode = PDC2xx_TIM_SET_MB(mode, 3485 pdc2xx_dma_mb[drvp->DMA_mode]); 3486 mode = PDC2xx_TIM_SET_MC(mode, 3487 pdc2xx_dma_mc[drvp->DMA_mode]); 3488 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3489 } else { 3490 mode = PDC2xx_TIM_SET_MB(mode, 3491 pdc2xx_dma_mb[0]); 3492 mode = PDC2xx_TIM_SET_MC(mode, 3493 pdc2xx_dma_mc[0]); 3494 } 3495 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3496 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3497 if (drvp->drive_flags & DRIVE_ATA) 3498 mode |= PDC2xx_TIM_PRE; 3499 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3500 if (drvp->PIO_mode >= 3) { 3501 mode |= PDC2xx_TIM_IORDY; 3502 if (drive == 0) 3503 mode |= PDC2xx_TIM_IORDYp; 3504 } 3505 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3506 "timings 0x%x\n", 3507 sc->sc_wdcdev.sc_dev.dv_xname, 3508 chp->channel, drive, mode), DEBUG_PROBE); 3509 pci_conf_write(sc->sc_pc, sc->sc_tag, 3510 PDC2xx_TIM(chp->channel, drive), mode); 3511 } 3512 if (idedma_ctl != 0) { 3513 /* Add software bits in status register */ 3514 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3515 IDEDMA_CTL, idedma_ctl); 3516 } 3517 pciide_print_modes(cp); 3518 } 3519 3520 int 3521 pdc202xx_pci_intr(arg) 3522 void *arg; 3523 { 3524 struct pciide_softc *sc = arg; 3525 struct pciide_channel *cp; 3526 struct channel_softc *wdc_cp; 3527 int i, rv, crv; 3528 u_int32_t scr; 3529 3530 rv = 0; 3531 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3532 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3533 cp = &sc->pciide_channels[i]; 3534 wdc_cp = &cp->wdc_channel; 3535 /* If a compat channel skip. */ 3536 if (cp->compat) 3537 continue; 3538 if (scr & PDC2xx_SCR_INT(i)) { 3539 crv = wdcintr(wdc_cp); 3540 if (crv == 0) 3541 printf("%s:%d: bogus intr (reg 0x%x)\n", 3542 sc->sc_wdcdev.sc_dev.dv_xname, i, scr); 3543 else 3544 rv = 1; 3545 } 3546 } 3547 return rv; 3548 } 3549 3550 int 3551 pdc20265_pci_intr(arg) 3552 void *arg; 3553 { 3554 struct pciide_softc *sc = arg; 3555 struct pciide_channel *cp; 3556 struct channel_softc *wdc_cp; 3557 int i, rv, crv; 3558 u_int32_t dmastat; 3559 3560 rv = 0; 3561 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3562 cp = &sc->pciide_channels[i]; 3563 wdc_cp = &cp->wdc_channel; 3564 /* If a compat channel skip. */ 3565 if (cp->compat) 3566 continue; 3567 /* 3568 * The Ultra/100 seems to assert PDC2xx_SCR_INT * spuriously, 3569 * however it asserts INT in IDEDMA_CTL even for non-DMA ops. 3570 * So use it instead (requires 2 reg reads instead of 1, 3571 * but we can't do it another way). 3572 */ 3573 dmastat = bus_space_read_1(sc->sc_dma_iot, 3574 sc->sc_dma_ioh, IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3575 if((dmastat & IDEDMA_CTL_INTR) == 0) 3576 continue; 3577 crv = wdcintr(wdc_cp); 3578 if (crv == 0) 3579 printf("%s:%d: bogus intr\n", 3580 sc->sc_wdcdev.sc_dev.dv_xname, i); 3581 else 3582 rv = 1; 3583 } 3584 return rv; 3585 } 3586 3587 void 3588 opti_chip_map(sc, pa) 3589 struct pciide_softc *sc; 3590 struct pci_attach_args *pa; 3591 { 3592 struct pciide_channel *cp; 3593 bus_size_t cmdsize, ctlsize; 3594 pcireg_t interface; 3595 u_int8_t init_ctrl; 3596 int channel; 3597 3598 if (pciide_chipen(sc, pa) == 0) 3599 return; 3600 printf("%s: bus-master DMA support present", 3601 sc->sc_wdcdev.sc_dev.dv_xname); 3602 3603 /* 3604 * XXXSCW: 3605 * There seem to be a couple of buggy revisions/implementations 3606 * of the OPTi pciide chipset. This kludge seems to fix one of 3607 * the reported problems (PR/11644) but still fails for the 3608 * other (PR/13151), although the latter may be due to other 3609 * issues too... 3610 */ 3611 if (PCI_REVISION(pa->pa_class) <= 0x12) { 3612 printf(" but disabled due to chip rev. <= 0x12"); 3613 sc->sc_dma_ok = 0; 3614 sc->sc_wdcdev.cap = 0; 3615 } else { 3616 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32; 3617 pciide_mapreg_dma(sc, pa); 3618 } 3619 printf("\n"); 3620 3621 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE; 3622 sc->sc_wdcdev.PIO_cap = 4; 3623 if (sc->sc_dma_ok) { 3624 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3625 sc->sc_wdcdev.irqack = pciide_irqack; 3626 sc->sc_wdcdev.DMA_cap = 2; 3627 } 3628 sc->sc_wdcdev.set_modes = opti_setup_channel; 3629 3630 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3631 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3632 3633 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3634 OPTI_REG_INIT_CONTROL); 3635 3636 interface = PCI_INTERFACE(pa->pa_class); 3637 3638 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3639 cp = &sc->pciide_channels[channel]; 3640 if (pciide_chansetup(sc, channel, interface) == 0) 3641 continue; 3642 if (channel == 1 && 3643 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3644 printf("%s: %s channel ignored (disabled)\n", 3645 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3646 continue; 3647 } 3648 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3649 pciide_pci_intr); 3650 if (cp->hw_ok == 0) 3651 continue; 3652 pciide_map_compat_intr(pa, cp, channel, interface); 3653 if (cp->hw_ok == 0) 3654 continue; 3655 opti_setup_channel(&cp->wdc_channel); 3656 } 3657 } 3658 3659 void 3660 opti_setup_channel(chp) 3661 struct channel_softc *chp; 3662 { 3663 struct ata_drive_datas *drvp; 3664 struct pciide_channel *cp = (struct pciide_channel*)chp; 3665 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3666 int drive, spd; 3667 int mode[2]; 3668 u_int8_t rv, mr; 3669 3670 /* 3671 * The `Delay' and `Address Setup Time' fields of the 3672 * Miscellaneous Register are always zero initially. 3673 */ 3674 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3675 mr &= ~(OPTI_MISC_DELAY_MASK | 3676 OPTI_MISC_ADDR_SETUP_MASK | 3677 OPTI_MISC_INDEX_MASK); 3678 3679 /* Prime the control register before setting timing values */ 3680 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3681 3682 /* Determine the clockrate of the PCIbus the chip is attached to */ 3683 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3684 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3685 3686 /* setup DMA if needed */ 3687 pciide_channel_dma_setup(cp); 3688 3689 for (drive = 0; drive < 2; drive++) { 3690 drvp = &chp->ch_drive[drive]; 3691 /* If no drive, skip */ 3692 if ((drvp->drive_flags & DRIVE) == 0) { 3693 mode[drive] = -1; 3694 continue; 3695 } 3696 3697 if ((drvp->drive_flags & DRIVE_DMA)) { 3698 /* 3699 * Timings will be used for both PIO and DMA, 3700 * so adjust DMA mode if needed 3701 */ 3702 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3703 drvp->PIO_mode = drvp->DMA_mode + 2; 3704 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3705 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3706 drvp->PIO_mode - 2 : 0; 3707 if (drvp->DMA_mode == 0) 3708 drvp->PIO_mode = 0; 3709 3710 mode[drive] = drvp->DMA_mode + 5; 3711 } else 3712 mode[drive] = drvp->PIO_mode; 3713 3714 if (drive && mode[0] >= 0 && 3715 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3716 /* 3717 * Can't have two drives using different values 3718 * for `Address Setup Time'. 3719 * Slow down the faster drive to compensate. 3720 */ 3721 int d = (opti_tim_as[spd][mode[0]] > 3722 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3723 3724 mode[d] = mode[1-d]; 3725 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3726 chp->ch_drive[d].DMA_mode = 0; 3727 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3728 } 3729 } 3730 3731 for (drive = 0; drive < 2; drive++) { 3732 int m; 3733 if ((m = mode[drive]) < 0) 3734 continue; 3735 3736 /* Set the Address Setup Time and select appropriate index */ 3737 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3738 rv |= OPTI_MISC_INDEX(drive); 3739 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3740 3741 /* Set the pulse width and recovery timing parameters */ 3742 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3743 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3744 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3745 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3746 3747 /* Set the Enhanced Mode register appropriately */ 3748 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3749 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3750 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3751 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3752 } 3753 3754 /* Finally, enable the timings */ 3755 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3756 3757 pciide_print_modes(cp); 3758 } 3759 3760 #define ACARD_IS_850(sc) \ 3761 ((sc)->sc_pp->ide_product == PCI_PRODUCT_ACARD_ATP850U) 3762 3763 void 3764 acard_chip_map(sc, pa) 3765 struct pciide_softc *sc; 3766 struct pci_attach_args *pa; 3767 { 3768 struct pciide_channel *cp; 3769 int i; 3770 pcireg_t interface; 3771 bus_size_t cmdsize, ctlsize; 3772 3773 if (pciide_chipen(sc, pa) == 0) 3774 return; 3775 3776 /* 3777 * when the chip is in native mode it identifies itself as a 3778 * 'misc mass storage'. Fake interface in this case. 3779 */ 3780 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 3781 interface = PCI_INTERFACE(pa->pa_class); 3782 } else { 3783 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 3784 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3785 } 3786 3787 printf("%s: bus-master DMA support present", 3788 sc->sc_wdcdev.sc_dev.dv_xname); 3789 pciide_mapreg_dma(sc, pa); 3790 printf("\n"); 3791 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3792 WDC_CAPABILITY_MODE; 3793 3794 if (sc->sc_dma_ok) { 3795 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3796 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3797 sc->sc_wdcdev.irqack = pciide_irqack; 3798 } 3799 sc->sc_wdcdev.PIO_cap = 4; 3800 sc->sc_wdcdev.DMA_cap = 2; 3801 sc->sc_wdcdev.UDMA_cap = ACARD_IS_850(sc) ? 2 : 4; 3802 3803 sc->sc_wdcdev.set_modes = acard_setup_channel; 3804 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3805 sc->sc_wdcdev.nchannels = 2; 3806 3807 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3808 cp = &sc->pciide_channels[i]; 3809 if (pciide_chansetup(sc, i, interface) == 0) 3810 continue; 3811 if (interface & PCIIDE_INTERFACE_PCI(i)) { 3812 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 3813 &ctlsize, pciide_pci_intr); 3814 } else { 3815 cp->hw_ok = pciide_mapregs_compat(pa, cp, i, 3816 &cmdsize, &ctlsize); 3817 } 3818 if (cp->hw_ok == 0) 3819 return; 3820 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 3821 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 3822 wdcattach(&cp->wdc_channel); 3823 acard_setup_channel(&cp->wdc_channel); 3824 } 3825 if (!ACARD_IS_850(sc)) { 3826 u_int32_t reg; 3827 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL); 3828 reg &= ~ATP860_CTRL_INT; 3829 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, reg); 3830 } 3831 } 3832 3833 void 3834 acard_setup_channel(chp) 3835 struct channel_softc *chp; 3836 { 3837 struct ata_drive_datas *drvp; 3838 struct pciide_channel *cp = (struct pciide_channel*)chp; 3839 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3840 int channel = chp->channel; 3841 int drive; 3842 u_int32_t idetime, udma_mode; 3843 u_int32_t idedma_ctl; 3844 3845 /* setup DMA if needed */ 3846 pciide_channel_dma_setup(cp); 3847 3848 if (ACARD_IS_850(sc)) { 3849 idetime = 0; 3850 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP850_UDMA); 3851 udma_mode &= ~ATP850_UDMA_MASK(channel); 3852 } else { 3853 idetime = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_IDETIME); 3854 idetime &= ~ATP860_SETTIME_MASK(channel); 3855 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, ATP860_UDMA); 3856 udma_mode &= ~ATP860_UDMA_MASK(channel); 3857 3858 /* check 80 pins cable */ 3859 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA) || 3860 (chp->ch_drive[1].drive_flags & DRIVE_UDMA)) { 3861 if (pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 3862 & ATP860_CTRL_80P(chp->channel)) { 3863 if (chp->ch_drive[0].UDMA_mode > 2) 3864 chp->ch_drive[0].UDMA_mode = 2; 3865 if (chp->ch_drive[1].UDMA_mode > 2) 3866 chp->ch_drive[1].UDMA_mode = 2; 3867 } 3868 } 3869 } 3870 3871 idedma_ctl = 0; 3872 3873 /* Per drive settings */ 3874 for (drive = 0; drive < 2; drive++) { 3875 drvp = &chp->ch_drive[drive]; 3876 /* If no drive, skip */ 3877 if ((drvp->drive_flags & DRIVE) == 0) 3878 continue; 3879 /* add timing values, setup DMA if needed */ 3880 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 3881 (drvp->drive_flags & DRIVE_UDMA)) { 3882 /* use Ultra/DMA */ 3883 if (ACARD_IS_850(sc)) { 3884 idetime |= ATP850_SETTIME(drive, 3885 acard_act_udma[drvp->UDMA_mode], 3886 acard_rec_udma[drvp->UDMA_mode]); 3887 udma_mode |= ATP850_UDMA_MODE(channel, drive, 3888 acard_udma_conf[drvp->UDMA_mode]); 3889 } else { 3890 idetime |= ATP860_SETTIME(channel, drive, 3891 acard_act_udma[drvp->UDMA_mode], 3892 acard_rec_udma[drvp->UDMA_mode]); 3893 udma_mode |= ATP860_UDMA_MODE(channel, drive, 3894 acard_udma_conf[drvp->UDMA_mode]); 3895 } 3896 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3897 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 3898 (drvp->drive_flags & DRIVE_DMA)) { 3899 /* use Multiword DMA */ 3900 drvp->drive_flags &= ~DRIVE_UDMA; 3901 if (ACARD_IS_850(sc)) { 3902 idetime |= ATP850_SETTIME(drive, 3903 acard_act_dma[drvp->DMA_mode], 3904 acard_rec_dma[drvp->DMA_mode]); 3905 } else { 3906 idetime |= ATP860_SETTIME(channel, drive, 3907 acard_act_dma[drvp->DMA_mode], 3908 acard_rec_dma[drvp->DMA_mode]); 3909 } 3910 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3911 } else { 3912 /* PIO only */ 3913 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 3914 if (ACARD_IS_850(sc)) { 3915 idetime |= ATP850_SETTIME(drive, 3916 acard_act_pio[drvp->PIO_mode], 3917 acard_rec_pio[drvp->PIO_mode]); 3918 } else { 3919 idetime |= ATP860_SETTIME(channel, drive, 3920 acard_act_pio[drvp->PIO_mode], 3921 acard_rec_pio[drvp->PIO_mode]); 3922 } 3923 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL, 3924 pci_conf_read(sc->sc_pc, sc->sc_tag, ATP8x0_CTRL) 3925 | ATP8x0_CTRL_EN(channel)); 3926 } 3927 } 3928 3929 if (idedma_ctl != 0) { 3930 /* Add software bits in status register */ 3931 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3932 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 3933 } 3934 pciide_print_modes(cp); 3935 3936 if (ACARD_IS_850(sc)) { 3937 pci_conf_write(sc->sc_pc, sc->sc_tag, 3938 ATP850_IDETIME(channel), idetime); 3939 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP850_UDMA, udma_mode); 3940 } else { 3941 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_IDETIME, idetime); 3942 pci_conf_write(sc->sc_pc, sc->sc_tag, ATP860_UDMA, udma_mode); 3943 } 3944 } 3945 3946 int 3947 acard_pci_intr(arg) 3948 void *arg; 3949 { 3950 struct pciide_softc *sc = arg; 3951 struct pciide_channel *cp; 3952 struct channel_softc *wdc_cp; 3953 int rv = 0; 3954 int dmastat, i, crv; 3955 3956 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3957 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3958 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3959 if ((dmastat & IDEDMA_CTL_INTR) == 0) 3960 continue; 3961 cp = &sc->pciide_channels[i]; 3962 wdc_cp = &cp->wdc_channel; 3963 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) { 3964 (void)wdcintr(wdc_cp); 3965 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3966 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3967 continue; 3968 } 3969 crv = wdcintr(wdc_cp); 3970 if (crv == 0) 3971 printf("%s:%d: bogus intr\n", 3972 sc->sc_wdcdev.sc_dev.dv_xname, i); 3973 else if (crv == 1) 3974 rv = 1; 3975 else if (rv == 0) 3976 rv = crv; 3977 } 3978 return rv; 3979 } 3980
Indexes created Thu Oct 02 10:09:58 GMT 2025