pciide.c revision 1.68.2.4
1 /* $NetBSD: pciide.c,v 1.68.2.4 2000/07/05 18:10:57 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <vm/vm.h> 102 #include <vm/vm_param.h> 103 #include <vm/vm_kern.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/cy82c693var.h> 121 122 /* inlines for reading/writing 8-bit PCI registers */ 123 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 124 int)); 125 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 126 int, u_int8_t)); 127 128 static __inline u_int8_t 129 pciide_pci_read(pc, pa, reg) 130 pci_chipset_tag_t pc; 131 pcitag_t pa; 132 int reg; 133 { 134 135 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 136 ((reg & 0x03) * 8) & 0xff); 137 } 138 139 static __inline void 140 pciide_pci_write(pc, pa, reg, val) 141 pci_chipset_tag_t pc; 142 pcitag_t pa; 143 int reg; 144 u_int8_t val; 145 { 146 pcireg_t pcival; 147 148 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 149 pcival &= ~(0xff << ((reg & 0x03) * 8)); 150 pcival |= (val << ((reg & 0x03) * 8)); 151 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 152 } 153 154 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 155 156 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 157 void piix_setup_channel __P((struct channel_softc*)); 158 void piix3_4_setup_channel __P((struct channel_softc*)); 159 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 160 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 161 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 162 163 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 164 void amd756_setup_channel __P((struct channel_softc*)); 165 166 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 167 void apollo_setup_channel __P((struct channel_softc*)); 168 169 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 170 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void cmd0643_9_setup_channel __P((struct channel_softc*)); 172 void cmd_channel_map __P((struct pci_attach_args *, 173 struct pciide_softc *, int)); 174 int cmd_pci_intr __P((void *)); 175 void cmd648_9_irqack __P((struct channel_softc *)); 176 177 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void cy693_setup_channel __P((struct channel_softc*)); 179 180 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void sis_setup_channel __P((struct channel_softc*)); 182 183 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 184 void acer_setup_channel __P((struct channel_softc*)); 185 int acer_pci_intr __P((void *)); 186 187 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 188 void pdc202xx_setup_channel __P((struct channel_softc*)); 189 int pdc202xx_pci_intr __P((void *)); 190 191 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 192 void opti_setup_channel __P((struct channel_softc*)); 193 194 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 195 void hpt_setup_channel __P((struct channel_softc*)); 196 int hpt_pci_intr __P((void *)); 197 198 void pciide_channel_dma_setup __P((struct pciide_channel *)); 199 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 200 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 201 void pciide_dma_start __P((void*, int, int)); 202 int pciide_dma_finish __P((void*, int, int, int)); 203 void pciide_irqack __P((struct channel_softc *)); 204 void pciide_print_modes __P((struct pciide_channel *)); 205 206 struct pciide_product_desc { 207 u_int32_t ide_product; 208 int ide_flags; 209 const char *ide_name; 210 /* map and setup chip, probe drives */ 211 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 212 }; 213 214 /* Flags for ide_flags */ 215 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 216 217 /* Default product description for devices not known from this controller */ 218 const struct pciide_product_desc default_product_desc = { 219 0, 220 0, 221 "Generic PCI IDE controller", 222 default_chip_map, 223 }; 224 225 const struct pciide_product_desc pciide_intel_products[] = { 226 { PCI_PRODUCT_INTEL_82092AA, 227 0, 228 "Intel 82092AA IDE controller", 229 default_chip_map, 230 }, 231 { PCI_PRODUCT_INTEL_82371FB_IDE, 232 0, 233 "Intel 82371FB IDE controller (PIIX)", 234 piix_chip_map, 235 }, 236 { PCI_PRODUCT_INTEL_82371SB_IDE, 237 0, 238 "Intel 82371SB IDE Interface (PIIX3)", 239 piix_chip_map, 240 }, 241 { PCI_PRODUCT_INTEL_82371AB_IDE, 242 0, 243 "Intel 82371AB IDE controller (PIIX4)", 244 piix_chip_map, 245 }, 246 { PCI_PRODUCT_INTEL_82801AA_IDE, 247 0, 248 "Intel 82801AA IDE Controller (ICH)", 249 piix_chip_map, 250 }, 251 { PCI_PRODUCT_INTEL_82801AB_IDE, 252 0, 253 "Intel 82801AB IDE Controller (ICH0)", 254 piix_chip_map, 255 }, 256 { 0, 257 0, 258 NULL, 259 } 260 }; 261 262 const struct pciide_product_desc pciide_amd_products[] = { 263 { PCI_PRODUCT_AMD_PBC756_IDE, 264 0, 265 "Advanced Micro Devices AMD756 IDE Controller", 266 amd756_chip_map 267 }, 268 { 0, 269 0, 270 NULL, 271 } 272 }; 273 274 const struct pciide_product_desc pciide_cmd_products[] = { 275 { PCI_PRODUCT_CMDTECH_640, 276 0, 277 "CMD Technology PCI0640", 278 cmd_chip_map 279 }, 280 { PCI_PRODUCT_CMDTECH_643, 281 0, 282 "CMD Technology PCI0643", 283 cmd0643_9_chip_map, 284 }, 285 { PCI_PRODUCT_CMDTECH_646, 286 0, 287 "CMD Technology PCI0646", 288 cmd0643_9_chip_map, 289 }, 290 { PCI_PRODUCT_CMDTECH_648, 291 IDE_PCI_CLASS_OVERRIDE, 292 "CMD Technology PCI0648", 293 cmd0643_9_chip_map, 294 }, 295 { PCI_PRODUCT_CMDTECH_649, 296 IDE_PCI_CLASS_OVERRIDE, 297 "CMD Technology PCI0649", 298 cmd0643_9_chip_map, 299 }, 300 { 0, 301 0, 302 NULL, 303 } 304 }; 305 306 const struct pciide_product_desc pciide_via_products[] = { 307 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 308 0, 309 "VIA Tech VT82C586 IDE Controller", 310 apollo_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 313 0, 314 "VIA Tech VT82C586A IDE Controller", 315 apollo_chip_map, 316 }, 317 { 0, 318 0, 319 NULL, 320 } 321 }; 322 323 const struct pciide_product_desc pciide_cypress_products[] = { 324 { PCI_PRODUCT_CONTAQ_82C693, 325 0, 326 "Cypress 82C693 IDE Controller", 327 cy693_chip_map, 328 }, 329 { 0, 330 0, 331 NULL, 332 } 333 }; 334 335 const struct pciide_product_desc pciide_sis_products[] = { 336 { PCI_PRODUCT_SIS_5597_IDE, 337 0, 338 "Silicon Integrated System 5597/5598 IDE controller", 339 sis_chip_map, 340 }, 341 { 0, 342 0, 343 NULL, 344 } 345 }; 346 347 const struct pciide_product_desc pciide_acer_products[] = { 348 { PCI_PRODUCT_ALI_M5229, 349 0, 350 "Acer Labs M5229 UDMA IDE Controller", 351 acer_chip_map, 352 }, 353 { 0, 354 0, 355 NULL, 356 } 357 }; 358 359 const struct pciide_product_desc pciide_promise_products[] = { 360 { PCI_PRODUCT_PROMISE_ULTRA33, 361 IDE_PCI_CLASS_OVERRIDE, 362 "Promise Ultra33/ATA Bus Master IDE Accelerator", 363 pdc202xx_chip_map, 364 }, 365 { PCI_PRODUCT_PROMISE_ULTRA66, 366 IDE_PCI_CLASS_OVERRIDE, 367 "Promise Ultra66/ATA Bus Master IDE Accelerator", 368 pdc202xx_chip_map, 369 }, 370 { 0, 371 0, 372 NULL, 373 } 374 }; 375 376 const struct pciide_product_desc pciide_opti_products[] = { 377 { PCI_PRODUCT_OPTI_82C621, 378 0, 379 "OPTi 82c621 PCI IDE controller", 380 opti_chip_map, 381 }, 382 { PCI_PRODUCT_OPTI_82C568, 383 0, 384 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 385 opti_chip_map, 386 }, 387 { PCI_PRODUCT_OPTI_82D568, 388 0, 389 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 390 opti_chip_map, 391 }, 392 { 0, 393 0, 394 NULL, 395 } 396 }; 397 398 const struct pciide_product_desc pciide_triones_products[] = { 399 { PCI_PRODUCT_TRIONES_HPT366, 400 IDE_PCI_CLASS_OVERRIDE, 401 "Triones/Highpoint HPT366/370 IDE Controller", 402 hpt_chip_map, 403 }, 404 { 0, 405 0, 406 NULL, 407 } 408 }; 409 410 struct pciide_vendor_desc { 411 u_int32_t ide_vendor; 412 const struct pciide_product_desc *ide_products; 413 }; 414 415 const struct pciide_vendor_desc pciide_vendors[] = { 416 { PCI_VENDOR_INTEL, pciide_intel_products }, 417 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 418 { PCI_VENDOR_VIATECH, pciide_via_products }, 419 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 420 { PCI_VENDOR_SIS, pciide_sis_products }, 421 { PCI_VENDOR_ALI, pciide_acer_products }, 422 { PCI_VENDOR_PROMISE, pciide_promise_products }, 423 { PCI_VENDOR_AMD, pciide_amd_products }, 424 { PCI_VENDOR_OPTI, pciide_opti_products }, 425 { PCI_VENDOR_TRIONES, pciide_triones_products }, 426 { 0, NULL } 427 }; 428 429 /* options passed via the 'flags' config keyword */ 430 #define PCIIDE_OPTIONS_DMA 0x01 431 432 int pciide_match __P((struct device *, struct cfdata *, void *)); 433 void pciide_attach __P((struct device *, struct device *, void *)); 434 435 struct cfattach pciide_ca = { 436 sizeof(struct pciide_softc), pciide_match, pciide_attach 437 }; 438 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 439 int pciide_mapregs_compat __P(( struct pci_attach_args *, 440 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 441 int pciide_mapregs_native __P((struct pci_attach_args *, 442 struct pciide_channel *, bus_size_t *, bus_size_t *, 443 int (*pci_intr) __P((void *)))); 444 void pciide_mapreg_dma __P((struct pciide_softc *, 445 struct pci_attach_args *)); 446 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 447 void pciide_mapchan __P((struct pci_attach_args *, 448 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 449 int (*pci_intr) __P((void *)))); 450 int pciide_chan_candisable __P((struct pciide_channel *)); 451 void pciide_map_compat_intr __P(( struct pci_attach_args *, 452 struct pciide_channel *, int, int)); 453 int pciide_print __P((void *, const char *pnp)); 454 int pciide_compat_intr __P((void *)); 455 int pciide_pci_intr __P((void *)); 456 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 457 458 const struct pciide_product_desc * 459 pciide_lookup_product(id) 460 u_int32_t id; 461 { 462 const struct pciide_product_desc *pp; 463 const struct pciide_vendor_desc *vp; 464 465 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 466 if (PCI_VENDOR(id) == vp->ide_vendor) 467 break; 468 469 if ((pp = vp->ide_products) == NULL) 470 return NULL; 471 472 for (; pp->ide_name != NULL; pp++) 473 if (PCI_PRODUCT(id) == pp->ide_product) 474 break; 475 476 if (pp->ide_name == NULL) 477 return NULL; 478 return pp; 479 } 480 481 int 482 pciide_match(parent, match, aux) 483 struct device *parent; 484 struct cfdata *match; 485 void *aux; 486 { 487 struct pci_attach_args *pa = aux; 488 const struct pciide_product_desc *pp; 489 490 /* 491 * Check the ID register to see that it's a PCI IDE controller. 492 * If it is, we assume that we can deal with it; it _should_ 493 * work in a standardized way... 494 */ 495 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 496 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 497 return (1); 498 } 499 500 /* 501 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 502 * controllers. Let see if we can deal with it anyway. 503 */ 504 pp = pciide_lookup_product(pa->pa_id); 505 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 506 return (1); 507 } 508 509 return (0); 510 } 511 512 void 513 pciide_attach(parent, self, aux) 514 struct device *parent, *self; 515 void *aux; 516 { 517 struct pci_attach_args *pa = aux; 518 pci_chipset_tag_t pc = pa->pa_pc; 519 pcitag_t tag = pa->pa_tag; 520 struct pciide_softc *sc = (struct pciide_softc *)self; 521 pcireg_t csr; 522 char devinfo[256]; 523 const char *displaydev; 524 525 sc->sc_pp = pciide_lookup_product(pa->pa_id); 526 if (sc->sc_pp == NULL) { 527 sc->sc_pp = &default_product_desc; 528 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 529 displaydev = devinfo; 530 } else 531 displaydev = sc->sc_pp->ide_name; 532 533 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 534 535 sc->sc_pc = pa->pa_pc; 536 sc->sc_tag = pa->pa_tag; 537 #ifdef WDCDEBUG 538 if (wdcdebug_pciide_mask & DEBUG_PROBE) 539 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 540 #endif 541 sc->sc_pp->chip_map(sc, pa); 542 543 if (sc->sc_dma_ok) { 544 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 545 csr |= PCI_COMMAND_MASTER_ENABLE; 546 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 547 } 548 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 549 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 550 } 551 552 /* tell wether the chip is enabled or not */ 553 int 554 pciide_chipen(sc, pa) 555 struct pciide_softc *sc; 556 struct pci_attach_args *pa; 557 { 558 pcireg_t csr; 559 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 560 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 561 PCI_COMMAND_STATUS_REG); 562 printf("%s: device disabled (at %s)\n", 563 sc->sc_wdcdev.sc_dev.dv_xname, 564 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 565 "device" : "bridge"); 566 return 0; 567 } 568 return 1; 569 } 570 571 int 572 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 573 struct pci_attach_args *pa; 574 struct pciide_channel *cp; 575 int compatchan; 576 bus_size_t *cmdsizep, *ctlsizep; 577 { 578 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 579 struct channel_softc *wdc_cp = &cp->wdc_channel; 580 581 cp->compat = 1; 582 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 583 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 584 585 wdc_cp->cmd_iot = pa->pa_iot; 586 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 587 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 588 printf("%s: couldn't map %s channel cmd regs\n", 589 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 590 return (0); 591 } 592 593 wdc_cp->ctl_iot = pa->pa_iot; 594 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 595 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 596 printf("%s: couldn't map %s channel ctl regs\n", 597 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 598 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 599 PCIIDE_COMPAT_CMD_SIZE); 600 return (0); 601 } 602 603 return (1); 604 } 605 606 int 607 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 608 struct pci_attach_args * pa; 609 struct pciide_channel *cp; 610 bus_size_t *cmdsizep, *ctlsizep; 611 int (*pci_intr) __P((void *)); 612 { 613 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 614 struct channel_softc *wdc_cp = &cp->wdc_channel; 615 const char *intrstr; 616 pci_intr_handle_t intrhandle; 617 618 cp->compat = 0; 619 620 if (sc->sc_pci_ih == NULL) { 621 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 622 pa->pa_intrline, &intrhandle) != 0) { 623 printf("%s: couldn't map native-PCI interrupt\n", 624 sc->sc_wdcdev.sc_dev.dv_xname); 625 return 0; 626 } 627 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 628 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 629 intrhandle, IPL_BIO, pci_intr, sc); 630 if (sc->sc_pci_ih != NULL) { 631 printf("%s: using %s for native-PCI interrupt\n", 632 sc->sc_wdcdev.sc_dev.dv_xname, 633 intrstr ? intrstr : "unknown interrupt"); 634 } else { 635 printf("%s: couldn't establish native-PCI interrupt", 636 sc->sc_wdcdev.sc_dev.dv_xname); 637 if (intrstr != NULL) 638 printf(" at %s", intrstr); 639 printf("\n"); 640 return 0; 641 } 642 } 643 cp->ih = sc->sc_pci_ih; 644 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 645 PCI_MAPREG_TYPE_IO, 0, 646 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 647 printf("%s: couldn't map %s channel cmd regs\n", 648 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 649 return 0; 650 } 651 652 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 653 PCI_MAPREG_TYPE_IO, 0, 654 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 655 printf("%s: couldn't map %s channel ctl regs\n", 656 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 657 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 658 return 0; 659 } 660 return (1); 661 } 662 663 void 664 pciide_mapreg_dma(sc, pa) 665 struct pciide_softc *sc; 666 struct pci_attach_args *pa; 667 { 668 pcireg_t maptype; 669 670 /* 671 * Map DMA registers 672 * 673 * Note that sc_dma_ok is the right variable to test to see if 674 * DMA can be done. If the interface doesn't support DMA, 675 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 676 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 677 * non-zero if the interface supports DMA and the registers 678 * could be mapped. 679 * 680 * XXX Note that despite the fact that the Bus Master IDE specs 681 * XXX say that "The bus master IDE function uses 16 bytes of IO 682 * XXX space," some controllers (at least the United 683 * XXX Microelectronics UM8886BF) place it in memory space. 684 */ 685 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 686 PCIIDE_REG_BUS_MASTER_DMA); 687 688 switch (maptype) { 689 case PCI_MAPREG_TYPE_IO: 690 case PCI_MAPREG_MEM_TYPE_32BIT: 691 sc->sc_dma_ok = (pci_mapreg_map(pa, 692 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 693 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 694 sc->sc_dmat = pa->pa_dmat; 695 if (sc->sc_dma_ok == 0) { 696 printf(", but unused (couldn't map registers)"); 697 } else { 698 sc->sc_wdcdev.dma_arg = sc; 699 sc->sc_wdcdev.dma_init = pciide_dma_init; 700 sc->sc_wdcdev.dma_start = pciide_dma_start; 701 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 702 } 703 break; 704 705 default: 706 sc->sc_dma_ok = 0; 707 printf(", but unsupported register maptype (0x%x)", maptype); 708 } 709 } 710 711 int 712 pciide_compat_intr(arg) 713 void *arg; 714 { 715 struct pciide_channel *cp = arg; 716 717 #ifdef DIAGNOSTIC 718 /* should only be called for a compat channel */ 719 if (cp->compat == 0) 720 panic("pciide compat intr called for non-compat chan %p\n", cp); 721 #endif 722 return (wdcintr(&cp->wdc_channel)); 723 } 724 725 int 726 pciide_pci_intr(arg) 727 void *arg; 728 { 729 struct pciide_softc *sc = arg; 730 struct pciide_channel *cp; 731 struct channel_softc *wdc_cp; 732 int i, rv, crv; 733 734 rv = 0; 735 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 736 cp = &sc->pciide_channels[i]; 737 wdc_cp = &cp->wdc_channel; 738 739 /* If a compat channel skip. */ 740 if (cp->compat) 741 continue; 742 /* if this channel not waiting for intr, skip */ 743 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 744 continue; 745 746 crv = wdcintr(wdc_cp); 747 if (crv == 0) 748 ; /* leave rv alone */ 749 else if (crv == 1) 750 rv = 1; /* claim the intr */ 751 else if (rv == 0) /* crv should be -1 in this case */ 752 rv = crv; /* if we've done no better, take it */ 753 } 754 return (rv); 755 } 756 757 void 758 pciide_channel_dma_setup(cp) 759 struct pciide_channel *cp; 760 { 761 int drive; 762 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 763 struct ata_drive_datas *drvp; 764 765 for (drive = 0; drive < 2; drive++) { 766 drvp = &cp->wdc_channel.ch_drive[drive]; 767 /* If no drive, skip */ 768 if ((drvp->drive_flags & DRIVE) == 0) 769 continue; 770 /* setup DMA if needed */ 771 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 772 (drvp->drive_flags & DRIVE_UDMA) == 0) || 773 sc->sc_dma_ok == 0) { 774 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 775 continue; 776 } 777 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 778 != 0) { 779 /* Abort DMA setup */ 780 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 781 continue; 782 } 783 } 784 } 785 786 int 787 pciide_dma_table_setup(sc, channel, drive) 788 struct pciide_softc *sc; 789 int channel, drive; 790 { 791 bus_dma_segment_t seg; 792 int error, rseg; 793 const bus_size_t dma_table_size = 794 sizeof(struct idedma_table) * NIDEDMA_TABLES; 795 struct pciide_dma_maps *dma_maps = 796 &sc->pciide_channels[channel].dma_maps[drive]; 797 798 /* If table was already allocated, just return */ 799 if (dma_maps->dma_table) 800 return 0; 801 802 /* Allocate memory for the DMA tables and map it */ 803 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 804 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 805 BUS_DMA_NOWAIT)) != 0) { 806 printf("%s:%d: unable to allocate table DMA for " 807 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 808 channel, drive, error); 809 return error; 810 } 811 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 812 dma_table_size, 813 (caddr_t *)&dma_maps->dma_table, 814 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 815 printf("%s:%d: unable to map table DMA for" 816 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 817 channel, drive, error); 818 return error; 819 } 820 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 821 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 822 seg.ds_addr), DEBUG_PROBE); 823 824 /* Create and load table DMA map for this disk */ 825 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 826 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 827 &dma_maps->dmamap_table)) != 0) { 828 printf("%s:%d: unable to create table DMA map for " 829 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 830 channel, drive, error); 831 return error; 832 } 833 if ((error = bus_dmamap_load(sc->sc_dmat, 834 dma_maps->dmamap_table, 835 dma_maps->dma_table, 836 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 837 printf("%s:%d: unable to load table DMA map for " 838 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 839 channel, drive, error); 840 return error; 841 } 842 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 843 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 844 /* Create a xfer DMA map for this drive */ 845 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 846 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 847 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 848 &dma_maps->dmamap_xfer)) != 0) { 849 printf("%s:%d: unable to create xfer DMA map for " 850 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 851 channel, drive, error); 852 return error; 853 } 854 return 0; 855 } 856 857 int 858 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 859 void *v; 860 int channel, drive; 861 void *databuf; 862 size_t datalen; 863 int flags; 864 { 865 struct pciide_softc *sc = v; 866 int error, seg; 867 struct pciide_dma_maps *dma_maps = 868 &sc->pciide_channels[channel].dma_maps[drive]; 869 870 error = bus_dmamap_load(sc->sc_dmat, 871 dma_maps->dmamap_xfer, 872 databuf, datalen, NULL, BUS_DMA_NOWAIT); 873 if (error) { 874 printf("%s:%d: unable to load xfer DMA map for" 875 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 876 channel, drive, error); 877 return error; 878 } 879 880 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 881 dma_maps->dmamap_xfer->dm_mapsize, 882 (flags & WDC_DMA_READ) ? 883 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 884 885 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 886 #ifdef DIAGNOSTIC 887 /* A segment must not cross a 64k boundary */ 888 { 889 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 890 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 891 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 892 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 893 printf("pciide_dma: segment %d physical addr 0x%lx" 894 " len 0x%lx not properly aligned\n", 895 seg, phys, len); 896 panic("pciide_dma: buf align"); 897 } 898 } 899 #endif 900 dma_maps->dma_table[seg].base_addr = 901 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 902 dma_maps->dma_table[seg].byte_count = 903 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 904 IDEDMA_BYTE_COUNT_MASK); 905 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 906 seg, le32toh(dma_maps->dma_table[seg].byte_count), 907 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 908 909 } 910 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 911 htole32(IDEDMA_BYTE_COUNT_EOT); 912 913 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 914 dma_maps->dmamap_table->dm_mapsize, 915 BUS_DMASYNC_PREWRITE); 916 917 /* Maps are ready. Start DMA function */ 918 #ifdef DIAGNOSTIC 919 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 920 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 921 dma_maps->dmamap_table->dm_segs[0].ds_addr); 922 panic("pciide_dma_init: table align"); 923 } 924 #endif 925 926 /* Clear status bits */ 927 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 928 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 929 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 930 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 931 /* Write table addr */ 932 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 933 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 934 dma_maps->dmamap_table->dm_segs[0].ds_addr); 935 /* set read/write */ 936 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 937 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 938 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 939 /* remember flags */ 940 dma_maps->dma_flags = flags; 941 return 0; 942 } 943 944 void 945 pciide_dma_start(v, channel, drive) 946 void *v; 947 int channel, drive; 948 { 949 struct pciide_softc *sc = v; 950 951 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 952 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 953 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 954 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 955 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 956 } 957 958 int 959 pciide_dma_finish(v, channel, drive, force) 960 void *v; 961 int channel, drive; 962 int force; 963 { 964 struct pciide_softc *sc = v; 965 u_int8_t status; 966 int error = 0; 967 struct pciide_dma_maps *dma_maps = 968 &sc->pciide_channels[channel].dma_maps[drive]; 969 970 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 971 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 972 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 973 DEBUG_XFERS); 974 975 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 976 return WDC_DMAST_NOIRQ; 977 978 /* stop DMA channel */ 979 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 980 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 981 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 982 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 983 984 /* Unload the map of the data buffer */ 985 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 986 dma_maps->dmamap_xfer->dm_mapsize, 987 (dma_maps->dma_flags & WDC_DMA_READ) ? 988 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 989 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 990 991 if ((status & IDEDMA_CTL_ERR) != 0) { 992 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 993 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 994 error |= WDC_DMAST_ERR; 995 } 996 997 if ((status & IDEDMA_CTL_INTR) == 0) { 998 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 999 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1000 drive, status); 1001 error |= WDC_DMAST_NOIRQ; 1002 } 1003 1004 if ((status & IDEDMA_CTL_ACT) != 0) { 1005 /* data underrun, may be a valid condition for ATAPI */ 1006 error |= WDC_DMAST_UNDER; 1007 } 1008 return error; 1009 } 1010 1011 void 1012 pciide_irqack(chp) 1013 struct channel_softc *chp; 1014 { 1015 struct pciide_channel *cp = (struct pciide_channel*)chp; 1016 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1017 1018 /* clear status bits in IDE DMA registers */ 1019 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1020 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1021 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1022 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1023 } 1024 1025 /* some common code used by several chip_map */ 1026 int 1027 pciide_chansetup(sc, channel, interface) 1028 struct pciide_softc *sc; 1029 int channel; 1030 pcireg_t interface; 1031 { 1032 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1033 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1034 cp->name = PCIIDE_CHANNEL_NAME(channel); 1035 cp->wdc_channel.channel = channel; 1036 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1037 cp->wdc_channel.ch_queue = 1038 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1039 if (cp->wdc_channel.ch_queue == NULL) { 1040 printf("%s %s channel: " 1041 "can't allocate memory for command queue", 1042 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1043 return 0; 1044 } 1045 printf("%s: %s channel %s to %s mode\n", 1046 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1047 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1048 "configured" : "wired", 1049 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1050 "native-PCI" : "compatibility"); 1051 return 1; 1052 } 1053 1054 /* some common code used by several chip channel_map */ 1055 void 1056 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1057 struct pci_attach_args *pa; 1058 struct pciide_channel *cp; 1059 pcireg_t interface; 1060 bus_size_t *cmdsizep, *ctlsizep; 1061 int (*pci_intr) __P((void *)); 1062 { 1063 struct channel_softc *wdc_cp = &cp->wdc_channel; 1064 1065 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1066 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1067 pci_intr); 1068 else 1069 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1070 wdc_cp->channel, cmdsizep, ctlsizep); 1071 1072 if (cp->hw_ok == 0) 1073 return; 1074 wdc_cp->data32iot = wdc_cp->cmd_iot; 1075 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1076 wdcattach(wdc_cp); 1077 } 1078 1079 /* 1080 * Generic code to call to know if a channel can be disabled. Return 1 1081 * if channel can be disabled, 0 if not 1082 */ 1083 int 1084 pciide_chan_candisable(cp) 1085 struct pciide_channel *cp; 1086 { 1087 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1088 struct channel_softc *wdc_cp = &cp->wdc_channel; 1089 1090 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1091 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1092 printf("%s: disabling %s channel (no drives)\n", 1093 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1094 cp->hw_ok = 0; 1095 return 1; 1096 } 1097 return 0; 1098 } 1099 1100 /* 1101 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1102 * Set hw_ok=0 on failure 1103 */ 1104 void 1105 pciide_map_compat_intr(pa, cp, compatchan, interface) 1106 struct pci_attach_args *pa; 1107 struct pciide_channel *cp; 1108 int compatchan, interface; 1109 { 1110 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1111 struct channel_softc *wdc_cp = &cp->wdc_channel; 1112 1113 if (cp->hw_ok == 0) 1114 return; 1115 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1116 return; 1117 1118 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1119 pa, compatchan, pciide_compat_intr, cp); 1120 if (cp->ih == NULL) { 1121 printf("%s: no compatibility interrupt for use by %s " 1122 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1123 cp->hw_ok = 0; 1124 } 1125 } 1126 1127 void 1128 pciide_print_modes(cp) 1129 struct pciide_channel *cp; 1130 { 1131 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1132 int drive; 1133 struct channel_softc *chp; 1134 struct ata_drive_datas *drvp; 1135 1136 chp = &cp->wdc_channel; 1137 for (drive = 0; drive < 2; drive++) { 1138 drvp = &chp->ch_drive[drive]; 1139 if ((drvp->drive_flags & DRIVE) == 0) 1140 continue; 1141 printf("%s(%s:%d:%d): using PIO mode %d", 1142 drvp->drv_softc->dv_xname, 1143 sc->sc_wdcdev.sc_dev.dv_xname, 1144 chp->channel, drive, drvp->PIO_mode); 1145 if (drvp->drive_flags & DRIVE_DMA) 1146 printf(", DMA mode %d", drvp->DMA_mode); 1147 if (drvp->drive_flags & DRIVE_UDMA) 1148 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1149 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1150 printf(" (using DMA data transfers)"); 1151 printf("\n"); 1152 } 1153 } 1154 1155 void 1156 default_chip_map(sc, pa) 1157 struct pciide_softc *sc; 1158 struct pci_attach_args *pa; 1159 { 1160 struct pciide_channel *cp; 1161 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1162 pcireg_t csr; 1163 int channel, drive; 1164 struct ata_drive_datas *drvp; 1165 u_int8_t idedma_ctl; 1166 bus_size_t cmdsize, ctlsize; 1167 char *failreason; 1168 1169 if (pciide_chipen(sc, pa) == 0) 1170 return; 1171 1172 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1173 printf("%s: bus-master DMA support present", 1174 sc->sc_wdcdev.sc_dev.dv_xname); 1175 if (sc->sc_pp == &default_product_desc && 1176 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1177 PCIIDE_OPTIONS_DMA) == 0) { 1178 printf(", but unused (no driver support)"); 1179 sc->sc_dma_ok = 0; 1180 } else { 1181 pciide_mapreg_dma(sc, pa); 1182 if (sc->sc_dma_ok != 0) 1183 printf(", used without full driver " 1184 "support"); 1185 } 1186 } else { 1187 printf("%s: hardware does not support DMA", 1188 sc->sc_wdcdev.sc_dev.dv_xname); 1189 sc->sc_dma_ok = 0; 1190 } 1191 printf("\n"); 1192 if (sc->sc_dma_ok) { 1193 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1194 sc->sc_wdcdev.irqack = pciide_irqack; 1195 } 1196 sc->sc_wdcdev.PIO_cap = 0; 1197 sc->sc_wdcdev.DMA_cap = 0; 1198 1199 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1200 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1201 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1202 1203 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1204 cp = &sc->pciide_channels[channel]; 1205 if (pciide_chansetup(sc, channel, interface) == 0) 1206 continue; 1207 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1208 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1209 &ctlsize, pciide_pci_intr); 1210 } else { 1211 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1212 channel, &cmdsize, &ctlsize); 1213 } 1214 if (cp->hw_ok == 0) 1215 continue; 1216 /* 1217 * Check to see if something appears to be there. 1218 */ 1219 failreason = NULL; 1220 if (!wdcprobe(&cp->wdc_channel)) { 1221 failreason = "not responding; disabled or no drives?"; 1222 goto next; 1223 } 1224 /* 1225 * Now, make sure it's actually attributable to this PCI IDE 1226 * channel by trying to access the channel again while the 1227 * PCI IDE controller's I/O space is disabled. (If the 1228 * channel no longer appears to be there, it belongs to 1229 * this controller.) YUCK! 1230 */ 1231 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1232 PCI_COMMAND_STATUS_REG); 1233 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1234 csr & ~PCI_COMMAND_IO_ENABLE); 1235 if (wdcprobe(&cp->wdc_channel)) 1236 failreason = "other hardware responding at addresses"; 1237 pci_conf_write(sc->sc_pc, sc->sc_tag, 1238 PCI_COMMAND_STATUS_REG, csr); 1239 next: 1240 if (failreason) { 1241 printf("%s: %s channel ignored (%s)\n", 1242 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1243 failreason); 1244 cp->hw_ok = 0; 1245 bus_space_unmap(cp->wdc_channel.cmd_iot, 1246 cp->wdc_channel.cmd_ioh, cmdsize); 1247 bus_space_unmap(cp->wdc_channel.ctl_iot, 1248 cp->wdc_channel.ctl_ioh, ctlsize); 1249 } else { 1250 pciide_map_compat_intr(pa, cp, channel, interface); 1251 } 1252 if (cp->hw_ok) { 1253 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1254 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1255 wdcattach(&cp->wdc_channel); 1256 } 1257 } 1258 1259 if (sc->sc_dma_ok == 0) 1260 return; 1261 1262 /* Allocate DMA maps */ 1263 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1264 idedma_ctl = 0; 1265 cp = &sc->pciide_channels[channel]; 1266 for (drive = 0; drive < 2; drive++) { 1267 drvp = &cp->wdc_channel.ch_drive[drive]; 1268 /* If no drive, skip */ 1269 if ((drvp->drive_flags & DRIVE) == 0) 1270 continue; 1271 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1272 continue; 1273 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1274 /* Abort DMA setup */ 1275 printf("%s:%d:%d: can't allocate DMA maps, " 1276 "using PIO transfers\n", 1277 sc->sc_wdcdev.sc_dev.dv_xname, 1278 channel, drive); 1279 drvp->drive_flags &= ~DRIVE_DMA; 1280 } 1281 printf("%s:%d:%d: using DMA data transfers\n", 1282 sc->sc_wdcdev.sc_dev.dv_xname, 1283 channel, drive); 1284 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1285 } 1286 if (idedma_ctl != 0) { 1287 /* Add software bits in status register */ 1288 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1289 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1290 idedma_ctl); 1291 } 1292 } 1293 } 1294 1295 void 1296 piix_chip_map(sc, pa) 1297 struct pciide_softc *sc; 1298 struct pci_attach_args *pa; 1299 { 1300 struct pciide_channel *cp; 1301 int channel; 1302 u_int32_t idetim; 1303 bus_size_t cmdsize, ctlsize; 1304 1305 if (pciide_chipen(sc, pa) == 0) 1306 return; 1307 1308 printf("%s: bus-master DMA support present", 1309 sc->sc_wdcdev.sc_dev.dv_xname); 1310 pciide_mapreg_dma(sc, pa); 1311 printf("\n"); 1312 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1313 WDC_CAPABILITY_MODE; 1314 if (sc->sc_dma_ok) { 1315 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1316 sc->sc_wdcdev.irqack = pciide_irqack; 1317 switch(sc->sc_pp->ide_product) { 1318 case PCI_PRODUCT_INTEL_82371AB_IDE: 1319 case PCI_PRODUCT_INTEL_82801AA_IDE: 1320 case PCI_PRODUCT_INTEL_82801AB_IDE: 1321 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1322 } 1323 } 1324 sc->sc_wdcdev.PIO_cap = 4; 1325 sc->sc_wdcdev.DMA_cap = 2; 1326 sc->sc_wdcdev.UDMA_cap = 1327 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1328 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1329 sc->sc_wdcdev.set_modes = piix_setup_channel; 1330 else 1331 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1332 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1333 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1334 1335 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1336 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1337 DEBUG_PROBE); 1338 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1339 WDCDEBUG_PRINT((", sidetim=0x%x", 1340 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1341 DEBUG_PROBE); 1342 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1343 WDCDEBUG_PRINT((", udamreg 0x%x", 1344 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1345 DEBUG_PROBE); 1346 } 1347 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1348 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1349 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1350 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1351 DEBUG_PROBE); 1352 } 1353 1354 } 1355 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1356 1357 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1358 cp = &sc->pciide_channels[channel]; 1359 /* PIIX is compat-only */ 1360 if (pciide_chansetup(sc, channel, 0) == 0) 1361 continue; 1362 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1363 if ((PIIX_IDETIM_READ(idetim, channel) & 1364 PIIX_IDETIM_IDE) == 0) { 1365 printf("%s: %s channel ignored (disabled)\n", 1366 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1367 continue; 1368 } 1369 /* PIIX are compat-only pciide devices */ 1370 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1371 if (cp->hw_ok == 0) 1372 continue; 1373 if (pciide_chan_candisable(cp)) { 1374 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1375 channel); 1376 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1377 idetim); 1378 } 1379 pciide_map_compat_intr(pa, cp, channel, 0); 1380 if (cp->hw_ok == 0) 1381 continue; 1382 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1383 } 1384 1385 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1386 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1387 DEBUG_PROBE); 1388 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1389 WDCDEBUG_PRINT((", sidetim=0x%x", 1390 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1391 DEBUG_PROBE); 1392 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1393 WDCDEBUG_PRINT((", udamreg 0x%x", 1394 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1395 DEBUG_PROBE); 1396 } 1397 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1398 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1399 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1400 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1401 DEBUG_PROBE); 1402 } 1403 } 1404 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1405 } 1406 1407 void 1408 piix_setup_channel(chp) 1409 struct channel_softc *chp; 1410 { 1411 u_int8_t mode[2], drive; 1412 u_int32_t oidetim, idetim, idedma_ctl; 1413 struct pciide_channel *cp = (struct pciide_channel*)chp; 1414 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1415 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1416 1417 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1418 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1419 idedma_ctl = 0; 1420 1421 /* set up new idetim: Enable IDE registers decode */ 1422 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1423 chp->channel); 1424 1425 /* setup DMA */ 1426 pciide_channel_dma_setup(cp); 1427 1428 /* 1429 * Here we have to mess up with drives mode: PIIX can't have 1430 * different timings for master and slave drives. 1431 * We need to find the best combination. 1432 */ 1433 1434 /* If both drives supports DMA, take the lower mode */ 1435 if ((drvp[0].drive_flags & DRIVE_DMA) && 1436 (drvp[1].drive_flags & DRIVE_DMA)) { 1437 mode[0] = mode[1] = 1438 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1439 drvp[0].DMA_mode = mode[0]; 1440 drvp[1].DMA_mode = mode[1]; 1441 goto ok; 1442 } 1443 /* 1444 * If only one drive supports DMA, use its mode, and 1445 * put the other one in PIO mode 0 if mode not compatible 1446 */ 1447 if (drvp[0].drive_flags & DRIVE_DMA) { 1448 mode[0] = drvp[0].DMA_mode; 1449 mode[1] = drvp[1].PIO_mode; 1450 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1451 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1452 mode[1] = drvp[1].PIO_mode = 0; 1453 goto ok; 1454 } 1455 if (drvp[1].drive_flags & DRIVE_DMA) { 1456 mode[1] = drvp[1].DMA_mode; 1457 mode[0] = drvp[0].PIO_mode; 1458 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1459 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1460 mode[0] = drvp[0].PIO_mode = 0; 1461 goto ok; 1462 } 1463 /* 1464 * If both drives are not DMA, takes the lower mode, unless 1465 * one of them is PIO mode < 2 1466 */ 1467 if (drvp[0].PIO_mode < 2) { 1468 mode[0] = drvp[0].PIO_mode = 0; 1469 mode[1] = drvp[1].PIO_mode; 1470 } else if (drvp[1].PIO_mode < 2) { 1471 mode[1] = drvp[1].PIO_mode = 0; 1472 mode[0] = drvp[0].PIO_mode; 1473 } else { 1474 mode[0] = mode[1] = 1475 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1476 drvp[0].PIO_mode = mode[0]; 1477 drvp[1].PIO_mode = mode[1]; 1478 } 1479 ok: /* The modes are setup */ 1480 for (drive = 0; drive < 2; drive++) { 1481 if (drvp[drive].drive_flags & DRIVE_DMA) { 1482 idetim |= piix_setup_idetim_timings( 1483 mode[drive], 1, chp->channel); 1484 goto end; 1485 } 1486 } 1487 /* If we are there, none of the drives are DMA */ 1488 if (mode[0] >= 2) 1489 idetim |= piix_setup_idetim_timings( 1490 mode[0], 0, chp->channel); 1491 else 1492 idetim |= piix_setup_idetim_timings( 1493 mode[1], 0, chp->channel); 1494 end: /* 1495 * timing mode is now set up in the controller. Enable 1496 * it per-drive 1497 */ 1498 for (drive = 0; drive < 2; drive++) { 1499 /* If no drive, skip */ 1500 if ((drvp[drive].drive_flags & DRIVE) == 0) 1501 continue; 1502 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1503 if (drvp[drive].drive_flags & DRIVE_DMA) 1504 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1505 } 1506 if (idedma_ctl != 0) { 1507 /* Add software bits in status register */ 1508 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1509 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1510 idedma_ctl); 1511 } 1512 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1513 pciide_print_modes(cp); 1514 } 1515 1516 void 1517 piix3_4_setup_channel(chp) 1518 struct channel_softc *chp; 1519 { 1520 struct ata_drive_datas *drvp; 1521 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1522 struct pciide_channel *cp = (struct pciide_channel*)chp; 1523 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1524 int drive; 1525 int channel = chp->channel; 1526 1527 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1528 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1529 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1530 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1531 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1532 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1533 PIIX_SIDETIM_RTC_MASK(channel)); 1534 1535 idedma_ctl = 0; 1536 /* If channel disabled, no need to go further */ 1537 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1538 return; 1539 /* set up new idetim: Enable IDE registers decode */ 1540 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1541 1542 /* setup DMA if needed */ 1543 pciide_channel_dma_setup(cp); 1544 1545 for (drive = 0; drive < 2; drive++) { 1546 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1547 PIIX_UDMATIM_SET(0x3, channel, drive)); 1548 drvp = &chp->ch_drive[drive]; 1549 /* If no drive, skip */ 1550 if ((drvp->drive_flags & DRIVE) == 0) 1551 continue; 1552 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1553 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1554 goto pio; 1555 1556 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1557 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1558 ideconf |= PIIX_CONFIG_PINGPONG; 1559 } 1560 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1561 /* setup Ultra/66 */ 1562 if (drvp->UDMA_mode > 2 && 1563 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1564 drvp->UDMA_mode = 2; 1565 if (drvp->UDMA_mode > 2) 1566 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1567 else 1568 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1569 } 1570 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1571 (drvp->drive_flags & DRIVE_UDMA)) { 1572 /* use Ultra/DMA */ 1573 drvp->drive_flags &= ~DRIVE_DMA; 1574 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1575 udmareg |= PIIX_UDMATIM_SET( 1576 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1577 } else { 1578 /* use Multiword DMA */ 1579 drvp->drive_flags &= ~DRIVE_UDMA; 1580 if (drive == 0) { 1581 idetim |= piix_setup_idetim_timings( 1582 drvp->DMA_mode, 1, channel); 1583 } else { 1584 sidetim |= piix_setup_sidetim_timings( 1585 drvp->DMA_mode, 1, channel); 1586 idetim =PIIX_IDETIM_SET(idetim, 1587 PIIX_IDETIM_SITRE, channel); 1588 } 1589 } 1590 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1591 1592 pio: /* use PIO mode */ 1593 idetim |= piix_setup_idetim_drvs(drvp); 1594 if (drive == 0) { 1595 idetim |= piix_setup_idetim_timings( 1596 drvp->PIO_mode, 0, channel); 1597 } else { 1598 sidetim |= piix_setup_sidetim_timings( 1599 drvp->PIO_mode, 0, channel); 1600 idetim =PIIX_IDETIM_SET(idetim, 1601 PIIX_IDETIM_SITRE, channel); 1602 } 1603 } 1604 if (idedma_ctl != 0) { 1605 /* Add software bits in status register */ 1606 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1607 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1608 idedma_ctl); 1609 } 1610 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1611 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1612 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1613 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1614 pciide_print_modes(cp); 1615 } 1616 1617 1618 /* setup ISP and RTC fields, based on mode */ 1619 static u_int32_t 1620 piix_setup_idetim_timings(mode, dma, channel) 1621 u_int8_t mode; 1622 u_int8_t dma; 1623 u_int8_t channel; 1624 { 1625 1626 if (dma) 1627 return PIIX_IDETIM_SET(0, 1628 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1629 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1630 channel); 1631 else 1632 return PIIX_IDETIM_SET(0, 1633 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1634 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1635 channel); 1636 } 1637 1638 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1639 static u_int32_t 1640 piix_setup_idetim_drvs(drvp) 1641 struct ata_drive_datas *drvp; 1642 { 1643 u_int32_t ret = 0; 1644 struct channel_softc *chp = drvp->chnl_softc; 1645 u_int8_t channel = chp->channel; 1646 u_int8_t drive = drvp->drive; 1647 1648 /* 1649 * If drive is using UDMA, timings setups are independant 1650 * So just check DMA and PIO here. 1651 */ 1652 if (drvp->drive_flags & DRIVE_DMA) { 1653 /* if mode = DMA mode 0, use compatible timings */ 1654 if ((drvp->drive_flags & DRIVE_DMA) && 1655 drvp->DMA_mode == 0) { 1656 drvp->PIO_mode = 0; 1657 return ret; 1658 } 1659 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1660 /* 1661 * PIO and DMA timings are the same, use fast timings for PIO 1662 * too, else use compat timings. 1663 */ 1664 if ((piix_isp_pio[drvp->PIO_mode] != 1665 piix_isp_dma[drvp->DMA_mode]) || 1666 (piix_rtc_pio[drvp->PIO_mode] != 1667 piix_rtc_dma[drvp->DMA_mode])) 1668 drvp->PIO_mode = 0; 1669 /* if PIO mode <= 2, use compat timings for PIO */ 1670 if (drvp->PIO_mode <= 2) { 1671 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1672 channel); 1673 return ret; 1674 } 1675 } 1676 1677 /* 1678 * Now setup PIO modes. If mode < 2, use compat timings. 1679 * Else enable fast timings. Enable IORDY and prefetch/post 1680 * if PIO mode >= 3. 1681 */ 1682 1683 if (drvp->PIO_mode < 2) 1684 return ret; 1685 1686 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1687 if (drvp->PIO_mode >= 3) { 1688 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1689 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1690 } 1691 return ret; 1692 } 1693 1694 /* setup values in SIDETIM registers, based on mode */ 1695 static u_int32_t 1696 piix_setup_sidetim_timings(mode, dma, channel) 1697 u_int8_t mode; 1698 u_int8_t dma; 1699 u_int8_t channel; 1700 { 1701 if (dma) 1702 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1703 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1704 else 1705 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1706 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1707 } 1708 1709 void 1710 amd756_chip_map(sc, pa) 1711 struct pciide_softc *sc; 1712 struct pci_attach_args *pa; 1713 { 1714 struct pciide_channel *cp; 1715 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1716 int channel; 1717 pcireg_t chanenable; 1718 bus_size_t cmdsize, ctlsize; 1719 1720 if (pciide_chipen(sc, pa) == 0) 1721 return; 1722 printf("%s: bus-master DMA support present", 1723 sc->sc_wdcdev.sc_dev.dv_xname); 1724 pciide_mapreg_dma(sc, pa); 1725 printf("\n"); 1726 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1727 WDC_CAPABILITY_MODE; 1728 if (sc->sc_dma_ok) { 1729 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1730 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1731 sc->sc_wdcdev.irqack = pciide_irqack; 1732 } 1733 sc->sc_wdcdev.PIO_cap = 4; 1734 sc->sc_wdcdev.DMA_cap = 2; 1735 sc->sc_wdcdev.UDMA_cap = 4; 1736 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1737 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1738 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1739 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1740 1741 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1742 DEBUG_PROBE); 1743 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1744 cp = &sc->pciide_channels[channel]; 1745 if (pciide_chansetup(sc, channel, interface) == 0) 1746 continue; 1747 1748 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1749 printf("%s: %s channel ignored (disabled)\n", 1750 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1751 continue; 1752 } 1753 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1754 pciide_pci_intr); 1755 1756 if (pciide_chan_candisable(cp)) 1757 chanenable &= ~AMD756_CHAN_EN(channel); 1758 pciide_map_compat_intr(pa, cp, channel, interface); 1759 if (cp->hw_ok == 0) 1760 continue; 1761 1762 amd756_setup_channel(&cp->wdc_channel); 1763 } 1764 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1765 chanenable); 1766 return; 1767 } 1768 1769 void 1770 amd756_setup_channel(chp) 1771 struct channel_softc *chp; 1772 { 1773 u_int32_t udmatim_reg, datatim_reg; 1774 u_int8_t idedma_ctl; 1775 int mode, drive; 1776 struct ata_drive_datas *drvp; 1777 struct pciide_channel *cp = (struct pciide_channel*)chp; 1778 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1779 1780 idedma_ctl = 0; 1781 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1782 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1783 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1784 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1785 1786 /* setup DMA if needed */ 1787 pciide_channel_dma_setup(cp); 1788 1789 for (drive = 0; drive < 2; drive++) { 1790 drvp = &chp->ch_drive[drive]; 1791 /* If no drive, skip */ 1792 if ((drvp->drive_flags & DRIVE) == 0) 1793 continue; 1794 /* add timing values, setup DMA if needed */ 1795 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1796 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1797 mode = drvp->PIO_mode; 1798 goto pio; 1799 } 1800 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1801 (drvp->drive_flags & DRIVE_UDMA)) { 1802 /* use Ultra/DMA */ 1803 drvp->drive_flags &= ~DRIVE_DMA; 1804 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1805 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1806 AMD756_UDMA_TIME(chp->channel, drive, 1807 amd756_udma_tim[drvp->UDMA_mode]); 1808 /* can use PIO timings, MW DMA unused */ 1809 mode = drvp->PIO_mode; 1810 } else { 1811 /* use Multiword DMA */ 1812 drvp->drive_flags &= ~DRIVE_UDMA; 1813 /* mode = min(pio, dma+2) */ 1814 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1815 mode = drvp->PIO_mode; 1816 else 1817 mode = drvp->DMA_mode + 2; 1818 } 1819 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1820 1821 pio: /* setup PIO mode */ 1822 if (mode <= 2) { 1823 drvp->DMA_mode = 0; 1824 drvp->PIO_mode = 0; 1825 mode = 0; 1826 } else { 1827 drvp->PIO_mode = mode; 1828 drvp->DMA_mode = mode - 2; 1829 } 1830 datatim_reg |= 1831 AMD756_DATATIM_PULSE(chp->channel, drive, 1832 amd756_pio_set[mode]) | 1833 AMD756_DATATIM_RECOV(chp->channel, drive, 1834 amd756_pio_rec[mode]); 1835 } 1836 if (idedma_ctl != 0) { 1837 /* Add software bits in status register */ 1838 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1839 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1840 idedma_ctl); 1841 } 1842 pciide_print_modes(cp); 1843 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1844 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1845 } 1846 1847 void 1848 apollo_chip_map(sc, pa) 1849 struct pciide_softc *sc; 1850 struct pci_attach_args *pa; 1851 { 1852 struct pciide_channel *cp; 1853 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1854 int channel; 1855 u_int32_t ideconf; 1856 bus_size_t cmdsize, ctlsize; 1857 1858 if (pciide_chipen(sc, pa) == 0) 1859 return; 1860 printf("%s: bus-master DMA support present", 1861 sc->sc_wdcdev.sc_dev.dv_xname); 1862 pciide_mapreg_dma(sc, pa); 1863 printf("\n"); 1864 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1865 WDC_CAPABILITY_MODE; 1866 if (sc->sc_dma_ok) { 1867 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1868 sc->sc_wdcdev.irqack = pciide_irqack; 1869 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1870 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1871 } 1872 sc->sc_wdcdev.PIO_cap = 4; 1873 sc->sc_wdcdev.DMA_cap = 2; 1874 sc->sc_wdcdev.UDMA_cap = 2; 1875 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1876 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1877 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1878 1879 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1880 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1881 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1882 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1883 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1884 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1885 DEBUG_PROBE); 1886 1887 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1888 cp = &sc->pciide_channels[channel]; 1889 if (pciide_chansetup(sc, channel, interface) == 0) 1890 continue; 1891 1892 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1893 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1894 printf("%s: %s channel ignored (disabled)\n", 1895 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1896 continue; 1897 } 1898 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1899 pciide_pci_intr); 1900 if (cp->hw_ok == 0) 1901 continue; 1902 if (pciide_chan_candisable(cp)) { 1903 ideconf &= ~APO_IDECONF_EN(channel); 1904 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1905 ideconf); 1906 } 1907 pciide_map_compat_intr(pa, cp, channel, interface); 1908 1909 if (cp->hw_ok == 0) 1910 continue; 1911 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1912 } 1913 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1914 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1915 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1916 } 1917 1918 void 1919 apollo_setup_channel(chp) 1920 struct channel_softc *chp; 1921 { 1922 u_int32_t udmatim_reg, datatim_reg; 1923 u_int8_t idedma_ctl; 1924 int mode, drive; 1925 struct ata_drive_datas *drvp; 1926 struct pciide_channel *cp = (struct pciide_channel*)chp; 1927 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1928 1929 idedma_ctl = 0; 1930 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1931 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1932 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1933 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1934 1935 /* setup DMA if needed */ 1936 pciide_channel_dma_setup(cp); 1937 1938 for (drive = 0; drive < 2; drive++) { 1939 drvp = &chp->ch_drive[drive]; 1940 /* If no drive, skip */ 1941 if ((drvp->drive_flags & DRIVE) == 0) 1942 continue; 1943 /* add timing values, setup DMA if needed */ 1944 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1945 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1946 mode = drvp->PIO_mode; 1947 goto pio; 1948 } 1949 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1950 (drvp->drive_flags & DRIVE_UDMA)) { 1951 /* use Ultra/DMA */ 1952 drvp->drive_flags &= ~DRIVE_DMA; 1953 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1954 APO_UDMA_EN_MTH(chp->channel, drive) | 1955 APO_UDMA_TIME(chp->channel, drive, 1956 apollo_udma_tim[drvp->UDMA_mode]); 1957 /* can use PIO timings, MW DMA unused */ 1958 mode = drvp->PIO_mode; 1959 } else { 1960 /* use Multiword DMA */ 1961 drvp->drive_flags &= ~DRIVE_UDMA; 1962 /* mode = min(pio, dma+2) */ 1963 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1964 mode = drvp->PIO_mode; 1965 else 1966 mode = drvp->DMA_mode + 2; 1967 } 1968 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1969 1970 pio: /* setup PIO mode */ 1971 if (mode <= 2) { 1972 drvp->DMA_mode = 0; 1973 drvp->PIO_mode = 0; 1974 mode = 0; 1975 } else { 1976 drvp->PIO_mode = mode; 1977 drvp->DMA_mode = mode - 2; 1978 } 1979 datatim_reg |= 1980 APO_DATATIM_PULSE(chp->channel, drive, 1981 apollo_pio_set[mode]) | 1982 APO_DATATIM_RECOV(chp->channel, drive, 1983 apollo_pio_rec[mode]); 1984 } 1985 if (idedma_ctl != 0) { 1986 /* Add software bits in status register */ 1987 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1988 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1989 idedma_ctl); 1990 } 1991 pciide_print_modes(cp); 1992 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 1993 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 1994 } 1995 1996 void 1997 cmd_channel_map(pa, sc, channel) 1998 struct pci_attach_args *pa; 1999 struct pciide_softc *sc; 2000 int channel; 2001 { 2002 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2003 bus_size_t cmdsize, ctlsize; 2004 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2005 int interface; 2006 2007 /* 2008 * The 0648/0649 can be told to identify as a RAID controller. 2009 * In this case, we have to fake interface 2010 */ 2011 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2012 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2013 PCIIDE_INTERFACE_SETTABLE(1); 2014 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2015 CMD_CONF_DSA1) 2016 interface |= PCIIDE_INTERFACE_PCI(0) | 2017 PCIIDE_INTERFACE_PCI(1); 2018 } else { 2019 interface = PCI_INTERFACE(pa->pa_class); 2020 } 2021 2022 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2023 cp->name = PCIIDE_CHANNEL_NAME(channel); 2024 cp->wdc_channel.channel = channel; 2025 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2026 2027 if (channel > 0) { 2028 cp->wdc_channel.ch_queue = 2029 sc->pciide_channels[0].wdc_channel.ch_queue; 2030 } else { 2031 cp->wdc_channel.ch_queue = 2032 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2033 } 2034 if (cp->wdc_channel.ch_queue == NULL) { 2035 printf("%s %s channel: " 2036 "can't allocate memory for command queue", 2037 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2038 return; 2039 } 2040 2041 printf("%s: %s channel %s to %s mode\n", 2042 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2043 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2044 "configured" : "wired", 2045 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2046 "native-PCI" : "compatibility"); 2047 2048 /* 2049 * with a CMD PCI64x, if we get here, the first channel is enabled: 2050 * there's no way to disable the first channel without disabling 2051 * the whole device 2052 */ 2053 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2054 printf("%s: %s channel ignored (disabled)\n", 2055 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2056 return; 2057 } 2058 2059 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2060 if (cp->hw_ok == 0) 2061 return; 2062 if (channel == 1) { 2063 if (pciide_chan_candisable(cp)) { 2064 ctrl &= ~CMD_CTRL_2PORT; 2065 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2066 CMD_CTRL, ctrl); 2067 } 2068 } 2069 pciide_map_compat_intr(pa, cp, channel, interface); 2070 } 2071 2072 int 2073 cmd_pci_intr(arg) 2074 void *arg; 2075 { 2076 struct pciide_softc *sc = arg; 2077 struct pciide_channel *cp; 2078 struct channel_softc *wdc_cp; 2079 int i, rv, crv; 2080 u_int32_t priirq, secirq; 2081 2082 rv = 0; 2083 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2084 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2085 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2086 cp = &sc->pciide_channels[i]; 2087 wdc_cp = &cp->wdc_channel; 2088 /* If a compat channel skip. */ 2089 if (cp->compat) 2090 continue; 2091 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2092 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2093 crv = wdcintr(wdc_cp); 2094 if (crv == 0) 2095 printf("%s:%d: bogus intr\n", 2096 sc->sc_wdcdev.sc_dev.dv_xname, i); 2097 else 2098 rv = 1; 2099 } 2100 } 2101 return rv; 2102 } 2103 2104 void 2105 cmd_chip_map(sc, pa) 2106 struct pciide_softc *sc; 2107 struct pci_attach_args *pa; 2108 { 2109 int channel; 2110 2111 /* 2112 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2113 * and base adresses registers can be disabled at 2114 * hardware level. In this case, the device is wired 2115 * in compat mode and its first channel is always enabled, 2116 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2117 * In fact, it seems that the first channel of the CMD PCI0640 2118 * can't be disabled. 2119 */ 2120 2121 #ifdef PCIIDE_CMD064x_DISABLE 2122 if (pciide_chipen(sc, pa) == 0) 2123 return; 2124 #endif 2125 2126 printf("%s: hardware does not support DMA\n", 2127 sc->sc_wdcdev.sc_dev.dv_xname); 2128 sc->sc_dma_ok = 0; 2129 2130 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2131 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2132 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2133 2134 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2135 cmd_channel_map(pa, sc, channel); 2136 } 2137 } 2138 2139 void 2140 cmd0643_9_chip_map(sc, pa) 2141 struct pciide_softc *sc; 2142 struct pci_attach_args *pa; 2143 { 2144 struct pciide_channel *cp; 2145 int channel; 2146 2147 /* 2148 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2149 * and base adresses registers can be disabled at 2150 * hardware level. In this case, the device is wired 2151 * in compat mode and its first channel is always enabled, 2152 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2153 * In fact, it seems that the first channel of the CMD PCI0640 2154 * can't be disabled. 2155 */ 2156 2157 #ifdef PCIIDE_CMD064x_DISABLE 2158 if (pciide_chipen(sc, pa) == 0) 2159 return; 2160 #endif 2161 printf("%s: bus-master DMA support present", 2162 sc->sc_wdcdev.sc_dev.dv_xname); 2163 pciide_mapreg_dma(sc, pa); 2164 printf("\n"); 2165 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2166 WDC_CAPABILITY_MODE; 2167 if (sc->sc_dma_ok) { 2168 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2169 switch (sc->sc_pp->ide_product) { 2170 case PCI_PRODUCT_CMDTECH_649: 2171 case PCI_PRODUCT_CMDTECH_648: 2172 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2173 sc->sc_wdcdev.UDMA_cap = 4; 2174 sc->sc_wdcdev.irqack = cmd648_9_irqack; 2175 break; 2176 default: 2177 sc->sc_wdcdev.irqack = pciide_irqack; 2178 } 2179 } 2180 2181 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2182 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2183 sc->sc_wdcdev.PIO_cap = 4; 2184 sc->sc_wdcdev.DMA_cap = 2; 2185 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2186 2187 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2188 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2189 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2190 DEBUG_PROBE); 2191 2192 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2193 cp = &sc->pciide_channels[channel]; 2194 cmd_channel_map(pa, sc, channel); 2195 if (cp->hw_ok == 0) 2196 continue; 2197 cmd0643_9_setup_channel(&cp->wdc_channel); 2198 } 2199 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2200 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2201 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2202 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2203 DEBUG_PROBE); 2204 } 2205 2206 void 2207 cmd0643_9_setup_channel(chp) 2208 struct channel_softc *chp; 2209 { 2210 struct ata_drive_datas *drvp; 2211 u_int8_t tim; 2212 u_int32_t idedma_ctl, udma_reg; 2213 int drive; 2214 struct pciide_channel *cp = (struct pciide_channel*)chp; 2215 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2216 2217 idedma_ctl = 0; 2218 /* setup DMA if needed */ 2219 pciide_channel_dma_setup(cp); 2220 2221 for (drive = 0; drive < 2; drive++) { 2222 drvp = &chp->ch_drive[drive]; 2223 /* If no drive, skip */ 2224 if ((drvp->drive_flags & DRIVE) == 0) 2225 continue; 2226 /* add timing values, setup DMA if needed */ 2227 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2228 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2229 if (drvp->drive_flags & DRIVE_UDMA) { 2230 /* UltraDMA on a 0648 or 0649 */ 2231 udma_reg = pciide_pci_read(sc->sc_pc, 2232 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2233 if (drvp->UDMA_mode > 2 && 2234 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2235 CMD_BICSR) & 2236 CMD_BICSR_80(chp->channel)) == 0) 2237 drvp->UDMA_mode = 2; 2238 if (drvp->UDMA_mode > 2) 2239 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2240 else 2241 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2242 udma_reg |= CMD_UDMATIM_UDMA(drive); 2243 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2244 CMD_UDMATIM_TIM_OFF(drive)); 2245 udma_reg |= 2246 (cmd0648_9_tim_udma[drvp->UDMA_mode] << 2247 CMD_UDMATIM_TIM_OFF(drive)); 2248 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2249 CMD_UDMATIM(chp->channel), udma_reg); 2250 } else { 2251 /* 2252 * use Multiword DMA. 2253 * Timings will be used for both PIO and DMA, 2254 * so adjust DMA mode if needed 2255 * if we have a 0648/9, turn off UDMA 2256 */ 2257 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2258 udma_reg = pciide_pci_read(sc->sc_pc, 2259 sc->sc_tag, 2260 CMD_UDMATIM(chp->channel)); 2261 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2262 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2263 CMD_UDMATIM(chp->channel), 2264 udma_reg); 2265 } 2266 if (drvp->PIO_mode >= 3 && 2267 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2268 drvp->DMA_mode = drvp->PIO_mode - 2; 2269 } 2270 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2271 } 2272 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2273 } 2274 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2275 CMD_DATA_TIM(chp->channel, drive), tim); 2276 } 2277 if (idedma_ctl != 0) { 2278 /* Add software bits in status register */ 2279 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2280 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2281 idedma_ctl); 2282 } 2283 pciide_print_modes(cp); 2284 } 2285 2286 void 2287 cmd648_9_irqack(chp) 2288 struct channel_softc *chp; 2289 { 2290 u_int32_t priirq, secirq; 2291 struct pciide_channel *cp = (struct pciide_channel*)chp; 2292 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2293 2294 if (chp->channel == 0) { 2295 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2296 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2297 } else { 2298 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2299 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2300 } 2301 pciide_irqack(chp); 2302 } 2303 2304 void 2305 cy693_chip_map(sc, pa) 2306 struct pciide_softc *sc; 2307 struct pci_attach_args *pa; 2308 { 2309 struct pciide_channel *cp; 2310 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2311 bus_size_t cmdsize, ctlsize; 2312 2313 if (pciide_chipen(sc, pa) == 0) 2314 return; 2315 /* 2316 * this chip has 2 PCI IDE functions, one for primary and one for 2317 * secondary. So we need to call pciide_mapregs_compat() with 2318 * the real channel 2319 */ 2320 if (pa->pa_function == 1) { 2321 sc->sc_cy_compatchan = 0; 2322 } else if (pa->pa_function == 2) { 2323 sc->sc_cy_compatchan = 1; 2324 } else { 2325 printf("%s: unexpected PCI function %d\n", 2326 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2327 return; 2328 } 2329 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2330 printf("%s: bus-master DMA support present", 2331 sc->sc_wdcdev.sc_dev.dv_xname); 2332 pciide_mapreg_dma(sc, pa); 2333 } else { 2334 printf("%s: hardware does not support DMA", 2335 sc->sc_wdcdev.sc_dev.dv_xname); 2336 sc->sc_dma_ok = 0; 2337 } 2338 printf("\n"); 2339 2340 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2341 if (sc->sc_cy_handle == NULL) { 2342 printf("%s: unable to map hyperCache control registers\n", 2343 sc->sc_wdcdev.sc_dev.dv_xname); 2344 sc->sc_dma_ok = 0; 2345 } 2346 2347 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2348 WDC_CAPABILITY_MODE; 2349 if (sc->sc_dma_ok) { 2350 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2351 sc->sc_wdcdev.irqack = pciide_irqack; 2352 } 2353 sc->sc_wdcdev.PIO_cap = 4; 2354 sc->sc_wdcdev.DMA_cap = 2; 2355 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2356 2357 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2358 sc->sc_wdcdev.nchannels = 1; 2359 2360 /* Only one channel for this chip; if we are here it's enabled */ 2361 cp = &sc->pciide_channels[0]; 2362 sc->wdc_chanarray[0] = &cp->wdc_channel; 2363 cp->name = PCIIDE_CHANNEL_NAME(0); 2364 cp->wdc_channel.channel = 0; 2365 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2366 cp->wdc_channel.ch_queue = 2367 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2368 if (cp->wdc_channel.ch_queue == NULL) { 2369 printf("%s primary channel: " 2370 "can't allocate memory for command queue", 2371 sc->sc_wdcdev.sc_dev.dv_xname); 2372 return; 2373 } 2374 printf("%s: primary channel %s to ", 2375 sc->sc_wdcdev.sc_dev.dv_xname, 2376 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2377 "configured" : "wired"); 2378 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2379 printf("native-PCI"); 2380 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2381 pciide_pci_intr); 2382 } else { 2383 printf("compatibility"); 2384 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2385 &cmdsize, &ctlsize); 2386 } 2387 printf(" mode\n"); 2388 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2389 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2390 wdcattach(&cp->wdc_channel); 2391 if (pciide_chan_candisable(cp)) { 2392 pci_conf_write(sc->sc_pc, sc->sc_tag, 2393 PCI_COMMAND_STATUS_REG, 0); 2394 } 2395 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2396 if (cp->hw_ok == 0) 2397 return; 2398 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2399 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2400 cy693_setup_channel(&cp->wdc_channel); 2401 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2402 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2403 } 2404 2405 void 2406 cy693_setup_channel(chp) 2407 struct channel_softc *chp; 2408 { 2409 struct ata_drive_datas *drvp; 2410 int drive; 2411 u_int32_t cy_cmd_ctrl; 2412 u_int32_t idedma_ctl; 2413 struct pciide_channel *cp = (struct pciide_channel*)chp; 2414 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2415 int dma_mode = -1; 2416 2417 cy_cmd_ctrl = idedma_ctl = 0; 2418 2419 /* setup DMA if needed */ 2420 pciide_channel_dma_setup(cp); 2421 2422 for (drive = 0; drive < 2; drive++) { 2423 drvp = &chp->ch_drive[drive]; 2424 /* If no drive, skip */ 2425 if ((drvp->drive_flags & DRIVE) == 0) 2426 continue; 2427 /* add timing values, setup DMA if needed */ 2428 if (drvp->drive_flags & DRIVE_DMA) { 2429 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2430 /* use Multiword DMA */ 2431 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2432 dma_mode = drvp->DMA_mode; 2433 } 2434 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2435 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2436 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2437 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2438 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2439 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2440 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2441 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2442 } 2443 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2444 chp->ch_drive[0].DMA_mode = dma_mode; 2445 chp->ch_drive[1].DMA_mode = dma_mode; 2446 2447 if (dma_mode == -1) 2448 dma_mode = 0; 2449 2450 if (sc->sc_cy_handle != NULL) { 2451 /* Note: `multiple' is implied. */ 2452 cy82c693_write(sc->sc_cy_handle, 2453 (sc->sc_cy_compatchan == 0) ? 2454 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2455 } 2456 2457 pciide_print_modes(cp); 2458 2459 if (idedma_ctl != 0) { 2460 /* Add software bits in status register */ 2461 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2462 IDEDMA_CTL, idedma_ctl); 2463 } 2464 } 2465 2466 void 2467 sis_chip_map(sc, pa) 2468 struct pciide_softc *sc; 2469 struct pci_attach_args *pa; 2470 { 2471 struct pciide_channel *cp; 2472 int channel; 2473 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2474 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2475 pcireg_t rev = PCI_REVISION(pa->pa_class); 2476 bus_size_t cmdsize, ctlsize; 2477 2478 if (pciide_chipen(sc, pa) == 0) 2479 return; 2480 printf("%s: bus-master DMA support present", 2481 sc->sc_wdcdev.sc_dev.dv_xname); 2482 pciide_mapreg_dma(sc, pa); 2483 printf("\n"); 2484 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2485 WDC_CAPABILITY_MODE; 2486 if (sc->sc_dma_ok) { 2487 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2488 sc->sc_wdcdev.irqack = pciide_irqack; 2489 if (rev >= 0xd0) 2490 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2491 } 2492 2493 sc->sc_wdcdev.PIO_cap = 4; 2494 sc->sc_wdcdev.DMA_cap = 2; 2495 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2496 sc->sc_wdcdev.UDMA_cap = 2; 2497 sc->sc_wdcdev.set_modes = sis_setup_channel; 2498 2499 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2500 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2501 2502 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2503 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2504 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2505 2506 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2507 cp = &sc->pciide_channels[channel]; 2508 if (pciide_chansetup(sc, channel, interface) == 0) 2509 continue; 2510 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2511 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2512 printf("%s: %s channel ignored (disabled)\n", 2513 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2514 continue; 2515 } 2516 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2517 pciide_pci_intr); 2518 if (cp->hw_ok == 0) 2519 continue; 2520 if (pciide_chan_candisable(cp)) { 2521 if (channel == 0) 2522 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2523 else 2524 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2525 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2526 sis_ctr0); 2527 } 2528 pciide_map_compat_intr(pa, cp, channel, interface); 2529 if (cp->hw_ok == 0) 2530 continue; 2531 sis_setup_channel(&cp->wdc_channel); 2532 } 2533 } 2534 2535 void 2536 sis_setup_channel(chp) 2537 struct channel_softc *chp; 2538 { 2539 struct ata_drive_datas *drvp; 2540 int drive; 2541 u_int32_t sis_tim; 2542 u_int32_t idedma_ctl; 2543 struct pciide_channel *cp = (struct pciide_channel*)chp; 2544 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2545 2546 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2547 "channel %d 0x%x\n", chp->channel, 2548 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2549 DEBUG_PROBE); 2550 sis_tim = 0; 2551 idedma_ctl = 0; 2552 /* setup DMA if needed */ 2553 pciide_channel_dma_setup(cp); 2554 2555 for (drive = 0; drive < 2; drive++) { 2556 drvp = &chp->ch_drive[drive]; 2557 /* If no drive, skip */ 2558 if ((drvp->drive_flags & DRIVE) == 0) 2559 continue; 2560 /* add timing values, setup DMA if needed */ 2561 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2562 (drvp->drive_flags & DRIVE_UDMA) == 0) 2563 goto pio; 2564 2565 if (drvp->drive_flags & DRIVE_UDMA) { 2566 /* use Ultra/DMA */ 2567 drvp->drive_flags &= ~DRIVE_DMA; 2568 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2569 SIS_TIM_UDMA_TIME_OFF(drive); 2570 sis_tim |= SIS_TIM_UDMA_EN(drive); 2571 } else { 2572 /* 2573 * use Multiword DMA 2574 * Timings will be used for both PIO and DMA, 2575 * so adjust DMA mode if needed 2576 */ 2577 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2578 drvp->PIO_mode = drvp->DMA_mode + 2; 2579 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2580 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2581 drvp->PIO_mode - 2 : 0; 2582 if (drvp->DMA_mode == 0) 2583 drvp->PIO_mode = 0; 2584 } 2585 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2586 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2587 SIS_TIM_ACT_OFF(drive); 2588 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2589 SIS_TIM_REC_OFF(drive); 2590 } 2591 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2592 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2593 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2594 if (idedma_ctl != 0) { 2595 /* Add software bits in status register */ 2596 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2597 IDEDMA_CTL, idedma_ctl); 2598 } 2599 pciide_print_modes(cp); 2600 } 2601 2602 void 2603 acer_chip_map(sc, pa) 2604 struct pciide_softc *sc; 2605 struct pci_attach_args *pa; 2606 { 2607 struct pciide_channel *cp; 2608 int channel; 2609 pcireg_t cr, interface; 2610 bus_size_t cmdsize, ctlsize; 2611 2612 if (pciide_chipen(sc, pa) == 0) 2613 return; 2614 printf("%s: bus-master DMA support present", 2615 sc->sc_wdcdev.sc_dev.dv_xname); 2616 pciide_mapreg_dma(sc, pa); 2617 printf("\n"); 2618 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2619 WDC_CAPABILITY_MODE; 2620 if (sc->sc_dma_ok) { 2621 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2622 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2623 sc->sc_wdcdev.irqack = pciide_irqack; 2624 } 2625 2626 sc->sc_wdcdev.PIO_cap = 4; 2627 sc->sc_wdcdev.DMA_cap = 2; 2628 sc->sc_wdcdev.UDMA_cap = 2; 2629 sc->sc_wdcdev.set_modes = acer_setup_channel; 2630 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2631 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2632 2633 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2634 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2635 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2636 2637 /* Enable "microsoft register bits" R/W. */ 2638 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2639 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2640 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2641 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2642 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2643 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2644 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2645 ~ACER_CHANSTATUSREGS_RO); 2646 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2647 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2648 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2649 /* Don't use cr, re-read the real register content instead */ 2650 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2651 PCI_CLASS_REG)); 2652 2653 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2654 cp = &sc->pciide_channels[channel]; 2655 if (pciide_chansetup(sc, channel, interface) == 0) 2656 continue; 2657 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2658 printf("%s: %s channel ignored (disabled)\n", 2659 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2660 continue; 2661 } 2662 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2663 acer_pci_intr); 2664 if (cp->hw_ok == 0) 2665 continue; 2666 if (pciide_chan_candisable(cp)) { 2667 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2668 pci_conf_write(sc->sc_pc, sc->sc_tag, 2669 PCI_CLASS_REG, cr); 2670 } 2671 pciide_map_compat_intr(pa, cp, channel, interface); 2672 acer_setup_channel(&cp->wdc_channel); 2673 } 2674 } 2675 2676 void 2677 acer_setup_channel(chp) 2678 struct channel_softc *chp; 2679 { 2680 struct ata_drive_datas *drvp; 2681 int drive; 2682 u_int32_t acer_fifo_udma; 2683 u_int32_t idedma_ctl; 2684 struct pciide_channel *cp = (struct pciide_channel*)chp; 2685 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2686 2687 idedma_ctl = 0; 2688 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2689 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2690 acer_fifo_udma), DEBUG_PROBE); 2691 /* setup DMA if needed */ 2692 pciide_channel_dma_setup(cp); 2693 2694 for (drive = 0; drive < 2; drive++) { 2695 drvp = &chp->ch_drive[drive]; 2696 /* If no drive, skip */ 2697 if ((drvp->drive_flags & DRIVE) == 0) 2698 continue; 2699 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2700 "channel %d drive %d 0x%x\n", chp->channel, drive, 2701 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2702 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2703 /* clear FIFO/DMA mode */ 2704 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2705 ACER_UDMA_EN(chp->channel, drive) | 2706 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2707 2708 /* add timing values, setup DMA if needed */ 2709 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2710 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2711 acer_fifo_udma |= 2712 ACER_FTH_OPL(chp->channel, drive, 0x1); 2713 goto pio; 2714 } 2715 2716 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2717 if (drvp->drive_flags & DRIVE_UDMA) { 2718 /* use Ultra/DMA */ 2719 drvp->drive_flags &= ~DRIVE_DMA; 2720 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2721 acer_fifo_udma |= 2722 ACER_UDMA_TIM(chp->channel, drive, 2723 acer_udma[drvp->UDMA_mode]); 2724 } else { 2725 /* 2726 * use Multiword DMA 2727 * Timings will be used for both PIO and DMA, 2728 * so adjust DMA mode if needed 2729 */ 2730 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2731 drvp->PIO_mode = drvp->DMA_mode + 2; 2732 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2733 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2734 drvp->PIO_mode - 2 : 0; 2735 if (drvp->DMA_mode == 0) 2736 drvp->PIO_mode = 0; 2737 } 2738 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2739 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2740 ACER_IDETIM(chp->channel, drive), 2741 acer_pio[drvp->PIO_mode]); 2742 } 2743 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2744 acer_fifo_udma), DEBUG_PROBE); 2745 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2746 if (idedma_ctl != 0) { 2747 /* Add software bits in status register */ 2748 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2749 IDEDMA_CTL, idedma_ctl); 2750 } 2751 pciide_print_modes(cp); 2752 } 2753 2754 int 2755 acer_pci_intr(arg) 2756 void *arg; 2757 { 2758 struct pciide_softc *sc = arg; 2759 struct pciide_channel *cp; 2760 struct channel_softc *wdc_cp; 2761 int i, rv, crv; 2762 u_int32_t chids; 2763 2764 rv = 0; 2765 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2766 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2767 cp = &sc->pciide_channels[i]; 2768 wdc_cp = &cp->wdc_channel; 2769 /* If a compat channel skip. */ 2770 if (cp->compat) 2771 continue; 2772 if (chids & ACER_CHIDS_INT(i)) { 2773 crv = wdcintr(wdc_cp); 2774 if (crv == 0) 2775 printf("%s:%d: bogus intr\n", 2776 sc->sc_wdcdev.sc_dev.dv_xname, i); 2777 else 2778 rv = 1; 2779 } 2780 } 2781 return rv; 2782 } 2783 2784 void 2785 hpt_chip_map(sc, pa) 2786 struct pciide_softc *sc; 2787 struct pci_attach_args *pa; 2788 { 2789 struct pciide_channel *cp; 2790 int i, compatchan, revision; 2791 pcireg_t interface; 2792 bus_size_t cmdsize, ctlsize; 2793 2794 if (pciide_chipen(sc, pa) == 0) 2795 return; 2796 revision = PCI_REVISION(pa->pa_class); 2797 2798 /* 2799 * when the chip is in native mode it identifies itself as a 2800 * 'misc mass storage'. Fake interface in this case. 2801 */ 2802 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2803 interface = PCI_INTERFACE(pa->pa_class); 2804 } else { 2805 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2806 PCIIDE_INTERFACE_PCI(0); 2807 if (revision == HPT370_REV) 2808 interface |= PCIIDE_INTERFACE_PCI(1); 2809 } 2810 2811 printf("%s: bus-master DMA support present", 2812 sc->sc_wdcdev.sc_dev.dv_xname); 2813 pciide_mapreg_dma(sc, pa); 2814 printf("\n"); 2815 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2816 WDC_CAPABILITY_MODE; 2817 if (sc->sc_dma_ok) { 2818 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2819 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2820 sc->sc_wdcdev.irqack = pciide_irqack; 2821 } 2822 sc->sc_wdcdev.PIO_cap = 4; 2823 sc->sc_wdcdev.DMA_cap = 2; 2824 sc->sc_wdcdev.UDMA_cap = 4; 2825 2826 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2827 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2828 sc->sc_wdcdev.nchannels = (revision == HPT366_REV) ? 1 : 2; 2829 if (revision == HPT366_REV) { 2830 /* 2831 * The 366 has 2 PCI IDE functions, one for primary and one 2832 * for secondary. So we need to call pciide_mapregs_compat() 2833 * with the real channel 2834 */ 2835 if (pa->pa_function == 0) { 2836 compatchan = 0; 2837 } else if (pa->pa_function == 1) { 2838 compatchan = 1; 2839 } else { 2840 printf("%s: unexpected PCI function %d\n", 2841 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2842 return; 2843 } 2844 sc->sc_wdcdev.nchannels = 1; 2845 } else { 2846 sc->sc_wdcdev.nchannels = 2; 2847 } 2848 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2849 cp = &sc->pciide_channels[i]; 2850 if (sc->sc_wdcdev.nchannels > 1) { 2851 compatchan = i; 2852 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2853 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2854 printf("%s: %s channel ignored (disabled)\n", 2855 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2856 continue; 2857 } 2858 } 2859 if (pciide_chansetup(sc, i, interface) == 0) 2860 continue; 2861 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2862 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2863 &ctlsize, hpt_pci_intr); 2864 } else { 2865 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2866 &cmdsize, &ctlsize); 2867 } 2868 if (cp->hw_ok == 0) 2869 return; 2870 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2871 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2872 wdcattach(&cp->wdc_channel); 2873 hpt_setup_channel(&cp->wdc_channel); 2874 } 2875 2876 return; 2877 } 2878 2879 2880 void 2881 hpt_setup_channel(chp) 2882 struct channel_softc *chp; 2883 { 2884 struct ata_drive_datas *drvp; 2885 int drive; 2886 int cable; 2887 u_int32_t before, after; 2888 u_int32_t idedma_ctl; 2889 struct pciide_channel *cp = (struct pciide_channel*)chp; 2890 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2891 2892 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 2893 2894 /* setup DMA if needed */ 2895 pciide_channel_dma_setup(cp); 2896 2897 idedma_ctl = 0; 2898 2899 /* Per drive settings */ 2900 for (drive = 0; drive < 2; drive++) { 2901 drvp = &chp->ch_drive[drive]; 2902 /* If no drive, skip */ 2903 if ((drvp->drive_flags & DRIVE) == 0) 2904 continue; 2905 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 2906 HPT_IDETIM(chp->channel, drive)); 2907 2908 /* add timing values, setup DMA if needed */ 2909 if (drvp->drive_flags & DRIVE_UDMA) { 2910 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 2911 drvp->UDMA_mode > 2) 2912 drvp->UDMA_mode = 2; 2913 after = (sc->sc_wdcdev.nchannels == 2) ? 2914 hpt370_udma[drvp->UDMA_mode] : 2915 hpt366_udma[drvp->UDMA_mode]; 2916 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2917 } else if (drvp->drive_flags & DRIVE_DMA) { 2918 /* 2919 * use Multiword DMA. 2920 * Timings will be used for both PIO and DMA, so adjust 2921 * DMA mode if needed 2922 */ 2923 if (drvp->PIO_mode >= 3 && 2924 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2925 drvp->DMA_mode = drvp->PIO_mode - 2; 2926 } 2927 after = (sc->sc_wdcdev.nchannels == 2) ? 2928 hpt370_dma[drvp->DMA_mode] : 2929 hpt366_dma[drvp->DMA_mode]; 2930 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2931 } else { 2932 /* PIO only */ 2933 after = (sc->sc_wdcdev.nchannels == 2) ? 2934 hpt370_pio[drvp->PIO_mode] : 2935 hpt366_pio[drvp->PIO_mode]; 2936 } 2937 pci_conf_write(sc->sc_pc, sc->sc_tag, 2938 HPT_IDETIM(chp->channel, drive), after); 2939 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 2940 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 2941 after, before), DEBUG_PROBE); 2942 } 2943 if (idedma_ctl != 0) { 2944 /* Add software bits in status register */ 2945 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2946 IDEDMA_CTL, idedma_ctl); 2947 } 2948 pciide_print_modes(cp); 2949 } 2950 2951 int 2952 hpt_pci_intr(arg) 2953 void *arg; 2954 { 2955 struct pciide_softc *sc = arg; 2956 struct pciide_channel *cp; 2957 struct channel_softc *wdc_cp; 2958 int rv = 0; 2959 int dmastat, i, crv; 2960 2961 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2962 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2963 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 2964 if((dmastat & IDEDMA_CTL_INTR) == 0) 2965 continue; 2966 cp = &sc->pciide_channels[i]; 2967 wdc_cp = &cp->wdc_channel; 2968 crv = wdcintr(wdc_cp); 2969 if (crv == 0) { 2970 printf("%s:%d: bogus intr\n", 2971 sc->sc_wdcdev.sc_dev.dv_xname, i); 2972 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2973 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 2974 } else 2975 rv = 1; 2976 } 2977 return rv; 2978 } 2979 2980 2981 /* A macro to test product */ 2982 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 2983 2984 void 2985 pdc202xx_chip_map(sc, pa) 2986 struct pciide_softc *sc; 2987 struct pci_attach_args *pa; 2988 { 2989 struct pciide_channel *cp; 2990 int channel; 2991 pcireg_t interface, st, mode; 2992 bus_size_t cmdsize, ctlsize; 2993 2994 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2995 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 2996 DEBUG_PROBE); 2997 if (pciide_chipen(sc, pa) == 0) 2998 return; 2999 3000 /* turn off RAID mode */ 3001 st &= ~PDC2xx_STATE_IDERAID; 3002 3003 /* 3004 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3005 * mode. We have to fake interface 3006 */ 3007 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3008 if (st & PDC2xx_STATE_NATIVE) 3009 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3010 3011 printf("%s: bus-master DMA support present", 3012 sc->sc_wdcdev.sc_dev.dv_xname); 3013 pciide_mapreg_dma(sc, pa); 3014 printf("\n"); 3015 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3016 WDC_CAPABILITY_MODE; 3017 if (sc->sc_dma_ok) { 3018 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3019 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3020 sc->sc_wdcdev.irqack = pciide_irqack; 3021 } 3022 sc->sc_wdcdev.PIO_cap = 4; 3023 sc->sc_wdcdev.DMA_cap = 2; 3024 if (PDC_IS_262(sc)) 3025 sc->sc_wdcdev.UDMA_cap = 4; 3026 else 3027 sc->sc_wdcdev.UDMA_cap = 2; 3028 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3029 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3030 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3031 3032 /* setup failsafe defaults */ 3033 mode = 0; 3034 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3035 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3036 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3037 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3038 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3039 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3040 "initial timings 0x%x, now 0x%x\n", channel, 3041 pci_conf_read(sc->sc_pc, sc->sc_tag, 3042 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3043 DEBUG_PROBE); 3044 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3045 mode | PDC2xx_TIM_IORDYp); 3046 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3047 "initial timings 0x%x, now 0x%x\n", channel, 3048 pci_conf_read(sc->sc_pc, sc->sc_tag, 3049 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3050 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3051 mode); 3052 } 3053 3054 mode = PDC2xx_SCR_DMA; 3055 if (PDC_IS_262(sc)) { 3056 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3057 } else { 3058 /* the BIOS set it up this way */ 3059 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3060 } 3061 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3062 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3063 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3064 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3065 DEBUG_PROBE); 3066 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3067 3068 /* controller initial state register is OK even without BIOS */ 3069 /* Set DMA mode to IDE DMA compatibility */ 3070 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3071 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3072 DEBUG_PROBE); 3073 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3074 mode | 0x1); 3075 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3076 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3077 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3078 mode | 0x1); 3079 3080 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3081 cp = &sc->pciide_channels[channel]; 3082 if (pciide_chansetup(sc, channel, interface) == 0) 3083 continue; 3084 if ((st & (PDC_IS_262(sc) ? 3085 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3086 printf("%s: %s channel ignored (disabled)\n", 3087 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3088 continue; 3089 } 3090 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3091 pdc202xx_pci_intr); 3092 if (cp->hw_ok == 0) 3093 continue; 3094 if (pciide_chan_candisable(cp)) 3095 st &= ~(PDC_IS_262(sc) ? 3096 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3097 pciide_map_compat_intr(pa, cp, channel, interface); 3098 pdc202xx_setup_channel(&cp->wdc_channel); 3099 } 3100 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3101 DEBUG_PROBE); 3102 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3103 return; 3104 } 3105 3106 void 3107 pdc202xx_setup_channel(chp) 3108 struct channel_softc *chp; 3109 { 3110 struct ata_drive_datas *drvp; 3111 int drive; 3112 pcireg_t mode, st; 3113 u_int32_t idedma_ctl, scr, atapi; 3114 struct pciide_channel *cp = (struct pciide_channel*)chp; 3115 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3116 int channel = chp->channel; 3117 3118 /* setup DMA if needed */ 3119 pciide_channel_dma_setup(cp); 3120 3121 idedma_ctl = 0; 3122 3123 /* Per channel settings */ 3124 if (PDC_IS_262(sc)) { 3125 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3126 PDC262_U66); 3127 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3128 /* Trimm UDMA mode */ 3129 if ((st & PDC262_STATE_80P(channel)) != 0 || 3130 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3131 chp->ch_drive[0].UDMA_mode <= 2) || 3132 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3133 chp->ch_drive[1].UDMA_mode <= 2)) { 3134 if (chp->ch_drive[0].UDMA_mode > 2) 3135 chp->ch_drive[0].UDMA_mode = 2; 3136 if (chp->ch_drive[1].UDMA_mode > 2) 3137 chp->ch_drive[1].UDMA_mode = 2; 3138 } 3139 /* Set U66 if needed */ 3140 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3141 chp->ch_drive[0].UDMA_mode > 2) || 3142 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3143 chp->ch_drive[1].UDMA_mode > 2)) 3144 scr |= PDC262_U66_EN(channel); 3145 else 3146 scr &= ~PDC262_U66_EN(channel); 3147 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3148 PDC262_U66, scr); 3149 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3150 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3151 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3152 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3153 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3154 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3155 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3156 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3157 atapi = 0; 3158 else 3159 atapi = PDC262_ATAPI_UDMA; 3160 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3161 PDC262_ATAPI(channel), atapi); 3162 } 3163 } 3164 for (drive = 0; drive < 2; drive++) { 3165 drvp = &chp->ch_drive[drive]; 3166 /* If no drive, skip */ 3167 if ((drvp->drive_flags & DRIVE) == 0) 3168 continue; 3169 mode = 0; 3170 if (drvp->drive_flags & DRIVE_UDMA) { 3171 mode = PDC2xx_TIM_SET_MB(mode, 3172 pdc2xx_udma_mb[drvp->UDMA_mode]); 3173 mode = PDC2xx_TIM_SET_MC(mode, 3174 pdc2xx_udma_mc[drvp->UDMA_mode]); 3175 drvp->drive_flags &= ~DRIVE_DMA; 3176 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3177 } else if (drvp->drive_flags & DRIVE_DMA) { 3178 mode = PDC2xx_TIM_SET_MB(mode, 3179 pdc2xx_dma_mb[drvp->DMA_mode]); 3180 mode = PDC2xx_TIM_SET_MC(mode, 3181 pdc2xx_dma_mc[drvp->DMA_mode]); 3182 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3183 } else { 3184 mode = PDC2xx_TIM_SET_MB(mode, 3185 pdc2xx_dma_mb[0]); 3186 mode = PDC2xx_TIM_SET_MC(mode, 3187 pdc2xx_dma_mc[0]); 3188 } 3189 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3190 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3191 if (drvp->drive_flags & DRIVE_ATA) 3192 mode |= PDC2xx_TIM_PRE; 3193 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3194 if (drvp->PIO_mode >= 3) { 3195 mode |= PDC2xx_TIM_IORDY; 3196 if (drive == 0) 3197 mode |= PDC2xx_TIM_IORDYp; 3198 } 3199 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3200 "timings 0x%x\n", 3201 sc->sc_wdcdev.sc_dev.dv_xname, 3202 chp->channel, drive, mode), DEBUG_PROBE); 3203 pci_conf_write(sc->sc_pc, sc->sc_tag, 3204 PDC2xx_TIM(chp->channel, drive), mode); 3205 } 3206 if (idedma_ctl != 0) { 3207 /* Add software bits in status register */ 3208 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3209 IDEDMA_CTL, idedma_ctl); 3210 } 3211 pciide_print_modes(cp); 3212 } 3213 3214 int 3215 pdc202xx_pci_intr(arg) 3216 void *arg; 3217 { 3218 struct pciide_softc *sc = arg; 3219 struct pciide_channel *cp; 3220 struct channel_softc *wdc_cp; 3221 int i, rv, crv; 3222 u_int32_t scr; 3223 3224 rv = 0; 3225 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3226 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3227 cp = &sc->pciide_channels[i]; 3228 wdc_cp = &cp->wdc_channel; 3229 /* If a compat channel skip. */ 3230 if (cp->compat) 3231 continue; 3232 if (scr & PDC2xx_SCR_INT(i)) { 3233 crv = wdcintr(wdc_cp); 3234 if (crv == 0) 3235 printf("%s:%d: bogus intr\n", 3236 sc->sc_wdcdev.sc_dev.dv_xname, i); 3237 else 3238 rv = 1; 3239 } 3240 } 3241 return rv; 3242 } 3243 3244 void 3245 opti_chip_map(sc, pa) 3246 struct pciide_softc *sc; 3247 struct pci_attach_args *pa; 3248 { 3249 struct pciide_channel *cp; 3250 bus_size_t cmdsize, ctlsize; 3251 pcireg_t interface; 3252 u_int8_t init_ctrl; 3253 int channel; 3254 3255 if (pciide_chipen(sc, pa) == 0) 3256 return; 3257 printf("%s: bus-master DMA support present", 3258 sc->sc_wdcdev.sc_dev.dv_xname); 3259 pciide_mapreg_dma(sc, pa); 3260 printf("\n"); 3261 3262 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3263 WDC_CAPABILITY_MODE; 3264 sc->sc_wdcdev.PIO_cap = 4; 3265 if (sc->sc_dma_ok) { 3266 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3267 sc->sc_wdcdev.irqack = pciide_irqack; 3268 sc->sc_wdcdev.DMA_cap = 2; 3269 } 3270 sc->sc_wdcdev.set_modes = opti_setup_channel; 3271 3272 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3273 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3274 3275 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3276 OPTI_REG_INIT_CONTROL); 3277 3278 interface = PCI_INTERFACE(pa->pa_class); 3279 3280 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3281 cp = &sc->pciide_channels[channel]; 3282 if (pciide_chansetup(sc, channel, interface) == 0) 3283 continue; 3284 if (channel == 1 && 3285 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3286 printf("%s: %s channel ignored (disabled)\n", 3287 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3288 continue; 3289 } 3290 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3291 pciide_pci_intr); 3292 if (cp->hw_ok == 0) 3293 continue; 3294 pciide_map_compat_intr(pa, cp, channel, interface); 3295 if (cp->hw_ok == 0) 3296 continue; 3297 opti_setup_channel(&cp->wdc_channel); 3298 } 3299 } 3300 3301 void 3302 opti_setup_channel(chp) 3303 struct channel_softc *chp; 3304 { 3305 struct ata_drive_datas *drvp; 3306 struct pciide_channel *cp = (struct pciide_channel*)chp; 3307 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3308 int drive, spd; 3309 int mode[2]; 3310 u_int8_t rv, mr; 3311 3312 /* 3313 * The `Delay' and `Address Setup Time' fields of the 3314 * Miscellaneous Register are always zero initially. 3315 */ 3316 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3317 mr &= ~(OPTI_MISC_DELAY_MASK | 3318 OPTI_MISC_ADDR_SETUP_MASK | 3319 OPTI_MISC_INDEX_MASK); 3320 3321 /* Prime the control register before setting timing values */ 3322 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3323 3324 /* Determine the clockrate of the PCIbus the chip is attached to */ 3325 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3326 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3327 3328 /* setup DMA if needed */ 3329 pciide_channel_dma_setup(cp); 3330 3331 for (drive = 0; drive < 2; drive++) { 3332 drvp = &chp->ch_drive[drive]; 3333 /* If no drive, skip */ 3334 if ((drvp->drive_flags & DRIVE) == 0) { 3335 mode[drive] = -1; 3336 continue; 3337 } 3338 3339 if ((drvp->drive_flags & DRIVE_DMA)) { 3340 /* 3341 * Timings will be used for both PIO and DMA, 3342 * so adjust DMA mode if needed 3343 */ 3344 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3345 drvp->PIO_mode = drvp->DMA_mode + 2; 3346 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3347 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3348 drvp->PIO_mode - 2 : 0; 3349 if (drvp->DMA_mode == 0) 3350 drvp->PIO_mode = 0; 3351 3352 mode[drive] = drvp->DMA_mode + 5; 3353 } else 3354 mode[drive] = drvp->PIO_mode; 3355 3356 if (drive && mode[0] >= 0 && 3357 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3358 /* 3359 * Can't have two drives using different values 3360 * for `Address Setup Time'. 3361 * Slow down the faster drive to compensate. 3362 */ 3363 int d = (opti_tim_as[spd][mode[0]] > 3364 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3365 3366 mode[d] = mode[1-d]; 3367 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3368 chp->ch_drive[d].DMA_mode = 0; 3369 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3370 } 3371 } 3372 3373 for (drive = 0; drive < 2; drive++) { 3374 int m; 3375 if ((m = mode[drive]) < 0) 3376 continue; 3377 3378 /* Set the Address Setup Time and select appropriate index */ 3379 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3380 rv |= OPTI_MISC_INDEX(drive); 3381 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3382 3383 /* Set the pulse width and recovery timing parameters */ 3384 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3385 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3386 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3387 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3388 3389 /* Set the Enhanced Mode register appropriately */ 3390 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3391 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3392 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3393 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3394 } 3395 3396 /* Finally, enable the timings */ 3397 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3398 3399 pciide_print_modes(cp); 3400 } 3401
Indexes created Thu Oct 02 10:09:58 GMT 2025