pciide.c revision 1.68.2.6
1 /* $NetBSD: pciide.c,v 1.68.2.6 2000/07/07 11:49:14 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <vm/vm.h> 102 #include <vm/vm_param.h> 103 #include <vm/vm_kern.h> 104 105 #include <dev/pci/pcireg.h> 106 #include <dev/pci/pcivar.h> 107 #include <dev/pci/pcidevs.h> 108 #include <dev/pci/pciidereg.h> 109 #include <dev/pci/pciidevar.h> 110 #include <dev/pci/pciide_piix_reg.h> 111 #include <dev/pci/pciide_amd_reg.h> 112 #include <dev/pci/pciide_apollo_reg.h> 113 #include <dev/pci/pciide_cmd_reg.h> 114 #include <dev/pci/pciide_cy693_reg.h> 115 #include <dev/pci/pciide_sis_reg.h> 116 #include <dev/pci/pciide_acer_reg.h> 117 #include <dev/pci/pciide_pdc202xx_reg.h> 118 #include <dev/pci/pciide_opti_reg.h> 119 #include <dev/pci/pciide_hpt_reg.h> 120 #include <dev/pci/cy82c693var.h> 121 122 /* inlines for reading/writing 8-bit PCI registers */ 123 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 124 int)); 125 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 126 int, u_int8_t)); 127 128 static __inline u_int8_t 129 pciide_pci_read(pc, pa, reg) 130 pci_chipset_tag_t pc; 131 pcitag_t pa; 132 int reg; 133 { 134 135 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 136 ((reg & 0x03) * 8) & 0xff); 137 } 138 139 static __inline void 140 pciide_pci_write(pc, pa, reg, val) 141 pci_chipset_tag_t pc; 142 pcitag_t pa; 143 int reg; 144 u_int8_t val; 145 { 146 pcireg_t pcival; 147 148 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 149 pcival &= ~(0xff << ((reg & 0x03) * 8)); 150 pcival |= (val << ((reg & 0x03) * 8)); 151 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 152 } 153 154 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 155 156 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 157 void piix_setup_channel __P((struct channel_softc*)); 158 void piix3_4_setup_channel __P((struct channel_softc*)); 159 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 160 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 161 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 162 163 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 164 void amd756_setup_channel __P((struct channel_softc*)); 165 166 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 167 void apollo_setup_channel __P((struct channel_softc*)); 168 169 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 170 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void cmd0643_9_setup_channel __P((struct channel_softc*)); 172 void cmd_channel_map __P((struct pci_attach_args *, 173 struct pciide_softc *, int)); 174 int cmd_pci_intr __P((void *)); 175 void cmd648_9_irqack __P((struct channel_softc *)); 176 177 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void cy693_setup_channel __P((struct channel_softc*)); 179 180 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void sis_setup_channel __P((struct channel_softc*)); 182 183 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 184 void acer_setup_channel __P((struct channel_softc*)); 185 int acer_pci_intr __P((void *)); 186 187 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 188 void pdc202xx_setup_channel __P((struct channel_softc*)); 189 int pdc202xx_pci_intr __P((void *)); 190 191 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 192 void opti_setup_channel __P((struct channel_softc*)); 193 194 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 195 void hpt_setup_channel __P((struct channel_softc*)); 196 int hpt_pci_intr __P((void *)); 197 198 void pciide_channel_dma_setup __P((struct pciide_channel *)); 199 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 200 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 201 void pciide_dma_start __P((void*, int, int)); 202 int pciide_dma_finish __P((void*, int, int, int)); 203 void pciide_irqack __P((struct channel_softc *)); 204 void pciide_print_modes __P((struct pciide_channel *)); 205 206 struct pciide_product_desc { 207 u_int32_t ide_product; 208 int ide_flags; 209 const char *ide_name; 210 /* map and setup chip, probe drives */ 211 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 212 }; 213 214 /* Flags for ide_flags */ 215 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 216 217 /* Default product description for devices not known from this controller */ 218 const struct pciide_product_desc default_product_desc = { 219 0, 220 0, 221 "Generic PCI IDE controller", 222 default_chip_map, 223 }; 224 225 const struct pciide_product_desc pciide_intel_products[] = { 226 { PCI_PRODUCT_INTEL_82092AA, 227 0, 228 "Intel 82092AA IDE controller", 229 default_chip_map, 230 }, 231 { PCI_PRODUCT_INTEL_82371FB_IDE, 232 0, 233 "Intel 82371FB IDE controller (PIIX)", 234 piix_chip_map, 235 }, 236 { PCI_PRODUCT_INTEL_82371SB_IDE, 237 0, 238 "Intel 82371SB IDE Interface (PIIX3)", 239 piix_chip_map, 240 }, 241 { PCI_PRODUCT_INTEL_82371AB_IDE, 242 0, 243 "Intel 82371AB IDE controller (PIIX4)", 244 piix_chip_map, 245 }, 246 { PCI_PRODUCT_INTEL_82801AA_IDE, 247 0, 248 "Intel 82801AA IDE Controller (ICH)", 249 piix_chip_map, 250 }, 251 { PCI_PRODUCT_INTEL_82801AB_IDE, 252 0, 253 "Intel 82801AB IDE Controller (ICH0)", 254 piix_chip_map, 255 }, 256 { 0, 257 0, 258 NULL, 259 } 260 }; 261 262 const struct pciide_product_desc pciide_amd_products[] = { 263 { PCI_PRODUCT_AMD_PBC756_IDE, 264 0, 265 "Advanced Micro Devices AMD756 IDE Controller", 266 amd756_chip_map 267 }, 268 { 0, 269 0, 270 NULL, 271 } 272 }; 273 274 const struct pciide_product_desc pciide_cmd_products[] = { 275 { PCI_PRODUCT_CMDTECH_640, 276 0, 277 "CMD Technology PCI0640", 278 cmd_chip_map 279 }, 280 { PCI_PRODUCT_CMDTECH_643, 281 0, 282 "CMD Technology PCI0643", 283 cmd0643_9_chip_map, 284 }, 285 { PCI_PRODUCT_CMDTECH_646, 286 0, 287 "CMD Technology PCI0646", 288 cmd0643_9_chip_map, 289 }, 290 { PCI_PRODUCT_CMDTECH_648, 291 IDE_PCI_CLASS_OVERRIDE, 292 "CMD Technology PCI0648", 293 cmd0643_9_chip_map, 294 }, 295 { PCI_PRODUCT_CMDTECH_649, 296 IDE_PCI_CLASS_OVERRIDE, 297 "CMD Technology PCI0649", 298 cmd0643_9_chip_map, 299 }, 300 { 0, 301 0, 302 NULL, 303 } 304 }; 305 306 const struct pciide_product_desc pciide_via_products[] = { 307 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 308 0, 309 "VIA Tech VT82C586 IDE Controller", 310 apollo_chip_map, 311 }, 312 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 313 0, 314 "VIA Tech VT82C586A IDE Controller", 315 apollo_chip_map, 316 }, 317 { 0, 318 0, 319 NULL, 320 } 321 }; 322 323 const struct pciide_product_desc pciide_cypress_products[] = { 324 { PCI_PRODUCT_CONTAQ_82C693, 325 0, 326 "Cypress 82C693 IDE Controller", 327 cy693_chip_map, 328 }, 329 { 0, 330 0, 331 NULL, 332 } 333 }; 334 335 const struct pciide_product_desc pciide_sis_products[] = { 336 { PCI_PRODUCT_SIS_5597_IDE, 337 0, 338 "Silicon Integrated System 5597/5598 IDE controller", 339 sis_chip_map, 340 }, 341 { 0, 342 0, 343 NULL, 344 } 345 }; 346 347 const struct pciide_product_desc pciide_acer_products[] = { 348 { PCI_PRODUCT_ALI_M5229, 349 0, 350 "Acer Labs M5229 UDMA IDE Controller", 351 acer_chip_map, 352 }, 353 { 0, 354 0, 355 NULL, 356 } 357 }; 358 359 const struct pciide_product_desc pciide_promise_products[] = { 360 { PCI_PRODUCT_PROMISE_ULTRA33, 361 IDE_PCI_CLASS_OVERRIDE, 362 "Promise Ultra33/ATA Bus Master IDE Accelerator", 363 pdc202xx_chip_map, 364 }, 365 { PCI_PRODUCT_PROMISE_ULTRA66, 366 IDE_PCI_CLASS_OVERRIDE, 367 "Promise Ultra66/ATA Bus Master IDE Accelerator", 368 pdc202xx_chip_map, 369 }, 370 { PCI_PRODUCT_PROMISE_ULTRA100, 371 IDE_PCI_CLASS_OVERRIDE, 372 "Promise Ultra100/ATA Bus Master IDE Accelerator", 373 pdc202xx_chip_map, 374 }, 375 { 0, 376 0, 377 NULL, 378 } 379 }; 380 381 const struct pciide_product_desc pciide_opti_products[] = { 382 { PCI_PRODUCT_OPTI_82C621, 383 0, 384 "OPTi 82c621 PCI IDE controller", 385 opti_chip_map, 386 }, 387 { PCI_PRODUCT_OPTI_82C568, 388 0, 389 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 390 opti_chip_map, 391 }, 392 { PCI_PRODUCT_OPTI_82D568, 393 0, 394 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 395 opti_chip_map, 396 }, 397 { 0, 398 0, 399 NULL, 400 } 401 }; 402 403 const struct pciide_product_desc pciide_triones_products[] = { 404 { PCI_PRODUCT_TRIONES_HPT366, 405 IDE_PCI_CLASS_OVERRIDE, 406 "Triones/Highpoint HPT366/370 IDE Controller", 407 hpt_chip_map, 408 }, 409 { 0, 410 0, 411 NULL, 412 } 413 }; 414 415 struct pciide_vendor_desc { 416 u_int32_t ide_vendor; 417 const struct pciide_product_desc *ide_products; 418 }; 419 420 const struct pciide_vendor_desc pciide_vendors[] = { 421 { PCI_VENDOR_INTEL, pciide_intel_products }, 422 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 423 { PCI_VENDOR_VIATECH, pciide_via_products }, 424 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 425 { PCI_VENDOR_SIS, pciide_sis_products }, 426 { PCI_VENDOR_ALI, pciide_acer_products }, 427 { PCI_VENDOR_PROMISE, pciide_promise_products }, 428 { PCI_VENDOR_AMD, pciide_amd_products }, 429 { PCI_VENDOR_OPTI, pciide_opti_products }, 430 { PCI_VENDOR_TRIONES, pciide_triones_products }, 431 { 0, NULL } 432 }; 433 434 /* options passed via the 'flags' config keyword */ 435 #define PCIIDE_OPTIONS_DMA 0x01 436 437 int pciide_match __P((struct device *, struct cfdata *, void *)); 438 void pciide_attach __P((struct device *, struct device *, void *)); 439 440 struct cfattach pciide_ca = { 441 sizeof(struct pciide_softc), pciide_match, pciide_attach 442 }; 443 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 444 int pciide_mapregs_compat __P(( struct pci_attach_args *, 445 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 446 int pciide_mapregs_native __P((struct pci_attach_args *, 447 struct pciide_channel *, bus_size_t *, bus_size_t *, 448 int (*pci_intr) __P((void *)))); 449 void pciide_mapreg_dma __P((struct pciide_softc *, 450 struct pci_attach_args *)); 451 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 452 void pciide_mapchan __P((struct pci_attach_args *, 453 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 454 int (*pci_intr) __P((void *)))); 455 int pciide_chan_candisable __P((struct pciide_channel *)); 456 void pciide_map_compat_intr __P(( struct pci_attach_args *, 457 struct pciide_channel *, int, int)); 458 int pciide_print __P((void *, const char *pnp)); 459 int pciide_compat_intr __P((void *)); 460 int pciide_pci_intr __P((void *)); 461 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 462 463 const struct pciide_product_desc * 464 pciide_lookup_product(id) 465 u_int32_t id; 466 { 467 const struct pciide_product_desc *pp; 468 const struct pciide_vendor_desc *vp; 469 470 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 471 if (PCI_VENDOR(id) == vp->ide_vendor) 472 break; 473 474 if ((pp = vp->ide_products) == NULL) 475 return NULL; 476 477 for (; pp->ide_name != NULL; pp++) 478 if (PCI_PRODUCT(id) == pp->ide_product) 479 break; 480 481 if (pp->ide_name == NULL) 482 return NULL; 483 return pp; 484 } 485 486 int 487 pciide_match(parent, match, aux) 488 struct device *parent; 489 struct cfdata *match; 490 void *aux; 491 { 492 struct pci_attach_args *pa = aux; 493 const struct pciide_product_desc *pp; 494 495 /* 496 * Check the ID register to see that it's a PCI IDE controller. 497 * If it is, we assume that we can deal with it; it _should_ 498 * work in a standardized way... 499 */ 500 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 501 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 502 return (1); 503 } 504 505 /* 506 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 507 * controllers. Let see if we can deal with it anyway. 508 */ 509 pp = pciide_lookup_product(pa->pa_id); 510 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 511 return (1); 512 } 513 514 return (0); 515 } 516 517 void 518 pciide_attach(parent, self, aux) 519 struct device *parent, *self; 520 void *aux; 521 { 522 struct pci_attach_args *pa = aux; 523 pci_chipset_tag_t pc = pa->pa_pc; 524 pcitag_t tag = pa->pa_tag; 525 struct pciide_softc *sc = (struct pciide_softc *)self; 526 pcireg_t csr; 527 char devinfo[256]; 528 const char *displaydev; 529 530 sc->sc_pp = pciide_lookup_product(pa->pa_id); 531 if (sc->sc_pp == NULL) { 532 sc->sc_pp = &default_product_desc; 533 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 534 displaydev = devinfo; 535 } else 536 displaydev = sc->sc_pp->ide_name; 537 538 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 539 540 sc->sc_pc = pa->pa_pc; 541 sc->sc_tag = pa->pa_tag; 542 #ifdef WDCDEBUG 543 if (wdcdebug_pciide_mask & DEBUG_PROBE) 544 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 545 #endif 546 sc->sc_pp->chip_map(sc, pa); 547 548 if (sc->sc_dma_ok) { 549 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 550 csr |= PCI_COMMAND_MASTER_ENABLE; 551 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 552 } 553 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 554 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 555 } 556 557 /* tell wether the chip is enabled or not */ 558 int 559 pciide_chipen(sc, pa) 560 struct pciide_softc *sc; 561 struct pci_attach_args *pa; 562 { 563 pcireg_t csr; 564 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 565 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 566 PCI_COMMAND_STATUS_REG); 567 printf("%s: device disabled (at %s)\n", 568 sc->sc_wdcdev.sc_dev.dv_xname, 569 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 570 "device" : "bridge"); 571 return 0; 572 } 573 return 1; 574 } 575 576 int 577 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 578 struct pci_attach_args *pa; 579 struct pciide_channel *cp; 580 int compatchan; 581 bus_size_t *cmdsizep, *ctlsizep; 582 { 583 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 584 struct channel_softc *wdc_cp = &cp->wdc_channel; 585 586 cp->compat = 1; 587 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 588 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 589 590 wdc_cp->cmd_iot = pa->pa_iot; 591 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 592 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 593 printf("%s: couldn't map %s channel cmd regs\n", 594 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 595 return (0); 596 } 597 598 wdc_cp->ctl_iot = pa->pa_iot; 599 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 600 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 601 printf("%s: couldn't map %s channel ctl regs\n", 602 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 603 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 604 PCIIDE_COMPAT_CMD_SIZE); 605 return (0); 606 } 607 608 return (1); 609 } 610 611 int 612 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 613 struct pci_attach_args * pa; 614 struct pciide_channel *cp; 615 bus_size_t *cmdsizep, *ctlsizep; 616 int (*pci_intr) __P((void *)); 617 { 618 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 619 struct channel_softc *wdc_cp = &cp->wdc_channel; 620 const char *intrstr; 621 pci_intr_handle_t intrhandle; 622 623 cp->compat = 0; 624 625 if (sc->sc_pci_ih == NULL) { 626 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 627 pa->pa_intrline, &intrhandle) != 0) { 628 printf("%s: couldn't map native-PCI interrupt\n", 629 sc->sc_wdcdev.sc_dev.dv_xname); 630 return 0; 631 } 632 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 633 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 634 intrhandle, IPL_BIO, pci_intr, sc); 635 if (sc->sc_pci_ih != NULL) { 636 printf("%s: using %s for native-PCI interrupt\n", 637 sc->sc_wdcdev.sc_dev.dv_xname, 638 intrstr ? intrstr : "unknown interrupt"); 639 } else { 640 printf("%s: couldn't establish native-PCI interrupt", 641 sc->sc_wdcdev.sc_dev.dv_xname); 642 if (intrstr != NULL) 643 printf(" at %s", intrstr); 644 printf("\n"); 645 return 0; 646 } 647 } 648 cp->ih = sc->sc_pci_ih; 649 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 650 PCI_MAPREG_TYPE_IO, 0, 651 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 652 printf("%s: couldn't map %s channel cmd regs\n", 653 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 654 return 0; 655 } 656 657 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 658 PCI_MAPREG_TYPE_IO, 0, 659 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 660 printf("%s: couldn't map %s channel ctl regs\n", 661 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 662 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 663 return 0; 664 } 665 return (1); 666 } 667 668 void 669 pciide_mapreg_dma(sc, pa) 670 struct pciide_softc *sc; 671 struct pci_attach_args *pa; 672 { 673 pcireg_t maptype; 674 675 /* 676 * Map DMA registers 677 * 678 * Note that sc_dma_ok is the right variable to test to see if 679 * DMA can be done. If the interface doesn't support DMA, 680 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 681 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 682 * non-zero if the interface supports DMA and the registers 683 * could be mapped. 684 * 685 * XXX Note that despite the fact that the Bus Master IDE specs 686 * XXX say that "The bus master IDE function uses 16 bytes of IO 687 * XXX space," some controllers (at least the United 688 * XXX Microelectronics UM8886BF) place it in memory space. 689 */ 690 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 691 PCIIDE_REG_BUS_MASTER_DMA); 692 693 switch (maptype) { 694 case PCI_MAPREG_TYPE_IO: 695 case PCI_MAPREG_MEM_TYPE_32BIT: 696 sc->sc_dma_ok = (pci_mapreg_map(pa, 697 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 698 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 699 sc->sc_dmat = pa->pa_dmat; 700 if (sc->sc_dma_ok == 0) { 701 printf(", but unused (couldn't map registers)"); 702 } else { 703 sc->sc_wdcdev.dma_arg = sc; 704 sc->sc_wdcdev.dma_init = pciide_dma_init; 705 sc->sc_wdcdev.dma_start = pciide_dma_start; 706 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 707 } 708 break; 709 710 default: 711 sc->sc_dma_ok = 0; 712 printf(", but unsupported register maptype (0x%x)", maptype); 713 } 714 } 715 716 int 717 pciide_compat_intr(arg) 718 void *arg; 719 { 720 struct pciide_channel *cp = arg; 721 722 #ifdef DIAGNOSTIC 723 /* should only be called for a compat channel */ 724 if (cp->compat == 0) 725 panic("pciide compat intr called for non-compat chan %p\n", cp); 726 #endif 727 return (wdcintr(&cp->wdc_channel)); 728 } 729 730 int 731 pciide_pci_intr(arg) 732 void *arg; 733 { 734 struct pciide_softc *sc = arg; 735 struct pciide_channel *cp; 736 struct channel_softc *wdc_cp; 737 int i, rv, crv; 738 739 rv = 0; 740 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 741 cp = &sc->pciide_channels[i]; 742 wdc_cp = &cp->wdc_channel; 743 744 /* If a compat channel skip. */ 745 if (cp->compat) 746 continue; 747 /* if this channel not waiting for intr, skip */ 748 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 749 continue; 750 751 crv = wdcintr(wdc_cp); 752 if (crv == 0) 753 ; /* leave rv alone */ 754 else if (crv == 1) 755 rv = 1; /* claim the intr */ 756 else if (rv == 0) /* crv should be -1 in this case */ 757 rv = crv; /* if we've done no better, take it */ 758 } 759 return (rv); 760 } 761 762 void 763 pciide_channel_dma_setup(cp) 764 struct pciide_channel *cp; 765 { 766 int drive; 767 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 768 struct ata_drive_datas *drvp; 769 770 for (drive = 0; drive < 2; drive++) { 771 drvp = &cp->wdc_channel.ch_drive[drive]; 772 /* If no drive, skip */ 773 if ((drvp->drive_flags & DRIVE) == 0) 774 continue; 775 /* setup DMA if needed */ 776 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 777 (drvp->drive_flags & DRIVE_UDMA) == 0) || 778 sc->sc_dma_ok == 0) { 779 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 780 continue; 781 } 782 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 783 != 0) { 784 /* Abort DMA setup */ 785 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 786 continue; 787 } 788 } 789 } 790 791 int 792 pciide_dma_table_setup(sc, channel, drive) 793 struct pciide_softc *sc; 794 int channel, drive; 795 { 796 bus_dma_segment_t seg; 797 int error, rseg; 798 const bus_size_t dma_table_size = 799 sizeof(struct idedma_table) * NIDEDMA_TABLES; 800 struct pciide_dma_maps *dma_maps = 801 &sc->pciide_channels[channel].dma_maps[drive]; 802 803 /* If table was already allocated, just return */ 804 if (dma_maps->dma_table) 805 return 0; 806 807 /* Allocate memory for the DMA tables and map it */ 808 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 809 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 810 BUS_DMA_NOWAIT)) != 0) { 811 printf("%s:%d: unable to allocate table DMA for " 812 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 813 channel, drive, error); 814 return error; 815 } 816 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 817 dma_table_size, 818 (caddr_t *)&dma_maps->dma_table, 819 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 820 printf("%s:%d: unable to map table DMA for" 821 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 822 channel, drive, error); 823 return error; 824 } 825 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 826 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 827 seg.ds_addr), DEBUG_PROBE); 828 829 /* Create and load table DMA map for this disk */ 830 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 831 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 832 &dma_maps->dmamap_table)) != 0) { 833 printf("%s:%d: unable to create table DMA map for " 834 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 835 channel, drive, error); 836 return error; 837 } 838 if ((error = bus_dmamap_load(sc->sc_dmat, 839 dma_maps->dmamap_table, 840 dma_maps->dma_table, 841 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 842 printf("%s:%d: unable to load table DMA map for " 843 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 844 channel, drive, error); 845 return error; 846 } 847 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 848 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 849 /* Create a xfer DMA map for this drive */ 850 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 851 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 852 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 853 &dma_maps->dmamap_xfer)) != 0) { 854 printf("%s:%d: unable to create xfer DMA map for " 855 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 856 channel, drive, error); 857 return error; 858 } 859 return 0; 860 } 861 862 int 863 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 864 void *v; 865 int channel, drive; 866 void *databuf; 867 size_t datalen; 868 int flags; 869 { 870 struct pciide_softc *sc = v; 871 int error, seg; 872 struct pciide_dma_maps *dma_maps = 873 &sc->pciide_channels[channel].dma_maps[drive]; 874 875 error = bus_dmamap_load(sc->sc_dmat, 876 dma_maps->dmamap_xfer, 877 databuf, datalen, NULL, BUS_DMA_NOWAIT); 878 if (error) { 879 printf("%s:%d: unable to load xfer DMA map for" 880 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 881 channel, drive, error); 882 return error; 883 } 884 885 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 886 dma_maps->dmamap_xfer->dm_mapsize, 887 (flags & WDC_DMA_READ) ? 888 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 889 890 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 891 #ifdef DIAGNOSTIC 892 /* A segment must not cross a 64k boundary */ 893 { 894 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 895 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 896 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 897 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 898 printf("pciide_dma: segment %d physical addr 0x%lx" 899 " len 0x%lx not properly aligned\n", 900 seg, phys, len); 901 panic("pciide_dma: buf align"); 902 } 903 } 904 #endif 905 dma_maps->dma_table[seg].base_addr = 906 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 907 dma_maps->dma_table[seg].byte_count = 908 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 909 IDEDMA_BYTE_COUNT_MASK); 910 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 911 seg, le32toh(dma_maps->dma_table[seg].byte_count), 912 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 913 914 } 915 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 916 htole32(IDEDMA_BYTE_COUNT_EOT); 917 918 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 919 dma_maps->dmamap_table->dm_mapsize, 920 BUS_DMASYNC_PREWRITE); 921 922 /* Maps are ready. Start DMA function */ 923 #ifdef DIAGNOSTIC 924 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 925 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 926 dma_maps->dmamap_table->dm_segs[0].ds_addr); 927 panic("pciide_dma_init: table align"); 928 } 929 #endif 930 931 /* Clear status bits */ 932 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 933 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 934 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 935 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 936 /* Write table addr */ 937 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 938 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 939 dma_maps->dmamap_table->dm_segs[0].ds_addr); 940 /* set read/write */ 941 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 942 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 943 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 944 /* remember flags */ 945 dma_maps->dma_flags = flags; 946 return 0; 947 } 948 949 void 950 pciide_dma_start(v, channel, drive) 951 void *v; 952 int channel, drive; 953 { 954 struct pciide_softc *sc = v; 955 956 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 957 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 958 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 959 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 960 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 961 } 962 963 int 964 pciide_dma_finish(v, channel, drive, force) 965 void *v; 966 int channel, drive; 967 int force; 968 { 969 struct pciide_softc *sc = v; 970 u_int8_t status; 971 int error = 0; 972 struct pciide_dma_maps *dma_maps = 973 &sc->pciide_channels[channel].dma_maps[drive]; 974 975 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 976 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 977 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 978 DEBUG_XFERS); 979 980 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 981 return WDC_DMAST_NOIRQ; 982 983 /* stop DMA channel */ 984 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 985 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 986 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 987 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 988 989 /* Unload the map of the data buffer */ 990 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 991 dma_maps->dmamap_xfer->dm_mapsize, 992 (dma_maps->dma_flags & WDC_DMA_READ) ? 993 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 994 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 995 996 if ((status & IDEDMA_CTL_ERR) != 0) { 997 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 998 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 999 error |= WDC_DMAST_ERR; 1000 } 1001 1002 if ((status & IDEDMA_CTL_INTR) == 0) { 1003 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1004 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1005 drive, status); 1006 error |= WDC_DMAST_NOIRQ; 1007 } 1008 1009 if ((status & IDEDMA_CTL_ACT) != 0) { 1010 /* data underrun, may be a valid condition for ATAPI */ 1011 error |= WDC_DMAST_UNDER; 1012 } 1013 return error; 1014 } 1015 1016 void 1017 pciide_irqack(chp) 1018 struct channel_softc *chp; 1019 { 1020 struct pciide_channel *cp = (struct pciide_channel*)chp; 1021 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1022 1023 /* clear status bits in IDE DMA registers */ 1024 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1025 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1026 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1027 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1028 } 1029 1030 /* some common code used by several chip_map */ 1031 int 1032 pciide_chansetup(sc, channel, interface) 1033 struct pciide_softc *sc; 1034 int channel; 1035 pcireg_t interface; 1036 { 1037 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1038 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1039 cp->name = PCIIDE_CHANNEL_NAME(channel); 1040 cp->wdc_channel.channel = channel; 1041 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1042 cp->wdc_channel.ch_queue = 1043 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1044 if (cp->wdc_channel.ch_queue == NULL) { 1045 printf("%s %s channel: " 1046 "can't allocate memory for command queue", 1047 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1048 return 0; 1049 } 1050 printf("%s: %s channel %s to %s mode\n", 1051 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1052 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1053 "configured" : "wired", 1054 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1055 "native-PCI" : "compatibility"); 1056 return 1; 1057 } 1058 1059 /* some common code used by several chip channel_map */ 1060 void 1061 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1062 struct pci_attach_args *pa; 1063 struct pciide_channel *cp; 1064 pcireg_t interface; 1065 bus_size_t *cmdsizep, *ctlsizep; 1066 int (*pci_intr) __P((void *)); 1067 { 1068 struct channel_softc *wdc_cp = &cp->wdc_channel; 1069 1070 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1071 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1072 pci_intr); 1073 else 1074 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1075 wdc_cp->channel, cmdsizep, ctlsizep); 1076 1077 if (cp->hw_ok == 0) 1078 return; 1079 wdc_cp->data32iot = wdc_cp->cmd_iot; 1080 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1081 wdcattach(wdc_cp); 1082 } 1083 1084 /* 1085 * Generic code to call to know if a channel can be disabled. Return 1 1086 * if channel can be disabled, 0 if not 1087 */ 1088 int 1089 pciide_chan_candisable(cp) 1090 struct pciide_channel *cp; 1091 { 1092 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1093 struct channel_softc *wdc_cp = &cp->wdc_channel; 1094 1095 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1096 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1097 printf("%s: disabling %s channel (no drives)\n", 1098 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1099 cp->hw_ok = 0; 1100 return 1; 1101 } 1102 return 0; 1103 } 1104 1105 /* 1106 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1107 * Set hw_ok=0 on failure 1108 */ 1109 void 1110 pciide_map_compat_intr(pa, cp, compatchan, interface) 1111 struct pci_attach_args *pa; 1112 struct pciide_channel *cp; 1113 int compatchan, interface; 1114 { 1115 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1116 struct channel_softc *wdc_cp = &cp->wdc_channel; 1117 1118 if (cp->hw_ok == 0) 1119 return; 1120 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1121 return; 1122 1123 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1124 pa, compatchan, pciide_compat_intr, cp); 1125 if (cp->ih == NULL) { 1126 printf("%s: no compatibility interrupt for use by %s " 1127 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1128 cp->hw_ok = 0; 1129 } 1130 } 1131 1132 void 1133 pciide_print_modes(cp) 1134 struct pciide_channel *cp; 1135 { 1136 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1137 int drive; 1138 struct channel_softc *chp; 1139 struct ata_drive_datas *drvp; 1140 1141 chp = &cp->wdc_channel; 1142 for (drive = 0; drive < 2; drive++) { 1143 drvp = &chp->ch_drive[drive]; 1144 if ((drvp->drive_flags & DRIVE) == 0) 1145 continue; 1146 printf("%s(%s:%d:%d): using PIO mode %d", 1147 drvp->drv_softc->dv_xname, 1148 sc->sc_wdcdev.sc_dev.dv_xname, 1149 chp->channel, drive, drvp->PIO_mode); 1150 if (drvp->drive_flags & DRIVE_DMA) 1151 printf(", DMA mode %d", drvp->DMA_mode); 1152 if (drvp->drive_flags & DRIVE_UDMA) 1153 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1154 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1155 printf(" (using DMA data transfers)"); 1156 printf("\n"); 1157 } 1158 } 1159 1160 void 1161 default_chip_map(sc, pa) 1162 struct pciide_softc *sc; 1163 struct pci_attach_args *pa; 1164 { 1165 struct pciide_channel *cp; 1166 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1167 pcireg_t csr; 1168 int channel, drive; 1169 struct ata_drive_datas *drvp; 1170 u_int8_t idedma_ctl; 1171 bus_size_t cmdsize, ctlsize; 1172 char *failreason; 1173 1174 if (pciide_chipen(sc, pa) == 0) 1175 return; 1176 1177 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1178 printf("%s: bus-master DMA support present", 1179 sc->sc_wdcdev.sc_dev.dv_xname); 1180 if (sc->sc_pp == &default_product_desc && 1181 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1182 PCIIDE_OPTIONS_DMA) == 0) { 1183 printf(", but unused (no driver support)"); 1184 sc->sc_dma_ok = 0; 1185 } else { 1186 pciide_mapreg_dma(sc, pa); 1187 if (sc->sc_dma_ok != 0) 1188 printf(", used without full driver " 1189 "support"); 1190 } 1191 } else { 1192 printf("%s: hardware does not support DMA", 1193 sc->sc_wdcdev.sc_dev.dv_xname); 1194 sc->sc_dma_ok = 0; 1195 } 1196 printf("\n"); 1197 if (sc->sc_dma_ok) { 1198 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1199 sc->sc_wdcdev.irqack = pciide_irqack; 1200 } 1201 sc->sc_wdcdev.PIO_cap = 0; 1202 sc->sc_wdcdev.DMA_cap = 0; 1203 1204 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1205 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1206 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1207 1208 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1209 cp = &sc->pciide_channels[channel]; 1210 if (pciide_chansetup(sc, channel, interface) == 0) 1211 continue; 1212 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1213 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1214 &ctlsize, pciide_pci_intr); 1215 } else { 1216 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1217 channel, &cmdsize, &ctlsize); 1218 } 1219 if (cp->hw_ok == 0) 1220 continue; 1221 /* 1222 * Check to see if something appears to be there. 1223 */ 1224 failreason = NULL; 1225 if (!wdcprobe(&cp->wdc_channel)) { 1226 failreason = "not responding; disabled or no drives?"; 1227 goto next; 1228 } 1229 /* 1230 * Now, make sure it's actually attributable to this PCI IDE 1231 * channel by trying to access the channel again while the 1232 * PCI IDE controller's I/O space is disabled. (If the 1233 * channel no longer appears to be there, it belongs to 1234 * this controller.) YUCK! 1235 */ 1236 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1237 PCI_COMMAND_STATUS_REG); 1238 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1239 csr & ~PCI_COMMAND_IO_ENABLE); 1240 if (wdcprobe(&cp->wdc_channel)) 1241 failreason = "other hardware responding at addresses"; 1242 pci_conf_write(sc->sc_pc, sc->sc_tag, 1243 PCI_COMMAND_STATUS_REG, csr); 1244 next: 1245 if (failreason) { 1246 printf("%s: %s channel ignored (%s)\n", 1247 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1248 failreason); 1249 cp->hw_ok = 0; 1250 bus_space_unmap(cp->wdc_channel.cmd_iot, 1251 cp->wdc_channel.cmd_ioh, cmdsize); 1252 bus_space_unmap(cp->wdc_channel.ctl_iot, 1253 cp->wdc_channel.ctl_ioh, ctlsize); 1254 } else { 1255 pciide_map_compat_intr(pa, cp, channel, interface); 1256 } 1257 if (cp->hw_ok) { 1258 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1259 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1260 wdcattach(&cp->wdc_channel); 1261 } 1262 } 1263 1264 if (sc->sc_dma_ok == 0) 1265 return; 1266 1267 /* Allocate DMA maps */ 1268 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1269 idedma_ctl = 0; 1270 cp = &sc->pciide_channels[channel]; 1271 for (drive = 0; drive < 2; drive++) { 1272 drvp = &cp->wdc_channel.ch_drive[drive]; 1273 /* If no drive, skip */ 1274 if ((drvp->drive_flags & DRIVE) == 0) 1275 continue; 1276 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1277 continue; 1278 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1279 /* Abort DMA setup */ 1280 printf("%s:%d:%d: can't allocate DMA maps, " 1281 "using PIO transfers\n", 1282 sc->sc_wdcdev.sc_dev.dv_xname, 1283 channel, drive); 1284 drvp->drive_flags &= ~DRIVE_DMA; 1285 } 1286 printf("%s:%d:%d: using DMA data transfers\n", 1287 sc->sc_wdcdev.sc_dev.dv_xname, 1288 channel, drive); 1289 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1290 } 1291 if (idedma_ctl != 0) { 1292 /* Add software bits in status register */ 1293 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1294 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1295 idedma_ctl); 1296 } 1297 } 1298 } 1299 1300 void 1301 piix_chip_map(sc, pa) 1302 struct pciide_softc *sc; 1303 struct pci_attach_args *pa; 1304 { 1305 struct pciide_channel *cp; 1306 int channel; 1307 u_int32_t idetim; 1308 bus_size_t cmdsize, ctlsize; 1309 1310 if (pciide_chipen(sc, pa) == 0) 1311 return; 1312 1313 printf("%s: bus-master DMA support present", 1314 sc->sc_wdcdev.sc_dev.dv_xname); 1315 pciide_mapreg_dma(sc, pa); 1316 printf("\n"); 1317 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1318 WDC_CAPABILITY_MODE; 1319 if (sc->sc_dma_ok) { 1320 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1321 sc->sc_wdcdev.irqack = pciide_irqack; 1322 switch(sc->sc_pp->ide_product) { 1323 case PCI_PRODUCT_INTEL_82371AB_IDE: 1324 case PCI_PRODUCT_INTEL_82801AA_IDE: 1325 case PCI_PRODUCT_INTEL_82801AB_IDE: 1326 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1327 } 1328 } 1329 sc->sc_wdcdev.PIO_cap = 4; 1330 sc->sc_wdcdev.DMA_cap = 2; 1331 sc->sc_wdcdev.UDMA_cap = 1332 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1333 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1334 sc->sc_wdcdev.set_modes = piix_setup_channel; 1335 else 1336 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1337 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1338 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1339 1340 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1341 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1342 DEBUG_PROBE); 1343 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1344 WDCDEBUG_PRINT((", sidetim=0x%x", 1345 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1346 DEBUG_PROBE); 1347 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1348 WDCDEBUG_PRINT((", udamreg 0x%x", 1349 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1350 DEBUG_PROBE); 1351 } 1352 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1353 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1354 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1355 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1356 DEBUG_PROBE); 1357 } 1358 1359 } 1360 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1361 1362 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1363 cp = &sc->pciide_channels[channel]; 1364 /* PIIX is compat-only */ 1365 if (pciide_chansetup(sc, channel, 0) == 0) 1366 continue; 1367 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1368 if ((PIIX_IDETIM_READ(idetim, channel) & 1369 PIIX_IDETIM_IDE) == 0) { 1370 printf("%s: %s channel ignored (disabled)\n", 1371 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1372 continue; 1373 } 1374 /* PIIX are compat-only pciide devices */ 1375 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1376 if (cp->hw_ok == 0) 1377 continue; 1378 if (pciide_chan_candisable(cp)) { 1379 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1380 channel); 1381 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1382 idetim); 1383 } 1384 pciide_map_compat_intr(pa, cp, channel, 0); 1385 if (cp->hw_ok == 0) 1386 continue; 1387 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1388 } 1389 1390 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1391 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1392 DEBUG_PROBE); 1393 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1394 WDCDEBUG_PRINT((", sidetim=0x%x", 1395 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1396 DEBUG_PROBE); 1397 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1398 WDCDEBUG_PRINT((", udamreg 0x%x", 1399 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1400 DEBUG_PROBE); 1401 } 1402 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1403 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1404 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1405 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1406 DEBUG_PROBE); 1407 } 1408 } 1409 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1410 } 1411 1412 void 1413 piix_setup_channel(chp) 1414 struct channel_softc *chp; 1415 { 1416 u_int8_t mode[2], drive; 1417 u_int32_t oidetim, idetim, idedma_ctl; 1418 struct pciide_channel *cp = (struct pciide_channel*)chp; 1419 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1420 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1421 1422 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1423 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1424 idedma_ctl = 0; 1425 1426 /* set up new idetim: Enable IDE registers decode */ 1427 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1428 chp->channel); 1429 1430 /* setup DMA */ 1431 pciide_channel_dma_setup(cp); 1432 1433 /* 1434 * Here we have to mess up with drives mode: PIIX can't have 1435 * different timings for master and slave drives. 1436 * We need to find the best combination. 1437 */ 1438 1439 /* If both drives supports DMA, take the lower mode */ 1440 if ((drvp[0].drive_flags & DRIVE_DMA) && 1441 (drvp[1].drive_flags & DRIVE_DMA)) { 1442 mode[0] = mode[1] = 1443 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1444 drvp[0].DMA_mode = mode[0]; 1445 drvp[1].DMA_mode = mode[1]; 1446 goto ok; 1447 } 1448 /* 1449 * If only one drive supports DMA, use its mode, and 1450 * put the other one in PIO mode 0 if mode not compatible 1451 */ 1452 if (drvp[0].drive_flags & DRIVE_DMA) { 1453 mode[0] = drvp[0].DMA_mode; 1454 mode[1] = drvp[1].PIO_mode; 1455 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1456 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1457 mode[1] = drvp[1].PIO_mode = 0; 1458 goto ok; 1459 } 1460 if (drvp[1].drive_flags & DRIVE_DMA) { 1461 mode[1] = drvp[1].DMA_mode; 1462 mode[0] = drvp[0].PIO_mode; 1463 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1464 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1465 mode[0] = drvp[0].PIO_mode = 0; 1466 goto ok; 1467 } 1468 /* 1469 * If both drives are not DMA, takes the lower mode, unless 1470 * one of them is PIO mode < 2 1471 */ 1472 if (drvp[0].PIO_mode < 2) { 1473 mode[0] = drvp[0].PIO_mode = 0; 1474 mode[1] = drvp[1].PIO_mode; 1475 } else if (drvp[1].PIO_mode < 2) { 1476 mode[1] = drvp[1].PIO_mode = 0; 1477 mode[0] = drvp[0].PIO_mode; 1478 } else { 1479 mode[0] = mode[1] = 1480 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1481 drvp[0].PIO_mode = mode[0]; 1482 drvp[1].PIO_mode = mode[1]; 1483 } 1484 ok: /* The modes are setup */ 1485 for (drive = 0; drive < 2; drive++) { 1486 if (drvp[drive].drive_flags & DRIVE_DMA) { 1487 idetim |= piix_setup_idetim_timings( 1488 mode[drive], 1, chp->channel); 1489 goto end; 1490 } 1491 } 1492 /* If we are there, none of the drives are DMA */ 1493 if (mode[0] >= 2) 1494 idetim |= piix_setup_idetim_timings( 1495 mode[0], 0, chp->channel); 1496 else 1497 idetim |= piix_setup_idetim_timings( 1498 mode[1], 0, chp->channel); 1499 end: /* 1500 * timing mode is now set up in the controller. Enable 1501 * it per-drive 1502 */ 1503 for (drive = 0; drive < 2; drive++) { 1504 /* If no drive, skip */ 1505 if ((drvp[drive].drive_flags & DRIVE) == 0) 1506 continue; 1507 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1508 if (drvp[drive].drive_flags & DRIVE_DMA) 1509 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1510 } 1511 if (idedma_ctl != 0) { 1512 /* Add software bits in status register */ 1513 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1514 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1515 idedma_ctl); 1516 } 1517 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1518 pciide_print_modes(cp); 1519 } 1520 1521 void 1522 piix3_4_setup_channel(chp) 1523 struct channel_softc *chp; 1524 { 1525 struct ata_drive_datas *drvp; 1526 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1527 struct pciide_channel *cp = (struct pciide_channel*)chp; 1528 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1529 int drive; 1530 int channel = chp->channel; 1531 1532 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1533 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1534 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1535 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1536 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1537 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1538 PIIX_SIDETIM_RTC_MASK(channel)); 1539 1540 idedma_ctl = 0; 1541 /* If channel disabled, no need to go further */ 1542 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1543 return; 1544 /* set up new idetim: Enable IDE registers decode */ 1545 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1546 1547 /* setup DMA if needed */ 1548 pciide_channel_dma_setup(cp); 1549 1550 for (drive = 0; drive < 2; drive++) { 1551 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1552 PIIX_UDMATIM_SET(0x3, channel, drive)); 1553 drvp = &chp->ch_drive[drive]; 1554 /* If no drive, skip */ 1555 if ((drvp->drive_flags & DRIVE) == 0) 1556 continue; 1557 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1558 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1559 goto pio; 1560 1561 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1562 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1563 ideconf |= PIIX_CONFIG_PINGPONG; 1564 } 1565 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1566 /* setup Ultra/66 */ 1567 if (drvp->UDMA_mode > 2 && 1568 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1569 drvp->UDMA_mode = 2; 1570 if (drvp->UDMA_mode > 2) 1571 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1572 else 1573 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1574 } 1575 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1576 (drvp->drive_flags & DRIVE_UDMA)) { 1577 /* use Ultra/DMA */ 1578 drvp->drive_flags &= ~DRIVE_DMA; 1579 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1580 udmareg |= PIIX_UDMATIM_SET( 1581 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1582 } else { 1583 /* use Multiword DMA */ 1584 drvp->drive_flags &= ~DRIVE_UDMA; 1585 if (drive == 0) { 1586 idetim |= piix_setup_idetim_timings( 1587 drvp->DMA_mode, 1, channel); 1588 } else { 1589 sidetim |= piix_setup_sidetim_timings( 1590 drvp->DMA_mode, 1, channel); 1591 idetim =PIIX_IDETIM_SET(idetim, 1592 PIIX_IDETIM_SITRE, channel); 1593 } 1594 } 1595 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1596 1597 pio: /* use PIO mode */ 1598 idetim |= piix_setup_idetim_drvs(drvp); 1599 if (drive == 0) { 1600 idetim |= piix_setup_idetim_timings( 1601 drvp->PIO_mode, 0, channel); 1602 } else { 1603 sidetim |= piix_setup_sidetim_timings( 1604 drvp->PIO_mode, 0, channel); 1605 idetim =PIIX_IDETIM_SET(idetim, 1606 PIIX_IDETIM_SITRE, channel); 1607 } 1608 } 1609 if (idedma_ctl != 0) { 1610 /* Add software bits in status register */ 1611 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1612 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1613 idedma_ctl); 1614 } 1615 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1616 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1617 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1618 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1619 pciide_print_modes(cp); 1620 } 1621 1622 1623 /* setup ISP and RTC fields, based on mode */ 1624 static u_int32_t 1625 piix_setup_idetim_timings(mode, dma, channel) 1626 u_int8_t mode; 1627 u_int8_t dma; 1628 u_int8_t channel; 1629 { 1630 1631 if (dma) 1632 return PIIX_IDETIM_SET(0, 1633 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1634 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1635 channel); 1636 else 1637 return PIIX_IDETIM_SET(0, 1638 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1639 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1640 channel); 1641 } 1642 1643 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1644 static u_int32_t 1645 piix_setup_idetim_drvs(drvp) 1646 struct ata_drive_datas *drvp; 1647 { 1648 u_int32_t ret = 0; 1649 struct channel_softc *chp = drvp->chnl_softc; 1650 u_int8_t channel = chp->channel; 1651 u_int8_t drive = drvp->drive; 1652 1653 /* 1654 * If drive is using UDMA, timings setups are independant 1655 * So just check DMA and PIO here. 1656 */ 1657 if (drvp->drive_flags & DRIVE_DMA) { 1658 /* if mode = DMA mode 0, use compatible timings */ 1659 if ((drvp->drive_flags & DRIVE_DMA) && 1660 drvp->DMA_mode == 0) { 1661 drvp->PIO_mode = 0; 1662 return ret; 1663 } 1664 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1665 /* 1666 * PIO and DMA timings are the same, use fast timings for PIO 1667 * too, else use compat timings. 1668 */ 1669 if ((piix_isp_pio[drvp->PIO_mode] != 1670 piix_isp_dma[drvp->DMA_mode]) || 1671 (piix_rtc_pio[drvp->PIO_mode] != 1672 piix_rtc_dma[drvp->DMA_mode])) 1673 drvp->PIO_mode = 0; 1674 /* if PIO mode <= 2, use compat timings for PIO */ 1675 if (drvp->PIO_mode <= 2) { 1676 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1677 channel); 1678 return ret; 1679 } 1680 } 1681 1682 /* 1683 * Now setup PIO modes. If mode < 2, use compat timings. 1684 * Else enable fast timings. Enable IORDY and prefetch/post 1685 * if PIO mode >= 3. 1686 */ 1687 1688 if (drvp->PIO_mode < 2) 1689 return ret; 1690 1691 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1692 if (drvp->PIO_mode >= 3) { 1693 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1694 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1695 } 1696 return ret; 1697 } 1698 1699 /* setup values in SIDETIM registers, based on mode */ 1700 static u_int32_t 1701 piix_setup_sidetim_timings(mode, dma, channel) 1702 u_int8_t mode; 1703 u_int8_t dma; 1704 u_int8_t channel; 1705 { 1706 if (dma) 1707 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1708 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1709 else 1710 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1711 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1712 } 1713 1714 void 1715 amd756_chip_map(sc, pa) 1716 struct pciide_softc *sc; 1717 struct pci_attach_args *pa; 1718 { 1719 struct pciide_channel *cp; 1720 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1721 int channel; 1722 pcireg_t chanenable; 1723 bus_size_t cmdsize, ctlsize; 1724 1725 if (pciide_chipen(sc, pa) == 0) 1726 return; 1727 printf("%s: bus-master DMA support present", 1728 sc->sc_wdcdev.sc_dev.dv_xname); 1729 pciide_mapreg_dma(sc, pa); 1730 printf("\n"); 1731 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1732 WDC_CAPABILITY_MODE; 1733 if (sc->sc_dma_ok) { 1734 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1735 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1736 sc->sc_wdcdev.irqack = pciide_irqack; 1737 } 1738 sc->sc_wdcdev.PIO_cap = 4; 1739 sc->sc_wdcdev.DMA_cap = 2; 1740 sc->sc_wdcdev.UDMA_cap = 4; 1741 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1742 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1743 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1744 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1745 1746 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1747 DEBUG_PROBE); 1748 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1749 cp = &sc->pciide_channels[channel]; 1750 if (pciide_chansetup(sc, channel, interface) == 0) 1751 continue; 1752 1753 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1754 printf("%s: %s channel ignored (disabled)\n", 1755 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1756 continue; 1757 } 1758 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1759 pciide_pci_intr); 1760 1761 if (pciide_chan_candisable(cp)) 1762 chanenable &= ~AMD756_CHAN_EN(channel); 1763 pciide_map_compat_intr(pa, cp, channel, interface); 1764 if (cp->hw_ok == 0) 1765 continue; 1766 1767 amd756_setup_channel(&cp->wdc_channel); 1768 } 1769 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1770 chanenable); 1771 return; 1772 } 1773 1774 void 1775 amd756_setup_channel(chp) 1776 struct channel_softc *chp; 1777 { 1778 u_int32_t udmatim_reg, datatim_reg; 1779 u_int8_t idedma_ctl; 1780 int mode, drive; 1781 struct ata_drive_datas *drvp; 1782 struct pciide_channel *cp = (struct pciide_channel*)chp; 1783 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1784 int rev = PCI_REVISION( 1785 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1786 1787 idedma_ctl = 0; 1788 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1789 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1790 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1791 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1792 1793 /* setup DMA if needed */ 1794 pciide_channel_dma_setup(cp); 1795 1796 for (drive = 0; drive < 2; drive++) { 1797 drvp = &chp->ch_drive[drive]; 1798 /* If no drive, skip */ 1799 if ((drvp->drive_flags & DRIVE) == 0) 1800 continue; 1801 /* add timing values, setup DMA if needed */ 1802 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1803 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1804 mode = drvp->PIO_mode; 1805 goto pio; 1806 } 1807 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1808 (drvp->drive_flags & DRIVE_UDMA)) { 1809 /* use Ultra/DMA */ 1810 drvp->drive_flags &= ~DRIVE_DMA; 1811 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1812 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1813 AMD756_UDMA_TIME(chp->channel, drive, 1814 amd756_udma_tim[drvp->UDMA_mode]); 1815 /* can use PIO timings, MW DMA unused */ 1816 mode = drvp->PIO_mode; 1817 } else { 1818 /* use Multiword DMA, but only if revision is OK */ 1819 drvp->drive_flags &= ~DRIVE_UDMA; 1820 #ifndef PCIIDE_AMD756_ENABLEDMA 1821 /* 1822 * The workaround doesn't seem to be necessary 1823 * with all drives, so it can be disabled by 1824 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1825 * triggered. 1826 */ 1827 if (AMD756_CHIPREV_DISABLEDMA(rev)) { 1828 printf("%s:%d:%d: multi-word DMA disabled due " 1829 "to chip revision\n", 1830 sc->sc_wdcdev.sc_dev.dv_xname, 1831 chp->channel, drive); 1832 mode = drvp->PIO_mode; 1833 drvp->drive_flags &= ~DRIVE_DMA; 1834 goto pio; 1835 } 1836 #endif 1837 /* mode = min(pio, dma+2) */ 1838 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1839 mode = drvp->PIO_mode; 1840 else 1841 mode = drvp->DMA_mode + 2; 1842 } 1843 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1844 1845 pio: /* setup PIO mode */ 1846 if (mode <= 2) { 1847 drvp->DMA_mode = 0; 1848 drvp->PIO_mode = 0; 1849 mode = 0; 1850 } else { 1851 drvp->PIO_mode = mode; 1852 drvp->DMA_mode = mode - 2; 1853 } 1854 datatim_reg |= 1855 AMD756_DATATIM_PULSE(chp->channel, drive, 1856 amd756_pio_set[mode]) | 1857 AMD756_DATATIM_RECOV(chp->channel, drive, 1858 amd756_pio_rec[mode]); 1859 } 1860 if (idedma_ctl != 0) { 1861 /* Add software bits in status register */ 1862 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1863 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1864 idedma_ctl); 1865 } 1866 pciide_print_modes(cp); 1867 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1868 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1869 } 1870 1871 void 1872 apollo_chip_map(sc, pa) 1873 struct pciide_softc *sc; 1874 struct pci_attach_args *pa; 1875 { 1876 struct pciide_channel *cp; 1877 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1878 int channel; 1879 u_int32_t ideconf; 1880 bus_size_t cmdsize, ctlsize; 1881 1882 if (pciide_chipen(sc, pa) == 0) 1883 return; 1884 printf("%s: bus-master DMA support present", 1885 sc->sc_wdcdev.sc_dev.dv_xname); 1886 pciide_mapreg_dma(sc, pa); 1887 printf("\n"); 1888 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1889 WDC_CAPABILITY_MODE; 1890 if (sc->sc_dma_ok) { 1891 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1892 sc->sc_wdcdev.irqack = pciide_irqack; 1893 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1894 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1895 } 1896 sc->sc_wdcdev.PIO_cap = 4; 1897 sc->sc_wdcdev.DMA_cap = 2; 1898 sc->sc_wdcdev.UDMA_cap = 2; 1899 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1900 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1901 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1902 1903 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1904 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1905 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1906 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1907 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1908 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1909 DEBUG_PROBE); 1910 1911 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1912 cp = &sc->pciide_channels[channel]; 1913 if (pciide_chansetup(sc, channel, interface) == 0) 1914 continue; 1915 1916 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1917 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1918 printf("%s: %s channel ignored (disabled)\n", 1919 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1920 continue; 1921 } 1922 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1923 pciide_pci_intr); 1924 if (cp->hw_ok == 0) 1925 continue; 1926 if (pciide_chan_candisable(cp)) { 1927 ideconf &= ~APO_IDECONF_EN(channel); 1928 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1929 ideconf); 1930 } 1931 pciide_map_compat_intr(pa, cp, channel, interface); 1932 1933 if (cp->hw_ok == 0) 1934 continue; 1935 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1936 } 1937 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1938 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1939 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1940 } 1941 1942 void 1943 apollo_setup_channel(chp) 1944 struct channel_softc *chp; 1945 { 1946 u_int32_t udmatim_reg, datatim_reg; 1947 u_int8_t idedma_ctl; 1948 int mode, drive; 1949 struct ata_drive_datas *drvp; 1950 struct pciide_channel *cp = (struct pciide_channel*)chp; 1951 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1952 1953 idedma_ctl = 0; 1954 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1955 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1956 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1957 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1958 1959 /* setup DMA if needed */ 1960 pciide_channel_dma_setup(cp); 1961 1962 for (drive = 0; drive < 2; drive++) { 1963 drvp = &chp->ch_drive[drive]; 1964 /* If no drive, skip */ 1965 if ((drvp->drive_flags & DRIVE) == 0) 1966 continue; 1967 /* add timing values, setup DMA if needed */ 1968 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1969 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1970 mode = drvp->PIO_mode; 1971 goto pio; 1972 } 1973 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1974 (drvp->drive_flags & DRIVE_UDMA)) { 1975 /* use Ultra/DMA */ 1976 drvp->drive_flags &= ~DRIVE_DMA; 1977 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1978 APO_UDMA_EN_MTH(chp->channel, drive) | 1979 APO_UDMA_TIME(chp->channel, drive, 1980 apollo_udma_tim[drvp->UDMA_mode]); 1981 /* can use PIO timings, MW DMA unused */ 1982 mode = drvp->PIO_mode; 1983 } else { 1984 /* use Multiword DMA */ 1985 drvp->drive_flags &= ~DRIVE_UDMA; 1986 /* mode = min(pio, dma+2) */ 1987 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1988 mode = drvp->PIO_mode; 1989 else 1990 mode = drvp->DMA_mode + 2; 1991 } 1992 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1993 1994 pio: /* setup PIO mode */ 1995 if (mode <= 2) { 1996 drvp->DMA_mode = 0; 1997 drvp->PIO_mode = 0; 1998 mode = 0; 1999 } else { 2000 drvp->PIO_mode = mode; 2001 drvp->DMA_mode = mode - 2; 2002 } 2003 datatim_reg |= 2004 APO_DATATIM_PULSE(chp->channel, drive, 2005 apollo_pio_set[mode]) | 2006 APO_DATATIM_RECOV(chp->channel, drive, 2007 apollo_pio_rec[mode]); 2008 } 2009 if (idedma_ctl != 0) { 2010 /* Add software bits in status register */ 2011 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2012 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2013 idedma_ctl); 2014 } 2015 pciide_print_modes(cp); 2016 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2017 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2018 } 2019 2020 void 2021 cmd_channel_map(pa, sc, channel) 2022 struct pci_attach_args *pa; 2023 struct pciide_softc *sc; 2024 int channel; 2025 { 2026 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2027 bus_size_t cmdsize, ctlsize; 2028 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2029 int interface; 2030 2031 /* 2032 * The 0648/0649 can be told to identify as a RAID controller. 2033 * In this case, we have to fake interface 2034 */ 2035 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2036 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2037 PCIIDE_INTERFACE_SETTABLE(1); 2038 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2039 CMD_CONF_DSA1) 2040 interface |= PCIIDE_INTERFACE_PCI(0) | 2041 PCIIDE_INTERFACE_PCI(1); 2042 } else { 2043 interface = PCI_INTERFACE(pa->pa_class); 2044 } 2045 2046 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2047 cp->name = PCIIDE_CHANNEL_NAME(channel); 2048 cp->wdc_channel.channel = channel; 2049 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2050 2051 if (channel > 0) { 2052 cp->wdc_channel.ch_queue = 2053 sc->pciide_channels[0].wdc_channel.ch_queue; 2054 } else { 2055 cp->wdc_channel.ch_queue = 2056 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2057 } 2058 if (cp->wdc_channel.ch_queue == NULL) { 2059 printf("%s %s channel: " 2060 "can't allocate memory for command queue", 2061 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2062 return; 2063 } 2064 2065 printf("%s: %s channel %s to %s mode\n", 2066 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2067 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2068 "configured" : "wired", 2069 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2070 "native-PCI" : "compatibility"); 2071 2072 /* 2073 * with a CMD PCI64x, if we get here, the first channel is enabled: 2074 * there's no way to disable the first channel without disabling 2075 * the whole device 2076 */ 2077 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2078 printf("%s: %s channel ignored (disabled)\n", 2079 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2080 return; 2081 } 2082 2083 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2084 if (cp->hw_ok == 0) 2085 return; 2086 if (channel == 1) { 2087 if (pciide_chan_candisable(cp)) { 2088 ctrl &= ~CMD_CTRL_2PORT; 2089 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2090 CMD_CTRL, ctrl); 2091 } 2092 } 2093 pciide_map_compat_intr(pa, cp, channel, interface); 2094 } 2095 2096 int 2097 cmd_pci_intr(arg) 2098 void *arg; 2099 { 2100 struct pciide_softc *sc = arg; 2101 struct pciide_channel *cp; 2102 struct channel_softc *wdc_cp; 2103 int i, rv, crv; 2104 u_int32_t priirq, secirq; 2105 2106 rv = 0; 2107 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2108 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2109 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2110 cp = &sc->pciide_channels[i]; 2111 wdc_cp = &cp->wdc_channel; 2112 /* If a compat channel skip. */ 2113 if (cp->compat) 2114 continue; 2115 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2116 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2117 crv = wdcintr(wdc_cp); 2118 if (crv == 0) 2119 printf("%s:%d: bogus intr\n", 2120 sc->sc_wdcdev.sc_dev.dv_xname, i); 2121 else 2122 rv = 1; 2123 } 2124 } 2125 return rv; 2126 } 2127 2128 void 2129 cmd_chip_map(sc, pa) 2130 struct pciide_softc *sc; 2131 struct pci_attach_args *pa; 2132 { 2133 int channel; 2134 2135 /* 2136 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2137 * and base adresses registers can be disabled at 2138 * hardware level. In this case, the device is wired 2139 * in compat mode and its first channel is always enabled, 2140 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2141 * In fact, it seems that the first channel of the CMD PCI0640 2142 * can't be disabled. 2143 */ 2144 2145 #ifdef PCIIDE_CMD064x_DISABLE 2146 if (pciide_chipen(sc, pa) == 0) 2147 return; 2148 #endif 2149 2150 printf("%s: hardware does not support DMA\n", 2151 sc->sc_wdcdev.sc_dev.dv_xname); 2152 sc->sc_dma_ok = 0; 2153 2154 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2155 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2156 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2157 2158 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2159 cmd_channel_map(pa, sc, channel); 2160 } 2161 } 2162 2163 void 2164 cmd0643_9_chip_map(sc, pa) 2165 struct pciide_softc *sc; 2166 struct pci_attach_args *pa; 2167 { 2168 struct pciide_channel *cp; 2169 int channel; 2170 2171 /* 2172 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2173 * and base adresses registers can be disabled at 2174 * hardware level. In this case, the device is wired 2175 * in compat mode and its first channel is always enabled, 2176 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2177 * In fact, it seems that the first channel of the CMD PCI0640 2178 * can't be disabled. 2179 */ 2180 2181 #ifdef PCIIDE_CMD064x_DISABLE 2182 if (pciide_chipen(sc, pa) == 0) 2183 return; 2184 #endif 2185 printf("%s: bus-master DMA support present", 2186 sc->sc_wdcdev.sc_dev.dv_xname); 2187 pciide_mapreg_dma(sc, pa); 2188 printf("\n"); 2189 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2190 WDC_CAPABILITY_MODE; 2191 if (sc->sc_dma_ok) { 2192 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2193 switch (sc->sc_pp->ide_product) { 2194 case PCI_PRODUCT_CMDTECH_649: 2195 case PCI_PRODUCT_CMDTECH_648: 2196 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2197 sc->sc_wdcdev.UDMA_cap = 4; 2198 sc->sc_wdcdev.irqack = cmd648_9_irqack; 2199 break; 2200 default: 2201 sc->sc_wdcdev.irqack = pciide_irqack; 2202 } 2203 } 2204 2205 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2206 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2207 sc->sc_wdcdev.PIO_cap = 4; 2208 sc->sc_wdcdev.DMA_cap = 2; 2209 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2210 2211 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2212 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2213 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2214 DEBUG_PROBE); 2215 2216 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2217 cp = &sc->pciide_channels[channel]; 2218 cmd_channel_map(pa, sc, channel); 2219 if (cp->hw_ok == 0) 2220 continue; 2221 cmd0643_9_setup_channel(&cp->wdc_channel); 2222 } 2223 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2224 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2225 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2226 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2227 DEBUG_PROBE); 2228 } 2229 2230 void 2231 cmd0643_9_setup_channel(chp) 2232 struct channel_softc *chp; 2233 { 2234 struct ata_drive_datas *drvp; 2235 u_int8_t tim; 2236 u_int32_t idedma_ctl, udma_reg; 2237 int drive; 2238 struct pciide_channel *cp = (struct pciide_channel*)chp; 2239 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2240 2241 idedma_ctl = 0; 2242 /* setup DMA if needed */ 2243 pciide_channel_dma_setup(cp); 2244 2245 for (drive = 0; drive < 2; drive++) { 2246 drvp = &chp->ch_drive[drive]; 2247 /* If no drive, skip */ 2248 if ((drvp->drive_flags & DRIVE) == 0) 2249 continue; 2250 /* add timing values, setup DMA if needed */ 2251 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2252 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2253 if (drvp->drive_flags & DRIVE_UDMA) { 2254 /* UltraDMA on a 0648 or 0649 */ 2255 udma_reg = pciide_pci_read(sc->sc_pc, 2256 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2257 if (drvp->UDMA_mode > 2 && 2258 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2259 CMD_BICSR) & 2260 CMD_BICSR_80(chp->channel)) == 0) 2261 drvp->UDMA_mode = 2; 2262 if (drvp->UDMA_mode > 2) 2263 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2264 else 2265 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2266 udma_reg |= CMD_UDMATIM_UDMA(drive); 2267 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2268 CMD_UDMATIM_TIM_OFF(drive)); 2269 udma_reg |= 2270 (cmd0648_9_tim_udma[drvp->UDMA_mode] << 2271 CMD_UDMATIM_TIM_OFF(drive)); 2272 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2273 CMD_UDMATIM(chp->channel), udma_reg); 2274 } else { 2275 /* 2276 * use Multiword DMA. 2277 * Timings will be used for both PIO and DMA, 2278 * so adjust DMA mode if needed 2279 * if we have a 0648/9, turn off UDMA 2280 */ 2281 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2282 udma_reg = pciide_pci_read(sc->sc_pc, 2283 sc->sc_tag, 2284 CMD_UDMATIM(chp->channel)); 2285 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2286 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2287 CMD_UDMATIM(chp->channel), 2288 udma_reg); 2289 } 2290 if (drvp->PIO_mode >= 3 && 2291 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2292 drvp->DMA_mode = drvp->PIO_mode - 2; 2293 } 2294 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2295 } 2296 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2297 } 2298 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2299 CMD_DATA_TIM(chp->channel, drive), tim); 2300 } 2301 if (idedma_ctl != 0) { 2302 /* Add software bits in status register */ 2303 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2304 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2305 idedma_ctl); 2306 } 2307 pciide_print_modes(cp); 2308 } 2309 2310 void 2311 cmd648_9_irqack(chp) 2312 struct channel_softc *chp; 2313 { 2314 u_int32_t priirq, secirq; 2315 struct pciide_channel *cp = (struct pciide_channel*)chp; 2316 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2317 2318 if (chp->channel == 0) { 2319 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2320 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2321 } else { 2322 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2323 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2324 } 2325 pciide_irqack(chp); 2326 } 2327 2328 void 2329 cy693_chip_map(sc, pa) 2330 struct pciide_softc *sc; 2331 struct pci_attach_args *pa; 2332 { 2333 struct pciide_channel *cp; 2334 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2335 bus_size_t cmdsize, ctlsize; 2336 2337 if (pciide_chipen(sc, pa) == 0) 2338 return; 2339 /* 2340 * this chip has 2 PCI IDE functions, one for primary and one for 2341 * secondary. So we need to call pciide_mapregs_compat() with 2342 * the real channel 2343 */ 2344 if (pa->pa_function == 1) { 2345 sc->sc_cy_compatchan = 0; 2346 } else if (pa->pa_function == 2) { 2347 sc->sc_cy_compatchan = 1; 2348 } else { 2349 printf("%s: unexpected PCI function %d\n", 2350 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2351 return; 2352 } 2353 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2354 printf("%s: bus-master DMA support present", 2355 sc->sc_wdcdev.sc_dev.dv_xname); 2356 pciide_mapreg_dma(sc, pa); 2357 } else { 2358 printf("%s: hardware does not support DMA", 2359 sc->sc_wdcdev.sc_dev.dv_xname); 2360 sc->sc_dma_ok = 0; 2361 } 2362 printf("\n"); 2363 2364 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2365 if (sc->sc_cy_handle == NULL) { 2366 printf("%s: unable to map hyperCache control registers\n", 2367 sc->sc_wdcdev.sc_dev.dv_xname); 2368 sc->sc_dma_ok = 0; 2369 } 2370 2371 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2372 WDC_CAPABILITY_MODE; 2373 if (sc->sc_dma_ok) { 2374 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2375 sc->sc_wdcdev.irqack = pciide_irqack; 2376 } 2377 sc->sc_wdcdev.PIO_cap = 4; 2378 sc->sc_wdcdev.DMA_cap = 2; 2379 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2380 2381 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2382 sc->sc_wdcdev.nchannels = 1; 2383 2384 /* Only one channel for this chip; if we are here it's enabled */ 2385 cp = &sc->pciide_channels[0]; 2386 sc->wdc_chanarray[0] = &cp->wdc_channel; 2387 cp->name = PCIIDE_CHANNEL_NAME(0); 2388 cp->wdc_channel.channel = 0; 2389 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2390 cp->wdc_channel.ch_queue = 2391 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2392 if (cp->wdc_channel.ch_queue == NULL) { 2393 printf("%s primary channel: " 2394 "can't allocate memory for command queue", 2395 sc->sc_wdcdev.sc_dev.dv_xname); 2396 return; 2397 } 2398 printf("%s: primary channel %s to ", 2399 sc->sc_wdcdev.sc_dev.dv_xname, 2400 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2401 "configured" : "wired"); 2402 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2403 printf("native-PCI"); 2404 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2405 pciide_pci_intr); 2406 } else { 2407 printf("compatibility"); 2408 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2409 &cmdsize, &ctlsize); 2410 } 2411 printf(" mode\n"); 2412 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2413 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2414 wdcattach(&cp->wdc_channel); 2415 if (pciide_chan_candisable(cp)) { 2416 pci_conf_write(sc->sc_pc, sc->sc_tag, 2417 PCI_COMMAND_STATUS_REG, 0); 2418 } 2419 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2420 if (cp->hw_ok == 0) 2421 return; 2422 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2423 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2424 cy693_setup_channel(&cp->wdc_channel); 2425 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2426 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2427 } 2428 2429 void 2430 cy693_setup_channel(chp) 2431 struct channel_softc *chp; 2432 { 2433 struct ata_drive_datas *drvp; 2434 int drive; 2435 u_int32_t cy_cmd_ctrl; 2436 u_int32_t idedma_ctl; 2437 struct pciide_channel *cp = (struct pciide_channel*)chp; 2438 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2439 int dma_mode = -1; 2440 2441 cy_cmd_ctrl = idedma_ctl = 0; 2442 2443 /* setup DMA if needed */ 2444 pciide_channel_dma_setup(cp); 2445 2446 for (drive = 0; drive < 2; drive++) { 2447 drvp = &chp->ch_drive[drive]; 2448 /* If no drive, skip */ 2449 if ((drvp->drive_flags & DRIVE) == 0) 2450 continue; 2451 /* add timing values, setup DMA if needed */ 2452 if (drvp->drive_flags & DRIVE_DMA) { 2453 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2454 /* use Multiword DMA */ 2455 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2456 dma_mode = drvp->DMA_mode; 2457 } 2458 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2459 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2460 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2461 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2462 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2463 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2464 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2465 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2466 } 2467 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2468 chp->ch_drive[0].DMA_mode = dma_mode; 2469 chp->ch_drive[1].DMA_mode = dma_mode; 2470 2471 if (dma_mode == -1) 2472 dma_mode = 0; 2473 2474 if (sc->sc_cy_handle != NULL) { 2475 /* Note: `multiple' is implied. */ 2476 cy82c693_write(sc->sc_cy_handle, 2477 (sc->sc_cy_compatchan == 0) ? 2478 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2479 } 2480 2481 pciide_print_modes(cp); 2482 2483 if (idedma_ctl != 0) { 2484 /* Add software bits in status register */ 2485 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2486 IDEDMA_CTL, idedma_ctl); 2487 } 2488 } 2489 2490 void 2491 sis_chip_map(sc, pa) 2492 struct pciide_softc *sc; 2493 struct pci_attach_args *pa; 2494 { 2495 struct pciide_channel *cp; 2496 int channel; 2497 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2498 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2499 pcireg_t rev = PCI_REVISION(pa->pa_class); 2500 bus_size_t cmdsize, ctlsize; 2501 2502 if (pciide_chipen(sc, pa) == 0) 2503 return; 2504 printf("%s: bus-master DMA support present", 2505 sc->sc_wdcdev.sc_dev.dv_xname); 2506 pciide_mapreg_dma(sc, pa); 2507 printf("\n"); 2508 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2509 WDC_CAPABILITY_MODE; 2510 if (sc->sc_dma_ok) { 2511 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2512 sc->sc_wdcdev.irqack = pciide_irqack; 2513 if (rev >= 0xd0) 2514 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2515 } 2516 2517 sc->sc_wdcdev.PIO_cap = 4; 2518 sc->sc_wdcdev.DMA_cap = 2; 2519 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2520 sc->sc_wdcdev.UDMA_cap = 2; 2521 sc->sc_wdcdev.set_modes = sis_setup_channel; 2522 2523 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2524 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2525 2526 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2527 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2528 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2529 2530 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2531 cp = &sc->pciide_channels[channel]; 2532 if (pciide_chansetup(sc, channel, interface) == 0) 2533 continue; 2534 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2535 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2536 printf("%s: %s channel ignored (disabled)\n", 2537 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2538 continue; 2539 } 2540 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2541 pciide_pci_intr); 2542 if (cp->hw_ok == 0) 2543 continue; 2544 if (pciide_chan_candisable(cp)) { 2545 if (channel == 0) 2546 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2547 else 2548 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2549 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2550 sis_ctr0); 2551 } 2552 pciide_map_compat_intr(pa, cp, channel, interface); 2553 if (cp->hw_ok == 0) 2554 continue; 2555 sis_setup_channel(&cp->wdc_channel); 2556 } 2557 } 2558 2559 void 2560 sis_setup_channel(chp) 2561 struct channel_softc *chp; 2562 { 2563 struct ata_drive_datas *drvp; 2564 int drive; 2565 u_int32_t sis_tim; 2566 u_int32_t idedma_ctl; 2567 struct pciide_channel *cp = (struct pciide_channel*)chp; 2568 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2569 2570 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2571 "channel %d 0x%x\n", chp->channel, 2572 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2573 DEBUG_PROBE); 2574 sis_tim = 0; 2575 idedma_ctl = 0; 2576 /* setup DMA if needed */ 2577 pciide_channel_dma_setup(cp); 2578 2579 for (drive = 0; drive < 2; drive++) { 2580 drvp = &chp->ch_drive[drive]; 2581 /* If no drive, skip */ 2582 if ((drvp->drive_flags & DRIVE) == 0) 2583 continue; 2584 /* add timing values, setup DMA if needed */ 2585 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2586 (drvp->drive_flags & DRIVE_UDMA) == 0) 2587 goto pio; 2588 2589 if (drvp->drive_flags & DRIVE_UDMA) { 2590 /* use Ultra/DMA */ 2591 drvp->drive_flags &= ~DRIVE_DMA; 2592 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2593 SIS_TIM_UDMA_TIME_OFF(drive); 2594 sis_tim |= SIS_TIM_UDMA_EN(drive); 2595 } else { 2596 /* 2597 * use Multiword DMA 2598 * Timings will be used for both PIO and DMA, 2599 * so adjust DMA mode if needed 2600 */ 2601 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2602 drvp->PIO_mode = drvp->DMA_mode + 2; 2603 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2604 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2605 drvp->PIO_mode - 2 : 0; 2606 if (drvp->DMA_mode == 0) 2607 drvp->PIO_mode = 0; 2608 } 2609 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2610 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2611 SIS_TIM_ACT_OFF(drive); 2612 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2613 SIS_TIM_REC_OFF(drive); 2614 } 2615 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2616 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2617 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2618 if (idedma_ctl != 0) { 2619 /* Add software bits in status register */ 2620 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2621 IDEDMA_CTL, idedma_ctl); 2622 } 2623 pciide_print_modes(cp); 2624 } 2625 2626 void 2627 acer_chip_map(sc, pa) 2628 struct pciide_softc *sc; 2629 struct pci_attach_args *pa; 2630 { 2631 struct pciide_channel *cp; 2632 int channel; 2633 pcireg_t cr, interface; 2634 bus_size_t cmdsize, ctlsize; 2635 2636 if (pciide_chipen(sc, pa) == 0) 2637 return; 2638 printf("%s: bus-master DMA support present", 2639 sc->sc_wdcdev.sc_dev.dv_xname); 2640 pciide_mapreg_dma(sc, pa); 2641 printf("\n"); 2642 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2643 WDC_CAPABILITY_MODE; 2644 if (sc->sc_dma_ok) { 2645 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2646 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2647 sc->sc_wdcdev.irqack = pciide_irqack; 2648 } 2649 2650 sc->sc_wdcdev.PIO_cap = 4; 2651 sc->sc_wdcdev.DMA_cap = 2; 2652 sc->sc_wdcdev.UDMA_cap = 2; 2653 sc->sc_wdcdev.set_modes = acer_setup_channel; 2654 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2655 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2656 2657 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2658 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2659 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2660 2661 /* Enable "microsoft register bits" R/W. */ 2662 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2663 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2664 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2665 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2666 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2667 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2668 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2669 ~ACER_CHANSTATUSREGS_RO); 2670 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2671 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2672 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2673 /* Don't use cr, re-read the real register content instead */ 2674 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2675 PCI_CLASS_REG)); 2676 2677 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2678 cp = &sc->pciide_channels[channel]; 2679 if (pciide_chansetup(sc, channel, interface) == 0) 2680 continue; 2681 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2682 printf("%s: %s channel ignored (disabled)\n", 2683 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2684 continue; 2685 } 2686 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2687 acer_pci_intr); 2688 if (cp->hw_ok == 0) 2689 continue; 2690 if (pciide_chan_candisable(cp)) { 2691 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2692 pci_conf_write(sc->sc_pc, sc->sc_tag, 2693 PCI_CLASS_REG, cr); 2694 } 2695 pciide_map_compat_intr(pa, cp, channel, interface); 2696 acer_setup_channel(&cp->wdc_channel); 2697 } 2698 } 2699 2700 void 2701 acer_setup_channel(chp) 2702 struct channel_softc *chp; 2703 { 2704 struct ata_drive_datas *drvp; 2705 int drive; 2706 u_int32_t acer_fifo_udma; 2707 u_int32_t idedma_ctl; 2708 struct pciide_channel *cp = (struct pciide_channel*)chp; 2709 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2710 2711 idedma_ctl = 0; 2712 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2713 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2714 acer_fifo_udma), DEBUG_PROBE); 2715 /* setup DMA if needed */ 2716 pciide_channel_dma_setup(cp); 2717 2718 for (drive = 0; drive < 2; drive++) { 2719 drvp = &chp->ch_drive[drive]; 2720 /* If no drive, skip */ 2721 if ((drvp->drive_flags & DRIVE) == 0) 2722 continue; 2723 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2724 "channel %d drive %d 0x%x\n", chp->channel, drive, 2725 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2726 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2727 /* clear FIFO/DMA mode */ 2728 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2729 ACER_UDMA_EN(chp->channel, drive) | 2730 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2731 2732 /* add timing values, setup DMA if needed */ 2733 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2734 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2735 acer_fifo_udma |= 2736 ACER_FTH_OPL(chp->channel, drive, 0x1); 2737 goto pio; 2738 } 2739 2740 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2741 if (drvp->drive_flags & DRIVE_UDMA) { 2742 /* use Ultra/DMA */ 2743 drvp->drive_flags &= ~DRIVE_DMA; 2744 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2745 acer_fifo_udma |= 2746 ACER_UDMA_TIM(chp->channel, drive, 2747 acer_udma[drvp->UDMA_mode]); 2748 } else { 2749 /* 2750 * use Multiword DMA 2751 * Timings will be used for both PIO and DMA, 2752 * so adjust DMA mode if needed 2753 */ 2754 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2755 drvp->PIO_mode = drvp->DMA_mode + 2; 2756 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2757 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2758 drvp->PIO_mode - 2 : 0; 2759 if (drvp->DMA_mode == 0) 2760 drvp->PIO_mode = 0; 2761 } 2762 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2763 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2764 ACER_IDETIM(chp->channel, drive), 2765 acer_pio[drvp->PIO_mode]); 2766 } 2767 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2768 acer_fifo_udma), DEBUG_PROBE); 2769 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2770 if (idedma_ctl != 0) { 2771 /* Add software bits in status register */ 2772 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2773 IDEDMA_CTL, idedma_ctl); 2774 } 2775 pciide_print_modes(cp); 2776 } 2777 2778 int 2779 acer_pci_intr(arg) 2780 void *arg; 2781 { 2782 struct pciide_softc *sc = arg; 2783 struct pciide_channel *cp; 2784 struct channel_softc *wdc_cp; 2785 int i, rv, crv; 2786 u_int32_t chids; 2787 2788 rv = 0; 2789 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2790 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2791 cp = &sc->pciide_channels[i]; 2792 wdc_cp = &cp->wdc_channel; 2793 /* If a compat channel skip. */ 2794 if (cp->compat) 2795 continue; 2796 if (chids & ACER_CHIDS_INT(i)) { 2797 crv = wdcintr(wdc_cp); 2798 if (crv == 0) 2799 printf("%s:%d: bogus intr\n", 2800 sc->sc_wdcdev.sc_dev.dv_xname, i); 2801 else 2802 rv = 1; 2803 } 2804 } 2805 return rv; 2806 } 2807 2808 void 2809 hpt_chip_map(sc, pa) 2810 struct pciide_softc *sc; 2811 struct pci_attach_args *pa; 2812 { 2813 struct pciide_channel *cp; 2814 int i, compatchan, revision; 2815 pcireg_t interface; 2816 bus_size_t cmdsize, ctlsize; 2817 2818 if (pciide_chipen(sc, pa) == 0) 2819 return; 2820 revision = PCI_REVISION(pa->pa_class); 2821 2822 /* 2823 * when the chip is in native mode it identifies itself as a 2824 * 'misc mass storage'. Fake interface in this case. 2825 */ 2826 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2827 interface = PCI_INTERFACE(pa->pa_class); 2828 } else { 2829 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2830 PCIIDE_INTERFACE_PCI(0); 2831 if (revision == HPT370_REV) 2832 interface |= PCIIDE_INTERFACE_PCI(1); 2833 } 2834 2835 printf("%s: bus-master DMA support present", 2836 sc->sc_wdcdev.sc_dev.dv_xname); 2837 pciide_mapreg_dma(sc, pa); 2838 printf("\n"); 2839 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2840 WDC_CAPABILITY_MODE; 2841 if (sc->sc_dma_ok) { 2842 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2843 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2844 sc->sc_wdcdev.irqack = pciide_irqack; 2845 } 2846 sc->sc_wdcdev.PIO_cap = 4; 2847 sc->sc_wdcdev.DMA_cap = 2; 2848 sc->sc_wdcdev.UDMA_cap = 4; 2849 2850 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2851 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2852 if (revision == HPT366_REV) { 2853 /* 2854 * The 366 has 2 PCI IDE functions, one for primary and one 2855 * for secondary. So we need to call pciide_mapregs_compat() 2856 * with the real channel 2857 */ 2858 if (pa->pa_function == 0) { 2859 compatchan = 0; 2860 } else if (pa->pa_function == 1) { 2861 compatchan = 1; 2862 } else { 2863 printf("%s: unexpected PCI function %d\n", 2864 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2865 return; 2866 } 2867 sc->sc_wdcdev.nchannels = 1; 2868 } else { 2869 sc->sc_wdcdev.nchannels = 2; 2870 } 2871 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2872 cp = &sc->pciide_channels[i]; 2873 if (sc->sc_wdcdev.nchannels > 1) { 2874 compatchan = i; 2875 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2876 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2877 printf("%s: %s channel ignored (disabled)\n", 2878 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2879 continue; 2880 } 2881 } 2882 if (pciide_chansetup(sc, i, interface) == 0) 2883 continue; 2884 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2885 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2886 &ctlsize, hpt_pci_intr); 2887 } else { 2888 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2889 &cmdsize, &ctlsize); 2890 } 2891 if (cp->hw_ok == 0) 2892 return; 2893 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2894 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2895 wdcattach(&cp->wdc_channel); 2896 hpt_setup_channel(&cp->wdc_channel); 2897 } 2898 2899 return; 2900 } 2901 2902 2903 void 2904 hpt_setup_channel(chp) 2905 struct channel_softc *chp; 2906 { 2907 struct ata_drive_datas *drvp; 2908 int drive; 2909 int cable; 2910 u_int32_t before, after; 2911 u_int32_t idedma_ctl; 2912 struct pciide_channel *cp = (struct pciide_channel*)chp; 2913 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2914 2915 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 2916 2917 /* setup DMA if needed */ 2918 pciide_channel_dma_setup(cp); 2919 2920 idedma_ctl = 0; 2921 2922 /* Per drive settings */ 2923 for (drive = 0; drive < 2; drive++) { 2924 drvp = &chp->ch_drive[drive]; 2925 /* If no drive, skip */ 2926 if ((drvp->drive_flags & DRIVE) == 0) 2927 continue; 2928 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 2929 HPT_IDETIM(chp->channel, drive)); 2930 2931 /* add timing values, setup DMA if needed */ 2932 if (drvp->drive_flags & DRIVE_UDMA) { 2933 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 2934 drvp->UDMA_mode > 2) 2935 drvp->UDMA_mode = 2; 2936 after = (sc->sc_wdcdev.nchannels == 2) ? 2937 hpt370_udma[drvp->UDMA_mode] : 2938 hpt366_udma[drvp->UDMA_mode]; 2939 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2940 } else if (drvp->drive_flags & DRIVE_DMA) { 2941 /* 2942 * use Multiword DMA. 2943 * Timings will be used for both PIO and DMA, so adjust 2944 * DMA mode if needed 2945 */ 2946 if (drvp->PIO_mode >= 3 && 2947 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2948 drvp->DMA_mode = drvp->PIO_mode - 2; 2949 } 2950 after = (sc->sc_wdcdev.nchannels == 2) ? 2951 hpt370_dma[drvp->DMA_mode] : 2952 hpt366_dma[drvp->DMA_mode]; 2953 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2954 } else { 2955 /* PIO only */ 2956 after = (sc->sc_wdcdev.nchannels == 2) ? 2957 hpt370_pio[drvp->PIO_mode] : 2958 hpt366_pio[drvp->PIO_mode]; 2959 } 2960 pci_conf_write(sc->sc_pc, sc->sc_tag, 2961 HPT_IDETIM(chp->channel, drive), after); 2962 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 2963 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 2964 after, before), DEBUG_PROBE); 2965 } 2966 if (idedma_ctl != 0) { 2967 /* Add software bits in status register */ 2968 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2969 IDEDMA_CTL, idedma_ctl); 2970 } 2971 pciide_print_modes(cp); 2972 } 2973 2974 int 2975 hpt_pci_intr(arg) 2976 void *arg; 2977 { 2978 struct pciide_softc *sc = arg; 2979 struct pciide_channel *cp; 2980 struct channel_softc *wdc_cp; 2981 int rv = 0; 2982 int dmastat, i, crv; 2983 2984 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2985 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2986 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 2987 if((dmastat & IDEDMA_CTL_INTR) == 0) 2988 continue; 2989 cp = &sc->pciide_channels[i]; 2990 wdc_cp = &cp->wdc_channel; 2991 crv = wdcintr(wdc_cp); 2992 if (crv == 0) { 2993 printf("%s:%d: bogus intr\n", 2994 sc->sc_wdcdev.sc_dev.dv_xname, i); 2995 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2996 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 2997 } else 2998 rv = 1; 2999 } 3000 return rv; 3001 } 3002 3003 3004 /* A macro to test product */ 3005 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 3006 3007 void 3008 pdc202xx_chip_map(sc, pa) 3009 struct pciide_softc *sc; 3010 struct pci_attach_args *pa; 3011 { 3012 struct pciide_channel *cp; 3013 int channel; 3014 pcireg_t interface, st, mode; 3015 bus_size_t cmdsize, ctlsize; 3016 3017 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3018 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3019 DEBUG_PROBE); 3020 if (pciide_chipen(sc, pa) == 0) 3021 return; 3022 3023 /* turn off RAID mode */ 3024 st &= ~PDC2xx_STATE_IDERAID; 3025 3026 /* 3027 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3028 * mode. We have to fake interface 3029 */ 3030 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3031 if (st & PDC2xx_STATE_NATIVE) 3032 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3033 3034 printf("%s: bus-master DMA support present", 3035 sc->sc_wdcdev.sc_dev.dv_xname); 3036 pciide_mapreg_dma(sc, pa); 3037 printf("\n"); 3038 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3039 WDC_CAPABILITY_MODE; 3040 if (sc->sc_dma_ok) { 3041 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3042 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3043 sc->sc_wdcdev.irqack = pciide_irqack; 3044 } 3045 sc->sc_wdcdev.PIO_cap = 4; 3046 sc->sc_wdcdev.DMA_cap = 2; 3047 if (PDC_IS_262(sc)) 3048 sc->sc_wdcdev.UDMA_cap = 4; 3049 else 3050 sc->sc_wdcdev.UDMA_cap = 2; 3051 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3052 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3053 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3054 3055 /* setup failsafe defaults */ 3056 mode = 0; 3057 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3058 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3059 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3060 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3061 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3062 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3063 "initial timings 0x%x, now 0x%x\n", channel, 3064 pci_conf_read(sc->sc_pc, sc->sc_tag, 3065 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3066 DEBUG_PROBE); 3067 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3068 mode | PDC2xx_TIM_IORDYp); 3069 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3070 "initial timings 0x%x, now 0x%x\n", channel, 3071 pci_conf_read(sc->sc_pc, sc->sc_tag, 3072 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3073 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3074 mode); 3075 } 3076 3077 mode = PDC2xx_SCR_DMA; 3078 if (PDC_IS_262(sc)) { 3079 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3080 } else { 3081 /* the BIOS set it up this way */ 3082 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3083 } 3084 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3085 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3086 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3087 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3088 DEBUG_PROBE); 3089 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3090 3091 /* controller initial state register is OK even without BIOS */ 3092 /* Set DMA mode to IDE DMA compatibility */ 3093 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3094 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3095 DEBUG_PROBE); 3096 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3097 mode | 0x1); 3098 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3099 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3100 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3101 mode | 0x1); 3102 3103 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3104 cp = &sc->pciide_channels[channel]; 3105 if (pciide_chansetup(sc, channel, interface) == 0) 3106 continue; 3107 if ((st & (PDC_IS_262(sc) ? 3108 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3109 printf("%s: %s channel ignored (disabled)\n", 3110 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3111 continue; 3112 } 3113 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3114 pdc202xx_pci_intr); 3115 if (cp->hw_ok == 0) 3116 continue; 3117 if (pciide_chan_candisable(cp)) 3118 st &= ~(PDC_IS_262(sc) ? 3119 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3120 pciide_map_compat_intr(pa, cp, channel, interface); 3121 pdc202xx_setup_channel(&cp->wdc_channel); 3122 } 3123 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3124 DEBUG_PROBE); 3125 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3126 return; 3127 } 3128 3129 void 3130 pdc202xx_setup_channel(chp) 3131 struct channel_softc *chp; 3132 { 3133 struct ata_drive_datas *drvp; 3134 int drive; 3135 pcireg_t mode, st; 3136 u_int32_t idedma_ctl, scr, atapi; 3137 struct pciide_channel *cp = (struct pciide_channel*)chp; 3138 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3139 int channel = chp->channel; 3140 3141 /* setup DMA if needed */ 3142 pciide_channel_dma_setup(cp); 3143 3144 idedma_ctl = 0; 3145 3146 /* Per channel settings */ 3147 if (PDC_IS_262(sc)) { 3148 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3149 PDC262_U66); 3150 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3151 /* Trimm UDMA mode */ 3152 if ((st & PDC262_STATE_80P(channel)) != 0 || 3153 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3154 chp->ch_drive[0].UDMA_mode <= 2) || 3155 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3156 chp->ch_drive[1].UDMA_mode <= 2)) { 3157 if (chp->ch_drive[0].UDMA_mode > 2) 3158 chp->ch_drive[0].UDMA_mode = 2; 3159 if (chp->ch_drive[1].UDMA_mode > 2) 3160 chp->ch_drive[1].UDMA_mode = 2; 3161 } 3162 /* Set U66 if needed */ 3163 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3164 chp->ch_drive[0].UDMA_mode > 2) || 3165 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3166 chp->ch_drive[1].UDMA_mode > 2)) 3167 scr |= PDC262_U66_EN(channel); 3168 else 3169 scr &= ~PDC262_U66_EN(channel); 3170 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3171 PDC262_U66, scr); 3172 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3173 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3174 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3175 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3176 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3177 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3178 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3179 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3180 atapi = 0; 3181 else 3182 atapi = PDC262_ATAPI_UDMA; 3183 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3184 PDC262_ATAPI(channel), atapi); 3185 } 3186 } 3187 for (drive = 0; drive < 2; drive++) { 3188 drvp = &chp->ch_drive[drive]; 3189 /* If no drive, skip */ 3190 if ((drvp->drive_flags & DRIVE) == 0) 3191 continue; 3192 mode = 0; 3193 if (drvp->drive_flags & DRIVE_UDMA) { 3194 mode = PDC2xx_TIM_SET_MB(mode, 3195 pdc2xx_udma_mb[drvp->UDMA_mode]); 3196 mode = PDC2xx_TIM_SET_MC(mode, 3197 pdc2xx_udma_mc[drvp->UDMA_mode]); 3198 drvp->drive_flags &= ~DRIVE_DMA; 3199 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3200 } else if (drvp->drive_flags & DRIVE_DMA) { 3201 mode = PDC2xx_TIM_SET_MB(mode, 3202 pdc2xx_dma_mb[drvp->DMA_mode]); 3203 mode = PDC2xx_TIM_SET_MC(mode, 3204 pdc2xx_dma_mc[drvp->DMA_mode]); 3205 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3206 } else { 3207 mode = PDC2xx_TIM_SET_MB(mode, 3208 pdc2xx_dma_mb[0]); 3209 mode = PDC2xx_TIM_SET_MC(mode, 3210 pdc2xx_dma_mc[0]); 3211 } 3212 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3213 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3214 if (drvp->drive_flags & DRIVE_ATA) 3215 mode |= PDC2xx_TIM_PRE; 3216 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3217 if (drvp->PIO_mode >= 3) { 3218 mode |= PDC2xx_TIM_IORDY; 3219 if (drive == 0) 3220 mode |= PDC2xx_TIM_IORDYp; 3221 } 3222 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3223 "timings 0x%x\n", 3224 sc->sc_wdcdev.sc_dev.dv_xname, 3225 chp->channel, drive, mode), DEBUG_PROBE); 3226 pci_conf_write(sc->sc_pc, sc->sc_tag, 3227 PDC2xx_TIM(chp->channel, drive), mode); 3228 } 3229 if (idedma_ctl != 0) { 3230 /* Add software bits in status register */ 3231 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3232 IDEDMA_CTL, idedma_ctl); 3233 } 3234 pciide_print_modes(cp); 3235 } 3236 3237 int 3238 pdc202xx_pci_intr(arg) 3239 void *arg; 3240 { 3241 struct pciide_softc *sc = arg; 3242 struct pciide_channel *cp; 3243 struct channel_softc *wdc_cp; 3244 int i, rv, crv; 3245 u_int32_t scr; 3246 3247 rv = 0; 3248 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3249 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3250 cp = &sc->pciide_channels[i]; 3251 wdc_cp = &cp->wdc_channel; 3252 /* If a compat channel skip. */ 3253 if (cp->compat) 3254 continue; 3255 if (scr & PDC2xx_SCR_INT(i)) { 3256 crv = wdcintr(wdc_cp); 3257 if (crv == 0) 3258 printf("%s:%d: bogus intr\n", 3259 sc->sc_wdcdev.sc_dev.dv_xname, i); 3260 else 3261 rv = 1; 3262 } 3263 } 3264 return rv; 3265 } 3266 3267 void 3268 opti_chip_map(sc, pa) 3269 struct pciide_softc *sc; 3270 struct pci_attach_args *pa; 3271 { 3272 struct pciide_channel *cp; 3273 bus_size_t cmdsize, ctlsize; 3274 pcireg_t interface; 3275 u_int8_t init_ctrl; 3276 int channel; 3277 3278 if (pciide_chipen(sc, pa) == 0) 3279 return; 3280 printf("%s: bus-master DMA support present", 3281 sc->sc_wdcdev.sc_dev.dv_xname); 3282 pciide_mapreg_dma(sc, pa); 3283 printf("\n"); 3284 3285 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3286 WDC_CAPABILITY_MODE; 3287 sc->sc_wdcdev.PIO_cap = 4; 3288 if (sc->sc_dma_ok) { 3289 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3290 sc->sc_wdcdev.irqack = pciide_irqack; 3291 sc->sc_wdcdev.DMA_cap = 2; 3292 } 3293 sc->sc_wdcdev.set_modes = opti_setup_channel; 3294 3295 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3296 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3297 3298 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3299 OPTI_REG_INIT_CONTROL); 3300 3301 interface = PCI_INTERFACE(pa->pa_class); 3302 3303 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3304 cp = &sc->pciide_channels[channel]; 3305 if (pciide_chansetup(sc, channel, interface) == 0) 3306 continue; 3307 if (channel == 1 && 3308 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3309 printf("%s: %s channel ignored (disabled)\n", 3310 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3311 continue; 3312 } 3313 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3314 pciide_pci_intr); 3315 if (cp->hw_ok == 0) 3316 continue; 3317 pciide_map_compat_intr(pa, cp, channel, interface); 3318 if (cp->hw_ok == 0) 3319 continue; 3320 opti_setup_channel(&cp->wdc_channel); 3321 } 3322 } 3323 3324 void 3325 opti_setup_channel(chp) 3326 struct channel_softc *chp; 3327 { 3328 struct ata_drive_datas *drvp; 3329 struct pciide_channel *cp = (struct pciide_channel*)chp; 3330 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3331 int drive, spd; 3332 int mode[2]; 3333 u_int8_t rv, mr; 3334 3335 /* 3336 * The `Delay' and `Address Setup Time' fields of the 3337 * Miscellaneous Register are always zero initially. 3338 */ 3339 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3340 mr &= ~(OPTI_MISC_DELAY_MASK | 3341 OPTI_MISC_ADDR_SETUP_MASK | 3342 OPTI_MISC_INDEX_MASK); 3343 3344 /* Prime the control register before setting timing values */ 3345 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3346 3347 /* Determine the clockrate of the PCIbus the chip is attached to */ 3348 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3349 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3350 3351 /* setup DMA if needed */ 3352 pciide_channel_dma_setup(cp); 3353 3354 for (drive = 0; drive < 2; drive++) { 3355 drvp = &chp->ch_drive[drive]; 3356 /* If no drive, skip */ 3357 if ((drvp->drive_flags & DRIVE) == 0) { 3358 mode[drive] = -1; 3359 continue; 3360 } 3361 3362 if ((drvp->drive_flags & DRIVE_DMA)) { 3363 /* 3364 * Timings will be used for both PIO and DMA, 3365 * so adjust DMA mode if needed 3366 */ 3367 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3368 drvp->PIO_mode = drvp->DMA_mode + 2; 3369 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3370 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3371 drvp->PIO_mode - 2 : 0; 3372 if (drvp->DMA_mode == 0) 3373 drvp->PIO_mode = 0; 3374 3375 mode[drive] = drvp->DMA_mode + 5; 3376 } else 3377 mode[drive] = drvp->PIO_mode; 3378 3379 if (drive && mode[0] >= 0 && 3380 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3381 /* 3382 * Can't have two drives using different values 3383 * for `Address Setup Time'. 3384 * Slow down the faster drive to compensate. 3385 */ 3386 int d = (opti_tim_as[spd][mode[0]] > 3387 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3388 3389 mode[d] = mode[1-d]; 3390 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3391 chp->ch_drive[d].DMA_mode = 0; 3392 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3393 } 3394 } 3395 3396 for (drive = 0; drive < 2; drive++) { 3397 int m; 3398 if ((m = mode[drive]) < 0) 3399 continue; 3400 3401 /* Set the Address Setup Time and select appropriate index */ 3402 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3403 rv |= OPTI_MISC_INDEX(drive); 3404 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3405 3406 /* Set the pulse width and recovery timing parameters */ 3407 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3408 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3409 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3410 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3411 3412 /* Set the Enhanced Mode register appropriately */ 3413 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3414 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3415 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3416 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3417 } 3418 3419 /* Finally, enable the timings */ 3420 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3421 3422 pciide_print_modes(cp); 3423 } 3424
Indexes created Thu Oct 02 10:09:58 GMT 2025