pciide.c revision 1.73
1 /* $NetBSD: pciide.c,v 1.73 2000/06/28 16:08:49 mrg Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 #include <dev/pci/pciidereg.h> 105 #include <dev/pci/pciidevar.h> 106 #include <dev/pci/pciide_piix_reg.h> 107 #include <dev/pci/pciide_amd_reg.h> 108 #include <dev/pci/pciide_apollo_reg.h> 109 #include <dev/pci/pciide_cmd_reg.h> 110 #include <dev/pci/pciide_cy693_reg.h> 111 #include <dev/pci/pciide_sis_reg.h> 112 #include <dev/pci/pciide_acer_reg.h> 113 #include <dev/pci/pciide_pdc202xx_reg.h> 114 #include <dev/pci/pciide_opti_reg.h> 115 #include <dev/pci/pciide_hpt_reg.h> 116 #include <dev/pci/cy82c693var.h> 117 118 /* inlines for reading/writing 8-bit PCI registers */ 119 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 120 int)); 121 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 122 int, u_int8_t)); 123 124 static __inline u_int8_t 125 pciide_pci_read(pc, pa, reg) 126 pci_chipset_tag_t pc; 127 pcitag_t pa; 128 int reg; 129 { 130 131 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 132 ((reg & 0x03) * 8) & 0xff); 133 } 134 135 static __inline void 136 pciide_pci_write(pc, pa, reg, val) 137 pci_chipset_tag_t pc; 138 pcitag_t pa; 139 int reg; 140 u_int8_t val; 141 { 142 pcireg_t pcival; 143 144 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 145 pcival &= ~(0xff << ((reg & 0x03) * 8)); 146 pcival |= (val << ((reg & 0x03) * 8)); 147 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 148 } 149 150 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 151 152 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 153 void piix_setup_channel __P((struct channel_softc*)); 154 void piix3_4_setup_channel __P((struct channel_softc*)); 155 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 156 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 157 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 158 159 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 160 void amd756_setup_channel __P((struct channel_softc*)); 161 162 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 163 void apollo_setup_channel __P((struct channel_softc*)); 164 165 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 166 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 167 void cmd0643_9_setup_channel __P((struct channel_softc*)); 168 void cmd_channel_map __P((struct pci_attach_args *, 169 struct pciide_softc *, int)); 170 int cmd_pci_intr __P((void *)); 171 void cmd648_9_irqack __P((struct channel_softc *)); 172 173 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cy693_setup_channel __P((struct channel_softc*)); 175 176 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 177 void sis_setup_channel __P((struct channel_softc*)); 178 179 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 180 void acer_setup_channel __P((struct channel_softc*)); 181 int acer_pci_intr __P((void *)); 182 183 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 184 void pdc202xx_setup_channel __P((struct channel_softc*)); 185 int pdc202xx_pci_intr __P((void *)); 186 187 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 188 void opti_setup_channel __P((struct channel_softc*)); 189 190 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 191 void hpt_setup_channel __P((struct channel_softc*)); 192 int hpt_pci_intr __P((void *)); 193 194 void pciide_channel_dma_setup __P((struct pciide_channel *)); 195 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 196 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 197 void pciide_dma_start __P((void*, int, int)); 198 int pciide_dma_finish __P((void*, int, int, int)); 199 void pciide_irqack __P((struct channel_softc *)); 200 void pciide_print_modes __P((struct pciide_channel *)); 201 202 struct pciide_product_desc { 203 u_int32_t ide_product; 204 int ide_flags; 205 const char *ide_name; 206 /* map and setup chip, probe drives */ 207 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 208 }; 209 210 /* Flags for ide_flags */ 211 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 212 213 /* Default product description for devices not known from this controller */ 214 const struct pciide_product_desc default_product_desc = { 215 0, 216 0, 217 "Generic PCI IDE controller", 218 default_chip_map, 219 }; 220 221 const struct pciide_product_desc pciide_intel_products[] = { 222 { PCI_PRODUCT_INTEL_82092AA, 223 0, 224 "Intel 82092AA IDE controller", 225 default_chip_map, 226 }, 227 { PCI_PRODUCT_INTEL_82371FB_IDE, 228 0, 229 "Intel 82371FB IDE controller (PIIX)", 230 piix_chip_map, 231 }, 232 { PCI_PRODUCT_INTEL_82371SB_IDE, 233 0, 234 "Intel 82371SB IDE Interface (PIIX3)", 235 piix_chip_map, 236 }, 237 { PCI_PRODUCT_INTEL_82371AB_IDE, 238 0, 239 "Intel 82371AB IDE controller (PIIX4)", 240 piix_chip_map, 241 }, 242 { PCI_PRODUCT_INTEL_82801AA_IDE, 243 0, 244 "Intel 82801AA IDE Controller (ICH)", 245 piix_chip_map, 246 }, 247 { PCI_PRODUCT_INTEL_82801AB_IDE, 248 0, 249 "Intel 82801AB IDE Controller (ICH0)", 250 piix_chip_map, 251 }, 252 { 0, 253 0, 254 NULL, 255 } 256 }; 257 258 const struct pciide_product_desc pciide_amd_products[] = { 259 { PCI_PRODUCT_AMD_PBC756_IDE, 260 0, 261 "Advanced Micro Devices AMD756 IDE Controller", 262 amd756_chip_map 263 }, 264 { 0, 265 0, 266 NULL, 267 } 268 }; 269 270 const struct pciide_product_desc pciide_cmd_products[] = { 271 { PCI_PRODUCT_CMDTECH_640, 272 0, 273 "CMD Technology PCI0640", 274 cmd_chip_map 275 }, 276 { PCI_PRODUCT_CMDTECH_643, 277 0, 278 "CMD Technology PCI0643", 279 cmd0643_9_chip_map, 280 }, 281 { PCI_PRODUCT_CMDTECH_646, 282 0, 283 "CMD Technology PCI0646", 284 cmd0643_9_chip_map, 285 }, 286 { PCI_PRODUCT_CMDTECH_648, 287 IDE_PCI_CLASS_OVERRIDE, 288 "CMD Technology PCI0648", 289 cmd0643_9_chip_map, 290 }, 291 { PCI_PRODUCT_CMDTECH_649, 292 IDE_PCI_CLASS_OVERRIDE, 293 "CMD Technology PCI0649", 294 cmd0643_9_chip_map, 295 }, 296 { 0, 297 0, 298 NULL, 299 } 300 }; 301 302 const struct pciide_product_desc pciide_via_products[] = { 303 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 304 0, 305 "VIA Tech VT82C586 IDE Controller", 306 apollo_chip_map, 307 }, 308 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 309 0, 310 "VIA Tech VT82C586A IDE Controller", 311 apollo_chip_map, 312 }, 313 { 0, 314 0, 315 NULL, 316 } 317 }; 318 319 const struct pciide_product_desc pciide_cypress_products[] = { 320 { PCI_PRODUCT_CONTAQ_82C693, 321 0, 322 "Cypress 82C693 IDE Controller", 323 cy693_chip_map, 324 }, 325 { 0, 326 0, 327 NULL, 328 } 329 }; 330 331 const struct pciide_product_desc pciide_sis_products[] = { 332 { PCI_PRODUCT_SIS_5597_IDE, 333 0, 334 "Silicon Integrated System 5597/5598 IDE controller", 335 sis_chip_map, 336 }, 337 { 0, 338 0, 339 NULL, 340 } 341 }; 342 343 const struct pciide_product_desc pciide_acer_products[] = { 344 { PCI_PRODUCT_ALI_M5229, 345 0, 346 "Acer Labs M5229 UDMA IDE Controller", 347 acer_chip_map, 348 }, 349 { 0, 350 0, 351 NULL, 352 } 353 }; 354 355 const struct pciide_product_desc pciide_promise_products[] = { 356 { PCI_PRODUCT_PROMISE_ULTRA33, 357 IDE_PCI_CLASS_OVERRIDE, 358 "Promise Ultra33/ATA Bus Master IDE Accelerator", 359 pdc202xx_chip_map, 360 }, 361 { PCI_PRODUCT_PROMISE_ULTRA66, 362 IDE_PCI_CLASS_OVERRIDE, 363 "Promise Ultra66/ATA Bus Master IDE Accelerator", 364 pdc202xx_chip_map, 365 }, 366 { 0, 367 0, 368 NULL, 369 } 370 }; 371 372 const struct pciide_product_desc pciide_opti_products[] = { 373 { PCI_PRODUCT_OPTI_82C621, 374 0, 375 "OPTi 82c621 PCI IDE controller", 376 opti_chip_map, 377 }, 378 { PCI_PRODUCT_OPTI_82C568, 379 0, 380 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 381 opti_chip_map, 382 }, 383 { PCI_PRODUCT_OPTI_82D568, 384 0, 385 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 386 opti_chip_map, 387 }, 388 { 0, 389 0, 390 NULL, 391 } 392 }; 393 394 const struct pciide_product_desc pciide_triones_products[] = { 395 { PCI_PRODUCT_TRIONES_HPT366, 396 IDE_PCI_CLASS_OVERRIDE, 397 "Triones/Highpoint HPT366/370 IDE Controller", 398 hpt_chip_map, 399 }, 400 { 0, 401 0, 402 NULL, 403 } 404 }; 405 406 struct pciide_vendor_desc { 407 u_int32_t ide_vendor; 408 const struct pciide_product_desc *ide_products; 409 }; 410 411 const struct pciide_vendor_desc pciide_vendors[] = { 412 { PCI_VENDOR_INTEL, pciide_intel_products }, 413 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 414 { PCI_VENDOR_VIATECH, pciide_via_products }, 415 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 416 { PCI_VENDOR_SIS, pciide_sis_products }, 417 { PCI_VENDOR_ALI, pciide_acer_products }, 418 { PCI_VENDOR_PROMISE, pciide_promise_products }, 419 { PCI_VENDOR_AMD, pciide_amd_products }, 420 { PCI_VENDOR_OPTI, pciide_opti_products }, 421 { PCI_VENDOR_TRIONES, pciide_triones_products }, 422 { 0, NULL } 423 }; 424 425 /* options passed via the 'flags' config keyword */ 426 #define PCIIDE_OPTIONS_DMA 0x01 427 428 int pciide_match __P((struct device *, struct cfdata *, void *)); 429 void pciide_attach __P((struct device *, struct device *, void *)); 430 431 struct cfattach pciide_ca = { 432 sizeof(struct pciide_softc), pciide_match, pciide_attach 433 }; 434 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 435 int pciide_mapregs_compat __P(( struct pci_attach_args *, 436 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 437 int pciide_mapregs_native __P((struct pci_attach_args *, 438 struct pciide_channel *, bus_size_t *, bus_size_t *, 439 int (*pci_intr) __P((void *)))); 440 void pciide_mapreg_dma __P((struct pciide_softc *, 441 struct pci_attach_args *)); 442 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 443 void pciide_mapchan __P((struct pci_attach_args *, 444 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 445 int (*pci_intr) __P((void *)))); 446 int pciide_chan_candisable __P((struct pciide_channel *)); 447 void pciide_map_compat_intr __P(( struct pci_attach_args *, 448 struct pciide_channel *, int, int)); 449 int pciide_print __P((void *, const char *pnp)); 450 int pciide_compat_intr __P((void *)); 451 int pciide_pci_intr __P((void *)); 452 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 453 454 const struct pciide_product_desc * 455 pciide_lookup_product(id) 456 u_int32_t id; 457 { 458 const struct pciide_product_desc *pp; 459 const struct pciide_vendor_desc *vp; 460 461 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 462 if (PCI_VENDOR(id) == vp->ide_vendor) 463 break; 464 465 if ((pp = vp->ide_products) == NULL) 466 return NULL; 467 468 for (; pp->ide_name != NULL; pp++) 469 if (PCI_PRODUCT(id) == pp->ide_product) 470 break; 471 472 if (pp->ide_name == NULL) 473 return NULL; 474 return pp; 475 } 476 477 int 478 pciide_match(parent, match, aux) 479 struct device *parent; 480 struct cfdata *match; 481 void *aux; 482 { 483 struct pci_attach_args *pa = aux; 484 const struct pciide_product_desc *pp; 485 486 /* 487 * Check the ID register to see that it's a PCI IDE controller. 488 * If it is, we assume that we can deal with it; it _should_ 489 * work in a standardized way... 490 */ 491 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 492 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 493 return (1); 494 } 495 496 /* 497 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 498 * controllers. Let see if we can deal with it anyway. 499 */ 500 pp = pciide_lookup_product(pa->pa_id); 501 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 502 return (1); 503 } 504 505 return (0); 506 } 507 508 void 509 pciide_attach(parent, self, aux) 510 struct device *parent, *self; 511 void *aux; 512 { 513 struct pci_attach_args *pa = aux; 514 pci_chipset_tag_t pc = pa->pa_pc; 515 pcitag_t tag = pa->pa_tag; 516 struct pciide_softc *sc = (struct pciide_softc *)self; 517 pcireg_t csr; 518 char devinfo[256]; 519 const char *displaydev; 520 521 sc->sc_pp = pciide_lookup_product(pa->pa_id); 522 if (sc->sc_pp == NULL) { 523 sc->sc_pp = &default_product_desc; 524 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 525 displaydev = devinfo; 526 } else 527 displaydev = sc->sc_pp->ide_name; 528 529 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 530 531 sc->sc_pc = pa->pa_pc; 532 sc->sc_tag = pa->pa_tag; 533 #ifdef WDCDEBUG 534 if (wdcdebug_pciide_mask & DEBUG_PROBE) 535 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 536 #endif 537 sc->sc_pp->chip_map(sc, pa); 538 539 if (sc->sc_dma_ok) { 540 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 541 csr |= PCI_COMMAND_MASTER_ENABLE; 542 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 543 } 544 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 545 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 546 } 547 548 /* tell wether the chip is enabled or not */ 549 int 550 pciide_chipen(sc, pa) 551 struct pciide_softc *sc; 552 struct pci_attach_args *pa; 553 { 554 pcireg_t csr; 555 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 556 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 557 PCI_COMMAND_STATUS_REG); 558 printf("%s: device disabled (at %s)\n", 559 sc->sc_wdcdev.sc_dev.dv_xname, 560 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 561 "device" : "bridge"); 562 return 0; 563 } 564 return 1; 565 } 566 567 int 568 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 569 struct pci_attach_args *pa; 570 struct pciide_channel *cp; 571 int compatchan; 572 bus_size_t *cmdsizep, *ctlsizep; 573 { 574 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 575 struct channel_softc *wdc_cp = &cp->wdc_channel; 576 577 cp->compat = 1; 578 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 579 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 580 581 wdc_cp->cmd_iot = pa->pa_iot; 582 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 583 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 584 printf("%s: couldn't map %s channel cmd regs\n", 585 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 586 return (0); 587 } 588 589 wdc_cp->ctl_iot = pa->pa_iot; 590 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 591 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 592 printf("%s: couldn't map %s channel ctl regs\n", 593 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 594 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 595 PCIIDE_COMPAT_CMD_SIZE); 596 return (0); 597 } 598 599 return (1); 600 } 601 602 int 603 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 604 struct pci_attach_args * pa; 605 struct pciide_channel *cp; 606 bus_size_t *cmdsizep, *ctlsizep; 607 int (*pci_intr) __P((void *)); 608 { 609 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 610 struct channel_softc *wdc_cp = &cp->wdc_channel; 611 const char *intrstr; 612 pci_intr_handle_t intrhandle; 613 614 cp->compat = 0; 615 616 if (sc->sc_pci_ih == NULL) { 617 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 618 pa->pa_intrline, &intrhandle) != 0) { 619 printf("%s: couldn't map native-PCI interrupt\n", 620 sc->sc_wdcdev.sc_dev.dv_xname); 621 return 0; 622 } 623 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 624 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 625 intrhandle, IPL_BIO, pci_intr, sc); 626 if (sc->sc_pci_ih != NULL) { 627 printf("%s: using %s for native-PCI interrupt\n", 628 sc->sc_wdcdev.sc_dev.dv_xname, 629 intrstr ? intrstr : "unknown interrupt"); 630 } else { 631 printf("%s: couldn't establish native-PCI interrupt", 632 sc->sc_wdcdev.sc_dev.dv_xname); 633 if (intrstr != NULL) 634 printf(" at %s", intrstr); 635 printf("\n"); 636 return 0; 637 } 638 } 639 cp->ih = sc->sc_pci_ih; 640 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 641 PCI_MAPREG_TYPE_IO, 0, 642 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 643 printf("%s: couldn't map %s channel cmd regs\n", 644 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 645 return 0; 646 } 647 648 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 649 PCI_MAPREG_TYPE_IO, 0, 650 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 651 printf("%s: couldn't map %s channel ctl regs\n", 652 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 653 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 654 return 0; 655 } 656 return (1); 657 } 658 659 void 660 pciide_mapreg_dma(sc, pa) 661 struct pciide_softc *sc; 662 struct pci_attach_args *pa; 663 { 664 pcireg_t maptype; 665 666 /* 667 * Map DMA registers 668 * 669 * Note that sc_dma_ok is the right variable to test to see if 670 * DMA can be done. If the interface doesn't support DMA, 671 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 672 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 673 * non-zero if the interface supports DMA and the registers 674 * could be mapped. 675 * 676 * XXX Note that despite the fact that the Bus Master IDE specs 677 * XXX say that "The bus master IDE function uses 16 bytes of IO 678 * XXX space," some controllers (at least the United 679 * XXX Microelectronics UM8886BF) place it in memory space. 680 */ 681 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 682 PCIIDE_REG_BUS_MASTER_DMA); 683 684 switch (maptype) { 685 case PCI_MAPREG_TYPE_IO: 686 case PCI_MAPREG_MEM_TYPE_32BIT: 687 sc->sc_dma_ok = (pci_mapreg_map(pa, 688 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 689 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 690 sc->sc_dmat = pa->pa_dmat; 691 if (sc->sc_dma_ok == 0) { 692 printf(", but unused (couldn't map registers)"); 693 } else { 694 sc->sc_wdcdev.dma_arg = sc; 695 sc->sc_wdcdev.dma_init = pciide_dma_init; 696 sc->sc_wdcdev.dma_start = pciide_dma_start; 697 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 698 } 699 break; 700 701 default: 702 sc->sc_dma_ok = 0; 703 printf(", but unsupported register maptype (0x%x)", maptype); 704 } 705 } 706 707 int 708 pciide_compat_intr(arg) 709 void *arg; 710 { 711 struct pciide_channel *cp = arg; 712 713 #ifdef DIAGNOSTIC 714 /* should only be called for a compat channel */ 715 if (cp->compat == 0) 716 panic("pciide compat intr called for non-compat chan %p\n", cp); 717 #endif 718 return (wdcintr(&cp->wdc_channel)); 719 } 720 721 int 722 pciide_pci_intr(arg) 723 void *arg; 724 { 725 struct pciide_softc *sc = arg; 726 struct pciide_channel *cp; 727 struct channel_softc *wdc_cp; 728 int i, rv, crv; 729 730 rv = 0; 731 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 732 cp = &sc->pciide_channels[i]; 733 wdc_cp = &cp->wdc_channel; 734 735 /* If a compat channel skip. */ 736 if (cp->compat) 737 continue; 738 /* if this channel not waiting for intr, skip */ 739 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 740 continue; 741 742 crv = wdcintr(wdc_cp); 743 if (crv == 0) 744 ; /* leave rv alone */ 745 else if (crv == 1) 746 rv = 1; /* claim the intr */ 747 else if (rv == 0) /* crv should be -1 in this case */ 748 rv = crv; /* if we've done no better, take it */ 749 } 750 return (rv); 751 } 752 753 void 754 pciide_channel_dma_setup(cp) 755 struct pciide_channel *cp; 756 { 757 int drive; 758 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 759 struct ata_drive_datas *drvp; 760 761 for (drive = 0; drive < 2; drive++) { 762 drvp = &cp->wdc_channel.ch_drive[drive]; 763 /* If no drive, skip */ 764 if ((drvp->drive_flags & DRIVE) == 0) 765 continue; 766 /* setup DMA if needed */ 767 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 768 (drvp->drive_flags & DRIVE_UDMA) == 0) || 769 sc->sc_dma_ok == 0) { 770 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 771 continue; 772 } 773 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 774 != 0) { 775 /* Abort DMA setup */ 776 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 777 continue; 778 } 779 } 780 } 781 782 int 783 pciide_dma_table_setup(sc, channel, drive) 784 struct pciide_softc *sc; 785 int channel, drive; 786 { 787 bus_dma_segment_t seg; 788 int error, rseg; 789 const bus_size_t dma_table_size = 790 sizeof(struct idedma_table) * NIDEDMA_TABLES; 791 struct pciide_dma_maps *dma_maps = 792 &sc->pciide_channels[channel].dma_maps[drive]; 793 794 /* If table was already allocated, just return */ 795 if (dma_maps->dma_table) 796 return 0; 797 798 /* Allocate memory for the DMA tables and map it */ 799 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 800 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 801 BUS_DMA_NOWAIT)) != 0) { 802 printf("%s:%d: unable to allocate table DMA for " 803 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 804 channel, drive, error); 805 return error; 806 } 807 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 808 dma_table_size, 809 (caddr_t *)&dma_maps->dma_table, 810 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 811 printf("%s:%d: unable to map table DMA for" 812 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 813 channel, drive, error); 814 return error; 815 } 816 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 817 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 818 seg.ds_addr), DEBUG_PROBE); 819 820 /* Create and load table DMA map for this disk */ 821 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 822 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 823 &dma_maps->dmamap_table)) != 0) { 824 printf("%s:%d: unable to create table DMA map for " 825 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 826 channel, drive, error); 827 return error; 828 } 829 if ((error = bus_dmamap_load(sc->sc_dmat, 830 dma_maps->dmamap_table, 831 dma_maps->dma_table, 832 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 833 printf("%s:%d: unable to load table DMA map for " 834 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 835 channel, drive, error); 836 return error; 837 } 838 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 839 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 840 /* Create a xfer DMA map for this drive */ 841 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 842 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 843 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 844 &dma_maps->dmamap_xfer)) != 0) { 845 printf("%s:%d: unable to create xfer DMA map for " 846 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 847 channel, drive, error); 848 return error; 849 } 850 return 0; 851 } 852 853 int 854 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 855 void *v; 856 int channel, drive; 857 void *databuf; 858 size_t datalen; 859 int flags; 860 { 861 struct pciide_softc *sc = v; 862 int error, seg; 863 struct pciide_dma_maps *dma_maps = 864 &sc->pciide_channels[channel].dma_maps[drive]; 865 866 error = bus_dmamap_load(sc->sc_dmat, 867 dma_maps->dmamap_xfer, 868 databuf, datalen, NULL, BUS_DMA_NOWAIT); 869 if (error) { 870 printf("%s:%d: unable to load xfer DMA map for" 871 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 872 channel, drive, error); 873 return error; 874 } 875 876 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 877 dma_maps->dmamap_xfer->dm_mapsize, 878 (flags & WDC_DMA_READ) ? 879 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 880 881 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 882 #ifdef DIAGNOSTIC 883 /* A segment must not cross a 64k boundary */ 884 { 885 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 886 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 887 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 888 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 889 printf("pciide_dma: segment %d physical addr 0x%lx" 890 " len 0x%lx not properly aligned\n", 891 seg, phys, len); 892 panic("pciide_dma: buf align"); 893 } 894 } 895 #endif 896 dma_maps->dma_table[seg].base_addr = 897 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 898 dma_maps->dma_table[seg].byte_count = 899 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 900 IDEDMA_BYTE_COUNT_MASK); 901 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 902 seg, le32toh(dma_maps->dma_table[seg].byte_count), 903 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 904 905 } 906 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 907 htole32(IDEDMA_BYTE_COUNT_EOT); 908 909 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 910 dma_maps->dmamap_table->dm_mapsize, 911 BUS_DMASYNC_PREWRITE); 912 913 /* Maps are ready. Start DMA function */ 914 #ifdef DIAGNOSTIC 915 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 916 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 917 dma_maps->dmamap_table->dm_segs[0].ds_addr); 918 panic("pciide_dma_init: table align"); 919 } 920 #endif 921 922 /* Clear status bits */ 923 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 924 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 925 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 926 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 927 /* Write table addr */ 928 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 929 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 930 dma_maps->dmamap_table->dm_segs[0].ds_addr); 931 /* set read/write */ 932 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 933 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 934 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 935 /* remember flags */ 936 dma_maps->dma_flags = flags; 937 return 0; 938 } 939 940 void 941 pciide_dma_start(v, channel, drive) 942 void *v; 943 int channel, drive; 944 { 945 struct pciide_softc *sc = v; 946 947 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 948 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 949 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 950 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 951 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 952 } 953 954 int 955 pciide_dma_finish(v, channel, drive, force) 956 void *v; 957 int channel, drive; 958 int force; 959 { 960 struct pciide_softc *sc = v; 961 u_int8_t status; 962 int error = 0; 963 struct pciide_dma_maps *dma_maps = 964 &sc->pciide_channels[channel].dma_maps[drive]; 965 966 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 967 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 968 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 969 DEBUG_XFERS); 970 971 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 972 return WDC_DMAST_NOIRQ; 973 974 /* stop DMA channel */ 975 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 976 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 977 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 978 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 979 980 /* Unload the map of the data buffer */ 981 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 982 dma_maps->dmamap_xfer->dm_mapsize, 983 (dma_maps->dma_flags & WDC_DMA_READ) ? 984 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 985 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 986 987 if ((status & IDEDMA_CTL_ERR) != 0) { 988 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 989 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 990 error |= WDC_DMAST_ERR; 991 } 992 993 if ((status & IDEDMA_CTL_INTR) == 0) { 994 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 995 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 996 drive, status); 997 error |= WDC_DMAST_NOIRQ; 998 } 999 1000 if ((status & IDEDMA_CTL_ACT) != 0) { 1001 /* data underrun, may be a valid condition for ATAPI */ 1002 error |= WDC_DMAST_UNDER; 1003 } 1004 return error; 1005 } 1006 1007 void 1008 pciide_irqack(chp) 1009 struct channel_softc *chp; 1010 { 1011 struct pciide_channel *cp = (struct pciide_channel*)chp; 1012 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1013 1014 /* clear status bits in IDE DMA registers */ 1015 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1016 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1017 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1018 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1019 } 1020 1021 /* some common code used by several chip_map */ 1022 int 1023 pciide_chansetup(sc, channel, interface) 1024 struct pciide_softc *sc; 1025 int channel; 1026 pcireg_t interface; 1027 { 1028 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1029 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1030 cp->name = PCIIDE_CHANNEL_NAME(channel); 1031 cp->wdc_channel.channel = channel; 1032 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1033 cp->wdc_channel.ch_queue = 1034 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1035 if (cp->wdc_channel.ch_queue == NULL) { 1036 printf("%s %s channel: " 1037 "can't allocate memory for command queue", 1038 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1039 return 0; 1040 } 1041 printf("%s: %s channel %s to %s mode\n", 1042 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1043 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1044 "configured" : "wired", 1045 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1046 "native-PCI" : "compatibility"); 1047 return 1; 1048 } 1049 1050 /* some common code used by several chip channel_map */ 1051 void 1052 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1053 struct pci_attach_args *pa; 1054 struct pciide_channel *cp; 1055 pcireg_t interface; 1056 bus_size_t *cmdsizep, *ctlsizep; 1057 int (*pci_intr) __P((void *)); 1058 { 1059 struct channel_softc *wdc_cp = &cp->wdc_channel; 1060 1061 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1062 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1063 pci_intr); 1064 else 1065 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1066 wdc_cp->channel, cmdsizep, ctlsizep); 1067 1068 if (cp->hw_ok == 0) 1069 return; 1070 wdc_cp->data32iot = wdc_cp->cmd_iot; 1071 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1072 wdcattach(wdc_cp); 1073 } 1074 1075 /* 1076 * Generic code to call to know if a channel can be disabled. Return 1 1077 * if channel can be disabled, 0 if not 1078 */ 1079 int 1080 pciide_chan_candisable(cp) 1081 struct pciide_channel *cp; 1082 { 1083 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1084 struct channel_softc *wdc_cp = &cp->wdc_channel; 1085 1086 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1087 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1088 printf("%s: disabling %s channel (no drives)\n", 1089 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1090 cp->hw_ok = 0; 1091 return 1; 1092 } 1093 return 0; 1094 } 1095 1096 /* 1097 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1098 * Set hw_ok=0 on failure 1099 */ 1100 void 1101 pciide_map_compat_intr(pa, cp, compatchan, interface) 1102 struct pci_attach_args *pa; 1103 struct pciide_channel *cp; 1104 int compatchan, interface; 1105 { 1106 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1107 struct channel_softc *wdc_cp = &cp->wdc_channel; 1108 1109 if (cp->hw_ok == 0) 1110 return; 1111 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1112 return; 1113 1114 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1115 pa, compatchan, pciide_compat_intr, cp); 1116 if (cp->ih == NULL) { 1117 printf("%s: no compatibility interrupt for use by %s " 1118 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1119 cp->hw_ok = 0; 1120 } 1121 } 1122 1123 void 1124 pciide_print_modes(cp) 1125 struct pciide_channel *cp; 1126 { 1127 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1128 int drive; 1129 struct channel_softc *chp; 1130 struct ata_drive_datas *drvp; 1131 1132 chp = &cp->wdc_channel; 1133 for (drive = 0; drive < 2; drive++) { 1134 drvp = &chp->ch_drive[drive]; 1135 if ((drvp->drive_flags & DRIVE) == 0) 1136 continue; 1137 printf("%s(%s:%d:%d): using PIO mode %d", 1138 drvp->drv_softc->dv_xname, 1139 sc->sc_wdcdev.sc_dev.dv_xname, 1140 chp->channel, drive, drvp->PIO_mode); 1141 if (drvp->drive_flags & DRIVE_DMA) 1142 printf(", DMA mode %d", drvp->DMA_mode); 1143 if (drvp->drive_flags & DRIVE_UDMA) 1144 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1145 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1146 printf(" (using DMA data transfers)"); 1147 printf("\n"); 1148 } 1149 } 1150 1151 void 1152 default_chip_map(sc, pa) 1153 struct pciide_softc *sc; 1154 struct pci_attach_args *pa; 1155 { 1156 struct pciide_channel *cp; 1157 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1158 pcireg_t csr; 1159 int channel, drive; 1160 struct ata_drive_datas *drvp; 1161 u_int8_t idedma_ctl; 1162 bus_size_t cmdsize, ctlsize; 1163 char *failreason; 1164 1165 if (pciide_chipen(sc, pa) == 0) 1166 return; 1167 1168 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1169 printf("%s: bus-master DMA support present", 1170 sc->sc_wdcdev.sc_dev.dv_xname); 1171 if (sc->sc_pp == &default_product_desc && 1172 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1173 PCIIDE_OPTIONS_DMA) == 0) { 1174 printf(", but unused (no driver support)"); 1175 sc->sc_dma_ok = 0; 1176 } else { 1177 pciide_mapreg_dma(sc, pa); 1178 if (sc->sc_dma_ok != 0) 1179 printf(", used without full driver " 1180 "support"); 1181 } 1182 } else { 1183 printf("%s: hardware does not support DMA", 1184 sc->sc_wdcdev.sc_dev.dv_xname); 1185 sc->sc_dma_ok = 0; 1186 } 1187 printf("\n"); 1188 if (sc->sc_dma_ok) { 1189 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1190 sc->sc_wdcdev.irqack = pciide_irqack; 1191 } 1192 sc->sc_wdcdev.PIO_cap = 0; 1193 sc->sc_wdcdev.DMA_cap = 0; 1194 1195 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1196 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1197 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1198 1199 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1200 cp = &sc->pciide_channels[channel]; 1201 if (pciide_chansetup(sc, channel, interface) == 0) 1202 continue; 1203 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1204 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1205 &ctlsize, pciide_pci_intr); 1206 } else { 1207 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1208 channel, &cmdsize, &ctlsize); 1209 } 1210 if (cp->hw_ok == 0) 1211 continue; 1212 /* 1213 * Check to see if something appears to be there. 1214 */ 1215 failreason = NULL; 1216 if (!wdcprobe(&cp->wdc_channel)) { 1217 failreason = "not responding; disabled or no drives?"; 1218 goto next; 1219 } 1220 /* 1221 * Now, make sure it's actually attributable to this PCI IDE 1222 * channel by trying to access the channel again while the 1223 * PCI IDE controller's I/O space is disabled. (If the 1224 * channel no longer appears to be there, it belongs to 1225 * this controller.) YUCK! 1226 */ 1227 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1228 PCI_COMMAND_STATUS_REG); 1229 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1230 csr & ~PCI_COMMAND_IO_ENABLE); 1231 if (wdcprobe(&cp->wdc_channel)) 1232 failreason = "other hardware responding at addresses"; 1233 pci_conf_write(sc->sc_pc, sc->sc_tag, 1234 PCI_COMMAND_STATUS_REG, csr); 1235 next: 1236 if (failreason) { 1237 printf("%s: %s channel ignored (%s)\n", 1238 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1239 failreason); 1240 cp->hw_ok = 0; 1241 bus_space_unmap(cp->wdc_channel.cmd_iot, 1242 cp->wdc_channel.cmd_ioh, cmdsize); 1243 bus_space_unmap(cp->wdc_channel.ctl_iot, 1244 cp->wdc_channel.ctl_ioh, ctlsize); 1245 } else { 1246 pciide_map_compat_intr(pa, cp, channel, interface); 1247 } 1248 if (cp->hw_ok) { 1249 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1250 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1251 wdcattach(&cp->wdc_channel); 1252 } 1253 } 1254 1255 if (sc->sc_dma_ok == 0) 1256 return; 1257 1258 /* Allocate DMA maps */ 1259 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1260 idedma_ctl = 0; 1261 cp = &sc->pciide_channels[channel]; 1262 for (drive = 0; drive < 2; drive++) { 1263 drvp = &cp->wdc_channel.ch_drive[drive]; 1264 /* If no drive, skip */ 1265 if ((drvp->drive_flags & DRIVE) == 0) 1266 continue; 1267 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1268 continue; 1269 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1270 /* Abort DMA setup */ 1271 printf("%s:%d:%d: can't allocate DMA maps, " 1272 "using PIO transfers\n", 1273 sc->sc_wdcdev.sc_dev.dv_xname, 1274 channel, drive); 1275 drvp->drive_flags &= ~DRIVE_DMA; 1276 } 1277 printf("%s:%d:%d: using DMA data transfers\n", 1278 sc->sc_wdcdev.sc_dev.dv_xname, 1279 channel, drive); 1280 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1281 } 1282 if (idedma_ctl != 0) { 1283 /* Add software bits in status register */ 1284 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1285 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1286 idedma_ctl); 1287 } 1288 } 1289 } 1290 1291 void 1292 piix_chip_map(sc, pa) 1293 struct pciide_softc *sc; 1294 struct pci_attach_args *pa; 1295 { 1296 struct pciide_channel *cp; 1297 int channel; 1298 u_int32_t idetim; 1299 bus_size_t cmdsize, ctlsize; 1300 1301 if (pciide_chipen(sc, pa) == 0) 1302 return; 1303 1304 printf("%s: bus-master DMA support present", 1305 sc->sc_wdcdev.sc_dev.dv_xname); 1306 pciide_mapreg_dma(sc, pa); 1307 printf("\n"); 1308 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1309 WDC_CAPABILITY_MODE; 1310 if (sc->sc_dma_ok) { 1311 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1312 sc->sc_wdcdev.irqack = pciide_irqack; 1313 switch(sc->sc_pp->ide_product) { 1314 case PCI_PRODUCT_INTEL_82371AB_IDE: 1315 case PCI_PRODUCT_INTEL_82801AA_IDE: 1316 case PCI_PRODUCT_INTEL_82801AB_IDE: 1317 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1318 } 1319 } 1320 sc->sc_wdcdev.PIO_cap = 4; 1321 sc->sc_wdcdev.DMA_cap = 2; 1322 sc->sc_wdcdev.UDMA_cap = 1323 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1324 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1325 sc->sc_wdcdev.set_modes = piix_setup_channel; 1326 else 1327 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1328 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1329 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1330 1331 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1332 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1333 DEBUG_PROBE); 1334 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1335 WDCDEBUG_PRINT((", sidetim=0x%x", 1336 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1337 DEBUG_PROBE); 1338 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1339 WDCDEBUG_PRINT((", udamreg 0x%x", 1340 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1341 DEBUG_PROBE); 1342 } 1343 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1344 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1345 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1346 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1347 DEBUG_PROBE); 1348 } 1349 1350 } 1351 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1352 1353 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1354 cp = &sc->pciide_channels[channel]; 1355 /* PIIX is compat-only */ 1356 if (pciide_chansetup(sc, channel, 0) == 0) 1357 continue; 1358 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1359 if ((PIIX_IDETIM_READ(idetim, channel) & 1360 PIIX_IDETIM_IDE) == 0) { 1361 printf("%s: %s channel ignored (disabled)\n", 1362 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1363 continue; 1364 } 1365 /* PIIX are compat-only pciide devices */ 1366 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1367 if (cp->hw_ok == 0) 1368 continue; 1369 if (pciide_chan_candisable(cp)) { 1370 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1371 channel); 1372 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1373 idetim); 1374 } 1375 pciide_map_compat_intr(pa, cp, channel, 0); 1376 if (cp->hw_ok == 0) 1377 continue; 1378 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1379 } 1380 1381 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1382 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1383 DEBUG_PROBE); 1384 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1385 WDCDEBUG_PRINT((", sidetim=0x%x", 1386 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1387 DEBUG_PROBE); 1388 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1389 WDCDEBUG_PRINT((", udamreg 0x%x", 1390 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1391 DEBUG_PROBE); 1392 } 1393 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1394 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1395 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1396 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1397 DEBUG_PROBE); 1398 } 1399 } 1400 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1401 } 1402 1403 void 1404 piix_setup_channel(chp) 1405 struct channel_softc *chp; 1406 { 1407 u_int8_t mode[2], drive; 1408 u_int32_t oidetim, idetim, idedma_ctl; 1409 struct pciide_channel *cp = (struct pciide_channel*)chp; 1410 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1411 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1412 1413 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1414 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1415 idedma_ctl = 0; 1416 1417 /* set up new idetim: Enable IDE registers decode */ 1418 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1419 chp->channel); 1420 1421 /* setup DMA */ 1422 pciide_channel_dma_setup(cp); 1423 1424 /* 1425 * Here we have to mess up with drives mode: PIIX can't have 1426 * different timings for master and slave drives. 1427 * We need to find the best combination. 1428 */ 1429 1430 /* If both drives supports DMA, take the lower mode */ 1431 if ((drvp[0].drive_flags & DRIVE_DMA) && 1432 (drvp[1].drive_flags & DRIVE_DMA)) { 1433 mode[0] = mode[1] = 1434 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1435 drvp[0].DMA_mode = mode[0]; 1436 drvp[1].DMA_mode = mode[1]; 1437 goto ok; 1438 } 1439 /* 1440 * If only one drive supports DMA, use its mode, and 1441 * put the other one in PIO mode 0 if mode not compatible 1442 */ 1443 if (drvp[0].drive_flags & DRIVE_DMA) { 1444 mode[0] = drvp[0].DMA_mode; 1445 mode[1] = drvp[1].PIO_mode; 1446 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1447 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1448 mode[1] = drvp[1].PIO_mode = 0; 1449 goto ok; 1450 } 1451 if (drvp[1].drive_flags & DRIVE_DMA) { 1452 mode[1] = drvp[1].DMA_mode; 1453 mode[0] = drvp[0].PIO_mode; 1454 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1455 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1456 mode[0] = drvp[0].PIO_mode = 0; 1457 goto ok; 1458 } 1459 /* 1460 * If both drives are not DMA, takes the lower mode, unless 1461 * one of them is PIO mode < 2 1462 */ 1463 if (drvp[0].PIO_mode < 2) { 1464 mode[0] = drvp[0].PIO_mode = 0; 1465 mode[1] = drvp[1].PIO_mode; 1466 } else if (drvp[1].PIO_mode < 2) { 1467 mode[1] = drvp[1].PIO_mode = 0; 1468 mode[0] = drvp[0].PIO_mode; 1469 } else { 1470 mode[0] = mode[1] = 1471 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1472 drvp[0].PIO_mode = mode[0]; 1473 drvp[1].PIO_mode = mode[1]; 1474 } 1475 ok: /* The modes are setup */ 1476 for (drive = 0; drive < 2; drive++) { 1477 if (drvp[drive].drive_flags & DRIVE_DMA) { 1478 idetim |= piix_setup_idetim_timings( 1479 mode[drive], 1, chp->channel); 1480 goto end; 1481 } 1482 } 1483 /* If we are there, none of the drives are DMA */ 1484 if (mode[0] >= 2) 1485 idetim |= piix_setup_idetim_timings( 1486 mode[0], 0, chp->channel); 1487 else 1488 idetim |= piix_setup_idetim_timings( 1489 mode[1], 0, chp->channel); 1490 end: /* 1491 * timing mode is now set up in the controller. Enable 1492 * it per-drive 1493 */ 1494 for (drive = 0; drive < 2; drive++) { 1495 /* If no drive, skip */ 1496 if ((drvp[drive].drive_flags & DRIVE) == 0) 1497 continue; 1498 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1499 if (drvp[drive].drive_flags & DRIVE_DMA) 1500 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1501 } 1502 if (idedma_ctl != 0) { 1503 /* Add software bits in status register */ 1504 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1505 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1506 idedma_ctl); 1507 } 1508 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1509 pciide_print_modes(cp); 1510 } 1511 1512 void 1513 piix3_4_setup_channel(chp) 1514 struct channel_softc *chp; 1515 { 1516 struct ata_drive_datas *drvp; 1517 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1518 struct pciide_channel *cp = (struct pciide_channel*)chp; 1519 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1520 int drive; 1521 int channel = chp->channel; 1522 1523 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1524 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1525 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1526 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1527 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1528 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1529 PIIX_SIDETIM_RTC_MASK(channel)); 1530 1531 idedma_ctl = 0; 1532 /* If channel disabled, no need to go further */ 1533 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1534 return; 1535 /* set up new idetim: Enable IDE registers decode */ 1536 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1537 1538 /* setup DMA if needed */ 1539 pciide_channel_dma_setup(cp); 1540 1541 for (drive = 0; drive < 2; drive++) { 1542 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1543 PIIX_UDMATIM_SET(0x3, channel, drive)); 1544 drvp = &chp->ch_drive[drive]; 1545 /* If no drive, skip */ 1546 if ((drvp->drive_flags & DRIVE) == 0) 1547 continue; 1548 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1549 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1550 goto pio; 1551 1552 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1553 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1554 ideconf |= PIIX_CONFIG_PINGPONG; 1555 } 1556 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1557 /* setup Ultra/66 */ 1558 if (drvp->UDMA_mode > 2 && 1559 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1560 drvp->UDMA_mode = 2; 1561 if (drvp->UDMA_mode > 2) 1562 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1563 else 1564 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1565 } 1566 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1567 (drvp->drive_flags & DRIVE_UDMA)) { 1568 /* use Ultra/DMA */ 1569 drvp->drive_flags &= ~DRIVE_DMA; 1570 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1571 udmareg |= PIIX_UDMATIM_SET( 1572 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1573 } else { 1574 /* use Multiword DMA */ 1575 drvp->drive_flags &= ~DRIVE_UDMA; 1576 if (drive == 0) { 1577 idetim |= piix_setup_idetim_timings( 1578 drvp->DMA_mode, 1, channel); 1579 } else { 1580 sidetim |= piix_setup_sidetim_timings( 1581 drvp->DMA_mode, 1, channel); 1582 idetim =PIIX_IDETIM_SET(idetim, 1583 PIIX_IDETIM_SITRE, channel); 1584 } 1585 } 1586 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1587 1588 pio: /* use PIO mode */ 1589 idetim |= piix_setup_idetim_drvs(drvp); 1590 if (drive == 0) { 1591 idetim |= piix_setup_idetim_timings( 1592 drvp->PIO_mode, 0, channel); 1593 } else { 1594 sidetim |= piix_setup_sidetim_timings( 1595 drvp->PIO_mode, 0, channel); 1596 idetim =PIIX_IDETIM_SET(idetim, 1597 PIIX_IDETIM_SITRE, channel); 1598 } 1599 } 1600 if (idedma_ctl != 0) { 1601 /* Add software bits in status register */ 1602 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1603 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1604 idedma_ctl); 1605 } 1606 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1607 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1608 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1609 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1610 pciide_print_modes(cp); 1611 } 1612 1613 1614 /* setup ISP and RTC fields, based on mode */ 1615 static u_int32_t 1616 piix_setup_idetim_timings(mode, dma, channel) 1617 u_int8_t mode; 1618 u_int8_t dma; 1619 u_int8_t channel; 1620 { 1621 1622 if (dma) 1623 return PIIX_IDETIM_SET(0, 1624 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1625 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1626 channel); 1627 else 1628 return PIIX_IDETIM_SET(0, 1629 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1630 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1631 channel); 1632 } 1633 1634 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1635 static u_int32_t 1636 piix_setup_idetim_drvs(drvp) 1637 struct ata_drive_datas *drvp; 1638 { 1639 u_int32_t ret = 0; 1640 struct channel_softc *chp = drvp->chnl_softc; 1641 u_int8_t channel = chp->channel; 1642 u_int8_t drive = drvp->drive; 1643 1644 /* 1645 * If drive is using UDMA, timings setups are independant 1646 * So just check DMA and PIO here. 1647 */ 1648 if (drvp->drive_flags & DRIVE_DMA) { 1649 /* if mode = DMA mode 0, use compatible timings */ 1650 if ((drvp->drive_flags & DRIVE_DMA) && 1651 drvp->DMA_mode == 0) { 1652 drvp->PIO_mode = 0; 1653 return ret; 1654 } 1655 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1656 /* 1657 * PIO and DMA timings are the same, use fast timings for PIO 1658 * too, else use compat timings. 1659 */ 1660 if ((piix_isp_pio[drvp->PIO_mode] != 1661 piix_isp_dma[drvp->DMA_mode]) || 1662 (piix_rtc_pio[drvp->PIO_mode] != 1663 piix_rtc_dma[drvp->DMA_mode])) 1664 drvp->PIO_mode = 0; 1665 /* if PIO mode <= 2, use compat timings for PIO */ 1666 if (drvp->PIO_mode <= 2) { 1667 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1668 channel); 1669 return ret; 1670 } 1671 } 1672 1673 /* 1674 * Now setup PIO modes. If mode < 2, use compat timings. 1675 * Else enable fast timings. Enable IORDY and prefetch/post 1676 * if PIO mode >= 3. 1677 */ 1678 1679 if (drvp->PIO_mode < 2) 1680 return ret; 1681 1682 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1683 if (drvp->PIO_mode >= 3) { 1684 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1685 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1686 } 1687 return ret; 1688 } 1689 1690 /* setup values in SIDETIM registers, based on mode */ 1691 static u_int32_t 1692 piix_setup_sidetim_timings(mode, dma, channel) 1693 u_int8_t mode; 1694 u_int8_t dma; 1695 u_int8_t channel; 1696 { 1697 if (dma) 1698 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1699 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1700 else 1701 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1702 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1703 } 1704 1705 void 1706 amd756_chip_map(sc, pa) 1707 struct pciide_softc *sc; 1708 struct pci_attach_args *pa; 1709 { 1710 struct pciide_channel *cp; 1711 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1712 int channel; 1713 pcireg_t chanenable; 1714 bus_size_t cmdsize, ctlsize; 1715 1716 if (pciide_chipen(sc, pa) == 0) 1717 return; 1718 printf("%s: bus-master DMA support present", 1719 sc->sc_wdcdev.sc_dev.dv_xname); 1720 pciide_mapreg_dma(sc, pa); 1721 printf("\n"); 1722 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1723 WDC_CAPABILITY_MODE; 1724 if (sc->sc_dma_ok) { 1725 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1726 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1727 sc->sc_wdcdev.irqack = pciide_irqack; 1728 } 1729 sc->sc_wdcdev.PIO_cap = 4; 1730 sc->sc_wdcdev.DMA_cap = 2; 1731 sc->sc_wdcdev.UDMA_cap = 4; 1732 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1733 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1734 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1735 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1736 1737 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1738 DEBUG_PROBE); 1739 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1740 cp = &sc->pciide_channels[channel]; 1741 if (pciide_chansetup(sc, channel, interface) == 0) 1742 continue; 1743 1744 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1745 printf("%s: %s channel ignored (disabled)\n", 1746 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1747 continue; 1748 } 1749 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1750 pciide_pci_intr); 1751 1752 if (pciide_chan_candisable(cp)) 1753 chanenable &= ~AMD756_CHAN_EN(channel); 1754 pciide_map_compat_intr(pa, cp, channel, interface); 1755 if (cp->hw_ok == 0) 1756 continue; 1757 1758 amd756_setup_channel(&cp->wdc_channel); 1759 } 1760 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1761 chanenable); 1762 return; 1763 } 1764 1765 void 1766 amd756_setup_channel(chp) 1767 struct channel_softc *chp; 1768 { 1769 u_int32_t udmatim_reg, datatim_reg; 1770 u_int8_t idedma_ctl; 1771 int mode, drive; 1772 struct ata_drive_datas *drvp; 1773 struct pciide_channel *cp = (struct pciide_channel*)chp; 1774 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1775 1776 idedma_ctl = 0; 1777 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1778 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1779 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1780 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1781 1782 /* setup DMA if needed */ 1783 pciide_channel_dma_setup(cp); 1784 1785 for (drive = 0; drive < 2; drive++) { 1786 drvp = &chp->ch_drive[drive]; 1787 /* If no drive, skip */ 1788 if ((drvp->drive_flags & DRIVE) == 0) 1789 continue; 1790 /* add timing values, setup DMA if needed */ 1791 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1792 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1793 mode = drvp->PIO_mode; 1794 goto pio; 1795 } 1796 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1797 (drvp->drive_flags & DRIVE_UDMA)) { 1798 /* use Ultra/DMA */ 1799 drvp->drive_flags &= ~DRIVE_DMA; 1800 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1801 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1802 AMD756_UDMA_TIME(chp->channel, drive, 1803 amd756_udma_tim[drvp->UDMA_mode]); 1804 /* can use PIO timings, MW DMA unused */ 1805 mode = drvp->PIO_mode; 1806 } else { 1807 /* use Multiword DMA */ 1808 drvp->drive_flags &= ~DRIVE_UDMA; 1809 /* mode = min(pio, dma+2) */ 1810 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1811 mode = drvp->PIO_mode; 1812 else 1813 mode = drvp->DMA_mode + 2; 1814 } 1815 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1816 1817 pio: /* setup PIO mode */ 1818 if (mode <= 2) { 1819 drvp->DMA_mode = 0; 1820 drvp->PIO_mode = 0; 1821 mode = 0; 1822 } else { 1823 drvp->PIO_mode = mode; 1824 drvp->DMA_mode = mode - 2; 1825 } 1826 datatim_reg |= 1827 AMD756_DATATIM_PULSE(chp->channel, drive, 1828 amd756_pio_set[mode]) | 1829 AMD756_DATATIM_RECOV(chp->channel, drive, 1830 amd756_pio_rec[mode]); 1831 } 1832 if (idedma_ctl != 0) { 1833 /* Add software bits in status register */ 1834 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1835 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1836 idedma_ctl); 1837 } 1838 pciide_print_modes(cp); 1839 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1840 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1841 } 1842 1843 void 1844 apollo_chip_map(sc, pa) 1845 struct pciide_softc *sc; 1846 struct pci_attach_args *pa; 1847 { 1848 struct pciide_channel *cp; 1849 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1850 int channel; 1851 u_int32_t ideconf; 1852 bus_size_t cmdsize, ctlsize; 1853 1854 if (pciide_chipen(sc, pa) == 0) 1855 return; 1856 printf("%s: bus-master DMA support present", 1857 sc->sc_wdcdev.sc_dev.dv_xname); 1858 pciide_mapreg_dma(sc, pa); 1859 printf("\n"); 1860 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1861 WDC_CAPABILITY_MODE; 1862 if (sc->sc_dma_ok) { 1863 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1864 sc->sc_wdcdev.irqack = pciide_irqack; 1865 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1866 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1867 } 1868 sc->sc_wdcdev.PIO_cap = 4; 1869 sc->sc_wdcdev.DMA_cap = 2; 1870 sc->sc_wdcdev.UDMA_cap = 2; 1871 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1872 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1873 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1874 1875 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1876 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1877 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1878 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1879 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1880 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1881 DEBUG_PROBE); 1882 1883 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1884 cp = &sc->pciide_channels[channel]; 1885 if (pciide_chansetup(sc, channel, interface) == 0) 1886 continue; 1887 1888 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1889 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1890 printf("%s: %s channel ignored (disabled)\n", 1891 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1892 continue; 1893 } 1894 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1895 pciide_pci_intr); 1896 if (cp->hw_ok == 0) 1897 continue; 1898 if (pciide_chan_candisable(cp)) { 1899 ideconf &= ~APO_IDECONF_EN(channel); 1900 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1901 ideconf); 1902 } 1903 pciide_map_compat_intr(pa, cp, channel, interface); 1904 1905 if (cp->hw_ok == 0) 1906 continue; 1907 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1908 } 1909 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1910 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1911 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1912 } 1913 1914 void 1915 apollo_setup_channel(chp) 1916 struct channel_softc *chp; 1917 { 1918 u_int32_t udmatim_reg, datatim_reg; 1919 u_int8_t idedma_ctl; 1920 int mode, drive; 1921 struct ata_drive_datas *drvp; 1922 struct pciide_channel *cp = (struct pciide_channel*)chp; 1923 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1924 1925 idedma_ctl = 0; 1926 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1927 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1928 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1929 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1930 1931 /* setup DMA if needed */ 1932 pciide_channel_dma_setup(cp); 1933 1934 for (drive = 0; drive < 2; drive++) { 1935 drvp = &chp->ch_drive[drive]; 1936 /* If no drive, skip */ 1937 if ((drvp->drive_flags & DRIVE) == 0) 1938 continue; 1939 /* add timing values, setup DMA if needed */ 1940 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1941 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1942 mode = drvp->PIO_mode; 1943 goto pio; 1944 } 1945 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1946 (drvp->drive_flags & DRIVE_UDMA)) { 1947 /* use Ultra/DMA */ 1948 drvp->drive_flags &= ~DRIVE_DMA; 1949 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1950 APO_UDMA_EN_MTH(chp->channel, drive) | 1951 APO_UDMA_TIME(chp->channel, drive, 1952 apollo_udma_tim[drvp->UDMA_mode]); 1953 /* can use PIO timings, MW DMA unused */ 1954 mode = drvp->PIO_mode; 1955 } else { 1956 /* use Multiword DMA */ 1957 drvp->drive_flags &= ~DRIVE_UDMA; 1958 /* mode = min(pio, dma+2) */ 1959 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1960 mode = drvp->PIO_mode; 1961 else 1962 mode = drvp->DMA_mode + 2; 1963 } 1964 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1965 1966 pio: /* setup PIO mode */ 1967 if (mode <= 2) { 1968 drvp->DMA_mode = 0; 1969 drvp->PIO_mode = 0; 1970 mode = 0; 1971 } else { 1972 drvp->PIO_mode = mode; 1973 drvp->DMA_mode = mode - 2; 1974 } 1975 datatim_reg |= 1976 APO_DATATIM_PULSE(chp->channel, drive, 1977 apollo_pio_set[mode]) | 1978 APO_DATATIM_RECOV(chp->channel, drive, 1979 apollo_pio_rec[mode]); 1980 } 1981 if (idedma_ctl != 0) { 1982 /* Add software bits in status register */ 1983 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1984 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1985 idedma_ctl); 1986 } 1987 pciide_print_modes(cp); 1988 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 1989 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 1990 } 1991 1992 void 1993 cmd_channel_map(pa, sc, channel) 1994 struct pci_attach_args *pa; 1995 struct pciide_softc *sc; 1996 int channel; 1997 { 1998 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1999 bus_size_t cmdsize, ctlsize; 2000 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2001 int interface; 2002 2003 /* 2004 * The 0648/0649 can be told to identify as a RAID controller. 2005 * In this case, we have to fake interface 2006 */ 2007 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2008 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2009 PCIIDE_INTERFACE_SETTABLE(1); 2010 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2011 CMD_CONF_DSA1) 2012 interface |= PCIIDE_INTERFACE_PCI(0) | 2013 PCIIDE_INTERFACE_PCI(1); 2014 } else { 2015 interface = PCI_INTERFACE(pa->pa_class); 2016 } 2017 2018 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2019 cp->name = PCIIDE_CHANNEL_NAME(channel); 2020 cp->wdc_channel.channel = channel; 2021 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2022 2023 if (channel > 0) { 2024 cp->wdc_channel.ch_queue = 2025 sc->pciide_channels[0].wdc_channel.ch_queue; 2026 } else { 2027 cp->wdc_channel.ch_queue = 2028 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2029 } 2030 if (cp->wdc_channel.ch_queue == NULL) { 2031 printf("%s %s channel: " 2032 "can't allocate memory for command queue", 2033 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2034 return; 2035 } 2036 2037 printf("%s: %s channel %s to %s mode\n", 2038 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2039 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2040 "configured" : "wired", 2041 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2042 "native-PCI" : "compatibility"); 2043 2044 /* 2045 * with a CMD PCI64x, if we get here, the first channel is enabled: 2046 * there's no way to disable the first channel without disabling 2047 * the whole device 2048 */ 2049 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2050 printf("%s: %s channel ignored (disabled)\n", 2051 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2052 return; 2053 } 2054 2055 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2056 if (cp->hw_ok == 0) 2057 return; 2058 if (channel == 1) { 2059 if (pciide_chan_candisable(cp)) { 2060 ctrl &= ~CMD_CTRL_2PORT; 2061 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2062 CMD_CTRL, ctrl); 2063 } 2064 } 2065 pciide_map_compat_intr(pa, cp, channel, interface); 2066 } 2067 2068 int 2069 cmd_pci_intr(arg) 2070 void *arg; 2071 { 2072 struct pciide_softc *sc = arg; 2073 struct pciide_channel *cp; 2074 struct channel_softc *wdc_cp; 2075 int i, rv, crv; 2076 u_int32_t priirq, secirq; 2077 2078 rv = 0; 2079 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2080 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2081 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2082 cp = &sc->pciide_channels[i]; 2083 wdc_cp = &cp->wdc_channel; 2084 /* If a compat channel skip. */ 2085 if (cp->compat) 2086 continue; 2087 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2088 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2089 crv = wdcintr(wdc_cp); 2090 if (crv == 0) 2091 printf("%s:%d: bogus intr\n", 2092 sc->sc_wdcdev.sc_dev.dv_xname, i); 2093 else 2094 rv = 1; 2095 } 2096 } 2097 return rv; 2098 } 2099 2100 void 2101 cmd_chip_map(sc, pa) 2102 struct pciide_softc *sc; 2103 struct pci_attach_args *pa; 2104 { 2105 int channel; 2106 2107 /* 2108 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2109 * and base adresses registers can be disabled at 2110 * hardware level. In this case, the device is wired 2111 * in compat mode and its first channel is always enabled, 2112 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2113 * In fact, it seems that the first channel of the CMD PCI0640 2114 * can't be disabled. 2115 */ 2116 2117 #ifdef PCIIDE_CMD064x_DISABLE 2118 if (pciide_chipen(sc, pa) == 0) 2119 return; 2120 #endif 2121 2122 printf("%s: hardware does not support DMA\n", 2123 sc->sc_wdcdev.sc_dev.dv_xname); 2124 sc->sc_dma_ok = 0; 2125 2126 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2127 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2128 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2129 2130 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2131 cmd_channel_map(pa, sc, channel); 2132 } 2133 } 2134 2135 void 2136 cmd0643_9_chip_map(sc, pa) 2137 struct pciide_softc *sc; 2138 struct pci_attach_args *pa; 2139 { 2140 struct pciide_channel *cp; 2141 int channel; 2142 2143 /* 2144 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2145 * and base adresses registers can be disabled at 2146 * hardware level. In this case, the device is wired 2147 * in compat mode and its first channel is always enabled, 2148 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2149 * In fact, it seems that the first channel of the CMD PCI0640 2150 * can't be disabled. 2151 */ 2152 2153 #ifdef PCIIDE_CMD064x_DISABLE 2154 if (pciide_chipen(sc, pa) == 0) 2155 return; 2156 #endif 2157 printf("%s: bus-master DMA support present", 2158 sc->sc_wdcdev.sc_dev.dv_xname); 2159 pciide_mapreg_dma(sc, pa); 2160 printf("\n"); 2161 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2162 WDC_CAPABILITY_MODE; 2163 if (sc->sc_dma_ok) { 2164 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2165 switch (sc->sc_pp->ide_product) { 2166 case PCI_PRODUCT_CMDTECH_649: 2167 case PCI_PRODUCT_CMDTECH_648: 2168 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2169 sc->sc_wdcdev.UDMA_cap = 4; 2170 sc->sc_wdcdev.irqack = cmd648_9_irqack; 2171 break; 2172 default: 2173 sc->sc_wdcdev.irqack = pciide_irqack; 2174 } 2175 } 2176 2177 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2178 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2179 sc->sc_wdcdev.PIO_cap = 4; 2180 sc->sc_wdcdev.DMA_cap = 2; 2181 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2182 2183 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2184 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2185 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2186 DEBUG_PROBE); 2187 2188 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2189 cp = &sc->pciide_channels[channel]; 2190 cmd_channel_map(pa, sc, channel); 2191 if (cp->hw_ok == 0) 2192 continue; 2193 cmd0643_9_setup_channel(&cp->wdc_channel); 2194 } 2195 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2196 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2197 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2198 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2199 DEBUG_PROBE); 2200 } 2201 2202 void 2203 cmd0643_9_setup_channel(chp) 2204 struct channel_softc *chp; 2205 { 2206 struct ata_drive_datas *drvp; 2207 u_int8_t tim; 2208 u_int32_t idedma_ctl, udma_reg; 2209 int drive; 2210 struct pciide_channel *cp = (struct pciide_channel*)chp; 2211 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2212 2213 idedma_ctl = 0; 2214 /* setup DMA if needed */ 2215 pciide_channel_dma_setup(cp); 2216 2217 for (drive = 0; drive < 2; drive++) { 2218 drvp = &chp->ch_drive[drive]; 2219 /* If no drive, skip */ 2220 if ((drvp->drive_flags & DRIVE) == 0) 2221 continue; 2222 /* add timing values, setup DMA if needed */ 2223 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2224 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2225 if (drvp->drive_flags & DRIVE_UDMA) { 2226 /* UltraDMA on a 0648 or 0649 */ 2227 udma_reg = pciide_pci_read(sc->sc_pc, 2228 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2229 if (drvp->UDMA_mode > 2 && 2230 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2231 CMD_BICSR) & 2232 CMD_BICSR_80(chp->channel)) == 0) 2233 drvp->UDMA_mode = 2; 2234 if (drvp->UDMA_mode > 2) 2235 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2236 else 2237 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2238 udma_reg |= CMD_UDMATIM_UDMA(drive); 2239 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2240 CMD_UDMATIM_TIM_OFF(drive)); 2241 udma_reg |= 2242 (cmd0648_9_tim_udma[drvp->UDMA_mode] << 2243 CMD_UDMATIM_TIM_OFF(drive)); 2244 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2245 CMD_UDMATIM(chp->channel), udma_reg); 2246 } else { 2247 /* 2248 * use Multiword DMA. 2249 * Timings will be used for both PIO and DMA, 2250 * so adjust DMA mode if needed 2251 * if we have a 0648/9, turn off UDMA 2252 */ 2253 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2254 udma_reg = pciide_pci_read(sc->sc_pc, 2255 sc->sc_tag, 2256 CMD_UDMATIM(chp->channel)); 2257 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2258 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2259 CMD_UDMATIM(chp->channel), 2260 udma_reg); 2261 } 2262 if (drvp->PIO_mode >= 3 && 2263 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2264 drvp->DMA_mode = drvp->PIO_mode - 2; 2265 } 2266 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2267 } 2268 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2269 } 2270 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2271 CMD_DATA_TIM(chp->channel, drive), tim); 2272 } 2273 if (idedma_ctl != 0) { 2274 /* Add software bits in status register */ 2275 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2276 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2277 idedma_ctl); 2278 } 2279 pciide_print_modes(cp); 2280 } 2281 2282 void 2283 cmd648_9_irqack(chp) 2284 struct channel_softc *chp; 2285 { 2286 u_int32_t priirq, secirq; 2287 struct pciide_channel *cp = (struct pciide_channel*)chp; 2288 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2289 2290 if (chp->channel == 0) { 2291 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2292 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2293 } else { 2294 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2295 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2296 } 2297 pciide_irqack(chp); 2298 } 2299 2300 void 2301 cy693_chip_map(sc, pa) 2302 struct pciide_softc *sc; 2303 struct pci_attach_args *pa; 2304 { 2305 struct pciide_channel *cp; 2306 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2307 bus_size_t cmdsize, ctlsize; 2308 2309 if (pciide_chipen(sc, pa) == 0) 2310 return; 2311 /* 2312 * this chip has 2 PCI IDE functions, one for primary and one for 2313 * secondary. So we need to call pciide_mapregs_compat() with 2314 * the real channel 2315 */ 2316 if (pa->pa_function == 1) { 2317 sc->sc_cy_compatchan = 0; 2318 } else if (pa->pa_function == 2) { 2319 sc->sc_cy_compatchan = 1; 2320 } else { 2321 printf("%s: unexpected PCI function %d\n", 2322 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2323 return; 2324 } 2325 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2326 printf("%s: bus-master DMA support present", 2327 sc->sc_wdcdev.sc_dev.dv_xname); 2328 pciide_mapreg_dma(sc, pa); 2329 } else { 2330 printf("%s: hardware does not support DMA", 2331 sc->sc_wdcdev.sc_dev.dv_xname); 2332 sc->sc_dma_ok = 0; 2333 } 2334 printf("\n"); 2335 2336 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2337 if (sc->sc_cy_handle == NULL) { 2338 printf("%s: unable to map hyperCache control registers\n", 2339 sc->sc_wdcdev.sc_dev.dv_xname); 2340 sc->sc_dma_ok = 0; 2341 } 2342 2343 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2344 WDC_CAPABILITY_MODE; 2345 if (sc->sc_dma_ok) { 2346 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2347 sc->sc_wdcdev.irqack = pciide_irqack; 2348 } 2349 sc->sc_wdcdev.PIO_cap = 4; 2350 sc->sc_wdcdev.DMA_cap = 2; 2351 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2352 2353 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2354 sc->sc_wdcdev.nchannels = 1; 2355 2356 /* Only one channel for this chip; if we are here it's enabled */ 2357 cp = &sc->pciide_channels[0]; 2358 sc->wdc_chanarray[0] = &cp->wdc_channel; 2359 cp->name = PCIIDE_CHANNEL_NAME(0); 2360 cp->wdc_channel.channel = 0; 2361 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2362 cp->wdc_channel.ch_queue = 2363 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2364 if (cp->wdc_channel.ch_queue == NULL) { 2365 printf("%s primary channel: " 2366 "can't allocate memory for command queue", 2367 sc->sc_wdcdev.sc_dev.dv_xname); 2368 return; 2369 } 2370 printf("%s: primary channel %s to ", 2371 sc->sc_wdcdev.sc_dev.dv_xname, 2372 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2373 "configured" : "wired"); 2374 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2375 printf("native-PCI"); 2376 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2377 pciide_pci_intr); 2378 } else { 2379 printf("compatibility"); 2380 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2381 &cmdsize, &ctlsize); 2382 } 2383 printf(" mode\n"); 2384 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2385 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2386 wdcattach(&cp->wdc_channel); 2387 if (pciide_chan_candisable(cp)) { 2388 pci_conf_write(sc->sc_pc, sc->sc_tag, 2389 PCI_COMMAND_STATUS_REG, 0); 2390 } 2391 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2392 if (cp->hw_ok == 0) 2393 return; 2394 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2395 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2396 cy693_setup_channel(&cp->wdc_channel); 2397 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2398 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2399 } 2400 2401 void 2402 cy693_setup_channel(chp) 2403 struct channel_softc *chp; 2404 { 2405 struct ata_drive_datas *drvp; 2406 int drive; 2407 u_int32_t cy_cmd_ctrl; 2408 u_int32_t idedma_ctl; 2409 struct pciide_channel *cp = (struct pciide_channel*)chp; 2410 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2411 int dma_mode = -1; 2412 2413 cy_cmd_ctrl = idedma_ctl = 0; 2414 2415 /* setup DMA if needed */ 2416 pciide_channel_dma_setup(cp); 2417 2418 for (drive = 0; drive < 2; drive++) { 2419 drvp = &chp->ch_drive[drive]; 2420 /* If no drive, skip */ 2421 if ((drvp->drive_flags & DRIVE) == 0) 2422 continue; 2423 /* add timing values, setup DMA if needed */ 2424 if (drvp->drive_flags & DRIVE_DMA) { 2425 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2426 /* use Multiword DMA */ 2427 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2428 dma_mode = drvp->DMA_mode; 2429 } 2430 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2431 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2432 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2433 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2434 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2435 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2436 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2437 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2438 } 2439 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2440 chp->ch_drive[0].DMA_mode = dma_mode; 2441 chp->ch_drive[1].DMA_mode = dma_mode; 2442 2443 if (dma_mode == -1) 2444 dma_mode = 0; 2445 2446 if (sc->sc_cy_handle != NULL) { 2447 /* Note: `multiple' is implied. */ 2448 cy82c693_write(sc->sc_cy_handle, 2449 (sc->sc_cy_compatchan == 0) ? 2450 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2451 } 2452 2453 pciide_print_modes(cp); 2454 2455 if (idedma_ctl != 0) { 2456 /* Add software bits in status register */ 2457 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2458 IDEDMA_CTL, idedma_ctl); 2459 } 2460 } 2461 2462 void 2463 sis_chip_map(sc, pa) 2464 struct pciide_softc *sc; 2465 struct pci_attach_args *pa; 2466 { 2467 struct pciide_channel *cp; 2468 int channel; 2469 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2470 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2471 pcireg_t rev = PCI_REVISION(pa->pa_class); 2472 bus_size_t cmdsize, ctlsize; 2473 2474 if (pciide_chipen(sc, pa) == 0) 2475 return; 2476 printf("%s: bus-master DMA support present", 2477 sc->sc_wdcdev.sc_dev.dv_xname); 2478 pciide_mapreg_dma(sc, pa); 2479 printf("\n"); 2480 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2481 WDC_CAPABILITY_MODE; 2482 if (sc->sc_dma_ok) { 2483 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2484 sc->sc_wdcdev.irqack = pciide_irqack; 2485 if (rev >= 0xd0) 2486 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2487 } 2488 2489 sc->sc_wdcdev.PIO_cap = 4; 2490 sc->sc_wdcdev.DMA_cap = 2; 2491 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2492 sc->sc_wdcdev.UDMA_cap = 2; 2493 sc->sc_wdcdev.set_modes = sis_setup_channel; 2494 2495 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2496 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2497 2498 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2499 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2500 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2501 2502 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2503 cp = &sc->pciide_channels[channel]; 2504 if (pciide_chansetup(sc, channel, interface) == 0) 2505 continue; 2506 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2507 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2508 printf("%s: %s channel ignored (disabled)\n", 2509 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2510 continue; 2511 } 2512 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2513 pciide_pci_intr); 2514 if (cp->hw_ok == 0) 2515 continue; 2516 if (pciide_chan_candisable(cp)) { 2517 if (channel == 0) 2518 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2519 else 2520 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2521 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2522 sis_ctr0); 2523 } 2524 pciide_map_compat_intr(pa, cp, channel, interface); 2525 if (cp->hw_ok == 0) 2526 continue; 2527 sis_setup_channel(&cp->wdc_channel); 2528 } 2529 } 2530 2531 void 2532 sis_setup_channel(chp) 2533 struct channel_softc *chp; 2534 { 2535 struct ata_drive_datas *drvp; 2536 int drive; 2537 u_int32_t sis_tim; 2538 u_int32_t idedma_ctl; 2539 struct pciide_channel *cp = (struct pciide_channel*)chp; 2540 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2541 2542 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2543 "channel %d 0x%x\n", chp->channel, 2544 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2545 DEBUG_PROBE); 2546 sis_tim = 0; 2547 idedma_ctl = 0; 2548 /* setup DMA if needed */ 2549 pciide_channel_dma_setup(cp); 2550 2551 for (drive = 0; drive < 2; drive++) { 2552 drvp = &chp->ch_drive[drive]; 2553 /* If no drive, skip */ 2554 if ((drvp->drive_flags & DRIVE) == 0) 2555 continue; 2556 /* add timing values, setup DMA if needed */ 2557 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2558 (drvp->drive_flags & DRIVE_UDMA) == 0) 2559 goto pio; 2560 2561 if (drvp->drive_flags & DRIVE_UDMA) { 2562 /* use Ultra/DMA */ 2563 drvp->drive_flags &= ~DRIVE_DMA; 2564 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2565 SIS_TIM_UDMA_TIME_OFF(drive); 2566 sis_tim |= SIS_TIM_UDMA_EN(drive); 2567 } else { 2568 /* 2569 * use Multiword DMA 2570 * Timings will be used for both PIO and DMA, 2571 * so adjust DMA mode if needed 2572 */ 2573 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2574 drvp->PIO_mode = drvp->DMA_mode + 2; 2575 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2576 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2577 drvp->PIO_mode - 2 : 0; 2578 if (drvp->DMA_mode == 0) 2579 drvp->PIO_mode = 0; 2580 } 2581 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2582 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2583 SIS_TIM_ACT_OFF(drive); 2584 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2585 SIS_TIM_REC_OFF(drive); 2586 } 2587 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2588 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2589 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2590 if (idedma_ctl != 0) { 2591 /* Add software bits in status register */ 2592 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2593 IDEDMA_CTL, idedma_ctl); 2594 } 2595 pciide_print_modes(cp); 2596 } 2597 2598 void 2599 acer_chip_map(sc, pa) 2600 struct pciide_softc *sc; 2601 struct pci_attach_args *pa; 2602 { 2603 struct pciide_channel *cp; 2604 int channel; 2605 pcireg_t cr, interface; 2606 bus_size_t cmdsize, ctlsize; 2607 2608 if (pciide_chipen(sc, pa) == 0) 2609 return; 2610 printf("%s: bus-master DMA support present", 2611 sc->sc_wdcdev.sc_dev.dv_xname); 2612 pciide_mapreg_dma(sc, pa); 2613 printf("\n"); 2614 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2615 WDC_CAPABILITY_MODE; 2616 if (sc->sc_dma_ok) { 2617 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2618 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2619 sc->sc_wdcdev.irqack = pciide_irqack; 2620 } 2621 2622 sc->sc_wdcdev.PIO_cap = 4; 2623 sc->sc_wdcdev.DMA_cap = 2; 2624 sc->sc_wdcdev.UDMA_cap = 2; 2625 sc->sc_wdcdev.set_modes = acer_setup_channel; 2626 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2627 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2628 2629 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2630 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2631 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2632 2633 /* Enable "microsoft register bits" R/W. */ 2634 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2635 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2636 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2637 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2638 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2639 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2640 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2641 ~ACER_CHANSTATUSREGS_RO); 2642 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2643 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2644 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2645 /* Don't use cr, re-read the real register content instead */ 2646 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2647 PCI_CLASS_REG)); 2648 2649 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2650 cp = &sc->pciide_channels[channel]; 2651 if (pciide_chansetup(sc, channel, interface) == 0) 2652 continue; 2653 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2654 printf("%s: %s channel ignored (disabled)\n", 2655 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2656 continue; 2657 } 2658 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2659 acer_pci_intr); 2660 if (cp->hw_ok == 0) 2661 continue; 2662 if (pciide_chan_candisable(cp)) { 2663 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2664 pci_conf_write(sc->sc_pc, sc->sc_tag, 2665 PCI_CLASS_REG, cr); 2666 } 2667 pciide_map_compat_intr(pa, cp, channel, interface); 2668 acer_setup_channel(&cp->wdc_channel); 2669 } 2670 } 2671 2672 void 2673 acer_setup_channel(chp) 2674 struct channel_softc *chp; 2675 { 2676 struct ata_drive_datas *drvp; 2677 int drive; 2678 u_int32_t acer_fifo_udma; 2679 u_int32_t idedma_ctl; 2680 struct pciide_channel *cp = (struct pciide_channel*)chp; 2681 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2682 2683 idedma_ctl = 0; 2684 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2685 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2686 acer_fifo_udma), DEBUG_PROBE); 2687 /* setup DMA if needed */ 2688 pciide_channel_dma_setup(cp); 2689 2690 for (drive = 0; drive < 2; drive++) { 2691 drvp = &chp->ch_drive[drive]; 2692 /* If no drive, skip */ 2693 if ((drvp->drive_flags & DRIVE) == 0) 2694 continue; 2695 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2696 "channel %d drive %d 0x%x\n", chp->channel, drive, 2697 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2698 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2699 /* clear FIFO/DMA mode */ 2700 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2701 ACER_UDMA_EN(chp->channel, drive) | 2702 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2703 2704 /* add timing values, setup DMA if needed */ 2705 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2706 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2707 acer_fifo_udma |= 2708 ACER_FTH_OPL(chp->channel, drive, 0x1); 2709 goto pio; 2710 } 2711 2712 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2713 if (drvp->drive_flags & DRIVE_UDMA) { 2714 /* use Ultra/DMA */ 2715 drvp->drive_flags &= ~DRIVE_DMA; 2716 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2717 acer_fifo_udma |= 2718 ACER_UDMA_TIM(chp->channel, drive, 2719 acer_udma[drvp->UDMA_mode]); 2720 } else { 2721 /* 2722 * use Multiword DMA 2723 * Timings will be used for both PIO and DMA, 2724 * so adjust DMA mode if needed 2725 */ 2726 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2727 drvp->PIO_mode = drvp->DMA_mode + 2; 2728 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2729 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2730 drvp->PIO_mode - 2 : 0; 2731 if (drvp->DMA_mode == 0) 2732 drvp->PIO_mode = 0; 2733 } 2734 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2735 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2736 ACER_IDETIM(chp->channel, drive), 2737 acer_pio[drvp->PIO_mode]); 2738 } 2739 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2740 acer_fifo_udma), DEBUG_PROBE); 2741 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2742 if (idedma_ctl != 0) { 2743 /* Add software bits in status register */ 2744 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2745 IDEDMA_CTL, idedma_ctl); 2746 } 2747 pciide_print_modes(cp); 2748 } 2749 2750 int 2751 acer_pci_intr(arg) 2752 void *arg; 2753 { 2754 struct pciide_softc *sc = arg; 2755 struct pciide_channel *cp; 2756 struct channel_softc *wdc_cp; 2757 int i, rv, crv; 2758 u_int32_t chids; 2759 2760 rv = 0; 2761 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2762 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2763 cp = &sc->pciide_channels[i]; 2764 wdc_cp = &cp->wdc_channel; 2765 /* If a compat channel skip. */ 2766 if (cp->compat) 2767 continue; 2768 if (chids & ACER_CHIDS_INT(i)) { 2769 crv = wdcintr(wdc_cp); 2770 if (crv == 0) 2771 printf("%s:%d: bogus intr\n", 2772 sc->sc_wdcdev.sc_dev.dv_xname, i); 2773 else 2774 rv = 1; 2775 } 2776 } 2777 return rv; 2778 } 2779 2780 void 2781 hpt_chip_map(sc, pa) 2782 struct pciide_softc *sc; 2783 struct pci_attach_args *pa; 2784 { 2785 struct pciide_channel *cp; 2786 int i, compatchan, revision; 2787 pcireg_t interface; 2788 bus_size_t cmdsize, ctlsize; 2789 2790 if (pciide_chipen(sc, pa) == 0) 2791 return; 2792 revision = PCI_REVISION(pa->pa_class); 2793 2794 /* 2795 * when the chip is in native mode it identifies itself as a 2796 * 'misc mass storage'. Fake interface in this case. 2797 */ 2798 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2799 interface = PCI_INTERFACE(pa->pa_class); 2800 } else { 2801 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2802 PCIIDE_INTERFACE_PCI(0); 2803 if (revision == HPT370_REV) 2804 interface |= PCIIDE_INTERFACE_PCI(1); 2805 } 2806 2807 printf("%s: bus-master DMA support present", 2808 sc->sc_wdcdev.sc_dev.dv_xname); 2809 pciide_mapreg_dma(sc, pa); 2810 printf("\n"); 2811 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2812 WDC_CAPABILITY_MODE; 2813 if (sc->sc_dma_ok) { 2814 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2815 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2816 sc->sc_wdcdev.irqack = pciide_irqack; 2817 } 2818 sc->sc_wdcdev.PIO_cap = 4; 2819 sc->sc_wdcdev.DMA_cap = 2; 2820 sc->sc_wdcdev.UDMA_cap = 4; 2821 2822 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2823 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2824 sc->sc_wdcdev.nchannels = (revision == HPT366_REV) ? 1 : 2; 2825 if (revision == HPT366_REV) { 2826 /* 2827 * The 366 has 2 PCI IDE functions, one for primary and one 2828 * for secondary. So we need to call pciide_mapregs_compat() 2829 * with the real channel 2830 */ 2831 if (pa->pa_function == 0) { 2832 compatchan = 0; 2833 } else if (pa->pa_function == 1) { 2834 compatchan = 1; 2835 } else { 2836 printf("%s: unexpected PCI function %d\n", 2837 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2838 return; 2839 } 2840 sc->sc_wdcdev.nchannels = 1; 2841 } else { 2842 sc->sc_wdcdev.nchannels = 2; 2843 } 2844 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2845 cp = &sc->pciide_channels[0]; 2846 if (sc->sc_wdcdev.nchannels > 1) { 2847 compatchan = i; 2848 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2849 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2850 printf("%s: %s channel ignored (disabled)\n", 2851 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2852 continue; 2853 } 2854 } 2855 if (pciide_chansetup(sc, i, interface) == 0) 2856 continue; 2857 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2858 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2859 &ctlsize, hpt_pci_intr); 2860 } else { 2861 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2862 &cmdsize, &ctlsize); 2863 } 2864 if (cp->hw_ok == 0) 2865 return; 2866 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2867 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2868 wdcattach(&cp->wdc_channel); 2869 hpt_setup_channel(&cp->wdc_channel); 2870 } 2871 2872 return; 2873 } 2874 2875 2876 void 2877 hpt_setup_channel(chp) 2878 struct channel_softc *chp; 2879 { 2880 struct ata_drive_datas *drvp; 2881 int drive; 2882 int cable; 2883 u_int32_t before, after; 2884 u_int32_t idedma_ctl; 2885 struct pciide_channel *cp = (struct pciide_channel*)chp; 2886 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2887 2888 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 2889 2890 /* setup DMA if needed */ 2891 pciide_channel_dma_setup(cp); 2892 2893 idedma_ctl = 0; 2894 2895 /* Per drive settings */ 2896 for (drive = 0; drive < 2; drive++) { 2897 drvp = &chp->ch_drive[drive]; 2898 /* If no drive, skip */ 2899 if ((drvp->drive_flags & DRIVE) == 0) 2900 continue; 2901 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 2902 HPT_IDETIM(chp->channel, drive)); 2903 2904 /* add timing values, setup DMA if needed */ 2905 if (drvp->drive_flags & DRIVE_UDMA) { 2906 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 2907 drvp->UDMA_mode > 2) 2908 drvp->UDMA_mode = 2; 2909 after = (sc->sc_wdcdev.nchannels == 2) ? 2910 hpt370_udma[drvp->UDMA_mode] : 2911 hpt366_udma[drvp->UDMA_mode]; 2912 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2913 } else if (drvp->drive_flags & DRIVE_DMA) { 2914 /* 2915 * use Multiword DMA. 2916 * Timings will be used for both PIO and DMA, so adjust 2917 * DMA mode if needed 2918 */ 2919 if (drvp->PIO_mode >= 3 && 2920 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2921 drvp->DMA_mode = drvp->PIO_mode - 2; 2922 } 2923 after = (sc->sc_wdcdev.nchannels == 2) ? 2924 hpt370_dma[drvp->DMA_mode] : 2925 hpt366_dma[drvp->DMA_mode]; 2926 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2927 } else { 2928 /* PIO only */ 2929 after = (sc->sc_wdcdev.nchannels == 2) ? 2930 hpt370_pio[drvp->PIO_mode] : 2931 hpt366_pio[drvp->PIO_mode]; 2932 } 2933 pci_conf_write(sc->sc_pc, sc->sc_tag, 2934 HPT_IDETIM(chp->channel, drive), after); 2935 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 2936 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 2937 after, before), DEBUG_PROBE); 2938 } 2939 if (idedma_ctl != 0) { 2940 /* Add software bits in status register */ 2941 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2942 IDEDMA_CTL, idedma_ctl); 2943 } 2944 pciide_print_modes(cp); 2945 } 2946 2947 int 2948 hpt_pci_intr(arg) 2949 void *arg; 2950 { 2951 struct pciide_softc *sc = arg; 2952 struct pciide_channel *cp; 2953 struct channel_softc *wdc_cp; 2954 int rv = 0; 2955 int dmastat, i, crv; 2956 2957 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2958 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2959 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 2960 if((dmastat & IDEDMA_CTL_INTR) == 0) 2961 continue; 2962 cp = &sc->pciide_channels[i]; 2963 wdc_cp = &cp->wdc_channel; 2964 crv = wdcintr(wdc_cp); 2965 if (crv == 0) { 2966 printf("%s:%d: bogus intr\n", 2967 sc->sc_wdcdev.sc_dev.dv_xname, i); 2968 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2969 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 2970 } else 2971 rv = 1; 2972 } 2973 return rv; 2974 } 2975 2976 2977 /* A macro to test product */ 2978 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 2979 2980 void 2981 pdc202xx_chip_map(sc, pa) 2982 struct pciide_softc *sc; 2983 struct pci_attach_args *pa; 2984 { 2985 struct pciide_channel *cp; 2986 int channel; 2987 pcireg_t interface, st, mode; 2988 bus_size_t cmdsize, ctlsize; 2989 2990 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2991 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 2992 DEBUG_PROBE); 2993 if (pciide_chipen(sc, pa) == 0) 2994 return; 2995 2996 /* turn off RAID mode */ 2997 st &= ~PDC2xx_STATE_IDERAID; 2998 2999 /* 3000 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3001 * mode. We have to fake interface 3002 */ 3003 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3004 if (st & PDC2xx_STATE_NATIVE) 3005 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3006 3007 printf("%s: bus-master DMA support present", 3008 sc->sc_wdcdev.sc_dev.dv_xname); 3009 pciide_mapreg_dma(sc, pa); 3010 printf("\n"); 3011 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3012 WDC_CAPABILITY_MODE; 3013 if (sc->sc_dma_ok) { 3014 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3015 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3016 sc->sc_wdcdev.irqack = pciide_irqack; 3017 } 3018 sc->sc_wdcdev.PIO_cap = 4; 3019 sc->sc_wdcdev.DMA_cap = 2; 3020 if (PDC_IS_262(sc)) 3021 sc->sc_wdcdev.UDMA_cap = 4; 3022 else 3023 sc->sc_wdcdev.UDMA_cap = 2; 3024 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3025 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3026 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3027 3028 /* setup failsafe defaults */ 3029 mode = 0; 3030 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3031 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3032 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3033 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3034 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3035 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3036 "initial timings 0x%x, now 0x%x\n", channel, 3037 pci_conf_read(sc->sc_pc, sc->sc_tag, 3038 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3039 DEBUG_PROBE); 3040 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3041 mode | PDC2xx_TIM_IORDYp); 3042 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3043 "initial timings 0x%x, now 0x%x\n", channel, 3044 pci_conf_read(sc->sc_pc, sc->sc_tag, 3045 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3046 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3047 mode); 3048 } 3049 3050 mode = PDC2xx_SCR_DMA; 3051 if (PDC_IS_262(sc)) { 3052 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3053 } else { 3054 /* the BIOS set it up this way */ 3055 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3056 } 3057 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3058 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3059 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3060 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3061 DEBUG_PROBE); 3062 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3063 3064 /* controller initial state register is OK even without BIOS */ 3065 /* Set DMA mode to IDE DMA compatibility */ 3066 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3067 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3068 DEBUG_PROBE); 3069 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3070 mode | 0x1); 3071 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3072 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3073 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3074 mode | 0x1); 3075 3076 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3077 cp = &sc->pciide_channels[channel]; 3078 if (pciide_chansetup(sc, channel, interface) == 0) 3079 continue; 3080 if ((st & (PDC_IS_262(sc) ? 3081 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3082 printf("%s: %s channel ignored (disabled)\n", 3083 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3084 continue; 3085 } 3086 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3087 pdc202xx_pci_intr); 3088 if (cp->hw_ok == 0) 3089 continue; 3090 if (pciide_chan_candisable(cp)) 3091 st &= ~(PDC_IS_262(sc) ? 3092 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3093 pciide_map_compat_intr(pa, cp, channel, interface); 3094 pdc202xx_setup_channel(&cp->wdc_channel); 3095 } 3096 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3097 DEBUG_PROBE); 3098 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3099 return; 3100 } 3101 3102 void 3103 pdc202xx_setup_channel(chp) 3104 struct channel_softc *chp; 3105 { 3106 struct ata_drive_datas *drvp; 3107 int drive; 3108 pcireg_t mode, st; 3109 u_int32_t idedma_ctl, scr, atapi; 3110 struct pciide_channel *cp = (struct pciide_channel*)chp; 3111 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3112 int channel = chp->channel; 3113 3114 /* setup DMA if needed */ 3115 pciide_channel_dma_setup(cp); 3116 3117 idedma_ctl = 0; 3118 3119 /* Per channel settings */ 3120 if (PDC_IS_262(sc)) { 3121 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3122 PDC262_U66); 3123 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3124 /* Trimm UDMA mode */ 3125 if ((st & PDC262_STATE_80P(channel)) != 0 || 3126 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3127 chp->ch_drive[0].UDMA_mode <= 2) || 3128 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3129 chp->ch_drive[1].UDMA_mode <= 2)) { 3130 if (chp->ch_drive[0].UDMA_mode > 2) 3131 chp->ch_drive[0].UDMA_mode = 2; 3132 if (chp->ch_drive[1].UDMA_mode > 2) 3133 chp->ch_drive[1].UDMA_mode = 2; 3134 } 3135 /* Set U66 if needed */ 3136 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3137 chp->ch_drive[0].UDMA_mode > 2) || 3138 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3139 chp->ch_drive[1].UDMA_mode > 2)) 3140 scr |= PDC262_U66_EN(channel); 3141 else 3142 scr &= ~PDC262_U66_EN(channel); 3143 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3144 PDC262_U66, scr); 3145 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3146 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3147 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3148 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3149 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3150 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3151 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3152 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3153 atapi = 0; 3154 else 3155 atapi = PDC262_ATAPI_UDMA; 3156 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3157 PDC262_ATAPI(channel), atapi); 3158 } 3159 } 3160 for (drive = 0; drive < 2; drive++) { 3161 drvp = &chp->ch_drive[drive]; 3162 /* If no drive, skip */ 3163 if ((drvp->drive_flags & DRIVE) == 0) 3164 continue; 3165 mode = 0; 3166 if (drvp->drive_flags & DRIVE_UDMA) { 3167 mode = PDC2xx_TIM_SET_MB(mode, 3168 pdc2xx_udma_mb[drvp->UDMA_mode]); 3169 mode = PDC2xx_TIM_SET_MC(mode, 3170 pdc2xx_udma_mc[drvp->UDMA_mode]); 3171 drvp->drive_flags &= ~DRIVE_DMA; 3172 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3173 } else if (drvp->drive_flags & DRIVE_DMA) { 3174 mode = PDC2xx_TIM_SET_MB(mode, 3175 pdc2xx_dma_mb[drvp->DMA_mode]); 3176 mode = PDC2xx_TIM_SET_MC(mode, 3177 pdc2xx_dma_mc[drvp->DMA_mode]); 3178 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3179 } else { 3180 mode = PDC2xx_TIM_SET_MB(mode, 3181 pdc2xx_dma_mb[0]); 3182 mode = PDC2xx_TIM_SET_MC(mode, 3183 pdc2xx_dma_mc[0]); 3184 } 3185 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3186 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3187 if (drvp->drive_flags & DRIVE_ATA) 3188 mode |= PDC2xx_TIM_PRE; 3189 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3190 if (drvp->PIO_mode >= 3) { 3191 mode |= PDC2xx_TIM_IORDY; 3192 if (drive == 0) 3193 mode |= PDC2xx_TIM_IORDYp; 3194 } 3195 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3196 "timings 0x%x\n", 3197 sc->sc_wdcdev.sc_dev.dv_xname, 3198 chp->channel, drive, mode), DEBUG_PROBE); 3199 pci_conf_write(sc->sc_pc, sc->sc_tag, 3200 PDC2xx_TIM(chp->channel, drive), mode); 3201 } 3202 if (idedma_ctl != 0) { 3203 /* Add software bits in status register */ 3204 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3205 IDEDMA_CTL, idedma_ctl); 3206 } 3207 pciide_print_modes(cp); 3208 } 3209 3210 int 3211 pdc202xx_pci_intr(arg) 3212 void *arg; 3213 { 3214 struct pciide_softc *sc = arg; 3215 struct pciide_channel *cp; 3216 struct channel_softc *wdc_cp; 3217 int i, rv, crv; 3218 u_int32_t scr; 3219 3220 rv = 0; 3221 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3222 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3223 cp = &sc->pciide_channels[i]; 3224 wdc_cp = &cp->wdc_channel; 3225 /* If a compat channel skip. */ 3226 if (cp->compat) 3227 continue; 3228 if (scr & PDC2xx_SCR_INT(i)) { 3229 crv = wdcintr(wdc_cp); 3230 if (crv == 0) 3231 printf("%s:%d: bogus intr\n", 3232 sc->sc_wdcdev.sc_dev.dv_xname, i); 3233 else 3234 rv = 1; 3235 } 3236 } 3237 return rv; 3238 } 3239 3240 void 3241 opti_chip_map(sc, pa) 3242 struct pciide_softc *sc; 3243 struct pci_attach_args *pa; 3244 { 3245 struct pciide_channel *cp; 3246 bus_size_t cmdsize, ctlsize; 3247 pcireg_t interface; 3248 u_int8_t init_ctrl; 3249 int channel; 3250 3251 if (pciide_chipen(sc, pa) == 0) 3252 return; 3253 printf("%s: bus-master DMA support present", 3254 sc->sc_wdcdev.sc_dev.dv_xname); 3255 pciide_mapreg_dma(sc, pa); 3256 printf("\n"); 3257 3258 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3259 WDC_CAPABILITY_MODE; 3260 sc->sc_wdcdev.PIO_cap = 4; 3261 if (sc->sc_dma_ok) { 3262 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3263 sc->sc_wdcdev.irqack = pciide_irqack; 3264 sc->sc_wdcdev.DMA_cap = 2; 3265 } 3266 sc->sc_wdcdev.set_modes = opti_setup_channel; 3267 3268 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3269 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3270 3271 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3272 OPTI_REG_INIT_CONTROL); 3273 3274 interface = PCI_INTERFACE(pa->pa_class); 3275 3276 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3277 cp = &sc->pciide_channels[channel]; 3278 if (pciide_chansetup(sc, channel, interface) == 0) 3279 continue; 3280 if (channel == 1 && 3281 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3282 printf("%s: %s channel ignored (disabled)\n", 3283 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3284 continue; 3285 } 3286 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3287 pciide_pci_intr); 3288 if (cp->hw_ok == 0) 3289 continue; 3290 pciide_map_compat_intr(pa, cp, channel, interface); 3291 if (cp->hw_ok == 0) 3292 continue; 3293 opti_setup_channel(&cp->wdc_channel); 3294 } 3295 } 3296 3297 void 3298 opti_setup_channel(chp) 3299 struct channel_softc *chp; 3300 { 3301 struct ata_drive_datas *drvp; 3302 struct pciide_channel *cp = (struct pciide_channel*)chp; 3303 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3304 int drive, spd; 3305 int mode[2]; 3306 u_int8_t rv, mr; 3307 3308 /* 3309 * The `Delay' and `Address Setup Time' fields of the 3310 * Miscellaneous Register are always zero initially. 3311 */ 3312 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3313 mr &= ~(OPTI_MISC_DELAY_MASK | 3314 OPTI_MISC_ADDR_SETUP_MASK | 3315 OPTI_MISC_INDEX_MASK); 3316 3317 /* Prime the control register before setting timing values */ 3318 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3319 3320 /* Determine the clockrate of the PCIbus the chip is attached to */ 3321 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3322 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3323 3324 /* setup DMA if needed */ 3325 pciide_channel_dma_setup(cp); 3326 3327 for (drive = 0; drive < 2; drive++) { 3328 drvp = &chp->ch_drive[drive]; 3329 /* If no drive, skip */ 3330 if ((drvp->drive_flags & DRIVE) == 0) { 3331 mode[drive] = -1; 3332 continue; 3333 } 3334 3335 if ((drvp->drive_flags & DRIVE_DMA)) { 3336 /* 3337 * Timings will be used for both PIO and DMA, 3338 * so adjust DMA mode if needed 3339 */ 3340 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3341 drvp->PIO_mode = drvp->DMA_mode + 2; 3342 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3343 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3344 drvp->PIO_mode - 2 : 0; 3345 if (drvp->DMA_mode == 0) 3346 drvp->PIO_mode = 0; 3347 3348 mode[drive] = drvp->DMA_mode + 5; 3349 } else 3350 mode[drive] = drvp->PIO_mode; 3351 3352 if (drive && mode[0] >= 0 && 3353 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3354 /* 3355 * Can't have two drives using different values 3356 * for `Address Setup Time'. 3357 * Slow down the faster drive to compensate. 3358 */ 3359 int d = (opti_tim_as[spd][mode[0]] > 3360 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3361 3362 mode[d] = mode[1-d]; 3363 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3364 chp->ch_drive[d].DMA_mode = 0; 3365 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3366 } 3367 } 3368 3369 for (drive = 0; drive < 2; drive++) { 3370 int m; 3371 if ((m = mode[drive]) < 0) 3372 continue; 3373 3374 /* Set the Address Setup Time and select appropriate index */ 3375 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3376 rv |= OPTI_MISC_INDEX(drive); 3377 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3378 3379 /* Set the pulse width and recovery timing parameters */ 3380 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3381 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3382 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3383 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3384 3385 /* Set the Enhanced Mode register appropriately */ 3386 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3387 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3388 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3389 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3390 } 3391 3392 /* Finally, enable the timings */ 3393 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3394 3395 pciide_print_modes(cp); 3396 } 3397
Indexes created Thu Oct 02 10:09:58 GMT 2025