pciide.c revision 1.75
1 /* $NetBSD: pciide.c,v 1.75 2000/07/05 16:11:35 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 #include <dev/pci/pciidereg.h> 105 #include <dev/pci/pciidevar.h> 106 #include <dev/pci/pciide_piix_reg.h> 107 #include <dev/pci/pciide_amd_reg.h> 108 #include <dev/pci/pciide_apollo_reg.h> 109 #include <dev/pci/pciide_cmd_reg.h> 110 #include <dev/pci/pciide_cy693_reg.h> 111 #include <dev/pci/pciide_sis_reg.h> 112 #include <dev/pci/pciide_acer_reg.h> 113 #include <dev/pci/pciide_pdc202xx_reg.h> 114 #include <dev/pci/pciide_opti_reg.h> 115 #include <dev/pci/pciide_hpt_reg.h> 116 #include <dev/pci/cy82c693var.h> 117 118 /* inlines for reading/writing 8-bit PCI registers */ 119 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 120 int)); 121 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 122 int, u_int8_t)); 123 124 static __inline u_int8_t 125 pciide_pci_read(pc, pa, reg) 126 pci_chipset_tag_t pc; 127 pcitag_t pa; 128 int reg; 129 { 130 131 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 132 ((reg & 0x03) * 8) & 0xff); 133 } 134 135 static __inline void 136 pciide_pci_write(pc, pa, reg, val) 137 pci_chipset_tag_t pc; 138 pcitag_t pa; 139 int reg; 140 u_int8_t val; 141 { 142 pcireg_t pcival; 143 144 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 145 pcival &= ~(0xff << ((reg & 0x03) * 8)); 146 pcival |= (val << ((reg & 0x03) * 8)); 147 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 148 } 149 150 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 151 152 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 153 void piix_setup_channel __P((struct channel_softc*)); 154 void piix3_4_setup_channel __P((struct channel_softc*)); 155 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 156 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 157 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 158 159 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 160 void amd756_setup_channel __P((struct channel_softc*)); 161 162 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 163 void apollo_setup_channel __P((struct channel_softc*)); 164 165 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 166 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 167 void cmd0643_9_setup_channel __P((struct channel_softc*)); 168 void cmd_channel_map __P((struct pci_attach_args *, 169 struct pciide_softc *, int)); 170 int cmd_pci_intr __P((void *)); 171 void cmd648_9_irqack __P((struct channel_softc *)); 172 173 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cy693_setup_channel __P((struct channel_softc*)); 175 176 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 177 void sis_setup_channel __P((struct channel_softc*)); 178 179 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 180 void acer_setup_channel __P((struct channel_softc*)); 181 int acer_pci_intr __P((void *)); 182 183 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 184 void pdc202xx_setup_channel __P((struct channel_softc*)); 185 int pdc202xx_pci_intr __P((void *)); 186 187 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 188 void opti_setup_channel __P((struct channel_softc*)); 189 190 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 191 void hpt_setup_channel __P((struct channel_softc*)); 192 int hpt_pci_intr __P((void *)); 193 194 void pciide_channel_dma_setup __P((struct pciide_channel *)); 195 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 196 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 197 void pciide_dma_start __P((void*, int, int)); 198 int pciide_dma_finish __P((void*, int, int, int)); 199 void pciide_irqack __P((struct channel_softc *)); 200 void pciide_print_modes __P((struct pciide_channel *)); 201 202 struct pciide_product_desc { 203 u_int32_t ide_product; 204 int ide_flags; 205 const char *ide_name; 206 /* map and setup chip, probe drives */ 207 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 208 }; 209 210 /* Flags for ide_flags */ 211 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 212 213 /* Default product description for devices not known from this controller */ 214 const struct pciide_product_desc default_product_desc = { 215 0, 216 0, 217 "Generic PCI IDE controller", 218 default_chip_map, 219 }; 220 221 const struct pciide_product_desc pciide_intel_products[] = { 222 { PCI_PRODUCT_INTEL_82092AA, 223 0, 224 "Intel 82092AA IDE controller", 225 default_chip_map, 226 }, 227 { PCI_PRODUCT_INTEL_82371FB_IDE, 228 0, 229 "Intel 82371FB IDE controller (PIIX)", 230 piix_chip_map, 231 }, 232 { PCI_PRODUCT_INTEL_82371SB_IDE, 233 0, 234 "Intel 82371SB IDE Interface (PIIX3)", 235 piix_chip_map, 236 }, 237 { PCI_PRODUCT_INTEL_82371AB_IDE, 238 0, 239 "Intel 82371AB IDE controller (PIIX4)", 240 piix_chip_map, 241 }, 242 { PCI_PRODUCT_INTEL_82801AA_IDE, 243 0, 244 "Intel 82801AA IDE Controller (ICH)", 245 piix_chip_map, 246 }, 247 { PCI_PRODUCT_INTEL_82801AB_IDE, 248 0, 249 "Intel 82801AB IDE Controller (ICH0)", 250 piix_chip_map, 251 }, 252 { 0, 253 0, 254 NULL, 255 } 256 }; 257 258 const struct pciide_product_desc pciide_amd_products[] = { 259 { PCI_PRODUCT_AMD_PBC756_IDE, 260 0, 261 "Advanced Micro Devices AMD756 IDE Controller", 262 amd756_chip_map 263 }, 264 { 0, 265 0, 266 NULL, 267 } 268 }; 269 270 const struct pciide_product_desc pciide_cmd_products[] = { 271 { PCI_PRODUCT_CMDTECH_640, 272 0, 273 "CMD Technology PCI0640", 274 cmd_chip_map 275 }, 276 { PCI_PRODUCT_CMDTECH_643, 277 0, 278 "CMD Technology PCI0643", 279 cmd0643_9_chip_map, 280 }, 281 { PCI_PRODUCT_CMDTECH_646, 282 0, 283 "CMD Technology PCI0646", 284 cmd0643_9_chip_map, 285 }, 286 { PCI_PRODUCT_CMDTECH_648, 287 IDE_PCI_CLASS_OVERRIDE, 288 "CMD Technology PCI0648", 289 cmd0643_9_chip_map, 290 }, 291 { PCI_PRODUCT_CMDTECH_649, 292 IDE_PCI_CLASS_OVERRIDE, 293 "CMD Technology PCI0649", 294 cmd0643_9_chip_map, 295 }, 296 { 0, 297 0, 298 NULL, 299 } 300 }; 301 302 const struct pciide_product_desc pciide_via_products[] = { 303 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 304 0, 305 "VIA Tech VT82C586 IDE Controller", 306 apollo_chip_map, 307 }, 308 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 309 0, 310 "VIA Tech VT82C586A IDE Controller", 311 apollo_chip_map, 312 }, 313 { 0, 314 0, 315 NULL, 316 } 317 }; 318 319 const struct pciide_product_desc pciide_cypress_products[] = { 320 { PCI_PRODUCT_CONTAQ_82C693, 321 0, 322 "Cypress 82C693 IDE Controller", 323 cy693_chip_map, 324 }, 325 { 0, 326 0, 327 NULL, 328 } 329 }; 330 331 const struct pciide_product_desc pciide_sis_products[] = { 332 { PCI_PRODUCT_SIS_5597_IDE, 333 0, 334 "Silicon Integrated System 5597/5598 IDE controller", 335 sis_chip_map, 336 }, 337 { 0, 338 0, 339 NULL, 340 } 341 }; 342 343 const struct pciide_product_desc pciide_acer_products[] = { 344 { PCI_PRODUCT_ALI_M5229, 345 0, 346 "Acer Labs M5229 UDMA IDE Controller", 347 acer_chip_map, 348 }, 349 { 0, 350 0, 351 NULL, 352 } 353 }; 354 355 const struct pciide_product_desc pciide_promise_products[] = { 356 { PCI_PRODUCT_PROMISE_ULTRA33, 357 IDE_PCI_CLASS_OVERRIDE, 358 "Promise Ultra33/ATA Bus Master IDE Accelerator", 359 pdc202xx_chip_map, 360 }, 361 { PCI_PRODUCT_PROMISE_ULTRA66, 362 IDE_PCI_CLASS_OVERRIDE, 363 "Promise Ultra66/ATA Bus Master IDE Accelerator", 364 pdc202xx_chip_map, 365 }, 366 { PCI_PRODUCT_PROMISE_ULTRA100, 367 IDE_PCI_CLASS_OVERRIDE, 368 "Promise Ultra100/ATA Bus Master IDE Accelerator", 369 pdc202xx_chip_map, 370 }, 371 { 0, 372 0, 373 NULL, 374 } 375 }; 376 377 const struct pciide_product_desc pciide_opti_products[] = { 378 { PCI_PRODUCT_OPTI_82C621, 379 0, 380 "OPTi 82c621 PCI IDE controller", 381 opti_chip_map, 382 }, 383 { PCI_PRODUCT_OPTI_82C568, 384 0, 385 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 386 opti_chip_map, 387 }, 388 { PCI_PRODUCT_OPTI_82D568, 389 0, 390 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 391 opti_chip_map, 392 }, 393 { 0, 394 0, 395 NULL, 396 } 397 }; 398 399 const struct pciide_product_desc pciide_triones_products[] = { 400 { PCI_PRODUCT_TRIONES_HPT366, 401 IDE_PCI_CLASS_OVERRIDE, 402 "Triones/Highpoint HPT366/370 IDE Controller", 403 hpt_chip_map, 404 }, 405 { 0, 406 0, 407 NULL, 408 } 409 }; 410 411 struct pciide_vendor_desc { 412 u_int32_t ide_vendor; 413 const struct pciide_product_desc *ide_products; 414 }; 415 416 const struct pciide_vendor_desc pciide_vendors[] = { 417 { PCI_VENDOR_INTEL, pciide_intel_products }, 418 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 419 { PCI_VENDOR_VIATECH, pciide_via_products }, 420 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 421 { PCI_VENDOR_SIS, pciide_sis_products }, 422 { PCI_VENDOR_ALI, pciide_acer_products }, 423 { PCI_VENDOR_PROMISE, pciide_promise_products }, 424 { PCI_VENDOR_AMD, pciide_amd_products }, 425 { PCI_VENDOR_OPTI, pciide_opti_products }, 426 { PCI_VENDOR_TRIONES, pciide_triones_products }, 427 { 0, NULL } 428 }; 429 430 /* options passed via the 'flags' config keyword */ 431 #define PCIIDE_OPTIONS_DMA 0x01 432 433 int pciide_match __P((struct device *, struct cfdata *, void *)); 434 void pciide_attach __P((struct device *, struct device *, void *)); 435 436 struct cfattach pciide_ca = { 437 sizeof(struct pciide_softc), pciide_match, pciide_attach 438 }; 439 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 440 int pciide_mapregs_compat __P(( struct pci_attach_args *, 441 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 442 int pciide_mapregs_native __P((struct pci_attach_args *, 443 struct pciide_channel *, bus_size_t *, bus_size_t *, 444 int (*pci_intr) __P((void *)))); 445 void pciide_mapreg_dma __P((struct pciide_softc *, 446 struct pci_attach_args *)); 447 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 448 void pciide_mapchan __P((struct pci_attach_args *, 449 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 450 int (*pci_intr) __P((void *)))); 451 int pciide_chan_candisable __P((struct pciide_channel *)); 452 void pciide_map_compat_intr __P(( struct pci_attach_args *, 453 struct pciide_channel *, int, int)); 454 int pciide_print __P((void *, const char *pnp)); 455 int pciide_compat_intr __P((void *)); 456 int pciide_pci_intr __P((void *)); 457 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 458 459 const struct pciide_product_desc * 460 pciide_lookup_product(id) 461 u_int32_t id; 462 { 463 const struct pciide_product_desc *pp; 464 const struct pciide_vendor_desc *vp; 465 466 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 467 if (PCI_VENDOR(id) == vp->ide_vendor) 468 break; 469 470 if ((pp = vp->ide_products) == NULL) 471 return NULL; 472 473 for (; pp->ide_name != NULL; pp++) 474 if (PCI_PRODUCT(id) == pp->ide_product) 475 break; 476 477 if (pp->ide_name == NULL) 478 return NULL; 479 return pp; 480 } 481 482 int 483 pciide_match(parent, match, aux) 484 struct device *parent; 485 struct cfdata *match; 486 void *aux; 487 { 488 struct pci_attach_args *pa = aux; 489 const struct pciide_product_desc *pp; 490 491 /* 492 * Check the ID register to see that it's a PCI IDE controller. 493 * If it is, we assume that we can deal with it; it _should_ 494 * work in a standardized way... 495 */ 496 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 497 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 498 return (1); 499 } 500 501 /* 502 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 503 * controllers. Let see if we can deal with it anyway. 504 */ 505 pp = pciide_lookup_product(pa->pa_id); 506 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 507 return (1); 508 } 509 510 return (0); 511 } 512 513 void 514 pciide_attach(parent, self, aux) 515 struct device *parent, *self; 516 void *aux; 517 { 518 struct pci_attach_args *pa = aux; 519 pci_chipset_tag_t pc = pa->pa_pc; 520 pcitag_t tag = pa->pa_tag; 521 struct pciide_softc *sc = (struct pciide_softc *)self; 522 pcireg_t csr; 523 char devinfo[256]; 524 const char *displaydev; 525 526 sc->sc_pp = pciide_lookup_product(pa->pa_id); 527 if (sc->sc_pp == NULL) { 528 sc->sc_pp = &default_product_desc; 529 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 530 displaydev = devinfo; 531 } else 532 displaydev = sc->sc_pp->ide_name; 533 534 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 535 536 sc->sc_pc = pa->pa_pc; 537 sc->sc_tag = pa->pa_tag; 538 #ifdef WDCDEBUG 539 if (wdcdebug_pciide_mask & DEBUG_PROBE) 540 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 541 #endif 542 sc->sc_pp->chip_map(sc, pa); 543 544 if (sc->sc_dma_ok) { 545 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 546 csr |= PCI_COMMAND_MASTER_ENABLE; 547 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 548 } 549 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 550 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 551 } 552 553 /* tell wether the chip is enabled or not */ 554 int 555 pciide_chipen(sc, pa) 556 struct pciide_softc *sc; 557 struct pci_attach_args *pa; 558 { 559 pcireg_t csr; 560 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 561 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 562 PCI_COMMAND_STATUS_REG); 563 printf("%s: device disabled (at %s)\n", 564 sc->sc_wdcdev.sc_dev.dv_xname, 565 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 566 "device" : "bridge"); 567 return 0; 568 } 569 return 1; 570 } 571 572 int 573 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 574 struct pci_attach_args *pa; 575 struct pciide_channel *cp; 576 int compatchan; 577 bus_size_t *cmdsizep, *ctlsizep; 578 { 579 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 580 struct channel_softc *wdc_cp = &cp->wdc_channel; 581 582 cp->compat = 1; 583 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 584 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 585 586 wdc_cp->cmd_iot = pa->pa_iot; 587 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 588 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 589 printf("%s: couldn't map %s channel cmd regs\n", 590 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 591 return (0); 592 } 593 594 wdc_cp->ctl_iot = pa->pa_iot; 595 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 596 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 597 printf("%s: couldn't map %s channel ctl regs\n", 598 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 599 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 600 PCIIDE_COMPAT_CMD_SIZE); 601 return (0); 602 } 603 604 return (1); 605 } 606 607 int 608 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 609 struct pci_attach_args * pa; 610 struct pciide_channel *cp; 611 bus_size_t *cmdsizep, *ctlsizep; 612 int (*pci_intr) __P((void *)); 613 { 614 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 615 struct channel_softc *wdc_cp = &cp->wdc_channel; 616 const char *intrstr; 617 pci_intr_handle_t intrhandle; 618 619 cp->compat = 0; 620 621 if (sc->sc_pci_ih == NULL) { 622 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 623 pa->pa_intrline, &intrhandle) != 0) { 624 printf("%s: couldn't map native-PCI interrupt\n", 625 sc->sc_wdcdev.sc_dev.dv_xname); 626 return 0; 627 } 628 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 629 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 630 intrhandle, IPL_BIO, pci_intr, sc); 631 if (sc->sc_pci_ih != NULL) { 632 printf("%s: using %s for native-PCI interrupt\n", 633 sc->sc_wdcdev.sc_dev.dv_xname, 634 intrstr ? intrstr : "unknown interrupt"); 635 } else { 636 printf("%s: couldn't establish native-PCI interrupt", 637 sc->sc_wdcdev.sc_dev.dv_xname); 638 if (intrstr != NULL) 639 printf(" at %s", intrstr); 640 printf("\n"); 641 return 0; 642 } 643 } 644 cp->ih = sc->sc_pci_ih; 645 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 646 PCI_MAPREG_TYPE_IO, 0, 647 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 648 printf("%s: couldn't map %s channel cmd regs\n", 649 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 650 return 0; 651 } 652 653 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 654 PCI_MAPREG_TYPE_IO, 0, 655 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 656 printf("%s: couldn't map %s channel ctl regs\n", 657 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 658 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 659 return 0; 660 } 661 return (1); 662 } 663 664 void 665 pciide_mapreg_dma(sc, pa) 666 struct pciide_softc *sc; 667 struct pci_attach_args *pa; 668 { 669 pcireg_t maptype; 670 671 /* 672 * Map DMA registers 673 * 674 * Note that sc_dma_ok is the right variable to test to see if 675 * DMA can be done. If the interface doesn't support DMA, 676 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 677 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 678 * non-zero if the interface supports DMA and the registers 679 * could be mapped. 680 * 681 * XXX Note that despite the fact that the Bus Master IDE specs 682 * XXX say that "The bus master IDE function uses 16 bytes of IO 683 * XXX space," some controllers (at least the United 684 * XXX Microelectronics UM8886BF) place it in memory space. 685 */ 686 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 687 PCIIDE_REG_BUS_MASTER_DMA); 688 689 switch (maptype) { 690 case PCI_MAPREG_TYPE_IO: 691 case PCI_MAPREG_MEM_TYPE_32BIT: 692 sc->sc_dma_ok = (pci_mapreg_map(pa, 693 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 694 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 695 sc->sc_dmat = pa->pa_dmat; 696 if (sc->sc_dma_ok == 0) { 697 printf(", but unused (couldn't map registers)"); 698 } else { 699 sc->sc_wdcdev.dma_arg = sc; 700 sc->sc_wdcdev.dma_init = pciide_dma_init; 701 sc->sc_wdcdev.dma_start = pciide_dma_start; 702 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 703 } 704 break; 705 706 default: 707 sc->sc_dma_ok = 0; 708 printf(", but unsupported register maptype (0x%x)", maptype); 709 } 710 } 711 712 int 713 pciide_compat_intr(arg) 714 void *arg; 715 { 716 struct pciide_channel *cp = arg; 717 718 #ifdef DIAGNOSTIC 719 /* should only be called for a compat channel */ 720 if (cp->compat == 0) 721 panic("pciide compat intr called for non-compat chan %p\n", cp); 722 #endif 723 return (wdcintr(&cp->wdc_channel)); 724 } 725 726 int 727 pciide_pci_intr(arg) 728 void *arg; 729 { 730 struct pciide_softc *sc = arg; 731 struct pciide_channel *cp; 732 struct channel_softc *wdc_cp; 733 int i, rv, crv; 734 735 rv = 0; 736 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 737 cp = &sc->pciide_channels[i]; 738 wdc_cp = &cp->wdc_channel; 739 740 /* If a compat channel skip. */ 741 if (cp->compat) 742 continue; 743 /* if this channel not waiting for intr, skip */ 744 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 745 continue; 746 747 crv = wdcintr(wdc_cp); 748 if (crv == 0) 749 ; /* leave rv alone */ 750 else if (crv == 1) 751 rv = 1; /* claim the intr */ 752 else if (rv == 0) /* crv should be -1 in this case */ 753 rv = crv; /* if we've done no better, take it */ 754 } 755 return (rv); 756 } 757 758 void 759 pciide_channel_dma_setup(cp) 760 struct pciide_channel *cp; 761 { 762 int drive; 763 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 764 struct ata_drive_datas *drvp; 765 766 for (drive = 0; drive < 2; drive++) { 767 drvp = &cp->wdc_channel.ch_drive[drive]; 768 /* If no drive, skip */ 769 if ((drvp->drive_flags & DRIVE) == 0) 770 continue; 771 /* setup DMA if needed */ 772 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 773 (drvp->drive_flags & DRIVE_UDMA) == 0) || 774 sc->sc_dma_ok == 0) { 775 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 776 continue; 777 } 778 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 779 != 0) { 780 /* Abort DMA setup */ 781 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 782 continue; 783 } 784 } 785 } 786 787 int 788 pciide_dma_table_setup(sc, channel, drive) 789 struct pciide_softc *sc; 790 int channel, drive; 791 { 792 bus_dma_segment_t seg; 793 int error, rseg; 794 const bus_size_t dma_table_size = 795 sizeof(struct idedma_table) * NIDEDMA_TABLES; 796 struct pciide_dma_maps *dma_maps = 797 &sc->pciide_channels[channel].dma_maps[drive]; 798 799 /* If table was already allocated, just return */ 800 if (dma_maps->dma_table) 801 return 0; 802 803 /* Allocate memory for the DMA tables and map it */ 804 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 805 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 806 BUS_DMA_NOWAIT)) != 0) { 807 printf("%s:%d: unable to allocate table DMA for " 808 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 809 channel, drive, error); 810 return error; 811 } 812 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 813 dma_table_size, 814 (caddr_t *)&dma_maps->dma_table, 815 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 816 printf("%s:%d: unable to map table DMA for" 817 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 818 channel, drive, error); 819 return error; 820 } 821 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 822 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 823 seg.ds_addr), DEBUG_PROBE); 824 825 /* Create and load table DMA map for this disk */ 826 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 827 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 828 &dma_maps->dmamap_table)) != 0) { 829 printf("%s:%d: unable to create table DMA map for " 830 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 831 channel, drive, error); 832 return error; 833 } 834 if ((error = bus_dmamap_load(sc->sc_dmat, 835 dma_maps->dmamap_table, 836 dma_maps->dma_table, 837 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 838 printf("%s:%d: unable to load table DMA map for " 839 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 840 channel, drive, error); 841 return error; 842 } 843 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 844 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 845 /* Create a xfer DMA map for this drive */ 846 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 847 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 848 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 849 &dma_maps->dmamap_xfer)) != 0) { 850 printf("%s:%d: unable to create xfer DMA map for " 851 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 852 channel, drive, error); 853 return error; 854 } 855 return 0; 856 } 857 858 int 859 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 860 void *v; 861 int channel, drive; 862 void *databuf; 863 size_t datalen; 864 int flags; 865 { 866 struct pciide_softc *sc = v; 867 int error, seg; 868 struct pciide_dma_maps *dma_maps = 869 &sc->pciide_channels[channel].dma_maps[drive]; 870 871 error = bus_dmamap_load(sc->sc_dmat, 872 dma_maps->dmamap_xfer, 873 databuf, datalen, NULL, BUS_DMA_NOWAIT); 874 if (error) { 875 printf("%s:%d: unable to load xfer DMA map for" 876 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 877 channel, drive, error); 878 return error; 879 } 880 881 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 882 dma_maps->dmamap_xfer->dm_mapsize, 883 (flags & WDC_DMA_READ) ? 884 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 885 886 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 887 #ifdef DIAGNOSTIC 888 /* A segment must not cross a 64k boundary */ 889 { 890 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 891 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 892 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 893 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 894 printf("pciide_dma: segment %d physical addr 0x%lx" 895 " len 0x%lx not properly aligned\n", 896 seg, phys, len); 897 panic("pciide_dma: buf align"); 898 } 899 } 900 #endif 901 dma_maps->dma_table[seg].base_addr = 902 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 903 dma_maps->dma_table[seg].byte_count = 904 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 905 IDEDMA_BYTE_COUNT_MASK); 906 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 907 seg, le32toh(dma_maps->dma_table[seg].byte_count), 908 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 909 910 } 911 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 912 htole32(IDEDMA_BYTE_COUNT_EOT); 913 914 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 915 dma_maps->dmamap_table->dm_mapsize, 916 BUS_DMASYNC_PREWRITE); 917 918 /* Maps are ready. Start DMA function */ 919 #ifdef DIAGNOSTIC 920 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 921 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 922 dma_maps->dmamap_table->dm_segs[0].ds_addr); 923 panic("pciide_dma_init: table align"); 924 } 925 #endif 926 927 /* Clear status bits */ 928 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 929 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 930 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 931 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 932 /* Write table addr */ 933 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 934 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 935 dma_maps->dmamap_table->dm_segs[0].ds_addr); 936 /* set read/write */ 937 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 938 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 939 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 940 /* remember flags */ 941 dma_maps->dma_flags = flags; 942 return 0; 943 } 944 945 void 946 pciide_dma_start(v, channel, drive) 947 void *v; 948 int channel, drive; 949 { 950 struct pciide_softc *sc = v; 951 952 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 953 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 954 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 955 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 956 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 957 } 958 959 int 960 pciide_dma_finish(v, channel, drive, force) 961 void *v; 962 int channel, drive; 963 int force; 964 { 965 struct pciide_softc *sc = v; 966 u_int8_t status; 967 int error = 0; 968 struct pciide_dma_maps *dma_maps = 969 &sc->pciide_channels[channel].dma_maps[drive]; 970 971 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 972 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 973 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 974 DEBUG_XFERS); 975 976 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 977 return WDC_DMAST_NOIRQ; 978 979 /* stop DMA channel */ 980 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 981 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 982 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 983 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 984 985 /* Unload the map of the data buffer */ 986 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 987 dma_maps->dmamap_xfer->dm_mapsize, 988 (dma_maps->dma_flags & WDC_DMA_READ) ? 989 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 990 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 991 992 if ((status & IDEDMA_CTL_ERR) != 0) { 993 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 994 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 995 error |= WDC_DMAST_ERR; 996 } 997 998 if ((status & IDEDMA_CTL_INTR) == 0) { 999 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1000 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1001 drive, status); 1002 error |= WDC_DMAST_NOIRQ; 1003 } 1004 1005 if ((status & IDEDMA_CTL_ACT) != 0) { 1006 /* data underrun, may be a valid condition for ATAPI */ 1007 error |= WDC_DMAST_UNDER; 1008 } 1009 return error; 1010 } 1011 1012 void 1013 pciide_irqack(chp) 1014 struct channel_softc *chp; 1015 { 1016 struct pciide_channel *cp = (struct pciide_channel*)chp; 1017 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1018 1019 /* clear status bits in IDE DMA registers */ 1020 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1021 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1022 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1023 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1024 } 1025 1026 /* some common code used by several chip_map */ 1027 int 1028 pciide_chansetup(sc, channel, interface) 1029 struct pciide_softc *sc; 1030 int channel; 1031 pcireg_t interface; 1032 { 1033 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1034 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1035 cp->name = PCIIDE_CHANNEL_NAME(channel); 1036 cp->wdc_channel.channel = channel; 1037 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1038 cp->wdc_channel.ch_queue = 1039 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1040 if (cp->wdc_channel.ch_queue == NULL) { 1041 printf("%s %s channel: " 1042 "can't allocate memory for command queue", 1043 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1044 return 0; 1045 } 1046 printf("%s: %s channel %s to %s mode\n", 1047 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1048 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1049 "configured" : "wired", 1050 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1051 "native-PCI" : "compatibility"); 1052 return 1; 1053 } 1054 1055 /* some common code used by several chip channel_map */ 1056 void 1057 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1058 struct pci_attach_args *pa; 1059 struct pciide_channel *cp; 1060 pcireg_t interface; 1061 bus_size_t *cmdsizep, *ctlsizep; 1062 int (*pci_intr) __P((void *)); 1063 { 1064 struct channel_softc *wdc_cp = &cp->wdc_channel; 1065 1066 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1067 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1068 pci_intr); 1069 else 1070 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1071 wdc_cp->channel, cmdsizep, ctlsizep); 1072 1073 if (cp->hw_ok == 0) 1074 return; 1075 wdc_cp->data32iot = wdc_cp->cmd_iot; 1076 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1077 wdcattach(wdc_cp); 1078 } 1079 1080 /* 1081 * Generic code to call to know if a channel can be disabled. Return 1 1082 * if channel can be disabled, 0 if not 1083 */ 1084 int 1085 pciide_chan_candisable(cp) 1086 struct pciide_channel *cp; 1087 { 1088 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1089 struct channel_softc *wdc_cp = &cp->wdc_channel; 1090 1091 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1092 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1093 printf("%s: disabling %s channel (no drives)\n", 1094 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1095 cp->hw_ok = 0; 1096 return 1; 1097 } 1098 return 0; 1099 } 1100 1101 /* 1102 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1103 * Set hw_ok=0 on failure 1104 */ 1105 void 1106 pciide_map_compat_intr(pa, cp, compatchan, interface) 1107 struct pci_attach_args *pa; 1108 struct pciide_channel *cp; 1109 int compatchan, interface; 1110 { 1111 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1112 struct channel_softc *wdc_cp = &cp->wdc_channel; 1113 1114 if (cp->hw_ok == 0) 1115 return; 1116 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1117 return; 1118 1119 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1120 pa, compatchan, pciide_compat_intr, cp); 1121 if (cp->ih == NULL) { 1122 printf("%s: no compatibility interrupt for use by %s " 1123 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1124 cp->hw_ok = 0; 1125 } 1126 } 1127 1128 void 1129 pciide_print_modes(cp) 1130 struct pciide_channel *cp; 1131 { 1132 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1133 int drive; 1134 struct channel_softc *chp; 1135 struct ata_drive_datas *drvp; 1136 1137 chp = &cp->wdc_channel; 1138 for (drive = 0; drive < 2; drive++) { 1139 drvp = &chp->ch_drive[drive]; 1140 if ((drvp->drive_flags & DRIVE) == 0) 1141 continue; 1142 printf("%s(%s:%d:%d): using PIO mode %d", 1143 drvp->drv_softc->dv_xname, 1144 sc->sc_wdcdev.sc_dev.dv_xname, 1145 chp->channel, drive, drvp->PIO_mode); 1146 if (drvp->drive_flags & DRIVE_DMA) 1147 printf(", DMA mode %d", drvp->DMA_mode); 1148 if (drvp->drive_flags & DRIVE_UDMA) 1149 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1150 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1151 printf(" (using DMA data transfers)"); 1152 printf("\n"); 1153 } 1154 } 1155 1156 void 1157 default_chip_map(sc, pa) 1158 struct pciide_softc *sc; 1159 struct pci_attach_args *pa; 1160 { 1161 struct pciide_channel *cp; 1162 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1163 pcireg_t csr; 1164 int channel, drive; 1165 struct ata_drive_datas *drvp; 1166 u_int8_t idedma_ctl; 1167 bus_size_t cmdsize, ctlsize; 1168 char *failreason; 1169 1170 if (pciide_chipen(sc, pa) == 0) 1171 return; 1172 1173 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1174 printf("%s: bus-master DMA support present", 1175 sc->sc_wdcdev.sc_dev.dv_xname); 1176 if (sc->sc_pp == &default_product_desc && 1177 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1178 PCIIDE_OPTIONS_DMA) == 0) { 1179 printf(", but unused (no driver support)"); 1180 sc->sc_dma_ok = 0; 1181 } else { 1182 pciide_mapreg_dma(sc, pa); 1183 if (sc->sc_dma_ok != 0) 1184 printf(", used without full driver " 1185 "support"); 1186 } 1187 } else { 1188 printf("%s: hardware does not support DMA", 1189 sc->sc_wdcdev.sc_dev.dv_xname); 1190 sc->sc_dma_ok = 0; 1191 } 1192 printf("\n"); 1193 if (sc->sc_dma_ok) { 1194 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1195 sc->sc_wdcdev.irqack = pciide_irqack; 1196 } 1197 sc->sc_wdcdev.PIO_cap = 0; 1198 sc->sc_wdcdev.DMA_cap = 0; 1199 1200 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1201 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1202 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1203 1204 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1205 cp = &sc->pciide_channels[channel]; 1206 if (pciide_chansetup(sc, channel, interface) == 0) 1207 continue; 1208 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1209 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1210 &ctlsize, pciide_pci_intr); 1211 } else { 1212 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1213 channel, &cmdsize, &ctlsize); 1214 } 1215 if (cp->hw_ok == 0) 1216 continue; 1217 /* 1218 * Check to see if something appears to be there. 1219 */ 1220 failreason = NULL; 1221 if (!wdcprobe(&cp->wdc_channel)) { 1222 failreason = "not responding; disabled or no drives?"; 1223 goto next; 1224 } 1225 /* 1226 * Now, make sure it's actually attributable to this PCI IDE 1227 * channel by trying to access the channel again while the 1228 * PCI IDE controller's I/O space is disabled. (If the 1229 * channel no longer appears to be there, it belongs to 1230 * this controller.) YUCK! 1231 */ 1232 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1233 PCI_COMMAND_STATUS_REG); 1234 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1235 csr & ~PCI_COMMAND_IO_ENABLE); 1236 if (wdcprobe(&cp->wdc_channel)) 1237 failreason = "other hardware responding at addresses"; 1238 pci_conf_write(sc->sc_pc, sc->sc_tag, 1239 PCI_COMMAND_STATUS_REG, csr); 1240 next: 1241 if (failreason) { 1242 printf("%s: %s channel ignored (%s)\n", 1243 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1244 failreason); 1245 cp->hw_ok = 0; 1246 bus_space_unmap(cp->wdc_channel.cmd_iot, 1247 cp->wdc_channel.cmd_ioh, cmdsize); 1248 bus_space_unmap(cp->wdc_channel.ctl_iot, 1249 cp->wdc_channel.ctl_ioh, ctlsize); 1250 } else { 1251 pciide_map_compat_intr(pa, cp, channel, interface); 1252 } 1253 if (cp->hw_ok) { 1254 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1255 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1256 wdcattach(&cp->wdc_channel); 1257 } 1258 } 1259 1260 if (sc->sc_dma_ok == 0) 1261 return; 1262 1263 /* Allocate DMA maps */ 1264 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1265 idedma_ctl = 0; 1266 cp = &sc->pciide_channels[channel]; 1267 for (drive = 0; drive < 2; drive++) { 1268 drvp = &cp->wdc_channel.ch_drive[drive]; 1269 /* If no drive, skip */ 1270 if ((drvp->drive_flags & DRIVE) == 0) 1271 continue; 1272 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1273 continue; 1274 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1275 /* Abort DMA setup */ 1276 printf("%s:%d:%d: can't allocate DMA maps, " 1277 "using PIO transfers\n", 1278 sc->sc_wdcdev.sc_dev.dv_xname, 1279 channel, drive); 1280 drvp->drive_flags &= ~DRIVE_DMA; 1281 } 1282 printf("%s:%d:%d: using DMA data transfers\n", 1283 sc->sc_wdcdev.sc_dev.dv_xname, 1284 channel, drive); 1285 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1286 } 1287 if (idedma_ctl != 0) { 1288 /* Add software bits in status register */ 1289 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1290 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1291 idedma_ctl); 1292 } 1293 } 1294 } 1295 1296 void 1297 piix_chip_map(sc, pa) 1298 struct pciide_softc *sc; 1299 struct pci_attach_args *pa; 1300 { 1301 struct pciide_channel *cp; 1302 int channel; 1303 u_int32_t idetim; 1304 bus_size_t cmdsize, ctlsize; 1305 1306 if (pciide_chipen(sc, pa) == 0) 1307 return; 1308 1309 printf("%s: bus-master DMA support present", 1310 sc->sc_wdcdev.sc_dev.dv_xname); 1311 pciide_mapreg_dma(sc, pa); 1312 printf("\n"); 1313 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1314 WDC_CAPABILITY_MODE; 1315 if (sc->sc_dma_ok) { 1316 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1317 sc->sc_wdcdev.irqack = pciide_irqack; 1318 switch(sc->sc_pp->ide_product) { 1319 case PCI_PRODUCT_INTEL_82371AB_IDE: 1320 case PCI_PRODUCT_INTEL_82801AA_IDE: 1321 case PCI_PRODUCT_INTEL_82801AB_IDE: 1322 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1323 } 1324 } 1325 sc->sc_wdcdev.PIO_cap = 4; 1326 sc->sc_wdcdev.DMA_cap = 2; 1327 sc->sc_wdcdev.UDMA_cap = 1328 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1329 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1330 sc->sc_wdcdev.set_modes = piix_setup_channel; 1331 else 1332 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1333 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1334 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1335 1336 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1337 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1338 DEBUG_PROBE); 1339 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1340 WDCDEBUG_PRINT((", sidetim=0x%x", 1341 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1342 DEBUG_PROBE); 1343 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1344 WDCDEBUG_PRINT((", udamreg 0x%x", 1345 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1346 DEBUG_PROBE); 1347 } 1348 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1349 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1350 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1351 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1352 DEBUG_PROBE); 1353 } 1354 1355 } 1356 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1357 1358 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1359 cp = &sc->pciide_channels[channel]; 1360 /* PIIX is compat-only */ 1361 if (pciide_chansetup(sc, channel, 0) == 0) 1362 continue; 1363 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1364 if ((PIIX_IDETIM_READ(idetim, channel) & 1365 PIIX_IDETIM_IDE) == 0) { 1366 printf("%s: %s channel ignored (disabled)\n", 1367 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1368 continue; 1369 } 1370 /* PIIX are compat-only pciide devices */ 1371 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1372 if (cp->hw_ok == 0) 1373 continue; 1374 if (pciide_chan_candisable(cp)) { 1375 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1376 channel); 1377 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1378 idetim); 1379 } 1380 pciide_map_compat_intr(pa, cp, channel, 0); 1381 if (cp->hw_ok == 0) 1382 continue; 1383 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1384 } 1385 1386 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1387 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1388 DEBUG_PROBE); 1389 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1390 WDCDEBUG_PRINT((", sidetim=0x%x", 1391 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1392 DEBUG_PROBE); 1393 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1394 WDCDEBUG_PRINT((", udamreg 0x%x", 1395 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1396 DEBUG_PROBE); 1397 } 1398 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1399 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1400 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1401 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1402 DEBUG_PROBE); 1403 } 1404 } 1405 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1406 } 1407 1408 void 1409 piix_setup_channel(chp) 1410 struct channel_softc *chp; 1411 { 1412 u_int8_t mode[2], drive; 1413 u_int32_t oidetim, idetim, idedma_ctl; 1414 struct pciide_channel *cp = (struct pciide_channel*)chp; 1415 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1416 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1417 1418 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1419 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1420 idedma_ctl = 0; 1421 1422 /* set up new idetim: Enable IDE registers decode */ 1423 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1424 chp->channel); 1425 1426 /* setup DMA */ 1427 pciide_channel_dma_setup(cp); 1428 1429 /* 1430 * Here we have to mess up with drives mode: PIIX can't have 1431 * different timings for master and slave drives. 1432 * We need to find the best combination. 1433 */ 1434 1435 /* If both drives supports DMA, take the lower mode */ 1436 if ((drvp[0].drive_flags & DRIVE_DMA) && 1437 (drvp[1].drive_flags & DRIVE_DMA)) { 1438 mode[0] = mode[1] = 1439 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1440 drvp[0].DMA_mode = mode[0]; 1441 drvp[1].DMA_mode = mode[1]; 1442 goto ok; 1443 } 1444 /* 1445 * If only one drive supports DMA, use its mode, and 1446 * put the other one in PIO mode 0 if mode not compatible 1447 */ 1448 if (drvp[0].drive_flags & DRIVE_DMA) { 1449 mode[0] = drvp[0].DMA_mode; 1450 mode[1] = drvp[1].PIO_mode; 1451 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1452 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1453 mode[1] = drvp[1].PIO_mode = 0; 1454 goto ok; 1455 } 1456 if (drvp[1].drive_flags & DRIVE_DMA) { 1457 mode[1] = drvp[1].DMA_mode; 1458 mode[0] = drvp[0].PIO_mode; 1459 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1460 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1461 mode[0] = drvp[0].PIO_mode = 0; 1462 goto ok; 1463 } 1464 /* 1465 * If both drives are not DMA, takes the lower mode, unless 1466 * one of them is PIO mode < 2 1467 */ 1468 if (drvp[0].PIO_mode < 2) { 1469 mode[0] = drvp[0].PIO_mode = 0; 1470 mode[1] = drvp[1].PIO_mode; 1471 } else if (drvp[1].PIO_mode < 2) { 1472 mode[1] = drvp[1].PIO_mode = 0; 1473 mode[0] = drvp[0].PIO_mode; 1474 } else { 1475 mode[0] = mode[1] = 1476 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1477 drvp[0].PIO_mode = mode[0]; 1478 drvp[1].PIO_mode = mode[1]; 1479 } 1480 ok: /* The modes are setup */ 1481 for (drive = 0; drive < 2; drive++) { 1482 if (drvp[drive].drive_flags & DRIVE_DMA) { 1483 idetim |= piix_setup_idetim_timings( 1484 mode[drive], 1, chp->channel); 1485 goto end; 1486 } 1487 } 1488 /* If we are there, none of the drives are DMA */ 1489 if (mode[0] >= 2) 1490 idetim |= piix_setup_idetim_timings( 1491 mode[0], 0, chp->channel); 1492 else 1493 idetim |= piix_setup_idetim_timings( 1494 mode[1], 0, chp->channel); 1495 end: /* 1496 * timing mode is now set up in the controller. Enable 1497 * it per-drive 1498 */ 1499 for (drive = 0; drive < 2; drive++) { 1500 /* If no drive, skip */ 1501 if ((drvp[drive].drive_flags & DRIVE) == 0) 1502 continue; 1503 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1504 if (drvp[drive].drive_flags & DRIVE_DMA) 1505 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1506 } 1507 if (idedma_ctl != 0) { 1508 /* Add software bits in status register */ 1509 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1510 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1511 idedma_ctl); 1512 } 1513 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1514 pciide_print_modes(cp); 1515 } 1516 1517 void 1518 piix3_4_setup_channel(chp) 1519 struct channel_softc *chp; 1520 { 1521 struct ata_drive_datas *drvp; 1522 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1523 struct pciide_channel *cp = (struct pciide_channel*)chp; 1524 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1525 int drive; 1526 int channel = chp->channel; 1527 1528 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1529 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1530 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1531 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1532 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1533 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1534 PIIX_SIDETIM_RTC_MASK(channel)); 1535 1536 idedma_ctl = 0; 1537 /* If channel disabled, no need to go further */ 1538 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1539 return; 1540 /* set up new idetim: Enable IDE registers decode */ 1541 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1542 1543 /* setup DMA if needed */ 1544 pciide_channel_dma_setup(cp); 1545 1546 for (drive = 0; drive < 2; drive++) { 1547 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1548 PIIX_UDMATIM_SET(0x3, channel, drive)); 1549 drvp = &chp->ch_drive[drive]; 1550 /* If no drive, skip */ 1551 if ((drvp->drive_flags & DRIVE) == 0) 1552 continue; 1553 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1554 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1555 goto pio; 1556 1557 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1558 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1559 ideconf |= PIIX_CONFIG_PINGPONG; 1560 } 1561 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1562 /* setup Ultra/66 */ 1563 if (drvp->UDMA_mode > 2 && 1564 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1565 drvp->UDMA_mode = 2; 1566 if (drvp->UDMA_mode > 2) 1567 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1568 else 1569 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1570 } 1571 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1572 (drvp->drive_flags & DRIVE_UDMA)) { 1573 /* use Ultra/DMA */ 1574 drvp->drive_flags &= ~DRIVE_DMA; 1575 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1576 udmareg |= PIIX_UDMATIM_SET( 1577 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1578 } else { 1579 /* use Multiword DMA */ 1580 drvp->drive_flags &= ~DRIVE_UDMA; 1581 if (drive == 0) { 1582 idetim |= piix_setup_idetim_timings( 1583 drvp->DMA_mode, 1, channel); 1584 } else { 1585 sidetim |= piix_setup_sidetim_timings( 1586 drvp->DMA_mode, 1, channel); 1587 idetim =PIIX_IDETIM_SET(idetim, 1588 PIIX_IDETIM_SITRE, channel); 1589 } 1590 } 1591 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1592 1593 pio: /* use PIO mode */ 1594 idetim |= piix_setup_idetim_drvs(drvp); 1595 if (drive == 0) { 1596 idetim |= piix_setup_idetim_timings( 1597 drvp->PIO_mode, 0, channel); 1598 } else { 1599 sidetim |= piix_setup_sidetim_timings( 1600 drvp->PIO_mode, 0, channel); 1601 idetim =PIIX_IDETIM_SET(idetim, 1602 PIIX_IDETIM_SITRE, channel); 1603 } 1604 } 1605 if (idedma_ctl != 0) { 1606 /* Add software bits in status register */ 1607 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1608 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1609 idedma_ctl); 1610 } 1611 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1612 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1613 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1614 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1615 pciide_print_modes(cp); 1616 } 1617 1618 1619 /* setup ISP and RTC fields, based on mode */ 1620 static u_int32_t 1621 piix_setup_idetim_timings(mode, dma, channel) 1622 u_int8_t mode; 1623 u_int8_t dma; 1624 u_int8_t channel; 1625 { 1626 1627 if (dma) 1628 return PIIX_IDETIM_SET(0, 1629 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1630 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1631 channel); 1632 else 1633 return PIIX_IDETIM_SET(0, 1634 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1635 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1636 channel); 1637 } 1638 1639 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1640 static u_int32_t 1641 piix_setup_idetim_drvs(drvp) 1642 struct ata_drive_datas *drvp; 1643 { 1644 u_int32_t ret = 0; 1645 struct channel_softc *chp = drvp->chnl_softc; 1646 u_int8_t channel = chp->channel; 1647 u_int8_t drive = drvp->drive; 1648 1649 /* 1650 * If drive is using UDMA, timings setups are independant 1651 * So just check DMA and PIO here. 1652 */ 1653 if (drvp->drive_flags & DRIVE_DMA) { 1654 /* if mode = DMA mode 0, use compatible timings */ 1655 if ((drvp->drive_flags & DRIVE_DMA) && 1656 drvp->DMA_mode == 0) { 1657 drvp->PIO_mode = 0; 1658 return ret; 1659 } 1660 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1661 /* 1662 * PIO and DMA timings are the same, use fast timings for PIO 1663 * too, else use compat timings. 1664 */ 1665 if ((piix_isp_pio[drvp->PIO_mode] != 1666 piix_isp_dma[drvp->DMA_mode]) || 1667 (piix_rtc_pio[drvp->PIO_mode] != 1668 piix_rtc_dma[drvp->DMA_mode])) 1669 drvp->PIO_mode = 0; 1670 /* if PIO mode <= 2, use compat timings for PIO */ 1671 if (drvp->PIO_mode <= 2) { 1672 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1673 channel); 1674 return ret; 1675 } 1676 } 1677 1678 /* 1679 * Now setup PIO modes. If mode < 2, use compat timings. 1680 * Else enable fast timings. Enable IORDY and prefetch/post 1681 * if PIO mode >= 3. 1682 */ 1683 1684 if (drvp->PIO_mode < 2) 1685 return ret; 1686 1687 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1688 if (drvp->PIO_mode >= 3) { 1689 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1690 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1691 } 1692 return ret; 1693 } 1694 1695 /* setup values in SIDETIM registers, based on mode */ 1696 static u_int32_t 1697 piix_setup_sidetim_timings(mode, dma, channel) 1698 u_int8_t mode; 1699 u_int8_t dma; 1700 u_int8_t channel; 1701 { 1702 if (dma) 1703 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1704 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1705 else 1706 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1707 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1708 } 1709 1710 void 1711 amd756_chip_map(sc, pa) 1712 struct pciide_softc *sc; 1713 struct pci_attach_args *pa; 1714 { 1715 struct pciide_channel *cp; 1716 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1717 int channel; 1718 pcireg_t chanenable; 1719 bus_size_t cmdsize, ctlsize; 1720 1721 if (pciide_chipen(sc, pa) == 0) 1722 return; 1723 printf("%s: bus-master DMA support present", 1724 sc->sc_wdcdev.sc_dev.dv_xname); 1725 pciide_mapreg_dma(sc, pa); 1726 printf("\n"); 1727 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1728 WDC_CAPABILITY_MODE; 1729 if (sc->sc_dma_ok) { 1730 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1731 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1732 sc->sc_wdcdev.irqack = pciide_irqack; 1733 } 1734 sc->sc_wdcdev.PIO_cap = 4; 1735 sc->sc_wdcdev.DMA_cap = 2; 1736 sc->sc_wdcdev.UDMA_cap = 4; 1737 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1738 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1739 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1740 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1741 1742 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1743 DEBUG_PROBE); 1744 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1745 cp = &sc->pciide_channels[channel]; 1746 if (pciide_chansetup(sc, channel, interface) == 0) 1747 continue; 1748 1749 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1750 printf("%s: %s channel ignored (disabled)\n", 1751 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1752 continue; 1753 } 1754 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1755 pciide_pci_intr); 1756 1757 if (pciide_chan_candisable(cp)) 1758 chanenable &= ~AMD756_CHAN_EN(channel); 1759 pciide_map_compat_intr(pa, cp, channel, interface); 1760 if (cp->hw_ok == 0) 1761 continue; 1762 1763 amd756_setup_channel(&cp->wdc_channel); 1764 } 1765 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1766 chanenable); 1767 return; 1768 } 1769 1770 void 1771 amd756_setup_channel(chp) 1772 struct channel_softc *chp; 1773 { 1774 u_int32_t udmatim_reg, datatim_reg; 1775 u_int8_t idedma_ctl; 1776 int mode, drive; 1777 struct ata_drive_datas *drvp; 1778 struct pciide_channel *cp = (struct pciide_channel*)chp; 1779 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1780 1781 idedma_ctl = 0; 1782 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1783 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1784 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1785 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1786 1787 /* setup DMA if needed */ 1788 pciide_channel_dma_setup(cp); 1789 1790 for (drive = 0; drive < 2; drive++) { 1791 drvp = &chp->ch_drive[drive]; 1792 /* If no drive, skip */ 1793 if ((drvp->drive_flags & DRIVE) == 0) 1794 continue; 1795 /* add timing values, setup DMA if needed */ 1796 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1797 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1798 mode = drvp->PIO_mode; 1799 goto pio; 1800 } 1801 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1802 (drvp->drive_flags & DRIVE_UDMA)) { 1803 /* use Ultra/DMA */ 1804 drvp->drive_flags &= ~DRIVE_DMA; 1805 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1806 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1807 AMD756_UDMA_TIME(chp->channel, drive, 1808 amd756_udma_tim[drvp->UDMA_mode]); 1809 /* can use PIO timings, MW DMA unused */ 1810 mode = drvp->PIO_mode; 1811 } else { 1812 /* use Multiword DMA */ 1813 drvp->drive_flags &= ~DRIVE_UDMA; 1814 /* mode = min(pio, dma+2) */ 1815 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1816 mode = drvp->PIO_mode; 1817 else 1818 mode = drvp->DMA_mode + 2; 1819 } 1820 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1821 1822 pio: /* setup PIO mode */ 1823 if (mode <= 2) { 1824 drvp->DMA_mode = 0; 1825 drvp->PIO_mode = 0; 1826 mode = 0; 1827 } else { 1828 drvp->PIO_mode = mode; 1829 drvp->DMA_mode = mode - 2; 1830 } 1831 datatim_reg |= 1832 AMD756_DATATIM_PULSE(chp->channel, drive, 1833 amd756_pio_set[mode]) | 1834 AMD756_DATATIM_RECOV(chp->channel, drive, 1835 amd756_pio_rec[mode]); 1836 } 1837 if (idedma_ctl != 0) { 1838 /* Add software bits in status register */ 1839 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1840 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1841 idedma_ctl); 1842 } 1843 pciide_print_modes(cp); 1844 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1845 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1846 } 1847 1848 void 1849 apollo_chip_map(sc, pa) 1850 struct pciide_softc *sc; 1851 struct pci_attach_args *pa; 1852 { 1853 struct pciide_channel *cp; 1854 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1855 int channel; 1856 u_int32_t ideconf; 1857 bus_size_t cmdsize, ctlsize; 1858 1859 if (pciide_chipen(sc, pa) == 0) 1860 return; 1861 printf("%s: bus-master DMA support present", 1862 sc->sc_wdcdev.sc_dev.dv_xname); 1863 pciide_mapreg_dma(sc, pa); 1864 printf("\n"); 1865 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1866 WDC_CAPABILITY_MODE; 1867 if (sc->sc_dma_ok) { 1868 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1869 sc->sc_wdcdev.irqack = pciide_irqack; 1870 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1871 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1872 } 1873 sc->sc_wdcdev.PIO_cap = 4; 1874 sc->sc_wdcdev.DMA_cap = 2; 1875 sc->sc_wdcdev.UDMA_cap = 2; 1876 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1877 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1878 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1879 1880 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1881 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1882 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1883 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1884 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1885 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1886 DEBUG_PROBE); 1887 1888 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1889 cp = &sc->pciide_channels[channel]; 1890 if (pciide_chansetup(sc, channel, interface) == 0) 1891 continue; 1892 1893 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1894 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1895 printf("%s: %s channel ignored (disabled)\n", 1896 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1897 continue; 1898 } 1899 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1900 pciide_pci_intr); 1901 if (cp->hw_ok == 0) 1902 continue; 1903 if (pciide_chan_candisable(cp)) { 1904 ideconf &= ~APO_IDECONF_EN(channel); 1905 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1906 ideconf); 1907 } 1908 pciide_map_compat_intr(pa, cp, channel, interface); 1909 1910 if (cp->hw_ok == 0) 1911 continue; 1912 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1913 } 1914 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1915 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1916 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1917 } 1918 1919 void 1920 apollo_setup_channel(chp) 1921 struct channel_softc *chp; 1922 { 1923 u_int32_t udmatim_reg, datatim_reg; 1924 u_int8_t idedma_ctl; 1925 int mode, drive; 1926 struct ata_drive_datas *drvp; 1927 struct pciide_channel *cp = (struct pciide_channel*)chp; 1928 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1929 1930 idedma_ctl = 0; 1931 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1932 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1933 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1934 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1935 1936 /* setup DMA if needed */ 1937 pciide_channel_dma_setup(cp); 1938 1939 for (drive = 0; drive < 2; drive++) { 1940 drvp = &chp->ch_drive[drive]; 1941 /* If no drive, skip */ 1942 if ((drvp->drive_flags & DRIVE) == 0) 1943 continue; 1944 /* add timing values, setup DMA if needed */ 1945 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1946 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1947 mode = drvp->PIO_mode; 1948 goto pio; 1949 } 1950 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1951 (drvp->drive_flags & DRIVE_UDMA)) { 1952 /* use Ultra/DMA */ 1953 drvp->drive_flags &= ~DRIVE_DMA; 1954 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1955 APO_UDMA_EN_MTH(chp->channel, drive) | 1956 APO_UDMA_TIME(chp->channel, drive, 1957 apollo_udma_tim[drvp->UDMA_mode]); 1958 /* can use PIO timings, MW DMA unused */ 1959 mode = drvp->PIO_mode; 1960 } else { 1961 /* use Multiword DMA */ 1962 drvp->drive_flags &= ~DRIVE_UDMA; 1963 /* mode = min(pio, dma+2) */ 1964 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1965 mode = drvp->PIO_mode; 1966 else 1967 mode = drvp->DMA_mode + 2; 1968 } 1969 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1970 1971 pio: /* setup PIO mode */ 1972 if (mode <= 2) { 1973 drvp->DMA_mode = 0; 1974 drvp->PIO_mode = 0; 1975 mode = 0; 1976 } else { 1977 drvp->PIO_mode = mode; 1978 drvp->DMA_mode = mode - 2; 1979 } 1980 datatim_reg |= 1981 APO_DATATIM_PULSE(chp->channel, drive, 1982 apollo_pio_set[mode]) | 1983 APO_DATATIM_RECOV(chp->channel, drive, 1984 apollo_pio_rec[mode]); 1985 } 1986 if (idedma_ctl != 0) { 1987 /* Add software bits in status register */ 1988 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1989 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1990 idedma_ctl); 1991 } 1992 pciide_print_modes(cp); 1993 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 1994 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 1995 } 1996 1997 void 1998 cmd_channel_map(pa, sc, channel) 1999 struct pci_attach_args *pa; 2000 struct pciide_softc *sc; 2001 int channel; 2002 { 2003 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2004 bus_size_t cmdsize, ctlsize; 2005 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2006 int interface; 2007 2008 /* 2009 * The 0648/0649 can be told to identify as a RAID controller. 2010 * In this case, we have to fake interface 2011 */ 2012 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2013 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2014 PCIIDE_INTERFACE_SETTABLE(1); 2015 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2016 CMD_CONF_DSA1) 2017 interface |= PCIIDE_INTERFACE_PCI(0) | 2018 PCIIDE_INTERFACE_PCI(1); 2019 } else { 2020 interface = PCI_INTERFACE(pa->pa_class); 2021 } 2022 2023 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2024 cp->name = PCIIDE_CHANNEL_NAME(channel); 2025 cp->wdc_channel.channel = channel; 2026 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2027 2028 if (channel > 0) { 2029 cp->wdc_channel.ch_queue = 2030 sc->pciide_channels[0].wdc_channel.ch_queue; 2031 } else { 2032 cp->wdc_channel.ch_queue = 2033 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2034 } 2035 if (cp->wdc_channel.ch_queue == NULL) { 2036 printf("%s %s channel: " 2037 "can't allocate memory for command queue", 2038 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2039 return; 2040 } 2041 2042 printf("%s: %s channel %s to %s mode\n", 2043 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2044 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2045 "configured" : "wired", 2046 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2047 "native-PCI" : "compatibility"); 2048 2049 /* 2050 * with a CMD PCI64x, if we get here, the first channel is enabled: 2051 * there's no way to disable the first channel without disabling 2052 * the whole device 2053 */ 2054 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2055 printf("%s: %s channel ignored (disabled)\n", 2056 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2057 return; 2058 } 2059 2060 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2061 if (cp->hw_ok == 0) 2062 return; 2063 if (channel == 1) { 2064 if (pciide_chan_candisable(cp)) { 2065 ctrl &= ~CMD_CTRL_2PORT; 2066 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2067 CMD_CTRL, ctrl); 2068 } 2069 } 2070 pciide_map_compat_intr(pa, cp, channel, interface); 2071 } 2072 2073 int 2074 cmd_pci_intr(arg) 2075 void *arg; 2076 { 2077 struct pciide_softc *sc = arg; 2078 struct pciide_channel *cp; 2079 struct channel_softc *wdc_cp; 2080 int i, rv, crv; 2081 u_int32_t priirq, secirq; 2082 2083 rv = 0; 2084 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2085 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2086 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2087 cp = &sc->pciide_channels[i]; 2088 wdc_cp = &cp->wdc_channel; 2089 /* If a compat channel skip. */ 2090 if (cp->compat) 2091 continue; 2092 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2093 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2094 crv = wdcintr(wdc_cp); 2095 if (crv == 0) 2096 printf("%s:%d: bogus intr\n", 2097 sc->sc_wdcdev.sc_dev.dv_xname, i); 2098 else 2099 rv = 1; 2100 } 2101 } 2102 return rv; 2103 } 2104 2105 void 2106 cmd_chip_map(sc, pa) 2107 struct pciide_softc *sc; 2108 struct pci_attach_args *pa; 2109 { 2110 int channel; 2111 2112 /* 2113 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2114 * and base adresses registers can be disabled at 2115 * hardware level. In this case, the device is wired 2116 * in compat mode and its first channel is always enabled, 2117 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2118 * In fact, it seems that the first channel of the CMD PCI0640 2119 * can't be disabled. 2120 */ 2121 2122 #ifdef PCIIDE_CMD064x_DISABLE 2123 if (pciide_chipen(sc, pa) == 0) 2124 return; 2125 #endif 2126 2127 printf("%s: hardware does not support DMA\n", 2128 sc->sc_wdcdev.sc_dev.dv_xname); 2129 sc->sc_dma_ok = 0; 2130 2131 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2132 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2133 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2134 2135 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2136 cmd_channel_map(pa, sc, channel); 2137 } 2138 } 2139 2140 void 2141 cmd0643_9_chip_map(sc, pa) 2142 struct pciide_softc *sc; 2143 struct pci_attach_args *pa; 2144 { 2145 struct pciide_channel *cp; 2146 int channel; 2147 2148 /* 2149 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2150 * and base adresses registers can be disabled at 2151 * hardware level. In this case, the device is wired 2152 * in compat mode and its first channel is always enabled, 2153 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2154 * In fact, it seems that the first channel of the CMD PCI0640 2155 * can't be disabled. 2156 */ 2157 2158 #ifdef PCIIDE_CMD064x_DISABLE 2159 if (pciide_chipen(sc, pa) == 0) 2160 return; 2161 #endif 2162 printf("%s: bus-master DMA support present", 2163 sc->sc_wdcdev.sc_dev.dv_xname); 2164 pciide_mapreg_dma(sc, pa); 2165 printf("\n"); 2166 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2167 WDC_CAPABILITY_MODE; 2168 if (sc->sc_dma_ok) { 2169 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2170 switch (sc->sc_pp->ide_product) { 2171 case PCI_PRODUCT_CMDTECH_649: 2172 case PCI_PRODUCT_CMDTECH_648: 2173 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2174 sc->sc_wdcdev.UDMA_cap = 4; 2175 sc->sc_wdcdev.irqack = cmd648_9_irqack; 2176 break; 2177 default: 2178 sc->sc_wdcdev.irqack = pciide_irqack; 2179 } 2180 } 2181 2182 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2183 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2184 sc->sc_wdcdev.PIO_cap = 4; 2185 sc->sc_wdcdev.DMA_cap = 2; 2186 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2187 2188 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2189 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2190 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2191 DEBUG_PROBE); 2192 2193 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2194 cp = &sc->pciide_channels[channel]; 2195 cmd_channel_map(pa, sc, channel); 2196 if (cp->hw_ok == 0) 2197 continue; 2198 cmd0643_9_setup_channel(&cp->wdc_channel); 2199 } 2200 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2201 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2202 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2203 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2204 DEBUG_PROBE); 2205 } 2206 2207 void 2208 cmd0643_9_setup_channel(chp) 2209 struct channel_softc *chp; 2210 { 2211 struct ata_drive_datas *drvp; 2212 u_int8_t tim; 2213 u_int32_t idedma_ctl, udma_reg; 2214 int drive; 2215 struct pciide_channel *cp = (struct pciide_channel*)chp; 2216 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2217 2218 idedma_ctl = 0; 2219 /* setup DMA if needed */ 2220 pciide_channel_dma_setup(cp); 2221 2222 for (drive = 0; drive < 2; drive++) { 2223 drvp = &chp->ch_drive[drive]; 2224 /* If no drive, skip */ 2225 if ((drvp->drive_flags & DRIVE) == 0) 2226 continue; 2227 /* add timing values, setup DMA if needed */ 2228 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2229 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2230 if (drvp->drive_flags & DRIVE_UDMA) { 2231 /* UltraDMA on a 0648 or 0649 */ 2232 udma_reg = pciide_pci_read(sc->sc_pc, 2233 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2234 if (drvp->UDMA_mode > 2 && 2235 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2236 CMD_BICSR) & 2237 CMD_BICSR_80(chp->channel)) == 0) 2238 drvp->UDMA_mode = 2; 2239 if (drvp->UDMA_mode > 2) 2240 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2241 else 2242 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2243 udma_reg |= CMD_UDMATIM_UDMA(drive); 2244 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2245 CMD_UDMATIM_TIM_OFF(drive)); 2246 udma_reg |= 2247 (cmd0648_9_tim_udma[drvp->UDMA_mode] << 2248 CMD_UDMATIM_TIM_OFF(drive)); 2249 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2250 CMD_UDMATIM(chp->channel), udma_reg); 2251 } else { 2252 /* 2253 * use Multiword DMA. 2254 * Timings will be used for both PIO and DMA, 2255 * so adjust DMA mode if needed 2256 * if we have a 0648/9, turn off UDMA 2257 */ 2258 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2259 udma_reg = pciide_pci_read(sc->sc_pc, 2260 sc->sc_tag, 2261 CMD_UDMATIM(chp->channel)); 2262 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2263 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2264 CMD_UDMATIM(chp->channel), 2265 udma_reg); 2266 } 2267 if (drvp->PIO_mode >= 3 && 2268 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2269 drvp->DMA_mode = drvp->PIO_mode - 2; 2270 } 2271 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2272 } 2273 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2274 } 2275 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2276 CMD_DATA_TIM(chp->channel, drive), tim); 2277 } 2278 if (idedma_ctl != 0) { 2279 /* Add software bits in status register */ 2280 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2281 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2282 idedma_ctl); 2283 } 2284 pciide_print_modes(cp); 2285 } 2286 2287 void 2288 cmd648_9_irqack(chp) 2289 struct channel_softc *chp; 2290 { 2291 u_int32_t priirq, secirq; 2292 struct pciide_channel *cp = (struct pciide_channel*)chp; 2293 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2294 2295 if (chp->channel == 0) { 2296 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2297 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2298 } else { 2299 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2300 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2301 } 2302 pciide_irqack(chp); 2303 } 2304 2305 void 2306 cy693_chip_map(sc, pa) 2307 struct pciide_softc *sc; 2308 struct pci_attach_args *pa; 2309 { 2310 struct pciide_channel *cp; 2311 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2312 bus_size_t cmdsize, ctlsize; 2313 2314 if (pciide_chipen(sc, pa) == 0) 2315 return; 2316 /* 2317 * this chip has 2 PCI IDE functions, one for primary and one for 2318 * secondary. So we need to call pciide_mapregs_compat() with 2319 * the real channel 2320 */ 2321 if (pa->pa_function == 1) { 2322 sc->sc_cy_compatchan = 0; 2323 } else if (pa->pa_function == 2) { 2324 sc->sc_cy_compatchan = 1; 2325 } else { 2326 printf("%s: unexpected PCI function %d\n", 2327 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2328 return; 2329 } 2330 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2331 printf("%s: bus-master DMA support present", 2332 sc->sc_wdcdev.sc_dev.dv_xname); 2333 pciide_mapreg_dma(sc, pa); 2334 } else { 2335 printf("%s: hardware does not support DMA", 2336 sc->sc_wdcdev.sc_dev.dv_xname); 2337 sc->sc_dma_ok = 0; 2338 } 2339 printf("\n"); 2340 2341 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2342 if (sc->sc_cy_handle == NULL) { 2343 printf("%s: unable to map hyperCache control registers\n", 2344 sc->sc_wdcdev.sc_dev.dv_xname); 2345 sc->sc_dma_ok = 0; 2346 } 2347 2348 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2349 WDC_CAPABILITY_MODE; 2350 if (sc->sc_dma_ok) { 2351 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2352 sc->sc_wdcdev.irqack = pciide_irqack; 2353 } 2354 sc->sc_wdcdev.PIO_cap = 4; 2355 sc->sc_wdcdev.DMA_cap = 2; 2356 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2357 2358 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2359 sc->sc_wdcdev.nchannels = 1; 2360 2361 /* Only one channel for this chip; if we are here it's enabled */ 2362 cp = &sc->pciide_channels[0]; 2363 sc->wdc_chanarray[0] = &cp->wdc_channel; 2364 cp->name = PCIIDE_CHANNEL_NAME(0); 2365 cp->wdc_channel.channel = 0; 2366 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2367 cp->wdc_channel.ch_queue = 2368 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2369 if (cp->wdc_channel.ch_queue == NULL) { 2370 printf("%s primary channel: " 2371 "can't allocate memory for command queue", 2372 sc->sc_wdcdev.sc_dev.dv_xname); 2373 return; 2374 } 2375 printf("%s: primary channel %s to ", 2376 sc->sc_wdcdev.sc_dev.dv_xname, 2377 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2378 "configured" : "wired"); 2379 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2380 printf("native-PCI"); 2381 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2382 pciide_pci_intr); 2383 } else { 2384 printf("compatibility"); 2385 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2386 &cmdsize, &ctlsize); 2387 } 2388 printf(" mode\n"); 2389 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2390 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2391 wdcattach(&cp->wdc_channel); 2392 if (pciide_chan_candisable(cp)) { 2393 pci_conf_write(sc->sc_pc, sc->sc_tag, 2394 PCI_COMMAND_STATUS_REG, 0); 2395 } 2396 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2397 if (cp->hw_ok == 0) 2398 return; 2399 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2400 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2401 cy693_setup_channel(&cp->wdc_channel); 2402 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2403 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2404 } 2405 2406 void 2407 cy693_setup_channel(chp) 2408 struct channel_softc *chp; 2409 { 2410 struct ata_drive_datas *drvp; 2411 int drive; 2412 u_int32_t cy_cmd_ctrl; 2413 u_int32_t idedma_ctl; 2414 struct pciide_channel *cp = (struct pciide_channel*)chp; 2415 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2416 int dma_mode = -1; 2417 2418 cy_cmd_ctrl = idedma_ctl = 0; 2419 2420 /* setup DMA if needed */ 2421 pciide_channel_dma_setup(cp); 2422 2423 for (drive = 0; drive < 2; drive++) { 2424 drvp = &chp->ch_drive[drive]; 2425 /* If no drive, skip */ 2426 if ((drvp->drive_flags & DRIVE) == 0) 2427 continue; 2428 /* add timing values, setup DMA if needed */ 2429 if (drvp->drive_flags & DRIVE_DMA) { 2430 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2431 /* use Multiword DMA */ 2432 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2433 dma_mode = drvp->DMA_mode; 2434 } 2435 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2436 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2437 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2438 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2439 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2440 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2441 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2442 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2443 } 2444 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2445 chp->ch_drive[0].DMA_mode = dma_mode; 2446 chp->ch_drive[1].DMA_mode = dma_mode; 2447 2448 if (dma_mode == -1) 2449 dma_mode = 0; 2450 2451 if (sc->sc_cy_handle != NULL) { 2452 /* Note: `multiple' is implied. */ 2453 cy82c693_write(sc->sc_cy_handle, 2454 (sc->sc_cy_compatchan == 0) ? 2455 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2456 } 2457 2458 pciide_print_modes(cp); 2459 2460 if (idedma_ctl != 0) { 2461 /* Add software bits in status register */ 2462 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2463 IDEDMA_CTL, idedma_ctl); 2464 } 2465 } 2466 2467 void 2468 sis_chip_map(sc, pa) 2469 struct pciide_softc *sc; 2470 struct pci_attach_args *pa; 2471 { 2472 struct pciide_channel *cp; 2473 int channel; 2474 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2475 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2476 pcireg_t rev = PCI_REVISION(pa->pa_class); 2477 bus_size_t cmdsize, ctlsize; 2478 2479 if (pciide_chipen(sc, pa) == 0) 2480 return; 2481 printf("%s: bus-master DMA support present", 2482 sc->sc_wdcdev.sc_dev.dv_xname); 2483 pciide_mapreg_dma(sc, pa); 2484 printf("\n"); 2485 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2486 WDC_CAPABILITY_MODE; 2487 if (sc->sc_dma_ok) { 2488 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2489 sc->sc_wdcdev.irqack = pciide_irqack; 2490 if (rev >= 0xd0) 2491 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2492 } 2493 2494 sc->sc_wdcdev.PIO_cap = 4; 2495 sc->sc_wdcdev.DMA_cap = 2; 2496 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2497 sc->sc_wdcdev.UDMA_cap = 2; 2498 sc->sc_wdcdev.set_modes = sis_setup_channel; 2499 2500 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2501 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2502 2503 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2504 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2505 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2506 2507 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2508 cp = &sc->pciide_channels[channel]; 2509 if (pciide_chansetup(sc, channel, interface) == 0) 2510 continue; 2511 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2512 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2513 printf("%s: %s channel ignored (disabled)\n", 2514 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2515 continue; 2516 } 2517 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2518 pciide_pci_intr); 2519 if (cp->hw_ok == 0) 2520 continue; 2521 if (pciide_chan_candisable(cp)) { 2522 if (channel == 0) 2523 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2524 else 2525 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2526 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2527 sis_ctr0); 2528 } 2529 pciide_map_compat_intr(pa, cp, channel, interface); 2530 if (cp->hw_ok == 0) 2531 continue; 2532 sis_setup_channel(&cp->wdc_channel); 2533 } 2534 } 2535 2536 void 2537 sis_setup_channel(chp) 2538 struct channel_softc *chp; 2539 { 2540 struct ata_drive_datas *drvp; 2541 int drive; 2542 u_int32_t sis_tim; 2543 u_int32_t idedma_ctl; 2544 struct pciide_channel *cp = (struct pciide_channel*)chp; 2545 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2546 2547 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2548 "channel %d 0x%x\n", chp->channel, 2549 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2550 DEBUG_PROBE); 2551 sis_tim = 0; 2552 idedma_ctl = 0; 2553 /* setup DMA if needed */ 2554 pciide_channel_dma_setup(cp); 2555 2556 for (drive = 0; drive < 2; drive++) { 2557 drvp = &chp->ch_drive[drive]; 2558 /* If no drive, skip */ 2559 if ((drvp->drive_flags & DRIVE) == 0) 2560 continue; 2561 /* add timing values, setup DMA if needed */ 2562 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2563 (drvp->drive_flags & DRIVE_UDMA) == 0) 2564 goto pio; 2565 2566 if (drvp->drive_flags & DRIVE_UDMA) { 2567 /* use Ultra/DMA */ 2568 drvp->drive_flags &= ~DRIVE_DMA; 2569 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2570 SIS_TIM_UDMA_TIME_OFF(drive); 2571 sis_tim |= SIS_TIM_UDMA_EN(drive); 2572 } else { 2573 /* 2574 * use Multiword DMA 2575 * Timings will be used for both PIO and DMA, 2576 * so adjust DMA mode if needed 2577 */ 2578 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2579 drvp->PIO_mode = drvp->DMA_mode + 2; 2580 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2581 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2582 drvp->PIO_mode - 2 : 0; 2583 if (drvp->DMA_mode == 0) 2584 drvp->PIO_mode = 0; 2585 } 2586 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2587 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2588 SIS_TIM_ACT_OFF(drive); 2589 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2590 SIS_TIM_REC_OFF(drive); 2591 } 2592 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2593 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2594 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2595 if (idedma_ctl != 0) { 2596 /* Add software bits in status register */ 2597 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2598 IDEDMA_CTL, idedma_ctl); 2599 } 2600 pciide_print_modes(cp); 2601 } 2602 2603 void 2604 acer_chip_map(sc, pa) 2605 struct pciide_softc *sc; 2606 struct pci_attach_args *pa; 2607 { 2608 struct pciide_channel *cp; 2609 int channel; 2610 pcireg_t cr, interface; 2611 bus_size_t cmdsize, ctlsize; 2612 2613 if (pciide_chipen(sc, pa) == 0) 2614 return; 2615 printf("%s: bus-master DMA support present", 2616 sc->sc_wdcdev.sc_dev.dv_xname); 2617 pciide_mapreg_dma(sc, pa); 2618 printf("\n"); 2619 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2620 WDC_CAPABILITY_MODE; 2621 if (sc->sc_dma_ok) { 2622 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2623 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2624 sc->sc_wdcdev.irqack = pciide_irqack; 2625 } 2626 2627 sc->sc_wdcdev.PIO_cap = 4; 2628 sc->sc_wdcdev.DMA_cap = 2; 2629 sc->sc_wdcdev.UDMA_cap = 2; 2630 sc->sc_wdcdev.set_modes = acer_setup_channel; 2631 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2632 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2633 2634 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2635 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2636 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2637 2638 /* Enable "microsoft register bits" R/W. */ 2639 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2640 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2641 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2642 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2643 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2644 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2645 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2646 ~ACER_CHANSTATUSREGS_RO); 2647 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2648 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2649 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2650 /* Don't use cr, re-read the real register content instead */ 2651 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2652 PCI_CLASS_REG)); 2653 2654 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2655 cp = &sc->pciide_channels[channel]; 2656 if (pciide_chansetup(sc, channel, interface) == 0) 2657 continue; 2658 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2659 printf("%s: %s channel ignored (disabled)\n", 2660 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2661 continue; 2662 } 2663 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2664 acer_pci_intr); 2665 if (cp->hw_ok == 0) 2666 continue; 2667 if (pciide_chan_candisable(cp)) { 2668 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2669 pci_conf_write(sc->sc_pc, sc->sc_tag, 2670 PCI_CLASS_REG, cr); 2671 } 2672 pciide_map_compat_intr(pa, cp, channel, interface); 2673 acer_setup_channel(&cp->wdc_channel); 2674 } 2675 } 2676 2677 void 2678 acer_setup_channel(chp) 2679 struct channel_softc *chp; 2680 { 2681 struct ata_drive_datas *drvp; 2682 int drive; 2683 u_int32_t acer_fifo_udma; 2684 u_int32_t idedma_ctl; 2685 struct pciide_channel *cp = (struct pciide_channel*)chp; 2686 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2687 2688 idedma_ctl = 0; 2689 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2690 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2691 acer_fifo_udma), DEBUG_PROBE); 2692 /* setup DMA if needed */ 2693 pciide_channel_dma_setup(cp); 2694 2695 for (drive = 0; drive < 2; drive++) { 2696 drvp = &chp->ch_drive[drive]; 2697 /* If no drive, skip */ 2698 if ((drvp->drive_flags & DRIVE) == 0) 2699 continue; 2700 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2701 "channel %d drive %d 0x%x\n", chp->channel, drive, 2702 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2703 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2704 /* clear FIFO/DMA mode */ 2705 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2706 ACER_UDMA_EN(chp->channel, drive) | 2707 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2708 2709 /* add timing values, setup DMA if needed */ 2710 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2711 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2712 acer_fifo_udma |= 2713 ACER_FTH_OPL(chp->channel, drive, 0x1); 2714 goto pio; 2715 } 2716 2717 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2718 if (drvp->drive_flags & DRIVE_UDMA) { 2719 /* use Ultra/DMA */ 2720 drvp->drive_flags &= ~DRIVE_DMA; 2721 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2722 acer_fifo_udma |= 2723 ACER_UDMA_TIM(chp->channel, drive, 2724 acer_udma[drvp->UDMA_mode]); 2725 } else { 2726 /* 2727 * use Multiword DMA 2728 * Timings will be used for both PIO and DMA, 2729 * so adjust DMA mode if needed 2730 */ 2731 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2732 drvp->PIO_mode = drvp->DMA_mode + 2; 2733 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2734 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2735 drvp->PIO_mode - 2 : 0; 2736 if (drvp->DMA_mode == 0) 2737 drvp->PIO_mode = 0; 2738 } 2739 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2740 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2741 ACER_IDETIM(chp->channel, drive), 2742 acer_pio[drvp->PIO_mode]); 2743 } 2744 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2745 acer_fifo_udma), DEBUG_PROBE); 2746 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2747 if (idedma_ctl != 0) { 2748 /* Add software bits in status register */ 2749 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2750 IDEDMA_CTL, idedma_ctl); 2751 } 2752 pciide_print_modes(cp); 2753 } 2754 2755 int 2756 acer_pci_intr(arg) 2757 void *arg; 2758 { 2759 struct pciide_softc *sc = arg; 2760 struct pciide_channel *cp; 2761 struct channel_softc *wdc_cp; 2762 int i, rv, crv; 2763 u_int32_t chids; 2764 2765 rv = 0; 2766 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2767 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2768 cp = &sc->pciide_channels[i]; 2769 wdc_cp = &cp->wdc_channel; 2770 /* If a compat channel skip. */ 2771 if (cp->compat) 2772 continue; 2773 if (chids & ACER_CHIDS_INT(i)) { 2774 crv = wdcintr(wdc_cp); 2775 if (crv == 0) 2776 printf("%s:%d: bogus intr\n", 2777 sc->sc_wdcdev.sc_dev.dv_xname, i); 2778 else 2779 rv = 1; 2780 } 2781 } 2782 return rv; 2783 } 2784 2785 void 2786 hpt_chip_map(sc, pa) 2787 struct pciide_softc *sc; 2788 struct pci_attach_args *pa; 2789 { 2790 struct pciide_channel *cp; 2791 int i, compatchan, revision; 2792 pcireg_t interface; 2793 bus_size_t cmdsize, ctlsize; 2794 2795 if (pciide_chipen(sc, pa) == 0) 2796 return; 2797 revision = PCI_REVISION(pa->pa_class); 2798 2799 /* 2800 * when the chip is in native mode it identifies itself as a 2801 * 'misc mass storage'. Fake interface in this case. 2802 */ 2803 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2804 interface = PCI_INTERFACE(pa->pa_class); 2805 } else { 2806 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2807 PCIIDE_INTERFACE_PCI(0); 2808 if (revision == HPT370_REV) 2809 interface |= PCIIDE_INTERFACE_PCI(1); 2810 } 2811 2812 printf("%s: bus-master DMA support present", 2813 sc->sc_wdcdev.sc_dev.dv_xname); 2814 pciide_mapreg_dma(sc, pa); 2815 printf("\n"); 2816 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2817 WDC_CAPABILITY_MODE; 2818 if (sc->sc_dma_ok) { 2819 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2820 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2821 sc->sc_wdcdev.irqack = pciide_irqack; 2822 } 2823 sc->sc_wdcdev.PIO_cap = 4; 2824 sc->sc_wdcdev.DMA_cap = 2; 2825 sc->sc_wdcdev.UDMA_cap = 4; 2826 2827 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2828 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2829 sc->sc_wdcdev.nchannels = (revision == HPT366_REV) ? 1 : 2; 2830 if (revision == HPT366_REV) { 2831 /* 2832 * The 366 has 2 PCI IDE functions, one for primary and one 2833 * for secondary. So we need to call pciide_mapregs_compat() 2834 * with the real channel 2835 */ 2836 if (pa->pa_function == 0) { 2837 compatchan = 0; 2838 } else if (pa->pa_function == 1) { 2839 compatchan = 1; 2840 } else { 2841 printf("%s: unexpected PCI function %d\n", 2842 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2843 return; 2844 } 2845 sc->sc_wdcdev.nchannels = 1; 2846 } else { 2847 sc->sc_wdcdev.nchannels = 2; 2848 } 2849 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2850 cp = &sc->pciide_channels[i]; 2851 if (sc->sc_wdcdev.nchannels > 1) { 2852 compatchan = i; 2853 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2854 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2855 printf("%s: %s channel ignored (disabled)\n", 2856 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2857 continue; 2858 } 2859 } 2860 if (pciide_chansetup(sc, i, interface) == 0) 2861 continue; 2862 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2863 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2864 &ctlsize, hpt_pci_intr); 2865 } else { 2866 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2867 &cmdsize, &ctlsize); 2868 } 2869 if (cp->hw_ok == 0) 2870 return; 2871 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2872 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2873 wdcattach(&cp->wdc_channel); 2874 hpt_setup_channel(&cp->wdc_channel); 2875 } 2876 2877 return; 2878 } 2879 2880 2881 void 2882 hpt_setup_channel(chp) 2883 struct channel_softc *chp; 2884 { 2885 struct ata_drive_datas *drvp; 2886 int drive; 2887 int cable; 2888 u_int32_t before, after; 2889 u_int32_t idedma_ctl; 2890 struct pciide_channel *cp = (struct pciide_channel*)chp; 2891 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2892 2893 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 2894 2895 /* setup DMA if needed */ 2896 pciide_channel_dma_setup(cp); 2897 2898 idedma_ctl = 0; 2899 2900 /* Per drive settings */ 2901 for (drive = 0; drive < 2; drive++) { 2902 drvp = &chp->ch_drive[drive]; 2903 /* If no drive, skip */ 2904 if ((drvp->drive_flags & DRIVE) == 0) 2905 continue; 2906 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 2907 HPT_IDETIM(chp->channel, drive)); 2908 2909 /* add timing values, setup DMA if needed */ 2910 if (drvp->drive_flags & DRIVE_UDMA) { 2911 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 2912 drvp->UDMA_mode > 2) 2913 drvp->UDMA_mode = 2; 2914 after = (sc->sc_wdcdev.nchannels == 2) ? 2915 hpt370_udma[drvp->UDMA_mode] : 2916 hpt366_udma[drvp->UDMA_mode]; 2917 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2918 } else if (drvp->drive_flags & DRIVE_DMA) { 2919 /* 2920 * use Multiword DMA. 2921 * Timings will be used for both PIO and DMA, so adjust 2922 * DMA mode if needed 2923 */ 2924 if (drvp->PIO_mode >= 3 && 2925 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2926 drvp->DMA_mode = drvp->PIO_mode - 2; 2927 } 2928 after = (sc->sc_wdcdev.nchannels == 2) ? 2929 hpt370_dma[drvp->DMA_mode] : 2930 hpt366_dma[drvp->DMA_mode]; 2931 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2932 } else { 2933 /* PIO only */ 2934 after = (sc->sc_wdcdev.nchannels == 2) ? 2935 hpt370_pio[drvp->PIO_mode] : 2936 hpt366_pio[drvp->PIO_mode]; 2937 } 2938 pci_conf_write(sc->sc_pc, sc->sc_tag, 2939 HPT_IDETIM(chp->channel, drive), after); 2940 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 2941 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 2942 after, before), DEBUG_PROBE); 2943 } 2944 if (idedma_ctl != 0) { 2945 /* Add software bits in status register */ 2946 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2947 IDEDMA_CTL, idedma_ctl); 2948 } 2949 pciide_print_modes(cp); 2950 } 2951 2952 int 2953 hpt_pci_intr(arg) 2954 void *arg; 2955 { 2956 struct pciide_softc *sc = arg; 2957 struct pciide_channel *cp; 2958 struct channel_softc *wdc_cp; 2959 int rv = 0; 2960 int dmastat, i, crv; 2961 2962 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2963 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2964 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 2965 if((dmastat & IDEDMA_CTL_INTR) == 0) 2966 continue; 2967 cp = &sc->pciide_channels[i]; 2968 wdc_cp = &cp->wdc_channel; 2969 crv = wdcintr(wdc_cp); 2970 if (crv == 0) { 2971 printf("%s:%d: bogus intr\n", 2972 sc->sc_wdcdev.sc_dev.dv_xname, i); 2973 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2974 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 2975 } else 2976 rv = 1; 2977 } 2978 return rv; 2979 } 2980 2981 2982 /* A macro to test product */ 2983 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 2984 2985 void 2986 pdc202xx_chip_map(sc, pa) 2987 struct pciide_softc *sc; 2988 struct pci_attach_args *pa; 2989 { 2990 struct pciide_channel *cp; 2991 int channel; 2992 pcireg_t interface, st, mode; 2993 bus_size_t cmdsize, ctlsize; 2994 2995 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 2996 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 2997 DEBUG_PROBE); 2998 if (pciide_chipen(sc, pa) == 0) 2999 return; 3000 3001 /* turn off RAID mode */ 3002 st &= ~PDC2xx_STATE_IDERAID; 3003 3004 /* 3005 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3006 * mode. We have to fake interface 3007 */ 3008 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3009 if (st & PDC2xx_STATE_NATIVE) 3010 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3011 3012 printf("%s: bus-master DMA support present", 3013 sc->sc_wdcdev.sc_dev.dv_xname); 3014 pciide_mapreg_dma(sc, pa); 3015 printf("\n"); 3016 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3017 WDC_CAPABILITY_MODE; 3018 if (sc->sc_dma_ok) { 3019 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3020 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3021 sc->sc_wdcdev.irqack = pciide_irqack; 3022 } 3023 sc->sc_wdcdev.PIO_cap = 4; 3024 sc->sc_wdcdev.DMA_cap = 2; 3025 if (PDC_IS_262(sc)) 3026 sc->sc_wdcdev.UDMA_cap = 4; 3027 else 3028 sc->sc_wdcdev.UDMA_cap = 2; 3029 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3030 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3031 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3032 3033 /* setup failsafe defaults */ 3034 mode = 0; 3035 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3036 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3037 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3038 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3039 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3040 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3041 "initial timings 0x%x, now 0x%x\n", channel, 3042 pci_conf_read(sc->sc_pc, sc->sc_tag, 3043 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3044 DEBUG_PROBE); 3045 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3046 mode | PDC2xx_TIM_IORDYp); 3047 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3048 "initial timings 0x%x, now 0x%x\n", channel, 3049 pci_conf_read(sc->sc_pc, sc->sc_tag, 3050 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3051 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3052 mode); 3053 } 3054 3055 mode = PDC2xx_SCR_DMA; 3056 if (PDC_IS_262(sc)) { 3057 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3058 } else { 3059 /* the BIOS set it up this way */ 3060 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3061 } 3062 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3063 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3064 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3065 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3066 DEBUG_PROBE); 3067 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3068 3069 /* controller initial state register is OK even without BIOS */ 3070 /* Set DMA mode to IDE DMA compatibility */ 3071 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3072 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3073 DEBUG_PROBE); 3074 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3075 mode | 0x1); 3076 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3077 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3078 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3079 mode | 0x1); 3080 3081 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3082 cp = &sc->pciide_channels[channel]; 3083 if (pciide_chansetup(sc, channel, interface) == 0) 3084 continue; 3085 if ((st & (PDC_IS_262(sc) ? 3086 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3087 printf("%s: %s channel ignored (disabled)\n", 3088 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3089 continue; 3090 } 3091 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3092 pdc202xx_pci_intr); 3093 if (cp->hw_ok == 0) 3094 continue; 3095 if (pciide_chan_candisable(cp)) 3096 st &= ~(PDC_IS_262(sc) ? 3097 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3098 pciide_map_compat_intr(pa, cp, channel, interface); 3099 pdc202xx_setup_channel(&cp->wdc_channel); 3100 } 3101 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3102 DEBUG_PROBE); 3103 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3104 return; 3105 } 3106 3107 void 3108 pdc202xx_setup_channel(chp) 3109 struct channel_softc *chp; 3110 { 3111 struct ata_drive_datas *drvp; 3112 int drive; 3113 pcireg_t mode, st; 3114 u_int32_t idedma_ctl, scr, atapi; 3115 struct pciide_channel *cp = (struct pciide_channel*)chp; 3116 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3117 int channel = chp->channel; 3118 3119 /* setup DMA if needed */ 3120 pciide_channel_dma_setup(cp); 3121 3122 idedma_ctl = 0; 3123 3124 /* Per channel settings */ 3125 if (PDC_IS_262(sc)) { 3126 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3127 PDC262_U66); 3128 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3129 /* Trimm UDMA mode */ 3130 if ((st & PDC262_STATE_80P(channel)) != 0 || 3131 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3132 chp->ch_drive[0].UDMA_mode <= 2) || 3133 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3134 chp->ch_drive[1].UDMA_mode <= 2)) { 3135 if (chp->ch_drive[0].UDMA_mode > 2) 3136 chp->ch_drive[0].UDMA_mode = 2; 3137 if (chp->ch_drive[1].UDMA_mode > 2) 3138 chp->ch_drive[1].UDMA_mode = 2; 3139 } 3140 /* Set U66 if needed */ 3141 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3142 chp->ch_drive[0].UDMA_mode > 2) || 3143 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3144 chp->ch_drive[1].UDMA_mode > 2)) 3145 scr |= PDC262_U66_EN(channel); 3146 else 3147 scr &= ~PDC262_U66_EN(channel); 3148 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3149 PDC262_U66, scr); 3150 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3151 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3152 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3153 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3154 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3155 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3156 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3157 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3158 atapi = 0; 3159 else 3160 atapi = PDC262_ATAPI_UDMA; 3161 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3162 PDC262_ATAPI(channel), atapi); 3163 } 3164 } 3165 for (drive = 0; drive < 2; drive++) { 3166 drvp = &chp->ch_drive[drive]; 3167 /* If no drive, skip */ 3168 if ((drvp->drive_flags & DRIVE) == 0) 3169 continue; 3170 mode = 0; 3171 if (drvp->drive_flags & DRIVE_UDMA) { 3172 mode = PDC2xx_TIM_SET_MB(mode, 3173 pdc2xx_udma_mb[drvp->UDMA_mode]); 3174 mode = PDC2xx_TIM_SET_MC(mode, 3175 pdc2xx_udma_mc[drvp->UDMA_mode]); 3176 drvp->drive_flags &= ~DRIVE_DMA; 3177 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3178 } else if (drvp->drive_flags & DRIVE_DMA) { 3179 mode = PDC2xx_TIM_SET_MB(mode, 3180 pdc2xx_dma_mb[drvp->DMA_mode]); 3181 mode = PDC2xx_TIM_SET_MC(mode, 3182 pdc2xx_dma_mc[drvp->DMA_mode]); 3183 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3184 } else { 3185 mode = PDC2xx_TIM_SET_MB(mode, 3186 pdc2xx_dma_mb[0]); 3187 mode = PDC2xx_TIM_SET_MC(mode, 3188 pdc2xx_dma_mc[0]); 3189 } 3190 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3191 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3192 if (drvp->drive_flags & DRIVE_ATA) 3193 mode |= PDC2xx_TIM_PRE; 3194 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3195 if (drvp->PIO_mode >= 3) { 3196 mode |= PDC2xx_TIM_IORDY; 3197 if (drive == 0) 3198 mode |= PDC2xx_TIM_IORDYp; 3199 } 3200 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3201 "timings 0x%x\n", 3202 sc->sc_wdcdev.sc_dev.dv_xname, 3203 chp->channel, drive, mode), DEBUG_PROBE); 3204 pci_conf_write(sc->sc_pc, sc->sc_tag, 3205 PDC2xx_TIM(chp->channel, drive), mode); 3206 } 3207 if (idedma_ctl != 0) { 3208 /* Add software bits in status register */ 3209 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3210 IDEDMA_CTL, idedma_ctl); 3211 } 3212 pciide_print_modes(cp); 3213 } 3214 3215 int 3216 pdc202xx_pci_intr(arg) 3217 void *arg; 3218 { 3219 struct pciide_softc *sc = arg; 3220 struct pciide_channel *cp; 3221 struct channel_softc *wdc_cp; 3222 int i, rv, crv; 3223 u_int32_t scr; 3224 3225 rv = 0; 3226 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3227 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3228 cp = &sc->pciide_channels[i]; 3229 wdc_cp = &cp->wdc_channel; 3230 /* If a compat channel skip. */ 3231 if (cp->compat) 3232 continue; 3233 if (scr & PDC2xx_SCR_INT(i)) { 3234 crv = wdcintr(wdc_cp); 3235 if (crv == 0) 3236 printf("%s:%d: bogus intr\n", 3237 sc->sc_wdcdev.sc_dev.dv_xname, i); 3238 else 3239 rv = 1; 3240 } 3241 } 3242 return rv; 3243 } 3244 3245 void 3246 opti_chip_map(sc, pa) 3247 struct pciide_softc *sc; 3248 struct pci_attach_args *pa; 3249 { 3250 struct pciide_channel *cp; 3251 bus_size_t cmdsize, ctlsize; 3252 pcireg_t interface; 3253 u_int8_t init_ctrl; 3254 int channel; 3255 3256 if (pciide_chipen(sc, pa) == 0) 3257 return; 3258 printf("%s: bus-master DMA support present", 3259 sc->sc_wdcdev.sc_dev.dv_xname); 3260 pciide_mapreg_dma(sc, pa); 3261 printf("\n"); 3262 3263 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3264 WDC_CAPABILITY_MODE; 3265 sc->sc_wdcdev.PIO_cap = 4; 3266 if (sc->sc_dma_ok) { 3267 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3268 sc->sc_wdcdev.irqack = pciide_irqack; 3269 sc->sc_wdcdev.DMA_cap = 2; 3270 } 3271 sc->sc_wdcdev.set_modes = opti_setup_channel; 3272 3273 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3274 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3275 3276 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3277 OPTI_REG_INIT_CONTROL); 3278 3279 interface = PCI_INTERFACE(pa->pa_class); 3280 3281 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3282 cp = &sc->pciide_channels[channel]; 3283 if (pciide_chansetup(sc, channel, interface) == 0) 3284 continue; 3285 if (channel == 1 && 3286 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3287 printf("%s: %s channel ignored (disabled)\n", 3288 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3289 continue; 3290 } 3291 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3292 pciide_pci_intr); 3293 if (cp->hw_ok == 0) 3294 continue; 3295 pciide_map_compat_intr(pa, cp, channel, interface); 3296 if (cp->hw_ok == 0) 3297 continue; 3298 opti_setup_channel(&cp->wdc_channel); 3299 } 3300 } 3301 3302 void 3303 opti_setup_channel(chp) 3304 struct channel_softc *chp; 3305 { 3306 struct ata_drive_datas *drvp; 3307 struct pciide_channel *cp = (struct pciide_channel*)chp; 3308 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3309 int drive, spd; 3310 int mode[2]; 3311 u_int8_t rv, mr; 3312 3313 /* 3314 * The `Delay' and `Address Setup Time' fields of the 3315 * Miscellaneous Register are always zero initially. 3316 */ 3317 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3318 mr &= ~(OPTI_MISC_DELAY_MASK | 3319 OPTI_MISC_ADDR_SETUP_MASK | 3320 OPTI_MISC_INDEX_MASK); 3321 3322 /* Prime the control register before setting timing values */ 3323 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3324 3325 /* Determine the clockrate of the PCIbus the chip is attached to */ 3326 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3327 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3328 3329 /* setup DMA if needed */ 3330 pciide_channel_dma_setup(cp); 3331 3332 for (drive = 0; drive < 2; drive++) { 3333 drvp = &chp->ch_drive[drive]; 3334 /* If no drive, skip */ 3335 if ((drvp->drive_flags & DRIVE) == 0) { 3336 mode[drive] = -1; 3337 continue; 3338 } 3339 3340 if ((drvp->drive_flags & DRIVE_DMA)) { 3341 /* 3342 * Timings will be used for both PIO and DMA, 3343 * so adjust DMA mode if needed 3344 */ 3345 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3346 drvp->PIO_mode = drvp->DMA_mode + 2; 3347 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3348 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3349 drvp->PIO_mode - 2 : 0; 3350 if (drvp->DMA_mode == 0) 3351 drvp->PIO_mode = 0; 3352 3353 mode[drive] = drvp->DMA_mode + 5; 3354 } else 3355 mode[drive] = drvp->PIO_mode; 3356 3357 if (drive && mode[0] >= 0 && 3358 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3359 /* 3360 * Can't have two drives using different values 3361 * for `Address Setup Time'. 3362 * Slow down the faster drive to compensate. 3363 */ 3364 int d = (opti_tim_as[spd][mode[0]] > 3365 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3366 3367 mode[d] = mode[1-d]; 3368 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3369 chp->ch_drive[d].DMA_mode = 0; 3370 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3371 } 3372 } 3373 3374 for (drive = 0; drive < 2; drive++) { 3375 int m; 3376 if ((m = mode[drive]) < 0) 3377 continue; 3378 3379 /* Set the Address Setup Time and select appropriate index */ 3380 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3381 rv |= OPTI_MISC_INDEX(drive); 3382 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3383 3384 /* Set the pulse width and recovery timing parameters */ 3385 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3386 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3387 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3388 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3389 3390 /* Set the Enhanced Mode register appropriately */ 3391 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3392 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3393 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3394 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3395 } 3396 3397 /* Finally, enable the timings */ 3398 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3399 3400 pciide_print_modes(cp); 3401 } 3402
Indexes created Wed Sep 24 05:09:52 GMT 2025