pciide.c revision 1.83
1 /* $NetBSD: pciide.c,v 1.83 2000/08/02 20:23:45 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 #include <dev/pci/pciidereg.h> 105 #include <dev/pci/pciidevar.h> 106 #include <dev/pci/pciide_piix_reg.h> 107 #include <dev/pci/pciide_amd_reg.h> 108 #include <dev/pci/pciide_apollo_reg.h> 109 #include <dev/pci/pciide_cmd_reg.h> 110 #include <dev/pci/pciide_cy693_reg.h> 111 #include <dev/pci/pciide_sis_reg.h> 112 #include <dev/pci/pciide_acer_reg.h> 113 #include <dev/pci/pciide_pdc202xx_reg.h> 114 #include <dev/pci/pciide_opti_reg.h> 115 #include <dev/pci/pciide_hpt_reg.h> 116 #include <dev/pci/cy82c693var.h> 117 118 /* inlines for reading/writing 8-bit PCI registers */ 119 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 120 int)); 121 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 122 int, u_int8_t)); 123 124 static __inline u_int8_t 125 pciide_pci_read(pc, pa, reg) 126 pci_chipset_tag_t pc; 127 pcitag_t pa; 128 int reg; 129 { 130 131 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 132 ((reg & 0x03) * 8) & 0xff); 133 } 134 135 static __inline void 136 pciide_pci_write(pc, pa, reg, val) 137 pci_chipset_tag_t pc; 138 pcitag_t pa; 139 int reg; 140 u_int8_t val; 141 { 142 pcireg_t pcival; 143 144 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 145 pcival &= ~(0xff << ((reg & 0x03) * 8)); 146 pcival |= (val << ((reg & 0x03) * 8)); 147 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 148 } 149 150 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 151 152 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 153 void piix_setup_channel __P((struct channel_softc*)); 154 void piix3_4_setup_channel __P((struct channel_softc*)); 155 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 156 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 157 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 158 159 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 160 void amd756_setup_channel __P((struct channel_softc*)); 161 162 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 163 void apollo_setup_channel __P((struct channel_softc*)); 164 165 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 166 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 167 void cmd0643_9_setup_channel __P((struct channel_softc*)); 168 void cmd_channel_map __P((struct pci_attach_args *, 169 struct pciide_softc *, int)); 170 int cmd_pci_intr __P((void *)); 171 void cmd646_9_irqack __P((struct channel_softc *)); 172 173 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 174 void cy693_setup_channel __P((struct channel_softc*)); 175 176 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 177 void sis_setup_channel __P((struct channel_softc*)); 178 179 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 180 void acer_setup_channel __P((struct channel_softc*)); 181 int acer_pci_intr __P((void *)); 182 183 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 184 void pdc202xx_setup_channel __P((struct channel_softc*)); 185 int pdc202xx_pci_intr __P((void *)); 186 187 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 188 void opti_setup_channel __P((struct channel_softc*)); 189 190 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 191 void hpt_setup_channel __P((struct channel_softc*)); 192 int hpt_pci_intr __P((void *)); 193 194 void pciide_channel_dma_setup __P((struct pciide_channel *)); 195 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 196 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 197 void pciide_dma_start __P((void*, int, int)); 198 int pciide_dma_finish __P((void*, int, int, int)); 199 void pciide_irqack __P((struct channel_softc *)); 200 void pciide_print_modes __P((struct pciide_channel *)); 201 202 struct pciide_product_desc { 203 u_int32_t ide_product; 204 int ide_flags; 205 const char *ide_name; 206 /* map and setup chip, probe drives */ 207 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 208 }; 209 210 /* Flags for ide_flags */ 211 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 212 213 /* Default product description for devices not known from this controller */ 214 const struct pciide_product_desc default_product_desc = { 215 0, 216 0, 217 "Generic PCI IDE controller", 218 default_chip_map, 219 }; 220 221 const struct pciide_product_desc pciide_intel_products[] = { 222 { PCI_PRODUCT_INTEL_82092AA, 223 0, 224 "Intel 82092AA IDE controller", 225 default_chip_map, 226 }, 227 { PCI_PRODUCT_INTEL_82371FB_IDE, 228 0, 229 "Intel 82371FB IDE controller (PIIX)", 230 piix_chip_map, 231 }, 232 { PCI_PRODUCT_INTEL_82371SB_IDE, 233 0, 234 "Intel 82371SB IDE Interface (PIIX3)", 235 piix_chip_map, 236 }, 237 { PCI_PRODUCT_INTEL_82371AB_IDE, 238 0, 239 "Intel 82371AB IDE controller (PIIX4)", 240 piix_chip_map, 241 }, 242 { PCI_PRODUCT_INTEL_82801AA_IDE, 243 0, 244 "Intel 82801AA IDE Controller (ICH)", 245 piix_chip_map, 246 }, 247 { PCI_PRODUCT_INTEL_82801AB_IDE, 248 0, 249 "Intel 82801AB IDE Controller (ICH0)", 250 piix_chip_map, 251 }, 252 { 0, 253 0, 254 NULL, 255 } 256 }; 257 258 const struct pciide_product_desc pciide_amd_products[] = { 259 { PCI_PRODUCT_AMD_PBC756_IDE, 260 0, 261 "Advanced Micro Devices AMD756 IDE Controller", 262 amd756_chip_map 263 }, 264 { 0, 265 0, 266 NULL, 267 } 268 }; 269 270 const struct pciide_product_desc pciide_cmd_products[] = { 271 { PCI_PRODUCT_CMDTECH_640, 272 0, 273 "CMD Technology PCI0640", 274 cmd_chip_map 275 }, 276 { PCI_PRODUCT_CMDTECH_643, 277 0, 278 "CMD Technology PCI0643", 279 cmd0643_9_chip_map, 280 }, 281 { PCI_PRODUCT_CMDTECH_646, 282 0, 283 "CMD Technology PCI0646", 284 cmd0643_9_chip_map, 285 }, 286 { PCI_PRODUCT_CMDTECH_648, 287 IDE_PCI_CLASS_OVERRIDE, 288 "CMD Technology PCI0648", 289 cmd0643_9_chip_map, 290 }, 291 { PCI_PRODUCT_CMDTECH_649, 292 IDE_PCI_CLASS_OVERRIDE, 293 "CMD Technology PCI0649", 294 cmd0643_9_chip_map, 295 }, 296 { 0, 297 0, 298 NULL, 299 } 300 }; 301 302 const struct pciide_product_desc pciide_via_products[] = { 303 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 304 0, 305 "VIA Tech VT82C586 IDE Controller", 306 apollo_chip_map, 307 }, 308 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 309 0, 310 "VIA Tech VT82C586A IDE Controller", 311 apollo_chip_map, 312 }, 313 { 0, 314 0, 315 NULL, 316 } 317 }; 318 319 const struct pciide_product_desc pciide_cypress_products[] = { 320 { PCI_PRODUCT_CONTAQ_82C693, 321 0, 322 "Cypress 82C693 IDE Controller", 323 cy693_chip_map, 324 }, 325 { 0, 326 0, 327 NULL, 328 } 329 }; 330 331 const struct pciide_product_desc pciide_sis_products[] = { 332 { PCI_PRODUCT_SIS_5597_IDE, 333 0, 334 "Silicon Integrated System 5597/5598 IDE controller", 335 sis_chip_map, 336 }, 337 { 0, 338 0, 339 NULL, 340 } 341 }; 342 343 const struct pciide_product_desc pciide_acer_products[] = { 344 { PCI_PRODUCT_ALI_M5229, 345 0, 346 "Acer Labs M5229 UDMA IDE Controller", 347 acer_chip_map, 348 }, 349 { 0, 350 0, 351 NULL, 352 } 353 }; 354 355 const struct pciide_product_desc pciide_promise_products[] = { 356 { PCI_PRODUCT_PROMISE_ULTRA33, 357 IDE_PCI_CLASS_OVERRIDE, 358 "Promise Ultra33/ATA Bus Master IDE Accelerator", 359 pdc202xx_chip_map, 360 }, 361 { PCI_PRODUCT_PROMISE_ULTRA66, 362 IDE_PCI_CLASS_OVERRIDE, 363 "Promise Ultra66/ATA Bus Master IDE Accelerator", 364 pdc202xx_chip_map, 365 }, 366 { PCI_PRODUCT_PROMISE_ULTRA100, 367 IDE_PCI_CLASS_OVERRIDE, 368 "Promise Ultra100/ATA Bus Master IDE Accelerator", 369 pdc202xx_chip_map, 370 }, 371 { 0, 372 0, 373 NULL, 374 } 375 }; 376 377 const struct pciide_product_desc pciide_opti_products[] = { 378 { PCI_PRODUCT_OPTI_82C621, 379 0, 380 "OPTi 82c621 PCI IDE controller", 381 opti_chip_map, 382 }, 383 { PCI_PRODUCT_OPTI_82C568, 384 0, 385 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 386 opti_chip_map, 387 }, 388 { PCI_PRODUCT_OPTI_82D568, 389 0, 390 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 391 opti_chip_map, 392 }, 393 { 0, 394 0, 395 NULL, 396 } 397 }; 398 399 const struct pciide_product_desc pciide_triones_products[] = { 400 { PCI_PRODUCT_TRIONES_HPT366, 401 IDE_PCI_CLASS_OVERRIDE, 402 "Triones/Highpoint HPT366/370 IDE Controller", 403 hpt_chip_map, 404 }, 405 { 0, 406 0, 407 NULL, 408 } 409 }; 410 411 struct pciide_vendor_desc { 412 u_int32_t ide_vendor; 413 const struct pciide_product_desc *ide_products; 414 }; 415 416 const struct pciide_vendor_desc pciide_vendors[] = { 417 { PCI_VENDOR_INTEL, pciide_intel_products }, 418 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 419 { PCI_VENDOR_VIATECH, pciide_via_products }, 420 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 421 { PCI_VENDOR_SIS, pciide_sis_products }, 422 { PCI_VENDOR_ALI, pciide_acer_products }, 423 { PCI_VENDOR_PROMISE, pciide_promise_products }, 424 { PCI_VENDOR_AMD, pciide_amd_products }, 425 { PCI_VENDOR_OPTI, pciide_opti_products }, 426 { PCI_VENDOR_TRIONES, pciide_triones_products }, 427 { 0, NULL } 428 }; 429 430 /* options passed via the 'flags' config keyword */ 431 #define PCIIDE_OPTIONS_DMA 0x01 432 433 int pciide_match __P((struct device *, struct cfdata *, void *)); 434 void pciide_attach __P((struct device *, struct device *, void *)); 435 436 struct cfattach pciide_ca = { 437 sizeof(struct pciide_softc), pciide_match, pciide_attach 438 }; 439 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 440 int pciide_mapregs_compat __P(( struct pci_attach_args *, 441 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 442 int pciide_mapregs_native __P((struct pci_attach_args *, 443 struct pciide_channel *, bus_size_t *, bus_size_t *, 444 int (*pci_intr) __P((void *)))); 445 void pciide_mapreg_dma __P((struct pciide_softc *, 446 struct pci_attach_args *)); 447 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 448 void pciide_mapchan __P((struct pci_attach_args *, 449 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 450 int (*pci_intr) __P((void *)))); 451 int pciide_chan_candisable __P((struct pciide_channel *)); 452 void pciide_map_compat_intr __P(( struct pci_attach_args *, 453 struct pciide_channel *, int, int)); 454 int pciide_print __P((void *, const char *pnp)); 455 int pciide_compat_intr __P((void *)); 456 int pciide_pci_intr __P((void *)); 457 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 458 459 const struct pciide_product_desc * 460 pciide_lookup_product(id) 461 u_int32_t id; 462 { 463 const struct pciide_product_desc *pp; 464 const struct pciide_vendor_desc *vp; 465 466 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 467 if (PCI_VENDOR(id) == vp->ide_vendor) 468 break; 469 470 if ((pp = vp->ide_products) == NULL) 471 return NULL; 472 473 for (; pp->ide_name != NULL; pp++) 474 if (PCI_PRODUCT(id) == pp->ide_product) 475 break; 476 477 if (pp->ide_name == NULL) 478 return NULL; 479 return pp; 480 } 481 482 int 483 pciide_match(parent, match, aux) 484 struct device *parent; 485 struct cfdata *match; 486 void *aux; 487 { 488 struct pci_attach_args *pa = aux; 489 const struct pciide_product_desc *pp; 490 491 /* 492 * Check the ID register to see that it's a PCI IDE controller. 493 * If it is, we assume that we can deal with it; it _should_ 494 * work in a standardized way... 495 */ 496 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 497 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 498 return (1); 499 } 500 501 /* 502 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 503 * controllers. Let see if we can deal with it anyway. 504 */ 505 pp = pciide_lookup_product(pa->pa_id); 506 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 507 return (1); 508 } 509 510 return (0); 511 } 512 513 void 514 pciide_attach(parent, self, aux) 515 struct device *parent, *self; 516 void *aux; 517 { 518 struct pci_attach_args *pa = aux; 519 pci_chipset_tag_t pc = pa->pa_pc; 520 pcitag_t tag = pa->pa_tag; 521 struct pciide_softc *sc = (struct pciide_softc *)self; 522 pcireg_t csr; 523 char devinfo[256]; 524 const char *displaydev; 525 526 sc->sc_pp = pciide_lookup_product(pa->pa_id); 527 if (sc->sc_pp == NULL) { 528 sc->sc_pp = &default_product_desc; 529 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 530 displaydev = devinfo; 531 } else 532 displaydev = sc->sc_pp->ide_name; 533 534 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 535 536 sc->sc_pc = pa->pa_pc; 537 sc->sc_tag = pa->pa_tag; 538 #ifdef WDCDEBUG 539 if (wdcdebug_pciide_mask & DEBUG_PROBE) 540 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 541 #endif 542 sc->sc_pp->chip_map(sc, pa); 543 544 if (sc->sc_dma_ok) { 545 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 546 csr |= PCI_COMMAND_MASTER_ENABLE; 547 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 548 } 549 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 550 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 551 } 552 553 /* tell wether the chip is enabled or not */ 554 int 555 pciide_chipen(sc, pa) 556 struct pciide_softc *sc; 557 struct pci_attach_args *pa; 558 { 559 pcireg_t csr; 560 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 561 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 562 PCI_COMMAND_STATUS_REG); 563 printf("%s: device disabled (at %s)\n", 564 sc->sc_wdcdev.sc_dev.dv_xname, 565 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 566 "device" : "bridge"); 567 return 0; 568 } 569 return 1; 570 } 571 572 int 573 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 574 struct pci_attach_args *pa; 575 struct pciide_channel *cp; 576 int compatchan; 577 bus_size_t *cmdsizep, *ctlsizep; 578 { 579 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 580 struct channel_softc *wdc_cp = &cp->wdc_channel; 581 582 cp->compat = 1; 583 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 584 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 585 586 wdc_cp->cmd_iot = pa->pa_iot; 587 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 588 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 589 printf("%s: couldn't map %s channel cmd regs\n", 590 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 591 return (0); 592 } 593 594 wdc_cp->ctl_iot = pa->pa_iot; 595 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 596 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 597 printf("%s: couldn't map %s channel ctl regs\n", 598 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 599 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 600 PCIIDE_COMPAT_CMD_SIZE); 601 return (0); 602 } 603 604 return (1); 605 } 606 607 int 608 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 609 struct pci_attach_args * pa; 610 struct pciide_channel *cp; 611 bus_size_t *cmdsizep, *ctlsizep; 612 int (*pci_intr) __P((void *)); 613 { 614 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 615 struct channel_softc *wdc_cp = &cp->wdc_channel; 616 const char *intrstr; 617 pci_intr_handle_t intrhandle; 618 619 cp->compat = 0; 620 621 if (sc->sc_pci_ih == NULL) { 622 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 623 pa->pa_intrline, &intrhandle) != 0) { 624 printf("%s: couldn't map native-PCI interrupt\n", 625 sc->sc_wdcdev.sc_dev.dv_xname); 626 return 0; 627 } 628 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 629 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 630 intrhandle, IPL_BIO, pci_intr, sc); 631 if (sc->sc_pci_ih != NULL) { 632 printf("%s: using %s for native-PCI interrupt\n", 633 sc->sc_wdcdev.sc_dev.dv_xname, 634 intrstr ? intrstr : "unknown interrupt"); 635 } else { 636 printf("%s: couldn't establish native-PCI interrupt", 637 sc->sc_wdcdev.sc_dev.dv_xname); 638 if (intrstr != NULL) 639 printf(" at %s", intrstr); 640 printf("\n"); 641 return 0; 642 } 643 } 644 cp->ih = sc->sc_pci_ih; 645 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 646 PCI_MAPREG_TYPE_IO, 0, 647 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 648 printf("%s: couldn't map %s channel cmd regs\n", 649 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 650 return 0; 651 } 652 653 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 654 PCI_MAPREG_TYPE_IO, 0, 655 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 656 printf("%s: couldn't map %s channel ctl regs\n", 657 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 658 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 659 return 0; 660 } 661 return (1); 662 } 663 664 void 665 pciide_mapreg_dma(sc, pa) 666 struct pciide_softc *sc; 667 struct pci_attach_args *pa; 668 { 669 pcireg_t maptype; 670 671 /* 672 * Map DMA registers 673 * 674 * Note that sc_dma_ok is the right variable to test to see if 675 * DMA can be done. If the interface doesn't support DMA, 676 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 677 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 678 * non-zero if the interface supports DMA and the registers 679 * could be mapped. 680 * 681 * XXX Note that despite the fact that the Bus Master IDE specs 682 * XXX say that "The bus master IDE function uses 16 bytes of IO 683 * XXX space," some controllers (at least the United 684 * XXX Microelectronics UM8886BF) place it in memory space. 685 */ 686 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 687 PCIIDE_REG_BUS_MASTER_DMA); 688 689 switch (maptype) { 690 case PCI_MAPREG_TYPE_IO: 691 case PCI_MAPREG_MEM_TYPE_32BIT: 692 sc->sc_dma_ok = (pci_mapreg_map(pa, 693 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 694 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 695 sc->sc_dmat = pa->pa_dmat; 696 if (sc->sc_dma_ok == 0) { 697 printf(", but unused (couldn't map registers)"); 698 } else { 699 sc->sc_wdcdev.dma_arg = sc; 700 sc->sc_wdcdev.dma_init = pciide_dma_init; 701 sc->sc_wdcdev.dma_start = pciide_dma_start; 702 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 703 } 704 break; 705 706 default: 707 sc->sc_dma_ok = 0; 708 printf(", but unsupported register maptype (0x%x)", maptype); 709 } 710 } 711 712 int 713 pciide_compat_intr(arg) 714 void *arg; 715 { 716 struct pciide_channel *cp = arg; 717 718 #ifdef DIAGNOSTIC 719 /* should only be called for a compat channel */ 720 if (cp->compat == 0) 721 panic("pciide compat intr called for non-compat chan %p\n", cp); 722 #endif 723 return (wdcintr(&cp->wdc_channel)); 724 } 725 726 int 727 pciide_pci_intr(arg) 728 void *arg; 729 { 730 struct pciide_softc *sc = arg; 731 struct pciide_channel *cp; 732 struct channel_softc *wdc_cp; 733 int i, rv, crv; 734 735 rv = 0; 736 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 737 cp = &sc->pciide_channels[i]; 738 wdc_cp = &cp->wdc_channel; 739 740 /* If a compat channel skip. */ 741 if (cp->compat) 742 continue; 743 /* if this channel not waiting for intr, skip */ 744 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 745 continue; 746 747 crv = wdcintr(wdc_cp); 748 if (crv == 0) 749 ; /* leave rv alone */ 750 else if (crv == 1) 751 rv = 1; /* claim the intr */ 752 else if (rv == 0) /* crv should be -1 in this case */ 753 rv = crv; /* if we've done no better, take it */ 754 } 755 return (rv); 756 } 757 758 void 759 pciide_channel_dma_setup(cp) 760 struct pciide_channel *cp; 761 { 762 int drive; 763 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 764 struct ata_drive_datas *drvp; 765 766 for (drive = 0; drive < 2; drive++) { 767 drvp = &cp->wdc_channel.ch_drive[drive]; 768 /* If no drive, skip */ 769 if ((drvp->drive_flags & DRIVE) == 0) 770 continue; 771 /* setup DMA if needed */ 772 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 773 (drvp->drive_flags & DRIVE_UDMA) == 0) || 774 sc->sc_dma_ok == 0) { 775 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 776 continue; 777 } 778 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 779 != 0) { 780 /* Abort DMA setup */ 781 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 782 continue; 783 } 784 } 785 } 786 787 int 788 pciide_dma_table_setup(sc, channel, drive) 789 struct pciide_softc *sc; 790 int channel, drive; 791 { 792 bus_dma_segment_t seg; 793 int error, rseg; 794 const bus_size_t dma_table_size = 795 sizeof(struct idedma_table) * NIDEDMA_TABLES; 796 struct pciide_dma_maps *dma_maps = 797 &sc->pciide_channels[channel].dma_maps[drive]; 798 799 /* If table was already allocated, just return */ 800 if (dma_maps->dma_table) 801 return 0; 802 803 /* Allocate memory for the DMA tables and map it */ 804 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 805 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 806 BUS_DMA_NOWAIT)) != 0) { 807 printf("%s:%d: unable to allocate table DMA for " 808 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 809 channel, drive, error); 810 return error; 811 } 812 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 813 dma_table_size, 814 (caddr_t *)&dma_maps->dma_table, 815 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 816 printf("%s:%d: unable to map table DMA for" 817 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 818 channel, drive, error); 819 return error; 820 } 821 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 822 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 823 seg.ds_addr), DEBUG_PROBE); 824 825 /* Create and load table DMA map for this disk */ 826 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 827 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 828 &dma_maps->dmamap_table)) != 0) { 829 printf("%s:%d: unable to create table DMA map for " 830 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 831 channel, drive, error); 832 return error; 833 } 834 if ((error = bus_dmamap_load(sc->sc_dmat, 835 dma_maps->dmamap_table, 836 dma_maps->dma_table, 837 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 838 printf("%s:%d: unable to load table DMA map for " 839 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 840 channel, drive, error); 841 return error; 842 } 843 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 844 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 845 /* Create a xfer DMA map for this drive */ 846 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 847 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 848 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 849 &dma_maps->dmamap_xfer)) != 0) { 850 printf("%s:%d: unable to create xfer DMA map for " 851 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 852 channel, drive, error); 853 return error; 854 } 855 return 0; 856 } 857 858 int 859 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 860 void *v; 861 int channel, drive; 862 void *databuf; 863 size_t datalen; 864 int flags; 865 { 866 struct pciide_softc *sc = v; 867 int error, seg; 868 struct pciide_dma_maps *dma_maps = 869 &sc->pciide_channels[channel].dma_maps[drive]; 870 871 error = bus_dmamap_load(sc->sc_dmat, 872 dma_maps->dmamap_xfer, 873 databuf, datalen, NULL, BUS_DMA_NOWAIT); 874 if (error) { 875 printf("%s:%d: unable to load xfer DMA map for" 876 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 877 channel, drive, error); 878 return error; 879 } 880 881 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 882 dma_maps->dmamap_xfer->dm_mapsize, 883 (flags & WDC_DMA_READ) ? 884 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 885 886 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 887 #ifdef DIAGNOSTIC 888 /* A segment must not cross a 64k boundary */ 889 { 890 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 891 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 892 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 893 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 894 printf("pciide_dma: segment %d physical addr 0x%lx" 895 " len 0x%lx not properly aligned\n", 896 seg, phys, len); 897 panic("pciide_dma: buf align"); 898 } 899 } 900 #endif 901 dma_maps->dma_table[seg].base_addr = 902 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 903 dma_maps->dma_table[seg].byte_count = 904 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 905 IDEDMA_BYTE_COUNT_MASK); 906 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 907 seg, le32toh(dma_maps->dma_table[seg].byte_count), 908 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 909 910 } 911 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 912 htole32(IDEDMA_BYTE_COUNT_EOT); 913 914 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 915 dma_maps->dmamap_table->dm_mapsize, 916 BUS_DMASYNC_PREWRITE); 917 918 /* Maps are ready. Start DMA function */ 919 #ifdef DIAGNOSTIC 920 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 921 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 922 dma_maps->dmamap_table->dm_segs[0].ds_addr); 923 panic("pciide_dma_init: table align"); 924 } 925 #endif 926 927 /* Clear status bits */ 928 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 929 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 930 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 931 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 932 /* Write table addr */ 933 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 934 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 935 dma_maps->dmamap_table->dm_segs[0].ds_addr); 936 /* set read/write */ 937 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 938 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 939 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 940 /* remember flags */ 941 dma_maps->dma_flags = flags; 942 return 0; 943 } 944 945 void 946 pciide_dma_start(v, channel, drive) 947 void *v; 948 int channel, drive; 949 { 950 struct pciide_softc *sc = v; 951 952 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 953 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 954 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 955 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 956 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 957 } 958 959 int 960 pciide_dma_finish(v, channel, drive, force) 961 void *v; 962 int channel, drive; 963 int force; 964 { 965 struct pciide_softc *sc = v; 966 u_int8_t status; 967 int error = 0; 968 struct pciide_dma_maps *dma_maps = 969 &sc->pciide_channels[channel].dma_maps[drive]; 970 971 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 972 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 973 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 974 DEBUG_XFERS); 975 976 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 977 return WDC_DMAST_NOIRQ; 978 979 /* stop DMA channel */ 980 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 981 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 982 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 983 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 984 985 /* Unload the map of the data buffer */ 986 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 987 dma_maps->dmamap_xfer->dm_mapsize, 988 (dma_maps->dma_flags & WDC_DMA_READ) ? 989 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 990 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 991 992 if ((status & IDEDMA_CTL_ERR) != 0) { 993 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 994 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 995 error |= WDC_DMAST_ERR; 996 } 997 998 if ((status & IDEDMA_CTL_INTR) == 0) { 999 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1000 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1001 drive, status); 1002 error |= WDC_DMAST_NOIRQ; 1003 } 1004 1005 if ((status & IDEDMA_CTL_ACT) != 0) { 1006 /* data underrun, may be a valid condition for ATAPI */ 1007 error |= WDC_DMAST_UNDER; 1008 } 1009 return error; 1010 } 1011 1012 void 1013 pciide_irqack(chp) 1014 struct channel_softc *chp; 1015 { 1016 struct pciide_channel *cp = (struct pciide_channel*)chp; 1017 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1018 1019 /* clear status bits in IDE DMA registers */ 1020 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1021 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1022 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1023 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1024 } 1025 1026 /* some common code used by several chip_map */ 1027 int 1028 pciide_chansetup(sc, channel, interface) 1029 struct pciide_softc *sc; 1030 int channel; 1031 pcireg_t interface; 1032 { 1033 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1034 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1035 cp->name = PCIIDE_CHANNEL_NAME(channel); 1036 cp->wdc_channel.channel = channel; 1037 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1038 cp->wdc_channel.ch_queue = 1039 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1040 if (cp->wdc_channel.ch_queue == NULL) { 1041 printf("%s %s channel: " 1042 "can't allocate memory for command queue", 1043 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1044 return 0; 1045 } 1046 printf("%s: %s channel %s to %s mode\n", 1047 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1048 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1049 "configured" : "wired", 1050 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1051 "native-PCI" : "compatibility"); 1052 return 1; 1053 } 1054 1055 /* some common code used by several chip channel_map */ 1056 void 1057 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1058 struct pci_attach_args *pa; 1059 struct pciide_channel *cp; 1060 pcireg_t interface; 1061 bus_size_t *cmdsizep, *ctlsizep; 1062 int (*pci_intr) __P((void *)); 1063 { 1064 struct channel_softc *wdc_cp = &cp->wdc_channel; 1065 1066 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1067 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1068 pci_intr); 1069 else 1070 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1071 wdc_cp->channel, cmdsizep, ctlsizep); 1072 1073 if (cp->hw_ok == 0) 1074 return; 1075 wdc_cp->data32iot = wdc_cp->cmd_iot; 1076 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1077 wdcattach(wdc_cp); 1078 } 1079 1080 /* 1081 * Generic code to call to know if a channel can be disabled. Return 1 1082 * if channel can be disabled, 0 if not 1083 */ 1084 int 1085 pciide_chan_candisable(cp) 1086 struct pciide_channel *cp; 1087 { 1088 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1089 struct channel_softc *wdc_cp = &cp->wdc_channel; 1090 1091 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1092 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1093 printf("%s: disabling %s channel (no drives)\n", 1094 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1095 cp->hw_ok = 0; 1096 return 1; 1097 } 1098 return 0; 1099 } 1100 1101 /* 1102 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1103 * Set hw_ok=0 on failure 1104 */ 1105 void 1106 pciide_map_compat_intr(pa, cp, compatchan, interface) 1107 struct pci_attach_args *pa; 1108 struct pciide_channel *cp; 1109 int compatchan, interface; 1110 { 1111 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1112 struct channel_softc *wdc_cp = &cp->wdc_channel; 1113 1114 if (cp->hw_ok == 0) 1115 return; 1116 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1117 return; 1118 1119 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1120 pa, compatchan, pciide_compat_intr, cp); 1121 if (cp->ih == NULL) { 1122 printf("%s: no compatibility interrupt for use by %s " 1123 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1124 cp->hw_ok = 0; 1125 } 1126 } 1127 1128 void 1129 pciide_print_modes(cp) 1130 struct pciide_channel *cp; 1131 { 1132 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1133 int drive; 1134 struct channel_softc *chp; 1135 struct ata_drive_datas *drvp; 1136 1137 chp = &cp->wdc_channel; 1138 for (drive = 0; drive < 2; drive++) { 1139 drvp = &chp->ch_drive[drive]; 1140 if ((drvp->drive_flags & DRIVE) == 0) 1141 continue; 1142 printf("%s(%s:%d:%d): using PIO mode %d", 1143 drvp->drv_softc->dv_xname, 1144 sc->sc_wdcdev.sc_dev.dv_xname, 1145 chp->channel, drive, drvp->PIO_mode); 1146 if (drvp->drive_flags & DRIVE_DMA) 1147 printf(", DMA mode %d", drvp->DMA_mode); 1148 if (drvp->drive_flags & DRIVE_UDMA) 1149 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1150 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1151 printf(" (using DMA data transfers)"); 1152 printf("\n"); 1153 } 1154 } 1155 1156 void 1157 default_chip_map(sc, pa) 1158 struct pciide_softc *sc; 1159 struct pci_attach_args *pa; 1160 { 1161 struct pciide_channel *cp; 1162 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1163 pcireg_t csr; 1164 int channel, drive; 1165 struct ata_drive_datas *drvp; 1166 u_int8_t idedma_ctl; 1167 bus_size_t cmdsize, ctlsize; 1168 char *failreason; 1169 1170 if (pciide_chipen(sc, pa) == 0) 1171 return; 1172 1173 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1174 printf("%s: bus-master DMA support present", 1175 sc->sc_wdcdev.sc_dev.dv_xname); 1176 if (sc->sc_pp == &default_product_desc && 1177 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1178 PCIIDE_OPTIONS_DMA) == 0) { 1179 printf(", but unused (no driver support)"); 1180 sc->sc_dma_ok = 0; 1181 } else { 1182 pciide_mapreg_dma(sc, pa); 1183 if (sc->sc_dma_ok != 0) 1184 printf(", used without full driver " 1185 "support"); 1186 } 1187 } else { 1188 printf("%s: hardware does not support DMA", 1189 sc->sc_wdcdev.sc_dev.dv_xname); 1190 sc->sc_dma_ok = 0; 1191 } 1192 printf("\n"); 1193 if (sc->sc_dma_ok) { 1194 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1195 sc->sc_wdcdev.irqack = pciide_irqack; 1196 } 1197 sc->sc_wdcdev.PIO_cap = 0; 1198 sc->sc_wdcdev.DMA_cap = 0; 1199 1200 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1201 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1202 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1203 1204 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1205 cp = &sc->pciide_channels[channel]; 1206 if (pciide_chansetup(sc, channel, interface) == 0) 1207 continue; 1208 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1209 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1210 &ctlsize, pciide_pci_intr); 1211 } else { 1212 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1213 channel, &cmdsize, &ctlsize); 1214 } 1215 if (cp->hw_ok == 0) 1216 continue; 1217 /* 1218 * Check to see if something appears to be there. 1219 */ 1220 failreason = NULL; 1221 if (!wdcprobe(&cp->wdc_channel)) { 1222 failreason = "not responding; disabled or no drives?"; 1223 goto next; 1224 } 1225 /* 1226 * Now, make sure it's actually attributable to this PCI IDE 1227 * channel by trying to access the channel again while the 1228 * PCI IDE controller's I/O space is disabled. (If the 1229 * channel no longer appears to be there, it belongs to 1230 * this controller.) YUCK! 1231 */ 1232 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1233 PCI_COMMAND_STATUS_REG); 1234 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1235 csr & ~PCI_COMMAND_IO_ENABLE); 1236 if (wdcprobe(&cp->wdc_channel)) 1237 failreason = "other hardware responding at addresses"; 1238 pci_conf_write(sc->sc_pc, sc->sc_tag, 1239 PCI_COMMAND_STATUS_REG, csr); 1240 next: 1241 if (failreason) { 1242 printf("%s: %s channel ignored (%s)\n", 1243 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1244 failreason); 1245 cp->hw_ok = 0; 1246 bus_space_unmap(cp->wdc_channel.cmd_iot, 1247 cp->wdc_channel.cmd_ioh, cmdsize); 1248 bus_space_unmap(cp->wdc_channel.ctl_iot, 1249 cp->wdc_channel.ctl_ioh, ctlsize); 1250 } else { 1251 pciide_map_compat_intr(pa, cp, channel, interface); 1252 } 1253 if (cp->hw_ok) { 1254 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1255 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1256 wdcattach(&cp->wdc_channel); 1257 } 1258 } 1259 1260 if (sc->sc_dma_ok == 0) 1261 return; 1262 1263 /* Allocate DMA maps */ 1264 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1265 idedma_ctl = 0; 1266 cp = &sc->pciide_channels[channel]; 1267 for (drive = 0; drive < 2; drive++) { 1268 drvp = &cp->wdc_channel.ch_drive[drive]; 1269 /* If no drive, skip */ 1270 if ((drvp->drive_flags & DRIVE) == 0) 1271 continue; 1272 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1273 continue; 1274 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1275 /* Abort DMA setup */ 1276 printf("%s:%d:%d: can't allocate DMA maps, " 1277 "using PIO transfers\n", 1278 sc->sc_wdcdev.sc_dev.dv_xname, 1279 channel, drive); 1280 drvp->drive_flags &= ~DRIVE_DMA; 1281 } 1282 printf("%s:%d:%d: using DMA data transfers\n", 1283 sc->sc_wdcdev.sc_dev.dv_xname, 1284 channel, drive); 1285 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1286 } 1287 if (idedma_ctl != 0) { 1288 /* Add software bits in status register */ 1289 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1290 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1291 idedma_ctl); 1292 } 1293 } 1294 } 1295 1296 void 1297 piix_chip_map(sc, pa) 1298 struct pciide_softc *sc; 1299 struct pci_attach_args *pa; 1300 { 1301 struct pciide_channel *cp; 1302 int channel; 1303 u_int32_t idetim; 1304 bus_size_t cmdsize, ctlsize; 1305 1306 if (pciide_chipen(sc, pa) == 0) 1307 return; 1308 1309 printf("%s: bus-master DMA support present", 1310 sc->sc_wdcdev.sc_dev.dv_xname); 1311 pciide_mapreg_dma(sc, pa); 1312 printf("\n"); 1313 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1314 WDC_CAPABILITY_MODE; 1315 if (sc->sc_dma_ok) { 1316 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1317 sc->sc_wdcdev.irqack = pciide_irqack; 1318 switch(sc->sc_pp->ide_product) { 1319 case PCI_PRODUCT_INTEL_82371AB_IDE: 1320 case PCI_PRODUCT_INTEL_82801AA_IDE: 1321 case PCI_PRODUCT_INTEL_82801AB_IDE: 1322 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1323 } 1324 } 1325 sc->sc_wdcdev.PIO_cap = 4; 1326 sc->sc_wdcdev.DMA_cap = 2; 1327 sc->sc_wdcdev.UDMA_cap = 1328 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1329 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1330 sc->sc_wdcdev.set_modes = piix_setup_channel; 1331 else 1332 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1333 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1334 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1335 1336 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1337 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1338 DEBUG_PROBE); 1339 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1340 WDCDEBUG_PRINT((", sidetim=0x%x", 1341 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1342 DEBUG_PROBE); 1343 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1344 WDCDEBUG_PRINT((", udamreg 0x%x", 1345 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1346 DEBUG_PROBE); 1347 } 1348 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1349 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1350 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1351 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1352 DEBUG_PROBE); 1353 } 1354 1355 } 1356 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1357 1358 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1359 cp = &sc->pciide_channels[channel]; 1360 /* PIIX is compat-only */ 1361 if (pciide_chansetup(sc, channel, 0) == 0) 1362 continue; 1363 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1364 if ((PIIX_IDETIM_READ(idetim, channel) & 1365 PIIX_IDETIM_IDE) == 0) { 1366 printf("%s: %s channel ignored (disabled)\n", 1367 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1368 continue; 1369 } 1370 /* PIIX are compat-only pciide devices */ 1371 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1372 if (cp->hw_ok == 0) 1373 continue; 1374 if (pciide_chan_candisable(cp)) { 1375 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1376 channel); 1377 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1378 idetim); 1379 } 1380 pciide_map_compat_intr(pa, cp, channel, 0); 1381 if (cp->hw_ok == 0) 1382 continue; 1383 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1384 } 1385 1386 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1387 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1388 DEBUG_PROBE); 1389 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1390 WDCDEBUG_PRINT((", sidetim=0x%x", 1391 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1392 DEBUG_PROBE); 1393 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1394 WDCDEBUG_PRINT((", udamreg 0x%x", 1395 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1396 DEBUG_PROBE); 1397 } 1398 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1399 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1400 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1401 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1402 DEBUG_PROBE); 1403 } 1404 } 1405 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1406 } 1407 1408 void 1409 piix_setup_channel(chp) 1410 struct channel_softc *chp; 1411 { 1412 u_int8_t mode[2], drive; 1413 u_int32_t oidetim, idetim, idedma_ctl; 1414 struct pciide_channel *cp = (struct pciide_channel*)chp; 1415 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1416 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1417 1418 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1419 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1420 idedma_ctl = 0; 1421 1422 /* set up new idetim: Enable IDE registers decode */ 1423 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1424 chp->channel); 1425 1426 /* setup DMA */ 1427 pciide_channel_dma_setup(cp); 1428 1429 /* 1430 * Here we have to mess up with drives mode: PIIX can't have 1431 * different timings for master and slave drives. 1432 * We need to find the best combination. 1433 */ 1434 1435 /* If both drives supports DMA, take the lower mode */ 1436 if ((drvp[0].drive_flags & DRIVE_DMA) && 1437 (drvp[1].drive_flags & DRIVE_DMA)) { 1438 mode[0] = mode[1] = 1439 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1440 drvp[0].DMA_mode = mode[0]; 1441 drvp[1].DMA_mode = mode[1]; 1442 goto ok; 1443 } 1444 /* 1445 * If only one drive supports DMA, use its mode, and 1446 * put the other one in PIO mode 0 if mode not compatible 1447 */ 1448 if (drvp[0].drive_flags & DRIVE_DMA) { 1449 mode[0] = drvp[0].DMA_mode; 1450 mode[1] = drvp[1].PIO_mode; 1451 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1452 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1453 mode[1] = drvp[1].PIO_mode = 0; 1454 goto ok; 1455 } 1456 if (drvp[1].drive_flags & DRIVE_DMA) { 1457 mode[1] = drvp[1].DMA_mode; 1458 mode[0] = drvp[0].PIO_mode; 1459 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1460 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1461 mode[0] = drvp[0].PIO_mode = 0; 1462 goto ok; 1463 } 1464 /* 1465 * If both drives are not DMA, takes the lower mode, unless 1466 * one of them is PIO mode < 2 1467 */ 1468 if (drvp[0].PIO_mode < 2) { 1469 mode[0] = drvp[0].PIO_mode = 0; 1470 mode[1] = drvp[1].PIO_mode; 1471 } else if (drvp[1].PIO_mode < 2) { 1472 mode[1] = drvp[1].PIO_mode = 0; 1473 mode[0] = drvp[0].PIO_mode; 1474 } else { 1475 mode[0] = mode[1] = 1476 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1477 drvp[0].PIO_mode = mode[0]; 1478 drvp[1].PIO_mode = mode[1]; 1479 } 1480 ok: /* The modes are setup */ 1481 for (drive = 0; drive < 2; drive++) { 1482 if (drvp[drive].drive_flags & DRIVE_DMA) { 1483 idetim |= piix_setup_idetim_timings( 1484 mode[drive], 1, chp->channel); 1485 goto end; 1486 } 1487 } 1488 /* If we are there, none of the drives are DMA */ 1489 if (mode[0] >= 2) 1490 idetim |= piix_setup_idetim_timings( 1491 mode[0], 0, chp->channel); 1492 else 1493 idetim |= piix_setup_idetim_timings( 1494 mode[1], 0, chp->channel); 1495 end: /* 1496 * timing mode is now set up in the controller. Enable 1497 * it per-drive 1498 */ 1499 for (drive = 0; drive < 2; drive++) { 1500 /* If no drive, skip */ 1501 if ((drvp[drive].drive_flags & DRIVE) == 0) 1502 continue; 1503 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1504 if (drvp[drive].drive_flags & DRIVE_DMA) 1505 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1506 } 1507 if (idedma_ctl != 0) { 1508 /* Add software bits in status register */ 1509 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1510 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1511 idedma_ctl); 1512 } 1513 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1514 pciide_print_modes(cp); 1515 } 1516 1517 void 1518 piix3_4_setup_channel(chp) 1519 struct channel_softc *chp; 1520 { 1521 struct ata_drive_datas *drvp; 1522 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1523 struct pciide_channel *cp = (struct pciide_channel*)chp; 1524 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1525 int drive; 1526 int channel = chp->channel; 1527 1528 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1529 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1530 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1531 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1532 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1533 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1534 PIIX_SIDETIM_RTC_MASK(channel)); 1535 1536 idedma_ctl = 0; 1537 /* If channel disabled, no need to go further */ 1538 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1539 return; 1540 /* set up new idetim: Enable IDE registers decode */ 1541 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1542 1543 /* setup DMA if needed */ 1544 pciide_channel_dma_setup(cp); 1545 1546 for (drive = 0; drive < 2; drive++) { 1547 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1548 PIIX_UDMATIM_SET(0x3, channel, drive)); 1549 drvp = &chp->ch_drive[drive]; 1550 /* If no drive, skip */ 1551 if ((drvp->drive_flags & DRIVE) == 0) 1552 continue; 1553 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1554 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1555 goto pio; 1556 1557 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1558 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1559 ideconf |= PIIX_CONFIG_PINGPONG; 1560 } 1561 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1562 /* setup Ultra/66 */ 1563 if (drvp->UDMA_mode > 2 && 1564 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1565 drvp->UDMA_mode = 2; 1566 if (drvp->UDMA_mode > 2) 1567 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1568 else 1569 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1570 } 1571 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1572 (drvp->drive_flags & DRIVE_UDMA)) { 1573 /* use Ultra/DMA */ 1574 drvp->drive_flags &= ~DRIVE_DMA; 1575 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1576 udmareg |= PIIX_UDMATIM_SET( 1577 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1578 } else { 1579 /* use Multiword DMA */ 1580 drvp->drive_flags &= ~DRIVE_UDMA; 1581 if (drive == 0) { 1582 idetim |= piix_setup_idetim_timings( 1583 drvp->DMA_mode, 1, channel); 1584 } else { 1585 sidetim |= piix_setup_sidetim_timings( 1586 drvp->DMA_mode, 1, channel); 1587 idetim =PIIX_IDETIM_SET(idetim, 1588 PIIX_IDETIM_SITRE, channel); 1589 } 1590 } 1591 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1592 1593 pio: /* use PIO mode */ 1594 idetim |= piix_setup_idetim_drvs(drvp); 1595 if (drive == 0) { 1596 idetim |= piix_setup_idetim_timings( 1597 drvp->PIO_mode, 0, channel); 1598 } else { 1599 sidetim |= piix_setup_sidetim_timings( 1600 drvp->PIO_mode, 0, channel); 1601 idetim =PIIX_IDETIM_SET(idetim, 1602 PIIX_IDETIM_SITRE, channel); 1603 } 1604 } 1605 if (idedma_ctl != 0) { 1606 /* Add software bits in status register */ 1607 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1608 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1609 idedma_ctl); 1610 } 1611 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1612 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1613 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1614 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1615 pciide_print_modes(cp); 1616 } 1617 1618 1619 /* setup ISP and RTC fields, based on mode */ 1620 static u_int32_t 1621 piix_setup_idetim_timings(mode, dma, channel) 1622 u_int8_t mode; 1623 u_int8_t dma; 1624 u_int8_t channel; 1625 { 1626 1627 if (dma) 1628 return PIIX_IDETIM_SET(0, 1629 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1630 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1631 channel); 1632 else 1633 return PIIX_IDETIM_SET(0, 1634 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1635 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1636 channel); 1637 } 1638 1639 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1640 static u_int32_t 1641 piix_setup_idetim_drvs(drvp) 1642 struct ata_drive_datas *drvp; 1643 { 1644 u_int32_t ret = 0; 1645 struct channel_softc *chp = drvp->chnl_softc; 1646 u_int8_t channel = chp->channel; 1647 u_int8_t drive = drvp->drive; 1648 1649 /* 1650 * If drive is using UDMA, timings setups are independant 1651 * So just check DMA and PIO here. 1652 */ 1653 if (drvp->drive_flags & DRIVE_DMA) { 1654 /* if mode = DMA mode 0, use compatible timings */ 1655 if ((drvp->drive_flags & DRIVE_DMA) && 1656 drvp->DMA_mode == 0) { 1657 drvp->PIO_mode = 0; 1658 return ret; 1659 } 1660 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1661 /* 1662 * PIO and DMA timings are the same, use fast timings for PIO 1663 * too, else use compat timings. 1664 */ 1665 if ((piix_isp_pio[drvp->PIO_mode] != 1666 piix_isp_dma[drvp->DMA_mode]) || 1667 (piix_rtc_pio[drvp->PIO_mode] != 1668 piix_rtc_dma[drvp->DMA_mode])) 1669 drvp->PIO_mode = 0; 1670 /* if PIO mode <= 2, use compat timings for PIO */ 1671 if (drvp->PIO_mode <= 2) { 1672 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1673 channel); 1674 return ret; 1675 } 1676 } 1677 1678 /* 1679 * Now setup PIO modes. If mode < 2, use compat timings. 1680 * Else enable fast timings. Enable IORDY and prefetch/post 1681 * if PIO mode >= 3. 1682 */ 1683 1684 if (drvp->PIO_mode < 2) 1685 return ret; 1686 1687 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1688 if (drvp->PIO_mode >= 3) { 1689 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1690 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1691 } 1692 return ret; 1693 } 1694 1695 /* setup values in SIDETIM registers, based on mode */ 1696 static u_int32_t 1697 piix_setup_sidetim_timings(mode, dma, channel) 1698 u_int8_t mode; 1699 u_int8_t dma; 1700 u_int8_t channel; 1701 { 1702 if (dma) 1703 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1704 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1705 else 1706 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1707 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1708 } 1709 1710 void 1711 amd756_chip_map(sc, pa) 1712 struct pciide_softc *sc; 1713 struct pci_attach_args *pa; 1714 { 1715 struct pciide_channel *cp; 1716 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1717 int channel; 1718 pcireg_t chanenable; 1719 bus_size_t cmdsize, ctlsize; 1720 1721 if (pciide_chipen(sc, pa) == 0) 1722 return; 1723 printf("%s: bus-master DMA support present", 1724 sc->sc_wdcdev.sc_dev.dv_xname); 1725 pciide_mapreg_dma(sc, pa); 1726 printf("\n"); 1727 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1728 WDC_CAPABILITY_MODE; 1729 if (sc->sc_dma_ok) { 1730 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1731 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1732 sc->sc_wdcdev.irqack = pciide_irqack; 1733 } 1734 sc->sc_wdcdev.PIO_cap = 4; 1735 sc->sc_wdcdev.DMA_cap = 2; 1736 sc->sc_wdcdev.UDMA_cap = 4; 1737 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1738 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1739 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1740 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1741 1742 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1743 DEBUG_PROBE); 1744 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1745 cp = &sc->pciide_channels[channel]; 1746 if (pciide_chansetup(sc, channel, interface) == 0) 1747 continue; 1748 1749 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1750 printf("%s: %s channel ignored (disabled)\n", 1751 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1752 continue; 1753 } 1754 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1755 pciide_pci_intr); 1756 1757 if (pciide_chan_candisable(cp)) 1758 chanenable &= ~AMD756_CHAN_EN(channel); 1759 pciide_map_compat_intr(pa, cp, channel, interface); 1760 if (cp->hw_ok == 0) 1761 continue; 1762 1763 amd756_setup_channel(&cp->wdc_channel); 1764 } 1765 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1766 chanenable); 1767 return; 1768 } 1769 1770 void 1771 amd756_setup_channel(chp) 1772 struct channel_softc *chp; 1773 { 1774 u_int32_t udmatim_reg, datatim_reg; 1775 u_int8_t idedma_ctl; 1776 int mode, drive; 1777 struct ata_drive_datas *drvp; 1778 struct pciide_channel *cp = (struct pciide_channel*)chp; 1779 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1780 #ifndef PCIIDE_AMD756_ENABLEDMA 1781 int rev = PCI_REVISION( 1782 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1783 #endif 1784 1785 idedma_ctl = 0; 1786 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1787 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1788 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1789 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1790 1791 /* setup DMA if needed */ 1792 pciide_channel_dma_setup(cp); 1793 1794 for (drive = 0; drive < 2; drive++) { 1795 drvp = &chp->ch_drive[drive]; 1796 /* If no drive, skip */ 1797 if ((drvp->drive_flags & DRIVE) == 0) 1798 continue; 1799 /* add timing values, setup DMA if needed */ 1800 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1801 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1802 mode = drvp->PIO_mode; 1803 goto pio; 1804 } 1805 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1806 (drvp->drive_flags & DRIVE_UDMA)) { 1807 /* use Ultra/DMA */ 1808 drvp->drive_flags &= ~DRIVE_DMA; 1809 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1810 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1811 AMD756_UDMA_TIME(chp->channel, drive, 1812 amd756_udma_tim[drvp->UDMA_mode]); 1813 /* can use PIO timings, MW DMA unused */ 1814 mode = drvp->PIO_mode; 1815 } else { 1816 /* use Multiword DMA, but only if revision is OK */ 1817 drvp->drive_flags &= ~DRIVE_UDMA; 1818 #ifndef PCIIDE_AMD756_ENABLEDMA 1819 /* 1820 * The workaround doesn't seem to be necessary 1821 * with all drives, so it can be disabled by 1822 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1823 * triggered. 1824 */ 1825 if (AMD756_CHIPREV_DISABLEDMA(rev)) { 1826 printf("%s:%d:%d: multi-word DMA disabled due " 1827 "to chip revision\n", 1828 sc->sc_wdcdev.sc_dev.dv_xname, 1829 chp->channel, drive); 1830 mode = drvp->PIO_mode; 1831 drvp->drive_flags &= ~DRIVE_DMA; 1832 goto pio; 1833 } 1834 #endif 1835 /* mode = min(pio, dma+2) */ 1836 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1837 mode = drvp->PIO_mode; 1838 else 1839 mode = drvp->DMA_mode + 2; 1840 } 1841 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1842 1843 pio: /* setup PIO mode */ 1844 if (mode <= 2) { 1845 drvp->DMA_mode = 0; 1846 drvp->PIO_mode = 0; 1847 mode = 0; 1848 } else { 1849 drvp->PIO_mode = mode; 1850 drvp->DMA_mode = mode - 2; 1851 } 1852 datatim_reg |= 1853 AMD756_DATATIM_PULSE(chp->channel, drive, 1854 amd756_pio_set[mode]) | 1855 AMD756_DATATIM_RECOV(chp->channel, drive, 1856 amd756_pio_rec[mode]); 1857 } 1858 if (idedma_ctl != 0) { 1859 /* Add software bits in status register */ 1860 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1861 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1862 idedma_ctl); 1863 } 1864 pciide_print_modes(cp); 1865 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1866 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1867 } 1868 1869 void 1870 apollo_chip_map(sc, pa) 1871 struct pciide_softc *sc; 1872 struct pci_attach_args *pa; 1873 { 1874 struct pciide_channel *cp; 1875 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1876 int channel; 1877 u_int32_t ideconf; 1878 bus_size_t cmdsize, ctlsize; 1879 1880 if (pciide_chipen(sc, pa) == 0) 1881 return; 1882 printf("%s: bus-master DMA support present", 1883 sc->sc_wdcdev.sc_dev.dv_xname); 1884 pciide_mapreg_dma(sc, pa); 1885 printf("\n"); 1886 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1887 WDC_CAPABILITY_MODE; 1888 if (sc->sc_dma_ok) { 1889 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1890 sc->sc_wdcdev.irqack = pciide_irqack; 1891 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE) 1892 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1893 } 1894 sc->sc_wdcdev.PIO_cap = 4; 1895 sc->sc_wdcdev.DMA_cap = 2; 1896 sc->sc_wdcdev.UDMA_cap = 2; 1897 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1898 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1899 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1900 1901 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1902 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1903 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1904 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1905 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1906 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1907 DEBUG_PROBE); 1908 1909 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1910 cp = &sc->pciide_channels[channel]; 1911 if (pciide_chansetup(sc, channel, interface) == 0) 1912 continue; 1913 1914 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1915 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1916 printf("%s: %s channel ignored (disabled)\n", 1917 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1918 continue; 1919 } 1920 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1921 pciide_pci_intr); 1922 if (cp->hw_ok == 0) 1923 continue; 1924 if (pciide_chan_candisable(cp)) { 1925 ideconf &= ~APO_IDECONF_EN(channel); 1926 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1927 ideconf); 1928 } 1929 pciide_map_compat_intr(pa, cp, channel, interface); 1930 1931 if (cp->hw_ok == 0) 1932 continue; 1933 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1934 } 1935 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1936 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1937 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1938 } 1939 1940 void 1941 apollo_setup_channel(chp) 1942 struct channel_softc *chp; 1943 { 1944 u_int32_t udmatim_reg, datatim_reg; 1945 u_int8_t idedma_ctl; 1946 int mode, drive; 1947 struct ata_drive_datas *drvp; 1948 struct pciide_channel *cp = (struct pciide_channel*)chp; 1949 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1950 1951 idedma_ctl = 0; 1952 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1953 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1954 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1955 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1956 1957 /* setup DMA if needed */ 1958 pciide_channel_dma_setup(cp); 1959 1960 for (drive = 0; drive < 2; drive++) { 1961 drvp = &chp->ch_drive[drive]; 1962 /* If no drive, skip */ 1963 if ((drvp->drive_flags & DRIVE) == 0) 1964 continue; 1965 /* add timing values, setup DMA if needed */ 1966 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1967 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1968 mode = drvp->PIO_mode; 1969 goto pio; 1970 } 1971 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1972 (drvp->drive_flags & DRIVE_UDMA)) { 1973 /* use Ultra/DMA */ 1974 drvp->drive_flags &= ~DRIVE_DMA; 1975 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1976 APO_UDMA_EN_MTH(chp->channel, drive) | 1977 APO_UDMA_TIME(chp->channel, drive, 1978 apollo_udma_tim[drvp->UDMA_mode]); 1979 /* can use PIO timings, MW DMA unused */ 1980 mode = drvp->PIO_mode; 1981 } else { 1982 /* use Multiword DMA */ 1983 drvp->drive_flags &= ~DRIVE_UDMA; 1984 /* mode = min(pio, dma+2) */ 1985 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1986 mode = drvp->PIO_mode; 1987 else 1988 mode = drvp->DMA_mode + 2; 1989 } 1990 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1991 1992 pio: /* setup PIO mode */ 1993 if (mode <= 2) { 1994 drvp->DMA_mode = 0; 1995 drvp->PIO_mode = 0; 1996 mode = 0; 1997 } else { 1998 drvp->PIO_mode = mode; 1999 drvp->DMA_mode = mode - 2; 2000 } 2001 datatim_reg |= 2002 APO_DATATIM_PULSE(chp->channel, drive, 2003 apollo_pio_set[mode]) | 2004 APO_DATATIM_RECOV(chp->channel, drive, 2005 apollo_pio_rec[mode]); 2006 } 2007 if (idedma_ctl != 0) { 2008 /* Add software bits in status register */ 2009 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2010 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2011 idedma_ctl); 2012 } 2013 pciide_print_modes(cp); 2014 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2015 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2016 } 2017 2018 void 2019 cmd_channel_map(pa, sc, channel) 2020 struct pci_attach_args *pa; 2021 struct pciide_softc *sc; 2022 int channel; 2023 { 2024 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2025 bus_size_t cmdsize, ctlsize; 2026 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2027 int interface; 2028 2029 /* 2030 * The 0648/0649 can be told to identify as a RAID controller. 2031 * In this case, we have to fake interface 2032 */ 2033 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2034 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2035 PCIIDE_INTERFACE_SETTABLE(1); 2036 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2037 CMD_CONF_DSA1) 2038 interface |= PCIIDE_INTERFACE_PCI(0) | 2039 PCIIDE_INTERFACE_PCI(1); 2040 } else { 2041 interface = PCI_INTERFACE(pa->pa_class); 2042 } 2043 2044 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2045 cp->name = PCIIDE_CHANNEL_NAME(channel); 2046 cp->wdc_channel.channel = channel; 2047 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2048 2049 if (channel > 0) { 2050 cp->wdc_channel.ch_queue = 2051 sc->pciide_channels[0].wdc_channel.ch_queue; 2052 } else { 2053 cp->wdc_channel.ch_queue = 2054 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2055 } 2056 if (cp->wdc_channel.ch_queue == NULL) { 2057 printf("%s %s channel: " 2058 "can't allocate memory for command queue", 2059 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2060 return; 2061 } 2062 2063 printf("%s: %s channel %s to %s mode\n", 2064 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2065 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2066 "configured" : "wired", 2067 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2068 "native-PCI" : "compatibility"); 2069 2070 /* 2071 * with a CMD PCI64x, if we get here, the first channel is enabled: 2072 * there's no way to disable the first channel without disabling 2073 * the whole device 2074 */ 2075 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2076 printf("%s: %s channel ignored (disabled)\n", 2077 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2078 return; 2079 } 2080 2081 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2082 if (cp->hw_ok == 0) 2083 return; 2084 if (channel == 1) { 2085 if (pciide_chan_candisable(cp)) { 2086 ctrl &= ~CMD_CTRL_2PORT; 2087 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2088 CMD_CTRL, ctrl); 2089 } 2090 } 2091 pciide_map_compat_intr(pa, cp, channel, interface); 2092 } 2093 2094 int 2095 cmd_pci_intr(arg) 2096 void *arg; 2097 { 2098 struct pciide_softc *sc = arg; 2099 struct pciide_channel *cp; 2100 struct channel_softc *wdc_cp; 2101 int i, rv, crv; 2102 u_int32_t priirq, secirq; 2103 2104 rv = 0; 2105 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2106 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2107 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2108 cp = &sc->pciide_channels[i]; 2109 wdc_cp = &cp->wdc_channel; 2110 /* If a compat channel skip. */ 2111 if (cp->compat) 2112 continue; 2113 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2114 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2115 crv = wdcintr(wdc_cp); 2116 if (crv == 0) 2117 printf("%s:%d: bogus intr\n", 2118 sc->sc_wdcdev.sc_dev.dv_xname, i); 2119 else 2120 rv = 1; 2121 } 2122 } 2123 return rv; 2124 } 2125 2126 void 2127 cmd_chip_map(sc, pa) 2128 struct pciide_softc *sc; 2129 struct pci_attach_args *pa; 2130 { 2131 int channel; 2132 2133 /* 2134 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2135 * and base adresses registers can be disabled at 2136 * hardware level. In this case, the device is wired 2137 * in compat mode and its first channel is always enabled, 2138 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2139 * In fact, it seems that the first channel of the CMD PCI0640 2140 * can't be disabled. 2141 */ 2142 2143 #ifdef PCIIDE_CMD064x_DISABLE 2144 if (pciide_chipen(sc, pa) == 0) 2145 return; 2146 #endif 2147 2148 printf("%s: hardware does not support DMA\n", 2149 sc->sc_wdcdev.sc_dev.dv_xname); 2150 sc->sc_dma_ok = 0; 2151 2152 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2153 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2154 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2155 2156 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2157 cmd_channel_map(pa, sc, channel); 2158 } 2159 } 2160 2161 void 2162 cmd0643_9_chip_map(sc, pa) 2163 struct pciide_softc *sc; 2164 struct pci_attach_args *pa; 2165 { 2166 struct pciide_channel *cp; 2167 int channel; 2168 int rev = PCI_REVISION( 2169 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2170 2171 /* 2172 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2173 * and base adresses registers can be disabled at 2174 * hardware level. In this case, the device is wired 2175 * in compat mode and its first channel is always enabled, 2176 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2177 * In fact, it seems that the first channel of the CMD PCI0640 2178 * can't be disabled. 2179 */ 2180 2181 #ifdef PCIIDE_CMD064x_DISABLE 2182 if (pciide_chipen(sc, pa) == 0) 2183 return; 2184 #endif 2185 printf("%s: bus-master DMA support present", 2186 sc->sc_wdcdev.sc_dev.dv_xname); 2187 pciide_mapreg_dma(sc, pa); 2188 printf("\n"); 2189 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2190 WDC_CAPABILITY_MODE; 2191 if (sc->sc_dma_ok) { 2192 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2193 switch (sc->sc_pp->ide_product) { 2194 case PCI_PRODUCT_CMDTECH_649: 2195 case PCI_PRODUCT_CMDTECH_648: 2196 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2197 sc->sc_wdcdev.UDMA_cap = 4; 2198 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2199 break; 2200 case PCI_PRODUCT_CMDTECH_646: 2201 if (rev >= CMD0646U2_REV) { 2202 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2203 sc->sc_wdcdev.UDMA_cap = 2; 2204 } else if (rev >= CMD0646U_REV) { 2205 /* 2206 * Linux's driver claims that the 646U is broken 2207 * with UDMA. Only enable it if we know what we're 2208 * doing 2209 */ 2210 #ifdef PCIIDE_CMD0646U_UDMA 2211 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2212 sc->sc_wdcdev.UDMA_cap = 2; 2213 #endif 2214 /* explicitely disable UDMA */ 2215 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2216 CMD_UDMATIM(0), 0); 2217 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2218 CMD_UDMATIM(1), 0); 2219 } 2220 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2221 break; 2222 default: 2223 sc->sc_wdcdev.irqack = pciide_irqack; 2224 } 2225 } 2226 2227 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2228 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2229 sc->sc_wdcdev.PIO_cap = 4; 2230 sc->sc_wdcdev.DMA_cap = 2; 2231 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2232 2233 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2234 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2235 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2236 DEBUG_PROBE); 2237 2238 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2239 cp = &sc->pciide_channels[channel]; 2240 cmd_channel_map(pa, sc, channel); 2241 if (cp->hw_ok == 0) 2242 continue; 2243 cmd0643_9_setup_channel(&cp->wdc_channel); 2244 } 2245 /* note - this also make sure we clear the irq disable and reset bits */ 2246 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2247 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2248 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2249 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2250 DEBUG_PROBE); 2251 } 2252 2253 void 2254 cmd0643_9_setup_channel(chp) 2255 struct channel_softc *chp; 2256 { 2257 struct ata_drive_datas *drvp; 2258 u_int8_t tim; 2259 u_int32_t idedma_ctl, udma_reg; 2260 int drive; 2261 struct pciide_channel *cp = (struct pciide_channel*)chp; 2262 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2263 2264 idedma_ctl = 0; 2265 /* setup DMA if needed */ 2266 pciide_channel_dma_setup(cp); 2267 2268 for (drive = 0; drive < 2; drive++) { 2269 drvp = &chp->ch_drive[drive]; 2270 /* If no drive, skip */ 2271 if ((drvp->drive_flags & DRIVE) == 0) 2272 continue; 2273 /* add timing values, setup DMA if needed */ 2274 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2275 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2276 if (drvp->drive_flags & DRIVE_UDMA) { 2277 /* UltraDMA on a 646U2, 0648 or 0649 */ 2278 udma_reg = pciide_pci_read(sc->sc_pc, 2279 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2280 if (drvp->UDMA_mode > 2 && 2281 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2282 CMD_BICSR) & 2283 CMD_BICSR_80(chp->channel)) == 0) 2284 drvp->UDMA_mode = 2; 2285 if (drvp->UDMA_mode > 2) 2286 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2287 else if (sc->sc_wdcdev.UDMA_cap > 2) 2288 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2289 udma_reg |= CMD_UDMATIM_UDMA(drive); 2290 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2291 CMD_UDMATIM_TIM_OFF(drive)); 2292 udma_reg |= 2293 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2294 CMD_UDMATIM_TIM_OFF(drive)); 2295 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2296 CMD_UDMATIM(chp->channel), udma_reg); 2297 } else { 2298 /* 2299 * use Multiword DMA. 2300 * Timings will be used for both PIO and DMA, 2301 * so adjust DMA mode if needed 2302 * if we have a 0646U2/8/9, turn off UDMA 2303 */ 2304 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2305 udma_reg = pciide_pci_read(sc->sc_pc, 2306 sc->sc_tag, 2307 CMD_UDMATIM(chp->channel)); 2308 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2309 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2310 CMD_UDMATIM(chp->channel), 2311 udma_reg); 2312 } 2313 if (drvp->PIO_mode >= 3 && 2314 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2315 drvp->DMA_mode = drvp->PIO_mode - 2; 2316 } 2317 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2318 } 2319 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2320 } 2321 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2322 CMD_DATA_TIM(chp->channel, drive), tim); 2323 } 2324 if (idedma_ctl != 0) { 2325 /* Add software bits in status register */ 2326 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2327 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2328 idedma_ctl); 2329 } 2330 pciide_print_modes(cp); 2331 } 2332 2333 void 2334 cmd646_9_irqack(chp) 2335 struct channel_softc *chp; 2336 { 2337 u_int32_t priirq, secirq; 2338 struct pciide_channel *cp = (struct pciide_channel*)chp; 2339 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2340 2341 if (chp->channel == 0) { 2342 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2343 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2344 } else { 2345 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2346 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2347 } 2348 pciide_irqack(chp); 2349 } 2350 2351 void 2352 cy693_chip_map(sc, pa) 2353 struct pciide_softc *sc; 2354 struct pci_attach_args *pa; 2355 { 2356 struct pciide_channel *cp; 2357 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2358 bus_size_t cmdsize, ctlsize; 2359 2360 if (pciide_chipen(sc, pa) == 0) 2361 return; 2362 /* 2363 * this chip has 2 PCI IDE functions, one for primary and one for 2364 * secondary. So we need to call pciide_mapregs_compat() with 2365 * the real channel 2366 */ 2367 if (pa->pa_function == 1) { 2368 sc->sc_cy_compatchan = 0; 2369 } else if (pa->pa_function == 2) { 2370 sc->sc_cy_compatchan = 1; 2371 } else { 2372 printf("%s: unexpected PCI function %d\n", 2373 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2374 return; 2375 } 2376 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2377 printf("%s: bus-master DMA support present", 2378 sc->sc_wdcdev.sc_dev.dv_xname); 2379 pciide_mapreg_dma(sc, pa); 2380 } else { 2381 printf("%s: hardware does not support DMA", 2382 sc->sc_wdcdev.sc_dev.dv_xname); 2383 sc->sc_dma_ok = 0; 2384 } 2385 printf("\n"); 2386 2387 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2388 if (sc->sc_cy_handle == NULL) { 2389 printf("%s: unable to map hyperCache control registers\n", 2390 sc->sc_wdcdev.sc_dev.dv_xname); 2391 sc->sc_dma_ok = 0; 2392 } 2393 2394 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2395 WDC_CAPABILITY_MODE; 2396 if (sc->sc_dma_ok) { 2397 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2398 sc->sc_wdcdev.irqack = pciide_irqack; 2399 } 2400 sc->sc_wdcdev.PIO_cap = 4; 2401 sc->sc_wdcdev.DMA_cap = 2; 2402 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2403 2404 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2405 sc->sc_wdcdev.nchannels = 1; 2406 2407 /* Only one channel for this chip; if we are here it's enabled */ 2408 cp = &sc->pciide_channels[0]; 2409 sc->wdc_chanarray[0] = &cp->wdc_channel; 2410 cp->name = PCIIDE_CHANNEL_NAME(0); 2411 cp->wdc_channel.channel = 0; 2412 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2413 cp->wdc_channel.ch_queue = 2414 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2415 if (cp->wdc_channel.ch_queue == NULL) { 2416 printf("%s primary channel: " 2417 "can't allocate memory for command queue", 2418 sc->sc_wdcdev.sc_dev.dv_xname); 2419 return; 2420 } 2421 printf("%s: primary channel %s to ", 2422 sc->sc_wdcdev.sc_dev.dv_xname, 2423 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2424 "configured" : "wired"); 2425 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2426 printf("native-PCI"); 2427 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2428 pciide_pci_intr); 2429 } else { 2430 printf("compatibility"); 2431 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2432 &cmdsize, &ctlsize); 2433 } 2434 printf(" mode\n"); 2435 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2436 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2437 wdcattach(&cp->wdc_channel); 2438 if (pciide_chan_candisable(cp)) { 2439 pci_conf_write(sc->sc_pc, sc->sc_tag, 2440 PCI_COMMAND_STATUS_REG, 0); 2441 } 2442 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2443 if (cp->hw_ok == 0) 2444 return; 2445 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2446 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2447 cy693_setup_channel(&cp->wdc_channel); 2448 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2449 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2450 } 2451 2452 void 2453 cy693_setup_channel(chp) 2454 struct channel_softc *chp; 2455 { 2456 struct ata_drive_datas *drvp; 2457 int drive; 2458 u_int32_t cy_cmd_ctrl; 2459 u_int32_t idedma_ctl; 2460 struct pciide_channel *cp = (struct pciide_channel*)chp; 2461 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2462 int dma_mode = -1; 2463 2464 cy_cmd_ctrl = idedma_ctl = 0; 2465 2466 /* setup DMA if needed */ 2467 pciide_channel_dma_setup(cp); 2468 2469 for (drive = 0; drive < 2; drive++) { 2470 drvp = &chp->ch_drive[drive]; 2471 /* If no drive, skip */ 2472 if ((drvp->drive_flags & DRIVE) == 0) 2473 continue; 2474 /* add timing values, setup DMA if needed */ 2475 if (drvp->drive_flags & DRIVE_DMA) { 2476 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2477 /* use Multiword DMA */ 2478 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2479 dma_mode = drvp->DMA_mode; 2480 } 2481 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2482 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2483 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2484 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2485 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2486 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2487 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2488 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2489 } 2490 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2491 chp->ch_drive[0].DMA_mode = dma_mode; 2492 chp->ch_drive[1].DMA_mode = dma_mode; 2493 2494 if (dma_mode == -1) 2495 dma_mode = 0; 2496 2497 if (sc->sc_cy_handle != NULL) { 2498 /* Note: `multiple' is implied. */ 2499 cy82c693_write(sc->sc_cy_handle, 2500 (sc->sc_cy_compatchan == 0) ? 2501 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2502 } 2503 2504 pciide_print_modes(cp); 2505 2506 if (idedma_ctl != 0) { 2507 /* Add software bits in status register */ 2508 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2509 IDEDMA_CTL, idedma_ctl); 2510 } 2511 } 2512 2513 void 2514 sis_chip_map(sc, pa) 2515 struct pciide_softc *sc; 2516 struct pci_attach_args *pa; 2517 { 2518 struct pciide_channel *cp; 2519 int channel; 2520 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2521 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2522 pcireg_t rev = PCI_REVISION(pa->pa_class); 2523 bus_size_t cmdsize, ctlsize; 2524 2525 if (pciide_chipen(sc, pa) == 0) 2526 return; 2527 printf("%s: bus-master DMA support present", 2528 sc->sc_wdcdev.sc_dev.dv_xname); 2529 pciide_mapreg_dma(sc, pa); 2530 printf("\n"); 2531 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2532 WDC_CAPABILITY_MODE; 2533 if (sc->sc_dma_ok) { 2534 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2535 sc->sc_wdcdev.irqack = pciide_irqack; 2536 if (rev >= 0xd0) 2537 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2538 } 2539 2540 sc->sc_wdcdev.PIO_cap = 4; 2541 sc->sc_wdcdev.DMA_cap = 2; 2542 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2543 sc->sc_wdcdev.UDMA_cap = 2; 2544 sc->sc_wdcdev.set_modes = sis_setup_channel; 2545 2546 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2547 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2548 2549 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2550 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2551 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2552 2553 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2554 cp = &sc->pciide_channels[channel]; 2555 if (pciide_chansetup(sc, channel, interface) == 0) 2556 continue; 2557 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2558 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2559 printf("%s: %s channel ignored (disabled)\n", 2560 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2561 continue; 2562 } 2563 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2564 pciide_pci_intr); 2565 if (cp->hw_ok == 0) 2566 continue; 2567 if (pciide_chan_candisable(cp)) { 2568 if (channel == 0) 2569 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2570 else 2571 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2572 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2573 sis_ctr0); 2574 } 2575 pciide_map_compat_intr(pa, cp, channel, interface); 2576 if (cp->hw_ok == 0) 2577 continue; 2578 sis_setup_channel(&cp->wdc_channel); 2579 } 2580 } 2581 2582 void 2583 sis_setup_channel(chp) 2584 struct channel_softc *chp; 2585 { 2586 struct ata_drive_datas *drvp; 2587 int drive; 2588 u_int32_t sis_tim; 2589 u_int32_t idedma_ctl; 2590 struct pciide_channel *cp = (struct pciide_channel*)chp; 2591 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2592 2593 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2594 "channel %d 0x%x\n", chp->channel, 2595 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2596 DEBUG_PROBE); 2597 sis_tim = 0; 2598 idedma_ctl = 0; 2599 /* setup DMA if needed */ 2600 pciide_channel_dma_setup(cp); 2601 2602 for (drive = 0; drive < 2; drive++) { 2603 drvp = &chp->ch_drive[drive]; 2604 /* If no drive, skip */ 2605 if ((drvp->drive_flags & DRIVE) == 0) 2606 continue; 2607 /* add timing values, setup DMA if needed */ 2608 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2609 (drvp->drive_flags & DRIVE_UDMA) == 0) 2610 goto pio; 2611 2612 if (drvp->drive_flags & DRIVE_UDMA) { 2613 /* use Ultra/DMA */ 2614 drvp->drive_flags &= ~DRIVE_DMA; 2615 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2616 SIS_TIM_UDMA_TIME_OFF(drive); 2617 sis_tim |= SIS_TIM_UDMA_EN(drive); 2618 } else { 2619 /* 2620 * use Multiword DMA 2621 * Timings will be used for both PIO and DMA, 2622 * so adjust DMA mode if needed 2623 */ 2624 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2625 drvp->PIO_mode = drvp->DMA_mode + 2; 2626 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2627 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2628 drvp->PIO_mode - 2 : 0; 2629 if (drvp->DMA_mode == 0) 2630 drvp->PIO_mode = 0; 2631 } 2632 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2633 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2634 SIS_TIM_ACT_OFF(drive); 2635 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2636 SIS_TIM_REC_OFF(drive); 2637 } 2638 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2639 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2640 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2641 if (idedma_ctl != 0) { 2642 /* Add software bits in status register */ 2643 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2644 IDEDMA_CTL, idedma_ctl); 2645 } 2646 pciide_print_modes(cp); 2647 } 2648 2649 void 2650 acer_chip_map(sc, pa) 2651 struct pciide_softc *sc; 2652 struct pci_attach_args *pa; 2653 { 2654 struct pciide_channel *cp; 2655 int channel; 2656 pcireg_t cr, interface; 2657 bus_size_t cmdsize, ctlsize; 2658 2659 if (pciide_chipen(sc, pa) == 0) 2660 return; 2661 printf("%s: bus-master DMA support present", 2662 sc->sc_wdcdev.sc_dev.dv_xname); 2663 pciide_mapreg_dma(sc, pa); 2664 printf("\n"); 2665 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2666 WDC_CAPABILITY_MODE; 2667 if (sc->sc_dma_ok) { 2668 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2669 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2670 sc->sc_wdcdev.irqack = pciide_irqack; 2671 } 2672 2673 sc->sc_wdcdev.PIO_cap = 4; 2674 sc->sc_wdcdev.DMA_cap = 2; 2675 sc->sc_wdcdev.UDMA_cap = 2; 2676 sc->sc_wdcdev.set_modes = acer_setup_channel; 2677 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2678 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2679 2680 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2681 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2682 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2683 2684 /* Enable "microsoft register bits" R/W. */ 2685 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2686 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2687 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2688 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2689 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2690 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2691 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2692 ~ACER_CHANSTATUSREGS_RO); 2693 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2694 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2695 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2696 /* Don't use cr, re-read the real register content instead */ 2697 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2698 PCI_CLASS_REG)); 2699 2700 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2701 cp = &sc->pciide_channels[channel]; 2702 if (pciide_chansetup(sc, channel, interface) == 0) 2703 continue; 2704 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2705 printf("%s: %s channel ignored (disabled)\n", 2706 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2707 continue; 2708 } 2709 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2710 acer_pci_intr); 2711 if (cp->hw_ok == 0) 2712 continue; 2713 if (pciide_chan_candisable(cp)) { 2714 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2715 pci_conf_write(sc->sc_pc, sc->sc_tag, 2716 PCI_CLASS_REG, cr); 2717 } 2718 pciide_map_compat_intr(pa, cp, channel, interface); 2719 acer_setup_channel(&cp->wdc_channel); 2720 } 2721 } 2722 2723 void 2724 acer_setup_channel(chp) 2725 struct channel_softc *chp; 2726 { 2727 struct ata_drive_datas *drvp; 2728 int drive; 2729 u_int32_t acer_fifo_udma; 2730 u_int32_t idedma_ctl; 2731 struct pciide_channel *cp = (struct pciide_channel*)chp; 2732 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2733 2734 idedma_ctl = 0; 2735 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2736 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2737 acer_fifo_udma), DEBUG_PROBE); 2738 /* setup DMA if needed */ 2739 pciide_channel_dma_setup(cp); 2740 2741 for (drive = 0; drive < 2; drive++) { 2742 drvp = &chp->ch_drive[drive]; 2743 /* If no drive, skip */ 2744 if ((drvp->drive_flags & DRIVE) == 0) 2745 continue; 2746 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2747 "channel %d drive %d 0x%x\n", chp->channel, drive, 2748 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2749 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2750 /* clear FIFO/DMA mode */ 2751 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2752 ACER_UDMA_EN(chp->channel, drive) | 2753 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2754 2755 /* add timing values, setup DMA if needed */ 2756 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2757 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2758 acer_fifo_udma |= 2759 ACER_FTH_OPL(chp->channel, drive, 0x1); 2760 goto pio; 2761 } 2762 2763 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2764 if (drvp->drive_flags & DRIVE_UDMA) { 2765 /* use Ultra/DMA */ 2766 drvp->drive_flags &= ~DRIVE_DMA; 2767 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2768 acer_fifo_udma |= 2769 ACER_UDMA_TIM(chp->channel, drive, 2770 acer_udma[drvp->UDMA_mode]); 2771 } else { 2772 /* 2773 * use Multiword DMA 2774 * Timings will be used for both PIO and DMA, 2775 * so adjust DMA mode if needed 2776 */ 2777 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2778 drvp->PIO_mode = drvp->DMA_mode + 2; 2779 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2780 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2781 drvp->PIO_mode - 2 : 0; 2782 if (drvp->DMA_mode == 0) 2783 drvp->PIO_mode = 0; 2784 } 2785 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2786 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2787 ACER_IDETIM(chp->channel, drive), 2788 acer_pio[drvp->PIO_mode]); 2789 } 2790 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2791 acer_fifo_udma), DEBUG_PROBE); 2792 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2793 if (idedma_ctl != 0) { 2794 /* Add software bits in status register */ 2795 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2796 IDEDMA_CTL, idedma_ctl); 2797 } 2798 pciide_print_modes(cp); 2799 } 2800 2801 int 2802 acer_pci_intr(arg) 2803 void *arg; 2804 { 2805 struct pciide_softc *sc = arg; 2806 struct pciide_channel *cp; 2807 struct channel_softc *wdc_cp; 2808 int i, rv, crv; 2809 u_int32_t chids; 2810 2811 rv = 0; 2812 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2813 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2814 cp = &sc->pciide_channels[i]; 2815 wdc_cp = &cp->wdc_channel; 2816 /* If a compat channel skip. */ 2817 if (cp->compat) 2818 continue; 2819 if (chids & ACER_CHIDS_INT(i)) { 2820 crv = wdcintr(wdc_cp); 2821 if (crv == 0) 2822 printf("%s:%d: bogus intr\n", 2823 sc->sc_wdcdev.sc_dev.dv_xname, i); 2824 else 2825 rv = 1; 2826 } 2827 } 2828 return rv; 2829 } 2830 2831 void 2832 hpt_chip_map(sc, pa) 2833 struct pciide_softc *sc; 2834 struct pci_attach_args *pa; 2835 { 2836 struct pciide_channel *cp; 2837 int i, compatchan, revision; 2838 pcireg_t interface; 2839 bus_size_t cmdsize, ctlsize; 2840 2841 if (pciide_chipen(sc, pa) == 0) 2842 return; 2843 revision = PCI_REVISION(pa->pa_class); 2844 2845 /* 2846 * when the chip is in native mode it identifies itself as a 2847 * 'misc mass storage'. Fake interface in this case. 2848 */ 2849 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2850 interface = PCI_INTERFACE(pa->pa_class); 2851 } else { 2852 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2853 PCIIDE_INTERFACE_PCI(0); 2854 if (revision == HPT370_REV) 2855 interface |= PCIIDE_INTERFACE_PCI(1); 2856 } 2857 2858 printf("%s: bus-master DMA support present", 2859 sc->sc_wdcdev.sc_dev.dv_xname); 2860 pciide_mapreg_dma(sc, pa); 2861 printf("\n"); 2862 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2863 WDC_CAPABILITY_MODE; 2864 if (sc->sc_dma_ok) { 2865 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2866 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2867 sc->sc_wdcdev.irqack = pciide_irqack; 2868 } 2869 sc->sc_wdcdev.PIO_cap = 4; 2870 sc->sc_wdcdev.DMA_cap = 2; 2871 sc->sc_wdcdev.UDMA_cap = 4; 2872 2873 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2874 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2875 if (revision == HPT366_REV) { 2876 /* 2877 * The 366 has 2 PCI IDE functions, one for primary and one 2878 * for secondary. So we need to call pciide_mapregs_compat() 2879 * with the real channel 2880 */ 2881 if (pa->pa_function == 0) { 2882 compatchan = 0; 2883 } else if (pa->pa_function == 1) { 2884 compatchan = 1; 2885 } else { 2886 printf("%s: unexpected PCI function %d\n", 2887 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2888 return; 2889 } 2890 sc->sc_wdcdev.nchannels = 1; 2891 } else { 2892 sc->sc_wdcdev.nchannels = 2; 2893 } 2894 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2895 cp = &sc->pciide_channels[i]; 2896 if (sc->sc_wdcdev.nchannels > 1) { 2897 compatchan = i; 2898 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2899 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2900 printf("%s: %s channel ignored (disabled)\n", 2901 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2902 continue; 2903 } 2904 } 2905 if (pciide_chansetup(sc, i, interface) == 0) 2906 continue; 2907 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2908 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2909 &ctlsize, hpt_pci_intr); 2910 } else { 2911 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2912 &cmdsize, &ctlsize); 2913 } 2914 if (cp->hw_ok == 0) 2915 return; 2916 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2917 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2918 wdcattach(&cp->wdc_channel); 2919 hpt_setup_channel(&cp->wdc_channel); 2920 } 2921 if (revision == HPT370_REV) { 2922 /* 2923 * HPT370_REV has a bit to disable interrupts, make sure 2924 * to clear it 2925 */ 2926 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 2927 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 2928 ~HPT_CSEL_IRQDIS); 2929 } 2930 return; 2931 } 2932 2933 2934 void 2935 hpt_setup_channel(chp) 2936 struct channel_softc *chp; 2937 { 2938 struct ata_drive_datas *drvp; 2939 int drive; 2940 int cable; 2941 u_int32_t before, after; 2942 u_int32_t idedma_ctl; 2943 struct pciide_channel *cp = (struct pciide_channel*)chp; 2944 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2945 2946 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 2947 2948 /* setup DMA if needed */ 2949 pciide_channel_dma_setup(cp); 2950 2951 idedma_ctl = 0; 2952 2953 /* Per drive settings */ 2954 for (drive = 0; drive < 2; drive++) { 2955 drvp = &chp->ch_drive[drive]; 2956 /* If no drive, skip */ 2957 if ((drvp->drive_flags & DRIVE) == 0) 2958 continue; 2959 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 2960 HPT_IDETIM(chp->channel, drive)); 2961 2962 /* add timing values, setup DMA if needed */ 2963 if (drvp->drive_flags & DRIVE_UDMA) { 2964 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 2965 drvp->UDMA_mode > 2) 2966 drvp->UDMA_mode = 2; 2967 after = (sc->sc_wdcdev.nchannels == 2) ? 2968 hpt370_udma[drvp->UDMA_mode] : 2969 hpt366_udma[drvp->UDMA_mode]; 2970 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2971 } else if (drvp->drive_flags & DRIVE_DMA) { 2972 /* 2973 * use Multiword DMA. 2974 * Timings will be used for both PIO and DMA, so adjust 2975 * DMA mode if needed 2976 */ 2977 if (drvp->PIO_mode >= 3 && 2978 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2979 drvp->DMA_mode = drvp->PIO_mode - 2; 2980 } 2981 after = (sc->sc_wdcdev.nchannels == 2) ? 2982 hpt370_dma[drvp->DMA_mode] : 2983 hpt366_dma[drvp->DMA_mode]; 2984 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2985 } else { 2986 /* PIO only */ 2987 after = (sc->sc_wdcdev.nchannels == 2) ? 2988 hpt370_pio[drvp->PIO_mode] : 2989 hpt366_pio[drvp->PIO_mode]; 2990 } 2991 pci_conf_write(sc->sc_pc, sc->sc_tag, 2992 HPT_IDETIM(chp->channel, drive), after); 2993 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 2994 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 2995 after, before), DEBUG_PROBE); 2996 } 2997 if (idedma_ctl != 0) { 2998 /* Add software bits in status register */ 2999 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3000 IDEDMA_CTL, idedma_ctl); 3001 } 3002 pciide_print_modes(cp); 3003 } 3004 3005 int 3006 hpt_pci_intr(arg) 3007 void *arg; 3008 { 3009 struct pciide_softc *sc = arg; 3010 struct pciide_channel *cp; 3011 struct channel_softc *wdc_cp; 3012 int rv = 0; 3013 int dmastat, i, crv; 3014 3015 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3016 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3017 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3018 if((dmastat & IDEDMA_CTL_INTR) == 0) 3019 continue; 3020 cp = &sc->pciide_channels[i]; 3021 wdc_cp = &cp->wdc_channel; 3022 crv = wdcintr(wdc_cp); 3023 if (crv == 0) { 3024 printf("%s:%d: bogus intr\n", 3025 sc->sc_wdcdev.sc_dev.dv_xname, i); 3026 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3027 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3028 } else 3029 rv = 1; 3030 } 3031 return rv; 3032 } 3033 3034 3035 /* A macro to test product */ 3036 #define PDC_IS_262(sc) (sc->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66) 3037 3038 void 3039 pdc202xx_chip_map(sc, pa) 3040 struct pciide_softc *sc; 3041 struct pci_attach_args *pa; 3042 { 3043 struct pciide_channel *cp; 3044 int channel; 3045 pcireg_t interface, st, mode; 3046 bus_size_t cmdsize, ctlsize; 3047 3048 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3049 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3050 DEBUG_PROBE); 3051 if (pciide_chipen(sc, pa) == 0) 3052 return; 3053 3054 /* turn off RAID mode */ 3055 st &= ~PDC2xx_STATE_IDERAID; 3056 3057 /* 3058 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3059 * mode. We have to fake interface 3060 */ 3061 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3062 if (st & PDC2xx_STATE_NATIVE) 3063 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3064 3065 printf("%s: bus-master DMA support present", 3066 sc->sc_wdcdev.sc_dev.dv_xname); 3067 pciide_mapreg_dma(sc, pa); 3068 printf("\n"); 3069 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3070 WDC_CAPABILITY_MODE; 3071 if (sc->sc_dma_ok) { 3072 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3073 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3074 sc->sc_wdcdev.irqack = pciide_irqack; 3075 } 3076 sc->sc_wdcdev.PIO_cap = 4; 3077 sc->sc_wdcdev.DMA_cap = 2; 3078 if (PDC_IS_262(sc)) 3079 sc->sc_wdcdev.UDMA_cap = 4; 3080 else 3081 sc->sc_wdcdev.UDMA_cap = 2; 3082 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3083 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3084 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3085 3086 /* setup failsafe defaults */ 3087 mode = 0; 3088 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3089 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3090 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3091 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3092 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3093 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3094 "initial timings 0x%x, now 0x%x\n", channel, 3095 pci_conf_read(sc->sc_pc, sc->sc_tag, 3096 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3097 DEBUG_PROBE); 3098 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3099 mode | PDC2xx_TIM_IORDYp); 3100 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3101 "initial timings 0x%x, now 0x%x\n", channel, 3102 pci_conf_read(sc->sc_pc, sc->sc_tag, 3103 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3104 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3105 mode); 3106 } 3107 3108 mode = PDC2xx_SCR_DMA; 3109 if (PDC_IS_262(sc)) { 3110 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3111 } else { 3112 /* the BIOS set it up this way */ 3113 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3114 } 3115 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3116 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3117 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3118 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3119 DEBUG_PROBE); 3120 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3121 3122 /* controller initial state register is OK even without BIOS */ 3123 /* Set DMA mode to IDE DMA compatibility */ 3124 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3125 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3126 DEBUG_PROBE); 3127 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3128 mode | 0x1); 3129 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3130 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3131 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3132 mode | 0x1); 3133 3134 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3135 cp = &sc->pciide_channels[channel]; 3136 if (pciide_chansetup(sc, channel, interface) == 0) 3137 continue; 3138 if ((st & (PDC_IS_262(sc) ? 3139 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3140 printf("%s: %s channel ignored (disabled)\n", 3141 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3142 continue; 3143 } 3144 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3145 pdc202xx_pci_intr); 3146 if (cp->hw_ok == 0) 3147 continue; 3148 if (pciide_chan_candisable(cp)) 3149 st &= ~(PDC_IS_262(sc) ? 3150 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3151 pciide_map_compat_intr(pa, cp, channel, interface); 3152 pdc202xx_setup_channel(&cp->wdc_channel); 3153 } 3154 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3155 DEBUG_PROBE); 3156 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3157 return; 3158 } 3159 3160 void 3161 pdc202xx_setup_channel(chp) 3162 struct channel_softc *chp; 3163 { 3164 struct ata_drive_datas *drvp; 3165 int drive; 3166 pcireg_t mode, st; 3167 u_int32_t idedma_ctl, scr, atapi; 3168 struct pciide_channel *cp = (struct pciide_channel*)chp; 3169 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3170 int channel = chp->channel; 3171 3172 /* setup DMA if needed */ 3173 pciide_channel_dma_setup(cp); 3174 3175 idedma_ctl = 0; 3176 3177 /* Per channel settings */ 3178 if (PDC_IS_262(sc)) { 3179 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3180 PDC262_U66); 3181 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3182 /* Trimm UDMA mode */ 3183 if ((st & PDC262_STATE_80P(channel)) != 0 || 3184 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3185 chp->ch_drive[0].UDMA_mode <= 2) || 3186 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3187 chp->ch_drive[1].UDMA_mode <= 2)) { 3188 if (chp->ch_drive[0].UDMA_mode > 2) 3189 chp->ch_drive[0].UDMA_mode = 2; 3190 if (chp->ch_drive[1].UDMA_mode > 2) 3191 chp->ch_drive[1].UDMA_mode = 2; 3192 } 3193 /* Set U66 if needed */ 3194 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3195 chp->ch_drive[0].UDMA_mode > 2) || 3196 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3197 chp->ch_drive[1].UDMA_mode > 2)) 3198 scr |= PDC262_U66_EN(channel); 3199 else 3200 scr &= ~PDC262_U66_EN(channel); 3201 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3202 PDC262_U66, scr); 3203 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3204 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3205 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3206 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3207 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3208 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3209 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3210 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3211 atapi = 0; 3212 else 3213 atapi = PDC262_ATAPI_UDMA; 3214 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3215 PDC262_ATAPI(channel), atapi); 3216 } 3217 } 3218 for (drive = 0; drive < 2; drive++) { 3219 drvp = &chp->ch_drive[drive]; 3220 /* If no drive, skip */ 3221 if ((drvp->drive_flags & DRIVE) == 0) 3222 continue; 3223 mode = 0; 3224 if (drvp->drive_flags & DRIVE_UDMA) { 3225 mode = PDC2xx_TIM_SET_MB(mode, 3226 pdc2xx_udma_mb[drvp->UDMA_mode]); 3227 mode = PDC2xx_TIM_SET_MC(mode, 3228 pdc2xx_udma_mc[drvp->UDMA_mode]); 3229 drvp->drive_flags &= ~DRIVE_DMA; 3230 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3231 } else if (drvp->drive_flags & DRIVE_DMA) { 3232 mode = PDC2xx_TIM_SET_MB(mode, 3233 pdc2xx_dma_mb[drvp->DMA_mode]); 3234 mode = PDC2xx_TIM_SET_MC(mode, 3235 pdc2xx_dma_mc[drvp->DMA_mode]); 3236 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3237 } else { 3238 mode = PDC2xx_TIM_SET_MB(mode, 3239 pdc2xx_dma_mb[0]); 3240 mode = PDC2xx_TIM_SET_MC(mode, 3241 pdc2xx_dma_mc[0]); 3242 } 3243 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3244 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3245 if (drvp->drive_flags & DRIVE_ATA) 3246 mode |= PDC2xx_TIM_PRE; 3247 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3248 if (drvp->PIO_mode >= 3) { 3249 mode |= PDC2xx_TIM_IORDY; 3250 if (drive == 0) 3251 mode |= PDC2xx_TIM_IORDYp; 3252 } 3253 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3254 "timings 0x%x\n", 3255 sc->sc_wdcdev.sc_dev.dv_xname, 3256 chp->channel, drive, mode), DEBUG_PROBE); 3257 pci_conf_write(sc->sc_pc, sc->sc_tag, 3258 PDC2xx_TIM(chp->channel, drive), mode); 3259 } 3260 if (idedma_ctl != 0) { 3261 /* Add software bits in status register */ 3262 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3263 IDEDMA_CTL, idedma_ctl); 3264 } 3265 pciide_print_modes(cp); 3266 } 3267 3268 int 3269 pdc202xx_pci_intr(arg) 3270 void *arg; 3271 { 3272 struct pciide_softc *sc = arg; 3273 struct pciide_channel *cp; 3274 struct channel_softc *wdc_cp; 3275 int i, rv, crv; 3276 u_int32_t scr; 3277 3278 rv = 0; 3279 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3280 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3281 cp = &sc->pciide_channels[i]; 3282 wdc_cp = &cp->wdc_channel; 3283 /* If a compat channel skip. */ 3284 if (cp->compat) 3285 continue; 3286 if (scr & PDC2xx_SCR_INT(i)) { 3287 crv = wdcintr(wdc_cp); 3288 if (crv == 0) 3289 printf("%s:%d: bogus intr\n", 3290 sc->sc_wdcdev.sc_dev.dv_xname, i); 3291 else 3292 rv = 1; 3293 } 3294 } 3295 return rv; 3296 } 3297 3298 void 3299 opti_chip_map(sc, pa) 3300 struct pciide_softc *sc; 3301 struct pci_attach_args *pa; 3302 { 3303 struct pciide_channel *cp; 3304 bus_size_t cmdsize, ctlsize; 3305 pcireg_t interface; 3306 u_int8_t init_ctrl; 3307 int channel; 3308 3309 if (pciide_chipen(sc, pa) == 0) 3310 return; 3311 printf("%s: bus-master DMA support present", 3312 sc->sc_wdcdev.sc_dev.dv_xname); 3313 pciide_mapreg_dma(sc, pa); 3314 printf("\n"); 3315 3316 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3317 WDC_CAPABILITY_MODE; 3318 sc->sc_wdcdev.PIO_cap = 4; 3319 if (sc->sc_dma_ok) { 3320 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3321 sc->sc_wdcdev.irqack = pciide_irqack; 3322 sc->sc_wdcdev.DMA_cap = 2; 3323 } 3324 sc->sc_wdcdev.set_modes = opti_setup_channel; 3325 3326 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3327 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3328 3329 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3330 OPTI_REG_INIT_CONTROL); 3331 3332 interface = PCI_INTERFACE(pa->pa_class); 3333 3334 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3335 cp = &sc->pciide_channels[channel]; 3336 if (pciide_chansetup(sc, channel, interface) == 0) 3337 continue; 3338 if (channel == 1 && 3339 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3340 printf("%s: %s channel ignored (disabled)\n", 3341 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3342 continue; 3343 } 3344 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3345 pciide_pci_intr); 3346 if (cp->hw_ok == 0) 3347 continue; 3348 pciide_map_compat_intr(pa, cp, channel, interface); 3349 if (cp->hw_ok == 0) 3350 continue; 3351 opti_setup_channel(&cp->wdc_channel); 3352 } 3353 } 3354 3355 void 3356 opti_setup_channel(chp) 3357 struct channel_softc *chp; 3358 { 3359 struct ata_drive_datas *drvp; 3360 struct pciide_channel *cp = (struct pciide_channel*)chp; 3361 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3362 int drive, spd; 3363 int mode[2]; 3364 u_int8_t rv, mr; 3365 3366 /* 3367 * The `Delay' and `Address Setup Time' fields of the 3368 * Miscellaneous Register are always zero initially. 3369 */ 3370 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3371 mr &= ~(OPTI_MISC_DELAY_MASK | 3372 OPTI_MISC_ADDR_SETUP_MASK | 3373 OPTI_MISC_INDEX_MASK); 3374 3375 /* Prime the control register before setting timing values */ 3376 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3377 3378 /* Determine the clockrate of the PCIbus the chip is attached to */ 3379 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3380 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3381 3382 /* setup DMA if needed */ 3383 pciide_channel_dma_setup(cp); 3384 3385 for (drive = 0; drive < 2; drive++) { 3386 drvp = &chp->ch_drive[drive]; 3387 /* If no drive, skip */ 3388 if ((drvp->drive_flags & DRIVE) == 0) { 3389 mode[drive] = -1; 3390 continue; 3391 } 3392 3393 if ((drvp->drive_flags & DRIVE_DMA)) { 3394 /* 3395 * Timings will be used for both PIO and DMA, 3396 * so adjust DMA mode if needed 3397 */ 3398 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3399 drvp->PIO_mode = drvp->DMA_mode + 2; 3400 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3401 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3402 drvp->PIO_mode - 2 : 0; 3403 if (drvp->DMA_mode == 0) 3404 drvp->PIO_mode = 0; 3405 3406 mode[drive] = drvp->DMA_mode + 5; 3407 } else 3408 mode[drive] = drvp->PIO_mode; 3409 3410 if (drive && mode[0] >= 0 && 3411 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3412 /* 3413 * Can't have two drives using different values 3414 * for `Address Setup Time'. 3415 * Slow down the faster drive to compensate. 3416 */ 3417 int d = (opti_tim_as[spd][mode[0]] > 3418 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3419 3420 mode[d] = mode[1-d]; 3421 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3422 chp->ch_drive[d].DMA_mode = 0; 3423 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3424 } 3425 } 3426 3427 for (drive = 0; drive < 2; drive++) { 3428 int m; 3429 if ((m = mode[drive]) < 0) 3430 continue; 3431 3432 /* Set the Address Setup Time and select appropriate index */ 3433 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3434 rv |= OPTI_MISC_INDEX(drive); 3435 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3436 3437 /* Set the pulse width and recovery timing parameters */ 3438 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3439 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3440 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3441 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3442 3443 /* Set the Enhanced Mode register appropriately */ 3444 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3445 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3446 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3447 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3448 } 3449 3450 /* Finally, enable the timings */ 3451 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3452 3453 pciide_print_modes(cp); 3454 } 3455
Indexes created Wed Sep 24 05:09:52 GMT 2025