pciide.c revision 1.88
1 /* $NetBSD: pciide.c,v 1.88 2000/10/04 09:34:09 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 #include <dev/pci/pciidereg.h> 105 #include <dev/pci/pciidevar.h> 106 #include <dev/pci/pciide_piix_reg.h> 107 #include <dev/pci/pciide_amd_reg.h> 108 #include <dev/pci/pciide_apollo_reg.h> 109 #include <dev/pci/pciide_cmd_reg.h> 110 #include <dev/pci/pciide_cy693_reg.h> 111 #include <dev/pci/pciide_sis_reg.h> 112 #include <dev/pci/pciide_acer_reg.h> 113 #include <dev/pci/pciide_pdc202xx_reg.h> 114 #include <dev/pci/pciide_opti_reg.h> 115 #include <dev/pci/pciide_hpt_reg.h> 116 #include <dev/pci/cy82c693var.h> 117 118 #include "opt_pciide.h" 119 120 /* inlines for reading/writing 8-bit PCI registers */ 121 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 122 int)); 123 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 124 int, u_int8_t)); 125 126 static __inline u_int8_t 127 pciide_pci_read(pc, pa, reg) 128 pci_chipset_tag_t pc; 129 pcitag_t pa; 130 int reg; 131 { 132 133 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 134 ((reg & 0x03) * 8) & 0xff); 135 } 136 137 static __inline void 138 pciide_pci_write(pc, pa, reg, val) 139 pci_chipset_tag_t pc; 140 pcitag_t pa; 141 int reg; 142 u_int8_t val; 143 { 144 pcireg_t pcival; 145 146 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 147 pcival &= ~(0xff << ((reg & 0x03) * 8)); 148 pcival |= (val << ((reg & 0x03) * 8)); 149 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 150 } 151 152 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 153 154 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 155 void piix_setup_channel __P((struct channel_softc*)); 156 void piix3_4_setup_channel __P((struct channel_softc*)); 157 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 158 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 159 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 160 161 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 162 void amd756_setup_channel __P((struct channel_softc*)); 163 164 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void apollo_setup_channel __P((struct channel_softc*)); 166 167 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 169 void cmd0643_9_setup_channel __P((struct channel_softc*)); 170 void cmd_channel_map __P((struct pci_attach_args *, 171 struct pciide_softc *, int)); 172 int cmd_pci_intr __P((void *)); 173 void cmd646_9_irqack __P((struct channel_softc *)); 174 175 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 176 void cy693_setup_channel __P((struct channel_softc*)); 177 178 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 179 void sis_setup_channel __P((struct channel_softc*)); 180 181 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void acer_setup_channel __P((struct channel_softc*)); 183 int acer_pci_intr __P((void *)); 184 185 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 186 void pdc202xx_setup_channel __P((struct channel_softc*)); 187 int pdc202xx_pci_intr __P((void *)); 188 189 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 190 void opti_setup_channel __P((struct channel_softc*)); 191 192 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void hpt_setup_channel __P((struct channel_softc*)); 194 int hpt_pci_intr __P((void *)); 195 196 void pciide_channel_dma_setup __P((struct pciide_channel *)); 197 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 198 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 199 void pciide_dma_start __P((void*, int, int)); 200 int pciide_dma_finish __P((void*, int, int, int)); 201 void pciide_irqack __P((struct channel_softc *)); 202 void pciide_print_modes __P((struct pciide_channel *)); 203 204 struct pciide_product_desc { 205 u_int32_t ide_product; 206 int ide_flags; 207 const char *ide_name; 208 /* map and setup chip, probe drives */ 209 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 210 }; 211 212 /* Flags for ide_flags */ 213 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 214 215 /* Default product description for devices not known from this controller */ 216 const struct pciide_product_desc default_product_desc = { 217 0, 218 0, 219 "Generic PCI IDE controller", 220 default_chip_map, 221 }; 222 223 const struct pciide_product_desc pciide_intel_products[] = { 224 { PCI_PRODUCT_INTEL_82092AA, 225 0, 226 "Intel 82092AA IDE controller", 227 default_chip_map, 228 }, 229 { PCI_PRODUCT_INTEL_82371FB_IDE, 230 0, 231 "Intel 82371FB IDE controller (PIIX)", 232 piix_chip_map, 233 }, 234 { PCI_PRODUCT_INTEL_82371SB_IDE, 235 0, 236 "Intel 82371SB IDE Interface (PIIX3)", 237 piix_chip_map, 238 }, 239 { PCI_PRODUCT_INTEL_82371AB_IDE, 240 0, 241 "Intel 82371AB IDE controller (PIIX4)", 242 piix_chip_map, 243 }, 244 { PCI_PRODUCT_INTEL_82440MX_IDE, 245 0, 246 "Intel 82440MX IDE controller", 247 piix_chip_map 248 }, 249 { PCI_PRODUCT_INTEL_82801AA_IDE, 250 0, 251 "Intel 82801AA IDE Controller (ICH)", 252 piix_chip_map, 253 }, 254 { PCI_PRODUCT_INTEL_82801AB_IDE, 255 0, 256 "Intel 82801AB IDE Controller (ICH0)", 257 piix_chip_map, 258 }, 259 { 0, 260 0, 261 NULL, 262 } 263 }; 264 265 const struct pciide_product_desc pciide_amd_products[] = { 266 { PCI_PRODUCT_AMD_PBC756_IDE, 267 0, 268 "Advanced Micro Devices AMD756 IDE Controller", 269 amd756_chip_map 270 }, 271 { 0, 272 0, 273 NULL, 274 } 275 }; 276 277 const struct pciide_product_desc pciide_cmd_products[] = { 278 { PCI_PRODUCT_CMDTECH_640, 279 0, 280 "CMD Technology PCI0640", 281 cmd_chip_map 282 }, 283 { PCI_PRODUCT_CMDTECH_643, 284 0, 285 "CMD Technology PCI0643", 286 cmd0643_9_chip_map, 287 }, 288 { PCI_PRODUCT_CMDTECH_646, 289 0, 290 "CMD Technology PCI0646", 291 cmd0643_9_chip_map, 292 }, 293 { PCI_PRODUCT_CMDTECH_648, 294 IDE_PCI_CLASS_OVERRIDE, 295 "CMD Technology PCI0648", 296 cmd0643_9_chip_map, 297 }, 298 { PCI_PRODUCT_CMDTECH_649, 299 IDE_PCI_CLASS_OVERRIDE, 300 "CMD Technology PCI0649", 301 cmd0643_9_chip_map, 302 }, 303 { 0, 304 0, 305 NULL, 306 } 307 }; 308 309 const struct pciide_product_desc pciide_via_products[] = { 310 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 311 0, 312 "VIA Tech VT82C586 IDE Controller", 313 apollo_chip_map, 314 }, 315 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 316 0, 317 "VIA Tech VT82C586A IDE Controller", 318 apollo_chip_map, 319 }, 320 { 0, 321 0, 322 NULL, 323 } 324 }; 325 326 const struct pciide_product_desc pciide_cypress_products[] = { 327 { PCI_PRODUCT_CONTAQ_82C693, 328 0, 329 "Cypress 82C693 IDE Controller", 330 cy693_chip_map, 331 }, 332 { 0, 333 0, 334 NULL, 335 } 336 }; 337 338 const struct pciide_product_desc pciide_sis_products[] = { 339 { PCI_PRODUCT_SIS_5597_IDE, 340 0, 341 "Silicon Integrated System 5597/5598 IDE controller", 342 sis_chip_map, 343 }, 344 { 0, 345 0, 346 NULL, 347 } 348 }; 349 350 const struct pciide_product_desc pciide_acer_products[] = { 351 { PCI_PRODUCT_ALI_M5229, 352 0, 353 "Acer Labs M5229 UDMA IDE Controller", 354 acer_chip_map, 355 }, 356 { 0, 357 0, 358 NULL, 359 } 360 }; 361 362 const struct pciide_product_desc pciide_promise_products[] = { 363 { PCI_PRODUCT_PROMISE_ULTRA33, 364 IDE_PCI_CLASS_OVERRIDE, 365 "Promise Ultra33/ATA Bus Master IDE Accelerator", 366 pdc202xx_chip_map, 367 }, 368 { PCI_PRODUCT_PROMISE_ULTRA66, 369 IDE_PCI_CLASS_OVERRIDE, 370 "Promise Ultra66/ATA Bus Master IDE Accelerator", 371 pdc202xx_chip_map, 372 }, 373 { PCI_PRODUCT_PROMISE_ULTRA100, 374 IDE_PCI_CLASS_OVERRIDE, 375 "Promise Ultra100/ATA Bus Master IDE Accelerator", 376 pdc202xx_chip_map, 377 }, 378 { PCI_PRODUCT_PROMISE_ULTRA100X, 379 IDE_PCI_CLASS_OVERRIDE, 380 "Promise Ultra100/ATA Bus Master IDE Accelerator", 381 pdc202xx_chip_map, 382 }, 383 { 0, 384 0, 385 NULL, 386 } 387 }; 388 389 const struct pciide_product_desc pciide_opti_products[] = { 390 { PCI_PRODUCT_OPTI_82C621, 391 0, 392 "OPTi 82c621 PCI IDE controller", 393 opti_chip_map, 394 }, 395 { PCI_PRODUCT_OPTI_82C568, 396 0, 397 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 398 opti_chip_map, 399 }, 400 { PCI_PRODUCT_OPTI_82D568, 401 0, 402 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 403 opti_chip_map, 404 }, 405 { 0, 406 0, 407 NULL, 408 } 409 }; 410 411 const struct pciide_product_desc pciide_triones_products[] = { 412 { PCI_PRODUCT_TRIONES_HPT366, 413 IDE_PCI_CLASS_OVERRIDE, 414 "Triones/Highpoint HPT366/370 IDE Controller", 415 hpt_chip_map, 416 }, 417 { 0, 418 0, 419 NULL, 420 } 421 }; 422 423 struct pciide_vendor_desc { 424 u_int32_t ide_vendor; 425 const struct pciide_product_desc *ide_products; 426 }; 427 428 const struct pciide_vendor_desc pciide_vendors[] = { 429 { PCI_VENDOR_INTEL, pciide_intel_products }, 430 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 431 { PCI_VENDOR_VIATECH, pciide_via_products }, 432 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 433 { PCI_VENDOR_SIS, pciide_sis_products }, 434 { PCI_VENDOR_ALI, pciide_acer_products }, 435 { PCI_VENDOR_PROMISE, pciide_promise_products }, 436 { PCI_VENDOR_AMD, pciide_amd_products }, 437 { PCI_VENDOR_OPTI, pciide_opti_products }, 438 { PCI_VENDOR_TRIONES, pciide_triones_products }, 439 { 0, NULL } 440 }; 441 442 /* options passed via the 'flags' config keyword */ 443 #define PCIIDE_OPTIONS_DMA 0x01 444 445 int pciide_match __P((struct device *, struct cfdata *, void *)); 446 void pciide_attach __P((struct device *, struct device *, void *)); 447 448 struct cfattach pciide_ca = { 449 sizeof(struct pciide_softc), pciide_match, pciide_attach 450 }; 451 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 452 int pciide_mapregs_compat __P(( struct pci_attach_args *, 453 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 454 int pciide_mapregs_native __P((struct pci_attach_args *, 455 struct pciide_channel *, bus_size_t *, bus_size_t *, 456 int (*pci_intr) __P((void *)))); 457 void pciide_mapreg_dma __P((struct pciide_softc *, 458 struct pci_attach_args *)); 459 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 460 void pciide_mapchan __P((struct pci_attach_args *, 461 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 462 int (*pci_intr) __P((void *)))); 463 int pciide_chan_candisable __P((struct pciide_channel *)); 464 void pciide_map_compat_intr __P(( struct pci_attach_args *, 465 struct pciide_channel *, int, int)); 466 int pciide_print __P((void *, const char *pnp)); 467 int pciide_compat_intr __P((void *)); 468 int pciide_pci_intr __P((void *)); 469 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 470 471 const struct pciide_product_desc * 472 pciide_lookup_product(id) 473 u_int32_t id; 474 { 475 const struct pciide_product_desc *pp; 476 const struct pciide_vendor_desc *vp; 477 478 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 479 if (PCI_VENDOR(id) == vp->ide_vendor) 480 break; 481 482 if ((pp = vp->ide_products) == NULL) 483 return NULL; 484 485 for (; pp->ide_name != NULL; pp++) 486 if (PCI_PRODUCT(id) == pp->ide_product) 487 break; 488 489 if (pp->ide_name == NULL) 490 return NULL; 491 return pp; 492 } 493 494 int 495 pciide_match(parent, match, aux) 496 struct device *parent; 497 struct cfdata *match; 498 void *aux; 499 { 500 struct pci_attach_args *pa = aux; 501 const struct pciide_product_desc *pp; 502 503 /* 504 * Check the ID register to see that it's a PCI IDE controller. 505 * If it is, we assume that we can deal with it; it _should_ 506 * work in a standardized way... 507 */ 508 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 509 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 510 return (1); 511 } 512 513 /* 514 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 515 * controllers. Let see if we can deal with it anyway. 516 */ 517 pp = pciide_lookup_product(pa->pa_id); 518 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 519 return (1); 520 } 521 522 return (0); 523 } 524 525 void 526 pciide_attach(parent, self, aux) 527 struct device *parent, *self; 528 void *aux; 529 { 530 struct pci_attach_args *pa = aux; 531 pci_chipset_tag_t pc = pa->pa_pc; 532 pcitag_t tag = pa->pa_tag; 533 struct pciide_softc *sc = (struct pciide_softc *)self; 534 pcireg_t csr; 535 char devinfo[256]; 536 const char *displaydev; 537 538 sc->sc_pp = pciide_lookup_product(pa->pa_id); 539 if (sc->sc_pp == NULL) { 540 sc->sc_pp = &default_product_desc; 541 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 542 displaydev = devinfo; 543 } else 544 displaydev = sc->sc_pp->ide_name; 545 546 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 547 548 sc->sc_pc = pa->pa_pc; 549 sc->sc_tag = pa->pa_tag; 550 #ifdef WDCDEBUG 551 if (wdcdebug_pciide_mask & DEBUG_PROBE) 552 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 553 #endif 554 sc->sc_pp->chip_map(sc, pa); 555 556 if (sc->sc_dma_ok) { 557 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 558 csr |= PCI_COMMAND_MASTER_ENABLE; 559 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 560 } 561 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 562 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 563 } 564 565 /* tell wether the chip is enabled or not */ 566 int 567 pciide_chipen(sc, pa) 568 struct pciide_softc *sc; 569 struct pci_attach_args *pa; 570 { 571 pcireg_t csr; 572 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 573 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 574 PCI_COMMAND_STATUS_REG); 575 printf("%s: device disabled (at %s)\n", 576 sc->sc_wdcdev.sc_dev.dv_xname, 577 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 578 "device" : "bridge"); 579 return 0; 580 } 581 return 1; 582 } 583 584 int 585 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 586 struct pci_attach_args *pa; 587 struct pciide_channel *cp; 588 int compatchan; 589 bus_size_t *cmdsizep, *ctlsizep; 590 { 591 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 592 struct channel_softc *wdc_cp = &cp->wdc_channel; 593 594 cp->compat = 1; 595 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 596 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 597 598 wdc_cp->cmd_iot = pa->pa_iot; 599 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 600 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 601 printf("%s: couldn't map %s channel cmd regs\n", 602 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 603 return (0); 604 } 605 606 wdc_cp->ctl_iot = pa->pa_iot; 607 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 608 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 609 printf("%s: couldn't map %s channel ctl regs\n", 610 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 611 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 612 PCIIDE_COMPAT_CMD_SIZE); 613 return (0); 614 } 615 616 return (1); 617 } 618 619 int 620 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 621 struct pci_attach_args * pa; 622 struct pciide_channel *cp; 623 bus_size_t *cmdsizep, *ctlsizep; 624 int (*pci_intr) __P((void *)); 625 { 626 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 627 struct channel_softc *wdc_cp = &cp->wdc_channel; 628 const char *intrstr; 629 pci_intr_handle_t intrhandle; 630 631 cp->compat = 0; 632 633 if (sc->sc_pci_ih == NULL) { 634 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 635 pa->pa_intrline, &intrhandle) != 0) { 636 printf("%s: couldn't map native-PCI interrupt\n", 637 sc->sc_wdcdev.sc_dev.dv_xname); 638 return 0; 639 } 640 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 641 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 642 intrhandle, IPL_BIO, pci_intr, sc); 643 if (sc->sc_pci_ih != NULL) { 644 printf("%s: using %s for native-PCI interrupt\n", 645 sc->sc_wdcdev.sc_dev.dv_xname, 646 intrstr ? intrstr : "unknown interrupt"); 647 } else { 648 printf("%s: couldn't establish native-PCI interrupt", 649 sc->sc_wdcdev.sc_dev.dv_xname); 650 if (intrstr != NULL) 651 printf(" at %s", intrstr); 652 printf("\n"); 653 return 0; 654 } 655 } 656 cp->ih = sc->sc_pci_ih; 657 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 658 PCI_MAPREG_TYPE_IO, 0, 659 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 660 printf("%s: couldn't map %s channel cmd regs\n", 661 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 662 return 0; 663 } 664 665 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 666 PCI_MAPREG_TYPE_IO, 0, 667 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 668 printf("%s: couldn't map %s channel ctl regs\n", 669 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 670 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 671 return 0; 672 } 673 return (1); 674 } 675 676 void 677 pciide_mapreg_dma(sc, pa) 678 struct pciide_softc *sc; 679 struct pci_attach_args *pa; 680 { 681 pcireg_t maptype; 682 683 /* 684 * Map DMA registers 685 * 686 * Note that sc_dma_ok is the right variable to test to see if 687 * DMA can be done. If the interface doesn't support DMA, 688 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 689 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 690 * non-zero if the interface supports DMA and the registers 691 * could be mapped. 692 * 693 * XXX Note that despite the fact that the Bus Master IDE specs 694 * XXX say that "The bus master IDE function uses 16 bytes of IO 695 * XXX space," some controllers (at least the United 696 * XXX Microelectronics UM8886BF) place it in memory space. 697 */ 698 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 699 PCIIDE_REG_BUS_MASTER_DMA); 700 701 switch (maptype) { 702 case PCI_MAPREG_TYPE_IO: 703 case PCI_MAPREG_MEM_TYPE_32BIT: 704 sc->sc_dma_ok = (pci_mapreg_map(pa, 705 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 706 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 707 sc->sc_dmat = pa->pa_dmat; 708 if (sc->sc_dma_ok == 0) { 709 printf(", but unused (couldn't map registers)"); 710 } else { 711 sc->sc_wdcdev.dma_arg = sc; 712 sc->sc_wdcdev.dma_init = pciide_dma_init; 713 sc->sc_wdcdev.dma_start = pciide_dma_start; 714 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 715 } 716 break; 717 718 default: 719 sc->sc_dma_ok = 0; 720 printf(", but unsupported register maptype (0x%x)", maptype); 721 } 722 } 723 724 int 725 pciide_compat_intr(arg) 726 void *arg; 727 { 728 struct pciide_channel *cp = arg; 729 730 #ifdef DIAGNOSTIC 731 /* should only be called for a compat channel */ 732 if (cp->compat == 0) 733 panic("pciide compat intr called for non-compat chan %p\n", cp); 734 #endif 735 return (wdcintr(&cp->wdc_channel)); 736 } 737 738 int 739 pciide_pci_intr(arg) 740 void *arg; 741 { 742 struct pciide_softc *sc = arg; 743 struct pciide_channel *cp; 744 struct channel_softc *wdc_cp; 745 int i, rv, crv; 746 747 rv = 0; 748 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 749 cp = &sc->pciide_channels[i]; 750 wdc_cp = &cp->wdc_channel; 751 752 /* If a compat channel skip. */ 753 if (cp->compat) 754 continue; 755 /* if this channel not waiting for intr, skip */ 756 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 757 continue; 758 759 crv = wdcintr(wdc_cp); 760 if (crv == 0) 761 ; /* leave rv alone */ 762 else if (crv == 1) 763 rv = 1; /* claim the intr */ 764 else if (rv == 0) /* crv should be -1 in this case */ 765 rv = crv; /* if we've done no better, take it */ 766 } 767 return (rv); 768 } 769 770 void 771 pciide_channel_dma_setup(cp) 772 struct pciide_channel *cp; 773 { 774 int drive; 775 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 776 struct ata_drive_datas *drvp; 777 778 for (drive = 0; drive < 2; drive++) { 779 drvp = &cp->wdc_channel.ch_drive[drive]; 780 /* If no drive, skip */ 781 if ((drvp->drive_flags & DRIVE) == 0) 782 continue; 783 /* setup DMA if needed */ 784 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 785 (drvp->drive_flags & DRIVE_UDMA) == 0) || 786 sc->sc_dma_ok == 0) { 787 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 788 continue; 789 } 790 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 791 != 0) { 792 /* Abort DMA setup */ 793 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 794 continue; 795 } 796 } 797 } 798 799 int 800 pciide_dma_table_setup(sc, channel, drive) 801 struct pciide_softc *sc; 802 int channel, drive; 803 { 804 bus_dma_segment_t seg; 805 int error, rseg; 806 const bus_size_t dma_table_size = 807 sizeof(struct idedma_table) * NIDEDMA_TABLES; 808 struct pciide_dma_maps *dma_maps = 809 &sc->pciide_channels[channel].dma_maps[drive]; 810 811 /* If table was already allocated, just return */ 812 if (dma_maps->dma_table) 813 return 0; 814 815 /* Allocate memory for the DMA tables and map it */ 816 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 817 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 818 BUS_DMA_NOWAIT)) != 0) { 819 printf("%s:%d: unable to allocate table DMA for " 820 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 821 channel, drive, error); 822 return error; 823 } 824 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 825 dma_table_size, 826 (caddr_t *)&dma_maps->dma_table, 827 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 828 printf("%s:%d: unable to map table DMA for" 829 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 830 channel, drive, error); 831 return error; 832 } 833 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 834 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 835 seg.ds_addr), DEBUG_PROBE); 836 837 /* Create and load table DMA map for this disk */ 838 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 839 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 840 &dma_maps->dmamap_table)) != 0) { 841 printf("%s:%d: unable to create table DMA map for " 842 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 843 channel, drive, error); 844 return error; 845 } 846 if ((error = bus_dmamap_load(sc->sc_dmat, 847 dma_maps->dmamap_table, 848 dma_maps->dma_table, 849 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 850 printf("%s:%d: unable to load table DMA map for " 851 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 852 channel, drive, error); 853 return error; 854 } 855 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 856 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 857 /* Create a xfer DMA map for this drive */ 858 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 859 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 860 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 861 &dma_maps->dmamap_xfer)) != 0) { 862 printf("%s:%d: unable to create xfer DMA map for " 863 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 864 channel, drive, error); 865 return error; 866 } 867 return 0; 868 } 869 870 int 871 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 872 void *v; 873 int channel, drive; 874 void *databuf; 875 size_t datalen; 876 int flags; 877 { 878 struct pciide_softc *sc = v; 879 int error, seg; 880 struct pciide_dma_maps *dma_maps = 881 &sc->pciide_channels[channel].dma_maps[drive]; 882 883 error = bus_dmamap_load(sc->sc_dmat, 884 dma_maps->dmamap_xfer, 885 databuf, datalen, NULL, BUS_DMA_NOWAIT); 886 if (error) { 887 printf("%s:%d: unable to load xfer DMA map for" 888 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 889 channel, drive, error); 890 return error; 891 } 892 893 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 894 dma_maps->dmamap_xfer->dm_mapsize, 895 (flags & WDC_DMA_READ) ? 896 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 897 898 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 899 #ifdef DIAGNOSTIC 900 /* A segment must not cross a 64k boundary */ 901 { 902 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 903 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 904 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 905 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 906 printf("pciide_dma: segment %d physical addr 0x%lx" 907 " len 0x%lx not properly aligned\n", 908 seg, phys, len); 909 panic("pciide_dma: buf align"); 910 } 911 } 912 #endif 913 dma_maps->dma_table[seg].base_addr = 914 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 915 dma_maps->dma_table[seg].byte_count = 916 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 917 IDEDMA_BYTE_COUNT_MASK); 918 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 919 seg, le32toh(dma_maps->dma_table[seg].byte_count), 920 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 921 922 } 923 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 924 htole32(IDEDMA_BYTE_COUNT_EOT); 925 926 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 927 dma_maps->dmamap_table->dm_mapsize, 928 BUS_DMASYNC_PREWRITE); 929 930 /* Maps are ready. Start DMA function */ 931 #ifdef DIAGNOSTIC 932 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 933 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 934 dma_maps->dmamap_table->dm_segs[0].ds_addr); 935 panic("pciide_dma_init: table align"); 936 } 937 #endif 938 939 /* Clear status bits */ 940 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 941 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 942 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 943 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 944 /* Write table addr */ 945 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 946 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 947 dma_maps->dmamap_table->dm_segs[0].ds_addr); 948 /* set read/write */ 949 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 950 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 951 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 952 /* remember flags */ 953 dma_maps->dma_flags = flags; 954 return 0; 955 } 956 957 void 958 pciide_dma_start(v, channel, drive) 959 void *v; 960 int channel, drive; 961 { 962 struct pciide_softc *sc = v; 963 964 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 965 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 966 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 967 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 968 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 969 } 970 971 int 972 pciide_dma_finish(v, channel, drive, force) 973 void *v; 974 int channel, drive; 975 int force; 976 { 977 struct pciide_softc *sc = v; 978 u_int8_t status; 979 int error = 0; 980 struct pciide_dma_maps *dma_maps = 981 &sc->pciide_channels[channel].dma_maps[drive]; 982 983 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 984 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 985 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 986 DEBUG_XFERS); 987 988 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 989 return WDC_DMAST_NOIRQ; 990 991 /* stop DMA channel */ 992 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 993 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 994 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 995 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 996 997 /* Unload the map of the data buffer */ 998 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 999 dma_maps->dmamap_xfer->dm_mapsize, 1000 (dma_maps->dma_flags & WDC_DMA_READ) ? 1001 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1002 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1003 1004 if ((status & IDEDMA_CTL_ERR) != 0) { 1005 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1006 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1007 error |= WDC_DMAST_ERR; 1008 } 1009 1010 if ((status & IDEDMA_CTL_INTR) == 0) { 1011 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1012 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1013 drive, status); 1014 error |= WDC_DMAST_NOIRQ; 1015 } 1016 1017 if ((status & IDEDMA_CTL_ACT) != 0) { 1018 /* data underrun, may be a valid condition for ATAPI */ 1019 error |= WDC_DMAST_UNDER; 1020 } 1021 return error; 1022 } 1023 1024 void 1025 pciide_irqack(chp) 1026 struct channel_softc *chp; 1027 { 1028 struct pciide_channel *cp = (struct pciide_channel*)chp; 1029 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1030 1031 /* clear status bits in IDE DMA registers */ 1032 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1033 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1034 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1035 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1036 } 1037 1038 /* some common code used by several chip_map */ 1039 int 1040 pciide_chansetup(sc, channel, interface) 1041 struct pciide_softc *sc; 1042 int channel; 1043 pcireg_t interface; 1044 { 1045 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1046 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1047 cp->name = PCIIDE_CHANNEL_NAME(channel); 1048 cp->wdc_channel.channel = channel; 1049 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1050 cp->wdc_channel.ch_queue = 1051 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1052 if (cp->wdc_channel.ch_queue == NULL) { 1053 printf("%s %s channel: " 1054 "can't allocate memory for command queue", 1055 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1056 return 0; 1057 } 1058 printf("%s: %s channel %s to %s mode\n", 1059 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1060 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1061 "configured" : "wired", 1062 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1063 "native-PCI" : "compatibility"); 1064 return 1; 1065 } 1066 1067 /* some common code used by several chip channel_map */ 1068 void 1069 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1070 struct pci_attach_args *pa; 1071 struct pciide_channel *cp; 1072 pcireg_t interface; 1073 bus_size_t *cmdsizep, *ctlsizep; 1074 int (*pci_intr) __P((void *)); 1075 { 1076 struct channel_softc *wdc_cp = &cp->wdc_channel; 1077 1078 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1079 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1080 pci_intr); 1081 else 1082 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1083 wdc_cp->channel, cmdsizep, ctlsizep); 1084 1085 if (cp->hw_ok == 0) 1086 return; 1087 wdc_cp->data32iot = wdc_cp->cmd_iot; 1088 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1089 wdcattach(wdc_cp); 1090 } 1091 1092 /* 1093 * Generic code to call to know if a channel can be disabled. Return 1 1094 * if channel can be disabled, 0 if not 1095 */ 1096 int 1097 pciide_chan_candisable(cp) 1098 struct pciide_channel *cp; 1099 { 1100 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1101 struct channel_softc *wdc_cp = &cp->wdc_channel; 1102 1103 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1104 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1105 printf("%s: disabling %s channel (no drives)\n", 1106 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1107 cp->hw_ok = 0; 1108 return 1; 1109 } 1110 return 0; 1111 } 1112 1113 /* 1114 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1115 * Set hw_ok=0 on failure 1116 */ 1117 void 1118 pciide_map_compat_intr(pa, cp, compatchan, interface) 1119 struct pci_attach_args *pa; 1120 struct pciide_channel *cp; 1121 int compatchan, interface; 1122 { 1123 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1124 struct channel_softc *wdc_cp = &cp->wdc_channel; 1125 1126 if (cp->hw_ok == 0) 1127 return; 1128 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1129 return; 1130 1131 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1132 pa, compatchan, pciide_compat_intr, cp); 1133 if (cp->ih == NULL) { 1134 printf("%s: no compatibility interrupt for use by %s " 1135 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1136 cp->hw_ok = 0; 1137 } 1138 } 1139 1140 void 1141 pciide_print_modes(cp) 1142 struct pciide_channel *cp; 1143 { 1144 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1145 int drive; 1146 struct channel_softc *chp; 1147 struct ata_drive_datas *drvp; 1148 1149 chp = &cp->wdc_channel; 1150 for (drive = 0; drive < 2; drive++) { 1151 drvp = &chp->ch_drive[drive]; 1152 if ((drvp->drive_flags & DRIVE) == 0) 1153 continue; 1154 printf("%s(%s:%d:%d): using PIO mode %d", 1155 drvp->drv_softc->dv_xname, 1156 sc->sc_wdcdev.sc_dev.dv_xname, 1157 chp->channel, drive, drvp->PIO_mode); 1158 if (drvp->drive_flags & DRIVE_DMA) 1159 printf(", DMA mode %d", drvp->DMA_mode); 1160 if (drvp->drive_flags & DRIVE_UDMA) 1161 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1162 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1163 printf(" (using DMA data transfers)"); 1164 printf("\n"); 1165 } 1166 } 1167 1168 void 1169 default_chip_map(sc, pa) 1170 struct pciide_softc *sc; 1171 struct pci_attach_args *pa; 1172 { 1173 struct pciide_channel *cp; 1174 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1175 pcireg_t csr; 1176 int channel, drive; 1177 struct ata_drive_datas *drvp; 1178 u_int8_t idedma_ctl; 1179 bus_size_t cmdsize, ctlsize; 1180 char *failreason; 1181 1182 if (pciide_chipen(sc, pa) == 0) 1183 return; 1184 1185 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1186 printf("%s: bus-master DMA support present", 1187 sc->sc_wdcdev.sc_dev.dv_xname); 1188 if (sc->sc_pp == &default_product_desc && 1189 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1190 PCIIDE_OPTIONS_DMA) == 0) { 1191 printf(", but unused (no driver support)"); 1192 sc->sc_dma_ok = 0; 1193 } else { 1194 pciide_mapreg_dma(sc, pa); 1195 if (sc->sc_dma_ok != 0) 1196 printf(", used without full driver " 1197 "support"); 1198 } 1199 } else { 1200 printf("%s: hardware does not support DMA", 1201 sc->sc_wdcdev.sc_dev.dv_xname); 1202 sc->sc_dma_ok = 0; 1203 } 1204 printf("\n"); 1205 if (sc->sc_dma_ok) { 1206 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1207 sc->sc_wdcdev.irqack = pciide_irqack; 1208 } 1209 sc->sc_wdcdev.PIO_cap = 0; 1210 sc->sc_wdcdev.DMA_cap = 0; 1211 1212 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1213 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1214 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1215 1216 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1217 cp = &sc->pciide_channels[channel]; 1218 if (pciide_chansetup(sc, channel, interface) == 0) 1219 continue; 1220 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1221 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1222 &ctlsize, pciide_pci_intr); 1223 } else { 1224 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1225 channel, &cmdsize, &ctlsize); 1226 } 1227 if (cp->hw_ok == 0) 1228 continue; 1229 /* 1230 * Check to see if something appears to be there. 1231 */ 1232 failreason = NULL; 1233 if (!wdcprobe(&cp->wdc_channel)) { 1234 failreason = "not responding; disabled or no drives?"; 1235 goto next; 1236 } 1237 /* 1238 * Now, make sure it's actually attributable to this PCI IDE 1239 * channel by trying to access the channel again while the 1240 * PCI IDE controller's I/O space is disabled. (If the 1241 * channel no longer appears to be there, it belongs to 1242 * this controller.) YUCK! 1243 */ 1244 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1245 PCI_COMMAND_STATUS_REG); 1246 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1247 csr & ~PCI_COMMAND_IO_ENABLE); 1248 if (wdcprobe(&cp->wdc_channel)) 1249 failreason = "other hardware responding at addresses"; 1250 pci_conf_write(sc->sc_pc, sc->sc_tag, 1251 PCI_COMMAND_STATUS_REG, csr); 1252 next: 1253 if (failreason) { 1254 printf("%s: %s channel ignored (%s)\n", 1255 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1256 failreason); 1257 cp->hw_ok = 0; 1258 bus_space_unmap(cp->wdc_channel.cmd_iot, 1259 cp->wdc_channel.cmd_ioh, cmdsize); 1260 bus_space_unmap(cp->wdc_channel.ctl_iot, 1261 cp->wdc_channel.ctl_ioh, ctlsize); 1262 } else { 1263 pciide_map_compat_intr(pa, cp, channel, interface); 1264 } 1265 if (cp->hw_ok) { 1266 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1267 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1268 wdcattach(&cp->wdc_channel); 1269 } 1270 } 1271 1272 if (sc->sc_dma_ok == 0) 1273 return; 1274 1275 /* Allocate DMA maps */ 1276 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1277 idedma_ctl = 0; 1278 cp = &sc->pciide_channels[channel]; 1279 for (drive = 0; drive < 2; drive++) { 1280 drvp = &cp->wdc_channel.ch_drive[drive]; 1281 /* If no drive, skip */ 1282 if ((drvp->drive_flags & DRIVE) == 0) 1283 continue; 1284 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1285 continue; 1286 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1287 /* Abort DMA setup */ 1288 printf("%s:%d:%d: can't allocate DMA maps, " 1289 "using PIO transfers\n", 1290 sc->sc_wdcdev.sc_dev.dv_xname, 1291 channel, drive); 1292 drvp->drive_flags &= ~DRIVE_DMA; 1293 } 1294 printf("%s:%d:%d: using DMA data transfers\n", 1295 sc->sc_wdcdev.sc_dev.dv_xname, 1296 channel, drive); 1297 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1298 } 1299 if (idedma_ctl != 0) { 1300 /* Add software bits in status register */ 1301 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1302 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1303 idedma_ctl); 1304 } 1305 } 1306 } 1307 1308 void 1309 piix_chip_map(sc, pa) 1310 struct pciide_softc *sc; 1311 struct pci_attach_args *pa; 1312 { 1313 struct pciide_channel *cp; 1314 int channel; 1315 u_int32_t idetim; 1316 bus_size_t cmdsize, ctlsize; 1317 1318 if (pciide_chipen(sc, pa) == 0) 1319 return; 1320 1321 printf("%s: bus-master DMA support present", 1322 sc->sc_wdcdev.sc_dev.dv_xname); 1323 pciide_mapreg_dma(sc, pa); 1324 printf("\n"); 1325 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1326 WDC_CAPABILITY_MODE; 1327 if (sc->sc_dma_ok) { 1328 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1329 sc->sc_wdcdev.irqack = pciide_irqack; 1330 switch(sc->sc_pp->ide_product) { 1331 case PCI_PRODUCT_INTEL_82371AB_IDE: 1332 case PCI_PRODUCT_INTEL_82440MX_IDE: 1333 case PCI_PRODUCT_INTEL_82801AA_IDE: 1334 case PCI_PRODUCT_INTEL_82801AB_IDE: 1335 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1336 } 1337 } 1338 sc->sc_wdcdev.PIO_cap = 4; 1339 sc->sc_wdcdev.DMA_cap = 2; 1340 sc->sc_wdcdev.UDMA_cap = 1341 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1342 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1343 sc->sc_wdcdev.set_modes = piix_setup_channel; 1344 else 1345 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1346 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1347 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1348 1349 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1350 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1351 DEBUG_PROBE); 1352 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1353 WDCDEBUG_PRINT((", sidetim=0x%x", 1354 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1355 DEBUG_PROBE); 1356 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1357 WDCDEBUG_PRINT((", udamreg 0x%x", 1358 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1359 DEBUG_PROBE); 1360 } 1361 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1362 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1363 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1364 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1365 DEBUG_PROBE); 1366 } 1367 1368 } 1369 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1370 1371 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1372 cp = &sc->pciide_channels[channel]; 1373 /* PIIX is compat-only */ 1374 if (pciide_chansetup(sc, channel, 0) == 0) 1375 continue; 1376 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1377 if ((PIIX_IDETIM_READ(idetim, channel) & 1378 PIIX_IDETIM_IDE) == 0) { 1379 printf("%s: %s channel ignored (disabled)\n", 1380 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1381 continue; 1382 } 1383 /* PIIX are compat-only pciide devices */ 1384 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1385 if (cp->hw_ok == 0) 1386 continue; 1387 if (pciide_chan_candisable(cp)) { 1388 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1389 channel); 1390 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1391 idetim); 1392 } 1393 pciide_map_compat_intr(pa, cp, channel, 0); 1394 if (cp->hw_ok == 0) 1395 continue; 1396 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1397 } 1398 1399 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1400 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1401 DEBUG_PROBE); 1402 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1403 WDCDEBUG_PRINT((", sidetim=0x%x", 1404 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1405 DEBUG_PROBE); 1406 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1407 WDCDEBUG_PRINT((", udamreg 0x%x", 1408 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1409 DEBUG_PROBE); 1410 } 1411 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1412 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1413 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1414 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1415 DEBUG_PROBE); 1416 } 1417 } 1418 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1419 } 1420 1421 void 1422 piix_setup_channel(chp) 1423 struct channel_softc *chp; 1424 { 1425 u_int8_t mode[2], drive; 1426 u_int32_t oidetim, idetim, idedma_ctl; 1427 struct pciide_channel *cp = (struct pciide_channel*)chp; 1428 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1429 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1430 1431 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1432 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1433 idedma_ctl = 0; 1434 1435 /* set up new idetim: Enable IDE registers decode */ 1436 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1437 chp->channel); 1438 1439 /* setup DMA */ 1440 pciide_channel_dma_setup(cp); 1441 1442 /* 1443 * Here we have to mess up with drives mode: PIIX can't have 1444 * different timings for master and slave drives. 1445 * We need to find the best combination. 1446 */ 1447 1448 /* If both drives supports DMA, take the lower mode */ 1449 if ((drvp[0].drive_flags & DRIVE_DMA) && 1450 (drvp[1].drive_flags & DRIVE_DMA)) { 1451 mode[0] = mode[1] = 1452 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1453 drvp[0].DMA_mode = mode[0]; 1454 drvp[1].DMA_mode = mode[1]; 1455 goto ok; 1456 } 1457 /* 1458 * If only one drive supports DMA, use its mode, and 1459 * put the other one in PIO mode 0 if mode not compatible 1460 */ 1461 if (drvp[0].drive_flags & DRIVE_DMA) { 1462 mode[0] = drvp[0].DMA_mode; 1463 mode[1] = drvp[1].PIO_mode; 1464 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1465 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1466 mode[1] = drvp[1].PIO_mode = 0; 1467 goto ok; 1468 } 1469 if (drvp[1].drive_flags & DRIVE_DMA) { 1470 mode[1] = drvp[1].DMA_mode; 1471 mode[0] = drvp[0].PIO_mode; 1472 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1473 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1474 mode[0] = drvp[0].PIO_mode = 0; 1475 goto ok; 1476 } 1477 /* 1478 * If both drives are not DMA, takes the lower mode, unless 1479 * one of them is PIO mode < 2 1480 */ 1481 if (drvp[0].PIO_mode < 2) { 1482 mode[0] = drvp[0].PIO_mode = 0; 1483 mode[1] = drvp[1].PIO_mode; 1484 } else if (drvp[1].PIO_mode < 2) { 1485 mode[1] = drvp[1].PIO_mode = 0; 1486 mode[0] = drvp[0].PIO_mode; 1487 } else { 1488 mode[0] = mode[1] = 1489 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1490 drvp[0].PIO_mode = mode[0]; 1491 drvp[1].PIO_mode = mode[1]; 1492 } 1493 ok: /* The modes are setup */ 1494 for (drive = 0; drive < 2; drive++) { 1495 if (drvp[drive].drive_flags & DRIVE_DMA) { 1496 idetim |= piix_setup_idetim_timings( 1497 mode[drive], 1, chp->channel); 1498 goto end; 1499 } 1500 } 1501 /* If we are there, none of the drives are DMA */ 1502 if (mode[0] >= 2) 1503 idetim |= piix_setup_idetim_timings( 1504 mode[0], 0, chp->channel); 1505 else 1506 idetim |= piix_setup_idetim_timings( 1507 mode[1], 0, chp->channel); 1508 end: /* 1509 * timing mode is now set up in the controller. Enable 1510 * it per-drive 1511 */ 1512 for (drive = 0; drive < 2; drive++) { 1513 /* If no drive, skip */ 1514 if ((drvp[drive].drive_flags & DRIVE) == 0) 1515 continue; 1516 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1517 if (drvp[drive].drive_flags & DRIVE_DMA) 1518 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1519 } 1520 if (idedma_ctl != 0) { 1521 /* Add software bits in status register */ 1522 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1523 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1524 idedma_ctl); 1525 } 1526 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1527 pciide_print_modes(cp); 1528 } 1529 1530 void 1531 piix3_4_setup_channel(chp) 1532 struct channel_softc *chp; 1533 { 1534 struct ata_drive_datas *drvp; 1535 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1536 struct pciide_channel *cp = (struct pciide_channel*)chp; 1537 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1538 int drive; 1539 int channel = chp->channel; 1540 1541 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1542 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1543 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1544 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1545 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1546 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1547 PIIX_SIDETIM_RTC_MASK(channel)); 1548 1549 idedma_ctl = 0; 1550 /* If channel disabled, no need to go further */ 1551 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1552 return; 1553 /* set up new idetim: Enable IDE registers decode */ 1554 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1555 1556 /* setup DMA if needed */ 1557 pciide_channel_dma_setup(cp); 1558 1559 for (drive = 0; drive < 2; drive++) { 1560 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1561 PIIX_UDMATIM_SET(0x3, channel, drive)); 1562 drvp = &chp->ch_drive[drive]; 1563 /* If no drive, skip */ 1564 if ((drvp->drive_flags & DRIVE) == 0) 1565 continue; 1566 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1567 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1568 goto pio; 1569 1570 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1571 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1572 ideconf |= PIIX_CONFIG_PINGPONG; 1573 } 1574 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1575 /* setup Ultra/66 */ 1576 if (drvp->UDMA_mode > 2 && 1577 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1578 drvp->UDMA_mode = 2; 1579 if (drvp->UDMA_mode > 2) 1580 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1581 else 1582 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1583 } 1584 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1585 (drvp->drive_flags & DRIVE_UDMA)) { 1586 /* use Ultra/DMA */ 1587 drvp->drive_flags &= ~DRIVE_DMA; 1588 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1589 udmareg |= PIIX_UDMATIM_SET( 1590 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1591 } else { 1592 /* use Multiword DMA */ 1593 drvp->drive_flags &= ~DRIVE_UDMA; 1594 if (drive == 0) { 1595 idetim |= piix_setup_idetim_timings( 1596 drvp->DMA_mode, 1, channel); 1597 } else { 1598 sidetim |= piix_setup_sidetim_timings( 1599 drvp->DMA_mode, 1, channel); 1600 idetim =PIIX_IDETIM_SET(idetim, 1601 PIIX_IDETIM_SITRE, channel); 1602 } 1603 } 1604 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1605 1606 pio: /* use PIO mode */ 1607 idetim |= piix_setup_idetim_drvs(drvp); 1608 if (drive == 0) { 1609 idetim |= piix_setup_idetim_timings( 1610 drvp->PIO_mode, 0, channel); 1611 } else { 1612 sidetim |= piix_setup_sidetim_timings( 1613 drvp->PIO_mode, 0, channel); 1614 idetim =PIIX_IDETIM_SET(idetim, 1615 PIIX_IDETIM_SITRE, channel); 1616 } 1617 } 1618 if (idedma_ctl != 0) { 1619 /* Add software bits in status register */ 1620 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1621 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1622 idedma_ctl); 1623 } 1624 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1625 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1626 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1627 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1628 pciide_print_modes(cp); 1629 } 1630 1631 1632 /* setup ISP and RTC fields, based on mode */ 1633 static u_int32_t 1634 piix_setup_idetim_timings(mode, dma, channel) 1635 u_int8_t mode; 1636 u_int8_t dma; 1637 u_int8_t channel; 1638 { 1639 1640 if (dma) 1641 return PIIX_IDETIM_SET(0, 1642 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1643 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1644 channel); 1645 else 1646 return PIIX_IDETIM_SET(0, 1647 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1648 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1649 channel); 1650 } 1651 1652 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1653 static u_int32_t 1654 piix_setup_idetim_drvs(drvp) 1655 struct ata_drive_datas *drvp; 1656 { 1657 u_int32_t ret = 0; 1658 struct channel_softc *chp = drvp->chnl_softc; 1659 u_int8_t channel = chp->channel; 1660 u_int8_t drive = drvp->drive; 1661 1662 /* 1663 * If drive is using UDMA, timings setups are independant 1664 * So just check DMA and PIO here. 1665 */ 1666 if (drvp->drive_flags & DRIVE_DMA) { 1667 /* if mode = DMA mode 0, use compatible timings */ 1668 if ((drvp->drive_flags & DRIVE_DMA) && 1669 drvp->DMA_mode == 0) { 1670 drvp->PIO_mode = 0; 1671 return ret; 1672 } 1673 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1674 /* 1675 * PIO and DMA timings are the same, use fast timings for PIO 1676 * too, else use compat timings. 1677 */ 1678 if ((piix_isp_pio[drvp->PIO_mode] != 1679 piix_isp_dma[drvp->DMA_mode]) || 1680 (piix_rtc_pio[drvp->PIO_mode] != 1681 piix_rtc_dma[drvp->DMA_mode])) 1682 drvp->PIO_mode = 0; 1683 /* if PIO mode <= 2, use compat timings for PIO */ 1684 if (drvp->PIO_mode <= 2) { 1685 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1686 channel); 1687 return ret; 1688 } 1689 } 1690 1691 /* 1692 * Now setup PIO modes. If mode < 2, use compat timings. 1693 * Else enable fast timings. Enable IORDY and prefetch/post 1694 * if PIO mode >= 3. 1695 */ 1696 1697 if (drvp->PIO_mode < 2) 1698 return ret; 1699 1700 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1701 if (drvp->PIO_mode >= 3) { 1702 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1703 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1704 } 1705 return ret; 1706 } 1707 1708 /* setup values in SIDETIM registers, based on mode */ 1709 static u_int32_t 1710 piix_setup_sidetim_timings(mode, dma, channel) 1711 u_int8_t mode; 1712 u_int8_t dma; 1713 u_int8_t channel; 1714 { 1715 if (dma) 1716 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1717 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1718 else 1719 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1720 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1721 } 1722 1723 void 1724 amd756_chip_map(sc, pa) 1725 struct pciide_softc *sc; 1726 struct pci_attach_args *pa; 1727 { 1728 struct pciide_channel *cp; 1729 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1730 int channel; 1731 pcireg_t chanenable; 1732 bus_size_t cmdsize, ctlsize; 1733 1734 if (pciide_chipen(sc, pa) == 0) 1735 return; 1736 printf("%s: bus-master DMA support present", 1737 sc->sc_wdcdev.sc_dev.dv_xname); 1738 pciide_mapreg_dma(sc, pa); 1739 printf("\n"); 1740 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1741 WDC_CAPABILITY_MODE; 1742 if (sc->sc_dma_ok) { 1743 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1744 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1745 sc->sc_wdcdev.irqack = pciide_irqack; 1746 } 1747 sc->sc_wdcdev.PIO_cap = 4; 1748 sc->sc_wdcdev.DMA_cap = 2; 1749 sc->sc_wdcdev.UDMA_cap = 4; 1750 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1751 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1752 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1753 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1754 1755 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1756 DEBUG_PROBE); 1757 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1758 cp = &sc->pciide_channels[channel]; 1759 if (pciide_chansetup(sc, channel, interface) == 0) 1760 continue; 1761 1762 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1763 printf("%s: %s channel ignored (disabled)\n", 1764 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1765 continue; 1766 } 1767 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1768 pciide_pci_intr); 1769 1770 if (pciide_chan_candisable(cp)) 1771 chanenable &= ~AMD756_CHAN_EN(channel); 1772 pciide_map_compat_intr(pa, cp, channel, interface); 1773 if (cp->hw_ok == 0) 1774 continue; 1775 1776 amd756_setup_channel(&cp->wdc_channel); 1777 } 1778 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1779 chanenable); 1780 return; 1781 } 1782 1783 void 1784 amd756_setup_channel(chp) 1785 struct channel_softc *chp; 1786 { 1787 u_int32_t udmatim_reg, datatim_reg; 1788 u_int8_t idedma_ctl; 1789 int mode, drive; 1790 struct ata_drive_datas *drvp; 1791 struct pciide_channel *cp = (struct pciide_channel*)chp; 1792 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1793 #ifndef PCIIDE_AMD756_ENABLEDMA 1794 int rev = PCI_REVISION( 1795 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1796 #endif 1797 1798 idedma_ctl = 0; 1799 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1800 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1801 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1802 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1803 1804 /* setup DMA if needed */ 1805 pciide_channel_dma_setup(cp); 1806 1807 for (drive = 0; drive < 2; drive++) { 1808 drvp = &chp->ch_drive[drive]; 1809 /* If no drive, skip */ 1810 if ((drvp->drive_flags & DRIVE) == 0) 1811 continue; 1812 /* add timing values, setup DMA if needed */ 1813 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1814 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1815 mode = drvp->PIO_mode; 1816 goto pio; 1817 } 1818 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1819 (drvp->drive_flags & DRIVE_UDMA)) { 1820 /* use Ultra/DMA */ 1821 drvp->drive_flags &= ~DRIVE_DMA; 1822 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1823 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1824 AMD756_UDMA_TIME(chp->channel, drive, 1825 amd756_udma_tim[drvp->UDMA_mode]); 1826 /* can use PIO timings, MW DMA unused */ 1827 mode = drvp->PIO_mode; 1828 } else { 1829 /* use Multiword DMA, but only if revision is OK */ 1830 drvp->drive_flags &= ~DRIVE_UDMA; 1831 #ifndef PCIIDE_AMD756_ENABLEDMA 1832 /* 1833 * The workaround doesn't seem to be necessary 1834 * with all drives, so it can be disabled by 1835 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1836 * triggered. 1837 */ 1838 if (AMD756_CHIPREV_DISABLEDMA(rev)) { 1839 printf("%s:%d:%d: multi-word DMA disabled due " 1840 "to chip revision\n", 1841 sc->sc_wdcdev.sc_dev.dv_xname, 1842 chp->channel, drive); 1843 mode = drvp->PIO_mode; 1844 drvp->drive_flags &= ~DRIVE_DMA; 1845 goto pio; 1846 } 1847 #endif 1848 /* mode = min(pio, dma+2) */ 1849 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1850 mode = drvp->PIO_mode; 1851 else 1852 mode = drvp->DMA_mode + 2; 1853 } 1854 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1855 1856 pio: /* setup PIO mode */ 1857 if (mode <= 2) { 1858 drvp->DMA_mode = 0; 1859 drvp->PIO_mode = 0; 1860 mode = 0; 1861 } else { 1862 drvp->PIO_mode = mode; 1863 drvp->DMA_mode = mode - 2; 1864 } 1865 datatim_reg |= 1866 AMD756_DATATIM_PULSE(chp->channel, drive, 1867 amd756_pio_set[mode]) | 1868 AMD756_DATATIM_RECOV(chp->channel, drive, 1869 amd756_pio_rec[mode]); 1870 } 1871 if (idedma_ctl != 0) { 1872 /* Add software bits in status register */ 1873 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1874 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1875 idedma_ctl); 1876 } 1877 pciide_print_modes(cp); 1878 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1879 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1880 } 1881 1882 void 1883 apollo_chip_map(sc, pa) 1884 struct pciide_softc *sc; 1885 struct pci_attach_args *pa; 1886 { 1887 struct pciide_channel *cp; 1888 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1889 int rev = PCI_REVISION(pa->pa_class); 1890 int channel; 1891 u_int32_t ideconf; 1892 bus_size_t cmdsize, ctlsize; 1893 1894 if (pciide_chipen(sc, pa) == 0) 1895 return; 1896 printf("%s: bus-master DMA support present", 1897 sc->sc_wdcdev.sc_dev.dv_xname); 1898 pciide_mapreg_dma(sc, pa); 1899 printf("\n"); 1900 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1901 WDC_CAPABILITY_MODE; 1902 if (sc->sc_dma_ok) { 1903 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1904 sc->sc_wdcdev.irqack = pciide_irqack; 1905 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE 1906 && rev >= 6) 1907 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1908 } 1909 sc->sc_wdcdev.PIO_cap = 4; 1910 sc->sc_wdcdev.DMA_cap = 2; 1911 sc->sc_wdcdev.UDMA_cap = 2; 1912 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1913 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1914 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1915 1916 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1917 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1918 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1919 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1920 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1921 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1922 DEBUG_PROBE); 1923 1924 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1925 cp = &sc->pciide_channels[channel]; 1926 if (pciide_chansetup(sc, channel, interface) == 0) 1927 continue; 1928 1929 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1930 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1931 printf("%s: %s channel ignored (disabled)\n", 1932 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1933 continue; 1934 } 1935 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1936 pciide_pci_intr); 1937 if (cp->hw_ok == 0) 1938 continue; 1939 if (pciide_chan_candisable(cp)) { 1940 ideconf &= ~APO_IDECONF_EN(channel); 1941 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1942 ideconf); 1943 } 1944 pciide_map_compat_intr(pa, cp, channel, interface); 1945 1946 if (cp->hw_ok == 0) 1947 continue; 1948 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1949 } 1950 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1951 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1952 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1953 } 1954 1955 void 1956 apollo_setup_channel(chp) 1957 struct channel_softc *chp; 1958 { 1959 u_int32_t udmatim_reg, datatim_reg; 1960 u_int8_t idedma_ctl; 1961 int mode, drive; 1962 struct ata_drive_datas *drvp; 1963 struct pciide_channel *cp = (struct pciide_channel*)chp; 1964 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1965 1966 idedma_ctl = 0; 1967 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1968 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1969 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1970 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1971 1972 /* setup DMA if needed */ 1973 pciide_channel_dma_setup(cp); 1974 1975 for (drive = 0; drive < 2; drive++) { 1976 drvp = &chp->ch_drive[drive]; 1977 /* If no drive, skip */ 1978 if ((drvp->drive_flags & DRIVE) == 0) 1979 continue; 1980 /* add timing values, setup DMA if needed */ 1981 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1982 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1983 mode = drvp->PIO_mode; 1984 goto pio; 1985 } 1986 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1987 (drvp->drive_flags & DRIVE_UDMA)) { 1988 /* use Ultra/DMA */ 1989 drvp->drive_flags &= ~DRIVE_DMA; 1990 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1991 APO_UDMA_EN_MTH(chp->channel, drive) | 1992 APO_UDMA_TIME(chp->channel, drive, 1993 apollo_udma_tim[drvp->UDMA_mode]); 1994 /* can use PIO timings, MW DMA unused */ 1995 mode = drvp->PIO_mode; 1996 } else { 1997 /* use Multiword DMA */ 1998 drvp->drive_flags &= ~DRIVE_UDMA; 1999 /* mode = min(pio, dma+2) */ 2000 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2001 mode = drvp->PIO_mode; 2002 else 2003 mode = drvp->DMA_mode + 2; 2004 } 2005 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2006 2007 pio: /* setup PIO mode */ 2008 if (mode <= 2) { 2009 drvp->DMA_mode = 0; 2010 drvp->PIO_mode = 0; 2011 mode = 0; 2012 } else { 2013 drvp->PIO_mode = mode; 2014 drvp->DMA_mode = mode - 2; 2015 } 2016 datatim_reg |= 2017 APO_DATATIM_PULSE(chp->channel, drive, 2018 apollo_pio_set[mode]) | 2019 APO_DATATIM_RECOV(chp->channel, drive, 2020 apollo_pio_rec[mode]); 2021 } 2022 if (idedma_ctl != 0) { 2023 /* Add software bits in status register */ 2024 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2025 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2026 idedma_ctl); 2027 } 2028 pciide_print_modes(cp); 2029 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2030 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2031 } 2032 2033 void 2034 cmd_channel_map(pa, sc, channel) 2035 struct pci_attach_args *pa; 2036 struct pciide_softc *sc; 2037 int channel; 2038 { 2039 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2040 bus_size_t cmdsize, ctlsize; 2041 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2042 int interface; 2043 2044 /* 2045 * The 0648/0649 can be told to identify as a RAID controller. 2046 * In this case, we have to fake interface 2047 */ 2048 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2049 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2050 PCIIDE_INTERFACE_SETTABLE(1); 2051 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2052 CMD_CONF_DSA1) 2053 interface |= PCIIDE_INTERFACE_PCI(0) | 2054 PCIIDE_INTERFACE_PCI(1); 2055 } else { 2056 interface = PCI_INTERFACE(pa->pa_class); 2057 } 2058 2059 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2060 cp->name = PCIIDE_CHANNEL_NAME(channel); 2061 cp->wdc_channel.channel = channel; 2062 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2063 2064 if (channel > 0) { 2065 cp->wdc_channel.ch_queue = 2066 sc->pciide_channels[0].wdc_channel.ch_queue; 2067 } else { 2068 cp->wdc_channel.ch_queue = 2069 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2070 } 2071 if (cp->wdc_channel.ch_queue == NULL) { 2072 printf("%s %s channel: " 2073 "can't allocate memory for command queue", 2074 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2075 return; 2076 } 2077 2078 printf("%s: %s channel %s to %s mode\n", 2079 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2080 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2081 "configured" : "wired", 2082 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2083 "native-PCI" : "compatibility"); 2084 2085 /* 2086 * with a CMD PCI64x, if we get here, the first channel is enabled: 2087 * there's no way to disable the first channel without disabling 2088 * the whole device 2089 */ 2090 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2091 printf("%s: %s channel ignored (disabled)\n", 2092 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2093 return; 2094 } 2095 2096 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2097 if (cp->hw_ok == 0) 2098 return; 2099 if (channel == 1) { 2100 if (pciide_chan_candisable(cp)) { 2101 ctrl &= ~CMD_CTRL_2PORT; 2102 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2103 CMD_CTRL, ctrl); 2104 } 2105 } 2106 pciide_map_compat_intr(pa, cp, channel, interface); 2107 } 2108 2109 int 2110 cmd_pci_intr(arg) 2111 void *arg; 2112 { 2113 struct pciide_softc *sc = arg; 2114 struct pciide_channel *cp; 2115 struct channel_softc *wdc_cp; 2116 int i, rv, crv; 2117 u_int32_t priirq, secirq; 2118 2119 rv = 0; 2120 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2121 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2122 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2123 cp = &sc->pciide_channels[i]; 2124 wdc_cp = &cp->wdc_channel; 2125 /* If a compat channel skip. */ 2126 if (cp->compat) 2127 continue; 2128 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2129 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2130 crv = wdcintr(wdc_cp); 2131 if (crv == 0) 2132 printf("%s:%d: bogus intr\n", 2133 sc->sc_wdcdev.sc_dev.dv_xname, i); 2134 else 2135 rv = 1; 2136 } 2137 } 2138 return rv; 2139 } 2140 2141 void 2142 cmd_chip_map(sc, pa) 2143 struct pciide_softc *sc; 2144 struct pci_attach_args *pa; 2145 { 2146 int channel; 2147 2148 /* 2149 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2150 * and base adresses registers can be disabled at 2151 * hardware level. In this case, the device is wired 2152 * in compat mode and its first channel is always enabled, 2153 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2154 * In fact, it seems that the first channel of the CMD PCI0640 2155 * can't be disabled. 2156 */ 2157 2158 #ifdef PCIIDE_CMD064x_DISABLE 2159 if (pciide_chipen(sc, pa) == 0) 2160 return; 2161 #endif 2162 2163 printf("%s: hardware does not support DMA\n", 2164 sc->sc_wdcdev.sc_dev.dv_xname); 2165 sc->sc_dma_ok = 0; 2166 2167 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2168 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2169 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2170 2171 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2172 cmd_channel_map(pa, sc, channel); 2173 } 2174 } 2175 2176 void 2177 cmd0643_9_chip_map(sc, pa) 2178 struct pciide_softc *sc; 2179 struct pci_attach_args *pa; 2180 { 2181 struct pciide_channel *cp; 2182 int channel; 2183 int rev = PCI_REVISION( 2184 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2185 2186 /* 2187 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2188 * and base adresses registers can be disabled at 2189 * hardware level. In this case, the device is wired 2190 * in compat mode and its first channel is always enabled, 2191 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2192 * In fact, it seems that the first channel of the CMD PCI0640 2193 * can't be disabled. 2194 */ 2195 2196 #ifdef PCIIDE_CMD064x_DISABLE 2197 if (pciide_chipen(sc, pa) == 0) 2198 return; 2199 #endif 2200 printf("%s: bus-master DMA support present", 2201 sc->sc_wdcdev.sc_dev.dv_xname); 2202 pciide_mapreg_dma(sc, pa); 2203 printf("\n"); 2204 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2205 WDC_CAPABILITY_MODE; 2206 if (sc->sc_dma_ok) { 2207 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2208 switch (sc->sc_pp->ide_product) { 2209 case PCI_PRODUCT_CMDTECH_649: 2210 case PCI_PRODUCT_CMDTECH_648: 2211 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2212 sc->sc_wdcdev.UDMA_cap = 4; 2213 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2214 break; 2215 case PCI_PRODUCT_CMDTECH_646: 2216 if (rev >= CMD0646U2_REV) { 2217 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2218 sc->sc_wdcdev.UDMA_cap = 2; 2219 } else if (rev >= CMD0646U_REV) { 2220 /* 2221 * Linux's driver claims that the 646U is broken 2222 * with UDMA. Only enable it if we know what we're 2223 * doing 2224 */ 2225 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2226 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2227 sc->sc_wdcdev.UDMA_cap = 2; 2228 #endif 2229 /* explicitely disable UDMA */ 2230 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2231 CMD_UDMATIM(0), 0); 2232 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2233 CMD_UDMATIM(1), 0); 2234 } 2235 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2236 break; 2237 default: 2238 sc->sc_wdcdev.irqack = pciide_irqack; 2239 } 2240 } 2241 2242 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2243 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2244 sc->sc_wdcdev.PIO_cap = 4; 2245 sc->sc_wdcdev.DMA_cap = 2; 2246 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2247 2248 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2249 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2250 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2251 DEBUG_PROBE); 2252 2253 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2254 cp = &sc->pciide_channels[channel]; 2255 cmd_channel_map(pa, sc, channel); 2256 if (cp->hw_ok == 0) 2257 continue; 2258 cmd0643_9_setup_channel(&cp->wdc_channel); 2259 } 2260 /* 2261 * note - this also makes sure we clear the irq disable and reset 2262 * bits 2263 */ 2264 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2265 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2266 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2267 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2268 DEBUG_PROBE); 2269 } 2270 2271 void 2272 cmd0643_9_setup_channel(chp) 2273 struct channel_softc *chp; 2274 { 2275 struct ata_drive_datas *drvp; 2276 u_int8_t tim; 2277 u_int32_t idedma_ctl, udma_reg; 2278 int drive; 2279 struct pciide_channel *cp = (struct pciide_channel*)chp; 2280 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2281 2282 idedma_ctl = 0; 2283 /* setup DMA if needed */ 2284 pciide_channel_dma_setup(cp); 2285 2286 for (drive = 0; drive < 2; drive++) { 2287 drvp = &chp->ch_drive[drive]; 2288 /* If no drive, skip */ 2289 if ((drvp->drive_flags & DRIVE) == 0) 2290 continue; 2291 /* add timing values, setup DMA if needed */ 2292 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2293 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2294 if (drvp->drive_flags & DRIVE_UDMA) { 2295 /* UltraDMA on a 646U2, 0648 or 0649 */ 2296 udma_reg = pciide_pci_read(sc->sc_pc, 2297 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2298 if (drvp->UDMA_mode > 2 && 2299 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2300 CMD_BICSR) & 2301 CMD_BICSR_80(chp->channel)) == 0) 2302 drvp->UDMA_mode = 2; 2303 if (drvp->UDMA_mode > 2) 2304 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2305 else if (sc->sc_wdcdev.UDMA_cap > 2) 2306 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2307 udma_reg |= CMD_UDMATIM_UDMA(drive); 2308 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2309 CMD_UDMATIM_TIM_OFF(drive)); 2310 udma_reg |= 2311 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2312 CMD_UDMATIM_TIM_OFF(drive)); 2313 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2314 CMD_UDMATIM(chp->channel), udma_reg); 2315 } else { 2316 /* 2317 * use Multiword DMA. 2318 * Timings will be used for both PIO and DMA, 2319 * so adjust DMA mode if needed 2320 * if we have a 0646U2/8/9, turn off UDMA 2321 */ 2322 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2323 udma_reg = pciide_pci_read(sc->sc_pc, 2324 sc->sc_tag, 2325 CMD_UDMATIM(chp->channel)); 2326 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2327 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2328 CMD_UDMATIM(chp->channel), 2329 udma_reg); 2330 } 2331 if (drvp->PIO_mode >= 3 && 2332 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2333 drvp->DMA_mode = drvp->PIO_mode - 2; 2334 } 2335 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2336 } 2337 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2338 } 2339 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2340 CMD_DATA_TIM(chp->channel, drive), tim); 2341 } 2342 if (idedma_ctl != 0) { 2343 /* Add software bits in status register */ 2344 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2345 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2346 idedma_ctl); 2347 } 2348 pciide_print_modes(cp); 2349 } 2350 2351 void 2352 cmd646_9_irqack(chp) 2353 struct channel_softc *chp; 2354 { 2355 u_int32_t priirq, secirq; 2356 struct pciide_channel *cp = (struct pciide_channel*)chp; 2357 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2358 2359 if (chp->channel == 0) { 2360 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2361 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2362 } else { 2363 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2364 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2365 } 2366 pciide_irqack(chp); 2367 } 2368 2369 void 2370 cy693_chip_map(sc, pa) 2371 struct pciide_softc *sc; 2372 struct pci_attach_args *pa; 2373 { 2374 struct pciide_channel *cp; 2375 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2376 bus_size_t cmdsize, ctlsize; 2377 2378 if (pciide_chipen(sc, pa) == 0) 2379 return; 2380 /* 2381 * this chip has 2 PCI IDE functions, one for primary and one for 2382 * secondary. So we need to call pciide_mapregs_compat() with 2383 * the real channel 2384 */ 2385 if (pa->pa_function == 1) { 2386 sc->sc_cy_compatchan = 0; 2387 } else if (pa->pa_function == 2) { 2388 sc->sc_cy_compatchan = 1; 2389 } else { 2390 printf("%s: unexpected PCI function %d\n", 2391 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2392 return; 2393 } 2394 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2395 printf("%s: bus-master DMA support present", 2396 sc->sc_wdcdev.sc_dev.dv_xname); 2397 pciide_mapreg_dma(sc, pa); 2398 } else { 2399 printf("%s: hardware does not support DMA", 2400 sc->sc_wdcdev.sc_dev.dv_xname); 2401 sc->sc_dma_ok = 0; 2402 } 2403 printf("\n"); 2404 2405 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2406 if (sc->sc_cy_handle == NULL) { 2407 printf("%s: unable to map hyperCache control registers\n", 2408 sc->sc_wdcdev.sc_dev.dv_xname); 2409 sc->sc_dma_ok = 0; 2410 } 2411 2412 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2413 WDC_CAPABILITY_MODE; 2414 if (sc->sc_dma_ok) { 2415 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2416 sc->sc_wdcdev.irqack = pciide_irqack; 2417 } 2418 sc->sc_wdcdev.PIO_cap = 4; 2419 sc->sc_wdcdev.DMA_cap = 2; 2420 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2421 2422 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2423 sc->sc_wdcdev.nchannels = 1; 2424 2425 /* Only one channel for this chip; if we are here it's enabled */ 2426 cp = &sc->pciide_channels[0]; 2427 sc->wdc_chanarray[0] = &cp->wdc_channel; 2428 cp->name = PCIIDE_CHANNEL_NAME(0); 2429 cp->wdc_channel.channel = 0; 2430 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2431 cp->wdc_channel.ch_queue = 2432 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2433 if (cp->wdc_channel.ch_queue == NULL) { 2434 printf("%s primary channel: " 2435 "can't allocate memory for command queue", 2436 sc->sc_wdcdev.sc_dev.dv_xname); 2437 return; 2438 } 2439 printf("%s: primary channel %s to ", 2440 sc->sc_wdcdev.sc_dev.dv_xname, 2441 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2442 "configured" : "wired"); 2443 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2444 printf("native-PCI"); 2445 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2446 pciide_pci_intr); 2447 } else { 2448 printf("compatibility"); 2449 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2450 &cmdsize, &ctlsize); 2451 } 2452 printf(" mode\n"); 2453 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2454 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2455 wdcattach(&cp->wdc_channel); 2456 if (pciide_chan_candisable(cp)) { 2457 pci_conf_write(sc->sc_pc, sc->sc_tag, 2458 PCI_COMMAND_STATUS_REG, 0); 2459 } 2460 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2461 if (cp->hw_ok == 0) 2462 return; 2463 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2464 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2465 cy693_setup_channel(&cp->wdc_channel); 2466 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2467 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2468 } 2469 2470 void 2471 cy693_setup_channel(chp) 2472 struct channel_softc *chp; 2473 { 2474 struct ata_drive_datas *drvp; 2475 int drive; 2476 u_int32_t cy_cmd_ctrl; 2477 u_int32_t idedma_ctl; 2478 struct pciide_channel *cp = (struct pciide_channel*)chp; 2479 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2480 int dma_mode = -1; 2481 2482 cy_cmd_ctrl = idedma_ctl = 0; 2483 2484 /* setup DMA if needed */ 2485 pciide_channel_dma_setup(cp); 2486 2487 for (drive = 0; drive < 2; drive++) { 2488 drvp = &chp->ch_drive[drive]; 2489 /* If no drive, skip */ 2490 if ((drvp->drive_flags & DRIVE) == 0) 2491 continue; 2492 /* add timing values, setup DMA if needed */ 2493 if (drvp->drive_flags & DRIVE_DMA) { 2494 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2495 /* use Multiword DMA */ 2496 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2497 dma_mode = drvp->DMA_mode; 2498 } 2499 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2500 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2501 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2502 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2503 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2504 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2505 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2506 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2507 } 2508 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2509 chp->ch_drive[0].DMA_mode = dma_mode; 2510 chp->ch_drive[1].DMA_mode = dma_mode; 2511 2512 if (dma_mode == -1) 2513 dma_mode = 0; 2514 2515 if (sc->sc_cy_handle != NULL) { 2516 /* Note: `multiple' is implied. */ 2517 cy82c693_write(sc->sc_cy_handle, 2518 (sc->sc_cy_compatchan == 0) ? 2519 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2520 } 2521 2522 pciide_print_modes(cp); 2523 2524 if (idedma_ctl != 0) { 2525 /* Add software bits in status register */ 2526 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2527 IDEDMA_CTL, idedma_ctl); 2528 } 2529 } 2530 2531 void 2532 sis_chip_map(sc, pa) 2533 struct pciide_softc *sc; 2534 struct pci_attach_args *pa; 2535 { 2536 struct pciide_channel *cp; 2537 int channel; 2538 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2539 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2540 pcireg_t rev = PCI_REVISION(pa->pa_class); 2541 bus_size_t cmdsize, ctlsize; 2542 2543 if (pciide_chipen(sc, pa) == 0) 2544 return; 2545 printf("%s: bus-master DMA support present", 2546 sc->sc_wdcdev.sc_dev.dv_xname); 2547 pciide_mapreg_dma(sc, pa); 2548 printf("\n"); 2549 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2550 WDC_CAPABILITY_MODE; 2551 if (sc->sc_dma_ok) { 2552 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2553 sc->sc_wdcdev.irqack = pciide_irqack; 2554 if (rev >= 0xd0) 2555 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2556 } 2557 2558 sc->sc_wdcdev.PIO_cap = 4; 2559 sc->sc_wdcdev.DMA_cap = 2; 2560 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2561 sc->sc_wdcdev.UDMA_cap = 2; 2562 sc->sc_wdcdev.set_modes = sis_setup_channel; 2563 2564 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2565 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2566 2567 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2568 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2569 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2570 2571 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2572 cp = &sc->pciide_channels[channel]; 2573 if (pciide_chansetup(sc, channel, interface) == 0) 2574 continue; 2575 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2576 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2577 printf("%s: %s channel ignored (disabled)\n", 2578 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2579 continue; 2580 } 2581 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2582 pciide_pci_intr); 2583 if (cp->hw_ok == 0) 2584 continue; 2585 if (pciide_chan_candisable(cp)) { 2586 if (channel == 0) 2587 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2588 else 2589 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2590 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2591 sis_ctr0); 2592 } 2593 pciide_map_compat_intr(pa, cp, channel, interface); 2594 if (cp->hw_ok == 0) 2595 continue; 2596 sis_setup_channel(&cp->wdc_channel); 2597 } 2598 } 2599 2600 void 2601 sis_setup_channel(chp) 2602 struct channel_softc *chp; 2603 { 2604 struct ata_drive_datas *drvp; 2605 int drive; 2606 u_int32_t sis_tim; 2607 u_int32_t idedma_ctl; 2608 struct pciide_channel *cp = (struct pciide_channel*)chp; 2609 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2610 2611 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2612 "channel %d 0x%x\n", chp->channel, 2613 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2614 DEBUG_PROBE); 2615 sis_tim = 0; 2616 idedma_ctl = 0; 2617 /* setup DMA if needed */ 2618 pciide_channel_dma_setup(cp); 2619 2620 for (drive = 0; drive < 2; drive++) { 2621 drvp = &chp->ch_drive[drive]; 2622 /* If no drive, skip */ 2623 if ((drvp->drive_flags & DRIVE) == 0) 2624 continue; 2625 /* add timing values, setup DMA if needed */ 2626 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2627 (drvp->drive_flags & DRIVE_UDMA) == 0) 2628 goto pio; 2629 2630 if (drvp->drive_flags & DRIVE_UDMA) { 2631 /* use Ultra/DMA */ 2632 drvp->drive_flags &= ~DRIVE_DMA; 2633 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2634 SIS_TIM_UDMA_TIME_OFF(drive); 2635 sis_tim |= SIS_TIM_UDMA_EN(drive); 2636 } else { 2637 /* 2638 * use Multiword DMA 2639 * Timings will be used for both PIO and DMA, 2640 * so adjust DMA mode if needed 2641 */ 2642 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2643 drvp->PIO_mode = drvp->DMA_mode + 2; 2644 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2645 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2646 drvp->PIO_mode - 2 : 0; 2647 if (drvp->DMA_mode == 0) 2648 drvp->PIO_mode = 0; 2649 } 2650 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2651 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2652 SIS_TIM_ACT_OFF(drive); 2653 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2654 SIS_TIM_REC_OFF(drive); 2655 } 2656 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2657 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2658 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2659 if (idedma_ctl != 0) { 2660 /* Add software bits in status register */ 2661 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2662 IDEDMA_CTL, idedma_ctl); 2663 } 2664 pciide_print_modes(cp); 2665 } 2666 2667 void 2668 acer_chip_map(sc, pa) 2669 struct pciide_softc *sc; 2670 struct pci_attach_args *pa; 2671 { 2672 struct pciide_channel *cp; 2673 int channel; 2674 pcireg_t cr, interface; 2675 bus_size_t cmdsize, ctlsize; 2676 2677 if (pciide_chipen(sc, pa) == 0) 2678 return; 2679 printf("%s: bus-master DMA support present", 2680 sc->sc_wdcdev.sc_dev.dv_xname); 2681 pciide_mapreg_dma(sc, pa); 2682 printf("\n"); 2683 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2684 WDC_CAPABILITY_MODE; 2685 if (sc->sc_dma_ok) { 2686 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2687 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2688 sc->sc_wdcdev.irqack = pciide_irqack; 2689 } 2690 2691 sc->sc_wdcdev.PIO_cap = 4; 2692 sc->sc_wdcdev.DMA_cap = 2; 2693 sc->sc_wdcdev.UDMA_cap = 2; 2694 sc->sc_wdcdev.set_modes = acer_setup_channel; 2695 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2696 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2697 2698 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2699 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2700 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2701 2702 /* Enable "microsoft register bits" R/W. */ 2703 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2704 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2705 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2706 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2707 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2708 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2709 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2710 ~ACER_CHANSTATUSREGS_RO); 2711 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2712 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2713 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2714 /* Don't use cr, re-read the real register content instead */ 2715 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2716 PCI_CLASS_REG)); 2717 2718 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2719 cp = &sc->pciide_channels[channel]; 2720 if (pciide_chansetup(sc, channel, interface) == 0) 2721 continue; 2722 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2723 printf("%s: %s channel ignored (disabled)\n", 2724 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2725 continue; 2726 } 2727 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2728 acer_pci_intr); 2729 if (cp->hw_ok == 0) 2730 continue; 2731 if (pciide_chan_candisable(cp)) { 2732 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2733 pci_conf_write(sc->sc_pc, sc->sc_tag, 2734 PCI_CLASS_REG, cr); 2735 } 2736 pciide_map_compat_intr(pa, cp, channel, interface); 2737 acer_setup_channel(&cp->wdc_channel); 2738 } 2739 } 2740 2741 void 2742 acer_setup_channel(chp) 2743 struct channel_softc *chp; 2744 { 2745 struct ata_drive_datas *drvp; 2746 int drive; 2747 u_int32_t acer_fifo_udma; 2748 u_int32_t idedma_ctl; 2749 struct pciide_channel *cp = (struct pciide_channel*)chp; 2750 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2751 2752 idedma_ctl = 0; 2753 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2754 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2755 acer_fifo_udma), DEBUG_PROBE); 2756 /* setup DMA if needed */ 2757 pciide_channel_dma_setup(cp); 2758 2759 for (drive = 0; drive < 2; drive++) { 2760 drvp = &chp->ch_drive[drive]; 2761 /* If no drive, skip */ 2762 if ((drvp->drive_flags & DRIVE) == 0) 2763 continue; 2764 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2765 "channel %d drive %d 0x%x\n", chp->channel, drive, 2766 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2767 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2768 /* clear FIFO/DMA mode */ 2769 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2770 ACER_UDMA_EN(chp->channel, drive) | 2771 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2772 2773 /* add timing values, setup DMA if needed */ 2774 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2775 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2776 acer_fifo_udma |= 2777 ACER_FTH_OPL(chp->channel, drive, 0x1); 2778 goto pio; 2779 } 2780 2781 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2782 if (drvp->drive_flags & DRIVE_UDMA) { 2783 /* use Ultra/DMA */ 2784 drvp->drive_flags &= ~DRIVE_DMA; 2785 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2786 acer_fifo_udma |= 2787 ACER_UDMA_TIM(chp->channel, drive, 2788 acer_udma[drvp->UDMA_mode]); 2789 } else { 2790 /* 2791 * use Multiword DMA 2792 * Timings will be used for both PIO and DMA, 2793 * so adjust DMA mode if needed 2794 */ 2795 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2796 drvp->PIO_mode = drvp->DMA_mode + 2; 2797 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2798 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2799 drvp->PIO_mode - 2 : 0; 2800 if (drvp->DMA_mode == 0) 2801 drvp->PIO_mode = 0; 2802 } 2803 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2804 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2805 ACER_IDETIM(chp->channel, drive), 2806 acer_pio[drvp->PIO_mode]); 2807 } 2808 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2809 acer_fifo_udma), DEBUG_PROBE); 2810 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2811 if (idedma_ctl != 0) { 2812 /* Add software bits in status register */ 2813 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2814 IDEDMA_CTL, idedma_ctl); 2815 } 2816 pciide_print_modes(cp); 2817 } 2818 2819 int 2820 acer_pci_intr(arg) 2821 void *arg; 2822 { 2823 struct pciide_softc *sc = arg; 2824 struct pciide_channel *cp; 2825 struct channel_softc *wdc_cp; 2826 int i, rv, crv; 2827 u_int32_t chids; 2828 2829 rv = 0; 2830 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2831 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2832 cp = &sc->pciide_channels[i]; 2833 wdc_cp = &cp->wdc_channel; 2834 /* If a compat channel skip. */ 2835 if (cp->compat) 2836 continue; 2837 if (chids & ACER_CHIDS_INT(i)) { 2838 crv = wdcintr(wdc_cp); 2839 if (crv == 0) 2840 printf("%s:%d: bogus intr\n", 2841 sc->sc_wdcdev.sc_dev.dv_xname, i); 2842 else 2843 rv = 1; 2844 } 2845 } 2846 return rv; 2847 } 2848 2849 void 2850 hpt_chip_map(sc, pa) 2851 struct pciide_softc *sc; 2852 struct pci_attach_args *pa; 2853 { 2854 struct pciide_channel *cp; 2855 int i, compatchan, revision; 2856 pcireg_t interface; 2857 bus_size_t cmdsize, ctlsize; 2858 2859 if (pciide_chipen(sc, pa) == 0) 2860 return; 2861 revision = PCI_REVISION(pa->pa_class); 2862 2863 /* 2864 * when the chip is in native mode it identifies itself as a 2865 * 'misc mass storage'. Fake interface in this case. 2866 */ 2867 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2868 interface = PCI_INTERFACE(pa->pa_class); 2869 } else { 2870 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2871 PCIIDE_INTERFACE_PCI(0); 2872 if (revision == HPT370_REV) 2873 interface |= PCIIDE_INTERFACE_PCI(1); 2874 } 2875 2876 printf("%s: bus-master DMA support present", 2877 sc->sc_wdcdev.sc_dev.dv_xname); 2878 pciide_mapreg_dma(sc, pa); 2879 printf("\n"); 2880 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2881 WDC_CAPABILITY_MODE; 2882 if (sc->sc_dma_ok) { 2883 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2884 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2885 sc->sc_wdcdev.irqack = pciide_irqack; 2886 } 2887 sc->sc_wdcdev.PIO_cap = 4; 2888 sc->sc_wdcdev.DMA_cap = 2; 2889 sc->sc_wdcdev.UDMA_cap = 4; 2890 2891 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2892 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2893 if (revision == HPT366_REV) { 2894 /* 2895 * The 366 has 2 PCI IDE functions, one for primary and one 2896 * for secondary. So we need to call pciide_mapregs_compat() 2897 * with the real channel 2898 */ 2899 if (pa->pa_function == 0) { 2900 compatchan = 0; 2901 } else if (pa->pa_function == 1) { 2902 compatchan = 1; 2903 } else { 2904 printf("%s: unexpected PCI function %d\n", 2905 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2906 return; 2907 } 2908 sc->sc_wdcdev.nchannels = 1; 2909 } else { 2910 sc->sc_wdcdev.nchannels = 2; 2911 } 2912 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2913 cp = &sc->pciide_channels[i]; 2914 if (sc->sc_wdcdev.nchannels > 1) { 2915 compatchan = i; 2916 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2917 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2918 printf("%s: %s channel ignored (disabled)\n", 2919 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2920 continue; 2921 } 2922 } 2923 if (pciide_chansetup(sc, i, interface) == 0) 2924 continue; 2925 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2926 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2927 &ctlsize, hpt_pci_intr); 2928 } else { 2929 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2930 &cmdsize, &ctlsize); 2931 } 2932 if (cp->hw_ok == 0) 2933 return; 2934 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2935 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2936 wdcattach(&cp->wdc_channel); 2937 hpt_setup_channel(&cp->wdc_channel); 2938 } 2939 if (revision == HPT370_REV) { 2940 /* 2941 * HPT370_REV has a bit to disable interrupts, make sure 2942 * to clear it 2943 */ 2944 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 2945 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 2946 ~HPT_CSEL_IRQDIS); 2947 } 2948 return; 2949 } 2950 2951 2952 void 2953 hpt_setup_channel(chp) 2954 struct channel_softc *chp; 2955 { 2956 struct ata_drive_datas *drvp; 2957 int drive; 2958 int cable; 2959 u_int32_t before, after; 2960 u_int32_t idedma_ctl; 2961 struct pciide_channel *cp = (struct pciide_channel*)chp; 2962 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2963 2964 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 2965 2966 /* setup DMA if needed */ 2967 pciide_channel_dma_setup(cp); 2968 2969 idedma_ctl = 0; 2970 2971 /* Per drive settings */ 2972 for (drive = 0; drive < 2; drive++) { 2973 drvp = &chp->ch_drive[drive]; 2974 /* If no drive, skip */ 2975 if ((drvp->drive_flags & DRIVE) == 0) 2976 continue; 2977 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 2978 HPT_IDETIM(chp->channel, drive)); 2979 2980 /* add timing values, setup DMA if needed */ 2981 if (drvp->drive_flags & DRIVE_UDMA) { 2982 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 2983 drvp->UDMA_mode > 2) 2984 drvp->UDMA_mode = 2; 2985 after = (sc->sc_wdcdev.nchannels == 2) ? 2986 hpt370_udma[drvp->UDMA_mode] : 2987 hpt366_udma[drvp->UDMA_mode]; 2988 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2989 } else if (drvp->drive_flags & DRIVE_DMA) { 2990 /* 2991 * use Multiword DMA. 2992 * Timings will be used for both PIO and DMA, so adjust 2993 * DMA mode if needed 2994 */ 2995 if (drvp->PIO_mode >= 3 && 2996 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2997 drvp->DMA_mode = drvp->PIO_mode - 2; 2998 } 2999 after = (sc->sc_wdcdev.nchannels == 2) ? 3000 hpt370_dma[drvp->DMA_mode] : 3001 hpt366_dma[drvp->DMA_mode]; 3002 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3003 } else { 3004 /* PIO only */ 3005 after = (sc->sc_wdcdev.nchannels == 2) ? 3006 hpt370_pio[drvp->PIO_mode] : 3007 hpt366_pio[drvp->PIO_mode]; 3008 } 3009 pci_conf_write(sc->sc_pc, sc->sc_tag, 3010 HPT_IDETIM(chp->channel, drive), after); 3011 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3012 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3013 after, before), DEBUG_PROBE); 3014 } 3015 if (idedma_ctl != 0) { 3016 /* Add software bits in status register */ 3017 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3018 IDEDMA_CTL, idedma_ctl); 3019 } 3020 pciide_print_modes(cp); 3021 } 3022 3023 int 3024 hpt_pci_intr(arg) 3025 void *arg; 3026 { 3027 struct pciide_softc *sc = arg; 3028 struct pciide_channel *cp; 3029 struct channel_softc *wdc_cp; 3030 int rv = 0; 3031 int dmastat, i, crv; 3032 3033 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3034 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3035 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3036 if((dmastat & IDEDMA_CTL_INTR) == 0) 3037 continue; 3038 cp = &sc->pciide_channels[i]; 3039 wdc_cp = &cp->wdc_channel; 3040 crv = wdcintr(wdc_cp); 3041 if (crv == 0) { 3042 printf("%s:%d: bogus intr\n", 3043 sc->sc_wdcdev.sc_dev.dv_xname, i); 3044 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3045 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3046 } else 3047 rv = 1; 3048 } 3049 return rv; 3050 } 3051 3052 3053 /* A macro to test product */ 3054 #define PDC_IS_262(sc) \ 3055 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3056 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3057 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3058 3059 void 3060 pdc202xx_chip_map(sc, pa) 3061 struct pciide_softc *sc; 3062 struct pci_attach_args *pa; 3063 { 3064 struct pciide_channel *cp; 3065 int channel; 3066 pcireg_t interface, st, mode; 3067 bus_size_t cmdsize, ctlsize; 3068 3069 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3070 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3071 DEBUG_PROBE); 3072 if (pciide_chipen(sc, pa) == 0) 3073 return; 3074 3075 /* turn off RAID mode */ 3076 st &= ~PDC2xx_STATE_IDERAID; 3077 3078 /* 3079 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3080 * mode. We have to fake interface 3081 */ 3082 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3083 if (st & PDC2xx_STATE_NATIVE) 3084 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3085 3086 printf("%s: bus-master DMA support present", 3087 sc->sc_wdcdev.sc_dev.dv_xname); 3088 pciide_mapreg_dma(sc, pa); 3089 printf("\n"); 3090 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3091 WDC_CAPABILITY_MODE; 3092 if (sc->sc_dma_ok) { 3093 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3094 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3095 sc->sc_wdcdev.irqack = pciide_irqack; 3096 } 3097 sc->sc_wdcdev.PIO_cap = 4; 3098 sc->sc_wdcdev.DMA_cap = 2; 3099 if (PDC_IS_262(sc)) 3100 sc->sc_wdcdev.UDMA_cap = 4; 3101 else 3102 sc->sc_wdcdev.UDMA_cap = 2; 3103 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3104 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3105 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3106 3107 /* setup failsafe defaults */ 3108 mode = 0; 3109 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3110 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3111 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3112 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3113 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3114 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3115 "initial timings 0x%x, now 0x%x\n", channel, 3116 pci_conf_read(sc->sc_pc, sc->sc_tag, 3117 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3118 DEBUG_PROBE); 3119 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3120 mode | PDC2xx_TIM_IORDYp); 3121 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3122 "initial timings 0x%x, now 0x%x\n", channel, 3123 pci_conf_read(sc->sc_pc, sc->sc_tag, 3124 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3125 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3126 mode); 3127 } 3128 3129 mode = PDC2xx_SCR_DMA; 3130 if (PDC_IS_262(sc)) { 3131 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3132 } else { 3133 /* the BIOS set it up this way */ 3134 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3135 } 3136 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3137 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3138 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3139 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3140 DEBUG_PROBE); 3141 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3142 3143 /* controller initial state register is OK even without BIOS */ 3144 /* Set DMA mode to IDE DMA compatibility */ 3145 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3146 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3147 DEBUG_PROBE); 3148 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3149 mode | 0x1); 3150 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3151 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3152 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3153 mode | 0x1); 3154 3155 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3156 cp = &sc->pciide_channels[channel]; 3157 if (pciide_chansetup(sc, channel, interface) == 0) 3158 continue; 3159 if ((st & (PDC_IS_262(sc) ? 3160 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3161 printf("%s: %s channel ignored (disabled)\n", 3162 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3163 continue; 3164 } 3165 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3166 pdc202xx_pci_intr); 3167 if (cp->hw_ok == 0) 3168 continue; 3169 if (pciide_chan_candisable(cp)) 3170 st &= ~(PDC_IS_262(sc) ? 3171 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3172 pciide_map_compat_intr(pa, cp, channel, interface); 3173 pdc202xx_setup_channel(&cp->wdc_channel); 3174 } 3175 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3176 DEBUG_PROBE); 3177 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3178 return; 3179 } 3180 3181 void 3182 pdc202xx_setup_channel(chp) 3183 struct channel_softc *chp; 3184 { 3185 struct ata_drive_datas *drvp; 3186 int drive; 3187 pcireg_t mode, st; 3188 u_int32_t idedma_ctl, scr, atapi; 3189 struct pciide_channel *cp = (struct pciide_channel*)chp; 3190 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3191 int channel = chp->channel; 3192 3193 /* setup DMA if needed */ 3194 pciide_channel_dma_setup(cp); 3195 3196 idedma_ctl = 0; 3197 3198 /* Per channel settings */ 3199 if (PDC_IS_262(sc)) { 3200 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3201 PDC262_U66); 3202 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3203 /* Trimm UDMA mode */ 3204 if ((st & PDC262_STATE_80P(channel)) != 0 || 3205 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3206 chp->ch_drive[0].UDMA_mode <= 2) || 3207 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3208 chp->ch_drive[1].UDMA_mode <= 2)) { 3209 if (chp->ch_drive[0].UDMA_mode > 2) 3210 chp->ch_drive[0].UDMA_mode = 2; 3211 if (chp->ch_drive[1].UDMA_mode > 2) 3212 chp->ch_drive[1].UDMA_mode = 2; 3213 } 3214 /* Set U66 if needed */ 3215 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3216 chp->ch_drive[0].UDMA_mode > 2) || 3217 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3218 chp->ch_drive[1].UDMA_mode > 2)) 3219 scr |= PDC262_U66_EN(channel); 3220 else 3221 scr &= ~PDC262_U66_EN(channel); 3222 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3223 PDC262_U66, scr); 3224 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3225 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3226 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3227 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3228 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3229 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3230 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3231 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3232 atapi = 0; 3233 else 3234 atapi = PDC262_ATAPI_UDMA; 3235 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3236 PDC262_ATAPI(channel), atapi); 3237 } 3238 } 3239 for (drive = 0; drive < 2; drive++) { 3240 drvp = &chp->ch_drive[drive]; 3241 /* If no drive, skip */ 3242 if ((drvp->drive_flags & DRIVE) == 0) 3243 continue; 3244 mode = 0; 3245 if (drvp->drive_flags & DRIVE_UDMA) { 3246 mode = PDC2xx_TIM_SET_MB(mode, 3247 pdc2xx_udma_mb[drvp->UDMA_mode]); 3248 mode = PDC2xx_TIM_SET_MC(mode, 3249 pdc2xx_udma_mc[drvp->UDMA_mode]); 3250 drvp->drive_flags &= ~DRIVE_DMA; 3251 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3252 } else if (drvp->drive_flags & DRIVE_DMA) { 3253 mode = PDC2xx_TIM_SET_MB(mode, 3254 pdc2xx_dma_mb[drvp->DMA_mode]); 3255 mode = PDC2xx_TIM_SET_MC(mode, 3256 pdc2xx_dma_mc[drvp->DMA_mode]); 3257 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3258 } else { 3259 mode = PDC2xx_TIM_SET_MB(mode, 3260 pdc2xx_dma_mb[0]); 3261 mode = PDC2xx_TIM_SET_MC(mode, 3262 pdc2xx_dma_mc[0]); 3263 } 3264 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3265 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3266 if (drvp->drive_flags & DRIVE_ATA) 3267 mode |= PDC2xx_TIM_PRE; 3268 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3269 if (drvp->PIO_mode >= 3) { 3270 mode |= PDC2xx_TIM_IORDY; 3271 if (drive == 0) 3272 mode |= PDC2xx_TIM_IORDYp; 3273 } 3274 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3275 "timings 0x%x\n", 3276 sc->sc_wdcdev.sc_dev.dv_xname, 3277 chp->channel, drive, mode), DEBUG_PROBE); 3278 pci_conf_write(sc->sc_pc, sc->sc_tag, 3279 PDC2xx_TIM(chp->channel, drive), mode); 3280 } 3281 if (idedma_ctl != 0) { 3282 /* Add software bits in status register */ 3283 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3284 IDEDMA_CTL, idedma_ctl); 3285 } 3286 pciide_print_modes(cp); 3287 } 3288 3289 int 3290 pdc202xx_pci_intr(arg) 3291 void *arg; 3292 { 3293 struct pciide_softc *sc = arg; 3294 struct pciide_channel *cp; 3295 struct channel_softc *wdc_cp; 3296 int i, rv, crv; 3297 u_int32_t scr; 3298 3299 rv = 0; 3300 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3301 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3302 cp = &sc->pciide_channels[i]; 3303 wdc_cp = &cp->wdc_channel; 3304 /* If a compat channel skip. */ 3305 if (cp->compat) 3306 continue; 3307 if (scr & PDC2xx_SCR_INT(i)) { 3308 crv = wdcintr(wdc_cp); 3309 if (crv == 0) 3310 printf("%s:%d: bogus intr\n", 3311 sc->sc_wdcdev.sc_dev.dv_xname, i); 3312 else 3313 rv = 1; 3314 } 3315 } 3316 return rv; 3317 } 3318 3319 void 3320 opti_chip_map(sc, pa) 3321 struct pciide_softc *sc; 3322 struct pci_attach_args *pa; 3323 { 3324 struct pciide_channel *cp; 3325 bus_size_t cmdsize, ctlsize; 3326 pcireg_t interface; 3327 u_int8_t init_ctrl; 3328 int channel; 3329 3330 if (pciide_chipen(sc, pa) == 0) 3331 return; 3332 printf("%s: bus-master DMA support present", 3333 sc->sc_wdcdev.sc_dev.dv_xname); 3334 pciide_mapreg_dma(sc, pa); 3335 printf("\n"); 3336 3337 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3338 WDC_CAPABILITY_MODE; 3339 sc->sc_wdcdev.PIO_cap = 4; 3340 if (sc->sc_dma_ok) { 3341 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3342 sc->sc_wdcdev.irqack = pciide_irqack; 3343 sc->sc_wdcdev.DMA_cap = 2; 3344 } 3345 sc->sc_wdcdev.set_modes = opti_setup_channel; 3346 3347 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3348 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3349 3350 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3351 OPTI_REG_INIT_CONTROL); 3352 3353 interface = PCI_INTERFACE(pa->pa_class); 3354 3355 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3356 cp = &sc->pciide_channels[channel]; 3357 if (pciide_chansetup(sc, channel, interface) == 0) 3358 continue; 3359 if (channel == 1 && 3360 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3361 printf("%s: %s channel ignored (disabled)\n", 3362 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3363 continue; 3364 } 3365 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3366 pciide_pci_intr); 3367 if (cp->hw_ok == 0) 3368 continue; 3369 pciide_map_compat_intr(pa, cp, channel, interface); 3370 if (cp->hw_ok == 0) 3371 continue; 3372 opti_setup_channel(&cp->wdc_channel); 3373 } 3374 } 3375 3376 void 3377 opti_setup_channel(chp) 3378 struct channel_softc *chp; 3379 { 3380 struct ata_drive_datas *drvp; 3381 struct pciide_channel *cp = (struct pciide_channel*)chp; 3382 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3383 int drive, spd; 3384 int mode[2]; 3385 u_int8_t rv, mr; 3386 3387 /* 3388 * The `Delay' and `Address Setup Time' fields of the 3389 * Miscellaneous Register are always zero initially. 3390 */ 3391 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3392 mr &= ~(OPTI_MISC_DELAY_MASK | 3393 OPTI_MISC_ADDR_SETUP_MASK | 3394 OPTI_MISC_INDEX_MASK); 3395 3396 /* Prime the control register before setting timing values */ 3397 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3398 3399 /* Determine the clockrate of the PCIbus the chip is attached to */ 3400 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3401 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3402 3403 /* setup DMA if needed */ 3404 pciide_channel_dma_setup(cp); 3405 3406 for (drive = 0; drive < 2; drive++) { 3407 drvp = &chp->ch_drive[drive]; 3408 /* If no drive, skip */ 3409 if ((drvp->drive_flags & DRIVE) == 0) { 3410 mode[drive] = -1; 3411 continue; 3412 } 3413 3414 if ((drvp->drive_flags & DRIVE_DMA)) { 3415 /* 3416 * Timings will be used for both PIO and DMA, 3417 * so adjust DMA mode if needed 3418 */ 3419 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3420 drvp->PIO_mode = drvp->DMA_mode + 2; 3421 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3422 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3423 drvp->PIO_mode - 2 : 0; 3424 if (drvp->DMA_mode == 0) 3425 drvp->PIO_mode = 0; 3426 3427 mode[drive] = drvp->DMA_mode + 5; 3428 } else 3429 mode[drive] = drvp->PIO_mode; 3430 3431 if (drive && mode[0] >= 0 && 3432 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3433 /* 3434 * Can't have two drives using different values 3435 * for `Address Setup Time'. 3436 * Slow down the faster drive to compensate. 3437 */ 3438 int d = (opti_tim_as[spd][mode[0]] > 3439 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3440 3441 mode[d] = mode[1-d]; 3442 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3443 chp->ch_drive[d].DMA_mode = 0; 3444 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3445 } 3446 } 3447 3448 for (drive = 0; drive < 2; drive++) { 3449 int m; 3450 if ((m = mode[drive]) < 0) 3451 continue; 3452 3453 /* Set the Address Setup Time and select appropriate index */ 3454 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3455 rv |= OPTI_MISC_INDEX(drive); 3456 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3457 3458 /* Set the pulse width and recovery timing parameters */ 3459 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3460 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3461 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3462 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3463 3464 /* Set the Enhanced Mode register appropriately */ 3465 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3466 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3467 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3468 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3469 } 3470 3471 /* Finally, enable the timings */ 3472 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3473 3474 pciide_print_modes(cp); 3475 } 3476
Indexes created Mon Sep 22 10:09:38 GMT 2025