pciide.c revision 1.89
1 /* $NetBSD: pciide.c,v 1.89 2000/11/05 21:14:59 matt Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 #include <dev/pci/pciidereg.h> 105 #include <dev/pci/pciidevar.h> 106 #include <dev/pci/pciide_piix_reg.h> 107 #include <dev/pci/pciide_amd_reg.h> 108 #include <dev/pci/pciide_apollo_reg.h> 109 #include <dev/pci/pciide_cmd_reg.h> 110 #include <dev/pci/pciide_cy693_reg.h> 111 #include <dev/pci/pciide_sis_reg.h> 112 #include <dev/pci/pciide_acer_reg.h> 113 #include <dev/pci/pciide_pdc202xx_reg.h> 114 #include <dev/pci/pciide_opti_reg.h> 115 #include <dev/pci/pciide_hpt_reg.h> 116 #include <dev/pci/cy82c693var.h> 117 118 #include "opt_pciide.h" 119 120 /* inlines for reading/writing 8-bit PCI registers */ 121 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 122 int)); 123 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 124 int, u_int8_t)); 125 126 static __inline u_int8_t 127 pciide_pci_read(pc, pa, reg) 128 pci_chipset_tag_t pc; 129 pcitag_t pa; 130 int reg; 131 { 132 133 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 134 ((reg & 0x03) * 8) & 0xff); 135 } 136 137 static __inline void 138 pciide_pci_write(pc, pa, reg, val) 139 pci_chipset_tag_t pc; 140 pcitag_t pa; 141 int reg; 142 u_int8_t val; 143 { 144 pcireg_t pcival; 145 146 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 147 pcival &= ~(0xff << ((reg & 0x03) * 8)); 148 pcival |= (val << ((reg & 0x03) * 8)); 149 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 150 } 151 152 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 153 154 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 155 void piix_setup_channel __P((struct channel_softc*)); 156 void piix3_4_setup_channel __P((struct channel_softc*)); 157 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 158 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 159 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 160 161 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 162 void amd756_setup_channel __P((struct channel_softc*)); 163 164 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void apollo_setup_channel __P((struct channel_softc*)); 166 167 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 169 void cmd0643_9_setup_channel __P((struct channel_softc*)); 170 void cmd_channel_map __P((struct pci_attach_args *, 171 struct pciide_softc *, int)); 172 int cmd_pci_intr __P((void *)); 173 void cmd646_9_irqack __P((struct channel_softc *)); 174 175 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 176 void cy693_setup_channel __P((struct channel_softc*)); 177 178 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 179 void sis_setup_channel __P((struct channel_softc*)); 180 181 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void acer_setup_channel __P((struct channel_softc*)); 183 int acer_pci_intr __P((void *)); 184 185 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 186 void pdc202xx_setup_channel __P((struct channel_softc*)); 187 int pdc202xx_pci_intr __P((void *)); 188 189 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 190 void opti_setup_channel __P((struct channel_softc*)); 191 192 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void hpt_setup_channel __P((struct channel_softc*)); 194 int hpt_pci_intr __P((void *)); 195 196 void pciide_channel_dma_setup __P((struct pciide_channel *)); 197 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 198 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 199 void pciide_dma_start __P((void*, int, int)); 200 int pciide_dma_finish __P((void*, int, int, int)); 201 void pciide_irqack __P((struct channel_softc *)); 202 void pciide_print_modes __P((struct pciide_channel *)); 203 204 struct pciide_product_desc { 205 u_int32_t ide_product; 206 int ide_flags; 207 const char *ide_name; 208 /* map and setup chip, probe drives */ 209 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 210 }; 211 212 /* Flags for ide_flags */ 213 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 214 215 /* Default product description for devices not known from this controller */ 216 const struct pciide_product_desc default_product_desc = { 217 0, 218 0, 219 "Generic PCI IDE controller", 220 default_chip_map, 221 }; 222 223 const struct pciide_product_desc pciide_intel_products[] = { 224 { PCI_PRODUCT_INTEL_82092AA, 225 0, 226 "Intel 82092AA IDE controller", 227 default_chip_map, 228 }, 229 { PCI_PRODUCT_INTEL_82371FB_IDE, 230 0, 231 "Intel 82371FB IDE controller (PIIX)", 232 piix_chip_map, 233 }, 234 { PCI_PRODUCT_INTEL_82371SB_IDE, 235 0, 236 "Intel 82371SB IDE Interface (PIIX3)", 237 piix_chip_map, 238 }, 239 { PCI_PRODUCT_INTEL_82371AB_IDE, 240 0, 241 "Intel 82371AB IDE controller (PIIX4)", 242 piix_chip_map, 243 }, 244 { PCI_PRODUCT_INTEL_82440MX_IDE, 245 0, 246 "Intel 82440MX IDE controller", 247 piix_chip_map 248 }, 249 { PCI_PRODUCT_INTEL_82801AA_IDE, 250 0, 251 "Intel 82801AA IDE Controller (ICH)", 252 piix_chip_map, 253 }, 254 { PCI_PRODUCT_INTEL_82801AB_IDE, 255 0, 256 "Intel 82801AB IDE Controller (ICH0)", 257 piix_chip_map, 258 }, 259 { 0, 260 0, 261 NULL, 262 } 263 }; 264 265 const struct pciide_product_desc pciide_amd_products[] = { 266 { PCI_PRODUCT_AMD_PBC756_IDE, 267 0, 268 "Advanced Micro Devices AMD756 IDE Controller", 269 amd756_chip_map 270 }, 271 { 0, 272 0, 273 NULL, 274 } 275 }; 276 277 const struct pciide_product_desc pciide_cmd_products[] = { 278 { PCI_PRODUCT_CMDTECH_640, 279 0, 280 "CMD Technology PCI0640", 281 cmd_chip_map 282 }, 283 { PCI_PRODUCT_CMDTECH_643, 284 0, 285 "CMD Technology PCI0643", 286 cmd0643_9_chip_map, 287 }, 288 { PCI_PRODUCT_CMDTECH_646, 289 0, 290 "CMD Technology PCI0646", 291 cmd0643_9_chip_map, 292 }, 293 { PCI_PRODUCT_CMDTECH_648, 294 IDE_PCI_CLASS_OVERRIDE, 295 "CMD Technology PCI0648", 296 cmd0643_9_chip_map, 297 }, 298 { PCI_PRODUCT_CMDTECH_649, 299 IDE_PCI_CLASS_OVERRIDE, 300 "CMD Technology PCI0649", 301 cmd0643_9_chip_map, 302 }, 303 { 0, 304 0, 305 NULL, 306 } 307 }; 308 309 const struct pciide_product_desc pciide_via_products[] = { 310 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 311 0, 312 "VIA Tech VT82C586 IDE Controller", 313 apollo_chip_map, 314 }, 315 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 316 0, 317 "VIA Tech VT82C586A IDE Controller", 318 apollo_chip_map, 319 }, 320 { 0, 321 0, 322 NULL, 323 } 324 }; 325 326 const struct pciide_product_desc pciide_cypress_products[] = { 327 { PCI_PRODUCT_CONTAQ_82C693, 328 0, 329 "Cypress 82C693 IDE Controller", 330 cy693_chip_map, 331 }, 332 { 0, 333 0, 334 NULL, 335 } 336 }; 337 338 const struct pciide_product_desc pciide_sis_products[] = { 339 { PCI_PRODUCT_SIS_5597_IDE, 340 0, 341 "Silicon Integrated System 5597/5598 IDE controller", 342 sis_chip_map, 343 }, 344 { 0, 345 0, 346 NULL, 347 } 348 }; 349 350 const struct pciide_product_desc pciide_acer_products[] = { 351 { PCI_PRODUCT_ALI_M5229, 352 0, 353 "Acer Labs M5229 UDMA IDE Controller", 354 acer_chip_map, 355 }, 356 { 0, 357 0, 358 NULL, 359 } 360 }; 361 362 const struct pciide_product_desc pciide_promise_products[] = { 363 { PCI_PRODUCT_PROMISE_ULTRA33, 364 IDE_PCI_CLASS_OVERRIDE, 365 "Promise Ultra33/ATA Bus Master IDE Accelerator", 366 pdc202xx_chip_map, 367 }, 368 { PCI_PRODUCT_PROMISE_ULTRA66, 369 IDE_PCI_CLASS_OVERRIDE, 370 "Promise Ultra66/ATA Bus Master IDE Accelerator", 371 pdc202xx_chip_map, 372 }, 373 { PCI_PRODUCT_PROMISE_ULTRA100, 374 IDE_PCI_CLASS_OVERRIDE, 375 "Promise Ultra100/ATA Bus Master IDE Accelerator", 376 pdc202xx_chip_map, 377 }, 378 { PCI_PRODUCT_PROMISE_ULTRA100X, 379 IDE_PCI_CLASS_OVERRIDE, 380 "Promise Ultra100/ATA Bus Master IDE Accelerator", 381 pdc202xx_chip_map, 382 }, 383 { 0, 384 0, 385 NULL, 386 } 387 }; 388 389 const struct pciide_product_desc pciide_opti_products[] = { 390 { PCI_PRODUCT_OPTI_82C621, 391 0, 392 "OPTi 82c621 PCI IDE controller", 393 opti_chip_map, 394 }, 395 { PCI_PRODUCT_OPTI_82C568, 396 0, 397 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 398 opti_chip_map, 399 }, 400 { PCI_PRODUCT_OPTI_82D568, 401 0, 402 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 403 opti_chip_map, 404 }, 405 { 0, 406 0, 407 NULL, 408 } 409 }; 410 411 const struct pciide_product_desc pciide_triones_products[] = { 412 { PCI_PRODUCT_TRIONES_HPT366, 413 IDE_PCI_CLASS_OVERRIDE, 414 "Triones/Highpoint HPT366/370 IDE Controller", 415 hpt_chip_map, 416 }, 417 { 0, 418 0, 419 NULL, 420 } 421 }; 422 423 struct pciide_vendor_desc { 424 u_int32_t ide_vendor; 425 const struct pciide_product_desc *ide_products; 426 }; 427 428 const struct pciide_vendor_desc pciide_vendors[] = { 429 { PCI_VENDOR_INTEL, pciide_intel_products }, 430 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 431 { PCI_VENDOR_VIATECH, pciide_via_products }, 432 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 433 { PCI_VENDOR_SIS, pciide_sis_products }, 434 { PCI_VENDOR_ALI, pciide_acer_products }, 435 { PCI_VENDOR_PROMISE, pciide_promise_products }, 436 { PCI_VENDOR_AMD, pciide_amd_products }, 437 { PCI_VENDOR_OPTI, pciide_opti_products }, 438 { PCI_VENDOR_TRIONES, pciide_triones_products }, 439 { 0, NULL } 440 }; 441 442 /* options passed via the 'flags' config keyword */ 443 #define PCIIDE_OPTIONS_DMA 0x01 444 445 int pciide_match __P((struct device *, struct cfdata *, void *)); 446 void pciide_attach __P((struct device *, struct device *, void *)); 447 448 struct cfattach pciide_ca = { 449 sizeof(struct pciide_softc), pciide_match, pciide_attach 450 }; 451 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 452 int pciide_mapregs_compat __P(( struct pci_attach_args *, 453 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 454 int pciide_mapregs_native __P((struct pci_attach_args *, 455 struct pciide_channel *, bus_size_t *, bus_size_t *, 456 int (*pci_intr) __P((void *)))); 457 void pciide_mapreg_dma __P((struct pciide_softc *, 458 struct pci_attach_args *)); 459 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 460 void pciide_mapchan __P((struct pci_attach_args *, 461 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 462 int (*pci_intr) __P((void *)))); 463 int pciide_chan_candisable __P((struct pciide_channel *)); 464 void pciide_map_compat_intr __P(( struct pci_attach_args *, 465 struct pciide_channel *, int, int)); 466 int pciide_print __P((void *, const char *pnp)); 467 int pciide_compat_intr __P((void *)); 468 int pciide_pci_intr __P((void *)); 469 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 470 471 const struct pciide_product_desc * 472 pciide_lookup_product(id) 473 u_int32_t id; 474 { 475 const struct pciide_product_desc *pp; 476 const struct pciide_vendor_desc *vp; 477 478 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 479 if (PCI_VENDOR(id) == vp->ide_vendor) 480 break; 481 482 if ((pp = vp->ide_products) == NULL) 483 return NULL; 484 485 for (; pp->ide_name != NULL; pp++) 486 if (PCI_PRODUCT(id) == pp->ide_product) 487 break; 488 489 if (pp->ide_name == NULL) 490 return NULL; 491 return pp; 492 } 493 494 int 495 pciide_match(parent, match, aux) 496 struct device *parent; 497 struct cfdata *match; 498 void *aux; 499 { 500 struct pci_attach_args *pa = aux; 501 const struct pciide_product_desc *pp; 502 503 /* 504 * Check the ID register to see that it's a PCI IDE controller. 505 * If it is, we assume that we can deal with it; it _should_ 506 * work in a standardized way... 507 */ 508 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 509 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 510 return (1); 511 } 512 513 /* 514 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 515 * controllers. Let see if we can deal with it anyway. 516 */ 517 pp = pciide_lookup_product(pa->pa_id); 518 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 519 return (1); 520 } 521 522 return (0); 523 } 524 525 void 526 pciide_attach(parent, self, aux) 527 struct device *parent, *self; 528 void *aux; 529 { 530 struct pci_attach_args *pa = aux; 531 pci_chipset_tag_t pc = pa->pa_pc; 532 pcitag_t tag = pa->pa_tag; 533 struct pciide_softc *sc = (struct pciide_softc *)self; 534 pcireg_t csr; 535 char devinfo[256]; 536 const char *displaydev; 537 538 sc->sc_pp = pciide_lookup_product(pa->pa_id); 539 if (sc->sc_pp == NULL) { 540 sc->sc_pp = &default_product_desc; 541 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 542 displaydev = devinfo; 543 } else 544 displaydev = sc->sc_pp->ide_name; 545 546 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 547 548 sc->sc_pc = pa->pa_pc; 549 sc->sc_tag = pa->pa_tag; 550 #ifdef WDCDEBUG 551 if (wdcdebug_pciide_mask & DEBUG_PROBE) 552 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 553 #endif 554 sc->sc_pp->chip_map(sc, pa); 555 556 if (sc->sc_dma_ok) { 557 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 558 csr |= PCI_COMMAND_MASTER_ENABLE; 559 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 560 } 561 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 562 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 563 } 564 565 /* tell wether the chip is enabled or not */ 566 int 567 pciide_chipen(sc, pa) 568 struct pciide_softc *sc; 569 struct pci_attach_args *pa; 570 { 571 pcireg_t csr; 572 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 573 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 574 PCI_COMMAND_STATUS_REG); 575 printf("%s: device disabled (at %s)\n", 576 sc->sc_wdcdev.sc_dev.dv_xname, 577 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 578 "device" : "bridge"); 579 return 0; 580 } 581 return 1; 582 } 583 584 int 585 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 586 struct pci_attach_args *pa; 587 struct pciide_channel *cp; 588 int compatchan; 589 bus_size_t *cmdsizep, *ctlsizep; 590 { 591 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 592 struct channel_softc *wdc_cp = &cp->wdc_channel; 593 594 cp->compat = 1; 595 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 596 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 597 598 wdc_cp->cmd_iot = pa->pa_iot; 599 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 600 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 601 printf("%s: couldn't map %s channel cmd regs\n", 602 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 603 return (0); 604 } 605 606 wdc_cp->ctl_iot = pa->pa_iot; 607 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 608 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 609 printf("%s: couldn't map %s channel ctl regs\n", 610 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 611 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 612 PCIIDE_COMPAT_CMD_SIZE); 613 return (0); 614 } 615 616 return (1); 617 } 618 619 int 620 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 621 struct pci_attach_args * pa; 622 struct pciide_channel *cp; 623 bus_size_t *cmdsizep, *ctlsizep; 624 int (*pci_intr) __P((void *)); 625 { 626 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 627 struct channel_softc *wdc_cp = &cp->wdc_channel; 628 const char *intrstr; 629 pci_intr_handle_t intrhandle; 630 631 cp->compat = 0; 632 633 if (sc->sc_pci_ih == NULL) { 634 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 635 pa->pa_intrline, &intrhandle) != 0) { 636 printf("%s: couldn't map native-PCI interrupt\n", 637 sc->sc_wdcdev.sc_dev.dv_xname); 638 return 0; 639 } 640 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 641 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 642 intrhandle, IPL_BIO, pci_intr, sc); 643 if (sc->sc_pci_ih != NULL) { 644 printf("%s: using %s for native-PCI interrupt\n", 645 sc->sc_wdcdev.sc_dev.dv_xname, 646 intrstr ? intrstr : "unknown interrupt"); 647 } else { 648 printf("%s: couldn't establish native-PCI interrupt", 649 sc->sc_wdcdev.sc_dev.dv_xname); 650 if (intrstr != NULL) 651 printf(" at %s", intrstr); 652 printf("\n"); 653 return 0; 654 } 655 } 656 cp->ih = sc->sc_pci_ih; 657 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 658 PCI_MAPREG_TYPE_IO, 0, 659 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 660 printf("%s: couldn't map %s channel cmd regs\n", 661 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 662 return 0; 663 } 664 665 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 666 PCI_MAPREG_TYPE_IO, 0, 667 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 668 printf("%s: couldn't map %s channel ctl regs\n", 669 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 670 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 671 return 0; 672 } 673 return (1); 674 } 675 676 void 677 pciide_mapreg_dma(sc, pa) 678 struct pciide_softc *sc; 679 struct pci_attach_args *pa; 680 { 681 pcireg_t maptype; 682 bus_addr_t addr; 683 684 /* 685 * Map DMA registers 686 * 687 * Note that sc_dma_ok is the right variable to test to see if 688 * DMA can be done. If the interface doesn't support DMA, 689 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 690 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 691 * non-zero if the interface supports DMA and the registers 692 * could be mapped. 693 * 694 * XXX Note that despite the fact that the Bus Master IDE specs 695 * XXX say that "The bus master IDE function uses 16 bytes of IO 696 * XXX space," some controllers (at least the United 697 * XXX Microelectronics UM8886BF) place it in memory space. 698 */ 699 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 700 PCIIDE_REG_BUS_MASTER_DMA); 701 702 switch (maptype) { 703 case PCI_MAPREG_TYPE_IO: 704 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 705 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 706 &addr, NULL, NULL) == 0); 707 if (sc->sc_dma_ok == 0) { 708 printf(", but unused (couldn't query registers)"); 709 break; 710 } 711 if (addr >= 0x10000) { 712 sc->sc_dma_ok = 0; 713 printf(", but unused (registers at unsafe address %#lx)", addr); 714 break; 715 } 716 /* FALLTHROUGH */ 717 718 case PCI_MAPREG_MEM_TYPE_32BIT: 719 sc->sc_dma_ok = (pci_mapreg_map(pa, 720 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 721 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 722 sc->sc_dmat = pa->pa_dmat; 723 if (sc->sc_dma_ok == 0) { 724 printf(", but unused (couldn't map registers)"); 725 } else { 726 sc->sc_wdcdev.dma_arg = sc; 727 sc->sc_wdcdev.dma_init = pciide_dma_init; 728 sc->sc_wdcdev.dma_start = pciide_dma_start; 729 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 730 } 731 break; 732 733 default: 734 sc->sc_dma_ok = 0; 735 printf(", but unsupported register maptype (0x%x)", maptype); 736 } 737 } 738 739 int 740 pciide_compat_intr(arg) 741 void *arg; 742 { 743 struct pciide_channel *cp = arg; 744 745 #ifdef DIAGNOSTIC 746 /* should only be called for a compat channel */ 747 if (cp->compat == 0) 748 panic("pciide compat intr called for non-compat chan %p\n", cp); 749 #endif 750 return (wdcintr(&cp->wdc_channel)); 751 } 752 753 int 754 pciide_pci_intr(arg) 755 void *arg; 756 { 757 struct pciide_softc *sc = arg; 758 struct pciide_channel *cp; 759 struct channel_softc *wdc_cp; 760 int i, rv, crv; 761 762 rv = 0; 763 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 764 cp = &sc->pciide_channels[i]; 765 wdc_cp = &cp->wdc_channel; 766 767 /* If a compat channel skip. */ 768 if (cp->compat) 769 continue; 770 /* if this channel not waiting for intr, skip */ 771 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 772 continue; 773 774 crv = wdcintr(wdc_cp); 775 if (crv == 0) 776 ; /* leave rv alone */ 777 else if (crv == 1) 778 rv = 1; /* claim the intr */ 779 else if (rv == 0) /* crv should be -1 in this case */ 780 rv = crv; /* if we've done no better, take it */ 781 } 782 return (rv); 783 } 784 785 void 786 pciide_channel_dma_setup(cp) 787 struct pciide_channel *cp; 788 { 789 int drive; 790 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 791 struct ata_drive_datas *drvp; 792 793 for (drive = 0; drive < 2; drive++) { 794 drvp = &cp->wdc_channel.ch_drive[drive]; 795 /* If no drive, skip */ 796 if ((drvp->drive_flags & DRIVE) == 0) 797 continue; 798 /* setup DMA if needed */ 799 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 800 (drvp->drive_flags & DRIVE_UDMA) == 0) || 801 sc->sc_dma_ok == 0) { 802 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 803 continue; 804 } 805 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 806 != 0) { 807 /* Abort DMA setup */ 808 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 809 continue; 810 } 811 } 812 } 813 814 int 815 pciide_dma_table_setup(sc, channel, drive) 816 struct pciide_softc *sc; 817 int channel, drive; 818 { 819 bus_dma_segment_t seg; 820 int error, rseg; 821 const bus_size_t dma_table_size = 822 sizeof(struct idedma_table) * NIDEDMA_TABLES; 823 struct pciide_dma_maps *dma_maps = 824 &sc->pciide_channels[channel].dma_maps[drive]; 825 826 /* If table was already allocated, just return */ 827 if (dma_maps->dma_table) 828 return 0; 829 830 /* Allocate memory for the DMA tables and map it */ 831 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 832 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 833 BUS_DMA_NOWAIT)) != 0) { 834 printf("%s:%d: unable to allocate table DMA for " 835 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 836 channel, drive, error); 837 return error; 838 } 839 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 840 dma_table_size, 841 (caddr_t *)&dma_maps->dma_table, 842 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 843 printf("%s:%d: unable to map table DMA for" 844 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 845 channel, drive, error); 846 return error; 847 } 848 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 849 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 850 seg.ds_addr), DEBUG_PROBE); 851 852 /* Create and load table DMA map for this disk */ 853 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 854 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 855 &dma_maps->dmamap_table)) != 0) { 856 printf("%s:%d: unable to create table DMA map for " 857 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 858 channel, drive, error); 859 return error; 860 } 861 if ((error = bus_dmamap_load(sc->sc_dmat, 862 dma_maps->dmamap_table, 863 dma_maps->dma_table, 864 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 865 printf("%s:%d: unable to load table DMA map for " 866 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 867 channel, drive, error); 868 return error; 869 } 870 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 871 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 872 /* Create a xfer DMA map for this drive */ 873 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 874 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 875 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 876 &dma_maps->dmamap_xfer)) != 0) { 877 printf("%s:%d: unable to create xfer DMA map for " 878 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 879 channel, drive, error); 880 return error; 881 } 882 return 0; 883 } 884 885 int 886 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 887 void *v; 888 int channel, drive; 889 void *databuf; 890 size_t datalen; 891 int flags; 892 { 893 struct pciide_softc *sc = v; 894 int error, seg; 895 struct pciide_dma_maps *dma_maps = 896 &sc->pciide_channels[channel].dma_maps[drive]; 897 898 error = bus_dmamap_load(sc->sc_dmat, 899 dma_maps->dmamap_xfer, 900 databuf, datalen, NULL, BUS_DMA_NOWAIT); 901 if (error) { 902 printf("%s:%d: unable to load xfer DMA map for" 903 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 904 channel, drive, error); 905 return error; 906 } 907 908 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 909 dma_maps->dmamap_xfer->dm_mapsize, 910 (flags & WDC_DMA_READ) ? 911 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 912 913 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 914 #ifdef DIAGNOSTIC 915 /* A segment must not cross a 64k boundary */ 916 { 917 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 918 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 919 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 920 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 921 printf("pciide_dma: segment %d physical addr 0x%lx" 922 " len 0x%lx not properly aligned\n", 923 seg, phys, len); 924 panic("pciide_dma: buf align"); 925 } 926 } 927 #endif 928 dma_maps->dma_table[seg].base_addr = 929 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 930 dma_maps->dma_table[seg].byte_count = 931 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 932 IDEDMA_BYTE_COUNT_MASK); 933 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 934 seg, le32toh(dma_maps->dma_table[seg].byte_count), 935 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 936 937 } 938 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 939 htole32(IDEDMA_BYTE_COUNT_EOT); 940 941 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 942 dma_maps->dmamap_table->dm_mapsize, 943 BUS_DMASYNC_PREWRITE); 944 945 /* Maps are ready. Start DMA function */ 946 #ifdef DIAGNOSTIC 947 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 948 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 949 dma_maps->dmamap_table->dm_segs[0].ds_addr); 950 panic("pciide_dma_init: table align"); 951 } 952 #endif 953 954 /* Clear status bits */ 955 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 956 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 957 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 958 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 959 /* Write table addr */ 960 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 961 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 962 dma_maps->dmamap_table->dm_segs[0].ds_addr); 963 /* set read/write */ 964 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 965 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 966 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 967 /* remember flags */ 968 dma_maps->dma_flags = flags; 969 return 0; 970 } 971 972 void 973 pciide_dma_start(v, channel, drive) 974 void *v; 975 int channel, drive; 976 { 977 struct pciide_softc *sc = v; 978 979 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 980 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 981 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 982 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 983 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 984 } 985 986 int 987 pciide_dma_finish(v, channel, drive, force) 988 void *v; 989 int channel, drive; 990 int force; 991 { 992 struct pciide_softc *sc = v; 993 u_int8_t status; 994 int error = 0; 995 struct pciide_dma_maps *dma_maps = 996 &sc->pciide_channels[channel].dma_maps[drive]; 997 998 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 999 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1000 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1001 DEBUG_XFERS); 1002 1003 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1004 return WDC_DMAST_NOIRQ; 1005 1006 /* stop DMA channel */ 1007 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1008 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1009 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1010 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1011 1012 /* Unload the map of the data buffer */ 1013 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1014 dma_maps->dmamap_xfer->dm_mapsize, 1015 (dma_maps->dma_flags & WDC_DMA_READ) ? 1016 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1017 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1018 1019 if ((status & IDEDMA_CTL_ERR) != 0) { 1020 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1021 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1022 error |= WDC_DMAST_ERR; 1023 } 1024 1025 if ((status & IDEDMA_CTL_INTR) == 0) { 1026 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1027 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1028 drive, status); 1029 error |= WDC_DMAST_NOIRQ; 1030 } 1031 1032 if ((status & IDEDMA_CTL_ACT) != 0) { 1033 /* data underrun, may be a valid condition for ATAPI */ 1034 error |= WDC_DMAST_UNDER; 1035 } 1036 return error; 1037 } 1038 1039 void 1040 pciide_irqack(chp) 1041 struct channel_softc *chp; 1042 { 1043 struct pciide_channel *cp = (struct pciide_channel*)chp; 1044 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1045 1046 /* clear status bits in IDE DMA registers */ 1047 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1048 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1049 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1050 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1051 } 1052 1053 /* some common code used by several chip_map */ 1054 int 1055 pciide_chansetup(sc, channel, interface) 1056 struct pciide_softc *sc; 1057 int channel; 1058 pcireg_t interface; 1059 { 1060 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1061 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1062 cp->name = PCIIDE_CHANNEL_NAME(channel); 1063 cp->wdc_channel.channel = channel; 1064 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1065 cp->wdc_channel.ch_queue = 1066 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1067 if (cp->wdc_channel.ch_queue == NULL) { 1068 printf("%s %s channel: " 1069 "can't allocate memory for command queue", 1070 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1071 return 0; 1072 } 1073 printf("%s: %s channel %s to %s mode\n", 1074 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1075 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1076 "configured" : "wired", 1077 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1078 "native-PCI" : "compatibility"); 1079 return 1; 1080 } 1081 1082 /* some common code used by several chip channel_map */ 1083 void 1084 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1085 struct pci_attach_args *pa; 1086 struct pciide_channel *cp; 1087 pcireg_t interface; 1088 bus_size_t *cmdsizep, *ctlsizep; 1089 int (*pci_intr) __P((void *)); 1090 { 1091 struct channel_softc *wdc_cp = &cp->wdc_channel; 1092 1093 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1094 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1095 pci_intr); 1096 else 1097 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1098 wdc_cp->channel, cmdsizep, ctlsizep); 1099 1100 if (cp->hw_ok == 0) 1101 return; 1102 wdc_cp->data32iot = wdc_cp->cmd_iot; 1103 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1104 wdcattach(wdc_cp); 1105 } 1106 1107 /* 1108 * Generic code to call to know if a channel can be disabled. Return 1 1109 * if channel can be disabled, 0 if not 1110 */ 1111 int 1112 pciide_chan_candisable(cp) 1113 struct pciide_channel *cp; 1114 { 1115 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1116 struct channel_softc *wdc_cp = &cp->wdc_channel; 1117 1118 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1119 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1120 printf("%s: disabling %s channel (no drives)\n", 1121 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1122 cp->hw_ok = 0; 1123 return 1; 1124 } 1125 return 0; 1126 } 1127 1128 /* 1129 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1130 * Set hw_ok=0 on failure 1131 */ 1132 void 1133 pciide_map_compat_intr(pa, cp, compatchan, interface) 1134 struct pci_attach_args *pa; 1135 struct pciide_channel *cp; 1136 int compatchan, interface; 1137 { 1138 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1139 struct channel_softc *wdc_cp = &cp->wdc_channel; 1140 1141 if (cp->hw_ok == 0) 1142 return; 1143 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1144 return; 1145 1146 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1147 pa, compatchan, pciide_compat_intr, cp); 1148 if (cp->ih == NULL) { 1149 printf("%s: no compatibility interrupt for use by %s " 1150 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1151 cp->hw_ok = 0; 1152 } 1153 } 1154 1155 void 1156 pciide_print_modes(cp) 1157 struct pciide_channel *cp; 1158 { 1159 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1160 int drive; 1161 struct channel_softc *chp; 1162 struct ata_drive_datas *drvp; 1163 1164 chp = &cp->wdc_channel; 1165 for (drive = 0; drive < 2; drive++) { 1166 drvp = &chp->ch_drive[drive]; 1167 if ((drvp->drive_flags & DRIVE) == 0) 1168 continue; 1169 printf("%s(%s:%d:%d): using PIO mode %d", 1170 drvp->drv_softc->dv_xname, 1171 sc->sc_wdcdev.sc_dev.dv_xname, 1172 chp->channel, drive, drvp->PIO_mode); 1173 if (drvp->drive_flags & DRIVE_DMA) 1174 printf(", DMA mode %d", drvp->DMA_mode); 1175 if (drvp->drive_flags & DRIVE_UDMA) 1176 printf(", Ultra-DMA mode %d", drvp->UDMA_mode); 1177 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 1178 printf(" (using DMA data transfers)"); 1179 printf("\n"); 1180 } 1181 } 1182 1183 void 1184 default_chip_map(sc, pa) 1185 struct pciide_softc *sc; 1186 struct pci_attach_args *pa; 1187 { 1188 struct pciide_channel *cp; 1189 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1190 pcireg_t csr; 1191 int channel, drive; 1192 struct ata_drive_datas *drvp; 1193 u_int8_t idedma_ctl; 1194 bus_size_t cmdsize, ctlsize; 1195 char *failreason; 1196 1197 if (pciide_chipen(sc, pa) == 0) 1198 return; 1199 1200 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1201 printf("%s: bus-master DMA support present", 1202 sc->sc_wdcdev.sc_dev.dv_xname); 1203 if (sc->sc_pp == &default_product_desc && 1204 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1205 PCIIDE_OPTIONS_DMA) == 0) { 1206 printf(", but unused (no driver support)"); 1207 sc->sc_dma_ok = 0; 1208 } else { 1209 pciide_mapreg_dma(sc, pa); 1210 if (sc->sc_dma_ok != 0) 1211 printf(", used without full driver " 1212 "support"); 1213 } 1214 } else { 1215 printf("%s: hardware does not support DMA", 1216 sc->sc_wdcdev.sc_dev.dv_xname); 1217 sc->sc_dma_ok = 0; 1218 } 1219 printf("\n"); 1220 if (sc->sc_dma_ok) { 1221 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1222 sc->sc_wdcdev.irqack = pciide_irqack; 1223 } 1224 sc->sc_wdcdev.PIO_cap = 0; 1225 sc->sc_wdcdev.DMA_cap = 0; 1226 1227 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1228 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1229 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1230 1231 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1232 cp = &sc->pciide_channels[channel]; 1233 if (pciide_chansetup(sc, channel, interface) == 0) 1234 continue; 1235 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1236 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1237 &ctlsize, pciide_pci_intr); 1238 } else { 1239 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1240 channel, &cmdsize, &ctlsize); 1241 } 1242 if (cp->hw_ok == 0) 1243 continue; 1244 /* 1245 * Check to see if something appears to be there. 1246 */ 1247 failreason = NULL; 1248 if (!wdcprobe(&cp->wdc_channel)) { 1249 failreason = "not responding; disabled or no drives?"; 1250 goto next; 1251 } 1252 /* 1253 * Now, make sure it's actually attributable to this PCI IDE 1254 * channel by trying to access the channel again while the 1255 * PCI IDE controller's I/O space is disabled. (If the 1256 * channel no longer appears to be there, it belongs to 1257 * this controller.) YUCK! 1258 */ 1259 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1260 PCI_COMMAND_STATUS_REG); 1261 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1262 csr & ~PCI_COMMAND_IO_ENABLE); 1263 if (wdcprobe(&cp->wdc_channel)) 1264 failreason = "other hardware responding at addresses"; 1265 pci_conf_write(sc->sc_pc, sc->sc_tag, 1266 PCI_COMMAND_STATUS_REG, csr); 1267 next: 1268 if (failreason) { 1269 printf("%s: %s channel ignored (%s)\n", 1270 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1271 failreason); 1272 cp->hw_ok = 0; 1273 bus_space_unmap(cp->wdc_channel.cmd_iot, 1274 cp->wdc_channel.cmd_ioh, cmdsize); 1275 bus_space_unmap(cp->wdc_channel.ctl_iot, 1276 cp->wdc_channel.ctl_ioh, ctlsize); 1277 } else { 1278 pciide_map_compat_intr(pa, cp, channel, interface); 1279 } 1280 if (cp->hw_ok) { 1281 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1282 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1283 wdcattach(&cp->wdc_channel); 1284 } 1285 } 1286 1287 if (sc->sc_dma_ok == 0) 1288 return; 1289 1290 /* Allocate DMA maps */ 1291 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1292 idedma_ctl = 0; 1293 cp = &sc->pciide_channels[channel]; 1294 for (drive = 0; drive < 2; drive++) { 1295 drvp = &cp->wdc_channel.ch_drive[drive]; 1296 /* If no drive, skip */ 1297 if ((drvp->drive_flags & DRIVE) == 0) 1298 continue; 1299 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1300 continue; 1301 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1302 /* Abort DMA setup */ 1303 printf("%s:%d:%d: can't allocate DMA maps, " 1304 "using PIO transfers\n", 1305 sc->sc_wdcdev.sc_dev.dv_xname, 1306 channel, drive); 1307 drvp->drive_flags &= ~DRIVE_DMA; 1308 } 1309 printf("%s:%d:%d: using DMA data transfers\n", 1310 sc->sc_wdcdev.sc_dev.dv_xname, 1311 channel, drive); 1312 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1313 } 1314 if (idedma_ctl != 0) { 1315 /* Add software bits in status register */ 1316 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1317 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1318 idedma_ctl); 1319 } 1320 } 1321 } 1322 1323 void 1324 piix_chip_map(sc, pa) 1325 struct pciide_softc *sc; 1326 struct pci_attach_args *pa; 1327 { 1328 struct pciide_channel *cp; 1329 int channel; 1330 u_int32_t idetim; 1331 bus_size_t cmdsize, ctlsize; 1332 1333 if (pciide_chipen(sc, pa) == 0) 1334 return; 1335 1336 printf("%s: bus-master DMA support present", 1337 sc->sc_wdcdev.sc_dev.dv_xname); 1338 pciide_mapreg_dma(sc, pa); 1339 printf("\n"); 1340 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1341 WDC_CAPABILITY_MODE; 1342 if (sc->sc_dma_ok) { 1343 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1344 sc->sc_wdcdev.irqack = pciide_irqack; 1345 switch(sc->sc_pp->ide_product) { 1346 case PCI_PRODUCT_INTEL_82371AB_IDE: 1347 case PCI_PRODUCT_INTEL_82440MX_IDE: 1348 case PCI_PRODUCT_INTEL_82801AA_IDE: 1349 case PCI_PRODUCT_INTEL_82801AB_IDE: 1350 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1351 } 1352 } 1353 sc->sc_wdcdev.PIO_cap = 4; 1354 sc->sc_wdcdev.DMA_cap = 2; 1355 sc->sc_wdcdev.UDMA_cap = 1356 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1357 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1358 sc->sc_wdcdev.set_modes = piix_setup_channel; 1359 else 1360 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1361 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1362 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1363 1364 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1365 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1366 DEBUG_PROBE); 1367 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1368 WDCDEBUG_PRINT((", sidetim=0x%x", 1369 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1370 DEBUG_PROBE); 1371 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1372 WDCDEBUG_PRINT((", udamreg 0x%x", 1373 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1374 DEBUG_PROBE); 1375 } 1376 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1377 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1378 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1379 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1380 DEBUG_PROBE); 1381 } 1382 1383 } 1384 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1385 1386 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1387 cp = &sc->pciide_channels[channel]; 1388 /* PIIX is compat-only */ 1389 if (pciide_chansetup(sc, channel, 0) == 0) 1390 continue; 1391 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1392 if ((PIIX_IDETIM_READ(idetim, channel) & 1393 PIIX_IDETIM_IDE) == 0) { 1394 printf("%s: %s channel ignored (disabled)\n", 1395 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1396 continue; 1397 } 1398 /* PIIX are compat-only pciide devices */ 1399 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1400 if (cp->hw_ok == 0) 1401 continue; 1402 if (pciide_chan_candisable(cp)) { 1403 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1404 channel); 1405 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1406 idetim); 1407 } 1408 pciide_map_compat_intr(pa, cp, channel, 0); 1409 if (cp->hw_ok == 0) 1410 continue; 1411 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1412 } 1413 1414 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1415 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1416 DEBUG_PROBE); 1417 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1418 WDCDEBUG_PRINT((", sidetim=0x%x", 1419 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1420 DEBUG_PROBE); 1421 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1422 WDCDEBUG_PRINT((", udamreg 0x%x", 1423 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1424 DEBUG_PROBE); 1425 } 1426 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1427 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1428 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1429 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1430 DEBUG_PROBE); 1431 } 1432 } 1433 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1434 } 1435 1436 void 1437 piix_setup_channel(chp) 1438 struct channel_softc *chp; 1439 { 1440 u_int8_t mode[2], drive; 1441 u_int32_t oidetim, idetim, idedma_ctl; 1442 struct pciide_channel *cp = (struct pciide_channel*)chp; 1443 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1444 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1445 1446 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1447 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1448 idedma_ctl = 0; 1449 1450 /* set up new idetim: Enable IDE registers decode */ 1451 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1452 chp->channel); 1453 1454 /* setup DMA */ 1455 pciide_channel_dma_setup(cp); 1456 1457 /* 1458 * Here we have to mess up with drives mode: PIIX can't have 1459 * different timings for master and slave drives. 1460 * We need to find the best combination. 1461 */ 1462 1463 /* If both drives supports DMA, take the lower mode */ 1464 if ((drvp[0].drive_flags & DRIVE_DMA) && 1465 (drvp[1].drive_flags & DRIVE_DMA)) { 1466 mode[0] = mode[1] = 1467 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1468 drvp[0].DMA_mode = mode[0]; 1469 drvp[1].DMA_mode = mode[1]; 1470 goto ok; 1471 } 1472 /* 1473 * If only one drive supports DMA, use its mode, and 1474 * put the other one in PIO mode 0 if mode not compatible 1475 */ 1476 if (drvp[0].drive_flags & DRIVE_DMA) { 1477 mode[0] = drvp[0].DMA_mode; 1478 mode[1] = drvp[1].PIO_mode; 1479 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1480 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1481 mode[1] = drvp[1].PIO_mode = 0; 1482 goto ok; 1483 } 1484 if (drvp[1].drive_flags & DRIVE_DMA) { 1485 mode[1] = drvp[1].DMA_mode; 1486 mode[0] = drvp[0].PIO_mode; 1487 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1488 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1489 mode[0] = drvp[0].PIO_mode = 0; 1490 goto ok; 1491 } 1492 /* 1493 * If both drives are not DMA, takes the lower mode, unless 1494 * one of them is PIO mode < 2 1495 */ 1496 if (drvp[0].PIO_mode < 2) { 1497 mode[0] = drvp[0].PIO_mode = 0; 1498 mode[1] = drvp[1].PIO_mode; 1499 } else if (drvp[1].PIO_mode < 2) { 1500 mode[1] = drvp[1].PIO_mode = 0; 1501 mode[0] = drvp[0].PIO_mode; 1502 } else { 1503 mode[0] = mode[1] = 1504 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1505 drvp[0].PIO_mode = mode[0]; 1506 drvp[1].PIO_mode = mode[1]; 1507 } 1508 ok: /* The modes are setup */ 1509 for (drive = 0; drive < 2; drive++) { 1510 if (drvp[drive].drive_flags & DRIVE_DMA) { 1511 idetim |= piix_setup_idetim_timings( 1512 mode[drive], 1, chp->channel); 1513 goto end; 1514 } 1515 } 1516 /* If we are there, none of the drives are DMA */ 1517 if (mode[0] >= 2) 1518 idetim |= piix_setup_idetim_timings( 1519 mode[0], 0, chp->channel); 1520 else 1521 idetim |= piix_setup_idetim_timings( 1522 mode[1], 0, chp->channel); 1523 end: /* 1524 * timing mode is now set up in the controller. Enable 1525 * it per-drive 1526 */ 1527 for (drive = 0; drive < 2; drive++) { 1528 /* If no drive, skip */ 1529 if ((drvp[drive].drive_flags & DRIVE) == 0) 1530 continue; 1531 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1532 if (drvp[drive].drive_flags & DRIVE_DMA) 1533 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1534 } 1535 if (idedma_ctl != 0) { 1536 /* Add software bits in status register */ 1537 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1538 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1539 idedma_ctl); 1540 } 1541 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1542 pciide_print_modes(cp); 1543 } 1544 1545 void 1546 piix3_4_setup_channel(chp) 1547 struct channel_softc *chp; 1548 { 1549 struct ata_drive_datas *drvp; 1550 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1551 struct pciide_channel *cp = (struct pciide_channel*)chp; 1552 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1553 int drive; 1554 int channel = chp->channel; 1555 1556 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1557 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1558 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1559 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1560 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1561 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1562 PIIX_SIDETIM_RTC_MASK(channel)); 1563 1564 idedma_ctl = 0; 1565 /* If channel disabled, no need to go further */ 1566 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1567 return; 1568 /* set up new idetim: Enable IDE registers decode */ 1569 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1570 1571 /* setup DMA if needed */ 1572 pciide_channel_dma_setup(cp); 1573 1574 for (drive = 0; drive < 2; drive++) { 1575 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1576 PIIX_UDMATIM_SET(0x3, channel, drive)); 1577 drvp = &chp->ch_drive[drive]; 1578 /* If no drive, skip */ 1579 if ((drvp->drive_flags & DRIVE) == 0) 1580 continue; 1581 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1582 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1583 goto pio; 1584 1585 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1586 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1587 ideconf |= PIIX_CONFIG_PINGPONG; 1588 } 1589 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1590 /* setup Ultra/66 */ 1591 if (drvp->UDMA_mode > 2 && 1592 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1593 drvp->UDMA_mode = 2; 1594 if (drvp->UDMA_mode > 2) 1595 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1596 else 1597 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1598 } 1599 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1600 (drvp->drive_flags & DRIVE_UDMA)) { 1601 /* use Ultra/DMA */ 1602 drvp->drive_flags &= ~DRIVE_DMA; 1603 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1604 udmareg |= PIIX_UDMATIM_SET( 1605 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1606 } else { 1607 /* use Multiword DMA */ 1608 drvp->drive_flags &= ~DRIVE_UDMA; 1609 if (drive == 0) { 1610 idetim |= piix_setup_idetim_timings( 1611 drvp->DMA_mode, 1, channel); 1612 } else { 1613 sidetim |= piix_setup_sidetim_timings( 1614 drvp->DMA_mode, 1, channel); 1615 idetim =PIIX_IDETIM_SET(idetim, 1616 PIIX_IDETIM_SITRE, channel); 1617 } 1618 } 1619 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1620 1621 pio: /* use PIO mode */ 1622 idetim |= piix_setup_idetim_drvs(drvp); 1623 if (drive == 0) { 1624 idetim |= piix_setup_idetim_timings( 1625 drvp->PIO_mode, 0, channel); 1626 } else { 1627 sidetim |= piix_setup_sidetim_timings( 1628 drvp->PIO_mode, 0, channel); 1629 idetim =PIIX_IDETIM_SET(idetim, 1630 PIIX_IDETIM_SITRE, channel); 1631 } 1632 } 1633 if (idedma_ctl != 0) { 1634 /* Add software bits in status register */ 1635 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1636 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1637 idedma_ctl); 1638 } 1639 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1640 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1641 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1642 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1643 pciide_print_modes(cp); 1644 } 1645 1646 1647 /* setup ISP and RTC fields, based on mode */ 1648 static u_int32_t 1649 piix_setup_idetim_timings(mode, dma, channel) 1650 u_int8_t mode; 1651 u_int8_t dma; 1652 u_int8_t channel; 1653 { 1654 1655 if (dma) 1656 return PIIX_IDETIM_SET(0, 1657 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1658 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1659 channel); 1660 else 1661 return PIIX_IDETIM_SET(0, 1662 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1663 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1664 channel); 1665 } 1666 1667 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1668 static u_int32_t 1669 piix_setup_idetim_drvs(drvp) 1670 struct ata_drive_datas *drvp; 1671 { 1672 u_int32_t ret = 0; 1673 struct channel_softc *chp = drvp->chnl_softc; 1674 u_int8_t channel = chp->channel; 1675 u_int8_t drive = drvp->drive; 1676 1677 /* 1678 * If drive is using UDMA, timings setups are independant 1679 * So just check DMA and PIO here. 1680 */ 1681 if (drvp->drive_flags & DRIVE_DMA) { 1682 /* if mode = DMA mode 0, use compatible timings */ 1683 if ((drvp->drive_flags & DRIVE_DMA) && 1684 drvp->DMA_mode == 0) { 1685 drvp->PIO_mode = 0; 1686 return ret; 1687 } 1688 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1689 /* 1690 * PIO and DMA timings are the same, use fast timings for PIO 1691 * too, else use compat timings. 1692 */ 1693 if ((piix_isp_pio[drvp->PIO_mode] != 1694 piix_isp_dma[drvp->DMA_mode]) || 1695 (piix_rtc_pio[drvp->PIO_mode] != 1696 piix_rtc_dma[drvp->DMA_mode])) 1697 drvp->PIO_mode = 0; 1698 /* if PIO mode <= 2, use compat timings for PIO */ 1699 if (drvp->PIO_mode <= 2) { 1700 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1701 channel); 1702 return ret; 1703 } 1704 } 1705 1706 /* 1707 * Now setup PIO modes. If mode < 2, use compat timings. 1708 * Else enable fast timings. Enable IORDY and prefetch/post 1709 * if PIO mode >= 3. 1710 */ 1711 1712 if (drvp->PIO_mode < 2) 1713 return ret; 1714 1715 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1716 if (drvp->PIO_mode >= 3) { 1717 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1718 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1719 } 1720 return ret; 1721 } 1722 1723 /* setup values in SIDETIM registers, based on mode */ 1724 static u_int32_t 1725 piix_setup_sidetim_timings(mode, dma, channel) 1726 u_int8_t mode; 1727 u_int8_t dma; 1728 u_int8_t channel; 1729 { 1730 if (dma) 1731 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1732 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1733 else 1734 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1735 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1736 } 1737 1738 void 1739 amd756_chip_map(sc, pa) 1740 struct pciide_softc *sc; 1741 struct pci_attach_args *pa; 1742 { 1743 struct pciide_channel *cp; 1744 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1745 int channel; 1746 pcireg_t chanenable; 1747 bus_size_t cmdsize, ctlsize; 1748 1749 if (pciide_chipen(sc, pa) == 0) 1750 return; 1751 printf("%s: bus-master DMA support present", 1752 sc->sc_wdcdev.sc_dev.dv_xname); 1753 pciide_mapreg_dma(sc, pa); 1754 printf("\n"); 1755 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1756 WDC_CAPABILITY_MODE; 1757 if (sc->sc_dma_ok) { 1758 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1759 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1760 sc->sc_wdcdev.irqack = pciide_irqack; 1761 } 1762 sc->sc_wdcdev.PIO_cap = 4; 1763 sc->sc_wdcdev.DMA_cap = 2; 1764 sc->sc_wdcdev.UDMA_cap = 4; 1765 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1766 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1767 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1768 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1769 1770 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1771 DEBUG_PROBE); 1772 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1773 cp = &sc->pciide_channels[channel]; 1774 if (pciide_chansetup(sc, channel, interface) == 0) 1775 continue; 1776 1777 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1778 printf("%s: %s channel ignored (disabled)\n", 1779 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1780 continue; 1781 } 1782 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1783 pciide_pci_intr); 1784 1785 if (pciide_chan_candisable(cp)) 1786 chanenable &= ~AMD756_CHAN_EN(channel); 1787 pciide_map_compat_intr(pa, cp, channel, interface); 1788 if (cp->hw_ok == 0) 1789 continue; 1790 1791 amd756_setup_channel(&cp->wdc_channel); 1792 } 1793 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1794 chanenable); 1795 return; 1796 } 1797 1798 void 1799 amd756_setup_channel(chp) 1800 struct channel_softc *chp; 1801 { 1802 u_int32_t udmatim_reg, datatim_reg; 1803 u_int8_t idedma_ctl; 1804 int mode, drive; 1805 struct ata_drive_datas *drvp; 1806 struct pciide_channel *cp = (struct pciide_channel*)chp; 1807 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1808 #ifndef PCIIDE_AMD756_ENABLEDMA 1809 int rev = PCI_REVISION( 1810 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1811 #endif 1812 1813 idedma_ctl = 0; 1814 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1815 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1816 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1817 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1818 1819 /* setup DMA if needed */ 1820 pciide_channel_dma_setup(cp); 1821 1822 for (drive = 0; drive < 2; drive++) { 1823 drvp = &chp->ch_drive[drive]; 1824 /* If no drive, skip */ 1825 if ((drvp->drive_flags & DRIVE) == 0) 1826 continue; 1827 /* add timing values, setup DMA if needed */ 1828 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1829 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1830 mode = drvp->PIO_mode; 1831 goto pio; 1832 } 1833 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1834 (drvp->drive_flags & DRIVE_UDMA)) { 1835 /* use Ultra/DMA */ 1836 drvp->drive_flags &= ~DRIVE_DMA; 1837 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1838 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1839 AMD756_UDMA_TIME(chp->channel, drive, 1840 amd756_udma_tim[drvp->UDMA_mode]); 1841 /* can use PIO timings, MW DMA unused */ 1842 mode = drvp->PIO_mode; 1843 } else { 1844 /* use Multiword DMA, but only if revision is OK */ 1845 drvp->drive_flags &= ~DRIVE_UDMA; 1846 #ifndef PCIIDE_AMD756_ENABLEDMA 1847 /* 1848 * The workaround doesn't seem to be necessary 1849 * with all drives, so it can be disabled by 1850 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1851 * triggered. 1852 */ 1853 if (AMD756_CHIPREV_DISABLEDMA(rev)) { 1854 printf("%s:%d:%d: multi-word DMA disabled due " 1855 "to chip revision\n", 1856 sc->sc_wdcdev.sc_dev.dv_xname, 1857 chp->channel, drive); 1858 mode = drvp->PIO_mode; 1859 drvp->drive_flags &= ~DRIVE_DMA; 1860 goto pio; 1861 } 1862 #endif 1863 /* mode = min(pio, dma+2) */ 1864 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1865 mode = drvp->PIO_mode; 1866 else 1867 mode = drvp->DMA_mode + 2; 1868 } 1869 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1870 1871 pio: /* setup PIO mode */ 1872 if (mode <= 2) { 1873 drvp->DMA_mode = 0; 1874 drvp->PIO_mode = 0; 1875 mode = 0; 1876 } else { 1877 drvp->PIO_mode = mode; 1878 drvp->DMA_mode = mode - 2; 1879 } 1880 datatim_reg |= 1881 AMD756_DATATIM_PULSE(chp->channel, drive, 1882 amd756_pio_set[mode]) | 1883 AMD756_DATATIM_RECOV(chp->channel, drive, 1884 amd756_pio_rec[mode]); 1885 } 1886 if (idedma_ctl != 0) { 1887 /* Add software bits in status register */ 1888 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1889 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1890 idedma_ctl); 1891 } 1892 pciide_print_modes(cp); 1893 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1894 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1895 } 1896 1897 void 1898 apollo_chip_map(sc, pa) 1899 struct pciide_softc *sc; 1900 struct pci_attach_args *pa; 1901 { 1902 struct pciide_channel *cp; 1903 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1904 int rev = PCI_REVISION(pa->pa_class); 1905 int channel; 1906 u_int32_t ideconf; 1907 bus_size_t cmdsize, ctlsize; 1908 1909 if (pciide_chipen(sc, pa) == 0) 1910 return; 1911 printf("%s: bus-master DMA support present", 1912 sc->sc_wdcdev.sc_dev.dv_xname); 1913 pciide_mapreg_dma(sc, pa); 1914 printf("\n"); 1915 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1916 WDC_CAPABILITY_MODE; 1917 if (sc->sc_dma_ok) { 1918 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1919 sc->sc_wdcdev.irqack = pciide_irqack; 1920 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE 1921 && rev >= 6) 1922 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1923 } 1924 sc->sc_wdcdev.PIO_cap = 4; 1925 sc->sc_wdcdev.DMA_cap = 2; 1926 sc->sc_wdcdev.UDMA_cap = 2; 1927 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1928 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1929 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1930 1931 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1932 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1933 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1934 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1935 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1936 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1937 DEBUG_PROBE); 1938 1939 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1940 cp = &sc->pciide_channels[channel]; 1941 if (pciide_chansetup(sc, channel, interface) == 0) 1942 continue; 1943 1944 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1945 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1946 printf("%s: %s channel ignored (disabled)\n", 1947 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1948 continue; 1949 } 1950 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1951 pciide_pci_intr); 1952 if (cp->hw_ok == 0) 1953 continue; 1954 if (pciide_chan_candisable(cp)) { 1955 ideconf &= ~APO_IDECONF_EN(channel); 1956 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1957 ideconf); 1958 } 1959 pciide_map_compat_intr(pa, cp, channel, interface); 1960 1961 if (cp->hw_ok == 0) 1962 continue; 1963 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1964 } 1965 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1966 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1967 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1968 } 1969 1970 void 1971 apollo_setup_channel(chp) 1972 struct channel_softc *chp; 1973 { 1974 u_int32_t udmatim_reg, datatim_reg; 1975 u_int8_t idedma_ctl; 1976 int mode, drive; 1977 struct ata_drive_datas *drvp; 1978 struct pciide_channel *cp = (struct pciide_channel*)chp; 1979 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1980 1981 idedma_ctl = 0; 1982 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1983 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1984 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1985 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1986 1987 /* setup DMA if needed */ 1988 pciide_channel_dma_setup(cp); 1989 1990 for (drive = 0; drive < 2; drive++) { 1991 drvp = &chp->ch_drive[drive]; 1992 /* If no drive, skip */ 1993 if ((drvp->drive_flags & DRIVE) == 0) 1994 continue; 1995 /* add timing values, setup DMA if needed */ 1996 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1997 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1998 mode = drvp->PIO_mode; 1999 goto pio; 2000 } 2001 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 2002 (drvp->drive_flags & DRIVE_UDMA)) { 2003 /* use Ultra/DMA */ 2004 drvp->drive_flags &= ~DRIVE_DMA; 2005 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 2006 APO_UDMA_EN_MTH(chp->channel, drive) | 2007 APO_UDMA_TIME(chp->channel, drive, 2008 apollo_udma_tim[drvp->UDMA_mode]); 2009 /* can use PIO timings, MW DMA unused */ 2010 mode = drvp->PIO_mode; 2011 } else { 2012 /* use Multiword DMA */ 2013 drvp->drive_flags &= ~DRIVE_UDMA; 2014 /* mode = min(pio, dma+2) */ 2015 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 2016 mode = drvp->PIO_mode; 2017 else 2018 mode = drvp->DMA_mode + 2; 2019 } 2020 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2021 2022 pio: /* setup PIO mode */ 2023 if (mode <= 2) { 2024 drvp->DMA_mode = 0; 2025 drvp->PIO_mode = 0; 2026 mode = 0; 2027 } else { 2028 drvp->PIO_mode = mode; 2029 drvp->DMA_mode = mode - 2; 2030 } 2031 datatim_reg |= 2032 APO_DATATIM_PULSE(chp->channel, drive, 2033 apollo_pio_set[mode]) | 2034 APO_DATATIM_RECOV(chp->channel, drive, 2035 apollo_pio_rec[mode]); 2036 } 2037 if (idedma_ctl != 0) { 2038 /* Add software bits in status register */ 2039 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2040 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2041 idedma_ctl); 2042 } 2043 pciide_print_modes(cp); 2044 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2045 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2046 } 2047 2048 void 2049 cmd_channel_map(pa, sc, channel) 2050 struct pci_attach_args *pa; 2051 struct pciide_softc *sc; 2052 int channel; 2053 { 2054 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2055 bus_size_t cmdsize, ctlsize; 2056 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2057 int interface; 2058 2059 /* 2060 * The 0648/0649 can be told to identify as a RAID controller. 2061 * In this case, we have to fake interface 2062 */ 2063 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2064 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2065 PCIIDE_INTERFACE_SETTABLE(1); 2066 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2067 CMD_CONF_DSA1) 2068 interface |= PCIIDE_INTERFACE_PCI(0) | 2069 PCIIDE_INTERFACE_PCI(1); 2070 } else { 2071 interface = PCI_INTERFACE(pa->pa_class); 2072 } 2073 2074 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2075 cp->name = PCIIDE_CHANNEL_NAME(channel); 2076 cp->wdc_channel.channel = channel; 2077 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2078 2079 if (channel > 0) { 2080 cp->wdc_channel.ch_queue = 2081 sc->pciide_channels[0].wdc_channel.ch_queue; 2082 } else { 2083 cp->wdc_channel.ch_queue = 2084 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2085 } 2086 if (cp->wdc_channel.ch_queue == NULL) { 2087 printf("%s %s channel: " 2088 "can't allocate memory for command queue", 2089 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2090 return; 2091 } 2092 2093 printf("%s: %s channel %s to %s mode\n", 2094 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2095 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2096 "configured" : "wired", 2097 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2098 "native-PCI" : "compatibility"); 2099 2100 /* 2101 * with a CMD PCI64x, if we get here, the first channel is enabled: 2102 * there's no way to disable the first channel without disabling 2103 * the whole device 2104 */ 2105 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2106 printf("%s: %s channel ignored (disabled)\n", 2107 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2108 return; 2109 } 2110 2111 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2112 if (cp->hw_ok == 0) 2113 return; 2114 if (channel == 1) { 2115 if (pciide_chan_candisable(cp)) { 2116 ctrl &= ~CMD_CTRL_2PORT; 2117 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2118 CMD_CTRL, ctrl); 2119 } 2120 } 2121 pciide_map_compat_intr(pa, cp, channel, interface); 2122 } 2123 2124 int 2125 cmd_pci_intr(arg) 2126 void *arg; 2127 { 2128 struct pciide_softc *sc = arg; 2129 struct pciide_channel *cp; 2130 struct channel_softc *wdc_cp; 2131 int i, rv, crv; 2132 u_int32_t priirq, secirq; 2133 2134 rv = 0; 2135 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2136 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2137 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2138 cp = &sc->pciide_channels[i]; 2139 wdc_cp = &cp->wdc_channel; 2140 /* If a compat channel skip. */ 2141 if (cp->compat) 2142 continue; 2143 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2144 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2145 crv = wdcintr(wdc_cp); 2146 if (crv == 0) 2147 printf("%s:%d: bogus intr\n", 2148 sc->sc_wdcdev.sc_dev.dv_xname, i); 2149 else 2150 rv = 1; 2151 } 2152 } 2153 return rv; 2154 } 2155 2156 void 2157 cmd_chip_map(sc, pa) 2158 struct pciide_softc *sc; 2159 struct pci_attach_args *pa; 2160 { 2161 int channel; 2162 2163 /* 2164 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2165 * and base adresses registers can be disabled at 2166 * hardware level. In this case, the device is wired 2167 * in compat mode and its first channel is always enabled, 2168 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2169 * In fact, it seems that the first channel of the CMD PCI0640 2170 * can't be disabled. 2171 */ 2172 2173 #ifdef PCIIDE_CMD064x_DISABLE 2174 if (pciide_chipen(sc, pa) == 0) 2175 return; 2176 #endif 2177 2178 printf("%s: hardware does not support DMA\n", 2179 sc->sc_wdcdev.sc_dev.dv_xname); 2180 sc->sc_dma_ok = 0; 2181 2182 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2183 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2184 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2185 2186 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2187 cmd_channel_map(pa, sc, channel); 2188 } 2189 } 2190 2191 void 2192 cmd0643_9_chip_map(sc, pa) 2193 struct pciide_softc *sc; 2194 struct pci_attach_args *pa; 2195 { 2196 struct pciide_channel *cp; 2197 int channel; 2198 int rev = PCI_REVISION( 2199 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2200 2201 /* 2202 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2203 * and base adresses registers can be disabled at 2204 * hardware level. In this case, the device is wired 2205 * in compat mode and its first channel is always enabled, 2206 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2207 * In fact, it seems that the first channel of the CMD PCI0640 2208 * can't be disabled. 2209 */ 2210 2211 #ifdef PCIIDE_CMD064x_DISABLE 2212 if (pciide_chipen(sc, pa) == 0) 2213 return; 2214 #endif 2215 printf("%s: bus-master DMA support present", 2216 sc->sc_wdcdev.sc_dev.dv_xname); 2217 pciide_mapreg_dma(sc, pa); 2218 printf("\n"); 2219 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2220 WDC_CAPABILITY_MODE; 2221 if (sc->sc_dma_ok) { 2222 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2223 switch (sc->sc_pp->ide_product) { 2224 case PCI_PRODUCT_CMDTECH_649: 2225 case PCI_PRODUCT_CMDTECH_648: 2226 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2227 sc->sc_wdcdev.UDMA_cap = 4; 2228 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2229 break; 2230 case PCI_PRODUCT_CMDTECH_646: 2231 if (rev >= CMD0646U2_REV) { 2232 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2233 sc->sc_wdcdev.UDMA_cap = 2; 2234 } else if (rev >= CMD0646U_REV) { 2235 /* 2236 * Linux's driver claims that the 646U is broken 2237 * with UDMA. Only enable it if we know what we're 2238 * doing 2239 */ 2240 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2241 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2242 sc->sc_wdcdev.UDMA_cap = 2; 2243 #endif 2244 /* explicitely disable UDMA */ 2245 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2246 CMD_UDMATIM(0), 0); 2247 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2248 CMD_UDMATIM(1), 0); 2249 } 2250 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2251 break; 2252 default: 2253 sc->sc_wdcdev.irqack = pciide_irqack; 2254 } 2255 } 2256 2257 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2258 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2259 sc->sc_wdcdev.PIO_cap = 4; 2260 sc->sc_wdcdev.DMA_cap = 2; 2261 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2262 2263 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2264 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2265 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2266 DEBUG_PROBE); 2267 2268 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2269 cp = &sc->pciide_channels[channel]; 2270 cmd_channel_map(pa, sc, channel); 2271 if (cp->hw_ok == 0) 2272 continue; 2273 cmd0643_9_setup_channel(&cp->wdc_channel); 2274 } 2275 /* 2276 * note - this also makes sure we clear the irq disable and reset 2277 * bits 2278 */ 2279 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2280 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2281 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2282 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2283 DEBUG_PROBE); 2284 } 2285 2286 void 2287 cmd0643_9_setup_channel(chp) 2288 struct channel_softc *chp; 2289 { 2290 struct ata_drive_datas *drvp; 2291 u_int8_t tim; 2292 u_int32_t idedma_ctl, udma_reg; 2293 int drive; 2294 struct pciide_channel *cp = (struct pciide_channel*)chp; 2295 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2296 2297 idedma_ctl = 0; 2298 /* setup DMA if needed */ 2299 pciide_channel_dma_setup(cp); 2300 2301 for (drive = 0; drive < 2; drive++) { 2302 drvp = &chp->ch_drive[drive]; 2303 /* If no drive, skip */ 2304 if ((drvp->drive_flags & DRIVE) == 0) 2305 continue; 2306 /* add timing values, setup DMA if needed */ 2307 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2308 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2309 if (drvp->drive_flags & DRIVE_UDMA) { 2310 /* UltraDMA on a 646U2, 0648 or 0649 */ 2311 udma_reg = pciide_pci_read(sc->sc_pc, 2312 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2313 if (drvp->UDMA_mode > 2 && 2314 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2315 CMD_BICSR) & 2316 CMD_BICSR_80(chp->channel)) == 0) 2317 drvp->UDMA_mode = 2; 2318 if (drvp->UDMA_mode > 2) 2319 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2320 else if (sc->sc_wdcdev.UDMA_cap > 2) 2321 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2322 udma_reg |= CMD_UDMATIM_UDMA(drive); 2323 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2324 CMD_UDMATIM_TIM_OFF(drive)); 2325 udma_reg |= 2326 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2327 CMD_UDMATIM_TIM_OFF(drive)); 2328 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2329 CMD_UDMATIM(chp->channel), udma_reg); 2330 } else { 2331 /* 2332 * use Multiword DMA. 2333 * Timings will be used for both PIO and DMA, 2334 * so adjust DMA mode if needed 2335 * if we have a 0646U2/8/9, turn off UDMA 2336 */ 2337 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2338 udma_reg = pciide_pci_read(sc->sc_pc, 2339 sc->sc_tag, 2340 CMD_UDMATIM(chp->channel)); 2341 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2342 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2343 CMD_UDMATIM(chp->channel), 2344 udma_reg); 2345 } 2346 if (drvp->PIO_mode >= 3 && 2347 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2348 drvp->DMA_mode = drvp->PIO_mode - 2; 2349 } 2350 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2351 } 2352 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2353 } 2354 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2355 CMD_DATA_TIM(chp->channel, drive), tim); 2356 } 2357 if (idedma_ctl != 0) { 2358 /* Add software bits in status register */ 2359 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2360 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2361 idedma_ctl); 2362 } 2363 pciide_print_modes(cp); 2364 } 2365 2366 void 2367 cmd646_9_irqack(chp) 2368 struct channel_softc *chp; 2369 { 2370 u_int32_t priirq, secirq; 2371 struct pciide_channel *cp = (struct pciide_channel*)chp; 2372 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2373 2374 if (chp->channel == 0) { 2375 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2376 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2377 } else { 2378 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2379 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2380 } 2381 pciide_irqack(chp); 2382 } 2383 2384 void 2385 cy693_chip_map(sc, pa) 2386 struct pciide_softc *sc; 2387 struct pci_attach_args *pa; 2388 { 2389 struct pciide_channel *cp; 2390 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2391 bus_size_t cmdsize, ctlsize; 2392 2393 if (pciide_chipen(sc, pa) == 0) 2394 return; 2395 /* 2396 * this chip has 2 PCI IDE functions, one for primary and one for 2397 * secondary. So we need to call pciide_mapregs_compat() with 2398 * the real channel 2399 */ 2400 if (pa->pa_function == 1) { 2401 sc->sc_cy_compatchan = 0; 2402 } else if (pa->pa_function == 2) { 2403 sc->sc_cy_compatchan = 1; 2404 } else { 2405 printf("%s: unexpected PCI function %d\n", 2406 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2407 return; 2408 } 2409 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2410 printf("%s: bus-master DMA support present", 2411 sc->sc_wdcdev.sc_dev.dv_xname); 2412 pciide_mapreg_dma(sc, pa); 2413 } else { 2414 printf("%s: hardware does not support DMA", 2415 sc->sc_wdcdev.sc_dev.dv_xname); 2416 sc->sc_dma_ok = 0; 2417 } 2418 printf("\n"); 2419 2420 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2421 if (sc->sc_cy_handle == NULL) { 2422 printf("%s: unable to map hyperCache control registers\n", 2423 sc->sc_wdcdev.sc_dev.dv_xname); 2424 sc->sc_dma_ok = 0; 2425 } 2426 2427 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2428 WDC_CAPABILITY_MODE; 2429 if (sc->sc_dma_ok) { 2430 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2431 sc->sc_wdcdev.irqack = pciide_irqack; 2432 } 2433 sc->sc_wdcdev.PIO_cap = 4; 2434 sc->sc_wdcdev.DMA_cap = 2; 2435 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2436 2437 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2438 sc->sc_wdcdev.nchannels = 1; 2439 2440 /* Only one channel for this chip; if we are here it's enabled */ 2441 cp = &sc->pciide_channels[0]; 2442 sc->wdc_chanarray[0] = &cp->wdc_channel; 2443 cp->name = PCIIDE_CHANNEL_NAME(0); 2444 cp->wdc_channel.channel = 0; 2445 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2446 cp->wdc_channel.ch_queue = 2447 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2448 if (cp->wdc_channel.ch_queue == NULL) { 2449 printf("%s primary channel: " 2450 "can't allocate memory for command queue", 2451 sc->sc_wdcdev.sc_dev.dv_xname); 2452 return; 2453 } 2454 printf("%s: primary channel %s to ", 2455 sc->sc_wdcdev.sc_dev.dv_xname, 2456 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2457 "configured" : "wired"); 2458 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2459 printf("native-PCI"); 2460 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2461 pciide_pci_intr); 2462 } else { 2463 printf("compatibility"); 2464 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2465 &cmdsize, &ctlsize); 2466 } 2467 printf(" mode\n"); 2468 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2469 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2470 wdcattach(&cp->wdc_channel); 2471 if (pciide_chan_candisable(cp)) { 2472 pci_conf_write(sc->sc_pc, sc->sc_tag, 2473 PCI_COMMAND_STATUS_REG, 0); 2474 } 2475 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2476 if (cp->hw_ok == 0) 2477 return; 2478 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2479 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2480 cy693_setup_channel(&cp->wdc_channel); 2481 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2482 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2483 } 2484 2485 void 2486 cy693_setup_channel(chp) 2487 struct channel_softc *chp; 2488 { 2489 struct ata_drive_datas *drvp; 2490 int drive; 2491 u_int32_t cy_cmd_ctrl; 2492 u_int32_t idedma_ctl; 2493 struct pciide_channel *cp = (struct pciide_channel*)chp; 2494 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2495 int dma_mode = -1; 2496 2497 cy_cmd_ctrl = idedma_ctl = 0; 2498 2499 /* setup DMA if needed */ 2500 pciide_channel_dma_setup(cp); 2501 2502 for (drive = 0; drive < 2; drive++) { 2503 drvp = &chp->ch_drive[drive]; 2504 /* If no drive, skip */ 2505 if ((drvp->drive_flags & DRIVE) == 0) 2506 continue; 2507 /* add timing values, setup DMA if needed */ 2508 if (drvp->drive_flags & DRIVE_DMA) { 2509 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2510 /* use Multiword DMA */ 2511 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2512 dma_mode = drvp->DMA_mode; 2513 } 2514 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2515 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2516 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2517 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2518 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2519 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2520 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2521 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2522 } 2523 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2524 chp->ch_drive[0].DMA_mode = dma_mode; 2525 chp->ch_drive[1].DMA_mode = dma_mode; 2526 2527 if (dma_mode == -1) 2528 dma_mode = 0; 2529 2530 if (sc->sc_cy_handle != NULL) { 2531 /* Note: `multiple' is implied. */ 2532 cy82c693_write(sc->sc_cy_handle, 2533 (sc->sc_cy_compatchan == 0) ? 2534 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2535 } 2536 2537 pciide_print_modes(cp); 2538 2539 if (idedma_ctl != 0) { 2540 /* Add software bits in status register */ 2541 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2542 IDEDMA_CTL, idedma_ctl); 2543 } 2544 } 2545 2546 void 2547 sis_chip_map(sc, pa) 2548 struct pciide_softc *sc; 2549 struct pci_attach_args *pa; 2550 { 2551 struct pciide_channel *cp; 2552 int channel; 2553 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2554 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2555 pcireg_t rev = PCI_REVISION(pa->pa_class); 2556 bus_size_t cmdsize, ctlsize; 2557 2558 if (pciide_chipen(sc, pa) == 0) 2559 return; 2560 printf("%s: bus-master DMA support present", 2561 sc->sc_wdcdev.sc_dev.dv_xname); 2562 pciide_mapreg_dma(sc, pa); 2563 printf("\n"); 2564 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2565 WDC_CAPABILITY_MODE; 2566 if (sc->sc_dma_ok) { 2567 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2568 sc->sc_wdcdev.irqack = pciide_irqack; 2569 if (rev >= 0xd0) 2570 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2571 } 2572 2573 sc->sc_wdcdev.PIO_cap = 4; 2574 sc->sc_wdcdev.DMA_cap = 2; 2575 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2576 sc->sc_wdcdev.UDMA_cap = 2; 2577 sc->sc_wdcdev.set_modes = sis_setup_channel; 2578 2579 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2580 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2581 2582 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2583 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2584 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2585 2586 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2587 cp = &sc->pciide_channels[channel]; 2588 if (pciide_chansetup(sc, channel, interface) == 0) 2589 continue; 2590 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2591 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2592 printf("%s: %s channel ignored (disabled)\n", 2593 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2594 continue; 2595 } 2596 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2597 pciide_pci_intr); 2598 if (cp->hw_ok == 0) 2599 continue; 2600 if (pciide_chan_candisable(cp)) { 2601 if (channel == 0) 2602 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2603 else 2604 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2605 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2606 sis_ctr0); 2607 } 2608 pciide_map_compat_intr(pa, cp, channel, interface); 2609 if (cp->hw_ok == 0) 2610 continue; 2611 sis_setup_channel(&cp->wdc_channel); 2612 } 2613 } 2614 2615 void 2616 sis_setup_channel(chp) 2617 struct channel_softc *chp; 2618 { 2619 struct ata_drive_datas *drvp; 2620 int drive; 2621 u_int32_t sis_tim; 2622 u_int32_t idedma_ctl; 2623 struct pciide_channel *cp = (struct pciide_channel*)chp; 2624 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2625 2626 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2627 "channel %d 0x%x\n", chp->channel, 2628 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2629 DEBUG_PROBE); 2630 sis_tim = 0; 2631 idedma_ctl = 0; 2632 /* setup DMA if needed */ 2633 pciide_channel_dma_setup(cp); 2634 2635 for (drive = 0; drive < 2; drive++) { 2636 drvp = &chp->ch_drive[drive]; 2637 /* If no drive, skip */ 2638 if ((drvp->drive_flags & DRIVE) == 0) 2639 continue; 2640 /* add timing values, setup DMA if needed */ 2641 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2642 (drvp->drive_flags & DRIVE_UDMA) == 0) 2643 goto pio; 2644 2645 if (drvp->drive_flags & DRIVE_UDMA) { 2646 /* use Ultra/DMA */ 2647 drvp->drive_flags &= ~DRIVE_DMA; 2648 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2649 SIS_TIM_UDMA_TIME_OFF(drive); 2650 sis_tim |= SIS_TIM_UDMA_EN(drive); 2651 } else { 2652 /* 2653 * use Multiword DMA 2654 * Timings will be used for both PIO and DMA, 2655 * so adjust DMA mode if needed 2656 */ 2657 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2658 drvp->PIO_mode = drvp->DMA_mode + 2; 2659 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2660 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2661 drvp->PIO_mode - 2 : 0; 2662 if (drvp->DMA_mode == 0) 2663 drvp->PIO_mode = 0; 2664 } 2665 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2666 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2667 SIS_TIM_ACT_OFF(drive); 2668 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2669 SIS_TIM_REC_OFF(drive); 2670 } 2671 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2672 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2673 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2674 if (idedma_ctl != 0) { 2675 /* Add software bits in status register */ 2676 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2677 IDEDMA_CTL, idedma_ctl); 2678 } 2679 pciide_print_modes(cp); 2680 } 2681 2682 void 2683 acer_chip_map(sc, pa) 2684 struct pciide_softc *sc; 2685 struct pci_attach_args *pa; 2686 { 2687 struct pciide_channel *cp; 2688 int channel; 2689 pcireg_t cr, interface; 2690 bus_size_t cmdsize, ctlsize; 2691 2692 if (pciide_chipen(sc, pa) == 0) 2693 return; 2694 printf("%s: bus-master DMA support present", 2695 sc->sc_wdcdev.sc_dev.dv_xname); 2696 pciide_mapreg_dma(sc, pa); 2697 printf("\n"); 2698 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2699 WDC_CAPABILITY_MODE; 2700 if (sc->sc_dma_ok) { 2701 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2702 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2703 sc->sc_wdcdev.irqack = pciide_irqack; 2704 } 2705 2706 sc->sc_wdcdev.PIO_cap = 4; 2707 sc->sc_wdcdev.DMA_cap = 2; 2708 sc->sc_wdcdev.UDMA_cap = 2; 2709 sc->sc_wdcdev.set_modes = acer_setup_channel; 2710 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2711 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2712 2713 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2714 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2715 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2716 2717 /* Enable "microsoft register bits" R/W. */ 2718 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2719 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2720 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2721 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2722 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2723 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2724 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2725 ~ACER_CHANSTATUSREGS_RO); 2726 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2727 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2728 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2729 /* Don't use cr, re-read the real register content instead */ 2730 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2731 PCI_CLASS_REG)); 2732 2733 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2734 cp = &sc->pciide_channels[channel]; 2735 if (pciide_chansetup(sc, channel, interface) == 0) 2736 continue; 2737 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2738 printf("%s: %s channel ignored (disabled)\n", 2739 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2740 continue; 2741 } 2742 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2743 acer_pci_intr); 2744 if (cp->hw_ok == 0) 2745 continue; 2746 if (pciide_chan_candisable(cp)) { 2747 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2748 pci_conf_write(sc->sc_pc, sc->sc_tag, 2749 PCI_CLASS_REG, cr); 2750 } 2751 pciide_map_compat_intr(pa, cp, channel, interface); 2752 acer_setup_channel(&cp->wdc_channel); 2753 } 2754 } 2755 2756 void 2757 acer_setup_channel(chp) 2758 struct channel_softc *chp; 2759 { 2760 struct ata_drive_datas *drvp; 2761 int drive; 2762 u_int32_t acer_fifo_udma; 2763 u_int32_t idedma_ctl; 2764 struct pciide_channel *cp = (struct pciide_channel*)chp; 2765 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2766 2767 idedma_ctl = 0; 2768 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2769 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2770 acer_fifo_udma), DEBUG_PROBE); 2771 /* setup DMA if needed */ 2772 pciide_channel_dma_setup(cp); 2773 2774 for (drive = 0; drive < 2; drive++) { 2775 drvp = &chp->ch_drive[drive]; 2776 /* If no drive, skip */ 2777 if ((drvp->drive_flags & DRIVE) == 0) 2778 continue; 2779 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2780 "channel %d drive %d 0x%x\n", chp->channel, drive, 2781 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2782 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2783 /* clear FIFO/DMA mode */ 2784 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2785 ACER_UDMA_EN(chp->channel, drive) | 2786 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2787 2788 /* add timing values, setup DMA if needed */ 2789 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2790 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2791 acer_fifo_udma |= 2792 ACER_FTH_OPL(chp->channel, drive, 0x1); 2793 goto pio; 2794 } 2795 2796 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2797 if (drvp->drive_flags & DRIVE_UDMA) { 2798 /* use Ultra/DMA */ 2799 drvp->drive_flags &= ~DRIVE_DMA; 2800 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2801 acer_fifo_udma |= 2802 ACER_UDMA_TIM(chp->channel, drive, 2803 acer_udma[drvp->UDMA_mode]); 2804 } else { 2805 /* 2806 * use Multiword DMA 2807 * Timings will be used for both PIO and DMA, 2808 * so adjust DMA mode if needed 2809 */ 2810 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2811 drvp->PIO_mode = drvp->DMA_mode + 2; 2812 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2813 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2814 drvp->PIO_mode - 2 : 0; 2815 if (drvp->DMA_mode == 0) 2816 drvp->PIO_mode = 0; 2817 } 2818 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2819 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2820 ACER_IDETIM(chp->channel, drive), 2821 acer_pio[drvp->PIO_mode]); 2822 } 2823 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2824 acer_fifo_udma), DEBUG_PROBE); 2825 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2826 if (idedma_ctl != 0) { 2827 /* Add software bits in status register */ 2828 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2829 IDEDMA_CTL, idedma_ctl); 2830 } 2831 pciide_print_modes(cp); 2832 } 2833 2834 int 2835 acer_pci_intr(arg) 2836 void *arg; 2837 { 2838 struct pciide_softc *sc = arg; 2839 struct pciide_channel *cp; 2840 struct channel_softc *wdc_cp; 2841 int i, rv, crv; 2842 u_int32_t chids; 2843 2844 rv = 0; 2845 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2846 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2847 cp = &sc->pciide_channels[i]; 2848 wdc_cp = &cp->wdc_channel; 2849 /* If a compat channel skip. */ 2850 if (cp->compat) 2851 continue; 2852 if (chids & ACER_CHIDS_INT(i)) { 2853 crv = wdcintr(wdc_cp); 2854 if (crv == 0) 2855 printf("%s:%d: bogus intr\n", 2856 sc->sc_wdcdev.sc_dev.dv_xname, i); 2857 else 2858 rv = 1; 2859 } 2860 } 2861 return rv; 2862 } 2863 2864 void 2865 hpt_chip_map(sc, pa) 2866 struct pciide_softc *sc; 2867 struct pci_attach_args *pa; 2868 { 2869 struct pciide_channel *cp; 2870 int i, compatchan, revision; 2871 pcireg_t interface; 2872 bus_size_t cmdsize, ctlsize; 2873 2874 if (pciide_chipen(sc, pa) == 0) 2875 return; 2876 revision = PCI_REVISION(pa->pa_class); 2877 2878 /* 2879 * when the chip is in native mode it identifies itself as a 2880 * 'misc mass storage'. Fake interface in this case. 2881 */ 2882 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2883 interface = PCI_INTERFACE(pa->pa_class); 2884 } else { 2885 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2886 PCIIDE_INTERFACE_PCI(0); 2887 if (revision == HPT370_REV) 2888 interface |= PCIIDE_INTERFACE_PCI(1); 2889 } 2890 2891 printf("%s: bus-master DMA support present", 2892 sc->sc_wdcdev.sc_dev.dv_xname); 2893 pciide_mapreg_dma(sc, pa); 2894 printf("\n"); 2895 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2896 WDC_CAPABILITY_MODE; 2897 if (sc->sc_dma_ok) { 2898 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2899 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2900 sc->sc_wdcdev.irqack = pciide_irqack; 2901 } 2902 sc->sc_wdcdev.PIO_cap = 4; 2903 sc->sc_wdcdev.DMA_cap = 2; 2904 sc->sc_wdcdev.UDMA_cap = 4; 2905 2906 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2907 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2908 if (revision == HPT366_REV) { 2909 /* 2910 * The 366 has 2 PCI IDE functions, one for primary and one 2911 * for secondary. So we need to call pciide_mapregs_compat() 2912 * with the real channel 2913 */ 2914 if (pa->pa_function == 0) { 2915 compatchan = 0; 2916 } else if (pa->pa_function == 1) { 2917 compatchan = 1; 2918 } else { 2919 printf("%s: unexpected PCI function %d\n", 2920 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2921 return; 2922 } 2923 sc->sc_wdcdev.nchannels = 1; 2924 } else { 2925 sc->sc_wdcdev.nchannels = 2; 2926 } 2927 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2928 cp = &sc->pciide_channels[i]; 2929 if (sc->sc_wdcdev.nchannels > 1) { 2930 compatchan = i; 2931 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2932 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2933 printf("%s: %s channel ignored (disabled)\n", 2934 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2935 continue; 2936 } 2937 } 2938 if (pciide_chansetup(sc, i, interface) == 0) 2939 continue; 2940 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2941 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2942 &ctlsize, hpt_pci_intr); 2943 } else { 2944 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2945 &cmdsize, &ctlsize); 2946 } 2947 if (cp->hw_ok == 0) 2948 return; 2949 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2950 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2951 wdcattach(&cp->wdc_channel); 2952 hpt_setup_channel(&cp->wdc_channel); 2953 } 2954 if (revision == HPT370_REV) { 2955 /* 2956 * HPT370_REV has a bit to disable interrupts, make sure 2957 * to clear it 2958 */ 2959 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 2960 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 2961 ~HPT_CSEL_IRQDIS); 2962 } 2963 return; 2964 } 2965 2966 2967 void 2968 hpt_setup_channel(chp) 2969 struct channel_softc *chp; 2970 { 2971 struct ata_drive_datas *drvp; 2972 int drive; 2973 int cable; 2974 u_int32_t before, after; 2975 u_int32_t idedma_ctl; 2976 struct pciide_channel *cp = (struct pciide_channel*)chp; 2977 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2978 2979 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 2980 2981 /* setup DMA if needed */ 2982 pciide_channel_dma_setup(cp); 2983 2984 idedma_ctl = 0; 2985 2986 /* Per drive settings */ 2987 for (drive = 0; drive < 2; drive++) { 2988 drvp = &chp->ch_drive[drive]; 2989 /* If no drive, skip */ 2990 if ((drvp->drive_flags & DRIVE) == 0) 2991 continue; 2992 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 2993 HPT_IDETIM(chp->channel, drive)); 2994 2995 /* add timing values, setup DMA if needed */ 2996 if (drvp->drive_flags & DRIVE_UDMA) { 2997 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 2998 drvp->UDMA_mode > 2) 2999 drvp->UDMA_mode = 2; 3000 after = (sc->sc_wdcdev.nchannels == 2) ? 3001 hpt370_udma[drvp->UDMA_mode] : 3002 hpt366_udma[drvp->UDMA_mode]; 3003 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3004 } else if (drvp->drive_flags & DRIVE_DMA) { 3005 /* 3006 * use Multiword DMA. 3007 * Timings will be used for both PIO and DMA, so adjust 3008 * DMA mode if needed 3009 */ 3010 if (drvp->PIO_mode >= 3 && 3011 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 3012 drvp->DMA_mode = drvp->PIO_mode - 2; 3013 } 3014 after = (sc->sc_wdcdev.nchannels == 2) ? 3015 hpt370_dma[drvp->DMA_mode] : 3016 hpt366_dma[drvp->DMA_mode]; 3017 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3018 } else { 3019 /* PIO only */ 3020 after = (sc->sc_wdcdev.nchannels == 2) ? 3021 hpt370_pio[drvp->PIO_mode] : 3022 hpt366_pio[drvp->PIO_mode]; 3023 } 3024 pci_conf_write(sc->sc_pc, sc->sc_tag, 3025 HPT_IDETIM(chp->channel, drive), after); 3026 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3027 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3028 after, before), DEBUG_PROBE); 3029 } 3030 if (idedma_ctl != 0) { 3031 /* Add software bits in status register */ 3032 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3033 IDEDMA_CTL, idedma_ctl); 3034 } 3035 pciide_print_modes(cp); 3036 } 3037 3038 int 3039 hpt_pci_intr(arg) 3040 void *arg; 3041 { 3042 struct pciide_softc *sc = arg; 3043 struct pciide_channel *cp; 3044 struct channel_softc *wdc_cp; 3045 int rv = 0; 3046 int dmastat, i, crv; 3047 3048 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3049 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3050 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3051 if((dmastat & IDEDMA_CTL_INTR) == 0) 3052 continue; 3053 cp = &sc->pciide_channels[i]; 3054 wdc_cp = &cp->wdc_channel; 3055 crv = wdcintr(wdc_cp); 3056 if (crv == 0) { 3057 printf("%s:%d: bogus intr\n", 3058 sc->sc_wdcdev.sc_dev.dv_xname, i); 3059 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3060 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3061 } else 3062 rv = 1; 3063 } 3064 return rv; 3065 } 3066 3067 3068 /* A macro to test product */ 3069 #define PDC_IS_262(sc) \ 3070 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3071 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3072 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3073 3074 void 3075 pdc202xx_chip_map(sc, pa) 3076 struct pciide_softc *sc; 3077 struct pci_attach_args *pa; 3078 { 3079 struct pciide_channel *cp; 3080 int channel; 3081 pcireg_t interface, st, mode; 3082 bus_size_t cmdsize, ctlsize; 3083 3084 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3085 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3086 DEBUG_PROBE); 3087 if (pciide_chipen(sc, pa) == 0) 3088 return; 3089 3090 /* turn off RAID mode */ 3091 st &= ~PDC2xx_STATE_IDERAID; 3092 3093 /* 3094 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3095 * mode. We have to fake interface 3096 */ 3097 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3098 if (st & PDC2xx_STATE_NATIVE) 3099 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3100 3101 printf("%s: bus-master DMA support present", 3102 sc->sc_wdcdev.sc_dev.dv_xname); 3103 pciide_mapreg_dma(sc, pa); 3104 printf("\n"); 3105 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3106 WDC_CAPABILITY_MODE; 3107 if (sc->sc_dma_ok) { 3108 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3109 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3110 sc->sc_wdcdev.irqack = pciide_irqack; 3111 } 3112 sc->sc_wdcdev.PIO_cap = 4; 3113 sc->sc_wdcdev.DMA_cap = 2; 3114 if (PDC_IS_262(sc)) 3115 sc->sc_wdcdev.UDMA_cap = 4; 3116 else 3117 sc->sc_wdcdev.UDMA_cap = 2; 3118 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3119 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3120 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3121 3122 /* setup failsafe defaults */ 3123 mode = 0; 3124 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3125 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3126 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3127 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3128 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3129 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3130 "initial timings 0x%x, now 0x%x\n", channel, 3131 pci_conf_read(sc->sc_pc, sc->sc_tag, 3132 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3133 DEBUG_PROBE); 3134 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3135 mode | PDC2xx_TIM_IORDYp); 3136 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3137 "initial timings 0x%x, now 0x%x\n", channel, 3138 pci_conf_read(sc->sc_pc, sc->sc_tag, 3139 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3140 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3141 mode); 3142 } 3143 3144 mode = PDC2xx_SCR_DMA; 3145 if (PDC_IS_262(sc)) { 3146 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3147 } else { 3148 /* the BIOS set it up this way */ 3149 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3150 } 3151 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3152 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3153 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3154 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3155 DEBUG_PROBE); 3156 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3157 3158 /* controller initial state register is OK even without BIOS */ 3159 /* Set DMA mode to IDE DMA compatibility */ 3160 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3161 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3162 DEBUG_PROBE); 3163 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3164 mode | 0x1); 3165 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3166 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3167 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3168 mode | 0x1); 3169 3170 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3171 cp = &sc->pciide_channels[channel]; 3172 if (pciide_chansetup(sc, channel, interface) == 0) 3173 continue; 3174 if ((st & (PDC_IS_262(sc) ? 3175 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3176 printf("%s: %s channel ignored (disabled)\n", 3177 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3178 continue; 3179 } 3180 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3181 pdc202xx_pci_intr); 3182 if (cp->hw_ok == 0) 3183 continue; 3184 if (pciide_chan_candisable(cp)) 3185 st &= ~(PDC_IS_262(sc) ? 3186 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3187 pciide_map_compat_intr(pa, cp, channel, interface); 3188 pdc202xx_setup_channel(&cp->wdc_channel); 3189 } 3190 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3191 DEBUG_PROBE); 3192 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3193 return; 3194 } 3195 3196 void 3197 pdc202xx_setup_channel(chp) 3198 struct channel_softc *chp; 3199 { 3200 struct ata_drive_datas *drvp; 3201 int drive; 3202 pcireg_t mode, st; 3203 u_int32_t idedma_ctl, scr, atapi; 3204 struct pciide_channel *cp = (struct pciide_channel*)chp; 3205 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3206 int channel = chp->channel; 3207 3208 /* setup DMA if needed */ 3209 pciide_channel_dma_setup(cp); 3210 3211 idedma_ctl = 0; 3212 3213 /* Per channel settings */ 3214 if (PDC_IS_262(sc)) { 3215 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3216 PDC262_U66); 3217 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3218 /* Trimm UDMA mode */ 3219 if ((st & PDC262_STATE_80P(channel)) != 0 || 3220 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3221 chp->ch_drive[0].UDMA_mode <= 2) || 3222 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3223 chp->ch_drive[1].UDMA_mode <= 2)) { 3224 if (chp->ch_drive[0].UDMA_mode > 2) 3225 chp->ch_drive[0].UDMA_mode = 2; 3226 if (chp->ch_drive[1].UDMA_mode > 2) 3227 chp->ch_drive[1].UDMA_mode = 2; 3228 } 3229 /* Set U66 if needed */ 3230 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3231 chp->ch_drive[0].UDMA_mode > 2) || 3232 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3233 chp->ch_drive[1].UDMA_mode > 2)) 3234 scr |= PDC262_U66_EN(channel); 3235 else 3236 scr &= ~PDC262_U66_EN(channel); 3237 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3238 PDC262_U66, scr); 3239 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3240 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3241 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3242 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3243 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3244 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3245 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3246 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3247 atapi = 0; 3248 else 3249 atapi = PDC262_ATAPI_UDMA; 3250 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3251 PDC262_ATAPI(channel), atapi); 3252 } 3253 } 3254 for (drive = 0; drive < 2; drive++) { 3255 drvp = &chp->ch_drive[drive]; 3256 /* If no drive, skip */ 3257 if ((drvp->drive_flags & DRIVE) == 0) 3258 continue; 3259 mode = 0; 3260 if (drvp->drive_flags & DRIVE_UDMA) { 3261 mode = PDC2xx_TIM_SET_MB(mode, 3262 pdc2xx_udma_mb[drvp->UDMA_mode]); 3263 mode = PDC2xx_TIM_SET_MC(mode, 3264 pdc2xx_udma_mc[drvp->UDMA_mode]); 3265 drvp->drive_flags &= ~DRIVE_DMA; 3266 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3267 } else if (drvp->drive_flags & DRIVE_DMA) { 3268 mode = PDC2xx_TIM_SET_MB(mode, 3269 pdc2xx_dma_mb[drvp->DMA_mode]); 3270 mode = PDC2xx_TIM_SET_MC(mode, 3271 pdc2xx_dma_mc[drvp->DMA_mode]); 3272 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3273 } else { 3274 mode = PDC2xx_TIM_SET_MB(mode, 3275 pdc2xx_dma_mb[0]); 3276 mode = PDC2xx_TIM_SET_MC(mode, 3277 pdc2xx_dma_mc[0]); 3278 } 3279 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3280 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3281 if (drvp->drive_flags & DRIVE_ATA) 3282 mode |= PDC2xx_TIM_PRE; 3283 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3284 if (drvp->PIO_mode >= 3) { 3285 mode |= PDC2xx_TIM_IORDY; 3286 if (drive == 0) 3287 mode |= PDC2xx_TIM_IORDYp; 3288 } 3289 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3290 "timings 0x%x\n", 3291 sc->sc_wdcdev.sc_dev.dv_xname, 3292 chp->channel, drive, mode), DEBUG_PROBE); 3293 pci_conf_write(sc->sc_pc, sc->sc_tag, 3294 PDC2xx_TIM(chp->channel, drive), mode); 3295 } 3296 if (idedma_ctl != 0) { 3297 /* Add software bits in status register */ 3298 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3299 IDEDMA_CTL, idedma_ctl); 3300 } 3301 pciide_print_modes(cp); 3302 } 3303 3304 int 3305 pdc202xx_pci_intr(arg) 3306 void *arg; 3307 { 3308 struct pciide_softc *sc = arg; 3309 struct pciide_channel *cp; 3310 struct channel_softc *wdc_cp; 3311 int i, rv, crv; 3312 u_int32_t scr; 3313 3314 rv = 0; 3315 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3316 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3317 cp = &sc->pciide_channels[i]; 3318 wdc_cp = &cp->wdc_channel; 3319 /* If a compat channel skip. */ 3320 if (cp->compat) 3321 continue; 3322 if (scr & PDC2xx_SCR_INT(i)) { 3323 crv = wdcintr(wdc_cp); 3324 if (crv == 0) 3325 printf("%s:%d: bogus intr\n", 3326 sc->sc_wdcdev.sc_dev.dv_xname, i); 3327 else 3328 rv = 1; 3329 } 3330 } 3331 return rv; 3332 } 3333 3334 void 3335 opti_chip_map(sc, pa) 3336 struct pciide_softc *sc; 3337 struct pci_attach_args *pa; 3338 { 3339 struct pciide_channel *cp; 3340 bus_size_t cmdsize, ctlsize; 3341 pcireg_t interface; 3342 u_int8_t init_ctrl; 3343 int channel; 3344 3345 if (pciide_chipen(sc, pa) == 0) 3346 return; 3347 printf("%s: bus-master DMA support present", 3348 sc->sc_wdcdev.sc_dev.dv_xname); 3349 pciide_mapreg_dma(sc, pa); 3350 printf("\n"); 3351 3352 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3353 WDC_CAPABILITY_MODE; 3354 sc->sc_wdcdev.PIO_cap = 4; 3355 if (sc->sc_dma_ok) { 3356 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3357 sc->sc_wdcdev.irqack = pciide_irqack; 3358 sc->sc_wdcdev.DMA_cap = 2; 3359 } 3360 sc->sc_wdcdev.set_modes = opti_setup_channel; 3361 3362 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3363 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3364 3365 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3366 OPTI_REG_INIT_CONTROL); 3367 3368 interface = PCI_INTERFACE(pa->pa_class); 3369 3370 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3371 cp = &sc->pciide_channels[channel]; 3372 if (pciide_chansetup(sc, channel, interface) == 0) 3373 continue; 3374 if (channel == 1 && 3375 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3376 printf("%s: %s channel ignored (disabled)\n", 3377 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3378 continue; 3379 } 3380 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3381 pciide_pci_intr); 3382 if (cp->hw_ok == 0) 3383 continue; 3384 pciide_map_compat_intr(pa, cp, channel, interface); 3385 if (cp->hw_ok == 0) 3386 continue; 3387 opti_setup_channel(&cp->wdc_channel); 3388 } 3389 } 3390 3391 void 3392 opti_setup_channel(chp) 3393 struct channel_softc *chp; 3394 { 3395 struct ata_drive_datas *drvp; 3396 struct pciide_channel *cp = (struct pciide_channel*)chp; 3397 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3398 int drive, spd; 3399 int mode[2]; 3400 u_int8_t rv, mr; 3401 3402 /* 3403 * The `Delay' and `Address Setup Time' fields of the 3404 * Miscellaneous Register are always zero initially. 3405 */ 3406 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3407 mr &= ~(OPTI_MISC_DELAY_MASK | 3408 OPTI_MISC_ADDR_SETUP_MASK | 3409 OPTI_MISC_INDEX_MASK); 3410 3411 /* Prime the control register before setting timing values */ 3412 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3413 3414 /* Determine the clockrate of the PCIbus the chip is attached to */ 3415 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3416 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3417 3418 /* setup DMA if needed */ 3419 pciide_channel_dma_setup(cp); 3420 3421 for (drive = 0; drive < 2; drive++) { 3422 drvp = &chp->ch_drive[drive]; 3423 /* If no drive, skip */ 3424 if ((drvp->drive_flags & DRIVE) == 0) { 3425 mode[drive] = -1; 3426 continue; 3427 } 3428 3429 if ((drvp->drive_flags & DRIVE_DMA)) { 3430 /* 3431 * Timings will be used for both PIO and DMA, 3432 * so adjust DMA mode if needed 3433 */ 3434 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3435 drvp->PIO_mode = drvp->DMA_mode + 2; 3436 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3437 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3438 drvp->PIO_mode - 2 : 0; 3439 if (drvp->DMA_mode == 0) 3440 drvp->PIO_mode = 0; 3441 3442 mode[drive] = drvp->DMA_mode + 5; 3443 } else 3444 mode[drive] = drvp->PIO_mode; 3445 3446 if (drive && mode[0] >= 0 && 3447 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3448 /* 3449 * Can't have two drives using different values 3450 * for `Address Setup Time'. 3451 * Slow down the faster drive to compensate. 3452 */ 3453 int d = (opti_tim_as[spd][mode[0]] > 3454 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3455 3456 mode[d] = mode[1-d]; 3457 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3458 chp->ch_drive[d].DMA_mode = 0; 3459 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3460 } 3461 } 3462 3463 for (drive = 0; drive < 2; drive++) { 3464 int m; 3465 if ((m = mode[drive]) < 0) 3466 continue; 3467 3468 /* Set the Address Setup Time and select appropriate index */ 3469 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3470 rv |= OPTI_MISC_INDEX(drive); 3471 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3472 3473 /* Set the pulse width and recovery timing parameters */ 3474 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3475 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3476 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3477 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3478 3479 /* Set the Enhanced Mode register appropriately */ 3480 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3481 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3482 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3483 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3484 } 3485 3486 /* Finally, enable the timings */ 3487 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3488 3489 pciide_print_modes(cp); 3490 } 3491
Indexes created Tue Sep 23 07:09:52 GMT 2025