pciide.c revision 1.90
1 /* $NetBSD: pciide.c,v 1.90 2000/11/08 17:57:37 wrstuden Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <machine/endian.h> 100 101 #include <dev/pci/pcireg.h> 102 #include <dev/pci/pcivar.h> 103 #include <dev/pci/pcidevs.h> 104 #include <dev/pci/pciidereg.h> 105 #include <dev/pci/pciidevar.h> 106 #include <dev/pci/pciide_piix_reg.h> 107 #include <dev/pci/pciide_amd_reg.h> 108 #include <dev/pci/pciide_apollo_reg.h> 109 #include <dev/pci/pciide_cmd_reg.h> 110 #include <dev/pci/pciide_cy693_reg.h> 111 #include <dev/pci/pciide_sis_reg.h> 112 #include <dev/pci/pciide_acer_reg.h> 113 #include <dev/pci/pciide_pdc202xx_reg.h> 114 #include <dev/pci/pciide_opti_reg.h> 115 #include <dev/pci/pciide_hpt_reg.h> 116 #include <dev/pci/cy82c693var.h> 117 118 #include "opt_pciide.h" 119 120 /* inlines for reading/writing 8-bit PCI registers */ 121 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 122 int)); 123 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 124 int, u_int8_t)); 125 126 static __inline u_int8_t 127 pciide_pci_read(pc, pa, reg) 128 pci_chipset_tag_t pc; 129 pcitag_t pa; 130 int reg; 131 { 132 133 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 134 ((reg & 0x03) * 8) & 0xff); 135 } 136 137 static __inline void 138 pciide_pci_write(pc, pa, reg, val) 139 pci_chipset_tag_t pc; 140 pcitag_t pa; 141 int reg; 142 u_int8_t val; 143 { 144 pcireg_t pcival; 145 146 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 147 pcival &= ~(0xff << ((reg & 0x03) * 8)); 148 pcival |= (val << ((reg & 0x03) * 8)); 149 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 150 } 151 152 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 153 154 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 155 void piix_setup_channel __P((struct channel_softc*)); 156 void piix3_4_setup_channel __P((struct channel_softc*)); 157 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 158 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 159 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 160 161 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 162 void amd756_setup_channel __P((struct channel_softc*)); 163 164 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 165 void apollo_setup_channel __P((struct channel_softc*)); 166 167 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 168 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 169 void cmd0643_9_setup_channel __P((struct channel_softc*)); 170 void cmd_channel_map __P((struct pci_attach_args *, 171 struct pciide_softc *, int)); 172 int cmd_pci_intr __P((void *)); 173 void cmd646_9_irqack __P((struct channel_softc *)); 174 175 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 176 void cy693_setup_channel __P((struct channel_softc*)); 177 178 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 179 void sis_setup_channel __P((struct channel_softc*)); 180 181 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 182 void acer_setup_channel __P((struct channel_softc*)); 183 int acer_pci_intr __P((void *)); 184 185 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 186 void pdc202xx_setup_channel __P((struct channel_softc*)); 187 int pdc202xx_pci_intr __P((void *)); 188 189 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 190 void opti_setup_channel __P((struct channel_softc*)); 191 192 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 193 void hpt_setup_channel __P((struct channel_softc*)); 194 int hpt_pci_intr __P((void *)); 195 196 void pciide_channel_dma_setup __P((struct pciide_channel *)); 197 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 198 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 199 void pciide_dma_start __P((void*, int, int)); 200 int pciide_dma_finish __P((void*, int, int, int)); 201 void pciide_irqack __P((struct channel_softc *)); 202 void pciide_print_modes __P((struct pciide_channel *)); 203 204 struct pciide_product_desc { 205 u_int32_t ide_product; 206 int ide_flags; 207 const char *ide_name; 208 /* map and setup chip, probe drives */ 209 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 210 }; 211 212 /* Flags for ide_flags */ 213 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 214 215 /* Default product description for devices not known from this controller */ 216 const struct pciide_product_desc default_product_desc = { 217 0, 218 0, 219 "Generic PCI IDE controller", 220 default_chip_map, 221 }; 222 223 const struct pciide_product_desc pciide_intel_products[] = { 224 { PCI_PRODUCT_INTEL_82092AA, 225 0, 226 "Intel 82092AA IDE controller", 227 default_chip_map, 228 }, 229 { PCI_PRODUCT_INTEL_82371FB_IDE, 230 0, 231 "Intel 82371FB IDE controller (PIIX)", 232 piix_chip_map, 233 }, 234 { PCI_PRODUCT_INTEL_82371SB_IDE, 235 0, 236 "Intel 82371SB IDE Interface (PIIX3)", 237 piix_chip_map, 238 }, 239 { PCI_PRODUCT_INTEL_82371AB_IDE, 240 0, 241 "Intel 82371AB IDE controller (PIIX4)", 242 piix_chip_map, 243 }, 244 { PCI_PRODUCT_INTEL_82440MX_IDE, 245 0, 246 "Intel 82440MX IDE controller", 247 piix_chip_map 248 }, 249 { PCI_PRODUCT_INTEL_82801AA_IDE, 250 0, 251 "Intel 82801AA IDE Controller (ICH)", 252 piix_chip_map, 253 }, 254 { PCI_PRODUCT_INTEL_82801AB_IDE, 255 0, 256 "Intel 82801AB IDE Controller (ICH0)", 257 piix_chip_map, 258 }, 259 { 0, 260 0, 261 NULL, 262 } 263 }; 264 265 const struct pciide_product_desc pciide_amd_products[] = { 266 { PCI_PRODUCT_AMD_PBC756_IDE, 267 0, 268 "Advanced Micro Devices AMD756 IDE Controller", 269 amd756_chip_map 270 }, 271 { 0, 272 0, 273 NULL, 274 } 275 }; 276 277 const struct pciide_product_desc pciide_cmd_products[] = { 278 { PCI_PRODUCT_CMDTECH_640, 279 0, 280 "CMD Technology PCI0640", 281 cmd_chip_map 282 }, 283 { PCI_PRODUCT_CMDTECH_643, 284 0, 285 "CMD Technology PCI0643", 286 cmd0643_9_chip_map, 287 }, 288 { PCI_PRODUCT_CMDTECH_646, 289 0, 290 "CMD Technology PCI0646", 291 cmd0643_9_chip_map, 292 }, 293 { PCI_PRODUCT_CMDTECH_648, 294 IDE_PCI_CLASS_OVERRIDE, 295 "CMD Technology PCI0648", 296 cmd0643_9_chip_map, 297 }, 298 { PCI_PRODUCT_CMDTECH_649, 299 IDE_PCI_CLASS_OVERRIDE, 300 "CMD Technology PCI0649", 301 cmd0643_9_chip_map, 302 }, 303 { 0, 304 0, 305 NULL, 306 } 307 }; 308 309 const struct pciide_product_desc pciide_via_products[] = { 310 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 311 0, 312 "VIA Tech VT82C586 IDE Controller", 313 apollo_chip_map, 314 }, 315 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 316 0, 317 "VIA Tech VT82C586A IDE Controller", 318 apollo_chip_map, 319 }, 320 { 0, 321 0, 322 NULL, 323 } 324 }; 325 326 const struct pciide_product_desc pciide_cypress_products[] = { 327 { PCI_PRODUCT_CONTAQ_82C693, 328 0, 329 "Cypress 82C693 IDE Controller", 330 cy693_chip_map, 331 }, 332 { 0, 333 0, 334 NULL, 335 } 336 }; 337 338 const struct pciide_product_desc pciide_sis_products[] = { 339 { PCI_PRODUCT_SIS_5597_IDE, 340 0, 341 "Silicon Integrated System 5597/5598 IDE controller", 342 sis_chip_map, 343 }, 344 { 0, 345 0, 346 NULL, 347 } 348 }; 349 350 const struct pciide_product_desc pciide_acer_products[] = { 351 { PCI_PRODUCT_ALI_M5229, 352 0, 353 "Acer Labs M5229 UDMA IDE Controller", 354 acer_chip_map, 355 }, 356 { 0, 357 0, 358 NULL, 359 } 360 }; 361 362 const struct pciide_product_desc pciide_promise_products[] = { 363 { PCI_PRODUCT_PROMISE_ULTRA33, 364 IDE_PCI_CLASS_OVERRIDE, 365 "Promise Ultra33/ATA Bus Master IDE Accelerator", 366 pdc202xx_chip_map, 367 }, 368 { PCI_PRODUCT_PROMISE_ULTRA66, 369 IDE_PCI_CLASS_OVERRIDE, 370 "Promise Ultra66/ATA Bus Master IDE Accelerator", 371 pdc202xx_chip_map, 372 }, 373 { PCI_PRODUCT_PROMISE_ULTRA100, 374 IDE_PCI_CLASS_OVERRIDE, 375 "Promise Ultra100/ATA Bus Master IDE Accelerator", 376 pdc202xx_chip_map, 377 }, 378 { PCI_PRODUCT_PROMISE_ULTRA100X, 379 IDE_PCI_CLASS_OVERRIDE, 380 "Promise Ultra100/ATA Bus Master IDE Accelerator", 381 pdc202xx_chip_map, 382 }, 383 { 0, 384 0, 385 NULL, 386 } 387 }; 388 389 const struct pciide_product_desc pciide_opti_products[] = { 390 { PCI_PRODUCT_OPTI_82C621, 391 0, 392 "OPTi 82c621 PCI IDE controller", 393 opti_chip_map, 394 }, 395 { PCI_PRODUCT_OPTI_82C568, 396 0, 397 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 398 opti_chip_map, 399 }, 400 { PCI_PRODUCT_OPTI_82D568, 401 0, 402 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 403 opti_chip_map, 404 }, 405 { 0, 406 0, 407 NULL, 408 } 409 }; 410 411 const struct pciide_product_desc pciide_triones_products[] = { 412 { PCI_PRODUCT_TRIONES_HPT366, 413 IDE_PCI_CLASS_OVERRIDE, 414 "Triones/Highpoint HPT366/370 IDE Controller", 415 hpt_chip_map, 416 }, 417 { 0, 418 0, 419 NULL, 420 } 421 }; 422 423 struct pciide_vendor_desc { 424 u_int32_t ide_vendor; 425 const struct pciide_product_desc *ide_products; 426 }; 427 428 const struct pciide_vendor_desc pciide_vendors[] = { 429 { PCI_VENDOR_INTEL, pciide_intel_products }, 430 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 431 { PCI_VENDOR_VIATECH, pciide_via_products }, 432 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 433 { PCI_VENDOR_SIS, pciide_sis_products }, 434 { PCI_VENDOR_ALI, pciide_acer_products }, 435 { PCI_VENDOR_PROMISE, pciide_promise_products }, 436 { PCI_VENDOR_AMD, pciide_amd_products }, 437 { PCI_VENDOR_OPTI, pciide_opti_products }, 438 { PCI_VENDOR_TRIONES, pciide_triones_products }, 439 { 0, NULL } 440 }; 441 442 /* options passed via the 'flags' config keyword */ 443 #define PCIIDE_OPTIONS_DMA 0x01 444 445 int pciide_match __P((struct device *, struct cfdata *, void *)); 446 void pciide_attach __P((struct device *, struct device *, void *)); 447 448 struct cfattach pciide_ca = { 449 sizeof(struct pciide_softc), pciide_match, pciide_attach 450 }; 451 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 452 int pciide_mapregs_compat __P(( struct pci_attach_args *, 453 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 454 int pciide_mapregs_native __P((struct pci_attach_args *, 455 struct pciide_channel *, bus_size_t *, bus_size_t *, 456 int (*pci_intr) __P((void *)))); 457 void pciide_mapreg_dma __P((struct pciide_softc *, 458 struct pci_attach_args *)); 459 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 460 void pciide_mapchan __P((struct pci_attach_args *, 461 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 462 int (*pci_intr) __P((void *)))); 463 int pciide_chan_candisable __P((struct pciide_channel *)); 464 void pciide_map_compat_intr __P(( struct pci_attach_args *, 465 struct pciide_channel *, int, int)); 466 int pciide_print __P((void *, const char *pnp)); 467 int pciide_compat_intr __P((void *)); 468 int pciide_pci_intr __P((void *)); 469 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 470 471 const struct pciide_product_desc * 472 pciide_lookup_product(id) 473 u_int32_t id; 474 { 475 const struct pciide_product_desc *pp; 476 const struct pciide_vendor_desc *vp; 477 478 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 479 if (PCI_VENDOR(id) == vp->ide_vendor) 480 break; 481 482 if ((pp = vp->ide_products) == NULL) 483 return NULL; 484 485 for (; pp->ide_name != NULL; pp++) 486 if (PCI_PRODUCT(id) == pp->ide_product) 487 break; 488 489 if (pp->ide_name == NULL) 490 return NULL; 491 return pp; 492 } 493 494 int 495 pciide_match(parent, match, aux) 496 struct device *parent; 497 struct cfdata *match; 498 void *aux; 499 { 500 struct pci_attach_args *pa = aux; 501 const struct pciide_product_desc *pp; 502 503 /* 504 * Check the ID register to see that it's a PCI IDE controller. 505 * If it is, we assume that we can deal with it; it _should_ 506 * work in a standardized way... 507 */ 508 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 509 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 510 return (1); 511 } 512 513 /* 514 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 515 * controllers. Let see if we can deal with it anyway. 516 */ 517 pp = pciide_lookup_product(pa->pa_id); 518 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 519 return (1); 520 } 521 522 return (0); 523 } 524 525 void 526 pciide_attach(parent, self, aux) 527 struct device *parent, *self; 528 void *aux; 529 { 530 struct pci_attach_args *pa = aux; 531 pci_chipset_tag_t pc = pa->pa_pc; 532 pcitag_t tag = pa->pa_tag; 533 struct pciide_softc *sc = (struct pciide_softc *)self; 534 pcireg_t csr; 535 char devinfo[256]; 536 const char *displaydev; 537 538 sc->sc_pp = pciide_lookup_product(pa->pa_id); 539 if (sc->sc_pp == NULL) { 540 sc->sc_pp = &default_product_desc; 541 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 542 displaydev = devinfo; 543 } else 544 displaydev = sc->sc_pp->ide_name; 545 546 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 547 548 sc->sc_pc = pa->pa_pc; 549 sc->sc_tag = pa->pa_tag; 550 #ifdef WDCDEBUG 551 if (wdcdebug_pciide_mask & DEBUG_PROBE) 552 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 553 #endif 554 sc->sc_pp->chip_map(sc, pa); 555 556 if (sc->sc_dma_ok) { 557 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 558 csr |= PCI_COMMAND_MASTER_ENABLE; 559 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 560 } 561 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 562 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 563 } 564 565 /* tell wether the chip is enabled or not */ 566 int 567 pciide_chipen(sc, pa) 568 struct pciide_softc *sc; 569 struct pci_attach_args *pa; 570 { 571 pcireg_t csr; 572 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 573 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 574 PCI_COMMAND_STATUS_REG); 575 printf("%s: device disabled (at %s)\n", 576 sc->sc_wdcdev.sc_dev.dv_xname, 577 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 578 "device" : "bridge"); 579 return 0; 580 } 581 return 1; 582 } 583 584 int 585 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 586 struct pci_attach_args *pa; 587 struct pciide_channel *cp; 588 int compatchan; 589 bus_size_t *cmdsizep, *ctlsizep; 590 { 591 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 592 struct channel_softc *wdc_cp = &cp->wdc_channel; 593 594 cp->compat = 1; 595 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 596 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 597 598 wdc_cp->cmd_iot = pa->pa_iot; 599 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 600 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 601 printf("%s: couldn't map %s channel cmd regs\n", 602 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 603 return (0); 604 } 605 606 wdc_cp->ctl_iot = pa->pa_iot; 607 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 608 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 609 printf("%s: couldn't map %s channel ctl regs\n", 610 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 611 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 612 PCIIDE_COMPAT_CMD_SIZE); 613 return (0); 614 } 615 616 return (1); 617 } 618 619 int 620 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 621 struct pci_attach_args * pa; 622 struct pciide_channel *cp; 623 bus_size_t *cmdsizep, *ctlsizep; 624 int (*pci_intr) __P((void *)); 625 { 626 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 627 struct channel_softc *wdc_cp = &cp->wdc_channel; 628 const char *intrstr; 629 pci_intr_handle_t intrhandle; 630 631 cp->compat = 0; 632 633 if (sc->sc_pci_ih == NULL) { 634 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 635 pa->pa_intrline, &intrhandle) != 0) { 636 printf("%s: couldn't map native-PCI interrupt\n", 637 sc->sc_wdcdev.sc_dev.dv_xname); 638 return 0; 639 } 640 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 641 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 642 intrhandle, IPL_BIO, pci_intr, sc); 643 if (sc->sc_pci_ih != NULL) { 644 printf("%s: using %s for native-PCI interrupt\n", 645 sc->sc_wdcdev.sc_dev.dv_xname, 646 intrstr ? intrstr : "unknown interrupt"); 647 } else { 648 printf("%s: couldn't establish native-PCI interrupt", 649 sc->sc_wdcdev.sc_dev.dv_xname); 650 if (intrstr != NULL) 651 printf(" at %s", intrstr); 652 printf("\n"); 653 return 0; 654 } 655 } 656 cp->ih = sc->sc_pci_ih; 657 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 658 PCI_MAPREG_TYPE_IO, 0, 659 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 660 printf("%s: couldn't map %s channel cmd regs\n", 661 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 662 return 0; 663 } 664 665 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 666 PCI_MAPREG_TYPE_IO, 0, 667 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 668 printf("%s: couldn't map %s channel ctl regs\n", 669 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 670 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 671 return 0; 672 } 673 return (1); 674 } 675 676 void 677 pciide_mapreg_dma(sc, pa) 678 struct pciide_softc *sc; 679 struct pci_attach_args *pa; 680 { 681 pcireg_t maptype; 682 bus_addr_t addr; 683 684 /* 685 * Map DMA registers 686 * 687 * Note that sc_dma_ok is the right variable to test to see if 688 * DMA can be done. If the interface doesn't support DMA, 689 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 690 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 691 * non-zero if the interface supports DMA and the registers 692 * could be mapped. 693 * 694 * XXX Note that despite the fact that the Bus Master IDE specs 695 * XXX say that "The bus master IDE function uses 16 bytes of IO 696 * XXX space," some controllers (at least the United 697 * XXX Microelectronics UM8886BF) place it in memory space. 698 */ 699 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 700 PCIIDE_REG_BUS_MASTER_DMA); 701 702 switch (maptype) { 703 case PCI_MAPREG_TYPE_IO: 704 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 705 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 706 &addr, NULL, NULL) == 0); 707 if (sc->sc_dma_ok == 0) { 708 printf(", but unused (couldn't query registers)"); 709 break; 710 } 711 if (addr >= 0x10000) { 712 sc->sc_dma_ok = 0; 713 printf(", but unused (registers at unsafe address %#lx)", addr); 714 break; 715 } 716 /* FALLTHROUGH */ 717 718 case PCI_MAPREG_MEM_TYPE_32BIT: 719 sc->sc_dma_ok = (pci_mapreg_map(pa, 720 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 721 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 722 sc->sc_dmat = pa->pa_dmat; 723 if (sc->sc_dma_ok == 0) { 724 printf(", but unused (couldn't map registers)"); 725 } else { 726 sc->sc_wdcdev.dma_arg = sc; 727 sc->sc_wdcdev.dma_init = pciide_dma_init; 728 sc->sc_wdcdev.dma_start = pciide_dma_start; 729 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 730 } 731 break; 732 733 default: 734 sc->sc_dma_ok = 0; 735 printf(", but unsupported register maptype (0x%x)", maptype); 736 } 737 } 738 739 int 740 pciide_compat_intr(arg) 741 void *arg; 742 { 743 struct pciide_channel *cp = arg; 744 745 #ifdef DIAGNOSTIC 746 /* should only be called for a compat channel */ 747 if (cp->compat == 0) 748 panic("pciide compat intr called for non-compat chan %p\n", cp); 749 #endif 750 return (wdcintr(&cp->wdc_channel)); 751 } 752 753 int 754 pciide_pci_intr(arg) 755 void *arg; 756 { 757 struct pciide_softc *sc = arg; 758 struct pciide_channel *cp; 759 struct channel_softc *wdc_cp; 760 int i, rv, crv; 761 762 rv = 0; 763 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 764 cp = &sc->pciide_channels[i]; 765 wdc_cp = &cp->wdc_channel; 766 767 /* If a compat channel skip. */ 768 if (cp->compat) 769 continue; 770 /* if this channel not waiting for intr, skip */ 771 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 772 continue; 773 774 crv = wdcintr(wdc_cp); 775 if (crv == 0) 776 ; /* leave rv alone */ 777 else if (crv == 1) 778 rv = 1; /* claim the intr */ 779 else if (rv == 0) /* crv should be -1 in this case */ 780 rv = crv; /* if we've done no better, take it */ 781 } 782 return (rv); 783 } 784 785 void 786 pciide_channel_dma_setup(cp) 787 struct pciide_channel *cp; 788 { 789 int drive; 790 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 791 struct ata_drive_datas *drvp; 792 793 for (drive = 0; drive < 2; drive++) { 794 drvp = &cp->wdc_channel.ch_drive[drive]; 795 /* If no drive, skip */ 796 if ((drvp->drive_flags & DRIVE) == 0) 797 continue; 798 /* setup DMA if needed */ 799 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 800 (drvp->drive_flags & DRIVE_UDMA) == 0) || 801 sc->sc_dma_ok == 0) { 802 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 803 continue; 804 } 805 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 806 != 0) { 807 /* Abort DMA setup */ 808 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 809 continue; 810 } 811 } 812 } 813 814 int 815 pciide_dma_table_setup(sc, channel, drive) 816 struct pciide_softc *sc; 817 int channel, drive; 818 { 819 bus_dma_segment_t seg; 820 int error, rseg; 821 const bus_size_t dma_table_size = 822 sizeof(struct idedma_table) * NIDEDMA_TABLES; 823 struct pciide_dma_maps *dma_maps = 824 &sc->pciide_channels[channel].dma_maps[drive]; 825 826 /* If table was already allocated, just return */ 827 if (dma_maps->dma_table) 828 return 0; 829 830 /* Allocate memory for the DMA tables and map it */ 831 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 832 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 833 BUS_DMA_NOWAIT)) != 0) { 834 printf("%s:%d: unable to allocate table DMA for " 835 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 836 channel, drive, error); 837 return error; 838 } 839 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 840 dma_table_size, 841 (caddr_t *)&dma_maps->dma_table, 842 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 843 printf("%s:%d: unable to map table DMA for" 844 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 845 channel, drive, error); 846 return error; 847 } 848 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 849 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 850 seg.ds_addr), DEBUG_PROBE); 851 852 /* Create and load table DMA map for this disk */ 853 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 854 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 855 &dma_maps->dmamap_table)) != 0) { 856 printf("%s:%d: unable to create table DMA map for " 857 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 858 channel, drive, error); 859 return error; 860 } 861 if ((error = bus_dmamap_load(sc->sc_dmat, 862 dma_maps->dmamap_table, 863 dma_maps->dma_table, 864 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 865 printf("%s:%d: unable to load table DMA map for " 866 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 867 channel, drive, error); 868 return error; 869 } 870 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 871 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 872 /* Create a xfer DMA map for this drive */ 873 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 874 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 875 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 876 &dma_maps->dmamap_xfer)) != 0) { 877 printf("%s:%d: unable to create xfer DMA map for " 878 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 879 channel, drive, error); 880 return error; 881 } 882 return 0; 883 } 884 885 int 886 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 887 void *v; 888 int channel, drive; 889 void *databuf; 890 size_t datalen; 891 int flags; 892 { 893 struct pciide_softc *sc = v; 894 int error, seg; 895 struct pciide_dma_maps *dma_maps = 896 &sc->pciide_channels[channel].dma_maps[drive]; 897 898 error = bus_dmamap_load(sc->sc_dmat, 899 dma_maps->dmamap_xfer, 900 databuf, datalen, NULL, BUS_DMA_NOWAIT); 901 if (error) { 902 printf("%s:%d: unable to load xfer DMA map for" 903 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 904 channel, drive, error); 905 return error; 906 } 907 908 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 909 dma_maps->dmamap_xfer->dm_mapsize, 910 (flags & WDC_DMA_READ) ? 911 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 912 913 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 914 #ifdef DIAGNOSTIC 915 /* A segment must not cross a 64k boundary */ 916 { 917 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 918 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 919 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 920 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 921 printf("pciide_dma: segment %d physical addr 0x%lx" 922 " len 0x%lx not properly aligned\n", 923 seg, phys, len); 924 panic("pciide_dma: buf align"); 925 } 926 } 927 #endif 928 dma_maps->dma_table[seg].base_addr = 929 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 930 dma_maps->dma_table[seg].byte_count = 931 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 932 IDEDMA_BYTE_COUNT_MASK); 933 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 934 seg, le32toh(dma_maps->dma_table[seg].byte_count), 935 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 936 937 } 938 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 939 htole32(IDEDMA_BYTE_COUNT_EOT); 940 941 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 942 dma_maps->dmamap_table->dm_mapsize, 943 BUS_DMASYNC_PREWRITE); 944 945 /* Maps are ready. Start DMA function */ 946 #ifdef DIAGNOSTIC 947 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 948 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 949 dma_maps->dmamap_table->dm_segs[0].ds_addr); 950 panic("pciide_dma_init: table align"); 951 } 952 #endif 953 954 /* Clear status bits */ 955 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 956 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 957 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 958 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 959 /* Write table addr */ 960 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 961 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 962 dma_maps->dmamap_table->dm_segs[0].ds_addr); 963 /* set read/write */ 964 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 965 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 966 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 967 /* remember flags */ 968 dma_maps->dma_flags = flags; 969 return 0; 970 } 971 972 void 973 pciide_dma_start(v, channel, drive) 974 void *v; 975 int channel, drive; 976 { 977 struct pciide_softc *sc = v; 978 979 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 980 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 981 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 982 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 983 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 984 } 985 986 int 987 pciide_dma_finish(v, channel, drive, force) 988 void *v; 989 int channel, drive; 990 int force; 991 { 992 struct pciide_softc *sc = v; 993 u_int8_t status; 994 int error = 0; 995 struct pciide_dma_maps *dma_maps = 996 &sc->pciide_channels[channel].dma_maps[drive]; 997 998 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 999 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1000 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1001 DEBUG_XFERS); 1002 1003 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1004 return WDC_DMAST_NOIRQ; 1005 1006 /* stop DMA channel */ 1007 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1008 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1009 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1010 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1011 1012 /* Unload the map of the data buffer */ 1013 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1014 dma_maps->dmamap_xfer->dm_mapsize, 1015 (dma_maps->dma_flags & WDC_DMA_READ) ? 1016 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1017 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1018 1019 if ((status & IDEDMA_CTL_ERR) != 0) { 1020 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1021 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1022 error |= WDC_DMAST_ERR; 1023 } 1024 1025 if ((status & IDEDMA_CTL_INTR) == 0) { 1026 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1027 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1028 drive, status); 1029 error |= WDC_DMAST_NOIRQ; 1030 } 1031 1032 if ((status & IDEDMA_CTL_ACT) != 0) { 1033 /* data underrun, may be a valid condition for ATAPI */ 1034 error |= WDC_DMAST_UNDER; 1035 } 1036 return error; 1037 } 1038 1039 void 1040 pciide_irqack(chp) 1041 struct channel_softc *chp; 1042 { 1043 struct pciide_channel *cp = (struct pciide_channel*)chp; 1044 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1045 1046 /* clear status bits in IDE DMA registers */ 1047 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1048 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1049 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1050 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1051 } 1052 1053 /* some common code used by several chip_map */ 1054 int 1055 pciide_chansetup(sc, channel, interface) 1056 struct pciide_softc *sc; 1057 int channel; 1058 pcireg_t interface; 1059 { 1060 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1061 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1062 cp->name = PCIIDE_CHANNEL_NAME(channel); 1063 cp->wdc_channel.channel = channel; 1064 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1065 cp->wdc_channel.ch_queue = 1066 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1067 if (cp->wdc_channel.ch_queue == NULL) { 1068 printf("%s %s channel: " 1069 "can't allocate memory for command queue", 1070 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1071 return 0; 1072 } 1073 printf("%s: %s channel %s to %s mode\n", 1074 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1075 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1076 "configured" : "wired", 1077 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1078 "native-PCI" : "compatibility"); 1079 return 1; 1080 } 1081 1082 /* some common code used by several chip channel_map */ 1083 void 1084 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1085 struct pci_attach_args *pa; 1086 struct pciide_channel *cp; 1087 pcireg_t interface; 1088 bus_size_t *cmdsizep, *ctlsizep; 1089 int (*pci_intr) __P((void *)); 1090 { 1091 struct channel_softc *wdc_cp = &cp->wdc_channel; 1092 1093 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1094 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1095 pci_intr); 1096 else 1097 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1098 wdc_cp->channel, cmdsizep, ctlsizep); 1099 1100 if (cp->hw_ok == 0) 1101 return; 1102 wdc_cp->data32iot = wdc_cp->cmd_iot; 1103 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1104 wdcattach(wdc_cp); 1105 } 1106 1107 /* 1108 * Generic code to call to know if a channel can be disabled. Return 1 1109 * if channel can be disabled, 0 if not 1110 */ 1111 int 1112 pciide_chan_candisable(cp) 1113 struct pciide_channel *cp; 1114 { 1115 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1116 struct channel_softc *wdc_cp = &cp->wdc_channel; 1117 1118 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1119 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1120 printf("%s: disabling %s channel (no drives)\n", 1121 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1122 cp->hw_ok = 0; 1123 return 1; 1124 } 1125 return 0; 1126 } 1127 1128 /* 1129 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1130 * Set hw_ok=0 on failure 1131 */ 1132 void 1133 pciide_map_compat_intr(pa, cp, compatchan, interface) 1134 struct pci_attach_args *pa; 1135 struct pciide_channel *cp; 1136 int compatchan, interface; 1137 { 1138 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1139 struct channel_softc *wdc_cp = &cp->wdc_channel; 1140 1141 if (cp->hw_ok == 0) 1142 return; 1143 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1144 return; 1145 1146 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1147 pa, compatchan, pciide_compat_intr, cp); 1148 if (cp->ih == NULL) { 1149 printf("%s: no compatibility interrupt for use by %s " 1150 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1151 cp->hw_ok = 0; 1152 } 1153 } 1154 1155 void 1156 pciide_print_modes(cp) 1157 struct pciide_channel *cp; 1158 { 1159 wdc_print_modes(&cp->wdc_channel); 1160 } 1161 1162 void 1163 default_chip_map(sc, pa) 1164 struct pciide_softc *sc; 1165 struct pci_attach_args *pa; 1166 { 1167 struct pciide_channel *cp; 1168 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1169 pcireg_t csr; 1170 int channel, drive; 1171 struct ata_drive_datas *drvp; 1172 u_int8_t idedma_ctl; 1173 bus_size_t cmdsize, ctlsize; 1174 char *failreason; 1175 1176 if (pciide_chipen(sc, pa) == 0) 1177 return; 1178 1179 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1180 printf("%s: bus-master DMA support present", 1181 sc->sc_wdcdev.sc_dev.dv_xname); 1182 if (sc->sc_pp == &default_product_desc && 1183 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1184 PCIIDE_OPTIONS_DMA) == 0) { 1185 printf(", but unused (no driver support)"); 1186 sc->sc_dma_ok = 0; 1187 } else { 1188 pciide_mapreg_dma(sc, pa); 1189 if (sc->sc_dma_ok != 0) 1190 printf(", used without full driver " 1191 "support"); 1192 } 1193 } else { 1194 printf("%s: hardware does not support DMA", 1195 sc->sc_wdcdev.sc_dev.dv_xname); 1196 sc->sc_dma_ok = 0; 1197 } 1198 printf("\n"); 1199 if (sc->sc_dma_ok) { 1200 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1201 sc->sc_wdcdev.irqack = pciide_irqack; 1202 } 1203 sc->sc_wdcdev.PIO_cap = 0; 1204 sc->sc_wdcdev.DMA_cap = 0; 1205 1206 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1207 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1208 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1209 1210 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1211 cp = &sc->pciide_channels[channel]; 1212 if (pciide_chansetup(sc, channel, interface) == 0) 1213 continue; 1214 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1215 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1216 &ctlsize, pciide_pci_intr); 1217 } else { 1218 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1219 channel, &cmdsize, &ctlsize); 1220 } 1221 if (cp->hw_ok == 0) 1222 continue; 1223 /* 1224 * Check to see if something appears to be there. 1225 */ 1226 failreason = NULL; 1227 if (!wdcprobe(&cp->wdc_channel)) { 1228 failreason = "not responding; disabled or no drives?"; 1229 goto next; 1230 } 1231 /* 1232 * Now, make sure it's actually attributable to this PCI IDE 1233 * channel by trying to access the channel again while the 1234 * PCI IDE controller's I/O space is disabled. (If the 1235 * channel no longer appears to be there, it belongs to 1236 * this controller.) YUCK! 1237 */ 1238 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1239 PCI_COMMAND_STATUS_REG); 1240 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1241 csr & ~PCI_COMMAND_IO_ENABLE); 1242 if (wdcprobe(&cp->wdc_channel)) 1243 failreason = "other hardware responding at addresses"; 1244 pci_conf_write(sc->sc_pc, sc->sc_tag, 1245 PCI_COMMAND_STATUS_REG, csr); 1246 next: 1247 if (failreason) { 1248 printf("%s: %s channel ignored (%s)\n", 1249 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1250 failreason); 1251 cp->hw_ok = 0; 1252 bus_space_unmap(cp->wdc_channel.cmd_iot, 1253 cp->wdc_channel.cmd_ioh, cmdsize); 1254 bus_space_unmap(cp->wdc_channel.ctl_iot, 1255 cp->wdc_channel.ctl_ioh, ctlsize); 1256 } else { 1257 pciide_map_compat_intr(pa, cp, channel, interface); 1258 } 1259 if (cp->hw_ok) { 1260 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1261 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1262 wdcattach(&cp->wdc_channel); 1263 } 1264 } 1265 1266 if (sc->sc_dma_ok == 0) 1267 return; 1268 1269 /* Allocate DMA maps */ 1270 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1271 idedma_ctl = 0; 1272 cp = &sc->pciide_channels[channel]; 1273 for (drive = 0; drive < 2; drive++) { 1274 drvp = &cp->wdc_channel.ch_drive[drive]; 1275 /* If no drive, skip */ 1276 if ((drvp->drive_flags & DRIVE) == 0) 1277 continue; 1278 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1279 continue; 1280 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1281 /* Abort DMA setup */ 1282 printf("%s:%d:%d: can't allocate DMA maps, " 1283 "using PIO transfers\n", 1284 sc->sc_wdcdev.sc_dev.dv_xname, 1285 channel, drive); 1286 drvp->drive_flags &= ~DRIVE_DMA; 1287 } 1288 printf("%s:%d:%d: using DMA data transfers\n", 1289 sc->sc_wdcdev.sc_dev.dv_xname, 1290 channel, drive); 1291 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1292 } 1293 if (idedma_ctl != 0) { 1294 /* Add software bits in status register */ 1295 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1296 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1297 idedma_ctl); 1298 } 1299 } 1300 } 1301 1302 void 1303 piix_chip_map(sc, pa) 1304 struct pciide_softc *sc; 1305 struct pci_attach_args *pa; 1306 { 1307 struct pciide_channel *cp; 1308 int channel; 1309 u_int32_t idetim; 1310 bus_size_t cmdsize, ctlsize; 1311 1312 if (pciide_chipen(sc, pa) == 0) 1313 return; 1314 1315 printf("%s: bus-master DMA support present", 1316 sc->sc_wdcdev.sc_dev.dv_xname); 1317 pciide_mapreg_dma(sc, pa); 1318 printf("\n"); 1319 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1320 WDC_CAPABILITY_MODE; 1321 if (sc->sc_dma_ok) { 1322 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1323 sc->sc_wdcdev.irqack = pciide_irqack; 1324 switch(sc->sc_pp->ide_product) { 1325 case PCI_PRODUCT_INTEL_82371AB_IDE: 1326 case PCI_PRODUCT_INTEL_82440MX_IDE: 1327 case PCI_PRODUCT_INTEL_82801AA_IDE: 1328 case PCI_PRODUCT_INTEL_82801AB_IDE: 1329 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1330 } 1331 } 1332 sc->sc_wdcdev.PIO_cap = 4; 1333 sc->sc_wdcdev.DMA_cap = 2; 1334 sc->sc_wdcdev.UDMA_cap = 1335 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1336 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1337 sc->sc_wdcdev.set_modes = piix_setup_channel; 1338 else 1339 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1340 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1341 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1342 1343 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1344 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1345 DEBUG_PROBE); 1346 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1347 WDCDEBUG_PRINT((", sidetim=0x%x", 1348 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1349 DEBUG_PROBE); 1350 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1351 WDCDEBUG_PRINT((", udamreg 0x%x", 1352 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1353 DEBUG_PROBE); 1354 } 1355 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1356 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1357 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1358 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1359 DEBUG_PROBE); 1360 } 1361 1362 } 1363 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1364 1365 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1366 cp = &sc->pciide_channels[channel]; 1367 /* PIIX is compat-only */ 1368 if (pciide_chansetup(sc, channel, 0) == 0) 1369 continue; 1370 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1371 if ((PIIX_IDETIM_READ(idetim, channel) & 1372 PIIX_IDETIM_IDE) == 0) { 1373 printf("%s: %s channel ignored (disabled)\n", 1374 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1375 continue; 1376 } 1377 /* PIIX are compat-only pciide devices */ 1378 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1379 if (cp->hw_ok == 0) 1380 continue; 1381 if (pciide_chan_candisable(cp)) { 1382 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1383 channel); 1384 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1385 idetim); 1386 } 1387 pciide_map_compat_intr(pa, cp, channel, 0); 1388 if (cp->hw_ok == 0) 1389 continue; 1390 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1391 } 1392 1393 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1394 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1395 DEBUG_PROBE); 1396 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1397 WDCDEBUG_PRINT((", sidetim=0x%x", 1398 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1399 DEBUG_PROBE); 1400 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1401 WDCDEBUG_PRINT((", udamreg 0x%x", 1402 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1403 DEBUG_PROBE); 1404 } 1405 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1406 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1407 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1408 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1409 DEBUG_PROBE); 1410 } 1411 } 1412 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1413 } 1414 1415 void 1416 piix_setup_channel(chp) 1417 struct channel_softc *chp; 1418 { 1419 u_int8_t mode[2], drive; 1420 u_int32_t oidetim, idetim, idedma_ctl; 1421 struct pciide_channel *cp = (struct pciide_channel*)chp; 1422 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1423 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1424 1425 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1426 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1427 idedma_ctl = 0; 1428 1429 /* set up new idetim: Enable IDE registers decode */ 1430 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1431 chp->channel); 1432 1433 /* setup DMA */ 1434 pciide_channel_dma_setup(cp); 1435 1436 /* 1437 * Here we have to mess up with drives mode: PIIX can't have 1438 * different timings for master and slave drives. 1439 * We need to find the best combination. 1440 */ 1441 1442 /* If both drives supports DMA, take the lower mode */ 1443 if ((drvp[0].drive_flags & DRIVE_DMA) && 1444 (drvp[1].drive_flags & DRIVE_DMA)) { 1445 mode[0] = mode[1] = 1446 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1447 drvp[0].DMA_mode = mode[0]; 1448 drvp[1].DMA_mode = mode[1]; 1449 goto ok; 1450 } 1451 /* 1452 * If only one drive supports DMA, use its mode, and 1453 * put the other one in PIO mode 0 if mode not compatible 1454 */ 1455 if (drvp[0].drive_flags & DRIVE_DMA) { 1456 mode[0] = drvp[0].DMA_mode; 1457 mode[1] = drvp[1].PIO_mode; 1458 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1459 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1460 mode[1] = drvp[1].PIO_mode = 0; 1461 goto ok; 1462 } 1463 if (drvp[1].drive_flags & DRIVE_DMA) { 1464 mode[1] = drvp[1].DMA_mode; 1465 mode[0] = drvp[0].PIO_mode; 1466 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1467 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1468 mode[0] = drvp[0].PIO_mode = 0; 1469 goto ok; 1470 } 1471 /* 1472 * If both drives are not DMA, takes the lower mode, unless 1473 * one of them is PIO mode < 2 1474 */ 1475 if (drvp[0].PIO_mode < 2) { 1476 mode[0] = drvp[0].PIO_mode = 0; 1477 mode[1] = drvp[1].PIO_mode; 1478 } else if (drvp[1].PIO_mode < 2) { 1479 mode[1] = drvp[1].PIO_mode = 0; 1480 mode[0] = drvp[0].PIO_mode; 1481 } else { 1482 mode[0] = mode[1] = 1483 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1484 drvp[0].PIO_mode = mode[0]; 1485 drvp[1].PIO_mode = mode[1]; 1486 } 1487 ok: /* The modes are setup */ 1488 for (drive = 0; drive < 2; drive++) { 1489 if (drvp[drive].drive_flags & DRIVE_DMA) { 1490 idetim |= piix_setup_idetim_timings( 1491 mode[drive], 1, chp->channel); 1492 goto end; 1493 } 1494 } 1495 /* If we are there, none of the drives are DMA */ 1496 if (mode[0] >= 2) 1497 idetim |= piix_setup_idetim_timings( 1498 mode[0], 0, chp->channel); 1499 else 1500 idetim |= piix_setup_idetim_timings( 1501 mode[1], 0, chp->channel); 1502 end: /* 1503 * timing mode is now set up in the controller. Enable 1504 * it per-drive 1505 */ 1506 for (drive = 0; drive < 2; drive++) { 1507 /* If no drive, skip */ 1508 if ((drvp[drive].drive_flags & DRIVE) == 0) 1509 continue; 1510 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1511 if (drvp[drive].drive_flags & DRIVE_DMA) 1512 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1513 } 1514 if (idedma_ctl != 0) { 1515 /* Add software bits in status register */ 1516 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1517 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1518 idedma_ctl); 1519 } 1520 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1521 pciide_print_modes(cp); 1522 } 1523 1524 void 1525 piix3_4_setup_channel(chp) 1526 struct channel_softc *chp; 1527 { 1528 struct ata_drive_datas *drvp; 1529 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1530 struct pciide_channel *cp = (struct pciide_channel*)chp; 1531 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1532 int drive; 1533 int channel = chp->channel; 1534 1535 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1536 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1537 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1538 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1539 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1540 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1541 PIIX_SIDETIM_RTC_MASK(channel)); 1542 1543 idedma_ctl = 0; 1544 /* If channel disabled, no need to go further */ 1545 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1546 return; 1547 /* set up new idetim: Enable IDE registers decode */ 1548 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1549 1550 /* setup DMA if needed */ 1551 pciide_channel_dma_setup(cp); 1552 1553 for (drive = 0; drive < 2; drive++) { 1554 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1555 PIIX_UDMATIM_SET(0x3, channel, drive)); 1556 drvp = &chp->ch_drive[drive]; 1557 /* If no drive, skip */ 1558 if ((drvp->drive_flags & DRIVE) == 0) 1559 continue; 1560 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1561 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1562 goto pio; 1563 1564 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1565 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1566 ideconf |= PIIX_CONFIG_PINGPONG; 1567 } 1568 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1569 /* setup Ultra/66 */ 1570 if (drvp->UDMA_mode > 2 && 1571 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1572 drvp->UDMA_mode = 2; 1573 if (drvp->UDMA_mode > 2) 1574 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1575 else 1576 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1577 } 1578 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1579 (drvp->drive_flags & DRIVE_UDMA)) { 1580 /* use Ultra/DMA */ 1581 drvp->drive_flags &= ~DRIVE_DMA; 1582 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1583 udmareg |= PIIX_UDMATIM_SET( 1584 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1585 } else { 1586 /* use Multiword DMA */ 1587 drvp->drive_flags &= ~DRIVE_UDMA; 1588 if (drive == 0) { 1589 idetim |= piix_setup_idetim_timings( 1590 drvp->DMA_mode, 1, channel); 1591 } else { 1592 sidetim |= piix_setup_sidetim_timings( 1593 drvp->DMA_mode, 1, channel); 1594 idetim =PIIX_IDETIM_SET(idetim, 1595 PIIX_IDETIM_SITRE, channel); 1596 } 1597 } 1598 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1599 1600 pio: /* use PIO mode */ 1601 idetim |= piix_setup_idetim_drvs(drvp); 1602 if (drive == 0) { 1603 idetim |= piix_setup_idetim_timings( 1604 drvp->PIO_mode, 0, channel); 1605 } else { 1606 sidetim |= piix_setup_sidetim_timings( 1607 drvp->PIO_mode, 0, channel); 1608 idetim =PIIX_IDETIM_SET(idetim, 1609 PIIX_IDETIM_SITRE, channel); 1610 } 1611 } 1612 if (idedma_ctl != 0) { 1613 /* Add software bits in status register */ 1614 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1615 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1616 idedma_ctl); 1617 } 1618 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1619 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1620 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1621 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1622 pciide_print_modes(cp); 1623 } 1624 1625 1626 /* setup ISP and RTC fields, based on mode */ 1627 static u_int32_t 1628 piix_setup_idetim_timings(mode, dma, channel) 1629 u_int8_t mode; 1630 u_int8_t dma; 1631 u_int8_t channel; 1632 { 1633 1634 if (dma) 1635 return PIIX_IDETIM_SET(0, 1636 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1637 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1638 channel); 1639 else 1640 return PIIX_IDETIM_SET(0, 1641 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1642 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1643 channel); 1644 } 1645 1646 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1647 static u_int32_t 1648 piix_setup_idetim_drvs(drvp) 1649 struct ata_drive_datas *drvp; 1650 { 1651 u_int32_t ret = 0; 1652 struct channel_softc *chp = drvp->chnl_softc; 1653 u_int8_t channel = chp->channel; 1654 u_int8_t drive = drvp->drive; 1655 1656 /* 1657 * If drive is using UDMA, timings setups are independant 1658 * So just check DMA and PIO here. 1659 */ 1660 if (drvp->drive_flags & DRIVE_DMA) { 1661 /* if mode = DMA mode 0, use compatible timings */ 1662 if ((drvp->drive_flags & DRIVE_DMA) && 1663 drvp->DMA_mode == 0) { 1664 drvp->PIO_mode = 0; 1665 return ret; 1666 } 1667 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1668 /* 1669 * PIO and DMA timings are the same, use fast timings for PIO 1670 * too, else use compat timings. 1671 */ 1672 if ((piix_isp_pio[drvp->PIO_mode] != 1673 piix_isp_dma[drvp->DMA_mode]) || 1674 (piix_rtc_pio[drvp->PIO_mode] != 1675 piix_rtc_dma[drvp->DMA_mode])) 1676 drvp->PIO_mode = 0; 1677 /* if PIO mode <= 2, use compat timings for PIO */ 1678 if (drvp->PIO_mode <= 2) { 1679 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1680 channel); 1681 return ret; 1682 } 1683 } 1684 1685 /* 1686 * Now setup PIO modes. If mode < 2, use compat timings. 1687 * Else enable fast timings. Enable IORDY and prefetch/post 1688 * if PIO mode >= 3. 1689 */ 1690 1691 if (drvp->PIO_mode < 2) 1692 return ret; 1693 1694 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1695 if (drvp->PIO_mode >= 3) { 1696 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1697 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1698 } 1699 return ret; 1700 } 1701 1702 /* setup values in SIDETIM registers, based on mode */ 1703 static u_int32_t 1704 piix_setup_sidetim_timings(mode, dma, channel) 1705 u_int8_t mode; 1706 u_int8_t dma; 1707 u_int8_t channel; 1708 { 1709 if (dma) 1710 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1711 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1712 else 1713 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1714 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1715 } 1716 1717 void 1718 amd756_chip_map(sc, pa) 1719 struct pciide_softc *sc; 1720 struct pci_attach_args *pa; 1721 { 1722 struct pciide_channel *cp; 1723 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1724 int channel; 1725 pcireg_t chanenable; 1726 bus_size_t cmdsize, ctlsize; 1727 1728 if (pciide_chipen(sc, pa) == 0) 1729 return; 1730 printf("%s: bus-master DMA support present", 1731 sc->sc_wdcdev.sc_dev.dv_xname); 1732 pciide_mapreg_dma(sc, pa); 1733 printf("\n"); 1734 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1735 WDC_CAPABILITY_MODE; 1736 if (sc->sc_dma_ok) { 1737 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1738 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1739 sc->sc_wdcdev.irqack = pciide_irqack; 1740 } 1741 sc->sc_wdcdev.PIO_cap = 4; 1742 sc->sc_wdcdev.DMA_cap = 2; 1743 sc->sc_wdcdev.UDMA_cap = 4; 1744 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1745 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1746 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1747 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1748 1749 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1750 DEBUG_PROBE); 1751 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1752 cp = &sc->pciide_channels[channel]; 1753 if (pciide_chansetup(sc, channel, interface) == 0) 1754 continue; 1755 1756 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1757 printf("%s: %s channel ignored (disabled)\n", 1758 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1759 continue; 1760 } 1761 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1762 pciide_pci_intr); 1763 1764 if (pciide_chan_candisable(cp)) 1765 chanenable &= ~AMD756_CHAN_EN(channel); 1766 pciide_map_compat_intr(pa, cp, channel, interface); 1767 if (cp->hw_ok == 0) 1768 continue; 1769 1770 amd756_setup_channel(&cp->wdc_channel); 1771 } 1772 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1773 chanenable); 1774 return; 1775 } 1776 1777 void 1778 amd756_setup_channel(chp) 1779 struct channel_softc *chp; 1780 { 1781 u_int32_t udmatim_reg, datatim_reg; 1782 u_int8_t idedma_ctl; 1783 int mode, drive; 1784 struct ata_drive_datas *drvp; 1785 struct pciide_channel *cp = (struct pciide_channel*)chp; 1786 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1787 #ifndef PCIIDE_AMD756_ENABLEDMA 1788 int rev = PCI_REVISION( 1789 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1790 #endif 1791 1792 idedma_ctl = 0; 1793 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1794 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1795 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1796 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1797 1798 /* setup DMA if needed */ 1799 pciide_channel_dma_setup(cp); 1800 1801 for (drive = 0; drive < 2; drive++) { 1802 drvp = &chp->ch_drive[drive]; 1803 /* If no drive, skip */ 1804 if ((drvp->drive_flags & DRIVE) == 0) 1805 continue; 1806 /* add timing values, setup DMA if needed */ 1807 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1808 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1809 mode = drvp->PIO_mode; 1810 goto pio; 1811 } 1812 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1813 (drvp->drive_flags & DRIVE_UDMA)) { 1814 /* use Ultra/DMA */ 1815 drvp->drive_flags &= ~DRIVE_DMA; 1816 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1817 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1818 AMD756_UDMA_TIME(chp->channel, drive, 1819 amd756_udma_tim[drvp->UDMA_mode]); 1820 /* can use PIO timings, MW DMA unused */ 1821 mode = drvp->PIO_mode; 1822 } else { 1823 /* use Multiword DMA, but only if revision is OK */ 1824 drvp->drive_flags &= ~DRIVE_UDMA; 1825 #ifndef PCIIDE_AMD756_ENABLEDMA 1826 /* 1827 * The workaround doesn't seem to be necessary 1828 * with all drives, so it can be disabled by 1829 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1830 * triggered. 1831 */ 1832 if (AMD756_CHIPREV_DISABLEDMA(rev)) { 1833 printf("%s:%d:%d: multi-word DMA disabled due " 1834 "to chip revision\n", 1835 sc->sc_wdcdev.sc_dev.dv_xname, 1836 chp->channel, drive); 1837 mode = drvp->PIO_mode; 1838 drvp->drive_flags &= ~DRIVE_DMA; 1839 goto pio; 1840 } 1841 #endif 1842 /* mode = min(pio, dma+2) */ 1843 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1844 mode = drvp->PIO_mode; 1845 else 1846 mode = drvp->DMA_mode + 2; 1847 } 1848 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1849 1850 pio: /* setup PIO mode */ 1851 if (mode <= 2) { 1852 drvp->DMA_mode = 0; 1853 drvp->PIO_mode = 0; 1854 mode = 0; 1855 } else { 1856 drvp->PIO_mode = mode; 1857 drvp->DMA_mode = mode - 2; 1858 } 1859 datatim_reg |= 1860 AMD756_DATATIM_PULSE(chp->channel, drive, 1861 amd756_pio_set[mode]) | 1862 AMD756_DATATIM_RECOV(chp->channel, drive, 1863 amd756_pio_rec[mode]); 1864 } 1865 if (idedma_ctl != 0) { 1866 /* Add software bits in status register */ 1867 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1868 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1869 idedma_ctl); 1870 } 1871 pciide_print_modes(cp); 1872 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1873 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1874 } 1875 1876 void 1877 apollo_chip_map(sc, pa) 1878 struct pciide_softc *sc; 1879 struct pci_attach_args *pa; 1880 { 1881 struct pciide_channel *cp; 1882 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1883 int rev = PCI_REVISION(pa->pa_class); 1884 int channel; 1885 u_int32_t ideconf; 1886 bus_size_t cmdsize, ctlsize; 1887 1888 if (pciide_chipen(sc, pa) == 0) 1889 return; 1890 printf("%s: bus-master DMA support present", 1891 sc->sc_wdcdev.sc_dev.dv_xname); 1892 pciide_mapreg_dma(sc, pa); 1893 printf("\n"); 1894 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1895 WDC_CAPABILITY_MODE; 1896 if (sc->sc_dma_ok) { 1897 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1898 sc->sc_wdcdev.irqack = pciide_irqack; 1899 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE 1900 && rev >= 6) 1901 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1902 } 1903 sc->sc_wdcdev.PIO_cap = 4; 1904 sc->sc_wdcdev.DMA_cap = 2; 1905 sc->sc_wdcdev.UDMA_cap = 2; 1906 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1907 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1908 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1909 1910 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1911 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1912 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1913 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1914 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1915 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1916 DEBUG_PROBE); 1917 1918 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1919 cp = &sc->pciide_channels[channel]; 1920 if (pciide_chansetup(sc, channel, interface) == 0) 1921 continue; 1922 1923 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1924 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1925 printf("%s: %s channel ignored (disabled)\n", 1926 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1927 continue; 1928 } 1929 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1930 pciide_pci_intr); 1931 if (cp->hw_ok == 0) 1932 continue; 1933 if (pciide_chan_candisable(cp)) { 1934 ideconf &= ~APO_IDECONF_EN(channel); 1935 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1936 ideconf); 1937 } 1938 pciide_map_compat_intr(pa, cp, channel, interface); 1939 1940 if (cp->hw_ok == 0) 1941 continue; 1942 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1943 } 1944 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1945 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1946 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1947 } 1948 1949 void 1950 apollo_setup_channel(chp) 1951 struct channel_softc *chp; 1952 { 1953 u_int32_t udmatim_reg, datatim_reg; 1954 u_int8_t idedma_ctl; 1955 int mode, drive; 1956 struct ata_drive_datas *drvp; 1957 struct pciide_channel *cp = (struct pciide_channel*)chp; 1958 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1959 1960 idedma_ctl = 0; 1961 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1962 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1963 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1964 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1965 1966 /* setup DMA if needed */ 1967 pciide_channel_dma_setup(cp); 1968 1969 for (drive = 0; drive < 2; drive++) { 1970 drvp = &chp->ch_drive[drive]; 1971 /* If no drive, skip */ 1972 if ((drvp->drive_flags & DRIVE) == 0) 1973 continue; 1974 /* add timing values, setup DMA if needed */ 1975 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1976 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1977 mode = drvp->PIO_mode; 1978 goto pio; 1979 } 1980 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1981 (drvp->drive_flags & DRIVE_UDMA)) { 1982 /* use Ultra/DMA */ 1983 drvp->drive_flags &= ~DRIVE_DMA; 1984 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1985 APO_UDMA_EN_MTH(chp->channel, drive) | 1986 APO_UDMA_TIME(chp->channel, drive, 1987 apollo_udma_tim[drvp->UDMA_mode]); 1988 /* can use PIO timings, MW DMA unused */ 1989 mode = drvp->PIO_mode; 1990 } else { 1991 /* use Multiword DMA */ 1992 drvp->drive_flags &= ~DRIVE_UDMA; 1993 /* mode = min(pio, dma+2) */ 1994 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1995 mode = drvp->PIO_mode; 1996 else 1997 mode = drvp->DMA_mode + 2; 1998 } 1999 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2000 2001 pio: /* setup PIO mode */ 2002 if (mode <= 2) { 2003 drvp->DMA_mode = 0; 2004 drvp->PIO_mode = 0; 2005 mode = 0; 2006 } else { 2007 drvp->PIO_mode = mode; 2008 drvp->DMA_mode = mode - 2; 2009 } 2010 datatim_reg |= 2011 APO_DATATIM_PULSE(chp->channel, drive, 2012 apollo_pio_set[mode]) | 2013 APO_DATATIM_RECOV(chp->channel, drive, 2014 apollo_pio_rec[mode]); 2015 } 2016 if (idedma_ctl != 0) { 2017 /* Add software bits in status register */ 2018 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2019 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2020 idedma_ctl); 2021 } 2022 pciide_print_modes(cp); 2023 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2024 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2025 } 2026 2027 void 2028 cmd_channel_map(pa, sc, channel) 2029 struct pci_attach_args *pa; 2030 struct pciide_softc *sc; 2031 int channel; 2032 { 2033 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2034 bus_size_t cmdsize, ctlsize; 2035 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2036 int interface; 2037 2038 /* 2039 * The 0648/0649 can be told to identify as a RAID controller. 2040 * In this case, we have to fake interface 2041 */ 2042 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2043 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2044 PCIIDE_INTERFACE_SETTABLE(1); 2045 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2046 CMD_CONF_DSA1) 2047 interface |= PCIIDE_INTERFACE_PCI(0) | 2048 PCIIDE_INTERFACE_PCI(1); 2049 } else { 2050 interface = PCI_INTERFACE(pa->pa_class); 2051 } 2052 2053 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2054 cp->name = PCIIDE_CHANNEL_NAME(channel); 2055 cp->wdc_channel.channel = channel; 2056 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2057 2058 if (channel > 0) { 2059 cp->wdc_channel.ch_queue = 2060 sc->pciide_channels[0].wdc_channel.ch_queue; 2061 } else { 2062 cp->wdc_channel.ch_queue = 2063 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2064 } 2065 if (cp->wdc_channel.ch_queue == NULL) { 2066 printf("%s %s channel: " 2067 "can't allocate memory for command queue", 2068 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2069 return; 2070 } 2071 2072 printf("%s: %s channel %s to %s mode\n", 2073 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2074 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2075 "configured" : "wired", 2076 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2077 "native-PCI" : "compatibility"); 2078 2079 /* 2080 * with a CMD PCI64x, if we get here, the first channel is enabled: 2081 * there's no way to disable the first channel without disabling 2082 * the whole device 2083 */ 2084 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2085 printf("%s: %s channel ignored (disabled)\n", 2086 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2087 return; 2088 } 2089 2090 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2091 if (cp->hw_ok == 0) 2092 return; 2093 if (channel == 1) { 2094 if (pciide_chan_candisable(cp)) { 2095 ctrl &= ~CMD_CTRL_2PORT; 2096 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2097 CMD_CTRL, ctrl); 2098 } 2099 } 2100 pciide_map_compat_intr(pa, cp, channel, interface); 2101 } 2102 2103 int 2104 cmd_pci_intr(arg) 2105 void *arg; 2106 { 2107 struct pciide_softc *sc = arg; 2108 struct pciide_channel *cp; 2109 struct channel_softc *wdc_cp; 2110 int i, rv, crv; 2111 u_int32_t priirq, secirq; 2112 2113 rv = 0; 2114 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2115 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2116 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2117 cp = &sc->pciide_channels[i]; 2118 wdc_cp = &cp->wdc_channel; 2119 /* If a compat channel skip. */ 2120 if (cp->compat) 2121 continue; 2122 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2123 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2124 crv = wdcintr(wdc_cp); 2125 if (crv == 0) 2126 printf("%s:%d: bogus intr\n", 2127 sc->sc_wdcdev.sc_dev.dv_xname, i); 2128 else 2129 rv = 1; 2130 } 2131 } 2132 return rv; 2133 } 2134 2135 void 2136 cmd_chip_map(sc, pa) 2137 struct pciide_softc *sc; 2138 struct pci_attach_args *pa; 2139 { 2140 int channel; 2141 2142 /* 2143 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2144 * and base adresses registers can be disabled at 2145 * hardware level. In this case, the device is wired 2146 * in compat mode and its first channel is always enabled, 2147 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2148 * In fact, it seems that the first channel of the CMD PCI0640 2149 * can't be disabled. 2150 */ 2151 2152 #ifdef PCIIDE_CMD064x_DISABLE 2153 if (pciide_chipen(sc, pa) == 0) 2154 return; 2155 #endif 2156 2157 printf("%s: hardware does not support DMA\n", 2158 sc->sc_wdcdev.sc_dev.dv_xname); 2159 sc->sc_dma_ok = 0; 2160 2161 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2162 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2163 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2164 2165 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2166 cmd_channel_map(pa, sc, channel); 2167 } 2168 } 2169 2170 void 2171 cmd0643_9_chip_map(sc, pa) 2172 struct pciide_softc *sc; 2173 struct pci_attach_args *pa; 2174 { 2175 struct pciide_channel *cp; 2176 int channel; 2177 int rev = PCI_REVISION( 2178 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2179 2180 /* 2181 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2182 * and base adresses registers can be disabled at 2183 * hardware level. In this case, the device is wired 2184 * in compat mode and its first channel is always enabled, 2185 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2186 * In fact, it seems that the first channel of the CMD PCI0640 2187 * can't be disabled. 2188 */ 2189 2190 #ifdef PCIIDE_CMD064x_DISABLE 2191 if (pciide_chipen(sc, pa) == 0) 2192 return; 2193 #endif 2194 printf("%s: bus-master DMA support present", 2195 sc->sc_wdcdev.sc_dev.dv_xname); 2196 pciide_mapreg_dma(sc, pa); 2197 printf("\n"); 2198 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2199 WDC_CAPABILITY_MODE; 2200 if (sc->sc_dma_ok) { 2201 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2202 switch (sc->sc_pp->ide_product) { 2203 case PCI_PRODUCT_CMDTECH_649: 2204 case PCI_PRODUCT_CMDTECH_648: 2205 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2206 sc->sc_wdcdev.UDMA_cap = 4; 2207 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2208 break; 2209 case PCI_PRODUCT_CMDTECH_646: 2210 if (rev >= CMD0646U2_REV) { 2211 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2212 sc->sc_wdcdev.UDMA_cap = 2; 2213 } else if (rev >= CMD0646U_REV) { 2214 /* 2215 * Linux's driver claims that the 646U is broken 2216 * with UDMA. Only enable it if we know what we're 2217 * doing 2218 */ 2219 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2220 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2221 sc->sc_wdcdev.UDMA_cap = 2; 2222 #endif 2223 /* explicitely disable UDMA */ 2224 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2225 CMD_UDMATIM(0), 0); 2226 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2227 CMD_UDMATIM(1), 0); 2228 } 2229 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2230 break; 2231 default: 2232 sc->sc_wdcdev.irqack = pciide_irqack; 2233 } 2234 } 2235 2236 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2237 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2238 sc->sc_wdcdev.PIO_cap = 4; 2239 sc->sc_wdcdev.DMA_cap = 2; 2240 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2241 2242 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2243 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2244 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2245 DEBUG_PROBE); 2246 2247 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2248 cp = &sc->pciide_channels[channel]; 2249 cmd_channel_map(pa, sc, channel); 2250 if (cp->hw_ok == 0) 2251 continue; 2252 cmd0643_9_setup_channel(&cp->wdc_channel); 2253 } 2254 /* 2255 * note - this also makes sure we clear the irq disable and reset 2256 * bits 2257 */ 2258 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2259 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2260 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2261 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2262 DEBUG_PROBE); 2263 } 2264 2265 void 2266 cmd0643_9_setup_channel(chp) 2267 struct channel_softc *chp; 2268 { 2269 struct ata_drive_datas *drvp; 2270 u_int8_t tim; 2271 u_int32_t idedma_ctl, udma_reg; 2272 int drive; 2273 struct pciide_channel *cp = (struct pciide_channel*)chp; 2274 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2275 2276 idedma_ctl = 0; 2277 /* setup DMA if needed */ 2278 pciide_channel_dma_setup(cp); 2279 2280 for (drive = 0; drive < 2; drive++) { 2281 drvp = &chp->ch_drive[drive]; 2282 /* If no drive, skip */ 2283 if ((drvp->drive_flags & DRIVE) == 0) 2284 continue; 2285 /* add timing values, setup DMA if needed */ 2286 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2287 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2288 if (drvp->drive_flags & DRIVE_UDMA) { 2289 /* UltraDMA on a 646U2, 0648 or 0649 */ 2290 udma_reg = pciide_pci_read(sc->sc_pc, 2291 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2292 if (drvp->UDMA_mode > 2 && 2293 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2294 CMD_BICSR) & 2295 CMD_BICSR_80(chp->channel)) == 0) 2296 drvp->UDMA_mode = 2; 2297 if (drvp->UDMA_mode > 2) 2298 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2299 else if (sc->sc_wdcdev.UDMA_cap > 2) 2300 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2301 udma_reg |= CMD_UDMATIM_UDMA(drive); 2302 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2303 CMD_UDMATIM_TIM_OFF(drive)); 2304 udma_reg |= 2305 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2306 CMD_UDMATIM_TIM_OFF(drive)); 2307 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2308 CMD_UDMATIM(chp->channel), udma_reg); 2309 } else { 2310 /* 2311 * use Multiword DMA. 2312 * Timings will be used for both PIO and DMA, 2313 * so adjust DMA mode if needed 2314 * if we have a 0646U2/8/9, turn off UDMA 2315 */ 2316 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2317 udma_reg = pciide_pci_read(sc->sc_pc, 2318 sc->sc_tag, 2319 CMD_UDMATIM(chp->channel)); 2320 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2321 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2322 CMD_UDMATIM(chp->channel), 2323 udma_reg); 2324 } 2325 if (drvp->PIO_mode >= 3 && 2326 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2327 drvp->DMA_mode = drvp->PIO_mode - 2; 2328 } 2329 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2330 } 2331 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2332 } 2333 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2334 CMD_DATA_TIM(chp->channel, drive), tim); 2335 } 2336 if (idedma_ctl != 0) { 2337 /* Add software bits in status register */ 2338 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2339 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2340 idedma_ctl); 2341 } 2342 pciide_print_modes(cp); 2343 } 2344 2345 void 2346 cmd646_9_irqack(chp) 2347 struct channel_softc *chp; 2348 { 2349 u_int32_t priirq, secirq; 2350 struct pciide_channel *cp = (struct pciide_channel*)chp; 2351 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2352 2353 if (chp->channel == 0) { 2354 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2355 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2356 } else { 2357 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2358 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2359 } 2360 pciide_irqack(chp); 2361 } 2362 2363 void 2364 cy693_chip_map(sc, pa) 2365 struct pciide_softc *sc; 2366 struct pci_attach_args *pa; 2367 { 2368 struct pciide_channel *cp; 2369 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2370 bus_size_t cmdsize, ctlsize; 2371 2372 if (pciide_chipen(sc, pa) == 0) 2373 return; 2374 /* 2375 * this chip has 2 PCI IDE functions, one for primary and one for 2376 * secondary. So we need to call pciide_mapregs_compat() with 2377 * the real channel 2378 */ 2379 if (pa->pa_function == 1) { 2380 sc->sc_cy_compatchan = 0; 2381 } else if (pa->pa_function == 2) { 2382 sc->sc_cy_compatchan = 1; 2383 } else { 2384 printf("%s: unexpected PCI function %d\n", 2385 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2386 return; 2387 } 2388 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2389 printf("%s: bus-master DMA support present", 2390 sc->sc_wdcdev.sc_dev.dv_xname); 2391 pciide_mapreg_dma(sc, pa); 2392 } else { 2393 printf("%s: hardware does not support DMA", 2394 sc->sc_wdcdev.sc_dev.dv_xname); 2395 sc->sc_dma_ok = 0; 2396 } 2397 printf("\n"); 2398 2399 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2400 if (sc->sc_cy_handle == NULL) { 2401 printf("%s: unable to map hyperCache control registers\n", 2402 sc->sc_wdcdev.sc_dev.dv_xname); 2403 sc->sc_dma_ok = 0; 2404 } 2405 2406 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2407 WDC_CAPABILITY_MODE; 2408 if (sc->sc_dma_ok) { 2409 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2410 sc->sc_wdcdev.irqack = pciide_irqack; 2411 } 2412 sc->sc_wdcdev.PIO_cap = 4; 2413 sc->sc_wdcdev.DMA_cap = 2; 2414 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2415 2416 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2417 sc->sc_wdcdev.nchannels = 1; 2418 2419 /* Only one channel for this chip; if we are here it's enabled */ 2420 cp = &sc->pciide_channels[0]; 2421 sc->wdc_chanarray[0] = &cp->wdc_channel; 2422 cp->name = PCIIDE_CHANNEL_NAME(0); 2423 cp->wdc_channel.channel = 0; 2424 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2425 cp->wdc_channel.ch_queue = 2426 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2427 if (cp->wdc_channel.ch_queue == NULL) { 2428 printf("%s primary channel: " 2429 "can't allocate memory for command queue", 2430 sc->sc_wdcdev.sc_dev.dv_xname); 2431 return; 2432 } 2433 printf("%s: primary channel %s to ", 2434 sc->sc_wdcdev.sc_dev.dv_xname, 2435 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2436 "configured" : "wired"); 2437 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2438 printf("native-PCI"); 2439 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2440 pciide_pci_intr); 2441 } else { 2442 printf("compatibility"); 2443 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2444 &cmdsize, &ctlsize); 2445 } 2446 printf(" mode\n"); 2447 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2448 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2449 wdcattach(&cp->wdc_channel); 2450 if (pciide_chan_candisable(cp)) { 2451 pci_conf_write(sc->sc_pc, sc->sc_tag, 2452 PCI_COMMAND_STATUS_REG, 0); 2453 } 2454 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2455 if (cp->hw_ok == 0) 2456 return; 2457 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2458 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2459 cy693_setup_channel(&cp->wdc_channel); 2460 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2461 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2462 } 2463 2464 void 2465 cy693_setup_channel(chp) 2466 struct channel_softc *chp; 2467 { 2468 struct ata_drive_datas *drvp; 2469 int drive; 2470 u_int32_t cy_cmd_ctrl; 2471 u_int32_t idedma_ctl; 2472 struct pciide_channel *cp = (struct pciide_channel*)chp; 2473 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2474 int dma_mode = -1; 2475 2476 cy_cmd_ctrl = idedma_ctl = 0; 2477 2478 /* setup DMA if needed */ 2479 pciide_channel_dma_setup(cp); 2480 2481 for (drive = 0; drive < 2; drive++) { 2482 drvp = &chp->ch_drive[drive]; 2483 /* If no drive, skip */ 2484 if ((drvp->drive_flags & DRIVE) == 0) 2485 continue; 2486 /* add timing values, setup DMA if needed */ 2487 if (drvp->drive_flags & DRIVE_DMA) { 2488 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2489 /* use Multiword DMA */ 2490 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2491 dma_mode = drvp->DMA_mode; 2492 } 2493 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2494 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2495 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2496 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2497 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2498 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2499 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2500 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2501 } 2502 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2503 chp->ch_drive[0].DMA_mode = dma_mode; 2504 chp->ch_drive[1].DMA_mode = dma_mode; 2505 2506 if (dma_mode == -1) 2507 dma_mode = 0; 2508 2509 if (sc->sc_cy_handle != NULL) { 2510 /* Note: `multiple' is implied. */ 2511 cy82c693_write(sc->sc_cy_handle, 2512 (sc->sc_cy_compatchan == 0) ? 2513 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2514 } 2515 2516 pciide_print_modes(cp); 2517 2518 if (idedma_ctl != 0) { 2519 /* Add software bits in status register */ 2520 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2521 IDEDMA_CTL, idedma_ctl); 2522 } 2523 } 2524 2525 void 2526 sis_chip_map(sc, pa) 2527 struct pciide_softc *sc; 2528 struct pci_attach_args *pa; 2529 { 2530 struct pciide_channel *cp; 2531 int channel; 2532 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2533 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2534 pcireg_t rev = PCI_REVISION(pa->pa_class); 2535 bus_size_t cmdsize, ctlsize; 2536 2537 if (pciide_chipen(sc, pa) == 0) 2538 return; 2539 printf("%s: bus-master DMA support present", 2540 sc->sc_wdcdev.sc_dev.dv_xname); 2541 pciide_mapreg_dma(sc, pa); 2542 printf("\n"); 2543 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2544 WDC_CAPABILITY_MODE; 2545 if (sc->sc_dma_ok) { 2546 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2547 sc->sc_wdcdev.irqack = pciide_irqack; 2548 if (rev >= 0xd0) 2549 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2550 } 2551 2552 sc->sc_wdcdev.PIO_cap = 4; 2553 sc->sc_wdcdev.DMA_cap = 2; 2554 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2555 sc->sc_wdcdev.UDMA_cap = 2; 2556 sc->sc_wdcdev.set_modes = sis_setup_channel; 2557 2558 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2559 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2560 2561 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2562 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2563 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2564 2565 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2566 cp = &sc->pciide_channels[channel]; 2567 if (pciide_chansetup(sc, channel, interface) == 0) 2568 continue; 2569 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2570 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2571 printf("%s: %s channel ignored (disabled)\n", 2572 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2573 continue; 2574 } 2575 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2576 pciide_pci_intr); 2577 if (cp->hw_ok == 0) 2578 continue; 2579 if (pciide_chan_candisable(cp)) { 2580 if (channel == 0) 2581 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2582 else 2583 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2584 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2585 sis_ctr0); 2586 } 2587 pciide_map_compat_intr(pa, cp, channel, interface); 2588 if (cp->hw_ok == 0) 2589 continue; 2590 sis_setup_channel(&cp->wdc_channel); 2591 } 2592 } 2593 2594 void 2595 sis_setup_channel(chp) 2596 struct channel_softc *chp; 2597 { 2598 struct ata_drive_datas *drvp; 2599 int drive; 2600 u_int32_t sis_tim; 2601 u_int32_t idedma_ctl; 2602 struct pciide_channel *cp = (struct pciide_channel*)chp; 2603 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2604 2605 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2606 "channel %d 0x%x\n", chp->channel, 2607 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2608 DEBUG_PROBE); 2609 sis_tim = 0; 2610 idedma_ctl = 0; 2611 /* setup DMA if needed */ 2612 pciide_channel_dma_setup(cp); 2613 2614 for (drive = 0; drive < 2; drive++) { 2615 drvp = &chp->ch_drive[drive]; 2616 /* If no drive, skip */ 2617 if ((drvp->drive_flags & DRIVE) == 0) 2618 continue; 2619 /* add timing values, setup DMA if needed */ 2620 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2621 (drvp->drive_flags & DRIVE_UDMA) == 0) 2622 goto pio; 2623 2624 if (drvp->drive_flags & DRIVE_UDMA) { 2625 /* use Ultra/DMA */ 2626 drvp->drive_flags &= ~DRIVE_DMA; 2627 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2628 SIS_TIM_UDMA_TIME_OFF(drive); 2629 sis_tim |= SIS_TIM_UDMA_EN(drive); 2630 } else { 2631 /* 2632 * use Multiword DMA 2633 * Timings will be used for both PIO and DMA, 2634 * so adjust DMA mode if needed 2635 */ 2636 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2637 drvp->PIO_mode = drvp->DMA_mode + 2; 2638 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2639 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2640 drvp->PIO_mode - 2 : 0; 2641 if (drvp->DMA_mode == 0) 2642 drvp->PIO_mode = 0; 2643 } 2644 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2645 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2646 SIS_TIM_ACT_OFF(drive); 2647 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2648 SIS_TIM_REC_OFF(drive); 2649 } 2650 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2651 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2652 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2653 if (idedma_ctl != 0) { 2654 /* Add software bits in status register */ 2655 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2656 IDEDMA_CTL, idedma_ctl); 2657 } 2658 pciide_print_modes(cp); 2659 } 2660 2661 void 2662 acer_chip_map(sc, pa) 2663 struct pciide_softc *sc; 2664 struct pci_attach_args *pa; 2665 { 2666 struct pciide_channel *cp; 2667 int channel; 2668 pcireg_t cr, interface; 2669 bus_size_t cmdsize, ctlsize; 2670 2671 if (pciide_chipen(sc, pa) == 0) 2672 return; 2673 printf("%s: bus-master DMA support present", 2674 sc->sc_wdcdev.sc_dev.dv_xname); 2675 pciide_mapreg_dma(sc, pa); 2676 printf("\n"); 2677 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2678 WDC_CAPABILITY_MODE; 2679 if (sc->sc_dma_ok) { 2680 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2681 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2682 sc->sc_wdcdev.irqack = pciide_irqack; 2683 } 2684 2685 sc->sc_wdcdev.PIO_cap = 4; 2686 sc->sc_wdcdev.DMA_cap = 2; 2687 sc->sc_wdcdev.UDMA_cap = 2; 2688 sc->sc_wdcdev.set_modes = acer_setup_channel; 2689 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2690 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2691 2692 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2693 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2694 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2695 2696 /* Enable "microsoft register bits" R/W. */ 2697 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2698 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2699 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2700 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2701 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2702 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2703 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2704 ~ACER_CHANSTATUSREGS_RO); 2705 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2706 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2707 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2708 /* Don't use cr, re-read the real register content instead */ 2709 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2710 PCI_CLASS_REG)); 2711 2712 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2713 cp = &sc->pciide_channels[channel]; 2714 if (pciide_chansetup(sc, channel, interface) == 0) 2715 continue; 2716 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2717 printf("%s: %s channel ignored (disabled)\n", 2718 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2719 continue; 2720 } 2721 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2722 acer_pci_intr); 2723 if (cp->hw_ok == 0) 2724 continue; 2725 if (pciide_chan_candisable(cp)) { 2726 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2727 pci_conf_write(sc->sc_pc, sc->sc_tag, 2728 PCI_CLASS_REG, cr); 2729 } 2730 pciide_map_compat_intr(pa, cp, channel, interface); 2731 acer_setup_channel(&cp->wdc_channel); 2732 } 2733 } 2734 2735 void 2736 acer_setup_channel(chp) 2737 struct channel_softc *chp; 2738 { 2739 struct ata_drive_datas *drvp; 2740 int drive; 2741 u_int32_t acer_fifo_udma; 2742 u_int32_t idedma_ctl; 2743 struct pciide_channel *cp = (struct pciide_channel*)chp; 2744 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2745 2746 idedma_ctl = 0; 2747 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2748 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2749 acer_fifo_udma), DEBUG_PROBE); 2750 /* setup DMA if needed */ 2751 pciide_channel_dma_setup(cp); 2752 2753 for (drive = 0; drive < 2; drive++) { 2754 drvp = &chp->ch_drive[drive]; 2755 /* If no drive, skip */ 2756 if ((drvp->drive_flags & DRIVE) == 0) 2757 continue; 2758 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2759 "channel %d drive %d 0x%x\n", chp->channel, drive, 2760 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2761 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2762 /* clear FIFO/DMA mode */ 2763 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2764 ACER_UDMA_EN(chp->channel, drive) | 2765 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2766 2767 /* add timing values, setup DMA if needed */ 2768 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2769 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2770 acer_fifo_udma |= 2771 ACER_FTH_OPL(chp->channel, drive, 0x1); 2772 goto pio; 2773 } 2774 2775 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2776 if (drvp->drive_flags & DRIVE_UDMA) { 2777 /* use Ultra/DMA */ 2778 drvp->drive_flags &= ~DRIVE_DMA; 2779 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2780 acer_fifo_udma |= 2781 ACER_UDMA_TIM(chp->channel, drive, 2782 acer_udma[drvp->UDMA_mode]); 2783 } else { 2784 /* 2785 * use Multiword DMA 2786 * Timings will be used for both PIO and DMA, 2787 * so adjust DMA mode if needed 2788 */ 2789 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2790 drvp->PIO_mode = drvp->DMA_mode + 2; 2791 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2792 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2793 drvp->PIO_mode - 2 : 0; 2794 if (drvp->DMA_mode == 0) 2795 drvp->PIO_mode = 0; 2796 } 2797 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2798 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2799 ACER_IDETIM(chp->channel, drive), 2800 acer_pio[drvp->PIO_mode]); 2801 } 2802 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2803 acer_fifo_udma), DEBUG_PROBE); 2804 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2805 if (idedma_ctl != 0) { 2806 /* Add software bits in status register */ 2807 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2808 IDEDMA_CTL, idedma_ctl); 2809 } 2810 pciide_print_modes(cp); 2811 } 2812 2813 int 2814 acer_pci_intr(arg) 2815 void *arg; 2816 { 2817 struct pciide_softc *sc = arg; 2818 struct pciide_channel *cp; 2819 struct channel_softc *wdc_cp; 2820 int i, rv, crv; 2821 u_int32_t chids; 2822 2823 rv = 0; 2824 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2825 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2826 cp = &sc->pciide_channels[i]; 2827 wdc_cp = &cp->wdc_channel; 2828 /* If a compat channel skip. */ 2829 if (cp->compat) 2830 continue; 2831 if (chids & ACER_CHIDS_INT(i)) { 2832 crv = wdcintr(wdc_cp); 2833 if (crv == 0) 2834 printf("%s:%d: bogus intr\n", 2835 sc->sc_wdcdev.sc_dev.dv_xname, i); 2836 else 2837 rv = 1; 2838 } 2839 } 2840 return rv; 2841 } 2842 2843 void 2844 hpt_chip_map(sc, pa) 2845 struct pciide_softc *sc; 2846 struct pci_attach_args *pa; 2847 { 2848 struct pciide_channel *cp; 2849 int i, compatchan, revision; 2850 pcireg_t interface; 2851 bus_size_t cmdsize, ctlsize; 2852 2853 if (pciide_chipen(sc, pa) == 0) 2854 return; 2855 revision = PCI_REVISION(pa->pa_class); 2856 2857 /* 2858 * when the chip is in native mode it identifies itself as a 2859 * 'misc mass storage'. Fake interface in this case. 2860 */ 2861 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2862 interface = PCI_INTERFACE(pa->pa_class); 2863 } else { 2864 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2865 PCIIDE_INTERFACE_PCI(0); 2866 if (revision == HPT370_REV) 2867 interface |= PCIIDE_INTERFACE_PCI(1); 2868 } 2869 2870 printf("%s: bus-master DMA support present", 2871 sc->sc_wdcdev.sc_dev.dv_xname); 2872 pciide_mapreg_dma(sc, pa); 2873 printf("\n"); 2874 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2875 WDC_CAPABILITY_MODE; 2876 if (sc->sc_dma_ok) { 2877 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2878 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2879 sc->sc_wdcdev.irqack = pciide_irqack; 2880 } 2881 sc->sc_wdcdev.PIO_cap = 4; 2882 sc->sc_wdcdev.DMA_cap = 2; 2883 sc->sc_wdcdev.UDMA_cap = 4; 2884 2885 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2886 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2887 if (revision == HPT366_REV) { 2888 /* 2889 * The 366 has 2 PCI IDE functions, one for primary and one 2890 * for secondary. So we need to call pciide_mapregs_compat() 2891 * with the real channel 2892 */ 2893 if (pa->pa_function == 0) { 2894 compatchan = 0; 2895 } else if (pa->pa_function == 1) { 2896 compatchan = 1; 2897 } else { 2898 printf("%s: unexpected PCI function %d\n", 2899 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2900 return; 2901 } 2902 sc->sc_wdcdev.nchannels = 1; 2903 } else { 2904 sc->sc_wdcdev.nchannels = 2; 2905 } 2906 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2907 cp = &sc->pciide_channels[i]; 2908 if (sc->sc_wdcdev.nchannels > 1) { 2909 compatchan = i; 2910 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2911 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2912 printf("%s: %s channel ignored (disabled)\n", 2913 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2914 continue; 2915 } 2916 } 2917 if (pciide_chansetup(sc, i, interface) == 0) 2918 continue; 2919 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2920 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2921 &ctlsize, hpt_pci_intr); 2922 } else { 2923 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2924 &cmdsize, &ctlsize); 2925 } 2926 if (cp->hw_ok == 0) 2927 return; 2928 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2929 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2930 wdcattach(&cp->wdc_channel); 2931 hpt_setup_channel(&cp->wdc_channel); 2932 } 2933 if (revision == HPT370_REV) { 2934 /* 2935 * HPT370_REV has a bit to disable interrupts, make sure 2936 * to clear it 2937 */ 2938 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 2939 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 2940 ~HPT_CSEL_IRQDIS); 2941 } 2942 return; 2943 } 2944 2945 2946 void 2947 hpt_setup_channel(chp) 2948 struct channel_softc *chp; 2949 { 2950 struct ata_drive_datas *drvp; 2951 int drive; 2952 int cable; 2953 u_int32_t before, after; 2954 u_int32_t idedma_ctl; 2955 struct pciide_channel *cp = (struct pciide_channel*)chp; 2956 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2957 2958 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 2959 2960 /* setup DMA if needed */ 2961 pciide_channel_dma_setup(cp); 2962 2963 idedma_ctl = 0; 2964 2965 /* Per drive settings */ 2966 for (drive = 0; drive < 2; drive++) { 2967 drvp = &chp->ch_drive[drive]; 2968 /* If no drive, skip */ 2969 if ((drvp->drive_flags & DRIVE) == 0) 2970 continue; 2971 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 2972 HPT_IDETIM(chp->channel, drive)); 2973 2974 /* add timing values, setup DMA if needed */ 2975 if (drvp->drive_flags & DRIVE_UDMA) { 2976 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 2977 drvp->UDMA_mode > 2) 2978 drvp->UDMA_mode = 2; 2979 after = (sc->sc_wdcdev.nchannels == 2) ? 2980 hpt370_udma[drvp->UDMA_mode] : 2981 hpt366_udma[drvp->UDMA_mode]; 2982 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2983 } else if (drvp->drive_flags & DRIVE_DMA) { 2984 /* 2985 * use Multiword DMA. 2986 * Timings will be used for both PIO and DMA, so adjust 2987 * DMA mode if needed 2988 */ 2989 if (drvp->PIO_mode >= 3 && 2990 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2991 drvp->DMA_mode = drvp->PIO_mode - 2; 2992 } 2993 after = (sc->sc_wdcdev.nchannels == 2) ? 2994 hpt370_dma[drvp->DMA_mode] : 2995 hpt366_dma[drvp->DMA_mode]; 2996 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2997 } else { 2998 /* PIO only */ 2999 after = (sc->sc_wdcdev.nchannels == 2) ? 3000 hpt370_pio[drvp->PIO_mode] : 3001 hpt366_pio[drvp->PIO_mode]; 3002 } 3003 pci_conf_write(sc->sc_pc, sc->sc_tag, 3004 HPT_IDETIM(chp->channel, drive), after); 3005 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3006 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3007 after, before), DEBUG_PROBE); 3008 } 3009 if (idedma_ctl != 0) { 3010 /* Add software bits in status register */ 3011 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3012 IDEDMA_CTL, idedma_ctl); 3013 } 3014 pciide_print_modes(cp); 3015 } 3016 3017 int 3018 hpt_pci_intr(arg) 3019 void *arg; 3020 { 3021 struct pciide_softc *sc = arg; 3022 struct pciide_channel *cp; 3023 struct channel_softc *wdc_cp; 3024 int rv = 0; 3025 int dmastat, i, crv; 3026 3027 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3028 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3029 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3030 if((dmastat & IDEDMA_CTL_INTR) == 0) 3031 continue; 3032 cp = &sc->pciide_channels[i]; 3033 wdc_cp = &cp->wdc_channel; 3034 crv = wdcintr(wdc_cp); 3035 if (crv == 0) { 3036 printf("%s:%d: bogus intr\n", 3037 sc->sc_wdcdev.sc_dev.dv_xname, i); 3038 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3039 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3040 } else 3041 rv = 1; 3042 } 3043 return rv; 3044 } 3045 3046 3047 /* A macro to test product */ 3048 #define PDC_IS_262(sc) \ 3049 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3050 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3051 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3052 3053 void 3054 pdc202xx_chip_map(sc, pa) 3055 struct pciide_softc *sc; 3056 struct pci_attach_args *pa; 3057 { 3058 struct pciide_channel *cp; 3059 int channel; 3060 pcireg_t interface, st, mode; 3061 bus_size_t cmdsize, ctlsize; 3062 3063 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3064 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3065 DEBUG_PROBE); 3066 if (pciide_chipen(sc, pa) == 0) 3067 return; 3068 3069 /* turn off RAID mode */ 3070 st &= ~PDC2xx_STATE_IDERAID; 3071 3072 /* 3073 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3074 * mode. We have to fake interface 3075 */ 3076 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3077 if (st & PDC2xx_STATE_NATIVE) 3078 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3079 3080 printf("%s: bus-master DMA support present", 3081 sc->sc_wdcdev.sc_dev.dv_xname); 3082 pciide_mapreg_dma(sc, pa); 3083 printf("\n"); 3084 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3085 WDC_CAPABILITY_MODE; 3086 if (sc->sc_dma_ok) { 3087 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3088 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3089 sc->sc_wdcdev.irqack = pciide_irqack; 3090 } 3091 sc->sc_wdcdev.PIO_cap = 4; 3092 sc->sc_wdcdev.DMA_cap = 2; 3093 if (PDC_IS_262(sc)) 3094 sc->sc_wdcdev.UDMA_cap = 4; 3095 else 3096 sc->sc_wdcdev.UDMA_cap = 2; 3097 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3098 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3099 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3100 3101 /* setup failsafe defaults */ 3102 mode = 0; 3103 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3104 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3105 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3106 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3107 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3108 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3109 "initial timings 0x%x, now 0x%x\n", channel, 3110 pci_conf_read(sc->sc_pc, sc->sc_tag, 3111 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3112 DEBUG_PROBE); 3113 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3114 mode | PDC2xx_TIM_IORDYp); 3115 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3116 "initial timings 0x%x, now 0x%x\n", channel, 3117 pci_conf_read(sc->sc_pc, sc->sc_tag, 3118 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3119 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3120 mode); 3121 } 3122 3123 mode = PDC2xx_SCR_DMA; 3124 if (PDC_IS_262(sc)) { 3125 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3126 } else { 3127 /* the BIOS set it up this way */ 3128 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3129 } 3130 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3131 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3132 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3133 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3134 DEBUG_PROBE); 3135 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3136 3137 /* controller initial state register is OK even without BIOS */ 3138 /* Set DMA mode to IDE DMA compatibility */ 3139 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3140 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3141 DEBUG_PROBE); 3142 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3143 mode | 0x1); 3144 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3145 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3146 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3147 mode | 0x1); 3148 3149 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3150 cp = &sc->pciide_channels[channel]; 3151 if (pciide_chansetup(sc, channel, interface) == 0) 3152 continue; 3153 if ((st & (PDC_IS_262(sc) ? 3154 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3155 printf("%s: %s channel ignored (disabled)\n", 3156 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3157 continue; 3158 } 3159 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3160 pdc202xx_pci_intr); 3161 if (cp->hw_ok == 0) 3162 continue; 3163 if (pciide_chan_candisable(cp)) 3164 st &= ~(PDC_IS_262(sc) ? 3165 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3166 pciide_map_compat_intr(pa, cp, channel, interface); 3167 pdc202xx_setup_channel(&cp->wdc_channel); 3168 } 3169 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3170 DEBUG_PROBE); 3171 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3172 return; 3173 } 3174 3175 void 3176 pdc202xx_setup_channel(chp) 3177 struct channel_softc *chp; 3178 { 3179 struct ata_drive_datas *drvp; 3180 int drive; 3181 pcireg_t mode, st; 3182 u_int32_t idedma_ctl, scr, atapi; 3183 struct pciide_channel *cp = (struct pciide_channel*)chp; 3184 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3185 int channel = chp->channel; 3186 3187 /* setup DMA if needed */ 3188 pciide_channel_dma_setup(cp); 3189 3190 idedma_ctl = 0; 3191 3192 /* Per channel settings */ 3193 if (PDC_IS_262(sc)) { 3194 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3195 PDC262_U66); 3196 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3197 /* Trimm UDMA mode */ 3198 if ((st & PDC262_STATE_80P(channel)) != 0 || 3199 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3200 chp->ch_drive[0].UDMA_mode <= 2) || 3201 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3202 chp->ch_drive[1].UDMA_mode <= 2)) { 3203 if (chp->ch_drive[0].UDMA_mode > 2) 3204 chp->ch_drive[0].UDMA_mode = 2; 3205 if (chp->ch_drive[1].UDMA_mode > 2) 3206 chp->ch_drive[1].UDMA_mode = 2; 3207 } 3208 /* Set U66 if needed */ 3209 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3210 chp->ch_drive[0].UDMA_mode > 2) || 3211 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3212 chp->ch_drive[1].UDMA_mode > 2)) 3213 scr |= PDC262_U66_EN(channel); 3214 else 3215 scr &= ~PDC262_U66_EN(channel); 3216 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3217 PDC262_U66, scr); 3218 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3219 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3220 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3221 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3222 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3223 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3224 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3225 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3226 atapi = 0; 3227 else 3228 atapi = PDC262_ATAPI_UDMA; 3229 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3230 PDC262_ATAPI(channel), atapi); 3231 } 3232 } 3233 for (drive = 0; drive < 2; drive++) { 3234 drvp = &chp->ch_drive[drive]; 3235 /* If no drive, skip */ 3236 if ((drvp->drive_flags & DRIVE) == 0) 3237 continue; 3238 mode = 0; 3239 if (drvp->drive_flags & DRIVE_UDMA) { 3240 mode = PDC2xx_TIM_SET_MB(mode, 3241 pdc2xx_udma_mb[drvp->UDMA_mode]); 3242 mode = PDC2xx_TIM_SET_MC(mode, 3243 pdc2xx_udma_mc[drvp->UDMA_mode]); 3244 drvp->drive_flags &= ~DRIVE_DMA; 3245 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3246 } else if (drvp->drive_flags & DRIVE_DMA) { 3247 mode = PDC2xx_TIM_SET_MB(mode, 3248 pdc2xx_dma_mb[drvp->DMA_mode]); 3249 mode = PDC2xx_TIM_SET_MC(mode, 3250 pdc2xx_dma_mc[drvp->DMA_mode]); 3251 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3252 } else { 3253 mode = PDC2xx_TIM_SET_MB(mode, 3254 pdc2xx_dma_mb[0]); 3255 mode = PDC2xx_TIM_SET_MC(mode, 3256 pdc2xx_dma_mc[0]); 3257 } 3258 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3259 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3260 if (drvp->drive_flags & DRIVE_ATA) 3261 mode |= PDC2xx_TIM_PRE; 3262 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3263 if (drvp->PIO_mode >= 3) { 3264 mode |= PDC2xx_TIM_IORDY; 3265 if (drive == 0) 3266 mode |= PDC2xx_TIM_IORDYp; 3267 } 3268 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3269 "timings 0x%x\n", 3270 sc->sc_wdcdev.sc_dev.dv_xname, 3271 chp->channel, drive, mode), DEBUG_PROBE); 3272 pci_conf_write(sc->sc_pc, sc->sc_tag, 3273 PDC2xx_TIM(chp->channel, drive), mode); 3274 } 3275 if (idedma_ctl != 0) { 3276 /* Add software bits in status register */ 3277 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3278 IDEDMA_CTL, idedma_ctl); 3279 } 3280 pciide_print_modes(cp); 3281 } 3282 3283 int 3284 pdc202xx_pci_intr(arg) 3285 void *arg; 3286 { 3287 struct pciide_softc *sc = arg; 3288 struct pciide_channel *cp; 3289 struct channel_softc *wdc_cp; 3290 int i, rv, crv; 3291 u_int32_t scr; 3292 3293 rv = 0; 3294 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3295 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3296 cp = &sc->pciide_channels[i]; 3297 wdc_cp = &cp->wdc_channel; 3298 /* If a compat channel skip. */ 3299 if (cp->compat) 3300 continue; 3301 if (scr & PDC2xx_SCR_INT(i)) { 3302 crv = wdcintr(wdc_cp); 3303 if (crv == 0) 3304 printf("%s:%d: bogus intr\n", 3305 sc->sc_wdcdev.sc_dev.dv_xname, i); 3306 else 3307 rv = 1; 3308 } 3309 } 3310 return rv; 3311 } 3312 3313 void 3314 opti_chip_map(sc, pa) 3315 struct pciide_softc *sc; 3316 struct pci_attach_args *pa; 3317 { 3318 struct pciide_channel *cp; 3319 bus_size_t cmdsize, ctlsize; 3320 pcireg_t interface; 3321 u_int8_t init_ctrl; 3322 int channel; 3323 3324 if (pciide_chipen(sc, pa) == 0) 3325 return; 3326 printf("%s: bus-master DMA support present", 3327 sc->sc_wdcdev.sc_dev.dv_xname); 3328 pciide_mapreg_dma(sc, pa); 3329 printf("\n"); 3330 3331 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3332 WDC_CAPABILITY_MODE; 3333 sc->sc_wdcdev.PIO_cap = 4; 3334 if (sc->sc_dma_ok) { 3335 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3336 sc->sc_wdcdev.irqack = pciide_irqack; 3337 sc->sc_wdcdev.DMA_cap = 2; 3338 } 3339 sc->sc_wdcdev.set_modes = opti_setup_channel; 3340 3341 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3342 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3343 3344 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3345 OPTI_REG_INIT_CONTROL); 3346 3347 interface = PCI_INTERFACE(pa->pa_class); 3348 3349 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3350 cp = &sc->pciide_channels[channel]; 3351 if (pciide_chansetup(sc, channel, interface) == 0) 3352 continue; 3353 if (channel == 1 && 3354 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3355 printf("%s: %s channel ignored (disabled)\n", 3356 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3357 continue; 3358 } 3359 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3360 pciide_pci_intr); 3361 if (cp->hw_ok == 0) 3362 continue; 3363 pciide_map_compat_intr(pa, cp, channel, interface); 3364 if (cp->hw_ok == 0) 3365 continue; 3366 opti_setup_channel(&cp->wdc_channel); 3367 } 3368 } 3369 3370 void 3371 opti_setup_channel(chp) 3372 struct channel_softc *chp; 3373 { 3374 struct ata_drive_datas *drvp; 3375 struct pciide_channel *cp = (struct pciide_channel*)chp; 3376 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3377 int drive, spd; 3378 int mode[2]; 3379 u_int8_t rv, mr; 3380 3381 /* 3382 * The `Delay' and `Address Setup Time' fields of the 3383 * Miscellaneous Register are always zero initially. 3384 */ 3385 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3386 mr &= ~(OPTI_MISC_DELAY_MASK | 3387 OPTI_MISC_ADDR_SETUP_MASK | 3388 OPTI_MISC_INDEX_MASK); 3389 3390 /* Prime the control register before setting timing values */ 3391 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3392 3393 /* Determine the clockrate of the PCIbus the chip is attached to */ 3394 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3395 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3396 3397 /* setup DMA if needed */ 3398 pciide_channel_dma_setup(cp); 3399 3400 for (drive = 0; drive < 2; drive++) { 3401 drvp = &chp->ch_drive[drive]; 3402 /* If no drive, skip */ 3403 if ((drvp->drive_flags & DRIVE) == 0) { 3404 mode[drive] = -1; 3405 continue; 3406 } 3407 3408 if ((drvp->drive_flags & DRIVE_DMA)) { 3409 /* 3410 * Timings will be used for both PIO and DMA, 3411 * so adjust DMA mode if needed 3412 */ 3413 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3414 drvp->PIO_mode = drvp->DMA_mode + 2; 3415 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3416 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3417 drvp->PIO_mode - 2 : 0; 3418 if (drvp->DMA_mode == 0) 3419 drvp->PIO_mode = 0; 3420 3421 mode[drive] = drvp->DMA_mode + 5; 3422 } else 3423 mode[drive] = drvp->PIO_mode; 3424 3425 if (drive && mode[0] >= 0 && 3426 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3427 /* 3428 * Can't have two drives using different values 3429 * for `Address Setup Time'. 3430 * Slow down the faster drive to compensate. 3431 */ 3432 int d = (opti_tim_as[spd][mode[0]] > 3433 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3434 3435 mode[d] = mode[1-d]; 3436 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3437 chp->ch_drive[d].DMA_mode = 0; 3438 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3439 } 3440 } 3441 3442 for (drive = 0; drive < 2; drive++) { 3443 int m; 3444 if ((m = mode[drive]) < 0) 3445 continue; 3446 3447 /* Set the Address Setup Time and select appropriate index */ 3448 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3449 rv |= OPTI_MISC_INDEX(drive); 3450 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3451 3452 /* Set the pulse width and recovery timing parameters */ 3453 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3454 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3455 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3456 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3457 3458 /* Set the Enhanced Mode register appropriately */ 3459 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3460 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3461 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3462 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3463 } 3464 3465 /* Finally, enable the timings */ 3466 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3467 3468 pciide_print_modes(cp); 3469 } 3470
Indexes created Tue Sep 23 02:09:52 GMT 2025