pciide.c revision 1.92
1 /* $NetBSD: pciide.c,v 1.92 2000/11/14 18:42:58 thorpej Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 */ 35 36 37 /* 38 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by Christopher G. Demetriou 51 * for the NetBSD Project. 52 * 4. The name of the author may not be used to endorse or promote products 53 * derived from this software without specific prior written permission 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 56 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 57 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 58 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 59 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 60 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 64 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67 /* 68 * PCI IDE controller driver. 69 * 70 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 71 * sys/dev/pci/ppb.c, revision 1.16). 72 * 73 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 74 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 75 * 5/16/94" from the PCI SIG. 76 * 77 */ 78 79 #ifndef WDCDEBUG 80 #define WDCDEBUG 81 #endif 82 83 #define DEBUG_DMA 0x01 84 #define DEBUG_XFERS 0x02 85 #define DEBUG_FUNCS 0x08 86 #define DEBUG_PROBE 0x10 87 #ifdef WDCDEBUG 88 int wdcdebug_pciide_mask = 0; 89 #define WDCDEBUG_PRINT(args, level) \ 90 if (wdcdebug_pciide_mask & (level)) printf args 91 #else 92 #define WDCDEBUG_PRINT(args, level) 93 #endif 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/device.h> 97 #include <sys/malloc.h> 98 99 #include <uvm/uvm_extern.h> 100 101 #include <machine/endian.h> 102 103 #include <dev/pci/pcireg.h> 104 #include <dev/pci/pcivar.h> 105 #include <dev/pci/pcidevs.h> 106 #include <dev/pci/pciidereg.h> 107 #include <dev/pci/pciidevar.h> 108 #include <dev/pci/pciide_piix_reg.h> 109 #include <dev/pci/pciide_amd_reg.h> 110 #include <dev/pci/pciide_apollo_reg.h> 111 #include <dev/pci/pciide_cmd_reg.h> 112 #include <dev/pci/pciide_cy693_reg.h> 113 #include <dev/pci/pciide_sis_reg.h> 114 #include <dev/pci/pciide_acer_reg.h> 115 #include <dev/pci/pciide_pdc202xx_reg.h> 116 #include <dev/pci/pciide_opti_reg.h> 117 #include <dev/pci/pciide_hpt_reg.h> 118 #include <dev/pci/cy82c693var.h> 119 120 #include "opt_pciide.h" 121 122 /* inlines for reading/writing 8-bit PCI registers */ 123 static __inline u_int8_t pciide_pci_read __P((pci_chipset_tag_t, pcitag_t, 124 int)); 125 static __inline void pciide_pci_write __P((pci_chipset_tag_t, pcitag_t, 126 int, u_int8_t)); 127 128 static __inline u_int8_t 129 pciide_pci_read(pc, pa, reg) 130 pci_chipset_tag_t pc; 131 pcitag_t pa; 132 int reg; 133 { 134 135 return (pci_conf_read(pc, pa, (reg & ~0x03)) >> 136 ((reg & 0x03) * 8) & 0xff); 137 } 138 139 static __inline void 140 pciide_pci_write(pc, pa, reg, val) 141 pci_chipset_tag_t pc; 142 pcitag_t pa; 143 int reg; 144 u_int8_t val; 145 { 146 pcireg_t pcival; 147 148 pcival = pci_conf_read(pc, pa, (reg & ~0x03)); 149 pcival &= ~(0xff << ((reg & 0x03) * 8)); 150 pcival |= (val << ((reg & 0x03) * 8)); 151 pci_conf_write(pc, pa, (reg & ~0x03), pcival); 152 } 153 154 void default_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 155 156 void piix_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 157 void piix_setup_channel __P((struct channel_softc*)); 158 void piix3_4_setup_channel __P((struct channel_softc*)); 159 static u_int32_t piix_setup_idetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 160 static u_int32_t piix_setup_idetim_drvs __P((struct ata_drive_datas*)); 161 static u_int32_t piix_setup_sidetim_timings __P((u_int8_t, u_int8_t, u_int8_t)); 162 163 void amd756_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 164 void amd756_setup_channel __P((struct channel_softc*)); 165 166 void apollo_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 167 void apollo_setup_channel __P((struct channel_softc*)); 168 169 void cmd_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 170 void cmd0643_9_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 171 void cmd0643_9_setup_channel __P((struct channel_softc*)); 172 void cmd_channel_map __P((struct pci_attach_args *, 173 struct pciide_softc *, int)); 174 int cmd_pci_intr __P((void *)); 175 void cmd646_9_irqack __P((struct channel_softc *)); 176 177 void cy693_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 178 void cy693_setup_channel __P((struct channel_softc*)); 179 180 void sis_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 181 void sis_setup_channel __P((struct channel_softc*)); 182 183 void acer_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 184 void acer_setup_channel __P((struct channel_softc*)); 185 int acer_pci_intr __P((void *)); 186 187 void pdc202xx_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 188 void pdc202xx_setup_channel __P((struct channel_softc*)); 189 int pdc202xx_pci_intr __P((void *)); 190 191 void opti_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 192 void opti_setup_channel __P((struct channel_softc*)); 193 194 void hpt_chip_map __P((struct pciide_softc*, struct pci_attach_args*)); 195 void hpt_setup_channel __P((struct channel_softc*)); 196 int hpt_pci_intr __P((void *)); 197 198 void pciide_channel_dma_setup __P((struct pciide_channel *)); 199 int pciide_dma_table_setup __P((struct pciide_softc*, int, int)); 200 int pciide_dma_init __P((void*, int, int, void *, size_t, int)); 201 void pciide_dma_start __P((void*, int, int)); 202 int pciide_dma_finish __P((void*, int, int, int)); 203 void pciide_irqack __P((struct channel_softc *)); 204 void pciide_print_modes __P((struct pciide_channel *)); 205 206 struct pciide_product_desc { 207 u_int32_t ide_product; 208 int ide_flags; 209 const char *ide_name; 210 /* map and setup chip, probe drives */ 211 void (*chip_map) __P((struct pciide_softc*, struct pci_attach_args*)); 212 }; 213 214 /* Flags for ide_flags */ 215 #define IDE_PCI_CLASS_OVERRIDE 0x0001 /* accept even if class != pciide */ 216 #define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */ 217 218 /* Default product description for devices not known from this controller */ 219 const struct pciide_product_desc default_product_desc = { 220 0, 221 0, 222 "Generic PCI IDE controller", 223 default_chip_map, 224 }; 225 226 const struct pciide_product_desc pciide_intel_products[] = { 227 { PCI_PRODUCT_INTEL_82092AA, 228 0, 229 "Intel 82092AA IDE controller", 230 default_chip_map, 231 }, 232 { PCI_PRODUCT_INTEL_82371FB_IDE, 233 0, 234 "Intel 82371FB IDE controller (PIIX)", 235 piix_chip_map, 236 }, 237 { PCI_PRODUCT_INTEL_82371SB_IDE, 238 0, 239 "Intel 82371SB IDE Interface (PIIX3)", 240 piix_chip_map, 241 }, 242 { PCI_PRODUCT_INTEL_82371AB_IDE, 243 0, 244 "Intel 82371AB IDE controller (PIIX4)", 245 piix_chip_map, 246 }, 247 { PCI_PRODUCT_INTEL_82440MX_IDE, 248 0, 249 "Intel 82440MX IDE controller", 250 piix_chip_map 251 }, 252 { PCI_PRODUCT_INTEL_82801AA_IDE, 253 0, 254 "Intel 82801AA IDE Controller (ICH)", 255 piix_chip_map, 256 }, 257 { PCI_PRODUCT_INTEL_82801AB_IDE, 258 0, 259 "Intel 82801AB IDE Controller (ICH0)", 260 piix_chip_map, 261 }, 262 { 0, 263 0, 264 NULL, 265 } 266 }; 267 268 const struct pciide_product_desc pciide_amd_products[] = { 269 { PCI_PRODUCT_AMD_PBC756_IDE, 270 0, 271 "Advanced Micro Devices AMD756 IDE Controller", 272 amd756_chip_map 273 }, 274 { 0, 275 0, 276 NULL, 277 } 278 }; 279 280 const struct pciide_product_desc pciide_cmd_products[] = { 281 { PCI_PRODUCT_CMDTECH_640, 282 0, 283 "CMD Technology PCI0640", 284 cmd_chip_map 285 }, 286 { PCI_PRODUCT_CMDTECH_643, 287 0, 288 "CMD Technology PCI0643", 289 cmd0643_9_chip_map, 290 }, 291 { PCI_PRODUCT_CMDTECH_646, 292 0, 293 "CMD Technology PCI0646", 294 cmd0643_9_chip_map, 295 }, 296 { PCI_PRODUCT_CMDTECH_648, 297 IDE_PCI_CLASS_OVERRIDE, 298 "CMD Technology PCI0648", 299 cmd0643_9_chip_map, 300 }, 301 { PCI_PRODUCT_CMDTECH_649, 302 IDE_PCI_CLASS_OVERRIDE, 303 "CMD Technology PCI0649", 304 cmd0643_9_chip_map, 305 }, 306 { 0, 307 0, 308 NULL, 309 } 310 }; 311 312 const struct pciide_product_desc pciide_via_products[] = { 313 { PCI_PRODUCT_VIATECH_VT82C586_IDE, 314 0, 315 "VIA Tech VT82C586 IDE Controller", 316 apollo_chip_map, 317 }, 318 { PCI_PRODUCT_VIATECH_VT82C586A_IDE, 319 0, 320 "VIA Tech VT82C586A IDE Controller", 321 apollo_chip_map, 322 }, 323 { 0, 324 0, 325 NULL, 326 } 327 }; 328 329 const struct pciide_product_desc pciide_cypress_products[] = { 330 { PCI_PRODUCT_CONTAQ_82C693, 331 IDE_16BIT_IOSPACE, 332 "Cypress 82C693 IDE Controller", 333 cy693_chip_map, 334 }, 335 { 0, 336 0, 337 NULL, 338 } 339 }; 340 341 const struct pciide_product_desc pciide_sis_products[] = { 342 { PCI_PRODUCT_SIS_5597_IDE, 343 0, 344 "Silicon Integrated System 5597/5598 IDE controller", 345 sis_chip_map, 346 }, 347 { 0, 348 0, 349 NULL, 350 } 351 }; 352 353 const struct pciide_product_desc pciide_acer_products[] = { 354 { PCI_PRODUCT_ALI_M5229, 355 0, 356 "Acer Labs M5229 UDMA IDE Controller", 357 acer_chip_map, 358 }, 359 { 0, 360 0, 361 NULL, 362 } 363 }; 364 365 const struct pciide_product_desc pciide_promise_products[] = { 366 { PCI_PRODUCT_PROMISE_ULTRA33, 367 IDE_PCI_CLASS_OVERRIDE|IDE_16BIT_IOSPACE, 368 "Promise Ultra33/ATA Bus Master IDE Accelerator", 369 pdc202xx_chip_map, 370 }, 371 { PCI_PRODUCT_PROMISE_ULTRA66, 372 IDE_PCI_CLASS_OVERRIDE|IDE_16BIT_IOSPACE, 373 "Promise Ultra66/ATA Bus Master IDE Accelerator", 374 pdc202xx_chip_map, 375 }, 376 { PCI_PRODUCT_PROMISE_ULTRA100, 377 IDE_PCI_CLASS_OVERRIDE|IDE_16BIT_IOSPACE, 378 "Promise Ultra100/ATA Bus Master IDE Accelerator", 379 pdc202xx_chip_map, 380 }, 381 { PCI_PRODUCT_PROMISE_ULTRA100X, 382 IDE_PCI_CLASS_OVERRIDE|IDE_16BIT_IOSPACE, 383 "Promise Ultra100/ATA Bus Master IDE Accelerator", 384 pdc202xx_chip_map, 385 }, 386 { 0, 387 0, 388 NULL, 389 } 390 }; 391 392 const struct pciide_product_desc pciide_opti_products[] = { 393 { PCI_PRODUCT_OPTI_82C621, 394 0, 395 "OPTi 82c621 PCI IDE controller", 396 opti_chip_map, 397 }, 398 { PCI_PRODUCT_OPTI_82C568, 399 0, 400 "OPTi 82c568 (82c621 compatible) PCI IDE controller", 401 opti_chip_map, 402 }, 403 { PCI_PRODUCT_OPTI_82D568, 404 0, 405 "OPTi 82d568 (82c621 compatible) PCI IDE controller", 406 opti_chip_map, 407 }, 408 { 0, 409 0, 410 NULL, 411 } 412 }; 413 414 const struct pciide_product_desc pciide_triones_products[] = { 415 { PCI_PRODUCT_TRIONES_HPT366, 416 IDE_PCI_CLASS_OVERRIDE, 417 "Triones/Highpoint HPT366/370 IDE Controller", 418 hpt_chip_map, 419 }, 420 { 0, 421 0, 422 NULL, 423 } 424 }; 425 426 struct pciide_vendor_desc { 427 u_int32_t ide_vendor; 428 const struct pciide_product_desc *ide_products; 429 }; 430 431 const struct pciide_vendor_desc pciide_vendors[] = { 432 { PCI_VENDOR_INTEL, pciide_intel_products }, 433 { PCI_VENDOR_CMDTECH, pciide_cmd_products }, 434 { PCI_VENDOR_VIATECH, pciide_via_products }, 435 { PCI_VENDOR_CONTAQ, pciide_cypress_products }, 436 { PCI_VENDOR_SIS, pciide_sis_products }, 437 { PCI_VENDOR_ALI, pciide_acer_products }, 438 { PCI_VENDOR_PROMISE, pciide_promise_products }, 439 { PCI_VENDOR_AMD, pciide_amd_products }, 440 { PCI_VENDOR_OPTI, pciide_opti_products }, 441 { PCI_VENDOR_TRIONES, pciide_triones_products }, 442 { 0, NULL } 443 }; 444 445 /* options passed via the 'flags' config keyword */ 446 #define PCIIDE_OPTIONS_DMA 0x01 447 448 int pciide_match __P((struct device *, struct cfdata *, void *)); 449 void pciide_attach __P((struct device *, struct device *, void *)); 450 451 struct cfattach pciide_ca = { 452 sizeof(struct pciide_softc), pciide_match, pciide_attach 453 }; 454 int pciide_chipen __P((struct pciide_softc *, struct pci_attach_args *)); 455 int pciide_mapregs_compat __P(( struct pci_attach_args *, 456 struct pciide_channel *, int, bus_size_t *, bus_size_t*)); 457 int pciide_mapregs_native __P((struct pci_attach_args *, 458 struct pciide_channel *, bus_size_t *, bus_size_t *, 459 int (*pci_intr) __P((void *)))); 460 void pciide_mapreg_dma __P((struct pciide_softc *, 461 struct pci_attach_args *)); 462 int pciide_chansetup __P((struct pciide_softc *, int, pcireg_t)); 463 void pciide_mapchan __P((struct pci_attach_args *, 464 struct pciide_channel *, pcireg_t, bus_size_t *, bus_size_t *, 465 int (*pci_intr) __P((void *)))); 466 int pciide_chan_candisable __P((struct pciide_channel *)); 467 void pciide_map_compat_intr __P(( struct pci_attach_args *, 468 struct pciide_channel *, int, int)); 469 int pciide_print __P((void *, const char *pnp)); 470 int pciide_compat_intr __P((void *)); 471 int pciide_pci_intr __P((void *)); 472 const struct pciide_product_desc* pciide_lookup_product __P((u_int32_t)); 473 474 const struct pciide_product_desc * 475 pciide_lookup_product(id) 476 u_int32_t id; 477 { 478 const struct pciide_product_desc *pp; 479 const struct pciide_vendor_desc *vp; 480 481 for (vp = pciide_vendors; vp->ide_products != NULL; vp++) 482 if (PCI_VENDOR(id) == vp->ide_vendor) 483 break; 484 485 if ((pp = vp->ide_products) == NULL) 486 return NULL; 487 488 for (; pp->ide_name != NULL; pp++) 489 if (PCI_PRODUCT(id) == pp->ide_product) 490 break; 491 492 if (pp->ide_name == NULL) 493 return NULL; 494 return pp; 495 } 496 497 int 498 pciide_match(parent, match, aux) 499 struct device *parent; 500 struct cfdata *match; 501 void *aux; 502 { 503 struct pci_attach_args *pa = aux; 504 const struct pciide_product_desc *pp; 505 506 /* 507 * Check the ID register to see that it's a PCI IDE controller. 508 * If it is, we assume that we can deal with it; it _should_ 509 * work in a standardized way... 510 */ 511 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 512 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 513 return (1); 514 } 515 516 /* 517 * Some controllers (e.g. promise Utra-33) don't claim to be PCI IDE 518 * controllers. Let see if we can deal with it anyway. 519 */ 520 pp = pciide_lookup_product(pa->pa_id); 521 if (pp && (pp->ide_flags & IDE_PCI_CLASS_OVERRIDE)) { 522 return (1); 523 } 524 525 return (0); 526 } 527 528 void 529 pciide_attach(parent, self, aux) 530 struct device *parent, *self; 531 void *aux; 532 { 533 struct pci_attach_args *pa = aux; 534 pci_chipset_tag_t pc = pa->pa_pc; 535 pcitag_t tag = pa->pa_tag; 536 struct pciide_softc *sc = (struct pciide_softc *)self; 537 pcireg_t csr; 538 char devinfo[256]; 539 const char *displaydev; 540 541 sc->sc_pp = pciide_lookup_product(pa->pa_id); 542 if (sc->sc_pp == NULL) { 543 sc->sc_pp = &default_product_desc; 544 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 545 displaydev = devinfo; 546 } else 547 displaydev = sc->sc_pp->ide_name; 548 549 printf(": %s (rev. 0x%02x)\n", displaydev, PCI_REVISION(pa->pa_class)); 550 551 sc->sc_pc = pa->pa_pc; 552 sc->sc_tag = pa->pa_tag; 553 #ifdef WDCDEBUG 554 if (wdcdebug_pciide_mask & DEBUG_PROBE) 555 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 556 #endif 557 sc->sc_pp->chip_map(sc, pa); 558 559 if (sc->sc_dma_ok) { 560 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 561 csr |= PCI_COMMAND_MASTER_ENABLE; 562 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 563 } 564 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 565 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 566 } 567 568 /* tell wether the chip is enabled or not */ 569 int 570 pciide_chipen(sc, pa) 571 struct pciide_softc *sc; 572 struct pci_attach_args *pa; 573 { 574 pcireg_t csr; 575 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 576 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 577 PCI_COMMAND_STATUS_REG); 578 printf("%s: device disabled (at %s)\n", 579 sc->sc_wdcdev.sc_dev.dv_xname, 580 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 581 "device" : "bridge"); 582 return 0; 583 } 584 return 1; 585 } 586 587 int 588 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 589 struct pci_attach_args *pa; 590 struct pciide_channel *cp; 591 int compatchan; 592 bus_size_t *cmdsizep, *ctlsizep; 593 { 594 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 595 struct channel_softc *wdc_cp = &cp->wdc_channel; 596 597 cp->compat = 1; 598 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 599 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 600 601 wdc_cp->cmd_iot = pa->pa_iot; 602 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 603 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 604 printf("%s: couldn't map %s channel cmd regs\n", 605 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 606 return (0); 607 } 608 609 wdc_cp->ctl_iot = pa->pa_iot; 610 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 611 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 612 printf("%s: couldn't map %s channel ctl regs\n", 613 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 614 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 615 PCIIDE_COMPAT_CMD_SIZE); 616 return (0); 617 } 618 619 return (1); 620 } 621 622 int 623 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 624 struct pci_attach_args * pa; 625 struct pciide_channel *cp; 626 bus_size_t *cmdsizep, *ctlsizep; 627 int (*pci_intr) __P((void *)); 628 { 629 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 630 struct channel_softc *wdc_cp = &cp->wdc_channel; 631 const char *intrstr; 632 pci_intr_handle_t intrhandle; 633 634 cp->compat = 0; 635 636 if (sc->sc_pci_ih == NULL) { 637 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 638 pa->pa_intrline, &intrhandle) != 0) { 639 printf("%s: couldn't map native-PCI interrupt\n", 640 sc->sc_wdcdev.sc_dev.dv_xname); 641 return 0; 642 } 643 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 644 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 645 intrhandle, IPL_BIO, pci_intr, sc); 646 if (sc->sc_pci_ih != NULL) { 647 printf("%s: using %s for native-PCI interrupt\n", 648 sc->sc_wdcdev.sc_dev.dv_xname, 649 intrstr ? intrstr : "unknown interrupt"); 650 } else { 651 printf("%s: couldn't establish native-PCI interrupt", 652 sc->sc_wdcdev.sc_dev.dv_xname); 653 if (intrstr != NULL) 654 printf(" at %s", intrstr); 655 printf("\n"); 656 return 0; 657 } 658 } 659 cp->ih = sc->sc_pci_ih; 660 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 661 PCI_MAPREG_TYPE_IO, 0, 662 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 663 printf("%s: couldn't map %s channel cmd regs\n", 664 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 665 return 0; 666 } 667 668 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 669 PCI_MAPREG_TYPE_IO, 0, 670 &wdc_cp->ctl_iot, &wdc_cp->ctl_ioh, NULL, ctlsizep) != 0) { 671 printf("%s: couldn't map %s channel ctl regs\n", 672 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 673 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 674 return 0; 675 } 676 return (1); 677 } 678 679 void 680 pciide_mapreg_dma(sc, pa) 681 struct pciide_softc *sc; 682 struct pci_attach_args *pa; 683 { 684 pcireg_t maptype; 685 bus_addr_t addr; 686 687 /* 688 * Map DMA registers 689 * 690 * Note that sc_dma_ok is the right variable to test to see if 691 * DMA can be done. If the interface doesn't support DMA, 692 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 693 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 694 * non-zero if the interface supports DMA and the registers 695 * could be mapped. 696 * 697 * XXX Note that despite the fact that the Bus Master IDE specs 698 * XXX say that "The bus master IDE function uses 16 bytes of IO 699 * XXX space," some controllers (at least the United 700 * XXX Microelectronics UM8886BF) place it in memory space. 701 */ 702 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 703 PCIIDE_REG_BUS_MASTER_DMA); 704 705 switch (maptype) { 706 case PCI_MAPREG_TYPE_IO: 707 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 708 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 709 &addr, NULL, NULL) == 0); 710 if (sc->sc_dma_ok == 0) { 711 printf(", but unused (couldn't query registers)"); 712 break; 713 } 714 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 715 && addr >= 0x10000) { 716 sc->sc_dma_ok = 0; 717 printf(", but unused (registers at unsafe address %#lx)", addr); 718 break; 719 } 720 /* FALLTHROUGH */ 721 722 case PCI_MAPREG_MEM_TYPE_32BIT: 723 sc->sc_dma_ok = (pci_mapreg_map(pa, 724 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 725 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 726 sc->sc_dmat = pa->pa_dmat; 727 if (sc->sc_dma_ok == 0) { 728 printf(", but unused (couldn't map registers)"); 729 } else { 730 sc->sc_wdcdev.dma_arg = sc; 731 sc->sc_wdcdev.dma_init = pciide_dma_init; 732 sc->sc_wdcdev.dma_start = pciide_dma_start; 733 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 734 } 735 break; 736 737 default: 738 sc->sc_dma_ok = 0; 739 printf(", but unsupported register maptype (0x%x)", maptype); 740 } 741 } 742 743 int 744 pciide_compat_intr(arg) 745 void *arg; 746 { 747 struct pciide_channel *cp = arg; 748 749 #ifdef DIAGNOSTIC 750 /* should only be called for a compat channel */ 751 if (cp->compat == 0) 752 panic("pciide compat intr called for non-compat chan %p\n", cp); 753 #endif 754 return (wdcintr(&cp->wdc_channel)); 755 } 756 757 int 758 pciide_pci_intr(arg) 759 void *arg; 760 { 761 struct pciide_softc *sc = arg; 762 struct pciide_channel *cp; 763 struct channel_softc *wdc_cp; 764 int i, rv, crv; 765 766 rv = 0; 767 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 768 cp = &sc->pciide_channels[i]; 769 wdc_cp = &cp->wdc_channel; 770 771 /* If a compat channel skip. */ 772 if (cp->compat) 773 continue; 774 /* if this channel not waiting for intr, skip */ 775 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 776 continue; 777 778 crv = wdcintr(wdc_cp); 779 if (crv == 0) 780 ; /* leave rv alone */ 781 else if (crv == 1) 782 rv = 1; /* claim the intr */ 783 else if (rv == 0) /* crv should be -1 in this case */ 784 rv = crv; /* if we've done no better, take it */ 785 } 786 return (rv); 787 } 788 789 void 790 pciide_channel_dma_setup(cp) 791 struct pciide_channel *cp; 792 { 793 int drive; 794 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 795 struct ata_drive_datas *drvp; 796 797 for (drive = 0; drive < 2; drive++) { 798 drvp = &cp->wdc_channel.ch_drive[drive]; 799 /* If no drive, skip */ 800 if ((drvp->drive_flags & DRIVE) == 0) 801 continue; 802 /* setup DMA if needed */ 803 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 804 (drvp->drive_flags & DRIVE_UDMA) == 0) || 805 sc->sc_dma_ok == 0) { 806 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 807 continue; 808 } 809 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 810 != 0) { 811 /* Abort DMA setup */ 812 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 813 continue; 814 } 815 } 816 } 817 818 int 819 pciide_dma_table_setup(sc, channel, drive) 820 struct pciide_softc *sc; 821 int channel, drive; 822 { 823 bus_dma_segment_t seg; 824 int error, rseg; 825 const bus_size_t dma_table_size = 826 sizeof(struct idedma_table) * NIDEDMA_TABLES; 827 struct pciide_dma_maps *dma_maps = 828 &sc->pciide_channels[channel].dma_maps[drive]; 829 830 /* If table was already allocated, just return */ 831 if (dma_maps->dma_table) 832 return 0; 833 834 /* Allocate memory for the DMA tables and map it */ 835 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 836 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 837 BUS_DMA_NOWAIT)) != 0) { 838 printf("%s:%d: unable to allocate table DMA for " 839 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 840 channel, drive, error); 841 return error; 842 } 843 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 844 dma_table_size, 845 (caddr_t *)&dma_maps->dma_table, 846 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 847 printf("%s:%d: unable to map table DMA for" 848 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 849 channel, drive, error); 850 return error; 851 } 852 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %ld, " 853 "phy 0x%lx\n", dma_maps->dma_table, dma_table_size, 854 seg.ds_addr), DEBUG_PROBE); 855 856 /* Create and load table DMA map for this disk */ 857 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 858 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 859 &dma_maps->dmamap_table)) != 0) { 860 printf("%s:%d: unable to create table DMA map for " 861 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 862 channel, drive, error); 863 return error; 864 } 865 if ((error = bus_dmamap_load(sc->sc_dmat, 866 dma_maps->dmamap_table, 867 dma_maps->dma_table, 868 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 869 printf("%s:%d: unable to load table DMA map for " 870 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 871 channel, drive, error); 872 return error; 873 } 874 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 875 dma_maps->dmamap_table->dm_segs[0].ds_addr), DEBUG_PROBE); 876 /* Create a xfer DMA map for this drive */ 877 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 878 NIDEDMA_TABLES, IDEDMA_BYTE_COUNT_MAX, IDEDMA_BYTE_COUNT_ALIGN, 879 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 880 &dma_maps->dmamap_xfer)) != 0) { 881 printf("%s:%d: unable to create xfer DMA map for " 882 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 883 channel, drive, error); 884 return error; 885 } 886 return 0; 887 } 888 889 int 890 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 891 void *v; 892 int channel, drive; 893 void *databuf; 894 size_t datalen; 895 int flags; 896 { 897 struct pciide_softc *sc = v; 898 int error, seg; 899 struct pciide_dma_maps *dma_maps = 900 &sc->pciide_channels[channel].dma_maps[drive]; 901 902 error = bus_dmamap_load(sc->sc_dmat, 903 dma_maps->dmamap_xfer, 904 databuf, datalen, NULL, BUS_DMA_NOWAIT); 905 if (error) { 906 printf("%s:%d: unable to load xfer DMA map for" 907 "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname, 908 channel, drive, error); 909 return error; 910 } 911 912 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 913 dma_maps->dmamap_xfer->dm_mapsize, 914 (flags & WDC_DMA_READ) ? 915 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 916 917 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 918 #ifdef DIAGNOSTIC 919 /* A segment must not cross a 64k boundary */ 920 { 921 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 922 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 923 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 924 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 925 printf("pciide_dma: segment %d physical addr 0x%lx" 926 " len 0x%lx not properly aligned\n", 927 seg, phys, len); 928 panic("pciide_dma: buf align"); 929 } 930 } 931 #endif 932 dma_maps->dma_table[seg].base_addr = 933 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 934 dma_maps->dma_table[seg].byte_count = 935 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 936 IDEDMA_BYTE_COUNT_MASK); 937 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 938 seg, le32toh(dma_maps->dma_table[seg].byte_count), 939 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 940 941 } 942 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 943 htole32(IDEDMA_BYTE_COUNT_EOT); 944 945 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 946 dma_maps->dmamap_table->dm_mapsize, 947 BUS_DMASYNC_PREWRITE); 948 949 /* Maps are ready. Start DMA function */ 950 #ifdef DIAGNOSTIC 951 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 952 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 953 dma_maps->dmamap_table->dm_segs[0].ds_addr); 954 panic("pciide_dma_init: table align"); 955 } 956 #endif 957 958 /* Clear status bits */ 959 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 960 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 961 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 962 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 963 /* Write table addr */ 964 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 965 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 966 dma_maps->dmamap_table->dm_segs[0].ds_addr); 967 /* set read/write */ 968 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 969 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 970 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 971 /* remember flags */ 972 dma_maps->dma_flags = flags; 973 return 0; 974 } 975 976 void 977 pciide_dma_start(v, channel, drive) 978 void *v; 979 int channel, drive; 980 { 981 struct pciide_softc *sc = v; 982 983 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 984 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 985 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 986 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 987 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 988 } 989 990 int 991 pciide_dma_finish(v, channel, drive, force) 992 void *v; 993 int channel, drive; 994 int force; 995 { 996 struct pciide_softc *sc = v; 997 u_int8_t status; 998 int error = 0; 999 struct pciide_dma_maps *dma_maps = 1000 &sc->pciide_channels[channel].dma_maps[drive]; 1001 1002 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1003 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 1004 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 1005 DEBUG_XFERS); 1006 1007 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 1008 return WDC_DMAST_NOIRQ; 1009 1010 /* stop DMA channel */ 1011 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1012 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 1013 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1014 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 1015 1016 /* Unload the map of the data buffer */ 1017 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 1018 dma_maps->dmamap_xfer->dm_mapsize, 1019 (dma_maps->dma_flags & WDC_DMA_READ) ? 1020 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1021 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 1022 1023 if ((status & IDEDMA_CTL_ERR) != 0) { 1024 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 1025 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 1026 error |= WDC_DMAST_ERR; 1027 } 1028 1029 if ((status & IDEDMA_CTL_INTR) == 0) { 1030 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 1031 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 1032 drive, status); 1033 error |= WDC_DMAST_NOIRQ; 1034 } 1035 1036 if ((status & IDEDMA_CTL_ACT) != 0) { 1037 /* data underrun, may be a valid condition for ATAPI */ 1038 error |= WDC_DMAST_UNDER; 1039 } 1040 return error; 1041 } 1042 1043 void 1044 pciide_irqack(chp) 1045 struct channel_softc *chp; 1046 { 1047 struct pciide_channel *cp = (struct pciide_channel*)chp; 1048 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1049 1050 /* clear status bits in IDE DMA registers */ 1051 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1052 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 1053 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1054 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 1055 } 1056 1057 /* some common code used by several chip_map */ 1058 int 1059 pciide_chansetup(sc, channel, interface) 1060 struct pciide_softc *sc; 1061 int channel; 1062 pcireg_t interface; 1063 { 1064 struct pciide_channel *cp = &sc->pciide_channels[channel]; 1065 sc->wdc_chanarray[channel] = &cp->wdc_channel; 1066 cp->name = PCIIDE_CHANNEL_NAME(channel); 1067 cp->wdc_channel.channel = channel; 1068 cp->wdc_channel.wdc = &sc->sc_wdcdev; 1069 cp->wdc_channel.ch_queue = 1070 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 1071 if (cp->wdc_channel.ch_queue == NULL) { 1072 printf("%s %s channel: " 1073 "can't allocate memory for command queue", 1074 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1075 return 0; 1076 } 1077 printf("%s: %s channel %s to %s mode\n", 1078 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1079 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 1080 "configured" : "wired", 1081 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 1082 "native-PCI" : "compatibility"); 1083 return 1; 1084 } 1085 1086 /* some common code used by several chip channel_map */ 1087 void 1088 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 1089 struct pci_attach_args *pa; 1090 struct pciide_channel *cp; 1091 pcireg_t interface; 1092 bus_size_t *cmdsizep, *ctlsizep; 1093 int (*pci_intr) __P((void *)); 1094 { 1095 struct channel_softc *wdc_cp = &cp->wdc_channel; 1096 1097 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 1098 cp->hw_ok = pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, 1099 pci_intr); 1100 else 1101 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1102 wdc_cp->channel, cmdsizep, ctlsizep); 1103 1104 if (cp->hw_ok == 0) 1105 return; 1106 wdc_cp->data32iot = wdc_cp->cmd_iot; 1107 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 1108 wdcattach(wdc_cp); 1109 } 1110 1111 /* 1112 * Generic code to call to know if a channel can be disabled. Return 1 1113 * if channel can be disabled, 0 if not 1114 */ 1115 int 1116 pciide_chan_candisable(cp) 1117 struct pciide_channel *cp; 1118 { 1119 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1120 struct channel_softc *wdc_cp = &cp->wdc_channel; 1121 1122 if ((wdc_cp->ch_drive[0].drive_flags & DRIVE) == 0 && 1123 (wdc_cp->ch_drive[1].drive_flags & DRIVE) == 0) { 1124 printf("%s: disabling %s channel (no drives)\n", 1125 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1126 cp->hw_ok = 0; 1127 return 1; 1128 } 1129 return 0; 1130 } 1131 1132 /* 1133 * generic code to map the compat intr if hw_ok=1 and it is a compat channel. 1134 * Set hw_ok=0 on failure 1135 */ 1136 void 1137 pciide_map_compat_intr(pa, cp, compatchan, interface) 1138 struct pci_attach_args *pa; 1139 struct pciide_channel *cp; 1140 int compatchan, interface; 1141 { 1142 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1143 struct channel_softc *wdc_cp = &cp->wdc_channel; 1144 1145 if (cp->hw_ok == 0) 1146 return; 1147 if ((interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) != 0) 1148 return; 1149 1150 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 1151 pa, compatchan, pciide_compat_intr, cp); 1152 if (cp->ih == NULL) { 1153 printf("%s: no compatibility interrupt for use by %s " 1154 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1155 cp->hw_ok = 0; 1156 } 1157 } 1158 1159 void 1160 pciide_print_modes(cp) 1161 struct pciide_channel *cp; 1162 { 1163 wdc_print_modes(&cp->wdc_channel); 1164 } 1165 1166 void 1167 default_chip_map(sc, pa) 1168 struct pciide_softc *sc; 1169 struct pci_attach_args *pa; 1170 { 1171 struct pciide_channel *cp; 1172 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1173 pcireg_t csr; 1174 int channel, drive; 1175 struct ata_drive_datas *drvp; 1176 u_int8_t idedma_ctl; 1177 bus_size_t cmdsize, ctlsize; 1178 char *failreason; 1179 1180 if (pciide_chipen(sc, pa) == 0) 1181 return; 1182 1183 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 1184 printf("%s: bus-master DMA support present", 1185 sc->sc_wdcdev.sc_dev.dv_xname); 1186 if (sc->sc_pp == &default_product_desc && 1187 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 1188 PCIIDE_OPTIONS_DMA) == 0) { 1189 printf(", but unused (no driver support)"); 1190 sc->sc_dma_ok = 0; 1191 } else { 1192 pciide_mapreg_dma(sc, pa); 1193 if (sc->sc_dma_ok != 0) 1194 printf(", used without full driver " 1195 "support"); 1196 } 1197 } else { 1198 printf("%s: hardware does not support DMA", 1199 sc->sc_wdcdev.sc_dev.dv_xname); 1200 sc->sc_dma_ok = 0; 1201 } 1202 printf("\n"); 1203 if (sc->sc_dma_ok) { 1204 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1205 sc->sc_wdcdev.irqack = pciide_irqack; 1206 } 1207 sc->sc_wdcdev.PIO_cap = 0; 1208 sc->sc_wdcdev.DMA_cap = 0; 1209 1210 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1211 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1212 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 1213 1214 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1215 cp = &sc->pciide_channels[channel]; 1216 if (pciide_chansetup(sc, channel, interface) == 0) 1217 continue; 1218 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1219 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 1220 &ctlsize, pciide_pci_intr); 1221 } else { 1222 cp->hw_ok = pciide_mapregs_compat(pa, cp, 1223 channel, &cmdsize, &ctlsize); 1224 } 1225 if (cp->hw_ok == 0) 1226 continue; 1227 /* 1228 * Check to see if something appears to be there. 1229 */ 1230 failreason = NULL; 1231 if (!wdcprobe(&cp->wdc_channel)) { 1232 failreason = "not responding; disabled or no drives?"; 1233 goto next; 1234 } 1235 /* 1236 * Now, make sure it's actually attributable to this PCI IDE 1237 * channel by trying to access the channel again while the 1238 * PCI IDE controller's I/O space is disabled. (If the 1239 * channel no longer appears to be there, it belongs to 1240 * this controller.) YUCK! 1241 */ 1242 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1243 PCI_COMMAND_STATUS_REG); 1244 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1245 csr & ~PCI_COMMAND_IO_ENABLE); 1246 if (wdcprobe(&cp->wdc_channel)) 1247 failreason = "other hardware responding at addresses"; 1248 pci_conf_write(sc->sc_pc, sc->sc_tag, 1249 PCI_COMMAND_STATUS_REG, csr); 1250 next: 1251 if (failreason) { 1252 printf("%s: %s channel ignored (%s)\n", 1253 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 1254 failreason); 1255 cp->hw_ok = 0; 1256 bus_space_unmap(cp->wdc_channel.cmd_iot, 1257 cp->wdc_channel.cmd_ioh, cmdsize); 1258 bus_space_unmap(cp->wdc_channel.ctl_iot, 1259 cp->wdc_channel.ctl_ioh, ctlsize); 1260 } else { 1261 pciide_map_compat_intr(pa, cp, channel, interface); 1262 } 1263 if (cp->hw_ok) { 1264 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 1265 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 1266 wdcattach(&cp->wdc_channel); 1267 } 1268 } 1269 1270 if (sc->sc_dma_ok == 0) 1271 return; 1272 1273 /* Allocate DMA maps */ 1274 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1275 idedma_ctl = 0; 1276 cp = &sc->pciide_channels[channel]; 1277 for (drive = 0; drive < 2; drive++) { 1278 drvp = &cp->wdc_channel.ch_drive[drive]; 1279 /* If no drive, skip */ 1280 if ((drvp->drive_flags & DRIVE) == 0) 1281 continue; 1282 if ((drvp->drive_flags & DRIVE_DMA) == 0) 1283 continue; 1284 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1285 /* Abort DMA setup */ 1286 printf("%s:%d:%d: can't allocate DMA maps, " 1287 "using PIO transfers\n", 1288 sc->sc_wdcdev.sc_dev.dv_xname, 1289 channel, drive); 1290 drvp->drive_flags &= ~DRIVE_DMA; 1291 } 1292 printf("%s:%d:%d: using DMA data transfers\n", 1293 sc->sc_wdcdev.sc_dev.dv_xname, 1294 channel, drive); 1295 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1296 } 1297 if (idedma_ctl != 0) { 1298 /* Add software bits in status register */ 1299 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1300 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1301 idedma_ctl); 1302 } 1303 } 1304 } 1305 1306 void 1307 piix_chip_map(sc, pa) 1308 struct pciide_softc *sc; 1309 struct pci_attach_args *pa; 1310 { 1311 struct pciide_channel *cp; 1312 int channel; 1313 u_int32_t idetim; 1314 bus_size_t cmdsize, ctlsize; 1315 1316 if (pciide_chipen(sc, pa) == 0) 1317 return; 1318 1319 printf("%s: bus-master DMA support present", 1320 sc->sc_wdcdev.sc_dev.dv_xname); 1321 pciide_mapreg_dma(sc, pa); 1322 printf("\n"); 1323 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1324 WDC_CAPABILITY_MODE; 1325 if (sc->sc_dma_ok) { 1326 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1327 sc->sc_wdcdev.irqack = pciide_irqack; 1328 switch(sc->sc_pp->ide_product) { 1329 case PCI_PRODUCT_INTEL_82371AB_IDE: 1330 case PCI_PRODUCT_INTEL_82440MX_IDE: 1331 case PCI_PRODUCT_INTEL_82801AA_IDE: 1332 case PCI_PRODUCT_INTEL_82801AB_IDE: 1333 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1334 } 1335 } 1336 sc->sc_wdcdev.PIO_cap = 4; 1337 sc->sc_wdcdev.DMA_cap = 2; 1338 sc->sc_wdcdev.UDMA_cap = 1339 (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) ? 4 : 2; 1340 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82371FB_IDE) 1341 sc->sc_wdcdev.set_modes = piix_setup_channel; 1342 else 1343 sc->sc_wdcdev.set_modes = piix3_4_setup_channel; 1344 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1345 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1346 1347 WDCDEBUG_PRINT(("piix_setup_chip: old idetim=0x%x", 1348 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1349 DEBUG_PROBE); 1350 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1351 WDCDEBUG_PRINT((", sidetim=0x%x", 1352 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1353 DEBUG_PROBE); 1354 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1355 WDCDEBUG_PRINT((", udamreg 0x%x", 1356 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1357 DEBUG_PROBE); 1358 } 1359 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1360 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1361 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1362 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1363 DEBUG_PROBE); 1364 } 1365 1366 } 1367 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1368 1369 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1370 cp = &sc->pciide_channels[channel]; 1371 /* PIIX is compat-only */ 1372 if (pciide_chansetup(sc, channel, 0) == 0) 1373 continue; 1374 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1375 if ((PIIX_IDETIM_READ(idetim, channel) & 1376 PIIX_IDETIM_IDE) == 0) { 1377 printf("%s: %s channel ignored (disabled)\n", 1378 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1379 continue; 1380 } 1381 /* PIIX are compat-only pciide devices */ 1382 pciide_mapchan(pa, cp, 0, &cmdsize, &ctlsize, pciide_pci_intr); 1383 if (cp->hw_ok == 0) 1384 continue; 1385 if (pciide_chan_candisable(cp)) { 1386 idetim = PIIX_IDETIM_CLEAR(idetim, PIIX_IDETIM_IDE, 1387 channel); 1388 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, 1389 idetim); 1390 } 1391 pciide_map_compat_intr(pa, cp, channel, 0); 1392 if (cp->hw_ok == 0) 1393 continue; 1394 sc->sc_wdcdev.set_modes(&cp->wdc_channel); 1395 } 1396 1397 WDCDEBUG_PRINT(("piix_setup_chip: idetim=0x%x", 1398 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM)), 1399 DEBUG_PROBE); 1400 if (sc->sc_pp->ide_product != PCI_PRODUCT_INTEL_82371FB_IDE) { 1401 WDCDEBUG_PRINT((", sidetim=0x%x", 1402 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM)), 1403 DEBUG_PROBE); 1404 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 1405 WDCDEBUG_PRINT((", udamreg 0x%x", 1406 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG)), 1407 DEBUG_PROBE); 1408 } 1409 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1410 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1411 WDCDEBUG_PRINT((", IDE_CONTROL 0x%x", 1412 pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG)), 1413 DEBUG_PROBE); 1414 } 1415 } 1416 WDCDEBUG_PRINT(("\n"), DEBUG_PROBE); 1417 } 1418 1419 void 1420 piix_setup_channel(chp) 1421 struct channel_softc *chp; 1422 { 1423 u_int8_t mode[2], drive; 1424 u_int32_t oidetim, idetim, idedma_ctl; 1425 struct pciide_channel *cp = (struct pciide_channel*)chp; 1426 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1427 struct ata_drive_datas *drvp = cp->wdc_channel.ch_drive; 1428 1429 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1430 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, chp->channel); 1431 idedma_ctl = 0; 1432 1433 /* set up new idetim: Enable IDE registers decode */ 1434 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, 1435 chp->channel); 1436 1437 /* setup DMA */ 1438 pciide_channel_dma_setup(cp); 1439 1440 /* 1441 * Here we have to mess up with drives mode: PIIX can't have 1442 * different timings for master and slave drives. 1443 * We need to find the best combination. 1444 */ 1445 1446 /* If both drives supports DMA, take the lower mode */ 1447 if ((drvp[0].drive_flags & DRIVE_DMA) && 1448 (drvp[1].drive_flags & DRIVE_DMA)) { 1449 mode[0] = mode[1] = 1450 min(drvp[0].DMA_mode, drvp[1].DMA_mode); 1451 drvp[0].DMA_mode = mode[0]; 1452 drvp[1].DMA_mode = mode[1]; 1453 goto ok; 1454 } 1455 /* 1456 * If only one drive supports DMA, use its mode, and 1457 * put the other one in PIO mode 0 if mode not compatible 1458 */ 1459 if (drvp[0].drive_flags & DRIVE_DMA) { 1460 mode[0] = drvp[0].DMA_mode; 1461 mode[1] = drvp[1].PIO_mode; 1462 if (piix_isp_pio[mode[1]] != piix_isp_dma[mode[0]] || 1463 piix_rtc_pio[mode[1]] != piix_rtc_dma[mode[0]]) 1464 mode[1] = drvp[1].PIO_mode = 0; 1465 goto ok; 1466 } 1467 if (drvp[1].drive_flags & DRIVE_DMA) { 1468 mode[1] = drvp[1].DMA_mode; 1469 mode[0] = drvp[0].PIO_mode; 1470 if (piix_isp_pio[mode[0]] != piix_isp_dma[mode[1]] || 1471 piix_rtc_pio[mode[0]] != piix_rtc_dma[mode[1]]) 1472 mode[0] = drvp[0].PIO_mode = 0; 1473 goto ok; 1474 } 1475 /* 1476 * If both drives are not DMA, takes the lower mode, unless 1477 * one of them is PIO mode < 2 1478 */ 1479 if (drvp[0].PIO_mode < 2) { 1480 mode[0] = drvp[0].PIO_mode = 0; 1481 mode[1] = drvp[1].PIO_mode; 1482 } else if (drvp[1].PIO_mode < 2) { 1483 mode[1] = drvp[1].PIO_mode = 0; 1484 mode[0] = drvp[0].PIO_mode; 1485 } else { 1486 mode[0] = mode[1] = 1487 min(drvp[1].PIO_mode, drvp[0].PIO_mode); 1488 drvp[0].PIO_mode = mode[0]; 1489 drvp[1].PIO_mode = mode[1]; 1490 } 1491 ok: /* The modes are setup */ 1492 for (drive = 0; drive < 2; drive++) { 1493 if (drvp[drive].drive_flags & DRIVE_DMA) { 1494 idetim |= piix_setup_idetim_timings( 1495 mode[drive], 1, chp->channel); 1496 goto end; 1497 } 1498 } 1499 /* If we are there, none of the drives are DMA */ 1500 if (mode[0] >= 2) 1501 idetim |= piix_setup_idetim_timings( 1502 mode[0], 0, chp->channel); 1503 else 1504 idetim |= piix_setup_idetim_timings( 1505 mode[1], 0, chp->channel); 1506 end: /* 1507 * timing mode is now set up in the controller. Enable 1508 * it per-drive 1509 */ 1510 for (drive = 0; drive < 2; drive++) { 1511 /* If no drive, skip */ 1512 if ((drvp[drive].drive_flags & DRIVE) == 0) 1513 continue; 1514 idetim |= piix_setup_idetim_drvs(&drvp[drive]); 1515 if (drvp[drive].drive_flags & DRIVE_DMA) 1516 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1517 } 1518 if (idedma_ctl != 0) { 1519 /* Add software bits in status register */ 1520 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1521 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1522 idedma_ctl); 1523 } 1524 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1525 pciide_print_modes(cp); 1526 } 1527 1528 void 1529 piix3_4_setup_channel(chp) 1530 struct channel_softc *chp; 1531 { 1532 struct ata_drive_datas *drvp; 1533 u_int32_t oidetim, idetim, sidetim, udmareg, ideconf, idedma_ctl; 1534 struct pciide_channel *cp = (struct pciide_channel*)chp; 1535 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1536 int drive; 1537 int channel = chp->channel; 1538 1539 oidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_IDETIM); 1540 sidetim = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM); 1541 udmareg = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG); 1542 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, PIIX_CONFIG); 1543 idetim = PIIX_IDETIM_CLEAR(oidetim, 0xffff, channel); 1544 sidetim &= ~(PIIX_SIDETIM_ISP_MASK(channel) | 1545 PIIX_SIDETIM_RTC_MASK(channel)); 1546 1547 idedma_ctl = 0; 1548 /* If channel disabled, no need to go further */ 1549 if ((PIIX_IDETIM_READ(oidetim, channel) & PIIX_IDETIM_IDE) == 0) 1550 return; 1551 /* set up new idetim: Enable IDE registers decode */ 1552 idetim = PIIX_IDETIM_SET(idetim, PIIX_IDETIM_IDE, channel); 1553 1554 /* setup DMA if needed */ 1555 pciide_channel_dma_setup(cp); 1556 1557 for (drive = 0; drive < 2; drive++) { 1558 udmareg &= ~(PIIX_UDMACTL_DRV_EN(channel, drive) | 1559 PIIX_UDMATIM_SET(0x3, channel, drive)); 1560 drvp = &chp->ch_drive[drive]; 1561 /* If no drive, skip */ 1562 if ((drvp->drive_flags & DRIVE) == 0) 1563 continue; 1564 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1565 (drvp->drive_flags & DRIVE_UDMA) == 0)) 1566 goto pio; 1567 1568 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE || 1569 sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AB_IDE) { 1570 ideconf |= PIIX_CONFIG_PINGPONG; 1571 } 1572 if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_82801AA_IDE) { 1573 /* setup Ultra/66 */ 1574 if (drvp->UDMA_mode > 2 && 1575 (ideconf & PIIX_CONFIG_CR(channel, drive)) == 0) 1576 drvp->UDMA_mode = 2; 1577 if (drvp->UDMA_mode > 2) 1578 ideconf |= PIIX_CONFIG_UDMA66(channel, drive); 1579 else 1580 ideconf &= ~PIIX_CONFIG_UDMA66(channel, drive); 1581 } 1582 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1583 (drvp->drive_flags & DRIVE_UDMA)) { 1584 /* use Ultra/DMA */ 1585 drvp->drive_flags &= ~DRIVE_DMA; 1586 udmareg |= PIIX_UDMACTL_DRV_EN( channel, drive); 1587 udmareg |= PIIX_UDMATIM_SET( 1588 piix4_sct_udma[drvp->UDMA_mode], channel, drive); 1589 } else { 1590 /* use Multiword DMA */ 1591 drvp->drive_flags &= ~DRIVE_UDMA; 1592 if (drive == 0) { 1593 idetim |= piix_setup_idetim_timings( 1594 drvp->DMA_mode, 1, channel); 1595 } else { 1596 sidetim |= piix_setup_sidetim_timings( 1597 drvp->DMA_mode, 1, channel); 1598 idetim =PIIX_IDETIM_SET(idetim, 1599 PIIX_IDETIM_SITRE, channel); 1600 } 1601 } 1602 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1603 1604 pio: /* use PIO mode */ 1605 idetim |= piix_setup_idetim_drvs(drvp); 1606 if (drive == 0) { 1607 idetim |= piix_setup_idetim_timings( 1608 drvp->PIO_mode, 0, channel); 1609 } else { 1610 sidetim |= piix_setup_sidetim_timings( 1611 drvp->PIO_mode, 0, channel); 1612 idetim =PIIX_IDETIM_SET(idetim, 1613 PIIX_IDETIM_SITRE, channel); 1614 } 1615 } 1616 if (idedma_ctl != 0) { 1617 /* Add software bits in status register */ 1618 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1619 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 1620 idedma_ctl); 1621 } 1622 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_IDETIM, idetim); 1623 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_SIDETIM, sidetim); 1624 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_UDMAREG, udmareg); 1625 pci_conf_write(sc->sc_pc, sc->sc_tag, PIIX_CONFIG, ideconf); 1626 pciide_print_modes(cp); 1627 } 1628 1629 1630 /* setup ISP and RTC fields, based on mode */ 1631 static u_int32_t 1632 piix_setup_idetim_timings(mode, dma, channel) 1633 u_int8_t mode; 1634 u_int8_t dma; 1635 u_int8_t channel; 1636 { 1637 1638 if (dma) 1639 return PIIX_IDETIM_SET(0, 1640 PIIX_IDETIM_ISP_SET(piix_isp_dma[mode]) | 1641 PIIX_IDETIM_RTC_SET(piix_rtc_dma[mode]), 1642 channel); 1643 else 1644 return PIIX_IDETIM_SET(0, 1645 PIIX_IDETIM_ISP_SET(piix_isp_pio[mode]) | 1646 PIIX_IDETIM_RTC_SET(piix_rtc_pio[mode]), 1647 channel); 1648 } 1649 1650 /* setup DTE, PPE, IE and TIME field based on PIO mode */ 1651 static u_int32_t 1652 piix_setup_idetim_drvs(drvp) 1653 struct ata_drive_datas *drvp; 1654 { 1655 u_int32_t ret = 0; 1656 struct channel_softc *chp = drvp->chnl_softc; 1657 u_int8_t channel = chp->channel; 1658 u_int8_t drive = drvp->drive; 1659 1660 /* 1661 * If drive is using UDMA, timings setups are independant 1662 * So just check DMA and PIO here. 1663 */ 1664 if (drvp->drive_flags & DRIVE_DMA) { 1665 /* if mode = DMA mode 0, use compatible timings */ 1666 if ((drvp->drive_flags & DRIVE_DMA) && 1667 drvp->DMA_mode == 0) { 1668 drvp->PIO_mode = 0; 1669 return ret; 1670 } 1671 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1672 /* 1673 * PIO and DMA timings are the same, use fast timings for PIO 1674 * too, else use compat timings. 1675 */ 1676 if ((piix_isp_pio[drvp->PIO_mode] != 1677 piix_isp_dma[drvp->DMA_mode]) || 1678 (piix_rtc_pio[drvp->PIO_mode] != 1679 piix_rtc_dma[drvp->DMA_mode])) 1680 drvp->PIO_mode = 0; 1681 /* if PIO mode <= 2, use compat timings for PIO */ 1682 if (drvp->PIO_mode <= 2) { 1683 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_DTE(drive), 1684 channel); 1685 return ret; 1686 } 1687 } 1688 1689 /* 1690 * Now setup PIO modes. If mode < 2, use compat timings. 1691 * Else enable fast timings. Enable IORDY and prefetch/post 1692 * if PIO mode >= 3. 1693 */ 1694 1695 if (drvp->PIO_mode < 2) 1696 return ret; 1697 1698 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_TIME(drive), channel); 1699 if (drvp->PIO_mode >= 3) { 1700 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_IE(drive), channel); 1701 ret = PIIX_IDETIM_SET(ret, PIIX_IDETIM_PPE(drive), channel); 1702 } 1703 return ret; 1704 } 1705 1706 /* setup values in SIDETIM registers, based on mode */ 1707 static u_int32_t 1708 piix_setup_sidetim_timings(mode, dma, channel) 1709 u_int8_t mode; 1710 u_int8_t dma; 1711 u_int8_t channel; 1712 { 1713 if (dma) 1714 return PIIX_SIDETIM_ISP_SET(piix_isp_dma[mode], channel) | 1715 PIIX_SIDETIM_RTC_SET(piix_rtc_dma[mode], channel); 1716 else 1717 return PIIX_SIDETIM_ISP_SET(piix_isp_pio[mode], channel) | 1718 PIIX_SIDETIM_RTC_SET(piix_rtc_pio[mode], channel); 1719 } 1720 1721 void 1722 amd756_chip_map(sc, pa) 1723 struct pciide_softc *sc; 1724 struct pci_attach_args *pa; 1725 { 1726 struct pciide_channel *cp; 1727 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1728 int channel; 1729 pcireg_t chanenable; 1730 bus_size_t cmdsize, ctlsize; 1731 1732 if (pciide_chipen(sc, pa) == 0) 1733 return; 1734 printf("%s: bus-master DMA support present", 1735 sc->sc_wdcdev.sc_dev.dv_xname); 1736 pciide_mapreg_dma(sc, pa); 1737 printf("\n"); 1738 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1739 WDC_CAPABILITY_MODE; 1740 if (sc->sc_dma_ok) { 1741 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 1742 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 1743 sc->sc_wdcdev.irqack = pciide_irqack; 1744 } 1745 sc->sc_wdcdev.PIO_cap = 4; 1746 sc->sc_wdcdev.DMA_cap = 2; 1747 sc->sc_wdcdev.UDMA_cap = 4; 1748 sc->sc_wdcdev.set_modes = amd756_setup_channel; 1749 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1750 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1751 chanenable = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN); 1752 1753 WDCDEBUG_PRINT(("amd756_chip_map: Channel enable=0x%x\n", chanenable), 1754 DEBUG_PROBE); 1755 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1756 cp = &sc->pciide_channels[channel]; 1757 if (pciide_chansetup(sc, channel, interface) == 0) 1758 continue; 1759 1760 if ((chanenable & AMD756_CHAN_EN(channel)) == 0) { 1761 printf("%s: %s channel ignored (disabled)\n", 1762 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1763 continue; 1764 } 1765 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1766 pciide_pci_intr); 1767 1768 if (pciide_chan_candisable(cp)) 1769 chanenable &= ~AMD756_CHAN_EN(channel); 1770 pciide_map_compat_intr(pa, cp, channel, interface); 1771 if (cp->hw_ok == 0) 1772 continue; 1773 1774 amd756_setup_channel(&cp->wdc_channel); 1775 } 1776 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_CHANSTATUS_EN, 1777 chanenable); 1778 return; 1779 } 1780 1781 void 1782 amd756_setup_channel(chp) 1783 struct channel_softc *chp; 1784 { 1785 u_int32_t udmatim_reg, datatim_reg; 1786 u_int8_t idedma_ctl; 1787 int mode, drive; 1788 struct ata_drive_datas *drvp; 1789 struct pciide_channel *cp = (struct pciide_channel*)chp; 1790 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1791 #ifndef PCIIDE_AMD756_ENABLEDMA 1792 int rev = PCI_REVISION( 1793 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 1794 #endif 1795 1796 idedma_ctl = 0; 1797 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_DATATIM); 1798 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, AMD756_UDMA); 1799 datatim_reg &= ~AMD756_DATATIM_MASK(chp->channel); 1800 udmatim_reg &= ~AMD756_UDMA_MASK(chp->channel); 1801 1802 /* setup DMA if needed */ 1803 pciide_channel_dma_setup(cp); 1804 1805 for (drive = 0; drive < 2; drive++) { 1806 drvp = &chp->ch_drive[drive]; 1807 /* If no drive, skip */ 1808 if ((drvp->drive_flags & DRIVE) == 0) 1809 continue; 1810 /* add timing values, setup DMA if needed */ 1811 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1812 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1813 mode = drvp->PIO_mode; 1814 goto pio; 1815 } 1816 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1817 (drvp->drive_flags & DRIVE_UDMA)) { 1818 /* use Ultra/DMA */ 1819 drvp->drive_flags &= ~DRIVE_DMA; 1820 udmatim_reg |= AMD756_UDMA_EN(chp->channel, drive) | 1821 AMD756_UDMA_EN_MTH(chp->channel, drive) | 1822 AMD756_UDMA_TIME(chp->channel, drive, 1823 amd756_udma_tim[drvp->UDMA_mode]); 1824 /* can use PIO timings, MW DMA unused */ 1825 mode = drvp->PIO_mode; 1826 } else { 1827 /* use Multiword DMA, but only if revision is OK */ 1828 drvp->drive_flags &= ~DRIVE_UDMA; 1829 #ifndef PCIIDE_AMD756_ENABLEDMA 1830 /* 1831 * The workaround doesn't seem to be necessary 1832 * with all drives, so it can be disabled by 1833 * PCIIDE_AMD756_ENABLEDMA. It causes a hard hang if 1834 * triggered. 1835 */ 1836 if (AMD756_CHIPREV_DISABLEDMA(rev)) { 1837 printf("%s:%d:%d: multi-word DMA disabled due " 1838 "to chip revision\n", 1839 sc->sc_wdcdev.sc_dev.dv_xname, 1840 chp->channel, drive); 1841 mode = drvp->PIO_mode; 1842 drvp->drive_flags &= ~DRIVE_DMA; 1843 goto pio; 1844 } 1845 #endif 1846 /* mode = min(pio, dma+2) */ 1847 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1848 mode = drvp->PIO_mode; 1849 else 1850 mode = drvp->DMA_mode + 2; 1851 } 1852 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1853 1854 pio: /* setup PIO mode */ 1855 if (mode <= 2) { 1856 drvp->DMA_mode = 0; 1857 drvp->PIO_mode = 0; 1858 mode = 0; 1859 } else { 1860 drvp->PIO_mode = mode; 1861 drvp->DMA_mode = mode - 2; 1862 } 1863 datatim_reg |= 1864 AMD756_DATATIM_PULSE(chp->channel, drive, 1865 amd756_pio_set[mode]) | 1866 AMD756_DATATIM_RECOV(chp->channel, drive, 1867 amd756_pio_rec[mode]); 1868 } 1869 if (idedma_ctl != 0) { 1870 /* Add software bits in status register */ 1871 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 1872 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 1873 idedma_ctl); 1874 } 1875 pciide_print_modes(cp); 1876 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_DATATIM, datatim_reg); 1877 pci_conf_write(sc->sc_pc, sc->sc_tag, AMD756_UDMA, udmatim_reg); 1878 } 1879 1880 void 1881 apollo_chip_map(sc, pa) 1882 struct pciide_softc *sc; 1883 struct pci_attach_args *pa; 1884 { 1885 struct pciide_channel *cp; 1886 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 1887 int rev = PCI_REVISION(pa->pa_class); 1888 int channel; 1889 u_int32_t ideconf; 1890 bus_size_t cmdsize, ctlsize; 1891 1892 if (pciide_chipen(sc, pa) == 0) 1893 return; 1894 printf("%s: bus-master DMA support present", 1895 sc->sc_wdcdev.sc_dev.dv_xname); 1896 pciide_mapreg_dma(sc, pa); 1897 printf("\n"); 1898 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 1899 WDC_CAPABILITY_MODE; 1900 if (sc->sc_dma_ok) { 1901 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 1902 sc->sc_wdcdev.irqack = pciide_irqack; 1903 if (sc->sc_pp->ide_product == PCI_PRODUCT_VIATECH_VT82C586A_IDE 1904 && rev >= 6) 1905 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 1906 } 1907 sc->sc_wdcdev.PIO_cap = 4; 1908 sc->sc_wdcdev.DMA_cap = 2; 1909 sc->sc_wdcdev.UDMA_cap = 2; 1910 sc->sc_wdcdev.set_modes = apollo_setup_channel; 1911 sc->sc_wdcdev.channels = sc->wdc_chanarray; 1912 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 1913 1914 WDCDEBUG_PRINT(("apollo_chip_map: old APO_IDECONF=0x%x, " 1915 "APO_CTLMISC=0x%x, APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1916 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF), 1917 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_CTLMISC), 1918 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1919 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), 1920 DEBUG_PROBE); 1921 1922 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 1923 cp = &sc->pciide_channels[channel]; 1924 if (pciide_chansetup(sc, channel, interface) == 0) 1925 continue; 1926 1927 ideconf = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_IDECONF); 1928 if ((ideconf & APO_IDECONF_EN(channel)) == 0) { 1929 printf("%s: %s channel ignored (disabled)\n", 1930 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 1931 continue; 1932 } 1933 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 1934 pciide_pci_intr); 1935 if (cp->hw_ok == 0) 1936 continue; 1937 if (pciide_chan_candisable(cp)) { 1938 ideconf &= ~APO_IDECONF_EN(channel); 1939 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_IDECONF, 1940 ideconf); 1941 } 1942 pciide_map_compat_intr(pa, cp, channel, interface); 1943 1944 if (cp->hw_ok == 0) 1945 continue; 1946 apollo_setup_channel(&sc->pciide_channels[channel].wdc_channel); 1947 } 1948 WDCDEBUG_PRINT(("apollo_chip_map: APO_DATATIM=0x%x, APO_UDMA=0x%x\n", 1949 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM), 1950 pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA)), DEBUG_PROBE); 1951 } 1952 1953 void 1954 apollo_setup_channel(chp) 1955 struct channel_softc *chp; 1956 { 1957 u_int32_t udmatim_reg, datatim_reg; 1958 u_int8_t idedma_ctl; 1959 int mode, drive; 1960 struct ata_drive_datas *drvp; 1961 struct pciide_channel *cp = (struct pciide_channel*)chp; 1962 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 1963 1964 idedma_ctl = 0; 1965 datatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_DATATIM); 1966 udmatim_reg = pci_conf_read(sc->sc_pc, sc->sc_tag, APO_UDMA); 1967 datatim_reg &= ~APO_DATATIM_MASK(chp->channel); 1968 udmatim_reg &= ~AP0_UDMA_MASK(chp->channel); 1969 1970 /* setup DMA if needed */ 1971 pciide_channel_dma_setup(cp); 1972 1973 for (drive = 0; drive < 2; drive++) { 1974 drvp = &chp->ch_drive[drive]; 1975 /* If no drive, skip */ 1976 if ((drvp->drive_flags & DRIVE) == 0) 1977 continue; 1978 /* add timing values, setup DMA if needed */ 1979 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 1980 (drvp->drive_flags & DRIVE_UDMA) == 0)) { 1981 mode = drvp->PIO_mode; 1982 goto pio; 1983 } 1984 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 1985 (drvp->drive_flags & DRIVE_UDMA)) { 1986 /* use Ultra/DMA */ 1987 drvp->drive_flags &= ~DRIVE_DMA; 1988 udmatim_reg |= APO_UDMA_EN(chp->channel, drive) | 1989 APO_UDMA_EN_MTH(chp->channel, drive) | 1990 APO_UDMA_TIME(chp->channel, drive, 1991 apollo_udma_tim[drvp->UDMA_mode]); 1992 /* can use PIO timings, MW DMA unused */ 1993 mode = drvp->PIO_mode; 1994 } else { 1995 /* use Multiword DMA */ 1996 drvp->drive_flags &= ~DRIVE_UDMA; 1997 /* mode = min(pio, dma+2) */ 1998 if (drvp->PIO_mode <= (drvp->DMA_mode +2)) 1999 mode = drvp->PIO_mode; 2000 else 2001 mode = drvp->DMA_mode + 2; 2002 } 2003 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2004 2005 pio: /* setup PIO mode */ 2006 if (mode <= 2) { 2007 drvp->DMA_mode = 0; 2008 drvp->PIO_mode = 0; 2009 mode = 0; 2010 } else { 2011 drvp->PIO_mode = mode; 2012 drvp->DMA_mode = mode - 2; 2013 } 2014 datatim_reg |= 2015 APO_DATATIM_PULSE(chp->channel, drive, 2016 apollo_pio_set[mode]) | 2017 APO_DATATIM_RECOV(chp->channel, drive, 2018 apollo_pio_rec[mode]); 2019 } 2020 if (idedma_ctl != 0) { 2021 /* Add software bits in status register */ 2022 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2023 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2024 idedma_ctl); 2025 } 2026 pciide_print_modes(cp); 2027 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_DATATIM, datatim_reg); 2028 pci_conf_write(sc->sc_pc, sc->sc_tag, APO_UDMA, udmatim_reg); 2029 } 2030 2031 void 2032 cmd_channel_map(pa, sc, channel) 2033 struct pci_attach_args *pa; 2034 struct pciide_softc *sc; 2035 int channel; 2036 { 2037 struct pciide_channel *cp = &sc->pciide_channels[channel]; 2038 bus_size_t cmdsize, ctlsize; 2039 u_int8_t ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CTRL); 2040 int interface; 2041 2042 /* 2043 * The 0648/0649 can be told to identify as a RAID controller. 2044 * In this case, we have to fake interface 2045 */ 2046 if (PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_MASS_STORAGE_IDE) { 2047 interface = PCIIDE_INTERFACE_SETTABLE(0) | 2048 PCIIDE_INTERFACE_SETTABLE(1); 2049 if (pciide_pci_read(pa->pa_pc, pa->pa_tag, CMD_CONF) & 2050 CMD_CONF_DSA1) 2051 interface |= PCIIDE_INTERFACE_PCI(0) | 2052 PCIIDE_INTERFACE_PCI(1); 2053 } else { 2054 interface = PCI_INTERFACE(pa->pa_class); 2055 } 2056 2057 sc->wdc_chanarray[channel] = &cp->wdc_channel; 2058 cp->name = PCIIDE_CHANNEL_NAME(channel); 2059 cp->wdc_channel.channel = channel; 2060 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2061 2062 if (channel > 0) { 2063 cp->wdc_channel.ch_queue = 2064 sc->pciide_channels[0].wdc_channel.ch_queue; 2065 } else { 2066 cp->wdc_channel.ch_queue = 2067 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2068 } 2069 if (cp->wdc_channel.ch_queue == NULL) { 2070 printf("%s %s channel: " 2071 "can't allocate memory for command queue", 2072 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2073 return; 2074 } 2075 2076 printf("%s: %s channel %s to %s mode\n", 2077 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 2078 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 2079 "configured" : "wired", 2080 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 2081 "native-PCI" : "compatibility"); 2082 2083 /* 2084 * with a CMD PCI64x, if we get here, the first channel is enabled: 2085 * there's no way to disable the first channel without disabling 2086 * the whole device 2087 */ 2088 if (channel != 0 && (ctrl & CMD_CTRL_2PORT) == 0) { 2089 printf("%s: %s channel ignored (disabled)\n", 2090 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2091 return; 2092 } 2093 2094 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, cmd_pci_intr); 2095 if (cp->hw_ok == 0) 2096 return; 2097 if (channel == 1) { 2098 if (pciide_chan_candisable(cp)) { 2099 ctrl &= ~CMD_CTRL_2PORT; 2100 pciide_pci_write(pa->pa_pc, pa->pa_tag, 2101 CMD_CTRL, ctrl); 2102 } 2103 } 2104 pciide_map_compat_intr(pa, cp, channel, interface); 2105 } 2106 2107 int 2108 cmd_pci_intr(arg) 2109 void *arg; 2110 { 2111 struct pciide_softc *sc = arg; 2112 struct pciide_channel *cp; 2113 struct channel_softc *wdc_cp; 2114 int i, rv, crv; 2115 u_int32_t priirq, secirq; 2116 2117 rv = 0; 2118 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2119 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2120 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2121 cp = &sc->pciide_channels[i]; 2122 wdc_cp = &cp->wdc_channel; 2123 /* If a compat channel skip. */ 2124 if (cp->compat) 2125 continue; 2126 if ((i == 0 && (priirq & CMD_CONF_DRV0_INTR)) || 2127 (i == 1 && (secirq & CMD_ARTTIM23_IRQ))) { 2128 crv = wdcintr(wdc_cp); 2129 if (crv == 0) 2130 printf("%s:%d: bogus intr\n", 2131 sc->sc_wdcdev.sc_dev.dv_xname, i); 2132 else 2133 rv = 1; 2134 } 2135 } 2136 return rv; 2137 } 2138 2139 void 2140 cmd_chip_map(sc, pa) 2141 struct pciide_softc *sc; 2142 struct pci_attach_args *pa; 2143 { 2144 int channel; 2145 2146 /* 2147 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2148 * and base adresses registers can be disabled at 2149 * hardware level. In this case, the device is wired 2150 * in compat mode and its first channel is always enabled, 2151 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2152 * In fact, it seems that the first channel of the CMD PCI0640 2153 * can't be disabled. 2154 */ 2155 2156 #ifdef PCIIDE_CMD064x_DISABLE 2157 if (pciide_chipen(sc, pa) == 0) 2158 return; 2159 #endif 2160 2161 printf("%s: hardware does not support DMA\n", 2162 sc->sc_wdcdev.sc_dev.dv_xname); 2163 sc->sc_dma_ok = 0; 2164 2165 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2166 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2167 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16; 2168 2169 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2170 cmd_channel_map(pa, sc, channel); 2171 } 2172 } 2173 2174 void 2175 cmd0643_9_chip_map(sc, pa) 2176 struct pciide_softc *sc; 2177 struct pci_attach_args *pa; 2178 { 2179 struct pciide_channel *cp; 2180 int channel; 2181 int rev = PCI_REVISION( 2182 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG)); 2183 2184 /* 2185 * For a CMD PCI064x, the use of PCI_COMMAND_IO_ENABLE 2186 * and base adresses registers can be disabled at 2187 * hardware level. In this case, the device is wired 2188 * in compat mode and its first channel is always enabled, 2189 * but we can't rely on PCI_COMMAND_IO_ENABLE. 2190 * In fact, it seems that the first channel of the CMD PCI0640 2191 * can't be disabled. 2192 */ 2193 2194 #ifdef PCIIDE_CMD064x_DISABLE 2195 if (pciide_chipen(sc, pa) == 0) 2196 return; 2197 #endif 2198 printf("%s: bus-master DMA support present", 2199 sc->sc_wdcdev.sc_dev.dv_xname); 2200 pciide_mapreg_dma(sc, pa); 2201 printf("\n"); 2202 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2203 WDC_CAPABILITY_MODE; 2204 if (sc->sc_dma_ok) { 2205 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2206 switch (sc->sc_pp->ide_product) { 2207 case PCI_PRODUCT_CMDTECH_649: 2208 case PCI_PRODUCT_CMDTECH_648: 2209 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2210 sc->sc_wdcdev.UDMA_cap = 4; 2211 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2212 break; 2213 case PCI_PRODUCT_CMDTECH_646: 2214 if (rev >= CMD0646U2_REV) { 2215 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2216 sc->sc_wdcdev.UDMA_cap = 2; 2217 } else if (rev >= CMD0646U_REV) { 2218 /* 2219 * Linux's driver claims that the 646U is broken 2220 * with UDMA. Only enable it if we know what we're 2221 * doing 2222 */ 2223 #ifdef PCIIDE_CMD0646U_ENABLEUDMA 2224 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2225 sc->sc_wdcdev.UDMA_cap = 2; 2226 #endif 2227 /* explicitely disable UDMA */ 2228 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2229 CMD_UDMATIM(0), 0); 2230 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2231 CMD_UDMATIM(1), 0); 2232 } 2233 sc->sc_wdcdev.irqack = cmd646_9_irqack; 2234 break; 2235 default: 2236 sc->sc_wdcdev.irqack = pciide_irqack; 2237 } 2238 } 2239 2240 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2241 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2242 sc->sc_wdcdev.PIO_cap = 4; 2243 sc->sc_wdcdev.DMA_cap = 2; 2244 sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel; 2245 2246 WDCDEBUG_PRINT(("cmd0643_9_chip_map: old timings reg 0x%x 0x%x\n", 2247 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2248 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2249 DEBUG_PROBE); 2250 2251 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2252 cp = &sc->pciide_channels[channel]; 2253 cmd_channel_map(pa, sc, channel); 2254 if (cp->hw_ok == 0) 2255 continue; 2256 cmd0643_9_setup_channel(&cp->wdc_channel); 2257 } 2258 /* 2259 * note - this also makes sure we clear the irq disable and reset 2260 * bits 2261 */ 2262 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_DMA_MODE, CMD_DMA_MULTIPLE); 2263 WDCDEBUG_PRINT(("cmd0643_9_chip_map: timings reg now 0x%x 0x%x\n", 2264 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54), 2265 pci_conf_read(sc->sc_pc, sc->sc_tag, 0x58)), 2266 DEBUG_PROBE); 2267 } 2268 2269 void 2270 cmd0643_9_setup_channel(chp) 2271 struct channel_softc *chp; 2272 { 2273 struct ata_drive_datas *drvp; 2274 u_int8_t tim; 2275 u_int32_t idedma_ctl, udma_reg; 2276 int drive; 2277 struct pciide_channel *cp = (struct pciide_channel*)chp; 2278 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2279 2280 idedma_ctl = 0; 2281 /* setup DMA if needed */ 2282 pciide_channel_dma_setup(cp); 2283 2284 for (drive = 0; drive < 2; drive++) { 2285 drvp = &chp->ch_drive[drive]; 2286 /* If no drive, skip */ 2287 if ((drvp->drive_flags & DRIVE) == 0) 2288 continue; 2289 /* add timing values, setup DMA if needed */ 2290 tim = cmd0643_9_data_tim_pio[drvp->PIO_mode]; 2291 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 2292 if (drvp->drive_flags & DRIVE_UDMA) { 2293 /* UltraDMA on a 646U2, 0648 or 0649 */ 2294 udma_reg = pciide_pci_read(sc->sc_pc, 2295 sc->sc_tag, CMD_UDMATIM(chp->channel)); 2296 if (drvp->UDMA_mode > 2 && 2297 (pciide_pci_read(sc->sc_pc, sc->sc_tag, 2298 CMD_BICSR) & 2299 CMD_BICSR_80(chp->channel)) == 0) 2300 drvp->UDMA_mode = 2; 2301 if (drvp->UDMA_mode > 2) 2302 udma_reg &= ~CMD_UDMATIM_UDMA33(drive); 2303 else if (sc->sc_wdcdev.UDMA_cap > 2) 2304 udma_reg |= CMD_UDMATIM_UDMA33(drive); 2305 udma_reg |= CMD_UDMATIM_UDMA(drive); 2306 udma_reg &= ~(CMD_UDMATIM_TIM_MASK << 2307 CMD_UDMATIM_TIM_OFF(drive)); 2308 udma_reg |= 2309 (cmd0646_9_tim_udma[drvp->UDMA_mode] << 2310 CMD_UDMATIM_TIM_OFF(drive)); 2311 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2312 CMD_UDMATIM(chp->channel), udma_reg); 2313 } else { 2314 /* 2315 * use Multiword DMA. 2316 * Timings will be used for both PIO and DMA, 2317 * so adjust DMA mode if needed 2318 * if we have a 0646U2/8/9, turn off UDMA 2319 */ 2320 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) { 2321 udma_reg = pciide_pci_read(sc->sc_pc, 2322 sc->sc_tag, 2323 CMD_UDMATIM(chp->channel)); 2324 udma_reg &= ~CMD_UDMATIM_UDMA(drive); 2325 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2326 CMD_UDMATIM(chp->channel), 2327 udma_reg); 2328 } 2329 if (drvp->PIO_mode >= 3 && 2330 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2331 drvp->DMA_mode = drvp->PIO_mode - 2; 2332 } 2333 tim = cmd0643_9_data_tim_dma[drvp->DMA_mode]; 2334 } 2335 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2336 } 2337 pciide_pci_write(sc->sc_pc, sc->sc_tag, 2338 CMD_DATA_TIM(chp->channel, drive), tim); 2339 } 2340 if (idedma_ctl != 0) { 2341 /* Add software bits in status register */ 2342 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2343 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 2344 idedma_ctl); 2345 } 2346 pciide_print_modes(cp); 2347 } 2348 2349 void 2350 cmd646_9_irqack(chp) 2351 struct channel_softc *chp; 2352 { 2353 u_int32_t priirq, secirq; 2354 struct pciide_channel *cp = (struct pciide_channel*)chp; 2355 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2356 2357 if (chp->channel == 0) { 2358 priirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_CONF); 2359 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_CONF, priirq); 2360 } else { 2361 secirq = pciide_pci_read(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23); 2362 pciide_pci_write(sc->sc_pc, sc->sc_tag, CMD_ARTTIM23, secirq); 2363 } 2364 pciide_irqack(chp); 2365 } 2366 2367 void 2368 cy693_chip_map(sc, pa) 2369 struct pciide_softc *sc; 2370 struct pci_attach_args *pa; 2371 { 2372 struct pciide_channel *cp; 2373 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2374 bus_size_t cmdsize, ctlsize; 2375 2376 if (pciide_chipen(sc, pa) == 0) 2377 return; 2378 /* 2379 * this chip has 2 PCI IDE functions, one for primary and one for 2380 * secondary. So we need to call pciide_mapregs_compat() with 2381 * the real channel 2382 */ 2383 if (pa->pa_function == 1) { 2384 sc->sc_cy_compatchan = 0; 2385 } else if (pa->pa_function == 2) { 2386 sc->sc_cy_compatchan = 1; 2387 } else { 2388 printf("%s: unexpected PCI function %d\n", 2389 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2390 return; 2391 } 2392 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 2393 printf("%s: bus-master DMA support present", 2394 sc->sc_wdcdev.sc_dev.dv_xname); 2395 pciide_mapreg_dma(sc, pa); 2396 } else { 2397 printf("%s: hardware does not support DMA", 2398 sc->sc_wdcdev.sc_dev.dv_xname); 2399 sc->sc_dma_ok = 0; 2400 } 2401 printf("\n"); 2402 2403 sc->sc_cy_handle = cy82c693_init(pa->pa_iot); 2404 if (sc->sc_cy_handle == NULL) { 2405 printf("%s: unable to map hyperCache control registers\n", 2406 sc->sc_wdcdev.sc_dev.dv_xname); 2407 sc->sc_dma_ok = 0; 2408 } 2409 2410 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2411 WDC_CAPABILITY_MODE; 2412 if (sc->sc_dma_ok) { 2413 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2414 sc->sc_wdcdev.irqack = pciide_irqack; 2415 } 2416 sc->sc_wdcdev.PIO_cap = 4; 2417 sc->sc_wdcdev.DMA_cap = 2; 2418 sc->sc_wdcdev.set_modes = cy693_setup_channel; 2419 2420 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2421 sc->sc_wdcdev.nchannels = 1; 2422 2423 /* Only one channel for this chip; if we are here it's enabled */ 2424 cp = &sc->pciide_channels[0]; 2425 sc->wdc_chanarray[0] = &cp->wdc_channel; 2426 cp->name = PCIIDE_CHANNEL_NAME(0); 2427 cp->wdc_channel.channel = 0; 2428 cp->wdc_channel.wdc = &sc->sc_wdcdev; 2429 cp->wdc_channel.ch_queue = 2430 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 2431 if (cp->wdc_channel.ch_queue == NULL) { 2432 printf("%s primary channel: " 2433 "can't allocate memory for command queue", 2434 sc->sc_wdcdev.sc_dev.dv_xname); 2435 return; 2436 } 2437 printf("%s: primary channel %s to ", 2438 sc->sc_wdcdev.sc_dev.dv_xname, 2439 (interface & PCIIDE_INTERFACE_SETTABLE(0)) ? 2440 "configured" : "wired"); 2441 if (interface & PCIIDE_INTERFACE_PCI(0)) { 2442 printf("native-PCI"); 2443 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 2444 pciide_pci_intr); 2445 } else { 2446 printf("compatibility"); 2447 cp->hw_ok = pciide_mapregs_compat(pa, cp, sc->sc_cy_compatchan, 2448 &cmdsize, &ctlsize); 2449 } 2450 printf(" mode\n"); 2451 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2452 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2453 wdcattach(&cp->wdc_channel); 2454 if (pciide_chan_candisable(cp)) { 2455 pci_conf_write(sc->sc_pc, sc->sc_tag, 2456 PCI_COMMAND_STATUS_REG, 0); 2457 } 2458 pciide_map_compat_intr(pa, cp, sc->sc_cy_compatchan, interface); 2459 if (cp->hw_ok == 0) 2460 return; 2461 WDCDEBUG_PRINT(("cy693_chip_map: old timings reg 0x%x\n", 2462 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)),DEBUG_PROBE); 2463 cy693_setup_channel(&cp->wdc_channel); 2464 WDCDEBUG_PRINT(("cy693_chip_map: new timings reg 0x%x\n", 2465 pci_conf_read(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL)), DEBUG_PROBE); 2466 } 2467 2468 void 2469 cy693_setup_channel(chp) 2470 struct channel_softc *chp; 2471 { 2472 struct ata_drive_datas *drvp; 2473 int drive; 2474 u_int32_t cy_cmd_ctrl; 2475 u_int32_t idedma_ctl; 2476 struct pciide_channel *cp = (struct pciide_channel*)chp; 2477 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2478 int dma_mode = -1; 2479 2480 cy_cmd_ctrl = idedma_ctl = 0; 2481 2482 /* setup DMA if needed */ 2483 pciide_channel_dma_setup(cp); 2484 2485 for (drive = 0; drive < 2; drive++) { 2486 drvp = &chp->ch_drive[drive]; 2487 /* If no drive, skip */ 2488 if ((drvp->drive_flags & DRIVE) == 0) 2489 continue; 2490 /* add timing values, setup DMA if needed */ 2491 if (drvp->drive_flags & DRIVE_DMA) { 2492 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2493 /* use Multiword DMA */ 2494 if (dma_mode == -1 || dma_mode > drvp->DMA_mode) 2495 dma_mode = drvp->DMA_mode; 2496 } 2497 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2498 CY_CMD_CTRL_IOW_PULSE_OFF(drive)); 2499 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2500 CY_CMD_CTRL_IOW_REC_OFF(drive)); 2501 cy_cmd_ctrl |= (cy_pio_pulse[drvp->PIO_mode] << 2502 CY_CMD_CTRL_IOR_PULSE_OFF(drive)); 2503 cy_cmd_ctrl |= (cy_pio_rec[drvp->PIO_mode] << 2504 CY_CMD_CTRL_IOR_REC_OFF(drive)); 2505 } 2506 pci_conf_write(sc->sc_pc, sc->sc_tag, CY_CMD_CTRL, cy_cmd_ctrl); 2507 chp->ch_drive[0].DMA_mode = dma_mode; 2508 chp->ch_drive[1].DMA_mode = dma_mode; 2509 2510 if (dma_mode == -1) 2511 dma_mode = 0; 2512 2513 if (sc->sc_cy_handle != NULL) { 2514 /* Note: `multiple' is implied. */ 2515 cy82c693_write(sc->sc_cy_handle, 2516 (sc->sc_cy_compatchan == 0) ? 2517 CY_DMA_IDX_PRIMARY : CY_DMA_IDX_SECONDARY, dma_mode); 2518 } 2519 2520 pciide_print_modes(cp); 2521 2522 if (idedma_ctl != 0) { 2523 /* Add software bits in status register */ 2524 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2525 IDEDMA_CTL, idedma_ctl); 2526 } 2527 } 2528 2529 void 2530 sis_chip_map(sc, pa) 2531 struct pciide_softc *sc; 2532 struct pci_attach_args *pa; 2533 { 2534 struct pciide_channel *cp; 2535 int channel; 2536 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 2537 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 2538 pcireg_t rev = PCI_REVISION(pa->pa_class); 2539 bus_size_t cmdsize, ctlsize; 2540 2541 if (pciide_chipen(sc, pa) == 0) 2542 return; 2543 printf("%s: bus-master DMA support present", 2544 sc->sc_wdcdev.sc_dev.dv_xname); 2545 pciide_mapreg_dma(sc, pa); 2546 printf("\n"); 2547 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2548 WDC_CAPABILITY_MODE; 2549 if (sc->sc_dma_ok) { 2550 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 2551 sc->sc_wdcdev.irqack = pciide_irqack; 2552 if (rev >= 0xd0) 2553 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 2554 } 2555 2556 sc->sc_wdcdev.PIO_cap = 4; 2557 sc->sc_wdcdev.DMA_cap = 2; 2558 if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) 2559 sc->sc_wdcdev.UDMA_cap = 2; 2560 sc->sc_wdcdev.set_modes = sis_setup_channel; 2561 2562 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2563 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2564 2565 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 2566 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 2567 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE); 2568 2569 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2570 cp = &sc->pciide_channels[channel]; 2571 if (pciide_chansetup(sc, channel, interface) == 0) 2572 continue; 2573 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 2574 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 2575 printf("%s: %s channel ignored (disabled)\n", 2576 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2577 continue; 2578 } 2579 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2580 pciide_pci_intr); 2581 if (cp->hw_ok == 0) 2582 continue; 2583 if (pciide_chan_candisable(cp)) { 2584 if (channel == 0) 2585 sis_ctr0 &= ~SIS_CTRL0_CHAN0_EN; 2586 else 2587 sis_ctr0 &= ~SIS_CTRL0_CHAN1_EN; 2588 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_CTRL0, 2589 sis_ctr0); 2590 } 2591 pciide_map_compat_intr(pa, cp, channel, interface); 2592 if (cp->hw_ok == 0) 2593 continue; 2594 sis_setup_channel(&cp->wdc_channel); 2595 } 2596 } 2597 2598 void 2599 sis_setup_channel(chp) 2600 struct channel_softc *chp; 2601 { 2602 struct ata_drive_datas *drvp; 2603 int drive; 2604 u_int32_t sis_tim; 2605 u_int32_t idedma_ctl; 2606 struct pciide_channel *cp = (struct pciide_channel*)chp; 2607 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2608 2609 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 2610 "channel %d 0x%x\n", chp->channel, 2611 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 2612 DEBUG_PROBE); 2613 sis_tim = 0; 2614 idedma_ctl = 0; 2615 /* setup DMA if needed */ 2616 pciide_channel_dma_setup(cp); 2617 2618 for (drive = 0; drive < 2; drive++) { 2619 drvp = &chp->ch_drive[drive]; 2620 /* If no drive, skip */ 2621 if ((drvp->drive_flags & DRIVE) == 0) 2622 continue; 2623 /* add timing values, setup DMA if needed */ 2624 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2625 (drvp->drive_flags & DRIVE_UDMA) == 0) 2626 goto pio; 2627 2628 if (drvp->drive_flags & DRIVE_UDMA) { 2629 /* use Ultra/DMA */ 2630 drvp->drive_flags &= ~DRIVE_DMA; 2631 sis_tim |= sis_udma_tim[drvp->UDMA_mode] << 2632 SIS_TIM_UDMA_TIME_OFF(drive); 2633 sis_tim |= SIS_TIM_UDMA_EN(drive); 2634 } else { 2635 /* 2636 * use Multiword DMA 2637 * Timings will be used for both PIO and DMA, 2638 * so adjust DMA mode if needed 2639 */ 2640 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2641 drvp->PIO_mode = drvp->DMA_mode + 2; 2642 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2643 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2644 drvp->PIO_mode - 2 : 0; 2645 if (drvp->DMA_mode == 0) 2646 drvp->PIO_mode = 0; 2647 } 2648 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2649 pio: sis_tim |= sis_pio_act[drvp->PIO_mode] << 2650 SIS_TIM_ACT_OFF(drive); 2651 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 2652 SIS_TIM_REC_OFF(drive); 2653 } 2654 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 2655 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 2656 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 2657 if (idedma_ctl != 0) { 2658 /* Add software bits in status register */ 2659 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2660 IDEDMA_CTL, idedma_ctl); 2661 } 2662 pciide_print_modes(cp); 2663 } 2664 2665 void 2666 acer_chip_map(sc, pa) 2667 struct pciide_softc *sc; 2668 struct pci_attach_args *pa; 2669 { 2670 struct pciide_channel *cp; 2671 int channel; 2672 pcireg_t cr, interface; 2673 bus_size_t cmdsize, ctlsize; 2674 2675 if (pciide_chipen(sc, pa) == 0) 2676 return; 2677 printf("%s: bus-master DMA support present", 2678 sc->sc_wdcdev.sc_dev.dv_xname); 2679 pciide_mapreg_dma(sc, pa); 2680 printf("\n"); 2681 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2682 WDC_CAPABILITY_MODE; 2683 if (sc->sc_dma_ok) { 2684 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2685 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2686 sc->sc_wdcdev.irqack = pciide_irqack; 2687 } 2688 2689 sc->sc_wdcdev.PIO_cap = 4; 2690 sc->sc_wdcdev.DMA_cap = 2; 2691 sc->sc_wdcdev.UDMA_cap = 2; 2692 sc->sc_wdcdev.set_modes = acer_setup_channel; 2693 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2694 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 2695 2696 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC, 2697 (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) | 2698 ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE); 2699 2700 /* Enable "microsoft register bits" R/W. */ 2701 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3, 2702 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI); 2703 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1, 2704 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) & 2705 ~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1))); 2706 pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2, 2707 pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) & 2708 ~ACER_CHANSTATUSREGS_RO); 2709 cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG); 2710 cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT); 2711 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr); 2712 /* Don't use cr, re-read the real register content instead */ 2713 interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag, 2714 PCI_CLASS_REG)); 2715 2716 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 2717 cp = &sc->pciide_channels[channel]; 2718 if (pciide_chansetup(sc, channel, interface) == 0) 2719 continue; 2720 if ((interface & PCIIDE_CHAN_EN(channel)) == 0) { 2721 printf("%s: %s channel ignored (disabled)\n", 2722 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2723 continue; 2724 } 2725 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 2726 acer_pci_intr); 2727 if (cp->hw_ok == 0) 2728 continue; 2729 if (pciide_chan_candisable(cp)) { 2730 cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT); 2731 pci_conf_write(sc->sc_pc, sc->sc_tag, 2732 PCI_CLASS_REG, cr); 2733 } 2734 pciide_map_compat_intr(pa, cp, channel, interface); 2735 acer_setup_channel(&cp->wdc_channel); 2736 } 2737 } 2738 2739 void 2740 acer_setup_channel(chp) 2741 struct channel_softc *chp; 2742 { 2743 struct ata_drive_datas *drvp; 2744 int drive; 2745 u_int32_t acer_fifo_udma; 2746 u_int32_t idedma_ctl; 2747 struct pciide_channel *cp = (struct pciide_channel*)chp; 2748 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2749 2750 idedma_ctl = 0; 2751 acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA); 2752 WDCDEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n", 2753 acer_fifo_udma), DEBUG_PROBE); 2754 /* setup DMA if needed */ 2755 pciide_channel_dma_setup(cp); 2756 2757 for (drive = 0; drive < 2; drive++) { 2758 drvp = &chp->ch_drive[drive]; 2759 /* If no drive, skip */ 2760 if ((drvp->drive_flags & DRIVE) == 0) 2761 continue; 2762 WDCDEBUG_PRINT(("acer_setup_channel: old timings reg for " 2763 "channel %d drive %d 0x%x\n", chp->channel, drive, 2764 pciide_pci_read(sc->sc_pc, sc->sc_tag, 2765 ACER_IDETIM(chp->channel, drive))), DEBUG_PROBE); 2766 /* clear FIFO/DMA mode */ 2767 acer_fifo_udma &= ~(ACER_FTH_OPL(chp->channel, drive, 0x3) | 2768 ACER_UDMA_EN(chp->channel, drive) | 2769 ACER_UDMA_TIM(chp->channel, drive, 0x7)); 2770 2771 /* add timing values, setup DMA if needed */ 2772 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 2773 (drvp->drive_flags & DRIVE_UDMA) == 0) { 2774 acer_fifo_udma |= 2775 ACER_FTH_OPL(chp->channel, drive, 0x1); 2776 goto pio; 2777 } 2778 2779 acer_fifo_udma |= ACER_FTH_OPL(chp->channel, drive, 0x2); 2780 if (drvp->drive_flags & DRIVE_UDMA) { 2781 /* use Ultra/DMA */ 2782 drvp->drive_flags &= ~DRIVE_DMA; 2783 acer_fifo_udma |= ACER_UDMA_EN(chp->channel, drive); 2784 acer_fifo_udma |= 2785 ACER_UDMA_TIM(chp->channel, drive, 2786 acer_udma[drvp->UDMA_mode]); 2787 } else { 2788 /* 2789 * use Multiword DMA 2790 * Timings will be used for both PIO and DMA, 2791 * so adjust DMA mode if needed 2792 */ 2793 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 2794 drvp->PIO_mode = drvp->DMA_mode + 2; 2795 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 2796 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 2797 drvp->PIO_mode - 2 : 0; 2798 if (drvp->DMA_mode == 0) 2799 drvp->PIO_mode = 0; 2800 } 2801 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2802 pio: pciide_pci_write(sc->sc_pc, sc->sc_tag, 2803 ACER_IDETIM(chp->channel, drive), 2804 acer_pio[drvp->PIO_mode]); 2805 } 2806 WDCDEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n", 2807 acer_fifo_udma), DEBUG_PROBE); 2808 pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma); 2809 if (idedma_ctl != 0) { 2810 /* Add software bits in status register */ 2811 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 2812 IDEDMA_CTL, idedma_ctl); 2813 } 2814 pciide_print_modes(cp); 2815 } 2816 2817 int 2818 acer_pci_intr(arg) 2819 void *arg; 2820 { 2821 struct pciide_softc *sc = arg; 2822 struct pciide_channel *cp; 2823 struct channel_softc *wdc_cp; 2824 int i, rv, crv; 2825 u_int32_t chids; 2826 2827 rv = 0; 2828 chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS); 2829 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2830 cp = &sc->pciide_channels[i]; 2831 wdc_cp = &cp->wdc_channel; 2832 /* If a compat channel skip. */ 2833 if (cp->compat) 2834 continue; 2835 if (chids & ACER_CHIDS_INT(i)) { 2836 crv = wdcintr(wdc_cp); 2837 if (crv == 0) 2838 printf("%s:%d: bogus intr\n", 2839 sc->sc_wdcdev.sc_dev.dv_xname, i); 2840 else 2841 rv = 1; 2842 } 2843 } 2844 return rv; 2845 } 2846 2847 void 2848 hpt_chip_map(sc, pa) 2849 struct pciide_softc *sc; 2850 struct pci_attach_args *pa; 2851 { 2852 struct pciide_channel *cp; 2853 int i, compatchan, revision; 2854 pcireg_t interface; 2855 bus_size_t cmdsize, ctlsize; 2856 2857 if (pciide_chipen(sc, pa) == 0) 2858 return; 2859 revision = PCI_REVISION(pa->pa_class); 2860 2861 /* 2862 * when the chip is in native mode it identifies itself as a 2863 * 'misc mass storage'. Fake interface in this case. 2864 */ 2865 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 2866 interface = PCI_INTERFACE(pa->pa_class); 2867 } else { 2868 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 2869 PCIIDE_INTERFACE_PCI(0); 2870 if (revision == HPT370_REV) 2871 interface |= PCIIDE_INTERFACE_PCI(1); 2872 } 2873 2874 printf("%s: bus-master DMA support present", 2875 sc->sc_wdcdev.sc_dev.dv_xname); 2876 pciide_mapreg_dma(sc, pa); 2877 printf("\n"); 2878 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 2879 WDC_CAPABILITY_MODE; 2880 if (sc->sc_dma_ok) { 2881 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 2882 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 2883 sc->sc_wdcdev.irqack = pciide_irqack; 2884 } 2885 sc->sc_wdcdev.PIO_cap = 4; 2886 sc->sc_wdcdev.DMA_cap = 2; 2887 sc->sc_wdcdev.UDMA_cap = 4; 2888 2889 sc->sc_wdcdev.set_modes = hpt_setup_channel; 2890 sc->sc_wdcdev.channels = sc->wdc_chanarray; 2891 if (revision == HPT366_REV) { 2892 /* 2893 * The 366 has 2 PCI IDE functions, one for primary and one 2894 * for secondary. So we need to call pciide_mapregs_compat() 2895 * with the real channel 2896 */ 2897 if (pa->pa_function == 0) { 2898 compatchan = 0; 2899 } else if (pa->pa_function == 1) { 2900 compatchan = 1; 2901 } else { 2902 printf("%s: unexpected PCI function %d\n", 2903 sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function); 2904 return; 2905 } 2906 sc->sc_wdcdev.nchannels = 1; 2907 } else { 2908 sc->sc_wdcdev.nchannels = 2; 2909 } 2910 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 2911 cp = &sc->pciide_channels[i]; 2912 if (sc->sc_wdcdev.nchannels > 1) { 2913 compatchan = i; 2914 if((pciide_pci_read(sc->sc_pc, sc->sc_tag, 2915 HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) { 2916 printf("%s: %s channel ignored (disabled)\n", 2917 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 2918 continue; 2919 } 2920 } 2921 if (pciide_chansetup(sc, i, interface) == 0) 2922 continue; 2923 if (interface & PCIIDE_INTERFACE_PCI(i)) { 2924 cp->hw_ok = pciide_mapregs_native(pa, cp, &cmdsize, 2925 &ctlsize, hpt_pci_intr); 2926 } else { 2927 cp->hw_ok = pciide_mapregs_compat(pa, cp, compatchan, 2928 &cmdsize, &ctlsize); 2929 } 2930 if (cp->hw_ok == 0) 2931 return; 2932 cp->wdc_channel.data32iot = cp->wdc_channel.cmd_iot; 2933 cp->wdc_channel.data32ioh = cp->wdc_channel.cmd_ioh; 2934 wdcattach(&cp->wdc_channel); 2935 hpt_setup_channel(&cp->wdc_channel); 2936 } 2937 if (revision == HPT370_REV) { 2938 /* 2939 * HPT370_REV has a bit to disable interrupts, make sure 2940 * to clear it 2941 */ 2942 pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL, 2943 pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) & 2944 ~HPT_CSEL_IRQDIS); 2945 } 2946 return; 2947 } 2948 2949 2950 void 2951 hpt_setup_channel(chp) 2952 struct channel_softc *chp; 2953 { 2954 struct ata_drive_datas *drvp; 2955 int drive; 2956 int cable; 2957 u_int32_t before, after; 2958 u_int32_t idedma_ctl; 2959 struct pciide_channel *cp = (struct pciide_channel*)chp; 2960 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 2961 2962 cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL); 2963 2964 /* setup DMA if needed */ 2965 pciide_channel_dma_setup(cp); 2966 2967 idedma_ctl = 0; 2968 2969 /* Per drive settings */ 2970 for (drive = 0; drive < 2; drive++) { 2971 drvp = &chp->ch_drive[drive]; 2972 /* If no drive, skip */ 2973 if ((drvp->drive_flags & DRIVE) == 0) 2974 continue; 2975 before = pci_conf_read(sc->sc_pc, sc->sc_tag, 2976 HPT_IDETIM(chp->channel, drive)); 2977 2978 /* add timing values, setup DMA if needed */ 2979 if (drvp->drive_flags & DRIVE_UDMA) { 2980 if ((cable & HPT_CSEL_CBLID(chp->channel)) != 0 && 2981 drvp->UDMA_mode > 2) 2982 drvp->UDMA_mode = 2; 2983 after = (sc->sc_wdcdev.nchannels == 2) ? 2984 hpt370_udma[drvp->UDMA_mode] : 2985 hpt366_udma[drvp->UDMA_mode]; 2986 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 2987 } else if (drvp->drive_flags & DRIVE_DMA) { 2988 /* 2989 * use Multiword DMA. 2990 * Timings will be used for both PIO and DMA, so adjust 2991 * DMA mode if needed 2992 */ 2993 if (drvp->PIO_mode >= 3 && 2994 (drvp->DMA_mode + 2) > drvp->PIO_mode) { 2995 drvp->DMA_mode = drvp->PIO_mode - 2; 2996 } 2997 after = (sc->sc_wdcdev.nchannels == 2) ? 2998 hpt370_dma[drvp->DMA_mode] : 2999 hpt366_dma[drvp->DMA_mode]; 3000 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3001 } else { 3002 /* PIO only */ 3003 after = (sc->sc_wdcdev.nchannels == 2) ? 3004 hpt370_pio[drvp->PIO_mode] : 3005 hpt366_pio[drvp->PIO_mode]; 3006 } 3007 pci_conf_write(sc->sc_pc, sc->sc_tag, 3008 HPT_IDETIM(chp->channel, drive), after); 3009 WDCDEBUG_PRINT(("%s: bus speed register set to 0x%08x " 3010 "(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname, 3011 after, before), DEBUG_PROBE); 3012 } 3013 if (idedma_ctl != 0) { 3014 /* Add software bits in status register */ 3015 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3016 IDEDMA_CTL, idedma_ctl); 3017 } 3018 pciide_print_modes(cp); 3019 } 3020 3021 int 3022 hpt_pci_intr(arg) 3023 void *arg; 3024 { 3025 struct pciide_softc *sc = arg; 3026 struct pciide_channel *cp; 3027 struct channel_softc *wdc_cp; 3028 int rv = 0; 3029 int dmastat, i, crv; 3030 3031 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3032 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3033 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 3034 if((dmastat & IDEDMA_CTL_INTR) == 0) 3035 continue; 3036 cp = &sc->pciide_channels[i]; 3037 wdc_cp = &cp->wdc_channel; 3038 crv = wdcintr(wdc_cp); 3039 if (crv == 0) { 3040 printf("%s:%d: bogus intr\n", 3041 sc->sc_wdcdev.sc_dev.dv_xname, i); 3042 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3043 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 3044 } else 3045 rv = 1; 3046 } 3047 return rv; 3048 } 3049 3050 3051 /* A macro to test product */ 3052 #define PDC_IS_262(sc) \ 3053 ((sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA66 || \ 3054 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100 || \ 3055 (sc)->sc_pp->ide_product == PCI_PRODUCT_PROMISE_ULTRA100X) 3056 3057 void 3058 pdc202xx_chip_map(sc, pa) 3059 struct pciide_softc *sc; 3060 struct pci_attach_args *pa; 3061 { 3062 struct pciide_channel *cp; 3063 int channel; 3064 pcireg_t interface, st, mode; 3065 bus_size_t cmdsize, ctlsize; 3066 3067 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3068 WDCDEBUG_PRINT(("pdc202xx_setup_chip: controller state 0x%x\n", st), 3069 DEBUG_PROBE); 3070 if (pciide_chipen(sc, pa) == 0) 3071 return; 3072 3073 /* turn off RAID mode */ 3074 st &= ~PDC2xx_STATE_IDERAID; 3075 3076 /* 3077 * can't rely on the PCI_CLASS_REG content if the chip was in raid 3078 * mode. We have to fake interface 3079 */ 3080 interface = PCIIDE_INTERFACE_SETTABLE(0) | PCIIDE_INTERFACE_SETTABLE(1); 3081 if (st & PDC2xx_STATE_NATIVE) 3082 interface |= PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 3083 3084 printf("%s: bus-master DMA support present", 3085 sc->sc_wdcdev.sc_dev.dv_xname); 3086 pciide_mapreg_dma(sc, pa); 3087 printf("\n"); 3088 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3089 WDC_CAPABILITY_MODE; 3090 if (sc->sc_dma_ok) { 3091 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 3092 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 3093 sc->sc_wdcdev.irqack = pciide_irqack; 3094 } 3095 sc->sc_wdcdev.PIO_cap = 4; 3096 sc->sc_wdcdev.DMA_cap = 2; 3097 if (PDC_IS_262(sc)) 3098 sc->sc_wdcdev.UDMA_cap = 4; 3099 else 3100 sc->sc_wdcdev.UDMA_cap = 2; 3101 sc->sc_wdcdev.set_modes = pdc202xx_setup_channel; 3102 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3103 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3104 3105 /* setup failsafe defaults */ 3106 mode = 0; 3107 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[0]); 3108 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[0]); 3109 mode = PDC2xx_TIM_SET_MB(mode, pdc2xx_dma_mb[0]); 3110 mode = PDC2xx_TIM_SET_MC(mode, pdc2xx_dma_mc[0]); 3111 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3112 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 0 " 3113 "initial timings 0x%x, now 0x%x\n", channel, 3114 pci_conf_read(sc->sc_pc, sc->sc_tag, 3115 PDC2xx_TIM(channel, 0)), mode | PDC2xx_TIM_IORDYp), 3116 DEBUG_PROBE); 3117 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 0), 3118 mode | PDC2xx_TIM_IORDYp); 3119 WDCDEBUG_PRINT(("pdc202xx_setup_chip: channel %d drive 1 " 3120 "initial timings 0x%x, now 0x%x\n", channel, 3121 pci_conf_read(sc->sc_pc, sc->sc_tag, 3122 PDC2xx_TIM(channel, 1)), mode), DEBUG_PROBE); 3123 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_TIM(channel, 1), 3124 mode); 3125 } 3126 3127 mode = PDC2xx_SCR_DMA; 3128 if (PDC_IS_262(sc)) { 3129 mode = PDC2xx_SCR_SET_GEN(mode, PDC262_SCR_GEN_LAT); 3130 } else { 3131 /* the BIOS set it up this way */ 3132 mode = PDC2xx_SCR_SET_GEN(mode, 0x1); 3133 } 3134 mode = PDC2xx_SCR_SET_I2C(mode, 0x3); /* ditto */ 3135 mode = PDC2xx_SCR_SET_POLL(mode, 0x1); /* ditto */ 3136 WDCDEBUG_PRINT(("pdc202xx_setup_chip: initial SCR 0x%x, now 0x%x\n", 3137 bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR), mode), 3138 DEBUG_PROBE); 3139 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR, mode); 3140 3141 /* controller initial state register is OK even without BIOS */ 3142 /* Set DMA mode to IDE DMA compatibility */ 3143 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM); 3144 WDCDEBUG_PRINT(("pdc202xx_setup_chip: primary mode 0x%x", mode ), 3145 DEBUG_PROBE); 3146 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_PM, 3147 mode | 0x1); 3148 mode = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM); 3149 WDCDEBUG_PRINT((", secondary mode 0x%x\n", mode ), DEBUG_PROBE); 3150 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SM, 3151 mode | 0x1); 3152 3153 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3154 cp = &sc->pciide_channels[channel]; 3155 if (pciide_chansetup(sc, channel, interface) == 0) 3156 continue; 3157 if ((st & (PDC_IS_262(sc) ? 3158 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel))) == 0) { 3159 printf("%s: %s channel ignored (disabled)\n", 3160 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3161 continue; 3162 } 3163 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3164 pdc202xx_pci_intr); 3165 if (cp->hw_ok == 0) 3166 continue; 3167 if (pciide_chan_candisable(cp)) 3168 st &= ~(PDC_IS_262(sc) ? 3169 PDC262_STATE_EN(channel):PDC246_STATE_EN(channel)); 3170 pciide_map_compat_intr(pa, cp, channel, interface); 3171 pdc202xx_setup_channel(&cp->wdc_channel); 3172 } 3173 WDCDEBUG_PRINT(("pdc202xx_setup_chip: new controller state 0x%x\n", st), 3174 DEBUG_PROBE); 3175 pci_conf_write(sc->sc_pc, sc->sc_tag, PDC2xx_STATE, st); 3176 return; 3177 } 3178 3179 void 3180 pdc202xx_setup_channel(chp) 3181 struct channel_softc *chp; 3182 { 3183 struct ata_drive_datas *drvp; 3184 int drive; 3185 pcireg_t mode, st; 3186 u_int32_t idedma_ctl, scr, atapi; 3187 struct pciide_channel *cp = (struct pciide_channel*)chp; 3188 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3189 int channel = chp->channel; 3190 3191 /* setup DMA if needed */ 3192 pciide_channel_dma_setup(cp); 3193 3194 idedma_ctl = 0; 3195 3196 /* Per channel settings */ 3197 if (PDC_IS_262(sc)) { 3198 scr = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3199 PDC262_U66); 3200 st = pci_conf_read(sc->sc_pc, sc->sc_tag, PDC2xx_STATE); 3201 /* Trimm UDMA mode */ 3202 if ((st & PDC262_STATE_80P(channel)) != 0 || 3203 (chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3204 chp->ch_drive[0].UDMA_mode <= 2) || 3205 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3206 chp->ch_drive[1].UDMA_mode <= 2)) { 3207 if (chp->ch_drive[0].UDMA_mode > 2) 3208 chp->ch_drive[0].UDMA_mode = 2; 3209 if (chp->ch_drive[1].UDMA_mode > 2) 3210 chp->ch_drive[1].UDMA_mode = 2; 3211 } 3212 /* Set U66 if needed */ 3213 if ((chp->ch_drive[0].drive_flags & DRIVE_UDMA && 3214 chp->ch_drive[0].UDMA_mode > 2) || 3215 (chp->ch_drive[1].drive_flags & DRIVE_UDMA && 3216 chp->ch_drive[1].UDMA_mode > 2)) 3217 scr |= PDC262_U66_EN(channel); 3218 else 3219 scr &= ~PDC262_U66_EN(channel); 3220 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3221 PDC262_U66, scr); 3222 if (chp->ch_drive[0].drive_flags & DRIVE_ATAPI || 3223 chp->ch_drive[1].drive_flags & DRIVE_ATAPI) { 3224 if (((chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3225 !(chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3226 (chp->ch_drive[1].drive_flags & DRIVE_DMA)) || 3227 ((chp->ch_drive[1].drive_flags & DRIVE_UDMA) && 3228 !(chp->ch_drive[0].drive_flags & DRIVE_UDMA) && 3229 (chp->ch_drive[0].drive_flags & DRIVE_DMA))) 3230 atapi = 0; 3231 else 3232 atapi = PDC262_ATAPI_UDMA; 3233 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 3234 PDC262_ATAPI(channel), atapi); 3235 } 3236 } 3237 for (drive = 0; drive < 2; drive++) { 3238 drvp = &chp->ch_drive[drive]; 3239 /* If no drive, skip */ 3240 if ((drvp->drive_flags & DRIVE) == 0) 3241 continue; 3242 mode = 0; 3243 if (drvp->drive_flags & DRIVE_UDMA) { 3244 mode = PDC2xx_TIM_SET_MB(mode, 3245 pdc2xx_udma_mb[drvp->UDMA_mode]); 3246 mode = PDC2xx_TIM_SET_MC(mode, 3247 pdc2xx_udma_mc[drvp->UDMA_mode]); 3248 drvp->drive_flags &= ~DRIVE_DMA; 3249 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3250 } else if (drvp->drive_flags & DRIVE_DMA) { 3251 mode = PDC2xx_TIM_SET_MB(mode, 3252 pdc2xx_dma_mb[drvp->DMA_mode]); 3253 mode = PDC2xx_TIM_SET_MC(mode, 3254 pdc2xx_dma_mc[drvp->DMA_mode]); 3255 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 3256 } else { 3257 mode = PDC2xx_TIM_SET_MB(mode, 3258 pdc2xx_dma_mb[0]); 3259 mode = PDC2xx_TIM_SET_MC(mode, 3260 pdc2xx_dma_mc[0]); 3261 } 3262 mode = PDC2xx_TIM_SET_PA(mode, pdc2xx_pa[drvp->PIO_mode]); 3263 mode = PDC2xx_TIM_SET_PB(mode, pdc2xx_pb[drvp->PIO_mode]); 3264 if (drvp->drive_flags & DRIVE_ATA) 3265 mode |= PDC2xx_TIM_PRE; 3266 mode |= PDC2xx_TIM_SYNC | PDC2xx_TIM_ERRDY; 3267 if (drvp->PIO_mode >= 3) { 3268 mode |= PDC2xx_TIM_IORDY; 3269 if (drive == 0) 3270 mode |= PDC2xx_TIM_IORDYp; 3271 } 3272 WDCDEBUG_PRINT(("pdc202xx_setup_channel: %s:%d:%d " 3273 "timings 0x%x\n", 3274 sc->sc_wdcdev.sc_dev.dv_xname, 3275 chp->channel, drive, mode), DEBUG_PROBE); 3276 pci_conf_write(sc->sc_pc, sc->sc_tag, 3277 PDC2xx_TIM(chp->channel, drive), mode); 3278 } 3279 if (idedma_ctl != 0) { 3280 /* Add software bits in status register */ 3281 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 3282 IDEDMA_CTL, idedma_ctl); 3283 } 3284 pciide_print_modes(cp); 3285 } 3286 3287 int 3288 pdc202xx_pci_intr(arg) 3289 void *arg; 3290 { 3291 struct pciide_softc *sc = arg; 3292 struct pciide_channel *cp; 3293 struct channel_softc *wdc_cp; 3294 int i, rv, crv; 3295 u_int32_t scr; 3296 3297 rv = 0; 3298 scr = bus_space_read_4(sc->sc_dma_iot, sc->sc_dma_ioh, PDC2xx_SCR); 3299 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 3300 cp = &sc->pciide_channels[i]; 3301 wdc_cp = &cp->wdc_channel; 3302 /* If a compat channel skip. */ 3303 if (cp->compat) 3304 continue; 3305 if (scr & PDC2xx_SCR_INT(i)) { 3306 crv = wdcintr(wdc_cp); 3307 if (crv == 0) 3308 printf("%s:%d: bogus intr\n", 3309 sc->sc_wdcdev.sc_dev.dv_xname, i); 3310 else 3311 rv = 1; 3312 } 3313 } 3314 return rv; 3315 } 3316 3317 void 3318 opti_chip_map(sc, pa) 3319 struct pciide_softc *sc; 3320 struct pci_attach_args *pa; 3321 { 3322 struct pciide_channel *cp; 3323 bus_size_t cmdsize, ctlsize; 3324 pcireg_t interface; 3325 u_int8_t init_ctrl; 3326 int channel; 3327 3328 if (pciide_chipen(sc, pa) == 0) 3329 return; 3330 printf("%s: bus-master DMA support present", 3331 sc->sc_wdcdev.sc_dev.dv_xname); 3332 pciide_mapreg_dma(sc, pa); 3333 printf("\n"); 3334 3335 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 3336 WDC_CAPABILITY_MODE; 3337 sc->sc_wdcdev.PIO_cap = 4; 3338 if (sc->sc_dma_ok) { 3339 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 3340 sc->sc_wdcdev.irqack = pciide_irqack; 3341 sc->sc_wdcdev.DMA_cap = 2; 3342 } 3343 sc->sc_wdcdev.set_modes = opti_setup_channel; 3344 3345 sc->sc_wdcdev.channels = sc->wdc_chanarray; 3346 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 3347 3348 init_ctrl = pciide_pci_read(sc->sc_pc, sc->sc_tag, 3349 OPTI_REG_INIT_CONTROL); 3350 3351 interface = PCI_INTERFACE(pa->pa_class); 3352 3353 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 3354 cp = &sc->pciide_channels[channel]; 3355 if (pciide_chansetup(sc, channel, interface) == 0) 3356 continue; 3357 if (channel == 1 && 3358 (init_ctrl & OPTI_INIT_CONTROL_CH2_DISABLE) != 0) { 3359 printf("%s: %s channel ignored (disabled)\n", 3360 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 3361 continue; 3362 } 3363 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 3364 pciide_pci_intr); 3365 if (cp->hw_ok == 0) 3366 continue; 3367 pciide_map_compat_intr(pa, cp, channel, interface); 3368 if (cp->hw_ok == 0) 3369 continue; 3370 opti_setup_channel(&cp->wdc_channel); 3371 } 3372 } 3373 3374 void 3375 opti_setup_channel(chp) 3376 struct channel_softc *chp; 3377 { 3378 struct ata_drive_datas *drvp; 3379 struct pciide_channel *cp = (struct pciide_channel*)chp; 3380 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 3381 int drive, spd; 3382 int mode[2]; 3383 u_int8_t rv, mr; 3384 3385 /* 3386 * The `Delay' and `Address Setup Time' fields of the 3387 * Miscellaneous Register are always zero initially. 3388 */ 3389 mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK; 3390 mr &= ~(OPTI_MISC_DELAY_MASK | 3391 OPTI_MISC_ADDR_SETUP_MASK | 3392 OPTI_MISC_INDEX_MASK); 3393 3394 /* Prime the control register before setting timing values */ 3395 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_DISABLE); 3396 3397 /* Determine the clockrate of the PCIbus the chip is attached to */ 3398 spd = (int) opti_read_config(chp, OPTI_REG_STRAP); 3399 spd &= OPTI_STRAP_PCI_SPEED_MASK; 3400 3401 /* setup DMA if needed */ 3402 pciide_channel_dma_setup(cp); 3403 3404 for (drive = 0; drive < 2; drive++) { 3405 drvp = &chp->ch_drive[drive]; 3406 /* If no drive, skip */ 3407 if ((drvp->drive_flags & DRIVE) == 0) { 3408 mode[drive] = -1; 3409 continue; 3410 } 3411 3412 if ((drvp->drive_flags & DRIVE_DMA)) { 3413 /* 3414 * Timings will be used for both PIO and DMA, 3415 * so adjust DMA mode if needed 3416 */ 3417 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 3418 drvp->PIO_mode = drvp->DMA_mode + 2; 3419 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 3420 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 3421 drvp->PIO_mode - 2 : 0; 3422 if (drvp->DMA_mode == 0) 3423 drvp->PIO_mode = 0; 3424 3425 mode[drive] = drvp->DMA_mode + 5; 3426 } else 3427 mode[drive] = drvp->PIO_mode; 3428 3429 if (drive && mode[0] >= 0 && 3430 (opti_tim_as[spd][mode[0]] != opti_tim_as[spd][mode[1]])) { 3431 /* 3432 * Can't have two drives using different values 3433 * for `Address Setup Time'. 3434 * Slow down the faster drive to compensate. 3435 */ 3436 int d = (opti_tim_as[spd][mode[0]] > 3437 opti_tim_as[spd][mode[1]]) ? 0 : 1; 3438 3439 mode[d] = mode[1-d]; 3440 chp->ch_drive[d].PIO_mode = chp->ch_drive[1-d].PIO_mode; 3441 chp->ch_drive[d].DMA_mode = 0; 3442 chp->ch_drive[d].drive_flags &= DRIVE_DMA; 3443 } 3444 } 3445 3446 for (drive = 0; drive < 2; drive++) { 3447 int m; 3448 if ((m = mode[drive]) < 0) 3449 continue; 3450 3451 /* Set the Address Setup Time and select appropriate index */ 3452 rv = opti_tim_as[spd][m] << OPTI_MISC_ADDR_SETUP_SHIFT; 3453 rv |= OPTI_MISC_INDEX(drive); 3454 opti_write_config(chp, OPTI_REG_MISC, mr | rv); 3455 3456 /* Set the pulse width and recovery timing parameters */ 3457 rv = opti_tim_cp[spd][m] << OPTI_PULSE_WIDTH_SHIFT; 3458 rv |= opti_tim_rt[spd][m] << OPTI_RECOVERY_TIME_SHIFT; 3459 opti_write_config(chp, OPTI_REG_READ_CYCLE_TIMING, rv); 3460 opti_write_config(chp, OPTI_REG_WRITE_CYCLE_TIMING, rv); 3461 3462 /* Set the Enhanced Mode register appropriately */ 3463 rv = pciide_pci_read(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE); 3464 rv &= ~OPTI_ENH_MODE_MASK(chp->channel, drive); 3465 rv |= OPTI_ENH_MODE(chp->channel, drive, opti_tim_em[m]); 3466 pciide_pci_write(sc->sc_pc, sc->sc_tag, OPTI_REG_ENH_MODE, rv); 3467 } 3468 3469 /* Finally, enable the timings */ 3470 opti_write_config(chp, OPTI_REG_CONTROL, OPTI_CONTROL_ENABLE); 3471 3472 pciide_print_modes(cp); 3473 } 3474
Indexes created Thu Oct 02 10:09:58 GMT 2025