pciide_acer_reg.h revision 1.1 1 /* $NetBSD: pciide_acer_reg.h,v 1.1 1999/02/02 16:13:59 bouyer Exp $ */
2
3 /*
4 * Copyright (c) 1999 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 */
35
36 /* class code attribute register 1 (1 byte) */
37 #define ACER_CCAR1 0x43
38 #define ACER_CHANSTATUS_RO 0x40
39 #define PCIIDE_CHAN_RO(chan) (0x20 >> (chan))
40
41 /* class code attribute register 2 (1 byte) */
42 #define ACER_CCAR2 0x4d
43 #define ACER_CHANSTATUSREGS_RO 0x80
44
45 /* class code attribute register 3 (1 byte) */
46 #define ACER_CCAR3 0x50
47 #define ACER_CCAR3_PI 0x02
48
49 /* flexible channel setting register */
50 #define ACER_FCS 0x52
51 #define ACER_FCS_TIMREG(chan,drv) ((0x8) >> ((drv) + (chan) * 2))
52
53 /* CD-ROM control register */
54 #define ACER_CDRC 0x53
55 #define ACER_CDRC_FIFO_DISABLE 0x02
56 #define ACER_CDRC_DMA_EN 0x01
57
58 /* Fifo threshold and Ultra-DMA settings (4 bytes). */
59 #define ACER_FTH_UDMA 0x54
60 #define ACER_FTH_VAL(chan, drv, val) \
61 (((val) & 0x3) << ((drv) * 4 + (chan) * 8))
62 #define ACER_FTH_OPL(chan, drv, val) \
63 (((val) & 0x3) << (2 + (drv) * 4 + (chan) * 8))
64 #define ACER_UDMA_EN(chan, drv) \
65 (0x8 << (16 + (drv) * 4 + (chan) * 8))
66 #define ACER_UDMA_TIM(chan, drv, val) \
67 (((val) & 0x7) << (16 + (drv) * 4 + (chan) * 8))
68
69 /* drives timings setup (1 byte) */
70 #define ACER_IDETIM(chan, drv) (0x5a + (drv) + (chan) * 4)
71
72 /*
73 * IDE bus frequency (1 byte)
74 * This should be setup by the BIOS - can we rely on this ?
75 */
76 #define ACER_IDE_CLK 0x78
77
78 static int8_t acer_udma[] = {0x4, 0x3, 0x2};
79 static int8_t acer_pio[] = {0x0c, 0x58, 0x44, 0x33, 0x31};
80 #ifdef unused
81 static int8_t acer_dma[] = {0x08, 0x33, 0x31};
82 #endif
83