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pciide_acer_reg.h revision 1.13 
      1 /*	$NetBSD: pciide_acer_reg.h,v 1.13 2017/07/21 21:01:13 nakayama Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1999 Manuel Bouyer.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     25  *
     26  */
     27 
     28 /*  class code attribute register 1 (1 byte) */
     29 #define ACER_CCAR1	0x43
     30 #define ACER_CHANSTATUS_RO            0x40
     31 #define PCIIDE_CHAN_RO(chan)            (0x20 >> (chan))
     32 
     33 /* from Linux, 80 pins cable detect */
     34 #define ACER_0x4A	0x4a
     35 /*
     36  * bit 0 is 0 -> primary has 80 pin cable
     37  * bit 1 is 0 -> secondary has 80 pin cable
     38  */
     39 #define ACER_0x4A_80PIN(chan)	(0x1 << (chan))
     40 /* From FreeBSD, use device interrupt as byte count end */
     41 #define ACER_0x4A_BCEINT	0x20
     42 
     43 /* From FreeBSD, for UDMA mode > 2 */
     44 #define ACER_0x4B	0x4b
     45 #define ACER_0x4B_UDMA66	0x01
     46 /* From Linux */
     47 #define ACER_0x4B_CDETECT	0x08
     48 
     49 /* class code attribute register 2 (1 byte) */
     50 #define ACER_CCAR2	0x4d
     51 #define ACER_CHANSTATUSREGS_RO 0x80
     52 
     53 /* class code attribute register 3 (1 byte) */
     54 #define ACER_CCAR3	0x50
     55 #define ACER_CCAR3_PI	0x02
     56 
     57 /* flexible channel setting register */
     58 #define ACER_FCS	0x52
     59 #define ACER_FCS_TIMREG(chan,drv)	((0x8) >> ((drv) + (chan) * 2))
     60 
     61 /* CD-ROM control register */
     62 #define ACER_CDRC	0x53
     63 #define ACER_CDRC_FIFO_DISABLE	0x02
     64 #define ACER_CDRC_DMA_EN	0x01
     65 
     66 /* Fifo threshold and Ultra-DMA settings (4 bytes). */
     67 #define ACER_FTH_UDMA	0x54
     68 #define ACER_FTH_VAL(chan, drv, val) \
     69 	(((val) & 0x3) << ((drv) * 4 + (chan) * 8))
     70 #define ACER_FTH_OPL(chan, drv, val) \
     71 	(((val) & 0x3) << (2 + (drv) * 4 + (chan) * 8))
     72 #define ACER_UDMA_EN(chan, drv) \
     73 	(0x8 << (16 + (drv) * 4 + (chan) * 8))
     74 #define ACER_UDMA_TIM(chan, drv, val) \
     75 	(((val) & 0x7) << (16 + (drv) * 4 + (chan) * 8))
     76 
     77 /* drives timings setup (1 byte) */
     78 #define ACER_IDETIM(chan, drv) (0x5a + (drv) + (chan) * 4)
     79 
     80 /* IRQ and drive select status */
     81 #define ACER_CHIDS	0x75
     82 #define ACER_CHIDS_DRV(channel)	((0x4) << (channel))
     83 #define ACER_CHIDS_INT(channel)	((0x1) << (channel))
     84 
     85 /* Linux: south-bridge's enable bit (m1533) */
     86 #define ACER_0x79	0x79
     87 #define ACER_0x79_REVC2_EN	0x4
     88 #define ACER_0x79_EN		0x2
     89 
     90 /* OpenSolaris: channel enable/disable in the PCI-ISA bridge */
     91 #define ACER_PCIB_CTRL	0x58
     92 #define ACER_PCIB_CTRL_ENCHAN(chan) (0x4 << (chan))
     93 
     94 /*
     95  * IDE bus frequency (1 byte)
     96  * This should be setup by the BIOS - can we rely on this ?
     97  */
     98 #define ACER_IDE_CLK	0x78
     99 
    100 /* acer UDMA3/4/5 from FreeBSD */
    101 static const int8_t acer_udma[] __unused =
    102     {0x4, 0x3, 0x2, 0x1, 0x0, 0x7};
    103 static const int8_t acer_pio[] __unused =
    104     {0x0c, 0x58, 0x44, 0x33, 0x31};
    105 #ifdef unused
    106 static const int8_t acer_dma[] __unused =
    107     {0x08, 0x33, 0x31};
    108 #endif
    109