pciide_acer_reg.h revision 1.3 1 /* $NetBSD: pciide_acer_reg.h,v 1.3 2000/05/15 08:46:01 bouyer Exp $ */
2
3 /*
4 * Copyright (c) 1999 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /* class code attribute register 1 (1 byte) */
36 #define ACER_CCAR1 0x43
37 #define ACER_CHANSTATUS_RO 0x40
38 #define PCIIDE_CHAN_RO(chan) (0x20 >> (chan))
39
40 /* class code attribute register 2 (1 byte) */
41 #define ACER_CCAR2 0x4d
42 #define ACER_CHANSTATUSREGS_RO 0x80
43
44 /* class code attribute register 3 (1 byte) */
45 #define ACER_CCAR3 0x50
46 #define ACER_CCAR3_PI 0x02
47
48 /* flexible channel setting register */
49 #define ACER_FCS 0x52
50 #define ACER_FCS_TIMREG(chan,drv) ((0x8) >> ((drv) + (chan) * 2))
51
52 /* CD-ROM control register */
53 #define ACER_CDRC 0x53
54 #define ACER_CDRC_FIFO_DISABLE 0x02
55 #define ACER_CDRC_DMA_EN 0x01
56
57 /* Fifo threshold and Ultra-DMA settings (4 bytes). */
58 #define ACER_FTH_UDMA 0x54
59 #define ACER_FTH_VAL(chan, drv, val) \
60 (((val) & 0x3) << ((drv) * 4 + (chan) * 8))
61 #define ACER_FTH_OPL(chan, drv, val) \
62 (((val) & 0x3) << (2 + (drv) * 4 + (chan) * 8))
63 #define ACER_UDMA_EN(chan, drv) \
64 (0x8 << (16 + (drv) * 4 + (chan) * 8))
65 #define ACER_UDMA_TIM(chan, drv, val) \
66 (((val) & 0x7) << (16 + (drv) * 4 + (chan) * 8))
67
68 /* drives timings setup (1 byte) */
69 #define ACER_IDETIM(chan, drv) (0x5a + (drv) + (chan) * 4)
70
71 /* IRQ and drive select status */
72 #define ACER_CHIDS 0x75
73 #define ACER_CHIDS_DRV(channel) ((0x4) << (channel))
74 #define ACER_CHIDS_INT(channel) ((0x1) << (channel))
75
76 /*
77 * IDE bus frequency (1 byte)
78 * This should be setup by the BIOS - can we rely on this ?
79 */
80 #define ACER_IDE_CLK 0x78
81
82 static int8_t acer_udma[] = {0x4, 0x3, 0x2};
83 static int8_t acer_pio[] = {0x0c, 0x58, 0x44, 0x33, 0x31};
84 #ifdef unused
85 static int8_t acer_dma[] = {0x08, 0x33, 0x31};
86 #endif
87