pciide_cmd_reg.h revision 1.4 1 /* $NetBSD: pciide_cmd_reg.h,v 1.4 1998/12/02 10:52:25 bouyer Exp $ */
2
3 /*
4 * Copyright (c) 1998 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 */
35
36 /*
37 * Registers definitions for CMD Technologies's PCI 064x IDE controllers.
38 * Available from http://www.cmd.com/
39 */
40
41 /* Configuration (RO) */
42 #define CMD_CONF 0x50
43 #define CMD_CONF_REV_MASK 0x03
44 #define CMD_CONF_DRV0_INTR 0x04
45 #define CMD_CONF_DEVID 0x18
46 #define CMD_CONF_VESAPRT 0x20
47 #define CMD_CONF_DSA1 0x40
48 #define CMD_CONF_DSA0 0x80
49
50 /* Control register (RW) */
51 #define CMD_CTRL 0x51
52 #define CMD_CTRL_HR_FIFO 0x01
53 #define CMD_CTRL_HW_FIFO 0x02
54 #define CMD_CTRL_DEVSEL 0x04
55 #define CMD_CTRL_2PORT 0x08
56 #define CMD_CTRL_PAR 0x10
57 #define CMD_CTRL_HW_HLD 0x20
58 #define CMD_CTRL_DRV0_RAHEAD 0x40
59 #define CMD_CTRL_DRV1_RAHEAD 0x80
60
61 /*
62 * data read/write timing registers . 0640 uses the same for drive 0 and 1
63 * on the secondary channel
64 */
65 #define CMD_DATA_TIM(chan, drive) \
66 (((chan) == 0) ? \
67 ((drive) == 0) ? 0x54: 0x56 \
68 : \
69 ((drive) == 0) ? 0x58 : 0x5b)
70
71 /* DMA master read mode select */
72 #define CMD_DMA_MODE 0x71
73 #define CMD_DMA 0x00
74 #define CMD_DMA_MULTIPLE 0x01
75 #define CMD_DMA_LINE 0x10
76
77
78 /*
79 * timings values for the 0643 and 0x646
80 * for all dma_mode we have to have
81 * DMA_timings(dma_mode) >= PIO_timings(dma_mode + 2)
82 */
83 static int8_t cmd0643_6_data_tim_pio[] = {0xA9, 0x57, 0x44, 0x32, 0x3F};
84 static int8_t cmd0643_6_data_tim_dma[] = {0x87, 0x32, 0x3F};
85