pciide_cmd_reg.h revision 1.6 1 /* $NetBSD: pciide_cmd_reg.h,v 1.6 2000/05/15 08:46:01 bouyer Exp $ */
2
3 /*
4 * Copyright (c) 1998 Manuel Bouyer.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by the University of
17 * California, Berkeley and its contributors.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Registers definitions for CMD Technologies's PCI 064x IDE controllers.
37 * Available from http://www.cmd.com/
38 */
39
40 /* Configuration (RO) */
41 #define CMD_CONF 0x50
42 #define CMD_CONF_REV_MASK 0x03
43 #define CMD_CONF_DRV0_INTR 0x04
44 #define CMD_CONF_DEVID 0x18
45 #define CMD_CONF_VESAPRT 0x20
46 #define CMD_CONF_DSA1 0x40
47 #define CMD_CONF_DSA0 0x80
48
49 /* Control register (RW) */
50 #define CMD_CTRL 0x51
51 #define CMD_CTRL_HR_FIFO 0x01
52 #define CMD_CTRL_HW_FIFO 0x02
53 #define CMD_CTRL_DEVSEL 0x04
54 #define CMD_CTRL_2PORT 0x08
55 #define CMD_CTRL_PAR 0x10
56 #define CMD_CTRL_HW_HLD 0x20
57 #define CMD_CTRL_DRV0_RAHEAD 0x40
58 #define CMD_CTRL_DRV1_RAHEAD 0x80
59
60 /*
61 * data read/write timing registers . 0640 uses the same for drive 0 and 1
62 * on the secondary channel
63 */
64 #define CMD_DATA_TIM(chan, drive) \
65 (((chan) == 0) ? \
66 ((drive) == 0) ? 0x54: 0x56 \
67 : \
68 ((drive) == 0) ? 0x58 : 0x5b)
69
70 /* secondary channel status and addr timings */
71 #define CMD_ARTTIM23 0x57
72 #define CMD_ARTTIM23_IRQ 0x10
73 #define CMD_ARTTIM23_RHAEAD(d) ((0x4) << (d))
74
75 /* DMA master read mode select */
76 #define CMD_DMA_MODE 0x71
77 #define CMD_DMA 0x00
78 #define CMD_DMA_MULTIPLE 0x01
79 #define CMD_DMA_LINE 0x10
80
81
82 /*
83 * timings values for the 0643 and 0x646
84 * for all dma_mode we have to have
85 * DMA_timings(dma_mode) >= PIO_timings(dma_mode + 2)
86 */
87 static int8_t cmd0643_6_data_tim_pio[] = {0xA9, 0x57, 0x44, 0x32, 0x3F};
88 static int8_t cmd0643_6_data_tim_dma[] = {0x87, 0x32, 0x3F};
89