pciide_common.c revision 1.12
1 /* $NetBSD: pciide_common.c,v 1.12 2004/06/04 21:15:00 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.12 2004/06/04 21:15:00 bouyer Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/malloc.h> 83 84 #include <uvm/uvm_extern.h> 85 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pcidevs.h> 89 #include <dev/pci/pciidereg.h> 90 #include <dev/pci/pciidevar.h> 91 92 #include <dev/ic/wdcreg.h> 93 94 #ifdef WDCDEBUG 95 int wdcdebug_pciide_mask = 0; 96 #endif 97 98 static const char dmaerrfmt[] = 99 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 100 101 /* Default product description for devices not known from this controller */ 102 const struct pciide_product_desc default_product_desc = { 103 0, 104 0, 105 "Generic PCI IDE controller", 106 default_chip_map, 107 }; 108 109 const struct pciide_product_desc * 110 pciide_lookup_product(id, pp) 111 pcireg_t id; 112 const struct pciide_product_desc *pp; 113 { 114 for (; pp->chip_map != NULL; pp++) 115 if (PCI_PRODUCT(id) == pp->ide_product) 116 break; 117 118 if (pp->chip_map == NULL) 119 return NULL; 120 return pp; 121 } 122 123 void 124 pciide_common_attach(sc, pa, pp) 125 struct pciide_softc *sc; 126 struct pci_attach_args *pa; 127 const struct pciide_product_desc *pp; 128 { 129 pci_chipset_tag_t pc = pa->pa_pc; 130 pcitag_t tag = pa->pa_tag; 131 pcireg_t csr; 132 char devinfo[256]; 133 const char *displaydev; 134 135 aprint_naive(": disk controller\n"); 136 aprint_normal("\n"); 137 138 sc->sc_pci_id = pa->pa_id; 139 if (pp == NULL) { 140 /* should only happen for generic pciide devices */ 141 sc->sc_pp = &default_product_desc; 142 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 143 displaydev = devinfo; 144 } else { 145 sc->sc_pp = pp; 146 displaydev = sc->sc_pp->ide_name; 147 } 148 149 /* if displaydev == NULL, printf is done in chip-specific map */ 150 if (displaydev) 151 aprint_normal("%s: %s (rev. 0x%02x)\n", 152 sc->sc_wdcdev.sc_dev.dv_xname, displaydev, 153 PCI_REVISION(pa->pa_class)); 154 155 sc->sc_pc = pa->pa_pc; 156 sc->sc_tag = pa->pa_tag; 157 158 /* Set up DMA defaults; these might be adjusted by chip_map. */ 159 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 160 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 161 162 #ifdef WDCDEBUG 163 if (wdcdebug_pciide_mask & DEBUG_PROBE) 164 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 165 #endif 166 sc->sc_pp->chip_map(sc, pa); 167 168 if (sc->sc_dma_ok) { 169 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 170 csr |= PCI_COMMAND_MASTER_ENABLE; 171 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 172 } 173 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 174 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 175 } 176 177 /* tell whether the chip is enabled or not */ 178 int 179 pciide_chipen(sc, pa) 180 struct pciide_softc *sc; 181 struct pci_attach_args *pa; 182 { 183 pcireg_t csr; 184 185 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 186 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 187 PCI_COMMAND_STATUS_REG); 188 aprint_normal("%s: device disabled (at %s)\n", 189 sc->sc_wdcdev.sc_dev.dv_xname, 190 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 191 "device" : "bridge"); 192 return 0; 193 } 194 return 1; 195 } 196 197 void 198 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 199 struct pci_attach_args *pa; 200 struct pciide_channel *cp; 201 int compatchan; 202 bus_size_t *cmdsizep, *ctlsizep; 203 { 204 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 205 struct wdc_channel *wdc_cp = &cp->wdc_channel; 206 int i; 207 208 cp->compat = 1; 209 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 210 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 211 212 wdc_cp->cmd_iot = pa->pa_iot; 213 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 214 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_baseioh) != 0) { 215 aprint_error("%s: couldn't map %s channel cmd regs\n", 216 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 217 goto bad; 218 } 219 220 wdc_cp->ctl_iot = pa->pa_iot; 221 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 222 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 223 aprint_error("%s: couldn't map %s channel ctl regs\n", 224 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 225 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 226 PCIIDE_COMPAT_CMD_SIZE); 227 goto bad; 228 } 229 230 for (i = 0; i < WDC_NREG; i++) { 231 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, i, 232 i == 0 ? 4 : 1, &wdc_cp->cmd_iohs[i]) != 0) { 233 aprint_error("%s: couldn't subregion %s channel " 234 "cmd regs\n", 235 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 236 goto bad; 237 } 238 } 239 wdc_init_shadow_regs(wdc_cp); 240 wdc_cp->data32iot = wdc_cp->cmd_iot; 241 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 242 pciide_map_compat_intr(pa, cp, compatchan); 243 return; 244 245 bad: 246 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 247 return; 248 } 249 250 void 251 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 252 struct pci_attach_args * pa; 253 struct pciide_channel *cp; 254 bus_size_t *cmdsizep, *ctlsizep; 255 int (*pci_intr) __P((void *)); 256 { 257 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 258 struct wdc_channel *wdc_cp = &cp->wdc_channel; 259 const char *intrstr; 260 pci_intr_handle_t intrhandle; 261 int i; 262 263 cp->compat = 0; 264 265 if (sc->sc_pci_ih == NULL) { 266 if (pci_intr_map(pa, &intrhandle) != 0) { 267 aprint_error("%s: couldn't map native-PCI interrupt\n", 268 sc->sc_wdcdev.sc_dev.dv_xname); 269 goto bad; 270 } 271 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 272 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 273 intrhandle, IPL_BIO, pci_intr, sc); 274 if (sc->sc_pci_ih != NULL) { 275 aprint_normal("%s: using %s for native-PCI interrupt\n", 276 sc->sc_wdcdev.sc_dev.dv_xname, 277 intrstr ? intrstr : "unknown interrupt"); 278 } else { 279 aprint_error( 280 "%s: couldn't establish native-PCI interrupt", 281 sc->sc_wdcdev.sc_dev.dv_xname); 282 if (intrstr != NULL) 283 aprint_normal(" at %s", intrstr); 284 aprint_normal("\n"); 285 goto bad; 286 } 287 } 288 cp->ih = sc->sc_pci_ih; 289 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel), 290 PCI_MAPREG_TYPE_IO, 0, 291 &wdc_cp->cmd_iot, &wdc_cp->cmd_baseioh, NULL, cmdsizep) != 0) { 292 aprint_error("%s: couldn't map %s channel cmd regs\n", 293 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 294 goto bad; 295 } 296 297 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel), 298 PCI_MAPREG_TYPE_IO, 0, 299 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 300 aprint_error("%s: couldn't map %s channel ctl regs\n", 301 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 302 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 303 *cmdsizep); 304 goto bad; 305 } 306 /* 307 * In native mode, 4 bytes of I/O space are mapped for the control 308 * register, the control register is at offset 2. Pass the generic 309 * code a handle for only one byte at the right offset. 310 */ 311 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 312 &wdc_cp->ctl_ioh) != 0) { 313 aprint_error("%s: unable to subregion %s channel ctl regs\n", 314 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 315 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 316 *cmdsizep); 317 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 318 goto bad; 319 } 320 321 for (i = 0; i < WDC_NREG; i++) { 322 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, i, 323 i == 0 ? 4 : 1, &wdc_cp->cmd_iohs[i]) != 0) { 324 aprint_error("%s: couldn't subregion %s channel " 325 "cmd regs\n", 326 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 327 goto bad; 328 } 329 } 330 wdc_init_shadow_regs(wdc_cp); 331 wdc_cp->data32iot = wdc_cp->cmd_iot; 332 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 333 return; 334 335 bad: 336 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 337 return; 338 } 339 340 void 341 pciide_mapreg_dma(sc, pa) 342 struct pciide_softc *sc; 343 struct pci_attach_args *pa; 344 { 345 pcireg_t maptype; 346 bus_addr_t addr; 347 struct pciide_channel *pc; 348 int reg, chan; 349 bus_size_t size; 350 351 /* 352 * Map DMA registers 353 * 354 * Note that sc_dma_ok is the right variable to test to see if 355 * DMA can be done. If the interface doesn't support DMA, 356 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 357 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 358 * non-zero if the interface supports DMA and the registers 359 * could be mapped. 360 * 361 * XXX Note that despite the fact that the Bus Master IDE specs 362 * XXX say that "The bus master IDE function uses 16 bytes of IO 363 * XXX space," some controllers (at least the United 364 * XXX Microelectronics UM8886BF) place it in memory space. 365 */ 366 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 367 PCIIDE_REG_BUS_MASTER_DMA); 368 369 switch (maptype) { 370 case PCI_MAPREG_TYPE_IO: 371 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 372 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 373 &addr, NULL, NULL) == 0); 374 if (sc->sc_dma_ok == 0) { 375 aprint_normal( 376 ", but unused (couldn't query registers)"); 377 break; 378 } 379 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 380 && addr >= 0x10000) { 381 sc->sc_dma_ok = 0; 382 aprint_normal( 383 ", but unused (registers at unsafe address " 384 "%#lx)", (unsigned long)addr); 385 break; 386 } 387 /* FALLTHROUGH */ 388 389 case PCI_MAPREG_MEM_TYPE_32BIT: 390 sc->sc_dma_ok = (pci_mapreg_map(pa, 391 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 392 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 393 sc->sc_dmat = pa->pa_dmat; 394 if (sc->sc_dma_ok == 0) { 395 aprint_normal(", but unused (couldn't map registers)"); 396 } else { 397 sc->sc_wdcdev.dma_arg = sc; 398 sc->sc_wdcdev.dma_init = pciide_dma_init; 399 sc->sc_wdcdev.dma_start = pciide_dma_start; 400 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 401 } 402 403 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 404 PCIIDE_OPTIONS_NODMA) { 405 aprint_normal( 406 ", but unused (forced off by config file)"); 407 sc->sc_dma_ok = 0; 408 } 409 break; 410 411 default: 412 sc->sc_dma_ok = 0; 413 aprint_normal( 414 ", but unsupported register maptype (0x%x)", maptype); 415 } 416 417 if (sc->sc_dma_ok == 0) 418 return; 419 420 /* 421 * Set up the default handles for the DMA registers. 422 * Just reserve 32 bits for each handle, unless space 423 * doesn't permit it. 424 */ 425 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { 426 pc = &sc->pciide_channels[chan]; 427 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 428 size = 4; 429 if (size > (IDEDMA_SCH_OFFSET - reg)) 430 size = IDEDMA_SCH_OFFSET - reg; 431 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 432 IDEDMA_SCH_OFFSET * chan + reg, size, 433 &pc->dma_iohs[reg]) != 0) { 434 sc->sc_dma_ok = 0; 435 aprint_normal(", but can't subregion offset %d " 436 "size %lu", reg, (u_long)size); 437 return; 438 } 439 } 440 } 441 } 442 443 int 444 pciide_compat_intr(arg) 445 void *arg; 446 { 447 struct pciide_channel *cp = arg; 448 449 #ifdef DIAGNOSTIC 450 /* should only be called for a compat channel */ 451 if (cp->compat == 0) 452 panic("pciide compat intr called for non-compat chan %p", cp); 453 #endif 454 return (wdcintr(&cp->wdc_channel)); 455 } 456 457 int 458 pciide_pci_intr(arg) 459 void *arg; 460 { 461 struct pciide_softc *sc = arg; 462 struct pciide_channel *cp; 463 struct wdc_channel *wdc_cp; 464 int i, rv, crv; 465 466 rv = 0; 467 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 468 cp = &sc->pciide_channels[i]; 469 wdc_cp = &cp->wdc_channel; 470 471 /* If a compat channel skip. */ 472 if (cp->compat) 473 continue; 474 /* if this channel not waiting for intr, skip */ 475 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 476 continue; 477 478 crv = wdcintr(wdc_cp); 479 if (crv == 0) 480 ; /* leave rv alone */ 481 else if (crv == 1) 482 rv = 1; /* claim the intr */ 483 else if (rv == 0) /* crv should be -1 in this case */ 484 rv = crv; /* if we've done no better, take it */ 485 } 486 return (rv); 487 } 488 489 void 490 pciide_channel_dma_setup(cp) 491 struct pciide_channel *cp; 492 { 493 int drive; 494 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 495 struct ata_drive_datas *drvp; 496 497 for (drive = 0; drive < 2; drive++) { 498 drvp = &cp->wdc_channel.ch_drive[drive]; 499 /* If no drive, skip */ 500 if ((drvp->drive_flags & DRIVE) == 0) 501 continue; 502 /* setup DMA if needed */ 503 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 504 (drvp->drive_flags & DRIVE_UDMA) == 0) || 505 sc->sc_dma_ok == 0) { 506 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 507 continue; 508 } 509 if (pciide_dma_table_setup(sc, cp->wdc_channel.ch_channel, 510 drive) != 0) { 511 /* Abort DMA setup */ 512 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 513 continue; 514 } 515 } 516 } 517 518 int 519 pciide_dma_table_setup(sc, channel, drive) 520 struct pciide_softc *sc; 521 int channel, drive; 522 { 523 bus_dma_segment_t seg; 524 int error, rseg; 525 const bus_size_t dma_table_size = 526 sizeof(struct idedma_table) * NIDEDMA_TABLES; 527 struct pciide_dma_maps *dma_maps = 528 &sc->pciide_channels[channel].dma_maps[drive]; 529 530 /* If table was already allocated, just return */ 531 if (dma_maps->dma_table) 532 return 0; 533 534 /* Allocate memory for the DMA tables and map it */ 535 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 536 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 537 BUS_DMA_NOWAIT)) != 0) { 538 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 539 "allocate", drive, error); 540 return error; 541 } 542 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 543 dma_table_size, 544 (caddr_t *)&dma_maps->dma_table, 545 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 546 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 547 "map", drive, error); 548 return error; 549 } 550 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 551 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 552 (unsigned long)seg.ds_addr), DEBUG_PROBE); 553 /* Create and load table DMA map for this disk */ 554 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 555 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 556 &dma_maps->dmamap_table)) != 0) { 557 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 558 "create", drive, error); 559 return error; 560 } 561 if ((error = bus_dmamap_load(sc->sc_dmat, 562 dma_maps->dmamap_table, 563 dma_maps->dma_table, 564 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 565 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 566 "load", drive, error); 567 return error; 568 } 569 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 570 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 571 DEBUG_PROBE); 572 /* Create a xfer DMA map for this drive */ 573 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 574 NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 575 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 576 &dma_maps->dmamap_xfer)) != 0) { 577 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 578 "create xfer", drive, error); 579 return error; 580 } 581 return 0; 582 } 583 584 int 585 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 586 void *v; 587 int channel, drive; 588 void *databuf; 589 size_t datalen; 590 int flags; 591 { 592 struct pciide_softc *sc = v; 593 int error, seg; 594 struct pciide_channel *cp = &sc->pciide_channels[channel]; 595 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 596 597 error = bus_dmamap_load(sc->sc_dmat, 598 dma_maps->dmamap_xfer, 599 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 600 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 601 if (error) { 602 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 603 "load xfer", drive, error); 604 return error; 605 } 606 607 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 608 dma_maps->dmamap_xfer->dm_mapsize, 609 (flags & WDC_DMA_READ) ? 610 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 611 612 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 613 #ifdef DIAGNOSTIC 614 /* A segment must not cross a 64k boundary */ 615 { 616 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 617 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 618 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 619 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 620 printf("pciide_dma: segment %d physical addr 0x%lx" 621 " len 0x%lx not properly aligned\n", 622 seg, phys, len); 623 panic("pciide_dma: buf align"); 624 } 625 } 626 #endif 627 dma_maps->dma_table[seg].base_addr = 628 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 629 dma_maps->dma_table[seg].byte_count = 630 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 631 IDEDMA_BYTE_COUNT_MASK); 632 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 633 seg, le32toh(dma_maps->dma_table[seg].byte_count), 634 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 635 636 } 637 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 638 htole32(IDEDMA_BYTE_COUNT_EOT); 639 640 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 641 dma_maps->dmamap_table->dm_mapsize, 642 BUS_DMASYNC_PREWRITE); 643 644 /* Maps are ready. Start DMA function */ 645 #ifdef DIAGNOSTIC 646 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 647 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 648 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 649 panic("pciide_dma_init: table align"); 650 } 651 #endif 652 653 /* Clear status bits */ 654 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 655 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 656 /* Write table addr */ 657 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 658 dma_maps->dmamap_table->dm_segs[0].ds_addr); 659 /* set read/write */ 660 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 661 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 662 /* remember flags */ 663 dma_maps->dma_flags = flags; 664 return 0; 665 } 666 667 void 668 pciide_dma_start(v, channel, drive) 669 void *v; 670 int channel, drive; 671 { 672 struct pciide_softc *sc = v; 673 struct pciide_channel *cp = &sc->pciide_channels[channel]; 674 675 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 676 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 677 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 678 | IDEDMA_CMD_START); 679 } 680 681 int 682 pciide_dma_finish(v, channel, drive, force) 683 void *v; 684 int channel, drive; 685 int force; 686 { 687 struct pciide_softc *sc = v; 688 u_int8_t status; 689 int error = 0; 690 struct pciide_channel *cp = &sc->pciide_channels[channel]; 691 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 692 693 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0); 694 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 695 DEBUG_XFERS); 696 697 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 698 return WDC_DMAST_NOIRQ; 699 700 /* stop DMA channel */ 701 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 702 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 703 & ~IDEDMA_CMD_START); 704 705 /* Unload the map of the data buffer */ 706 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 707 dma_maps->dmamap_xfer->dm_mapsize, 708 (dma_maps->dma_flags & WDC_DMA_READ) ? 709 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 710 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 711 712 if ((status & IDEDMA_CTL_ERR) != 0) { 713 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 714 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 715 error |= WDC_DMAST_ERR; 716 } 717 718 if ((status & IDEDMA_CTL_INTR) == 0) { 719 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 720 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 721 drive, status); 722 error |= WDC_DMAST_NOIRQ; 723 } 724 725 if ((status & IDEDMA_CTL_ACT) != 0) { 726 /* data underrun, may be a valid condition for ATAPI */ 727 error |= WDC_DMAST_UNDER; 728 } 729 return error; 730 } 731 732 void 733 pciide_irqack(chp) 734 struct wdc_channel *chp; 735 { 736 struct pciide_channel *cp = (struct pciide_channel*)chp; 737 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 738 739 /* clear status bits in IDE DMA registers */ 740 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 741 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 742 } 743 744 /* some common code used by several chip_map */ 745 int 746 pciide_chansetup(sc, channel, interface) 747 struct pciide_softc *sc; 748 int channel; 749 pcireg_t interface; 750 { 751 struct pciide_channel *cp = &sc->pciide_channels[channel]; 752 sc->wdc_chanarray[channel] = &cp->wdc_channel; 753 cp->name = PCIIDE_CHANNEL_NAME(channel); 754 cp->wdc_channel.ch_channel = channel; 755 cp->wdc_channel.ch_wdc = &sc->sc_wdcdev; 756 cp->wdc_channel.ch_queue = 757 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 758 if (cp->wdc_channel.ch_queue == NULL) { 759 aprint_error("%s %s channel: " 760 "can't allocate memory for command queue", 761 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 762 return 0; 763 } 764 aprint_normal("%s: %s channel %s to %s mode\n", 765 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 766 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 767 "configured" : "wired", 768 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 769 "native-PCI" : "compatibility"); 770 return 1; 771 } 772 773 /* some common code used by several chip channel_map */ 774 void 775 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 776 struct pci_attach_args *pa; 777 struct pciide_channel *cp; 778 pcireg_t interface; 779 bus_size_t *cmdsizep, *ctlsizep; 780 int (*pci_intr) __P((void *)); 781 { 782 struct wdc_channel *wdc_cp = &cp->wdc_channel; 783 784 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) 785 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr); 786 else 787 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep, 788 ctlsizep); 789 wdcattach(wdc_cp); 790 } 791 792 /* 793 * generic code to map the compat intr. 794 */ 795 void 796 pciide_map_compat_intr(pa, cp, compatchan) 797 struct pci_attach_args *pa; 798 struct pciide_channel *cp; 799 int compatchan; 800 { 801 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 802 803 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 804 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 805 pa, compatchan, pciide_compat_intr, cp); 806 if (cp->ih == NULL) { 807 #endif 808 aprint_error("%s: no compatibility interrupt for use by %s " 809 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 810 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 811 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 812 } 813 #endif 814 } 815 816 void 817 default_chip_map(sc, pa) 818 struct pciide_softc *sc; 819 struct pci_attach_args *pa; 820 { 821 struct pciide_channel *cp; 822 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 823 pcireg_t csr; 824 int channel, drive; 825 struct ata_drive_datas *drvp; 826 u_int8_t idedma_ctl; 827 bus_size_t cmdsize, ctlsize; 828 char *failreason; 829 830 if (pciide_chipen(sc, pa) == 0) 831 return; 832 833 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 834 aprint_normal("%s: bus-master DMA support present", 835 sc->sc_wdcdev.sc_dev.dv_xname); 836 if (sc->sc_pp == &default_product_desc && 837 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 838 PCIIDE_OPTIONS_DMA) == 0) { 839 aprint_normal(", but unused (no driver support)"); 840 sc->sc_dma_ok = 0; 841 } else { 842 pciide_mapreg_dma(sc, pa); 843 if (sc->sc_dma_ok != 0) 844 aprint_normal(", used without full driver " 845 "support"); 846 } 847 } else { 848 aprint_normal("%s: hardware does not support DMA", 849 sc->sc_wdcdev.sc_dev.dv_xname); 850 sc->sc_dma_ok = 0; 851 } 852 aprint_normal("\n"); 853 if (sc->sc_dma_ok) { 854 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 855 sc->sc_wdcdev.irqack = pciide_irqack; 856 } 857 sc->sc_wdcdev.PIO_cap = 0; 858 sc->sc_wdcdev.DMA_cap = 0; 859 860 sc->sc_wdcdev.channels = sc->wdc_chanarray; 861 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 862 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 863 864 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 865 cp = &sc->pciide_channels[channel]; 866 if (pciide_chansetup(sc, channel, interface) == 0) 867 continue; 868 if (interface & PCIIDE_INTERFACE_PCI(channel)) 869 pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 870 pciide_pci_intr); 871 else 872 pciide_mapregs_compat(pa, cp, 873 cp->wdc_channel.ch_channel, &cmdsize, &ctlsize); 874 if (cp->wdc_channel.ch_flags & WDCF_DISABLED) 875 continue; 876 /* 877 * Check to see if something appears to be there. 878 */ 879 failreason = NULL; 880 /* 881 * In native mode, always enable the controller. It's 882 * not possible to have an ISA board using the same address 883 * anyway. 884 */ 885 if (interface & PCIIDE_INTERFACE_PCI(channel)) 886 goto next; 887 if (!wdcprobe(&cp->wdc_channel)) { 888 failreason = "not responding; disabled or no drives?"; 889 goto next; 890 } 891 /* 892 * Now, make sure it's actually attributable to this PCI IDE 893 * channel by trying to access the channel again while the 894 * PCI IDE controller's I/O space is disabled. (If the 895 * channel no longer appears to be there, it belongs to 896 * this controller.) YUCK! 897 */ 898 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 899 PCI_COMMAND_STATUS_REG); 900 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 901 csr & ~PCI_COMMAND_IO_ENABLE); 902 if (wdcprobe(&cp->wdc_channel)) 903 failreason = "other hardware responding at addresses"; 904 pci_conf_write(sc->sc_pc, sc->sc_tag, 905 PCI_COMMAND_STATUS_REG, csr); 906 next: 907 if (failreason) { 908 aprint_error("%s: %s channel ignored (%s)\n", 909 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 910 failreason); 911 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 912 bus_space_unmap(cp->wdc_channel.cmd_iot, 913 cp->wdc_channel.cmd_baseioh, cmdsize); 914 bus_space_unmap(cp->wdc_channel.ctl_iot, 915 cp->wdc_channel.ctl_ioh, ctlsize); 916 917 } else { 918 wdcattach(&cp->wdc_channel); 919 } 920 } 921 922 if (sc->sc_dma_ok == 0) 923 return; 924 925 /* Allocate DMA maps */ 926 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 927 idedma_ctl = 0; 928 cp = &sc->pciide_channels[channel]; 929 for (drive = 0; drive < 2; drive++) { 930 drvp = &cp->wdc_channel.ch_drive[drive]; 931 /* If no drive, skip */ 932 if ((drvp->drive_flags & DRIVE) == 0) 933 continue; 934 if ((drvp->drive_flags & DRIVE_DMA) == 0) 935 continue; 936 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 937 /* Abort DMA setup */ 938 aprint_error( 939 "%s:%d:%d: can't allocate DMA maps, " 940 "using PIO transfers\n", 941 sc->sc_wdcdev.sc_dev.dv_xname, 942 channel, drive); 943 drvp->drive_flags &= ~DRIVE_DMA; 944 } 945 aprint_normal("%s:%d:%d: using DMA data transfers\n", 946 sc->sc_wdcdev.sc_dev.dv_xname, 947 channel, drive); 948 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 949 } 950 if (idedma_ctl != 0) { 951 /* Add software bits in status register */ 952 bus_space_write_1(sc->sc_dma_iot, 953 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 954 } 955 } 956 } 957 958 void 959 sata_setup_channel(chp) 960 struct wdc_channel *chp; 961 { 962 struct ata_drive_datas *drvp; 963 int drive; 964 u_int32_t idedma_ctl; 965 struct pciide_channel *cp = (struct pciide_channel*)chp; 966 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.ch_wdc; 967 968 /* setup DMA if needed */ 969 pciide_channel_dma_setup(cp); 970 971 idedma_ctl = 0; 972 973 for (drive = 0; drive < 2; drive++) { 974 drvp = &chp->ch_drive[drive]; 975 /* If no drive, skip */ 976 if ((drvp->drive_flags & DRIVE) == 0) 977 continue; 978 if (drvp->drive_flags & DRIVE_UDMA) { 979 /* use Ultra/DMA */ 980 drvp->drive_flags &= ~DRIVE_DMA; 981 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 982 } else if (drvp->drive_flags & DRIVE_DMA) { 983 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 984 } 985 } 986 987 /* 988 * Nothing to do to setup modes; it is meaningless in S-ATA 989 * (but many S-ATA drives still want to get the SET_FEATURE 990 * command). 991 */ 992 if (idedma_ctl != 0) { 993 /* Add software bits in status register */ 994 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 995 idedma_ctl); 996 } 997 } 998
Indexes created Thu Oct 02 07:10:07 GMT 2025