pciide_common.c revision 1.16
1 /* $NetBSD: pciide_common.c,v 1.16 2004/08/13 04:10:49 thorpej Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.16 2004/08/13 04:10:49 thorpej Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/malloc.h> 83 84 #include <uvm/uvm_extern.h> 85 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pcidevs.h> 89 #include <dev/pci/pciidereg.h> 90 #include <dev/pci/pciidevar.h> 91 92 #include <dev/ic/wdcreg.h> 93 94 #ifdef ATADEBUG 95 int atadebug_pciide_mask = 0; 96 #endif 97 98 static const char dmaerrfmt[] = 99 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 100 101 /* Default product description for devices not known from this controller */ 102 const struct pciide_product_desc default_product_desc = { 103 0, 104 0, 105 "Generic PCI IDE controller", 106 default_chip_map, 107 }; 108 109 const struct pciide_product_desc * 110 pciide_lookup_product(id, pp) 111 pcireg_t id; 112 const struct pciide_product_desc *pp; 113 { 114 for (; pp->chip_map != NULL; pp++) 115 if (PCI_PRODUCT(id) == pp->ide_product) 116 break; 117 118 if (pp->chip_map == NULL) 119 return NULL; 120 return pp; 121 } 122 123 void 124 pciide_common_attach(sc, pa, pp) 125 struct pciide_softc *sc; 126 struct pci_attach_args *pa; 127 const struct pciide_product_desc *pp; 128 { 129 pci_chipset_tag_t pc = pa->pa_pc; 130 pcitag_t tag = pa->pa_tag; 131 pcireg_t csr; 132 char devinfo[256]; 133 const char *displaydev; 134 135 aprint_naive(": disk controller\n"); 136 aprint_normal("\n"); 137 138 sc->sc_pci_id = pa->pa_id; 139 if (pp == NULL) { 140 /* should only happen for generic pciide devices */ 141 sc->sc_pp = &default_product_desc; 142 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 143 displaydev = devinfo; 144 } else { 145 sc->sc_pp = pp; 146 displaydev = sc->sc_pp->ide_name; 147 } 148 149 /* if displaydev == NULL, printf is done in chip-specific map */ 150 if (displaydev) 151 aprint_normal("%s: %s (rev. 0x%02x)\n", 152 sc->sc_wdcdev.sc_dev.dv_xname, displaydev, 153 PCI_REVISION(pa->pa_class)); 154 155 sc->sc_pc = pa->pa_pc; 156 sc->sc_tag = pa->pa_tag; 157 158 /* Set up DMA defaults; these might be adjusted by chip_map. */ 159 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 160 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 161 162 #ifdef ATADEBUG 163 if (atadebug_pciide_mask & DEBUG_PROBE) 164 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 165 #endif 166 sc->sc_pp->chip_map(sc, pa); 167 168 if (sc->sc_dma_ok) { 169 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 170 csr |= PCI_COMMAND_MASTER_ENABLE; 171 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 172 } 173 ATADEBUG_PRINT(("pciide: command/status register=%x\n", 174 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 175 } 176 177 /* tell whether the chip is enabled or not */ 178 int 179 pciide_chipen(sc, pa) 180 struct pciide_softc *sc; 181 struct pci_attach_args *pa; 182 { 183 pcireg_t csr; 184 185 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 186 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 187 PCI_COMMAND_STATUS_REG); 188 aprint_normal("%s: device disabled (at %s)\n", 189 sc->sc_wdcdev.sc_dev.dv_xname, 190 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 191 "device" : "bridge"); 192 return 0; 193 } 194 return 1; 195 } 196 197 void 198 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 199 struct pci_attach_args *pa; 200 struct pciide_channel *cp; 201 int compatchan; 202 bus_size_t *cmdsizep, *ctlsizep; 203 { 204 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 205 struct wdc_channel *wdc_cp = &cp->wdc_channel; 206 int i; 207 208 cp->compat = 1; 209 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 210 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 211 212 wdc_cp->cmd_iot = pa->pa_iot; 213 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 214 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_baseioh) != 0) { 215 aprint_error("%s: couldn't map %s channel cmd regs\n", 216 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 217 goto bad; 218 } 219 220 wdc_cp->ctl_iot = pa->pa_iot; 221 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 222 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 223 aprint_error("%s: couldn't map %s channel ctl regs\n", 224 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 225 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 226 PCIIDE_COMPAT_CMD_SIZE); 227 goto bad; 228 } 229 230 for (i = 0; i < WDC_NREG; i++) { 231 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, i, 232 i == 0 ? 4 : 1, &wdc_cp->cmd_iohs[i]) != 0) { 233 aprint_error("%s: couldn't subregion %s channel " 234 "cmd regs\n", 235 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 236 goto bad; 237 } 238 } 239 wdc_init_shadow_regs(wdc_cp); 240 wdc_cp->data32iot = wdc_cp->cmd_iot; 241 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 242 return; 243 244 bad: 245 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 246 return; 247 } 248 249 void 250 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 251 struct pci_attach_args * pa; 252 struct pciide_channel *cp; 253 bus_size_t *cmdsizep, *ctlsizep; 254 int (*pci_intr) __P((void *)); 255 { 256 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 257 struct wdc_channel *wdc_cp = &cp->wdc_channel; 258 const char *intrstr; 259 pci_intr_handle_t intrhandle; 260 int i; 261 262 cp->compat = 0; 263 264 if (sc->sc_pci_ih == NULL) { 265 if (pci_intr_map(pa, &intrhandle) != 0) { 266 aprint_error("%s: couldn't map native-PCI interrupt\n", 267 sc->sc_wdcdev.sc_dev.dv_xname); 268 goto bad; 269 } 270 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 271 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 272 intrhandle, IPL_BIO, pci_intr, sc); 273 if (sc->sc_pci_ih != NULL) { 274 aprint_normal("%s: using %s for native-PCI interrupt\n", 275 sc->sc_wdcdev.sc_dev.dv_xname, 276 intrstr ? intrstr : "unknown interrupt"); 277 } else { 278 aprint_error( 279 "%s: couldn't establish native-PCI interrupt", 280 sc->sc_wdcdev.sc_dev.dv_xname); 281 if (intrstr != NULL) 282 aprint_normal(" at %s", intrstr); 283 aprint_normal("\n"); 284 goto bad; 285 } 286 } 287 cp->ih = sc->sc_pci_ih; 288 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel), 289 PCI_MAPREG_TYPE_IO, 0, 290 &wdc_cp->cmd_iot, &wdc_cp->cmd_baseioh, NULL, cmdsizep) != 0) { 291 aprint_error("%s: couldn't map %s channel cmd regs\n", 292 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 293 goto bad; 294 } 295 296 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel), 297 PCI_MAPREG_TYPE_IO, 0, 298 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 299 aprint_error("%s: couldn't map %s channel ctl regs\n", 300 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 301 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 302 *cmdsizep); 303 goto bad; 304 } 305 /* 306 * In native mode, 4 bytes of I/O space are mapped for the control 307 * register, the control register is at offset 2. Pass the generic 308 * code a handle for only one byte at the right offset. 309 */ 310 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 311 &wdc_cp->ctl_ioh) != 0) { 312 aprint_error("%s: unable to subregion %s channel ctl regs\n", 313 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 314 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 315 *cmdsizep); 316 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 317 goto bad; 318 } 319 320 for (i = 0; i < WDC_NREG; i++) { 321 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, i, 322 i == 0 ? 4 : 1, &wdc_cp->cmd_iohs[i]) != 0) { 323 aprint_error("%s: couldn't subregion %s channel " 324 "cmd regs\n", 325 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 326 goto bad; 327 } 328 } 329 wdc_init_shadow_regs(wdc_cp); 330 wdc_cp->data32iot = wdc_cp->cmd_iot; 331 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 332 return; 333 334 bad: 335 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 336 return; 337 } 338 339 void 340 pciide_mapreg_dma(sc, pa) 341 struct pciide_softc *sc; 342 struct pci_attach_args *pa; 343 { 344 pcireg_t maptype; 345 bus_addr_t addr; 346 struct pciide_channel *pc; 347 int reg, chan; 348 bus_size_t size; 349 350 /* 351 * Map DMA registers 352 * 353 * Note that sc_dma_ok is the right variable to test to see if 354 * DMA can be done. If the interface doesn't support DMA, 355 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 356 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 357 * non-zero if the interface supports DMA and the registers 358 * could be mapped. 359 * 360 * XXX Note that despite the fact that the Bus Master IDE specs 361 * XXX say that "The bus master IDE function uses 16 bytes of IO 362 * XXX space," some controllers (at least the United 363 * XXX Microelectronics UM8886BF) place it in memory space. 364 */ 365 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 366 PCIIDE_REG_BUS_MASTER_DMA); 367 368 switch (maptype) { 369 case PCI_MAPREG_TYPE_IO: 370 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 371 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 372 &addr, NULL, NULL) == 0); 373 if (sc->sc_dma_ok == 0) { 374 aprint_normal( 375 ", but unused (couldn't query registers)"); 376 break; 377 } 378 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 379 && addr >= 0x10000) { 380 sc->sc_dma_ok = 0; 381 aprint_normal( 382 ", but unused (registers at unsafe address " 383 "%#lx)", (unsigned long)addr); 384 break; 385 } 386 /* FALLTHROUGH */ 387 388 case PCI_MAPREG_MEM_TYPE_32BIT: 389 sc->sc_dma_ok = (pci_mapreg_map(pa, 390 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 391 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 392 sc->sc_dmat = pa->pa_dmat; 393 if (sc->sc_dma_ok == 0) { 394 aprint_normal(", but unused (couldn't map registers)"); 395 } else { 396 sc->sc_wdcdev.dma_arg = sc; 397 sc->sc_wdcdev.dma_init = pciide_dma_init; 398 sc->sc_wdcdev.dma_start = pciide_dma_start; 399 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 400 } 401 402 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 403 PCIIDE_OPTIONS_NODMA) { 404 aprint_normal( 405 ", but unused (forced off by config file)"); 406 sc->sc_dma_ok = 0; 407 } 408 break; 409 410 default: 411 sc->sc_dma_ok = 0; 412 aprint_normal( 413 ", but unsupported register maptype (0x%x)", maptype); 414 } 415 416 if (sc->sc_dma_ok == 0) 417 return; 418 419 /* 420 * Set up the default handles for the DMA registers. 421 * Just reserve 32 bits for each handle, unless space 422 * doesn't permit it. 423 */ 424 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { 425 pc = &sc->pciide_channels[chan]; 426 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 427 size = 4; 428 if (size > (IDEDMA_SCH_OFFSET - reg)) 429 size = IDEDMA_SCH_OFFSET - reg; 430 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 431 IDEDMA_SCH_OFFSET * chan + reg, size, 432 &pc->dma_iohs[reg]) != 0) { 433 sc->sc_dma_ok = 0; 434 aprint_normal(", but can't subregion offset %d " 435 "size %lu", reg, (u_long)size); 436 return; 437 } 438 } 439 } 440 } 441 442 int 443 pciide_compat_intr(arg) 444 void *arg; 445 { 446 struct pciide_channel *cp = arg; 447 448 #ifdef DIAGNOSTIC 449 /* should only be called for a compat channel */ 450 if (cp->compat == 0) 451 panic("pciide compat intr called for non-compat chan %p", cp); 452 #endif 453 return (wdcintr(&cp->wdc_channel)); 454 } 455 456 int 457 pciide_pci_intr(arg) 458 void *arg; 459 { 460 struct pciide_softc *sc = arg; 461 struct pciide_channel *cp; 462 struct wdc_channel *wdc_cp; 463 int i, rv, crv; 464 465 rv = 0; 466 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 467 cp = &sc->pciide_channels[i]; 468 wdc_cp = &cp->wdc_channel; 469 470 /* If a compat channel skip. */ 471 if (cp->compat) 472 continue; 473 /* if this channel not waiting for intr, skip */ 474 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 475 continue; 476 477 crv = wdcintr(wdc_cp); 478 if (crv == 0) 479 ; /* leave rv alone */ 480 else if (crv == 1) 481 rv = 1; /* claim the intr */ 482 else if (rv == 0) /* crv should be -1 in this case */ 483 rv = crv; /* if we've done no better, take it */ 484 } 485 return (rv); 486 } 487 488 void 489 pciide_channel_dma_setup(cp) 490 struct pciide_channel *cp; 491 { 492 int drive; 493 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 494 struct ata_drive_datas *drvp; 495 496 for (drive = 0; drive < 2; drive++) { 497 drvp = &cp->wdc_channel.ch_drive[drive]; 498 /* If no drive, skip */ 499 if ((drvp->drive_flags & DRIVE) == 0) 500 continue; 501 /* setup DMA if needed */ 502 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 503 (drvp->drive_flags & DRIVE_UDMA) == 0) || 504 sc->sc_dma_ok == 0) { 505 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 506 continue; 507 } 508 if (pciide_dma_table_setup(sc, cp->wdc_channel.ch_channel, 509 drive) != 0) { 510 /* Abort DMA setup */ 511 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 512 continue; 513 } 514 } 515 } 516 517 int 518 pciide_dma_table_setup(sc, channel, drive) 519 struct pciide_softc *sc; 520 int channel, drive; 521 { 522 bus_dma_segment_t seg; 523 int error, rseg; 524 const bus_size_t dma_table_size = 525 sizeof(struct idedma_table) * NIDEDMA_TABLES; 526 struct pciide_dma_maps *dma_maps = 527 &sc->pciide_channels[channel].dma_maps[drive]; 528 529 /* If table was already allocated, just return */ 530 if (dma_maps->dma_table) 531 return 0; 532 533 /* Allocate memory for the DMA tables and map it */ 534 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 535 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 536 BUS_DMA_NOWAIT)) != 0) { 537 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 538 "allocate", drive, error); 539 return error; 540 } 541 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 542 dma_table_size, 543 (caddr_t *)&dma_maps->dma_table, 544 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 545 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 546 "map", drive, error); 547 return error; 548 } 549 ATADEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 550 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 551 (unsigned long)seg.ds_addr), DEBUG_PROBE); 552 /* Create and load table DMA map for this disk */ 553 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 554 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 555 &dma_maps->dmamap_table)) != 0) { 556 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 557 "create", drive, error); 558 return error; 559 } 560 if ((error = bus_dmamap_load(sc->sc_dmat, 561 dma_maps->dmamap_table, 562 dma_maps->dma_table, 563 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 564 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 565 "load", drive, error); 566 return error; 567 } 568 ATADEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 569 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 570 DEBUG_PROBE); 571 /* Create a xfer DMA map for this drive */ 572 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 573 NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 574 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 575 &dma_maps->dmamap_xfer)) != 0) { 576 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 577 "create xfer", drive, error); 578 return error; 579 } 580 return 0; 581 } 582 583 int 584 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 585 void *v; 586 int channel, drive; 587 void *databuf; 588 size_t datalen; 589 int flags; 590 { 591 struct pciide_softc *sc = v; 592 int error, seg; 593 struct pciide_channel *cp = &sc->pciide_channels[channel]; 594 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 595 596 error = bus_dmamap_load(sc->sc_dmat, 597 dma_maps->dmamap_xfer, 598 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 599 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 600 if (error) { 601 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 602 "load xfer", drive, error); 603 return error; 604 } 605 606 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 607 dma_maps->dmamap_xfer->dm_mapsize, 608 (flags & WDC_DMA_READ) ? 609 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 610 611 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 612 #ifdef DIAGNOSTIC 613 /* A segment must not cross a 64k boundary */ 614 { 615 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 616 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 617 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 618 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 619 printf("pciide_dma: segment %d physical addr 0x%lx" 620 " len 0x%lx not properly aligned\n", 621 seg, phys, len); 622 panic("pciide_dma: buf align"); 623 } 624 } 625 #endif 626 dma_maps->dma_table[seg].base_addr = 627 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 628 dma_maps->dma_table[seg].byte_count = 629 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 630 IDEDMA_BYTE_COUNT_MASK); 631 ATADEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 632 seg, le32toh(dma_maps->dma_table[seg].byte_count), 633 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 634 635 } 636 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 637 htole32(IDEDMA_BYTE_COUNT_EOT); 638 639 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 640 dma_maps->dmamap_table->dm_mapsize, 641 BUS_DMASYNC_PREWRITE); 642 643 /* Maps are ready. Start DMA function */ 644 #ifdef DIAGNOSTIC 645 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 646 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 647 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 648 panic("pciide_dma_init: table align"); 649 } 650 #endif 651 652 /* Clear status bits */ 653 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 654 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 655 /* Write table addr */ 656 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 657 dma_maps->dmamap_table->dm_segs[0].ds_addr); 658 /* set read/write */ 659 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 660 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 661 /* remember flags */ 662 dma_maps->dma_flags = flags; 663 return 0; 664 } 665 666 void 667 pciide_dma_start(v, channel, drive) 668 void *v; 669 int channel, drive; 670 { 671 struct pciide_softc *sc = v; 672 struct pciide_channel *cp = &sc->pciide_channels[channel]; 673 674 ATADEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 675 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 676 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 677 | IDEDMA_CMD_START); 678 } 679 680 int 681 pciide_dma_finish(v, channel, drive, force) 682 void *v; 683 int channel, drive; 684 int force; 685 { 686 struct pciide_softc *sc = v; 687 u_int8_t status; 688 int error = 0; 689 struct pciide_channel *cp = &sc->pciide_channels[channel]; 690 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 691 692 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0); 693 ATADEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 694 DEBUG_XFERS); 695 696 if (force == WDC_DMAEND_END && (status & IDEDMA_CTL_INTR) == 0) 697 return WDC_DMAST_NOIRQ; 698 699 /* stop DMA channel */ 700 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 701 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 702 & ~IDEDMA_CMD_START); 703 704 /* Unload the map of the data buffer */ 705 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 706 dma_maps->dmamap_xfer->dm_mapsize, 707 (dma_maps->dma_flags & WDC_DMA_READ) ? 708 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 709 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 710 711 if ((status & IDEDMA_CTL_ERR) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 712 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 713 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 714 error |= WDC_DMAST_ERR; 715 } 716 717 if ((status & IDEDMA_CTL_INTR) == 0 && force != WDC_DMAEND_ABRT_QUIET) { 718 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 719 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 720 drive, status); 721 error |= WDC_DMAST_NOIRQ; 722 } 723 724 if ((status & IDEDMA_CTL_ACT) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 725 /* data underrun, may be a valid condition for ATAPI */ 726 error |= WDC_DMAST_UNDER; 727 } 728 return error; 729 } 730 731 void 732 pciide_irqack(chp) 733 struct wdc_channel *chp; 734 { 735 struct pciide_channel *cp = (struct pciide_channel*)chp; 736 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 737 738 /* clear status bits in IDE DMA registers */ 739 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 740 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 741 } 742 743 /* some common code used by several chip_map */ 744 int 745 pciide_chansetup(sc, channel, interface) 746 struct pciide_softc *sc; 747 int channel; 748 pcireg_t interface; 749 { 750 struct pciide_channel *cp = &sc->pciide_channels[channel]; 751 sc->wdc_chanarray[channel] = &cp->wdc_channel; 752 cp->name = PCIIDE_CHANNEL_NAME(channel); 753 cp->wdc_channel.ch_channel = channel; 754 cp->wdc_channel.ch_wdc = &sc->sc_wdcdev; 755 cp->wdc_channel.ch_queue = 756 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 757 if (cp->wdc_channel.ch_queue == NULL) { 758 aprint_error("%s %s channel: " 759 "can't allocate memory for command queue", 760 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 761 return 0; 762 } 763 aprint_normal("%s: %s channel %s to %s mode\n", 764 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 765 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 766 "configured" : "wired", 767 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 768 "native-PCI" : "compatibility"); 769 return 1; 770 } 771 772 /* some common code used by several chip channel_map */ 773 void 774 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 775 struct pci_attach_args *pa; 776 struct pciide_channel *cp; 777 pcireg_t interface; 778 bus_size_t *cmdsizep, *ctlsizep; 779 int (*pci_intr) __P((void *)); 780 { 781 struct wdc_channel *wdc_cp = &cp->wdc_channel; 782 783 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) 784 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr); 785 else { 786 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep, 787 ctlsizep); 788 if ((cp->wdc_channel.ch_flags & WDCF_DISABLED) == 0) 789 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 790 } 791 wdcattach(wdc_cp); 792 } 793 794 /* 795 * generic code to map the compat intr. 796 */ 797 void 798 pciide_map_compat_intr(pa, cp, compatchan) 799 struct pci_attach_args *pa; 800 struct pciide_channel *cp; 801 int compatchan; 802 { 803 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 804 805 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 806 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 807 pa, compatchan, pciide_compat_intr, cp); 808 if (cp->ih == NULL) { 809 #endif 810 aprint_error("%s: no compatibility interrupt for use by %s " 811 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 812 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 813 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 814 } 815 #endif 816 } 817 818 void 819 default_chip_map(sc, pa) 820 struct pciide_softc *sc; 821 struct pci_attach_args *pa; 822 { 823 struct pciide_channel *cp; 824 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 825 pcireg_t csr; 826 int channel, drive; 827 struct ata_drive_datas *drvp; 828 u_int8_t idedma_ctl; 829 bus_size_t cmdsize, ctlsize; 830 char *failreason; 831 832 if (pciide_chipen(sc, pa) == 0) 833 return; 834 835 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 836 aprint_normal("%s: bus-master DMA support present", 837 sc->sc_wdcdev.sc_dev.dv_xname); 838 if (sc->sc_pp == &default_product_desc && 839 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 840 PCIIDE_OPTIONS_DMA) == 0) { 841 aprint_normal(", but unused (no driver support)"); 842 sc->sc_dma_ok = 0; 843 } else { 844 pciide_mapreg_dma(sc, pa); 845 if (sc->sc_dma_ok != 0) 846 aprint_normal(", used without full driver " 847 "support"); 848 } 849 } else { 850 aprint_normal("%s: hardware does not support DMA", 851 sc->sc_wdcdev.sc_dev.dv_xname); 852 sc->sc_dma_ok = 0; 853 } 854 aprint_normal("\n"); 855 if (sc->sc_dma_ok) { 856 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 857 sc->sc_wdcdev.irqack = pciide_irqack; 858 } 859 sc->sc_wdcdev.PIO_cap = 0; 860 sc->sc_wdcdev.DMA_cap = 0; 861 862 sc->sc_wdcdev.channels = sc->wdc_chanarray; 863 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 864 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 865 866 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 867 cp = &sc->pciide_channels[channel]; 868 if (pciide_chansetup(sc, channel, interface) == 0) 869 continue; 870 if (interface & PCIIDE_INTERFACE_PCI(channel)) 871 pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 872 pciide_pci_intr); 873 else 874 pciide_mapregs_compat(pa, cp, 875 cp->wdc_channel.ch_channel, &cmdsize, &ctlsize); 876 if (cp->wdc_channel.ch_flags & WDCF_DISABLED) 877 continue; 878 /* 879 * Check to see if something appears to be there. 880 */ 881 failreason = NULL; 882 /* 883 * In native mode, always enable the controller. It's 884 * not possible to have an ISA board using the same address 885 * anyway. 886 */ 887 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 888 wdcattach(&cp->wdc_channel); 889 continue; 890 } 891 if (!wdcprobe(&cp->wdc_channel)) { 892 failreason = "not responding; disabled or no drives?"; 893 goto next; 894 } 895 /* 896 * Now, make sure it's actually attributable to this PCI IDE 897 * channel by trying to access the channel again while the 898 * PCI IDE controller's I/O space is disabled. (If the 899 * channel no longer appears to be there, it belongs to 900 * this controller.) YUCK! 901 */ 902 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 903 PCI_COMMAND_STATUS_REG); 904 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 905 csr & ~PCI_COMMAND_IO_ENABLE); 906 if (wdcprobe(&cp->wdc_channel)) 907 failreason = "other hardware responding at addresses"; 908 pci_conf_write(sc->sc_pc, sc->sc_tag, 909 PCI_COMMAND_STATUS_REG, csr); 910 next: 911 if (failreason) { 912 aprint_error("%s: %s channel ignored (%s)\n", 913 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 914 failreason); 915 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 916 bus_space_unmap(cp->wdc_channel.cmd_iot, 917 cp->wdc_channel.cmd_baseioh, cmdsize); 918 bus_space_unmap(cp->wdc_channel.ctl_iot, 919 cp->wdc_channel.ctl_ioh, ctlsize); 920 } else { 921 pciide_map_compat_intr(pa, cp, 922 cp->wdc_channel.ch_channel); 923 wdcattach(&cp->wdc_channel); 924 } 925 } 926 927 if (sc->sc_dma_ok == 0) 928 return; 929 930 /* Allocate DMA maps */ 931 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 932 idedma_ctl = 0; 933 cp = &sc->pciide_channels[channel]; 934 for (drive = 0; drive < 2; drive++) { 935 drvp = &cp->wdc_channel.ch_drive[drive]; 936 /* If no drive, skip */ 937 if ((drvp->drive_flags & DRIVE) == 0) 938 continue; 939 if ((drvp->drive_flags & DRIVE_DMA) == 0) 940 continue; 941 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 942 /* Abort DMA setup */ 943 aprint_error( 944 "%s:%d:%d: can't allocate DMA maps, " 945 "using PIO transfers\n", 946 sc->sc_wdcdev.sc_dev.dv_xname, 947 channel, drive); 948 drvp->drive_flags &= ~DRIVE_DMA; 949 } 950 aprint_normal("%s:%d:%d: using DMA data transfers\n", 951 sc->sc_wdcdev.sc_dev.dv_xname, 952 channel, drive); 953 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 954 } 955 if (idedma_ctl != 0) { 956 /* Add software bits in status register */ 957 bus_space_write_1(sc->sc_dma_iot, 958 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 959 } 960 } 961 } 962 963 void 964 sata_setup_channel(chp) 965 struct wdc_channel *chp; 966 { 967 struct ata_drive_datas *drvp; 968 int drive; 969 u_int32_t idedma_ctl; 970 struct pciide_channel *cp = (struct pciide_channel*)chp; 971 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.ch_wdc; 972 973 /* setup DMA if needed */ 974 pciide_channel_dma_setup(cp); 975 976 idedma_ctl = 0; 977 978 for (drive = 0; drive < 2; drive++) { 979 drvp = &chp->ch_drive[drive]; 980 /* If no drive, skip */ 981 if ((drvp->drive_flags & DRIVE) == 0) 982 continue; 983 if (drvp->drive_flags & DRIVE_UDMA) { 984 /* use Ultra/DMA */ 985 drvp->drive_flags &= ~DRIVE_DMA; 986 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 987 } else if (drvp->drive_flags & DRIVE_DMA) { 988 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 989 } 990 } 991 992 /* 993 * Nothing to do to setup modes; it is meaningless in S-ATA 994 * (but many S-ATA drives still want to get the SET_FEATURE 995 * command). 996 */ 997 if (idedma_ctl != 0) { 998 /* Add software bits in status register */ 999 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 1000 idedma_ctl); 1001 } 1002 } 1003
Indexes created Thu Oct 02 07:10:07 GMT 2025