pciide_common.c revision 1.2
1 /* $NetBSD: pciide_common.c,v 1.2 2003/10/23 19:29:35 bouyer Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.2 2003/10/23 19:29:35 bouyer Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/malloc.h> 83 84 #include <uvm/uvm_extern.h> 85 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pcidevs.h> 89 #include <dev/pci/pciidereg.h> 90 #include <dev/pci/pciidevar.h> 91 92 #ifdef WDCDEBUG 93 int wdcdebug_pciide_mask = 0; 94 #endif 95 96 static const char dmaerrfmt[] = 97 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 98 99 100 101 /* options passed via the 'flags' config keyword */ 102 #define PCIIDE_OPTIONS_DMA 0x01 103 #define PCIIDE_OPTIONS_NODMA 0x02 104 105 /* Default product description for devices not known from this controller */ 106 const struct pciide_product_desc default_product_desc = { 107 0, 108 0, 109 "Generic PCI IDE controller", 110 default_chip_map, 111 }; 112 113 const struct pciide_product_desc * 114 pciide_lookup_product(id, pp) 115 pcireg_t id; 116 const struct pciide_product_desc *pp; 117 { 118 for (; pp->chip_map != NULL; pp++) 119 if (PCI_PRODUCT(id) == pp->ide_product) 120 break; 121 122 if (pp->chip_map == NULL) 123 return NULL; 124 return pp; 125 } 126 127 void 128 pciide_common_attach(sc, pa, pp) 129 struct pciide_softc *sc; 130 struct pci_attach_args *pa; 131 const struct pciide_product_desc *pp; 132 { 133 pci_chipset_tag_t pc = pa->pa_pc; 134 pcitag_t tag = pa->pa_tag; 135 pcireg_t csr; 136 char devinfo[256]; 137 const char *displaydev; 138 139 aprint_naive(": disk controller\n"); 140 aprint_normal("\n"); 141 142 sc->sc_pci_id = pa->pa_id; 143 if (pp == NULL) { 144 /* should only happen for generic pciide devices */ 145 sc->sc_pp = &default_product_desc; 146 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 147 displaydev = devinfo; 148 } else { 149 sc->sc_pp = pp; 150 displaydev = sc->sc_pp->ide_name; 151 } 152 153 /* if displaydev == NULL, printf is done in chip-specific map */ 154 if (displaydev) 155 aprint_normal("%s: %s (rev. 0x%02x)\n", 156 sc->sc_wdcdev.sc_dev.dv_xname, displaydev, 157 PCI_REVISION(pa->pa_class)); 158 159 sc->sc_pc = pa->pa_pc; 160 sc->sc_tag = pa->pa_tag; 161 162 /* Set up DMA defaults; these might be adjusted by chip_map. */ 163 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 164 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 165 166 #ifdef WDCDEBUG 167 if (wdcdebug_pciide_mask & DEBUG_PROBE) 168 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 169 #endif 170 sc->sc_pp->chip_map(sc, pa); 171 172 if (sc->sc_dma_ok) { 173 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 174 csr |= PCI_COMMAND_MASTER_ENABLE; 175 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 176 } 177 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 178 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 179 } 180 181 /* tell whether the chip is enabled or not */ 182 int 183 pciide_chipen(sc, pa) 184 struct pciide_softc *sc; 185 struct pci_attach_args *pa; 186 { 187 pcireg_t csr; 188 189 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 190 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 191 PCI_COMMAND_STATUS_REG); 192 aprint_normal("%s: device disabled (at %s)\n", 193 sc->sc_wdcdev.sc_dev.dv_xname, 194 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 195 "device" : "bridge"); 196 return 0; 197 } 198 return 1; 199 } 200 201 void 202 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 203 struct pci_attach_args *pa; 204 struct pciide_channel *cp; 205 int compatchan; 206 bus_size_t *cmdsizep, *ctlsizep; 207 { 208 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 209 struct channel_softc *wdc_cp = &cp->wdc_channel; 210 211 cp->compat = 1; 212 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 213 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 214 215 wdc_cp->cmd_iot = pa->pa_iot; 216 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 217 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_ioh) != 0) { 218 aprint_error("%s: couldn't map %s channel cmd regs\n", 219 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 220 goto bad; 221 } 222 223 wdc_cp->ctl_iot = pa->pa_iot; 224 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 225 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 226 aprint_error("%s: couldn't map %s channel ctl regs\n", 227 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 228 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, 229 PCIIDE_COMPAT_CMD_SIZE); 230 goto bad; 231 } 232 233 wdc_cp->data32iot = wdc_cp->cmd_iot; 234 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 235 pciide_map_compat_intr(pa, cp, compatchan); 236 return; 237 238 bad: 239 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 240 return; 241 } 242 243 void 244 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 245 struct pci_attach_args * pa; 246 struct pciide_channel *cp; 247 bus_size_t *cmdsizep, *ctlsizep; 248 int (*pci_intr) __P((void *)); 249 { 250 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 251 struct channel_softc *wdc_cp = &cp->wdc_channel; 252 const char *intrstr; 253 pci_intr_handle_t intrhandle; 254 255 cp->compat = 0; 256 257 if (sc->sc_pci_ih == NULL) { 258 if (pci_intr_map(pa, &intrhandle) != 0) { 259 aprint_error("%s: couldn't map native-PCI interrupt\n", 260 sc->sc_wdcdev.sc_dev.dv_xname); 261 goto bad; 262 } 263 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 264 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 265 intrhandle, IPL_BIO, pci_intr, sc); 266 if (sc->sc_pci_ih != NULL) { 267 aprint_normal("%s: using %s for native-PCI interrupt\n", 268 sc->sc_wdcdev.sc_dev.dv_xname, 269 intrstr ? intrstr : "unknown interrupt"); 270 } else { 271 aprint_error( 272 "%s: couldn't establish native-PCI interrupt", 273 sc->sc_wdcdev.sc_dev.dv_xname); 274 if (intrstr != NULL) 275 aprint_normal(" at %s", intrstr); 276 aprint_normal("\n"); 277 goto bad; 278 } 279 } 280 cp->ih = sc->sc_pci_ih; 281 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 282 PCI_MAPREG_TYPE_IO, 0, 283 &wdc_cp->cmd_iot, &wdc_cp->cmd_ioh, NULL, cmdsizep) != 0) { 284 aprint_error("%s: couldn't map %s channel cmd regs\n", 285 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 286 goto bad; 287 } 288 289 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 290 PCI_MAPREG_TYPE_IO, 0, 291 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 292 aprint_error("%s: couldn't map %s channel ctl regs\n", 293 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 294 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 295 goto bad; 296 } 297 /* 298 * In native mode, 4 bytes of I/O space are mapped for the control 299 * register, the control register is at offset 2. Pass the generic 300 * code a handle for only one byte at the right offset. 301 */ 302 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 303 &wdc_cp->ctl_ioh) != 0) { 304 aprint_error("%s: unable to subregion %s channel ctl regs\n", 305 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 306 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_ioh, *cmdsizep); 307 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 308 goto bad; 309 } 310 311 wdc_cp->data32iot = wdc_cp->cmd_iot; 312 wdc_cp->data32ioh = wdc_cp->cmd_ioh; 313 return; 314 315 bad: 316 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 317 return; 318 } 319 320 void 321 pciide_mapreg_dma(sc, pa) 322 struct pciide_softc *sc; 323 struct pci_attach_args *pa; 324 { 325 pcireg_t maptype; 326 bus_addr_t addr; 327 328 /* 329 * Map DMA registers 330 * 331 * Note that sc_dma_ok is the right variable to test to see if 332 * DMA can be done. If the interface doesn't support DMA, 333 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 334 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 335 * non-zero if the interface supports DMA and the registers 336 * could be mapped. 337 * 338 * XXX Note that despite the fact that the Bus Master IDE specs 339 * XXX say that "The bus master IDE function uses 16 bytes of IO 340 * XXX space," some controllers (at least the United 341 * XXX Microelectronics UM8886BF) place it in memory space. 342 */ 343 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 344 PCIIDE_REG_BUS_MASTER_DMA); 345 346 switch (maptype) { 347 case PCI_MAPREG_TYPE_IO: 348 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 349 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 350 &addr, NULL, NULL) == 0); 351 if (sc->sc_dma_ok == 0) { 352 aprint_normal( 353 ", but unused (couldn't query registers)"); 354 break; 355 } 356 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 357 && addr >= 0x10000) { 358 sc->sc_dma_ok = 0; 359 aprint_normal( 360 ", but unused (registers at unsafe address " 361 "%#lx)", (unsigned long)addr); 362 break; 363 } 364 /* FALLTHROUGH */ 365 366 case PCI_MAPREG_MEM_TYPE_32BIT: 367 sc->sc_dma_ok = (pci_mapreg_map(pa, 368 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 369 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 370 sc->sc_dmat = pa->pa_dmat; 371 if (sc->sc_dma_ok == 0) { 372 aprint_normal(", but unused (couldn't map registers)"); 373 } else { 374 sc->sc_wdcdev.dma_arg = sc; 375 sc->sc_wdcdev.dma_init = pciide_dma_init; 376 sc->sc_wdcdev.dma_start = pciide_dma_start; 377 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 378 } 379 380 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 381 PCIIDE_OPTIONS_NODMA) { 382 aprint_normal( 383 ", but unused (forced off by config file)"); 384 sc->sc_dma_ok = 0; 385 } 386 break; 387 388 default: 389 sc->sc_dma_ok = 0; 390 aprint_normal( 391 ", but unsupported register maptype (0x%x)", maptype); 392 } 393 } 394 395 int 396 pciide_compat_intr(arg) 397 void *arg; 398 { 399 struct pciide_channel *cp = arg; 400 401 #ifdef DIAGNOSTIC 402 /* should only be called for a compat channel */ 403 if (cp->compat == 0) 404 panic("pciide compat intr called for non-compat chan %p", cp); 405 #endif 406 return (wdcintr(&cp->wdc_channel)); 407 } 408 409 int 410 pciide_pci_intr(arg) 411 void *arg; 412 { 413 struct pciide_softc *sc = arg; 414 struct pciide_channel *cp; 415 struct channel_softc *wdc_cp; 416 int i, rv, crv; 417 418 rv = 0; 419 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 420 cp = &sc->pciide_channels[i]; 421 wdc_cp = &cp->wdc_channel; 422 423 /* If a compat channel skip. */ 424 if (cp->compat) 425 continue; 426 /* if this channel not waiting for intr, skip */ 427 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 428 continue; 429 430 crv = wdcintr(wdc_cp); 431 if (crv == 0) 432 ; /* leave rv alone */ 433 else if (crv == 1) 434 rv = 1; /* claim the intr */ 435 else if (rv == 0) /* crv should be -1 in this case */ 436 rv = crv; /* if we've done no better, take it */ 437 } 438 return (rv); 439 } 440 441 void 442 pciide_channel_dma_setup(cp) 443 struct pciide_channel *cp; 444 { 445 int drive; 446 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 447 struct ata_drive_datas *drvp; 448 449 for (drive = 0; drive < 2; drive++) { 450 drvp = &cp->wdc_channel.ch_drive[drive]; 451 /* If no drive, skip */ 452 if ((drvp->drive_flags & DRIVE) == 0) 453 continue; 454 /* setup DMA if needed */ 455 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 456 (drvp->drive_flags & DRIVE_UDMA) == 0) || 457 sc->sc_dma_ok == 0) { 458 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 459 continue; 460 } 461 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 462 != 0) { 463 /* Abort DMA setup */ 464 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 465 continue; 466 } 467 } 468 } 469 470 int 471 pciide_dma_table_setup(sc, channel, drive) 472 struct pciide_softc *sc; 473 int channel, drive; 474 { 475 bus_dma_segment_t seg; 476 int error, rseg; 477 const bus_size_t dma_table_size = 478 sizeof(struct idedma_table) * NIDEDMA_TABLES; 479 struct pciide_dma_maps *dma_maps = 480 &sc->pciide_channels[channel].dma_maps[drive]; 481 482 /* If table was already allocated, just return */ 483 if (dma_maps->dma_table) 484 return 0; 485 486 /* Allocate memory for the DMA tables and map it */ 487 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 488 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 489 BUS_DMA_NOWAIT)) != 0) { 490 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 491 "allocate", drive, error); 492 return error; 493 } 494 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 495 dma_table_size, 496 (caddr_t *)&dma_maps->dma_table, 497 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 498 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 499 "map", drive, error); 500 return error; 501 } 502 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 503 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 504 (unsigned long)seg.ds_addr), DEBUG_PROBE); 505 /* Create and load table DMA map for this disk */ 506 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 507 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 508 &dma_maps->dmamap_table)) != 0) { 509 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 510 "create", drive, error); 511 return error; 512 } 513 if ((error = bus_dmamap_load(sc->sc_dmat, 514 dma_maps->dmamap_table, 515 dma_maps->dma_table, 516 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 517 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 518 "load", drive, error); 519 return error; 520 } 521 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 522 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 523 DEBUG_PROBE); 524 /* Create a xfer DMA map for this drive */ 525 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 526 NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 527 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 528 &dma_maps->dmamap_xfer)) != 0) { 529 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 530 "create xfer", drive, error); 531 return error; 532 } 533 return 0; 534 } 535 536 int 537 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 538 void *v; 539 int channel, drive; 540 void *databuf; 541 size_t datalen; 542 int flags; 543 { 544 struct pciide_softc *sc = v; 545 int error, seg; 546 struct pciide_dma_maps *dma_maps = 547 &sc->pciide_channels[channel].dma_maps[drive]; 548 549 error = bus_dmamap_load(sc->sc_dmat, 550 dma_maps->dmamap_xfer, 551 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 552 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 553 if (error) { 554 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 555 "load xfer", drive, error); 556 return error; 557 } 558 559 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 560 dma_maps->dmamap_xfer->dm_mapsize, 561 (flags & WDC_DMA_READ) ? 562 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 563 564 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 565 #ifdef DIAGNOSTIC 566 /* A segment must not cross a 64k boundary */ 567 { 568 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 569 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 570 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 571 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 572 printf("pciide_dma: segment %d physical addr 0x%lx" 573 " len 0x%lx not properly aligned\n", 574 seg, phys, len); 575 panic("pciide_dma: buf align"); 576 } 577 } 578 #endif 579 dma_maps->dma_table[seg].base_addr = 580 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 581 dma_maps->dma_table[seg].byte_count = 582 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 583 IDEDMA_BYTE_COUNT_MASK); 584 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 585 seg, le32toh(dma_maps->dma_table[seg].byte_count), 586 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 587 588 } 589 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 590 htole32(IDEDMA_BYTE_COUNT_EOT); 591 592 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 593 dma_maps->dmamap_table->dm_mapsize, 594 BUS_DMASYNC_PREWRITE); 595 596 /* Maps are ready. Start DMA function */ 597 #ifdef DIAGNOSTIC 598 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 599 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 600 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 601 panic("pciide_dma_init: table align"); 602 } 603 #endif 604 605 /* Clear status bits */ 606 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 607 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, 608 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 609 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel)); 610 /* Write table addr */ 611 bus_space_write_4(sc->sc_dma_iot, sc->sc_dma_ioh, 612 IDEDMA_TBL + IDEDMA_SCH_OFFSET * channel, 613 dma_maps->dmamap_table->dm_segs[0].ds_addr); 614 /* set read/write */ 615 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 616 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 617 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE: 0); 618 /* remember flags */ 619 dma_maps->dma_flags = flags; 620 return 0; 621 } 622 623 void 624 pciide_dma_start(v, channel, drive) 625 void *v; 626 int channel, drive; 627 { 628 struct pciide_softc *sc = v; 629 630 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 631 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 632 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 633 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 634 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) | IDEDMA_CMD_START); 635 } 636 637 int 638 pciide_dma_finish(v, channel, drive, force) 639 void *v; 640 int channel, drive; 641 int force; 642 { 643 struct pciide_softc *sc = v; 644 u_int8_t status; 645 int error = 0; 646 struct pciide_dma_maps *dma_maps = 647 &sc->pciide_channels[channel].dma_maps[drive]; 648 649 status = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 650 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel); 651 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 652 DEBUG_XFERS); 653 654 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 655 return WDC_DMAST_NOIRQ; 656 657 /* stop DMA channel */ 658 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 659 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel, 660 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 661 IDEDMA_CMD + IDEDMA_SCH_OFFSET * channel) & ~IDEDMA_CMD_START); 662 663 /* Unload the map of the data buffer */ 664 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 665 dma_maps->dmamap_xfer->dm_mapsize, 666 (dma_maps->dma_flags & WDC_DMA_READ) ? 667 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 668 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 669 670 if ((status & IDEDMA_CTL_ERR) != 0) { 671 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 672 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 673 error |= WDC_DMAST_ERR; 674 } 675 676 if ((status & IDEDMA_CTL_INTR) == 0) { 677 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 678 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 679 drive, status); 680 error |= WDC_DMAST_NOIRQ; 681 } 682 683 if ((status & IDEDMA_CTL_ACT) != 0) { 684 /* data underrun, may be a valid condition for ATAPI */ 685 error |= WDC_DMAST_UNDER; 686 } 687 return error; 688 } 689 690 void 691 pciide_irqack(chp) 692 struct channel_softc *chp; 693 { 694 struct pciide_channel *cp = (struct pciide_channel*)chp; 695 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 696 697 /* clear status bits in IDE DMA registers */ 698 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 699 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel, 700 bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 701 IDEDMA_CTL + IDEDMA_SCH_OFFSET * chp->channel)); 702 } 703 704 /* some common code used by several chip_map */ 705 int 706 pciide_chansetup(sc, channel, interface) 707 struct pciide_softc *sc; 708 int channel; 709 pcireg_t interface; 710 { 711 struct pciide_channel *cp = &sc->pciide_channels[channel]; 712 sc->wdc_chanarray[channel] = &cp->wdc_channel; 713 cp->name = PCIIDE_CHANNEL_NAME(channel); 714 cp->wdc_channel.channel = channel; 715 cp->wdc_channel.wdc = &sc->sc_wdcdev; 716 cp->wdc_channel.ch_queue = 717 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 718 if (cp->wdc_channel.ch_queue == NULL) { 719 aprint_error("%s %s channel: " 720 "can't allocate memory for command queue", 721 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 722 return 0; 723 } 724 aprint_normal("%s: %s channel %s to %s mode\n", 725 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 726 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 727 "configured" : "wired", 728 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 729 "native-PCI" : "compatibility"); 730 return 1; 731 } 732 733 /* some common code used by several chip channel_map */ 734 void 735 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 736 struct pci_attach_args *pa; 737 struct pciide_channel *cp; 738 pcireg_t interface; 739 bus_size_t *cmdsizep, *ctlsizep; 740 int (*pci_intr) __P((void *)); 741 { 742 struct channel_softc *wdc_cp = &cp->wdc_channel; 743 744 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 745 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr); 746 else 747 pciide_mapregs_compat(pa, cp, wdc_cp->channel, cmdsizep, 748 ctlsizep); 749 wdcattach(wdc_cp); 750 } 751 752 /* 753 * generic code to map the compat intr. 754 */ 755 void 756 pciide_map_compat_intr(pa, cp, compatchan) 757 struct pci_attach_args *pa; 758 struct pciide_channel *cp; 759 int compatchan; 760 { 761 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 762 763 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 764 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 765 pa, compatchan, pciide_compat_intr, cp); 766 if (cp->ih == NULL) { 767 #endif 768 aprint_error("%s: no compatibility interrupt for use by %s " 769 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 770 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 771 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 772 } 773 #endif 774 } 775 776 void 777 default_chip_map(sc, pa) 778 struct pciide_softc *sc; 779 struct pci_attach_args *pa; 780 { 781 struct pciide_channel *cp; 782 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 783 pcireg_t csr; 784 int channel, drive; 785 struct ata_drive_datas *drvp; 786 u_int8_t idedma_ctl; 787 bus_size_t cmdsize, ctlsize; 788 char *failreason; 789 790 if (pciide_chipen(sc, pa) == 0) 791 return; 792 793 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 794 aprint_normal("%s: bus-master DMA support present", 795 sc->sc_wdcdev.sc_dev.dv_xname); 796 if (sc->sc_pp == &default_product_desc && 797 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 798 PCIIDE_OPTIONS_DMA) == 0) { 799 aprint_normal(", but unused (no driver support)"); 800 sc->sc_dma_ok = 0; 801 } else { 802 pciide_mapreg_dma(sc, pa); 803 if (sc->sc_dma_ok != 0) 804 aprint_normal(", used without full driver " 805 "support"); 806 } 807 } else { 808 aprint_normal("%s: hardware does not support DMA", 809 sc->sc_wdcdev.sc_dev.dv_xname); 810 sc->sc_dma_ok = 0; 811 } 812 aprint_normal("\n"); 813 if (sc->sc_dma_ok) { 814 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 815 sc->sc_wdcdev.irqack = pciide_irqack; 816 } 817 sc->sc_wdcdev.PIO_cap = 0; 818 sc->sc_wdcdev.DMA_cap = 0; 819 820 sc->sc_wdcdev.channels = sc->wdc_chanarray; 821 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 822 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 823 824 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 825 cp = &sc->pciide_channels[channel]; 826 if (pciide_chansetup(sc, channel, interface) == 0) 827 continue; 828 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 829 pciide_pci_intr); 830 if (cp->wdc_channel.ch_flags & WDCF_DISABLED) 831 continue; 832 /* 833 * Check to see if something appears to be there. 834 */ 835 failreason = NULL; 836 /* 837 * In native mode, always enable the controller. It's 838 * not possible to have an ISA board using the same address 839 * anyway. 840 */ 841 if (interface & PCIIDE_INTERFACE_PCI(channel)) 842 goto next; 843 if (!wdcprobe(&cp->wdc_channel)) { 844 failreason = "not responding; disabled or no drives?"; 845 goto next; 846 } 847 /* 848 * Now, make sure it's actually attributable to this PCI IDE 849 * channel by trying to access the channel again while the 850 * PCI IDE controller's I/O space is disabled. (If the 851 * channel no longer appears to be there, it belongs to 852 * this controller.) YUCK! 853 */ 854 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 855 PCI_COMMAND_STATUS_REG); 856 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 857 csr & ~PCI_COMMAND_IO_ENABLE); 858 if (wdcprobe(&cp->wdc_channel)) 859 failreason = "other hardware responding at addresses"; 860 pci_conf_write(sc->sc_pc, sc->sc_tag, 861 PCI_COMMAND_STATUS_REG, csr); 862 next: 863 if (failreason) { 864 aprint_error("%s: %s channel ignored (%s)\n", 865 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 866 failreason); 867 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 868 bus_space_unmap(cp->wdc_channel.cmd_iot, 869 cp->wdc_channel.cmd_ioh, cmdsize); 870 bus_space_unmap(cp->wdc_channel.ctl_iot, 871 cp->wdc_channel.ctl_ioh, ctlsize); 872 873 } 874 } 875 876 if (sc->sc_dma_ok == 0) 877 return; 878 879 /* Allocate DMA maps */ 880 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 881 idedma_ctl = 0; 882 cp = &sc->pciide_channels[channel]; 883 for (drive = 0; drive < 2; drive++) { 884 drvp = &cp->wdc_channel.ch_drive[drive]; 885 /* If no drive, skip */ 886 if ((drvp->drive_flags & DRIVE) == 0) 887 continue; 888 if ((drvp->drive_flags & DRIVE_DMA) == 0) 889 continue; 890 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 891 /* Abort DMA setup */ 892 aprint_error( 893 "%s:%d:%d: can't allocate DMA maps, " 894 "using PIO transfers\n", 895 sc->sc_wdcdev.sc_dev.dv_xname, 896 channel, drive); 897 drvp->drive_flags &= ~DRIVE_DMA; 898 } 899 aprint_normal("%s:%d:%d: using DMA data transfers\n", 900 sc->sc_wdcdev.sc_dev.dv_xname, 901 channel, drive); 902 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 903 } 904 if (idedma_ctl != 0) { 905 /* Add software bits in status register */ 906 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 907 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * channel), 908 idedma_ctl); 909 } 910 } 911 } 912 913 void 914 sata_setup_channel(chp) 915 struct channel_softc *chp; 916 { 917 struct ata_drive_datas *drvp; 918 int drive; 919 u_int32_t idedma_ctl; 920 struct pciide_channel *cp = (struct pciide_channel*)chp; 921 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 922 923 /* setup DMA if needed */ 924 pciide_channel_dma_setup(cp); 925 926 idedma_ctl = 0; 927 928 for (drive = 0; drive < 2; drive++) { 929 drvp = &chp->ch_drive[drive]; 930 /* If no drive, skip */ 931 if ((drvp->drive_flags & DRIVE) == 0) 932 continue; 933 if (drvp->drive_flags & DRIVE_UDMA) { 934 /* use Ultra/DMA */ 935 drvp->drive_flags &= ~DRIVE_DMA; 936 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 937 } else if (drvp->drive_flags & DRIVE_DMA) { 938 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 939 } 940 } 941 942 /* 943 * Nothing to do to setup modes; it is meaningless in S-ATA 944 * (but many S-ATA drives still want to get the SET_FEATURE 945 * command). 946 */ 947 if (idedma_ctl != 0) { 948 /* Add software bits in status register */ 949 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 950 IDEDMA_CTL + (IDEDMA_SCH_OFFSET * chp->channel), 951 idedma_ctl); 952 } 953 } 954
Indexes created Thu Oct 02 07:10:07 GMT 2025