pciide_common.c revision 1.20
1 /* $NetBSD: pciide_common.c,v 1.20 2004/08/20 06:39:39 thorpej Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.20 2004/08/20 06:39:39 thorpej Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/malloc.h> 83 84 #include <uvm/uvm_extern.h> 85 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pcidevs.h> 89 #include <dev/pci/pciidereg.h> 90 #include <dev/pci/pciidevar.h> 91 92 #include <dev/ic/wdcreg.h> 93 94 #ifdef ATADEBUG 95 int atadebug_pciide_mask = 0; 96 #endif 97 98 static const char dmaerrfmt[] = 99 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 100 101 /* Default product description for devices not known from this controller */ 102 const struct pciide_product_desc default_product_desc = { 103 0, 104 0, 105 "Generic PCI IDE controller", 106 default_chip_map, 107 }; 108 109 const struct pciide_product_desc * 110 pciide_lookup_product(id, pp) 111 pcireg_t id; 112 const struct pciide_product_desc *pp; 113 { 114 for (; pp->chip_map != NULL; pp++) 115 if (PCI_PRODUCT(id) == pp->ide_product) 116 break; 117 118 if (pp->chip_map == NULL) 119 return NULL; 120 return pp; 121 } 122 123 void 124 pciide_common_attach(sc, pa, pp) 125 struct pciide_softc *sc; 126 struct pci_attach_args *pa; 127 const struct pciide_product_desc *pp; 128 { 129 pci_chipset_tag_t pc = pa->pa_pc; 130 pcitag_t tag = pa->pa_tag; 131 pcireg_t csr; 132 char devinfo[256]; 133 const char *displaydev; 134 135 aprint_naive(": disk controller\n"); 136 aprint_normal("\n"); 137 138 sc->sc_pci_id = pa->pa_id; 139 if (pp == NULL) { 140 /* should only happen for generic pciide devices */ 141 sc->sc_pp = &default_product_desc; 142 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 143 displaydev = devinfo; 144 } else { 145 sc->sc_pp = pp; 146 displaydev = sc->sc_pp->ide_name; 147 } 148 149 /* if displaydev == NULL, printf is done in chip-specific map */ 150 if (displaydev) 151 aprint_normal("%s: %s (rev. 0x%02x)\n", 152 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, displaydev, 153 PCI_REVISION(pa->pa_class)); 154 155 sc->sc_pc = pa->pa_pc; 156 sc->sc_tag = pa->pa_tag; 157 158 /* Set up DMA defaults; these might be adjusted by chip_map. */ 159 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 160 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 161 162 #ifdef ATADEBUG 163 if (atadebug_pciide_mask & DEBUG_PROBE) 164 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 165 #endif 166 sc->sc_pp->chip_map(sc, pa); 167 168 if (sc->sc_dma_ok) { 169 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 170 csr |= PCI_COMMAND_MASTER_ENABLE; 171 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 172 } 173 ATADEBUG_PRINT(("pciide: command/status register=%x\n", 174 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 175 } 176 177 /* tell whether the chip is enabled or not */ 178 int 179 pciide_chipen(sc, pa) 180 struct pciide_softc *sc; 181 struct pci_attach_args *pa; 182 { 183 pcireg_t csr; 184 185 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 186 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 187 PCI_COMMAND_STATUS_REG); 188 aprint_normal("%s: device disabled (at %s)\n", 189 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 190 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 191 "device" : "bridge"); 192 return 0; 193 } 194 return 1; 195 } 196 197 void 198 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 199 struct pci_attach_args *pa; 200 struct pciide_channel *cp; 201 int compatchan; 202 bus_size_t *cmdsizep, *ctlsizep; 203 { 204 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 205 struct ata_channel *wdc_cp = &cp->ata_channel; 206 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 207 int i; 208 209 cp->compat = 1; 210 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 211 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 212 213 wdr->cmd_iot = pa->pa_iot; 214 if (bus_space_map(wdr->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 215 PCIIDE_COMPAT_CMD_SIZE, 0, &wdr->cmd_baseioh) != 0) { 216 aprint_error("%s: couldn't map %s channel cmd regs\n", 217 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 218 goto bad; 219 } 220 221 wdr->ctl_iot = pa->pa_iot; 222 if (bus_space_map(wdr->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 223 PCIIDE_COMPAT_CTL_SIZE, 0, &wdr->ctl_ioh) != 0) { 224 aprint_error("%s: couldn't map %s channel ctl regs\n", 225 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 226 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 227 PCIIDE_COMPAT_CMD_SIZE); 228 goto bad; 229 } 230 231 for (i = 0; i < WDC_NREG; i++) { 232 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 233 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 234 aprint_error("%s: couldn't subregion %s channel " 235 "cmd regs\n", 236 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 237 goto bad; 238 } 239 } 240 wdc_init_shadow_regs(wdc_cp); 241 wdr->data32iot = wdr->cmd_iot; 242 wdr->data32ioh = wdr->cmd_iohs[0]; 243 return; 244 245 bad: 246 cp->ata_channel.ch_flags |= ATACH_DISABLED; 247 return; 248 } 249 250 void 251 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 252 struct pci_attach_args * pa; 253 struct pciide_channel *cp; 254 bus_size_t *cmdsizep, *ctlsizep; 255 int (*pci_intr) __P((void *)); 256 { 257 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 258 struct ata_channel *wdc_cp = &cp->ata_channel; 259 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 260 const char *intrstr; 261 pci_intr_handle_t intrhandle; 262 int i; 263 264 cp->compat = 0; 265 266 if (sc->sc_pci_ih == NULL) { 267 if (pci_intr_map(pa, &intrhandle) != 0) { 268 aprint_error("%s: couldn't map native-PCI interrupt\n", 269 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 270 goto bad; 271 } 272 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 273 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 274 intrhandle, IPL_BIO, pci_intr, sc); 275 if (sc->sc_pci_ih != NULL) { 276 aprint_normal("%s: using %s for native-PCI interrupt\n", 277 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 278 intrstr ? intrstr : "unknown interrupt"); 279 } else { 280 aprint_error( 281 "%s: couldn't establish native-PCI interrupt", 282 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 283 if (intrstr != NULL) 284 aprint_normal(" at %s", intrstr); 285 aprint_normal("\n"); 286 goto bad; 287 } 288 } 289 cp->ih = sc->sc_pci_ih; 290 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel), 291 PCI_MAPREG_TYPE_IO, 0, 292 &wdr->cmd_iot, &wdr->cmd_baseioh, NULL, cmdsizep) != 0) { 293 aprint_error("%s: couldn't map %s channel cmd regs\n", 294 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 295 goto bad; 296 } 297 298 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel), 299 PCI_MAPREG_TYPE_IO, 0, 300 &wdr->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 301 aprint_error("%s: couldn't map %s channel ctl regs\n", 302 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 303 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 304 *cmdsizep); 305 goto bad; 306 } 307 /* 308 * In native mode, 4 bytes of I/O space are mapped for the control 309 * register, the control register is at offset 2. Pass the generic 310 * code a handle for only one byte at the right offset. 311 */ 312 if (bus_space_subregion(wdr->ctl_iot, cp->ctl_baseioh, 2, 1, 313 &wdr->ctl_ioh) != 0) { 314 aprint_error("%s: unable to subregion %s channel ctl regs\n", 315 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 316 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 317 *cmdsizep); 318 bus_space_unmap(wdr->cmd_iot, cp->ctl_baseioh, *ctlsizep); 319 goto bad; 320 } 321 322 for (i = 0; i < WDC_NREG; i++) { 323 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 324 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 325 aprint_error("%s: couldn't subregion %s channel " 326 "cmd regs\n", 327 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 328 goto bad; 329 } 330 } 331 wdc_init_shadow_regs(wdc_cp); 332 wdr->data32iot = wdr->cmd_iot; 333 wdr->data32ioh = wdr->cmd_iohs[0]; 334 return; 335 336 bad: 337 cp->ata_channel.ch_flags |= ATACH_DISABLED; 338 return; 339 } 340 341 void 342 pciide_mapreg_dma(sc, pa) 343 struct pciide_softc *sc; 344 struct pci_attach_args *pa; 345 { 346 pcireg_t maptype; 347 bus_addr_t addr; 348 struct pciide_channel *pc; 349 int reg, chan; 350 bus_size_t size; 351 352 /* 353 * Map DMA registers 354 * 355 * Note that sc_dma_ok is the right variable to test to see if 356 * DMA can be done. If the interface doesn't support DMA, 357 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 358 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 359 * non-zero if the interface supports DMA and the registers 360 * could be mapped. 361 * 362 * XXX Note that despite the fact that the Bus Master IDE specs 363 * XXX say that "The bus master IDE function uses 16 bytes of IO 364 * XXX space," some controllers (at least the United 365 * XXX Microelectronics UM8886BF) place it in memory space. 366 */ 367 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 368 PCIIDE_REG_BUS_MASTER_DMA); 369 370 switch (maptype) { 371 case PCI_MAPREG_TYPE_IO: 372 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 373 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 374 &addr, NULL, NULL) == 0); 375 if (sc->sc_dma_ok == 0) { 376 aprint_normal( 377 ", but unused (couldn't query registers)"); 378 break; 379 } 380 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 381 && addr >= 0x10000) { 382 sc->sc_dma_ok = 0; 383 aprint_normal( 384 ", but unused (registers at unsafe address " 385 "%#lx)", (unsigned long)addr); 386 break; 387 } 388 /* FALLTHROUGH */ 389 390 case PCI_MAPREG_MEM_TYPE_32BIT: 391 sc->sc_dma_ok = (pci_mapreg_map(pa, 392 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 393 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 394 sc->sc_dmat = pa->pa_dmat; 395 if (sc->sc_dma_ok == 0) { 396 aprint_normal(", but unused (couldn't map registers)"); 397 } else { 398 sc->sc_wdcdev.dma_arg = sc; 399 sc->sc_wdcdev.dma_init = pciide_dma_init; 400 sc->sc_wdcdev.dma_start = pciide_dma_start; 401 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 402 } 403 404 if (sc->sc_wdcdev.sc_atac.atac_dev.dv_cfdata->cf_flags & 405 PCIIDE_OPTIONS_NODMA) { 406 aprint_normal( 407 ", but unused (forced off by config file)"); 408 sc->sc_dma_ok = 0; 409 } 410 break; 411 412 default: 413 sc->sc_dma_ok = 0; 414 aprint_normal( 415 ", but unsupported register maptype (0x%x)", maptype); 416 } 417 418 if (sc->sc_dma_ok == 0) 419 return; 420 421 /* 422 * Set up the default handles for the DMA registers. 423 * Just reserve 32 bits for each handle, unless space 424 * doesn't permit it. 425 */ 426 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { 427 pc = &sc->pciide_channels[chan]; 428 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 429 size = 4; 430 if (size > (IDEDMA_SCH_OFFSET - reg)) 431 size = IDEDMA_SCH_OFFSET - reg; 432 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 433 IDEDMA_SCH_OFFSET * chan + reg, size, 434 &pc->dma_iohs[reg]) != 0) { 435 sc->sc_dma_ok = 0; 436 aprint_normal(", but can't subregion offset %d " 437 "size %lu", reg, (u_long)size); 438 return; 439 } 440 } 441 } 442 } 443 444 int 445 pciide_compat_intr(arg) 446 void *arg; 447 { 448 struct pciide_channel *cp = arg; 449 450 #ifdef DIAGNOSTIC 451 /* should only be called for a compat channel */ 452 if (cp->compat == 0) 453 panic("pciide compat intr called for non-compat chan %p", cp); 454 #endif 455 return (wdcintr(&cp->ata_channel)); 456 } 457 458 int 459 pciide_pci_intr(arg) 460 void *arg; 461 { 462 struct pciide_softc *sc = arg; 463 struct pciide_channel *cp; 464 struct ata_channel *wdc_cp; 465 int i, rv, crv; 466 467 rv = 0; 468 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 469 cp = &sc->pciide_channels[i]; 470 wdc_cp = &cp->ata_channel; 471 472 /* If a compat channel skip. */ 473 if (cp->compat) 474 continue; 475 /* if this channel not waiting for intr, skip */ 476 if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0) 477 continue; 478 479 crv = wdcintr(wdc_cp); 480 if (crv == 0) 481 ; /* leave rv alone */ 482 else if (crv == 1) 483 rv = 1; /* claim the intr */ 484 else if (rv == 0) /* crv should be -1 in this case */ 485 rv = crv; /* if we've done no better, take it */ 486 } 487 return (rv); 488 } 489 490 void 491 pciide_channel_dma_setup(cp) 492 struct pciide_channel *cp; 493 { 494 int drive; 495 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 496 struct ata_drive_datas *drvp; 497 498 KASSERT(cp->ata_channel.ch_ndrive != 0); 499 500 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 501 drvp = &cp->ata_channel.ch_drive[drive]; 502 /* If no drive, skip */ 503 if ((drvp->drive_flags & DRIVE) == 0) 504 continue; 505 /* setup DMA if needed */ 506 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 507 (drvp->drive_flags & DRIVE_UDMA) == 0) || 508 sc->sc_dma_ok == 0) { 509 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 510 continue; 511 } 512 if (pciide_dma_table_setup(sc, cp->ata_channel.ch_channel, 513 drive) != 0) { 514 /* Abort DMA setup */ 515 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 516 continue; 517 } 518 } 519 } 520 521 int 522 pciide_dma_table_setup(sc, channel, drive) 523 struct pciide_softc *sc; 524 int channel, drive; 525 { 526 bus_dma_segment_t seg; 527 int error, rseg; 528 const bus_size_t dma_table_size = 529 sizeof(struct idedma_table) * NIDEDMA_TABLES; 530 struct pciide_dma_maps *dma_maps = 531 &sc->pciide_channels[channel].dma_maps[drive]; 532 533 /* If table was already allocated, just return */ 534 if (dma_maps->dma_table) 535 return 0; 536 537 /* Allocate memory for the DMA tables and map it */ 538 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 539 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 540 BUS_DMA_NOWAIT)) != 0) { 541 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 542 channel, "allocate", drive, error); 543 return error; 544 } 545 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 546 dma_table_size, 547 (caddr_t *)&dma_maps->dma_table, 548 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 549 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 550 channel, "map", drive, error); 551 return error; 552 } 553 ATADEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 554 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 555 (unsigned long)seg.ds_addr), DEBUG_PROBE); 556 /* Create and load table DMA map for this disk */ 557 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 558 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 559 &dma_maps->dmamap_table)) != 0) { 560 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 561 channel, "create", drive, error); 562 return error; 563 } 564 if ((error = bus_dmamap_load(sc->sc_dmat, 565 dma_maps->dmamap_table, 566 dma_maps->dma_table, 567 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 568 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 569 channel, "load", drive, error); 570 return error; 571 } 572 ATADEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 573 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 574 DEBUG_PROBE); 575 /* Create a xfer DMA map for this drive */ 576 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 577 NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 578 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 579 &dma_maps->dmamap_xfer)) != 0) { 580 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 581 channel, "create xfer", drive, error); 582 return error; 583 } 584 return 0; 585 } 586 587 int 588 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 589 void *v; 590 int channel, drive; 591 void *databuf; 592 size_t datalen; 593 int flags; 594 { 595 struct pciide_softc *sc = v; 596 int error, seg; 597 struct pciide_channel *cp = &sc->pciide_channels[channel]; 598 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 599 600 error = bus_dmamap_load(sc->sc_dmat, 601 dma_maps->dmamap_xfer, 602 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 603 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 604 if (error) { 605 printf(dmaerrfmt, sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 606 channel, "load xfer", drive, error); 607 return error; 608 } 609 610 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 611 dma_maps->dmamap_xfer->dm_mapsize, 612 (flags & WDC_DMA_READ) ? 613 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 614 615 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 616 #ifdef DIAGNOSTIC 617 /* A segment must not cross a 64k boundary */ 618 { 619 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 620 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 621 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 622 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 623 printf("pciide_dma: segment %d physical addr 0x%lx" 624 " len 0x%lx not properly aligned\n", 625 seg, phys, len); 626 panic("pciide_dma: buf align"); 627 } 628 } 629 #endif 630 dma_maps->dma_table[seg].base_addr = 631 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 632 dma_maps->dma_table[seg].byte_count = 633 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 634 IDEDMA_BYTE_COUNT_MASK); 635 ATADEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 636 seg, le32toh(dma_maps->dma_table[seg].byte_count), 637 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 638 639 } 640 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 641 htole32(IDEDMA_BYTE_COUNT_EOT); 642 643 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 644 dma_maps->dmamap_table->dm_mapsize, 645 BUS_DMASYNC_PREWRITE); 646 647 /* Maps are ready. Start DMA function */ 648 #ifdef DIAGNOSTIC 649 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 650 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 651 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 652 panic("pciide_dma_init: table align"); 653 } 654 #endif 655 656 /* Clear status bits */ 657 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 658 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 659 /* Write table addr */ 660 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 661 dma_maps->dmamap_table->dm_segs[0].ds_addr); 662 /* set read/write */ 663 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 664 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 665 /* remember flags */ 666 dma_maps->dma_flags = flags; 667 return 0; 668 } 669 670 void 671 pciide_dma_start(v, channel, drive) 672 void *v; 673 int channel, drive; 674 { 675 struct pciide_softc *sc = v; 676 struct pciide_channel *cp = &sc->pciide_channels[channel]; 677 678 ATADEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 679 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 680 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 681 | IDEDMA_CMD_START); 682 } 683 684 int 685 pciide_dma_finish(v, channel, drive, force) 686 void *v; 687 int channel, drive; 688 int force; 689 { 690 struct pciide_softc *sc = v; 691 u_int8_t status; 692 int error = 0; 693 struct pciide_channel *cp = &sc->pciide_channels[channel]; 694 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 695 696 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0); 697 ATADEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 698 DEBUG_XFERS); 699 700 if (force == WDC_DMAEND_END && (status & IDEDMA_CTL_INTR) == 0) 701 return WDC_DMAST_NOIRQ; 702 703 /* stop DMA channel */ 704 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 705 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 706 & ~IDEDMA_CMD_START); 707 708 /* Unload the map of the data buffer */ 709 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 710 dma_maps->dmamap_xfer->dm_mapsize, 711 (dma_maps->dma_flags & WDC_DMA_READ) ? 712 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 713 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 714 715 if ((status & IDEDMA_CTL_ERR) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 716 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 717 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, channel, drive, 718 status); 719 error |= WDC_DMAST_ERR; 720 } 721 722 if ((status & IDEDMA_CTL_INTR) == 0 && force != WDC_DMAEND_ABRT_QUIET) { 723 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 724 "status=0x%x\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 725 channel, drive, status); 726 error |= WDC_DMAST_NOIRQ; 727 } 728 729 if ((status & IDEDMA_CTL_ACT) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 730 /* data underrun, may be a valid condition for ATAPI */ 731 error |= WDC_DMAST_UNDER; 732 } 733 return error; 734 } 735 736 void 737 pciide_irqack(chp) 738 struct ata_channel *chp; 739 { 740 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 741 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 742 743 /* clear status bits in IDE DMA registers */ 744 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 745 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 746 } 747 748 /* some common code used by several chip_map */ 749 int 750 pciide_chansetup(sc, channel, interface) 751 struct pciide_softc *sc; 752 int channel; 753 pcireg_t interface; 754 { 755 struct pciide_channel *cp = &sc->pciide_channels[channel]; 756 sc->wdc_chanarray[channel] = &cp->ata_channel; 757 cp->name = PCIIDE_CHANNEL_NAME(channel); 758 cp->ata_channel.ch_channel = channel; 759 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 760 cp->ata_channel.ch_queue = 761 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 762 if (cp->ata_channel.ch_queue == NULL) { 763 aprint_error("%s %s channel: " 764 "can't allocate memory for command queue", 765 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 766 return 0; 767 } 768 aprint_normal("%s: %s channel %s to %s mode\n", 769 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name, 770 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 771 "configured" : "wired", 772 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 773 "native-PCI" : "compatibility"); 774 return 1; 775 } 776 777 /* some common code used by several chip channel_map */ 778 void 779 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 780 struct pci_attach_args *pa; 781 struct pciide_channel *cp; 782 pcireg_t interface; 783 bus_size_t *cmdsizep, *ctlsizep; 784 int (*pci_intr) __P((void *)); 785 { 786 struct ata_channel *wdc_cp = &cp->ata_channel; 787 788 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) 789 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr); 790 else { 791 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep, 792 ctlsizep); 793 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 794 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 795 } 796 wdcattach(wdc_cp); 797 } 798 799 /* 800 * generic code to map the compat intr. 801 */ 802 void 803 pciide_map_compat_intr(pa, cp, compatchan) 804 struct pci_attach_args *pa; 805 struct pciide_channel *cp; 806 int compatchan; 807 { 808 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 809 810 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 811 cp->ih = 812 pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_atac.atac_dev, 813 pa, compatchan, pciide_compat_intr, cp); 814 if (cp->ih == NULL) { 815 #endif 816 aprint_error("%s: no compatibility interrupt for use by %s " 817 "channel\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 818 cp->name); 819 cp->ata_channel.ch_flags |= ATACH_DISABLED; 820 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 821 } 822 #endif 823 } 824 825 void 826 default_chip_map(sc, pa) 827 struct pciide_softc *sc; 828 struct pci_attach_args *pa; 829 { 830 struct pciide_channel *cp; 831 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 832 pcireg_t csr; 833 int channel, drive; 834 struct ata_drive_datas *drvp; 835 u_int8_t idedma_ctl; 836 bus_size_t cmdsize, ctlsize; 837 char *failreason; 838 struct wdc_regs *wdr; 839 840 if (pciide_chipen(sc, pa) == 0) 841 return; 842 843 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 844 aprint_normal("%s: bus-master DMA support present", 845 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 846 if (sc->sc_pp == &default_product_desc && 847 (sc->sc_wdcdev.sc_atac.atac_dev.dv_cfdata->cf_flags & 848 PCIIDE_OPTIONS_DMA) == 0) { 849 aprint_normal(", but unused (no driver support)"); 850 sc->sc_dma_ok = 0; 851 } else { 852 pciide_mapreg_dma(sc, pa); 853 if (sc->sc_dma_ok != 0) 854 aprint_normal(", used without full driver " 855 "support"); 856 } 857 } else { 858 aprint_normal("%s: hardware does not support DMA", 859 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 860 sc->sc_dma_ok = 0; 861 } 862 aprint_normal("\n"); 863 if (sc->sc_dma_ok) { 864 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 865 sc->sc_wdcdev.irqack = pciide_irqack; 866 } 867 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 868 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 869 870 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 871 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 872 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 873 874 wdc_allocate_regs(&sc->sc_wdcdev); 875 876 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 877 channel++) { 878 cp = &sc->pciide_channels[channel]; 879 if (pciide_chansetup(sc, channel, interface) == 0) 880 continue; 881 wdr = CHAN_TO_WDC_REGS(&cp->ata_channel); 882 if (interface & PCIIDE_INTERFACE_PCI(channel)) 883 pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 884 pciide_pci_intr); 885 else 886 pciide_mapregs_compat(pa, cp, 887 cp->ata_channel.ch_channel, &cmdsize, &ctlsize); 888 if (cp->ata_channel.ch_flags & ATACH_DISABLED) 889 continue; 890 /* 891 * Check to see if something appears to be there. 892 */ 893 failreason = NULL; 894 /* 895 * In native mode, always enable the controller. It's 896 * not possible to have an ISA board using the same address 897 * anyway. 898 */ 899 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 900 wdcattach(&cp->ata_channel); 901 continue; 902 } 903 if (!wdcprobe(&cp->ata_channel)) { 904 failreason = "not responding; disabled or no drives?"; 905 goto next; 906 } 907 /* 908 * Now, make sure it's actually attributable to this PCI IDE 909 * channel by trying to access the channel again while the 910 * PCI IDE controller's I/O space is disabled. (If the 911 * channel no longer appears to be there, it belongs to 912 * this controller.) YUCK! 913 */ 914 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 915 PCI_COMMAND_STATUS_REG); 916 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 917 csr & ~PCI_COMMAND_IO_ENABLE); 918 if (wdcprobe(&cp->ata_channel)) 919 failreason = "other hardware responding at addresses"; 920 pci_conf_write(sc->sc_pc, sc->sc_tag, 921 PCI_COMMAND_STATUS_REG, csr); 922 next: 923 if (failreason) { 924 aprint_error("%s: %s channel ignored (%s)\n", 925 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name, 926 failreason); 927 cp->ata_channel.ch_flags |= ATACH_DISABLED; 928 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 929 cmdsize); 930 bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh, ctlsize); 931 } else { 932 pciide_map_compat_intr(pa, cp, 933 cp->ata_channel.ch_channel); 934 wdcattach(&cp->ata_channel); 935 } 936 } 937 938 if (sc->sc_dma_ok == 0) 939 return; 940 941 /* Allocate DMA maps */ 942 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 943 channel++) { 944 idedma_ctl = 0; 945 cp = &sc->pciide_channels[channel]; 946 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 947 drvp = &cp->ata_channel.ch_drive[drive]; 948 /* If no drive, skip */ 949 if ((drvp->drive_flags & DRIVE) == 0) 950 continue; 951 if ((drvp->drive_flags & DRIVE_DMA) == 0) 952 continue; 953 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 954 /* Abort DMA setup */ 955 aprint_error( 956 "%s:%d:%d: can't allocate DMA maps, " 957 "using PIO transfers\n", 958 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 959 channel, drive); 960 drvp->drive_flags &= ~DRIVE_DMA; 961 } 962 aprint_normal("%s:%d:%d: using DMA data transfers\n", 963 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 964 channel, drive); 965 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 966 } 967 if (idedma_ctl != 0) { 968 /* Add software bits in status register */ 969 bus_space_write_1(sc->sc_dma_iot, 970 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 971 } 972 } 973 } 974 975 void 976 sata_setup_channel(chp) 977 struct ata_channel *chp; 978 { 979 struct ata_drive_datas *drvp; 980 int drive; 981 u_int32_t idedma_ctl; 982 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 983 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 984 985 /* setup DMA if needed */ 986 pciide_channel_dma_setup(cp); 987 988 idedma_ctl = 0; 989 990 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 991 drvp = &chp->ch_drive[drive]; 992 /* If no drive, skip */ 993 if ((drvp->drive_flags & DRIVE) == 0) 994 continue; 995 if (drvp->drive_flags & DRIVE_UDMA) { 996 /* use Ultra/DMA */ 997 drvp->drive_flags &= ~DRIVE_DMA; 998 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 999 } else if (drvp->drive_flags & DRIVE_DMA) { 1000 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1001 } 1002 } 1003 1004 /* 1005 * Nothing to do to setup modes; it is meaningless in S-ATA 1006 * (but many S-ATA drives still want to get the SET_FEATURE 1007 * command). 1008 */ 1009 if (idedma_ctl != 0) { 1010 /* Add software bits in status register */ 1011 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 1012 idedma_ctl); 1013 } 1014 } 1015
Indexes created Thu Oct 02 07:10:07 GMT 2025