pciide_common.c revision 1.3
1 /* $NetBSD: pciide_common.c,v 1.3 2003/11/27 23:02:40 fvdl Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.3 2003/11/27 23:02:40 fvdl Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/malloc.h> 83 84 #include <uvm/uvm_extern.h> 85 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pcidevs.h> 89 #include <dev/pci/pciidereg.h> 90 #include <dev/pci/pciidevar.h> 91 92 #include <dev/ic/wdcreg.h> 93 94 #ifdef WDCDEBUG 95 int wdcdebug_pciide_mask = 0; 96 #endif 97 98 static const char dmaerrfmt[] = 99 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 100 101 102 103 /* options passed via the 'flags' config keyword */ 104 #define PCIIDE_OPTIONS_DMA 0x01 105 #define PCIIDE_OPTIONS_NODMA 0x02 106 107 /* Default product description for devices not known from this controller */ 108 const struct pciide_product_desc default_product_desc = { 109 0, 110 0, 111 "Generic PCI IDE controller", 112 default_chip_map, 113 }; 114 115 const struct pciide_product_desc * 116 pciide_lookup_product(id, pp) 117 pcireg_t id; 118 const struct pciide_product_desc *pp; 119 { 120 for (; pp->chip_map != NULL; pp++) 121 if (PCI_PRODUCT(id) == pp->ide_product) 122 break; 123 124 if (pp->chip_map == NULL) 125 return NULL; 126 return pp; 127 } 128 129 void 130 pciide_common_attach(sc, pa, pp) 131 struct pciide_softc *sc; 132 struct pci_attach_args *pa; 133 const struct pciide_product_desc *pp; 134 { 135 pci_chipset_tag_t pc = pa->pa_pc; 136 pcitag_t tag = pa->pa_tag; 137 pcireg_t csr; 138 char devinfo[256]; 139 const char *displaydev; 140 141 aprint_naive(": disk controller\n"); 142 aprint_normal("\n"); 143 144 sc->sc_pci_id = pa->pa_id; 145 if (pp == NULL) { 146 /* should only happen for generic pciide devices */ 147 sc->sc_pp = &default_product_desc; 148 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo); 149 displaydev = devinfo; 150 } else { 151 sc->sc_pp = pp; 152 displaydev = sc->sc_pp->ide_name; 153 } 154 155 /* if displaydev == NULL, printf is done in chip-specific map */ 156 if (displaydev) 157 aprint_normal("%s: %s (rev. 0x%02x)\n", 158 sc->sc_wdcdev.sc_dev.dv_xname, displaydev, 159 PCI_REVISION(pa->pa_class)); 160 161 sc->sc_pc = pa->pa_pc; 162 sc->sc_tag = pa->pa_tag; 163 164 /* Set up DMA defaults; these might be adjusted by chip_map. */ 165 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 166 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 167 168 #ifdef WDCDEBUG 169 if (wdcdebug_pciide_mask & DEBUG_PROBE) 170 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 171 #endif 172 sc->sc_pp->chip_map(sc, pa); 173 174 if (sc->sc_dma_ok) { 175 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 176 csr |= PCI_COMMAND_MASTER_ENABLE; 177 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 178 } 179 WDCDEBUG_PRINT(("pciide: command/status register=%x\n", 180 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 181 } 182 183 /* tell whether the chip is enabled or not */ 184 int 185 pciide_chipen(sc, pa) 186 struct pciide_softc *sc; 187 struct pci_attach_args *pa; 188 { 189 pcireg_t csr; 190 191 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 192 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 193 PCI_COMMAND_STATUS_REG); 194 aprint_normal("%s: device disabled (at %s)\n", 195 sc->sc_wdcdev.sc_dev.dv_xname, 196 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 197 "device" : "bridge"); 198 return 0; 199 } 200 return 1; 201 } 202 203 void 204 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 205 struct pci_attach_args *pa; 206 struct pciide_channel *cp; 207 int compatchan; 208 bus_size_t *cmdsizep, *ctlsizep; 209 { 210 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 211 struct channel_softc *wdc_cp = &cp->wdc_channel; 212 int i; 213 214 cp->compat = 1; 215 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 216 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 217 218 wdc_cp->cmd_iot = pa->pa_iot; 219 if (bus_space_map(wdc_cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 220 PCIIDE_COMPAT_CMD_SIZE, 0, &wdc_cp->cmd_baseioh) != 0) { 221 aprint_error("%s: couldn't map %s channel cmd regs\n", 222 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 223 goto bad; 224 } 225 226 wdc_cp->ctl_iot = pa->pa_iot; 227 if (bus_space_map(wdc_cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 228 PCIIDE_COMPAT_CTL_SIZE, 0, &wdc_cp->ctl_ioh) != 0) { 229 aprint_error("%s: couldn't map %s channel ctl regs\n", 230 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 231 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 232 PCIIDE_COMPAT_CMD_SIZE); 233 goto bad; 234 } 235 236 for (i = 0; i < WDC_NREG; i++) { 237 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, i, 238 i == 0 ? 4 : 1, &wdc_cp->cmd_iohs[i]) != 0) { 239 aprint_error("%s: couldn't subregion %s channel " 240 "cmd regs\n", 241 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 242 goto bad; 243 } 244 } 245 wdc_cp->data32iot = wdc_cp->cmd_iot; 246 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 247 pciide_map_compat_intr(pa, cp, compatchan); 248 return; 249 250 bad: 251 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 252 return; 253 } 254 255 void 256 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 257 struct pci_attach_args * pa; 258 struct pciide_channel *cp; 259 bus_size_t *cmdsizep, *ctlsizep; 260 int (*pci_intr) __P((void *)); 261 { 262 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 263 struct channel_softc *wdc_cp = &cp->wdc_channel; 264 const char *intrstr; 265 pci_intr_handle_t intrhandle; 266 int i; 267 268 cp->compat = 0; 269 270 if (sc->sc_pci_ih == NULL) { 271 if (pci_intr_map(pa, &intrhandle) != 0) { 272 aprint_error("%s: couldn't map native-PCI interrupt\n", 273 sc->sc_wdcdev.sc_dev.dv_xname); 274 goto bad; 275 } 276 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 277 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 278 intrhandle, IPL_BIO, pci_intr, sc); 279 if (sc->sc_pci_ih != NULL) { 280 aprint_normal("%s: using %s for native-PCI interrupt\n", 281 sc->sc_wdcdev.sc_dev.dv_xname, 282 intrstr ? intrstr : "unknown interrupt"); 283 } else { 284 aprint_error( 285 "%s: couldn't establish native-PCI interrupt", 286 sc->sc_wdcdev.sc_dev.dv_xname); 287 if (intrstr != NULL) 288 aprint_normal(" at %s", intrstr); 289 aprint_normal("\n"); 290 goto bad; 291 } 292 } 293 cp->ih = sc->sc_pci_ih; 294 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->channel), 295 PCI_MAPREG_TYPE_IO, 0, 296 &wdc_cp->cmd_iot, &wdc_cp->cmd_baseioh, NULL, cmdsizep) != 0) { 297 aprint_error("%s: couldn't map %s channel cmd regs\n", 298 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 299 goto bad; 300 } 301 302 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->channel), 303 PCI_MAPREG_TYPE_IO, 0, 304 &wdc_cp->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 305 aprint_error("%s: couldn't map %s channel ctl regs\n", 306 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 307 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 308 *cmdsizep); 309 goto bad; 310 } 311 /* 312 * In native mode, 4 bytes of I/O space are mapped for the control 313 * register, the control register is at offset 2. Pass the generic 314 * code a handle for only one byte at the right offset. 315 */ 316 if (bus_space_subregion(wdc_cp->ctl_iot, cp->ctl_baseioh, 2, 1, 317 &wdc_cp->ctl_ioh) != 0) { 318 aprint_error("%s: unable to subregion %s channel ctl regs\n", 319 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 320 bus_space_unmap(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 321 *cmdsizep); 322 bus_space_unmap(wdc_cp->cmd_iot, cp->ctl_baseioh, *ctlsizep); 323 goto bad; 324 } 325 326 for (i = 0; i < WDC_NREG; i++) { 327 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, i, 328 i == 0 ? 4 : 1, &wdc_cp->cmd_iohs[i]) != 0) { 329 aprint_error("%s: couldn't subregion %s channel " 330 "cmd regs\n", 331 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 332 goto bad; 333 } 334 } 335 wdc_cp->data32iot = wdc_cp->cmd_iot; 336 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 337 return; 338 339 bad: 340 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 341 return; 342 } 343 344 void 345 pciide_mapreg_dma(sc, pa) 346 struct pciide_softc *sc; 347 struct pci_attach_args *pa; 348 { 349 pcireg_t maptype; 350 bus_addr_t addr; 351 struct pciide_channel *pc; 352 int reg, chan; 353 bus_size_t size; 354 355 /* 356 * Map DMA registers 357 * 358 * Note that sc_dma_ok is the right variable to test to see if 359 * DMA can be done. If the interface doesn't support DMA, 360 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 361 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 362 * non-zero if the interface supports DMA and the registers 363 * could be mapped. 364 * 365 * XXX Note that despite the fact that the Bus Master IDE specs 366 * XXX say that "The bus master IDE function uses 16 bytes of IO 367 * XXX space," some controllers (at least the United 368 * XXX Microelectronics UM8886BF) place it in memory space. 369 */ 370 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 371 PCIIDE_REG_BUS_MASTER_DMA); 372 373 switch (maptype) { 374 case PCI_MAPREG_TYPE_IO: 375 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 376 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 377 &addr, NULL, NULL) == 0); 378 if (sc->sc_dma_ok == 0) { 379 aprint_normal( 380 ", but unused (couldn't query registers)"); 381 break; 382 } 383 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 384 && addr >= 0x10000) { 385 sc->sc_dma_ok = 0; 386 aprint_normal( 387 ", but unused (registers at unsafe address " 388 "%#lx)", (unsigned long)addr); 389 break; 390 } 391 /* FALLTHROUGH */ 392 393 case PCI_MAPREG_MEM_TYPE_32BIT: 394 sc->sc_dma_ok = (pci_mapreg_map(pa, 395 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 396 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 397 sc->sc_dmat = pa->pa_dmat; 398 if (sc->sc_dma_ok == 0) { 399 aprint_normal(", but unused (couldn't map registers)"); 400 } else { 401 sc->sc_wdcdev.dma_arg = sc; 402 sc->sc_wdcdev.dma_init = pciide_dma_init; 403 sc->sc_wdcdev.dma_start = pciide_dma_start; 404 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 405 } 406 407 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 408 PCIIDE_OPTIONS_NODMA) { 409 aprint_normal( 410 ", but unused (forced off by config file)"); 411 sc->sc_dma_ok = 0; 412 } 413 break; 414 415 default: 416 sc->sc_dma_ok = 0; 417 aprint_normal( 418 ", but unsupported register maptype (0x%x)", maptype); 419 } 420 421 /* 422 * Set up the default handles for the DMA registers. 423 * Just reserve 32 bits for each handle, unless space 424 * doesn't permit it. 425 */ 426 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { 427 pc = &sc->pciide_channels[chan]; 428 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 429 size = 4; 430 if (size > (IDEDMA_SCH_OFFSET - reg)) 431 size = IDEDMA_SCH_OFFSET - reg; 432 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 433 IDEDMA_SCH_OFFSET * chan + reg, size, 434 &pc->dma_iohs[reg]) != 0) { 435 sc->sc_dma_ok = 0; 436 aprint_normal(", but can't subregion offset %d " 437 "size %lu", reg, (u_long)size); 438 return; 439 } 440 } 441 } 442 } 443 444 int 445 pciide_compat_intr(arg) 446 void *arg; 447 { 448 struct pciide_channel *cp = arg; 449 450 #ifdef DIAGNOSTIC 451 /* should only be called for a compat channel */ 452 if (cp->compat == 0) 453 panic("pciide compat intr called for non-compat chan %p", cp); 454 #endif 455 return (wdcintr(&cp->wdc_channel)); 456 } 457 458 int 459 pciide_pci_intr(arg) 460 void *arg; 461 { 462 struct pciide_softc *sc = arg; 463 struct pciide_channel *cp; 464 struct channel_softc *wdc_cp; 465 int i, rv, crv; 466 467 rv = 0; 468 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 469 cp = &sc->pciide_channels[i]; 470 wdc_cp = &cp->wdc_channel; 471 472 /* If a compat channel skip. */ 473 if (cp->compat) 474 continue; 475 /* if this channel not waiting for intr, skip */ 476 if ((wdc_cp->ch_flags & WDCF_IRQ_WAIT) == 0) 477 continue; 478 479 crv = wdcintr(wdc_cp); 480 if (crv == 0) 481 ; /* leave rv alone */ 482 else if (crv == 1) 483 rv = 1; /* claim the intr */ 484 else if (rv == 0) /* crv should be -1 in this case */ 485 rv = crv; /* if we've done no better, take it */ 486 } 487 return (rv); 488 } 489 490 void 491 pciide_channel_dma_setup(cp) 492 struct pciide_channel *cp; 493 { 494 int drive; 495 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 496 struct ata_drive_datas *drvp; 497 498 for (drive = 0; drive < 2; drive++) { 499 drvp = &cp->wdc_channel.ch_drive[drive]; 500 /* If no drive, skip */ 501 if ((drvp->drive_flags & DRIVE) == 0) 502 continue; 503 /* setup DMA if needed */ 504 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 505 (drvp->drive_flags & DRIVE_UDMA) == 0) || 506 sc->sc_dma_ok == 0) { 507 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 508 continue; 509 } 510 if (pciide_dma_table_setup(sc, cp->wdc_channel.channel, drive) 511 != 0) { 512 /* Abort DMA setup */ 513 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 514 continue; 515 } 516 } 517 } 518 519 int 520 pciide_dma_table_setup(sc, channel, drive) 521 struct pciide_softc *sc; 522 int channel, drive; 523 { 524 bus_dma_segment_t seg; 525 int error, rseg; 526 const bus_size_t dma_table_size = 527 sizeof(struct idedma_table) * NIDEDMA_TABLES; 528 struct pciide_dma_maps *dma_maps = 529 &sc->pciide_channels[channel].dma_maps[drive]; 530 531 /* If table was already allocated, just return */ 532 if (dma_maps->dma_table) 533 return 0; 534 535 /* Allocate memory for the DMA tables and map it */ 536 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 537 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 538 BUS_DMA_NOWAIT)) != 0) { 539 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 540 "allocate", drive, error); 541 return error; 542 } 543 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 544 dma_table_size, 545 (caddr_t *)&dma_maps->dma_table, 546 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 547 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 548 "map", drive, error); 549 return error; 550 } 551 WDCDEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 552 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 553 (unsigned long)seg.ds_addr), DEBUG_PROBE); 554 /* Create and load table DMA map for this disk */ 555 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 556 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 557 &dma_maps->dmamap_table)) != 0) { 558 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 559 "create", drive, error); 560 return error; 561 } 562 if ((error = bus_dmamap_load(sc->sc_dmat, 563 dma_maps->dmamap_table, 564 dma_maps->dma_table, 565 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 566 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 567 "load", drive, error); 568 return error; 569 } 570 WDCDEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 571 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 572 DEBUG_PROBE); 573 /* Create a xfer DMA map for this drive */ 574 if ((error = bus_dmamap_create(sc->sc_dmat, IDEDMA_BYTE_COUNT_MAX, 575 NIDEDMA_TABLES, sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 576 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 577 &dma_maps->dmamap_xfer)) != 0) { 578 aprint_error(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 579 "create xfer", drive, error); 580 return error; 581 } 582 return 0; 583 } 584 585 int 586 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 587 void *v; 588 int channel, drive; 589 void *databuf; 590 size_t datalen; 591 int flags; 592 { 593 struct pciide_softc *sc = v; 594 int error, seg; 595 struct pciide_channel *cp = &sc->pciide_channels[channel]; 596 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 597 598 error = bus_dmamap_load(sc->sc_dmat, 599 dma_maps->dmamap_xfer, 600 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 601 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 602 if (error) { 603 printf(dmaerrfmt, sc->sc_wdcdev.sc_dev.dv_xname, channel, 604 "load xfer", drive, error); 605 return error; 606 } 607 608 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 609 dma_maps->dmamap_xfer->dm_mapsize, 610 (flags & WDC_DMA_READ) ? 611 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 612 613 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 614 #ifdef DIAGNOSTIC 615 /* A segment must not cross a 64k boundary */ 616 { 617 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 618 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 619 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 620 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 621 printf("pciide_dma: segment %d physical addr 0x%lx" 622 " len 0x%lx not properly aligned\n", 623 seg, phys, len); 624 panic("pciide_dma: buf align"); 625 } 626 } 627 #endif 628 dma_maps->dma_table[seg].base_addr = 629 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 630 dma_maps->dma_table[seg].byte_count = 631 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 632 IDEDMA_BYTE_COUNT_MASK); 633 WDCDEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 634 seg, le32toh(dma_maps->dma_table[seg].byte_count), 635 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 636 637 } 638 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 639 htole32(IDEDMA_BYTE_COUNT_EOT); 640 641 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 642 dma_maps->dmamap_table->dm_mapsize, 643 BUS_DMASYNC_PREWRITE); 644 645 /* Maps are ready. Start DMA function */ 646 #ifdef DIAGNOSTIC 647 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 648 printf("pciide_dma_init: addr 0x%lx not properly aligned\n", 649 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 650 panic("pciide_dma_init: table align"); 651 } 652 #endif 653 654 /* Clear status bits */ 655 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 656 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 657 /* Write table addr */ 658 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 659 dma_maps->dmamap_table->dm_segs[0].ds_addr); 660 /* set read/write */ 661 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 662 (flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0); 663 /* remember flags */ 664 dma_maps->dma_flags = flags; 665 return 0; 666 } 667 668 void 669 pciide_dma_start(v, channel, drive) 670 void *v; 671 int channel, drive; 672 { 673 struct pciide_softc *sc = v; 674 struct pciide_channel *cp = &sc->pciide_channels[channel]; 675 676 WDCDEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 677 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 678 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 679 | IDEDMA_CMD_START); 680 } 681 682 int 683 pciide_dma_finish(v, channel, drive, force) 684 void *v; 685 int channel, drive; 686 int force; 687 { 688 struct pciide_softc *sc = v; 689 u_int8_t status; 690 int error = 0; 691 struct pciide_channel *cp = &sc->pciide_channels[channel]; 692 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 693 694 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0); 695 WDCDEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 696 DEBUG_XFERS); 697 698 if (force == 0 && (status & IDEDMA_CTL_INTR) == 0) 699 return WDC_DMAST_NOIRQ; 700 701 /* stop DMA channel */ 702 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 703 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 704 & ~IDEDMA_CMD_START); 705 706 /* Unload the map of the data buffer */ 707 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 708 dma_maps->dmamap_xfer->dm_mapsize, 709 (dma_maps->dma_flags & WDC_DMA_READ) ? 710 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 711 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 712 713 if ((status & IDEDMA_CTL_ERR) != 0) { 714 printf("%s:%d:%d: bus-master DMA error: status=0x%x\n", 715 sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status); 716 error |= WDC_DMAST_ERR; 717 } 718 719 if ((status & IDEDMA_CTL_INTR) == 0) { 720 printf("%s:%d:%d: bus-master DMA error: missing interrupt, " 721 "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel, 722 drive, status); 723 error |= WDC_DMAST_NOIRQ; 724 } 725 726 if ((status & IDEDMA_CTL_ACT) != 0) { 727 /* data underrun, may be a valid condition for ATAPI */ 728 error |= WDC_DMAST_UNDER; 729 } 730 return error; 731 } 732 733 void 734 pciide_irqack(chp) 735 struct channel_softc *chp; 736 { 737 struct pciide_channel *cp = (struct pciide_channel*)chp; 738 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 739 740 /* clear status bits in IDE DMA registers */ 741 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 742 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 743 } 744 745 /* some common code used by several chip_map */ 746 int 747 pciide_chansetup(sc, channel, interface) 748 struct pciide_softc *sc; 749 int channel; 750 pcireg_t interface; 751 { 752 struct pciide_channel *cp = &sc->pciide_channels[channel]; 753 sc->wdc_chanarray[channel] = &cp->wdc_channel; 754 cp->name = PCIIDE_CHANNEL_NAME(channel); 755 cp->wdc_channel.channel = channel; 756 cp->wdc_channel.wdc = &sc->sc_wdcdev; 757 cp->wdc_channel.ch_queue = 758 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 759 if (cp->wdc_channel.ch_queue == NULL) { 760 aprint_error("%s %s channel: " 761 "can't allocate memory for command queue", 762 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 763 return 0; 764 } 765 aprint_normal("%s: %s channel %s to %s mode\n", 766 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 767 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 768 "configured" : "wired", 769 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 770 "native-PCI" : "compatibility"); 771 return 1; 772 } 773 774 /* some common code used by several chip channel_map */ 775 void 776 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 777 struct pci_attach_args *pa; 778 struct pciide_channel *cp; 779 pcireg_t interface; 780 bus_size_t *cmdsizep, *ctlsizep; 781 int (*pci_intr) __P((void *)); 782 { 783 struct channel_softc *wdc_cp = &cp->wdc_channel; 784 785 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->channel)) 786 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr); 787 else 788 pciide_mapregs_compat(pa, cp, wdc_cp->channel, cmdsizep, 789 ctlsizep); 790 wdcattach(wdc_cp); 791 } 792 793 /* 794 * generic code to map the compat intr. 795 */ 796 void 797 pciide_map_compat_intr(pa, cp, compatchan) 798 struct pci_attach_args *pa; 799 struct pciide_channel *cp; 800 int compatchan; 801 { 802 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 803 804 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 805 cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev, 806 pa, compatchan, pciide_compat_intr, cp); 807 if (cp->ih == NULL) { 808 #endif 809 aprint_error("%s: no compatibility interrupt for use by %s " 810 "channel\n", sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 811 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 812 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 813 } 814 #endif 815 } 816 817 void 818 default_chip_map(sc, pa) 819 struct pciide_softc *sc; 820 struct pci_attach_args *pa; 821 { 822 struct pciide_channel *cp; 823 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 824 pcireg_t csr; 825 int channel, drive; 826 struct ata_drive_datas *drvp; 827 u_int8_t idedma_ctl; 828 bus_size_t cmdsize, ctlsize; 829 char *failreason; 830 831 if (pciide_chipen(sc, pa) == 0) 832 return; 833 834 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 835 aprint_normal("%s: bus-master DMA support present", 836 sc->sc_wdcdev.sc_dev.dv_xname); 837 if (sc->sc_pp == &default_product_desc && 838 (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 839 PCIIDE_OPTIONS_DMA) == 0) { 840 aprint_normal(", but unused (no driver support)"); 841 sc->sc_dma_ok = 0; 842 } else { 843 pciide_mapreg_dma(sc, pa); 844 if (sc->sc_dma_ok != 0) 845 aprint_normal(", used without full driver " 846 "support"); 847 } 848 } else { 849 aprint_normal("%s: hardware does not support DMA", 850 sc->sc_wdcdev.sc_dev.dv_xname); 851 sc->sc_dma_ok = 0; 852 } 853 aprint_normal("\n"); 854 if (sc->sc_dma_ok) { 855 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 856 sc->sc_wdcdev.irqack = pciide_irqack; 857 } 858 sc->sc_wdcdev.PIO_cap = 0; 859 sc->sc_wdcdev.DMA_cap = 0; 860 861 sc->sc_wdcdev.channels = sc->wdc_chanarray; 862 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 863 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16; 864 865 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 866 cp = &sc->pciide_channels[channel]; 867 if (pciide_chansetup(sc, channel, interface) == 0) 868 continue; 869 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 870 pciide_pci_intr); 871 if (cp->wdc_channel.ch_flags & WDCF_DISABLED) 872 continue; 873 /* 874 * Check to see if something appears to be there. 875 */ 876 failreason = NULL; 877 /* 878 * In native mode, always enable the controller. It's 879 * not possible to have an ISA board using the same address 880 * anyway. 881 */ 882 if (interface & PCIIDE_INTERFACE_PCI(channel)) 883 goto next; 884 if (!wdcprobe(&cp->wdc_channel)) { 885 failreason = "not responding; disabled or no drives?"; 886 goto next; 887 } 888 /* 889 * Now, make sure it's actually attributable to this PCI IDE 890 * channel by trying to access the channel again while the 891 * PCI IDE controller's I/O space is disabled. (If the 892 * channel no longer appears to be there, it belongs to 893 * this controller.) YUCK! 894 */ 895 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 896 PCI_COMMAND_STATUS_REG); 897 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 898 csr & ~PCI_COMMAND_IO_ENABLE); 899 if (wdcprobe(&cp->wdc_channel)) 900 failreason = "other hardware responding at addresses"; 901 pci_conf_write(sc->sc_pc, sc->sc_tag, 902 PCI_COMMAND_STATUS_REG, csr); 903 next: 904 if (failreason) { 905 aprint_error("%s: %s channel ignored (%s)\n", 906 sc->sc_wdcdev.sc_dev.dv_xname, cp->name, 907 failreason); 908 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 909 bus_space_unmap(cp->wdc_channel.cmd_iot, 910 cp->wdc_channel.cmd_baseioh, cmdsize); 911 bus_space_unmap(cp->wdc_channel.ctl_iot, 912 cp->wdc_channel.ctl_ioh, ctlsize); 913 914 } 915 } 916 917 if (sc->sc_dma_ok == 0) 918 return; 919 920 /* Allocate DMA maps */ 921 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 922 idedma_ctl = 0; 923 cp = &sc->pciide_channels[channel]; 924 for (drive = 0; drive < 2; drive++) { 925 drvp = &cp->wdc_channel.ch_drive[drive]; 926 /* If no drive, skip */ 927 if ((drvp->drive_flags & DRIVE) == 0) 928 continue; 929 if ((drvp->drive_flags & DRIVE_DMA) == 0) 930 continue; 931 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 932 /* Abort DMA setup */ 933 aprint_error( 934 "%s:%d:%d: can't allocate DMA maps, " 935 "using PIO transfers\n", 936 sc->sc_wdcdev.sc_dev.dv_xname, 937 channel, drive); 938 drvp->drive_flags &= ~DRIVE_DMA; 939 } 940 aprint_normal("%s:%d:%d: using DMA data transfers\n", 941 sc->sc_wdcdev.sc_dev.dv_xname, 942 channel, drive); 943 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 944 } 945 if (idedma_ctl != 0) { 946 /* Add software bits in status register */ 947 bus_space_write_1(sc->sc_dma_iot, 948 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 949 } 950 } 951 } 952 953 void 954 sata_setup_channel(chp) 955 struct channel_softc *chp; 956 { 957 struct ata_drive_datas *drvp; 958 int drive; 959 u_int32_t idedma_ctl; 960 struct pciide_channel *cp = (struct pciide_channel*)chp; 961 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 962 963 /* setup DMA if needed */ 964 pciide_channel_dma_setup(cp); 965 966 idedma_ctl = 0; 967 968 for (drive = 0; drive < 2; drive++) { 969 drvp = &chp->ch_drive[drive]; 970 /* If no drive, skip */ 971 if ((drvp->drive_flags & DRIVE) == 0) 972 continue; 973 if (drvp->drive_flags & DRIVE_UDMA) { 974 /* use Ultra/DMA */ 975 drvp->drive_flags &= ~DRIVE_DMA; 976 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 977 } else if (drvp->drive_flags & DRIVE_DMA) { 978 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 979 } 980 } 981 982 /* 983 * Nothing to do to setup modes; it is meaningless in S-ATA 984 * (but many S-ATA drives still want to get the SET_FEATURE 985 * command). 986 */ 987 if (idedma_ctl != 0) { 988 /* Add software bits in status register */ 989 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 990 idedma_ctl); 991 } 992 } 993
Indexes created Thu Oct 02 07:10:07 GMT 2025