pciide_common.c revision 1.39
1 /* $NetBSD: pciide_common.c,v 1.39 2009/03/14 15:36:19 dsl Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.39 2009/03/14 15:36:19 dsl Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/malloc.h> 83 84 #include <uvm/uvm_extern.h> 85 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pcidevs.h> 89 #include <dev/pci/pciidereg.h> 90 #include <dev/pci/pciidevar.h> 91 92 #include <dev/ic/wdcreg.h> 93 94 #ifdef ATADEBUG 95 int atadebug_pciide_mask = 0; 96 #endif 97 98 #if NATA_DMA 99 static const char dmaerrfmt[] = 100 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 101 #endif 102 103 /* Default product description for devices not known from this controller */ 104 const struct pciide_product_desc default_product_desc = { 105 0, 106 0, 107 "Generic PCI IDE controller", 108 default_chip_map, 109 }; 110 111 const struct pciide_product_desc * 112 pciide_lookup_product(pcireg_t id, const struct pciide_product_desc *pp) 113 { 114 for (; pp->chip_map != NULL; pp++) 115 if (PCI_PRODUCT(id) == pp->ide_product) 116 break; 117 118 if (pp->chip_map == NULL) 119 return NULL; 120 return pp; 121 } 122 123 void 124 pciide_common_attach(struct pciide_softc *sc, struct pci_attach_args *pa, const struct pciide_product_desc *pp) 125 { 126 pci_chipset_tag_t pc = pa->pa_pc; 127 pcitag_t tag = pa->pa_tag; 128 #if NATA_DMA 129 pcireg_t csr; 130 #endif 131 char devinfo[256]; 132 const char *displaydev; 133 134 aprint_naive(": disk controller\n"); 135 aprint_normal("\n"); 136 137 sc->sc_pci_id = pa->pa_id; 138 if (pp == NULL) { 139 /* should only happen for generic pciide devices */ 140 sc->sc_pp = &default_product_desc; 141 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 142 displaydev = devinfo; 143 } else { 144 sc->sc_pp = pp; 145 displaydev = sc->sc_pp->ide_name; 146 } 147 148 /* if displaydev == NULL, printf is done in chip-specific map */ 149 if (displaydev) 150 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 151 "%s (rev. 0x%02x)\n", displaydev, 152 PCI_REVISION(pa->pa_class)); 153 154 sc->sc_pc = pa->pa_pc; 155 sc->sc_tag = pa->pa_tag; 156 157 #if NATA_DMA 158 /* Set up DMA defaults; these might be adjusted by chip_map. */ 159 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 160 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 161 #endif 162 163 #ifdef ATADEBUG 164 if (atadebug_pciide_mask & DEBUG_PROBE) 165 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 166 #endif 167 sc->sc_pp->chip_map(sc, pa); 168 169 #if NATA_DMA 170 if (sc->sc_dma_ok) { 171 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 172 csr |= PCI_COMMAND_MASTER_ENABLE; 173 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 174 } 175 #endif 176 ATADEBUG_PRINT(("pciide: command/status register=%x\n", 177 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 178 } 179 180 /* tell whether the chip is enabled or not */ 181 int 182 pciide_chipen(struct pciide_softc *sc, struct pci_attach_args *pa) 183 { 184 pcireg_t csr; 185 186 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 187 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 188 PCI_COMMAND_STATUS_REG); 189 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 190 "device disabled (at %s)\n", 191 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 192 "device" : "bridge"); 193 return 0; 194 } 195 return 1; 196 } 197 198 void 199 pciide_mapregs_compat(pa, cp, compatchan, cmdsizep, ctlsizep) 200 struct pci_attach_args *pa; 201 struct pciide_channel *cp; 202 int compatchan; 203 bus_size_t *cmdsizep, *ctlsizep; 204 { 205 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 206 struct ata_channel *wdc_cp = &cp->ata_channel; 207 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 208 int i; 209 210 cp->compat = 1; 211 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 212 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 213 214 wdr->cmd_iot = pa->pa_iot; 215 if (bus_space_map(wdr->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 216 PCIIDE_COMPAT_CMD_SIZE, 0, &wdr->cmd_baseioh) != 0) { 217 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 218 "couldn't map %s channel cmd regs\n", cp->name); 219 goto bad; 220 } 221 222 wdr->ctl_iot = pa->pa_iot; 223 if (bus_space_map(wdr->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 224 PCIIDE_COMPAT_CTL_SIZE, 0, &wdr->ctl_ioh) != 0) { 225 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 226 "couldn't map %s channel ctl regs\n", cp->name); 227 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 228 PCIIDE_COMPAT_CMD_SIZE); 229 goto bad; 230 } 231 232 for (i = 0; i < WDC_NREG; i++) { 233 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 234 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 235 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 236 "couldn't subregion %s channel cmd regs\n", 237 cp->name); 238 goto bad; 239 } 240 } 241 wdc_init_shadow_regs(wdc_cp); 242 wdr->data32iot = wdr->cmd_iot; 243 wdr->data32ioh = wdr->cmd_iohs[0]; 244 return; 245 246 bad: 247 cp->ata_channel.ch_flags |= ATACH_DISABLED; 248 return; 249 } 250 251 void 252 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 253 struct pci_attach_args * pa; 254 struct pciide_channel *cp; 255 bus_size_t *cmdsizep, *ctlsizep; 256 int (*pci_intr)(void *); 257 { 258 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 259 struct ata_channel *wdc_cp = &cp->ata_channel; 260 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 261 const char *intrstr; 262 pci_intr_handle_t intrhandle; 263 int i; 264 265 cp->compat = 0; 266 267 if (sc->sc_pci_ih == NULL) { 268 if (pci_intr_map(pa, &intrhandle) != 0) { 269 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 270 "couldn't map native-PCI interrupt\n"); 271 goto bad; 272 } 273 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 274 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 275 intrhandle, IPL_BIO, pci_intr, sc); 276 if (sc->sc_pci_ih != NULL) { 277 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 278 "using %s for native-PCI interrupt\n", 279 intrstr ? intrstr : "unknown interrupt"); 280 } else { 281 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 282 "couldn't establish native-PCI interrupt"); 283 if (intrstr != NULL) 284 aprint_error(" at %s", intrstr); 285 aprint_error("\n"); 286 goto bad; 287 } 288 } 289 cp->ih = sc->sc_pci_ih; 290 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel), 291 PCI_MAPREG_TYPE_IO, 0, 292 &wdr->cmd_iot, &wdr->cmd_baseioh, NULL, cmdsizep) != 0) { 293 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 294 "couldn't map %s channel cmd regs\n", cp->name); 295 goto bad; 296 } 297 298 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel), 299 PCI_MAPREG_TYPE_IO, 0, 300 &wdr->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 301 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 302 "couldn't map %s channel ctl regs\n", cp->name); 303 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 304 *cmdsizep); 305 goto bad; 306 } 307 /* 308 * In native mode, 4 bytes of I/O space are mapped for the control 309 * register, the control register is at offset 2. Pass the generic 310 * code a handle for only one byte at the right offset. 311 */ 312 if (bus_space_subregion(wdr->ctl_iot, cp->ctl_baseioh, 2, 1, 313 &wdr->ctl_ioh) != 0) { 314 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 315 "unable to subregion %s channel ctl regs\n", cp->name); 316 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 317 *cmdsizep); 318 bus_space_unmap(wdr->cmd_iot, cp->ctl_baseioh, *ctlsizep); 319 goto bad; 320 } 321 322 for (i = 0; i < WDC_NREG; i++) { 323 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 324 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 325 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 326 "couldn't subregion %s channel cmd regs\n", 327 cp->name); 328 goto bad; 329 } 330 } 331 wdc_init_shadow_regs(wdc_cp); 332 wdr->data32iot = wdr->cmd_iot; 333 wdr->data32ioh = wdr->cmd_iohs[0]; 334 return; 335 336 bad: 337 cp->ata_channel.ch_flags |= ATACH_DISABLED; 338 return; 339 } 340 341 #if NATA_DMA 342 void 343 pciide_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 344 { 345 pcireg_t maptype; 346 bus_addr_t addr; 347 struct pciide_channel *pc; 348 int reg, chan; 349 bus_size_t size; 350 351 /* 352 * Map DMA registers 353 * 354 * Note that sc_dma_ok is the right variable to test to see if 355 * DMA can be done. If the interface doesn't support DMA, 356 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 357 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 358 * non-zero if the interface supports DMA and the registers 359 * could be mapped. 360 * 361 * XXX Note that despite the fact that the Bus Master IDE specs 362 * XXX say that "The bus master IDE function uses 16 bytes of IO 363 * XXX space," some controllers (at least the United 364 * XXX Microelectronics UM8886BF) place it in memory space. 365 */ 366 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 367 PCIIDE_REG_BUS_MASTER_DMA); 368 369 switch (maptype) { 370 case PCI_MAPREG_TYPE_IO: 371 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 372 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 373 &addr, NULL, NULL) == 0); 374 if (sc->sc_dma_ok == 0) { 375 aprint_verbose( 376 ", but unused (couldn't query registers)"); 377 break; 378 } 379 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 380 && addr >= 0x10000) { 381 sc->sc_dma_ok = 0; 382 aprint_verbose( 383 ", but unused (registers at unsafe address " 384 "%#lx)", (unsigned long)addr); 385 break; 386 } 387 /* FALLTHROUGH */ 388 389 case PCI_MAPREG_MEM_TYPE_32BIT: 390 sc->sc_dma_ok = (pci_mapreg_map(pa, 391 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 392 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 393 sc->sc_dmat = pa->pa_dmat; 394 if (sc->sc_dma_ok == 0) { 395 aprint_verbose(", but unused (couldn't map registers)"); 396 } else { 397 sc->sc_wdcdev.dma_arg = sc; 398 sc->sc_wdcdev.dma_init = pciide_dma_init; 399 sc->sc_wdcdev.dma_start = pciide_dma_start; 400 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 401 } 402 403 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 404 PCIIDE_OPTIONS_NODMA) { 405 aprint_verbose( 406 ", but unused (forced off by config file)"); 407 sc->sc_dma_ok = 0; 408 } 409 break; 410 411 default: 412 sc->sc_dma_ok = 0; 413 aprint_verbose( 414 ", but unsupported register maptype (0x%x)", maptype); 415 } 416 417 if (sc->sc_dma_ok == 0) 418 return; 419 420 /* 421 * Set up the default handles for the DMA registers. 422 * Just reserve 32 bits for each handle, unless space 423 * doesn't permit it. 424 */ 425 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { 426 pc = &sc->pciide_channels[chan]; 427 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 428 size = 4; 429 if (size > (IDEDMA_SCH_OFFSET - reg)) 430 size = IDEDMA_SCH_OFFSET - reg; 431 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 432 IDEDMA_SCH_OFFSET * chan + reg, size, 433 &pc->dma_iohs[reg]) != 0) { 434 sc->sc_dma_ok = 0; 435 aprint_verbose(", but can't subregion offset %d " 436 "size %lu", reg, (u_long)size); 437 return; 438 } 439 } 440 } 441 } 442 #endif /* NATA_DMA */ 443 444 int 445 pciide_compat_intr(void *arg) 446 { 447 struct pciide_channel *cp = arg; 448 449 #ifdef DIAGNOSTIC 450 /* should only be called for a compat channel */ 451 if (cp->compat == 0) 452 panic("pciide compat intr called for non-compat chan %p", cp); 453 #endif 454 return (wdcintr(&cp->ata_channel)); 455 } 456 457 int 458 pciide_pci_intr(void *arg) 459 { 460 struct pciide_softc *sc = arg; 461 struct pciide_channel *cp; 462 struct ata_channel *wdc_cp; 463 int i, rv, crv; 464 465 rv = 0; 466 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 467 cp = &sc->pciide_channels[i]; 468 wdc_cp = &cp->ata_channel; 469 470 /* If a compat channel skip. */ 471 if (cp->compat) 472 continue; 473 /* if this channel not waiting for intr, skip */ 474 if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0) 475 continue; 476 477 crv = wdcintr(wdc_cp); 478 if (crv == 0) 479 ; /* leave rv alone */ 480 else if (crv == 1) 481 rv = 1; /* claim the intr */ 482 else if (rv == 0) /* crv should be -1 in this case */ 483 rv = crv; /* if we've done no better, take it */ 484 } 485 return (rv); 486 } 487 488 #if NATA_DMA 489 void 490 pciide_channel_dma_setup(struct pciide_channel *cp) 491 { 492 int drive, s; 493 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 494 struct ata_drive_datas *drvp; 495 496 KASSERT(cp->ata_channel.ch_ndrive != 0); 497 498 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 499 drvp = &cp->ata_channel.ch_drive[drive]; 500 /* If no drive, skip */ 501 if ((drvp->drive_flags & DRIVE) == 0) 502 continue; 503 /* setup DMA if needed */ 504 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 505 (drvp->drive_flags & DRIVE_UDMA) == 0) || 506 sc->sc_dma_ok == 0) { 507 s = splbio(); 508 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 509 splx(s); 510 continue; 511 } 512 if (pciide_dma_table_setup(sc, cp->ata_channel.ch_channel, 513 drive) != 0) { 514 /* Abort DMA setup */ 515 s = splbio(); 516 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 517 splx(s); 518 continue; 519 } 520 } 521 } 522 523 #define NIDEDMA_TABLES(sc) \ 524 (MAXPHYS/(min((sc)->sc_dma_maxsegsz, PAGE_SIZE)) + 1) 525 526 int 527 pciide_dma_table_setup(sc, channel, drive) 528 struct pciide_softc *sc; 529 int channel, drive; 530 { 531 bus_dma_segment_t seg; 532 int error, rseg; 533 const bus_size_t dma_table_size = 534 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc); 535 struct pciide_dma_maps *dma_maps = 536 &sc->pciide_channels[channel].dma_maps[drive]; 537 538 /* If table was already allocated, just return */ 539 if (dma_maps->dma_table) 540 return 0; 541 542 /* Allocate memory for the DMA tables and map it */ 543 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 544 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 545 BUS_DMA_NOWAIT)) != 0) { 546 aprint_error(dmaerrfmt, 547 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 548 "allocate", drive, error); 549 return error; 550 } 551 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 552 dma_table_size, 553 (void **)&dma_maps->dma_table, 554 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 555 aprint_error(dmaerrfmt, 556 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 557 "map", drive, error); 558 return error; 559 } 560 ATADEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 561 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 562 (unsigned long)seg.ds_addr), DEBUG_PROBE); 563 /* Create and load table DMA map for this disk */ 564 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 565 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 566 &dma_maps->dmamap_table)) != 0) { 567 aprint_error(dmaerrfmt, 568 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 569 "create", drive, error); 570 return error; 571 } 572 if ((error = bus_dmamap_load(sc->sc_dmat, 573 dma_maps->dmamap_table, 574 dma_maps->dma_table, 575 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 576 aprint_error(dmaerrfmt, 577 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 578 "load", drive, error); 579 return error; 580 } 581 ATADEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 582 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 583 DEBUG_PROBE); 584 /* Create a xfer DMA map for this drive */ 585 if ((error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 586 NIDEDMA_TABLES(sc), sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 587 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 588 &dma_maps->dmamap_xfer)) != 0) { 589 aprint_error(dmaerrfmt, 590 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 591 "create xfer", drive, error); 592 return error; 593 } 594 return 0; 595 } 596 597 int 598 pciide_dma_dmamap_setup(sc, channel, drive, databuf, datalen, flags) 599 struct pciide_softc *sc; 600 int channel, drive; 601 void *databuf; 602 size_t datalen; 603 int flags; 604 { 605 int error, seg; 606 struct pciide_channel *cp = &sc->pciide_channels[channel]; 607 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 608 609 error = bus_dmamap_load(sc->sc_dmat, 610 dma_maps->dmamap_xfer, 611 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 612 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 613 if (error) { 614 aprint_error(dmaerrfmt, 615 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 616 "load xfer", drive, error); 617 return error; 618 } 619 620 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 621 dma_maps->dmamap_xfer->dm_mapsize, 622 (flags & WDC_DMA_READ) ? 623 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 624 625 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 626 #ifdef DIAGNOSTIC 627 /* A segment must not cross a 64k boundary */ 628 { 629 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 630 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 631 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 632 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 633 printf("pciide_dma: segment %d physical addr 0x%lx" 634 " len 0x%lx not properly aligned\n", 635 seg, phys, len); 636 panic("pciide_dma: buf align"); 637 } 638 } 639 #endif 640 dma_maps->dma_table[seg].base_addr = 641 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 642 dma_maps->dma_table[seg].byte_count = 643 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 644 IDEDMA_BYTE_COUNT_MASK); 645 ATADEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 646 seg, le32toh(dma_maps->dma_table[seg].byte_count), 647 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 648 649 } 650 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 651 htole32(IDEDMA_BYTE_COUNT_EOT); 652 653 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 654 dma_maps->dmamap_table->dm_mapsize, 655 BUS_DMASYNC_PREWRITE); 656 657 #ifdef DIAGNOSTIC 658 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 659 printf("pciide_dma_dmamap_setup: addr 0x%lx " 660 "not properly aligned\n", 661 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 662 panic("pciide_dma_init: table align"); 663 } 664 #endif 665 /* remember flags */ 666 dma_maps->dma_flags = flags; 667 668 return 0; 669 } 670 671 int 672 pciide_dma_init(v, channel, drive, databuf, datalen, flags) 673 void *v; 674 int channel, drive; 675 void *databuf; 676 size_t datalen; 677 int flags; 678 { 679 struct pciide_softc *sc = v; 680 int error; 681 struct pciide_channel *cp = &sc->pciide_channels[channel]; 682 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 683 684 if ((error = pciide_dma_dmamap_setup(sc, channel, drive, 685 databuf, datalen, flags)) != 0) 686 return error; 687 /* Maps are ready. Start DMA function */ 688 /* Clear status bits */ 689 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 690 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 691 /* Write table addr */ 692 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 693 dma_maps->dmamap_table->dm_segs[0].ds_addr); 694 /* set read/write */ 695 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 696 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 697 return 0; 698 } 699 700 void 701 pciide_dma_start(void *v, int channel, int drive) 702 { 703 struct pciide_softc *sc = v; 704 struct pciide_channel *cp = &sc->pciide_channels[channel]; 705 706 ATADEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 707 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 708 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 709 | IDEDMA_CMD_START); 710 } 711 712 int 713 pciide_dma_finish(v, channel, drive, force) 714 void *v; 715 int channel, drive; 716 int force; 717 { 718 struct pciide_softc *sc = v; 719 u_int8_t status; 720 int error = 0; 721 struct pciide_channel *cp = &sc->pciide_channels[channel]; 722 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 723 724 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0); 725 ATADEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 726 DEBUG_XFERS); 727 728 if (force == WDC_DMAEND_END && (status & IDEDMA_CTL_INTR) == 0) 729 return WDC_DMAST_NOIRQ; 730 731 /* stop DMA channel */ 732 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 733 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 734 & ~IDEDMA_CMD_START); 735 736 /* Unload the map of the data buffer */ 737 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 738 dma_maps->dmamap_xfer->dm_mapsize, 739 (dma_maps->dma_flags & WDC_DMA_READ) ? 740 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 741 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 742 743 if ((status & IDEDMA_CTL_ERR) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 744 aprint_error("%s:%d:%d: bus-master DMA error: status=0x%x\n", 745 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 746 drive, status); 747 error |= WDC_DMAST_ERR; 748 } 749 750 if ((status & IDEDMA_CTL_INTR) == 0 && force != WDC_DMAEND_ABRT_QUIET) { 751 aprint_error("%s:%d:%d: bus-master DMA error: missing " 752 "interrupt, status=0x%x\n", 753 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 754 channel, drive, status); 755 error |= WDC_DMAST_NOIRQ; 756 } 757 758 if ((status & IDEDMA_CTL_ACT) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 759 /* data underrun, may be a valid condition for ATAPI */ 760 error |= WDC_DMAST_UNDER; 761 } 762 return error; 763 } 764 765 void 766 pciide_irqack(struct ata_channel *chp) 767 { 768 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 769 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 770 771 /* clear status bits in IDE DMA registers */ 772 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 773 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 774 } 775 #endif /* NATA_DMA */ 776 777 /* some common code used by several chip_map */ 778 int 779 pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface) 780 { 781 struct pciide_channel *cp = &sc->pciide_channels[channel]; 782 sc->wdc_chanarray[channel] = &cp->ata_channel; 783 cp->name = PCIIDE_CHANNEL_NAME(channel); 784 cp->ata_channel.ch_channel = channel; 785 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 786 cp->ata_channel.ch_queue = 787 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 788 if (cp->ata_channel.ch_queue == NULL) { 789 aprint_error("%s %s channel: " 790 "can't allocate memory for command queue", 791 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 792 return 0; 793 } 794 cp->ata_channel.ch_ndrive = 2; 795 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 796 "%s channel %s to %s mode\n", cp->name, 797 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 798 "configured" : "wired", 799 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 800 "native-PCI" : "compatibility"); 801 return 1; 802 } 803 804 /* some common code used by several chip channel_map */ 805 void 806 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 807 struct pci_attach_args *pa; 808 struct pciide_channel *cp; 809 pcireg_t interface; 810 bus_size_t *cmdsizep, *ctlsizep; 811 int (*pci_intr)(void *); 812 { 813 struct ata_channel *wdc_cp = &cp->ata_channel; 814 815 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) 816 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr); 817 else { 818 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep, 819 ctlsizep); 820 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 821 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 822 } 823 wdcattach(wdc_cp); 824 } 825 826 /* 827 * generic code to map the compat intr. 828 */ 829 void 830 pciide_map_compat_intr(struct pci_attach_args *pa, struct pciide_channel *cp, int compatchan) 831 { 832 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 833 834 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 835 cp->ih = 836 pciide_machdep_compat_intr_establish(sc->sc_wdcdev.sc_atac.atac_dev, 837 pa, compatchan, pciide_compat_intr, cp); 838 if (cp->ih == NULL) { 839 #endif 840 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 841 "no compatibility interrupt for use by %s " 842 "channel\n", cp->name); 843 cp->ata_channel.ch_flags |= ATACH_DISABLED; 844 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 845 } 846 #endif 847 } 848 849 void 850 default_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 851 { 852 struct pciide_channel *cp; 853 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 854 pcireg_t csr; 855 int channel; 856 #if NATA_DMA 857 int drive; 858 u_int8_t idedma_ctl; 859 #endif 860 bus_size_t cmdsize, ctlsize; 861 const char *failreason; 862 struct wdc_regs *wdr; 863 864 if (pciide_chipen(sc, pa) == 0) 865 return; 866 867 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 868 #if NATA_DMA 869 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 870 "bus-master DMA support present"); 871 if (sc->sc_pp == &default_product_desc && 872 (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 873 PCIIDE_OPTIONS_DMA) == 0) { 874 aprint_verbose(", but unused (no driver support)"); 875 sc->sc_dma_ok = 0; 876 } else { 877 pciide_mapreg_dma(sc, pa); 878 if (sc->sc_dma_ok != 0) 879 aprint_verbose(", used without full driver " 880 "support"); 881 } 882 #else 883 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 884 "bus-master DMA support present, but unused (no driver " 885 "support)"); 886 #endif /* NATA_DMA */ 887 } else { 888 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 889 "hardware does not support DMA"); 890 #if NATA_DMA 891 sc->sc_dma_ok = 0; 892 #endif 893 } 894 aprint_verbose("\n"); 895 #if NATA_DMA 896 if (sc->sc_dma_ok) { 897 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 898 sc->sc_wdcdev.irqack = pciide_irqack; 899 } 900 #endif 901 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 902 #if NATA_DMA 903 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 904 #endif 905 906 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 907 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 908 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 909 910 wdc_allocate_regs(&sc->sc_wdcdev); 911 912 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 913 channel++) { 914 cp = &sc->pciide_channels[channel]; 915 if (pciide_chansetup(sc, channel, interface) == 0) 916 continue; 917 wdr = CHAN_TO_WDC_REGS(&cp->ata_channel); 918 if (interface & PCIIDE_INTERFACE_PCI(channel)) 919 pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 920 pciide_pci_intr); 921 else 922 pciide_mapregs_compat(pa, cp, 923 cp->ata_channel.ch_channel, &cmdsize, &ctlsize); 924 if (cp->ata_channel.ch_flags & ATACH_DISABLED) 925 continue; 926 /* 927 * Check to see if something appears to be there. 928 */ 929 failreason = NULL; 930 /* 931 * In native mode, always enable the controller. It's 932 * not possible to have an ISA board using the same address 933 * anyway. 934 */ 935 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 936 wdcattach(&cp->ata_channel); 937 continue; 938 } 939 if (!wdcprobe(&cp->ata_channel)) { 940 failreason = "not responding; disabled or no drives?"; 941 goto next; 942 } 943 /* 944 * Now, make sure it's actually attributable to this PCI IDE 945 * channel by trying to access the channel again while the 946 * PCI IDE controller's I/O space is disabled. (If the 947 * channel no longer appears to be there, it belongs to 948 * this controller.) YUCK! 949 */ 950 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 951 PCI_COMMAND_STATUS_REG); 952 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 953 csr & ~PCI_COMMAND_IO_ENABLE); 954 if (wdcprobe(&cp->ata_channel)) 955 failreason = "other hardware responding at addresses"; 956 pci_conf_write(sc->sc_pc, sc->sc_tag, 957 PCI_COMMAND_STATUS_REG, csr); 958 next: 959 if (failreason) { 960 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 961 "%s channel ignored (%s)\n", cp->name, failreason); 962 cp->ata_channel.ch_flags |= ATACH_DISABLED; 963 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 964 cmdsize); 965 bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh, ctlsize); 966 } else { 967 pciide_map_compat_intr(pa, cp, 968 cp->ata_channel.ch_channel); 969 wdcattach(&cp->ata_channel); 970 } 971 } 972 973 #if NATA_DMA 974 if (sc->sc_dma_ok == 0) 975 return; 976 977 /* Allocate DMA maps */ 978 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 979 channel++) { 980 idedma_ctl = 0; 981 cp = &sc->pciide_channels[channel]; 982 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 983 /* 984 * we have not probed the drives yet, allocate 985 * ressources for all of them. 986 */ 987 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 988 /* Abort DMA setup */ 989 aprint_error( 990 "%s:%d:%d: can't allocate DMA maps, " 991 "using PIO transfers\n", 992 device_xname( 993 sc->sc_wdcdev.sc_atac.atac_dev), 994 channel, drive); 995 sc->sc_dma_ok = 0; 996 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA; 997 sc->sc_wdcdev.irqack = NULL; 998 break; 999 } 1000 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1001 } 1002 if (idedma_ctl != 0) { 1003 /* Add software bits in status register */ 1004 bus_space_write_1(sc->sc_dma_iot, 1005 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 1006 } 1007 } 1008 #endif /* NATA_DMA */ 1009 } 1010 1011 void 1012 sata_setup_channel(struct ata_channel *chp) 1013 { 1014 #if NATA_DMA 1015 struct ata_drive_datas *drvp; 1016 int drive; 1017 #if NATA_UDMA 1018 int s; 1019 #endif 1020 u_int32_t idedma_ctl; 1021 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 1022 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 1023 1024 /* setup DMA if needed */ 1025 pciide_channel_dma_setup(cp); 1026 1027 idedma_ctl = 0; 1028 1029 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 1030 drvp = &chp->ch_drive[drive]; 1031 /* If no drive, skip */ 1032 if ((drvp->drive_flags & DRIVE) == 0) 1033 continue; 1034 #if NATA_UDMA 1035 if (drvp->drive_flags & DRIVE_UDMA) { 1036 /* use Ultra/DMA */ 1037 s = splbio(); 1038 drvp->drive_flags &= ~DRIVE_DMA; 1039 splx(s); 1040 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1041 } else 1042 #endif /* NATA_UDMA */ 1043 if (drvp->drive_flags & DRIVE_DMA) { 1044 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1045 } 1046 } 1047 1048 /* 1049 * Nothing to do to setup modes; it is meaningless in S-ATA 1050 * (but many S-ATA drives still want to get the SET_FEATURE 1051 * command). 1052 */ 1053 if (idedma_ctl != 0) { 1054 /* Add software bits in status register */ 1055 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 1056 idedma_ctl); 1057 } 1058 #endif /* NATA_DMA */ 1059 } 1060
Indexes created Thu Oct 02 07:10:07 GMT 2025