pciide_common.c revision 1.40
1 /* $NetBSD: pciide_common.c,v 1.40 2009/03/14 21:04:21 dsl Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 */ 34 35 36 /* 37 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by Christopher G. Demetriou 50 * for the NetBSD Project. 51 * 4. The name of the author may not be used to endorse or promote products 52 * derived from this software without specific prior written permission 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 55 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 56 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 57 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 58 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 59 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 60 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 61 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 62 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 63 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66 /* 67 * PCI IDE controller driver. 68 * 69 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 70 * sys/dev/pci/ppb.c, revision 1.16). 71 * 72 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 73 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 74 * 5/16/94" from the PCI SIG. 75 * 76 */ 77 78 #include <sys/cdefs.h> 79 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.40 2009/03/14 21:04:21 dsl Exp $"); 80 81 #include <sys/param.h> 82 #include <sys/malloc.h> 83 84 #include <uvm/uvm_extern.h> 85 86 #include <dev/pci/pcireg.h> 87 #include <dev/pci/pcivar.h> 88 #include <dev/pci/pcidevs.h> 89 #include <dev/pci/pciidereg.h> 90 #include <dev/pci/pciidevar.h> 91 92 #include <dev/ic/wdcreg.h> 93 94 #ifdef ATADEBUG 95 int atadebug_pciide_mask = 0; 96 #endif 97 98 #if NATA_DMA 99 static const char dmaerrfmt[] = 100 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 101 #endif 102 103 /* Default product description for devices not known from this controller */ 104 const struct pciide_product_desc default_product_desc = { 105 0, 106 0, 107 "Generic PCI IDE controller", 108 default_chip_map, 109 }; 110 111 const struct pciide_product_desc * 112 pciide_lookup_product(pcireg_t id, const struct pciide_product_desc *pp) 113 { 114 for (; pp->chip_map != NULL; pp++) 115 if (PCI_PRODUCT(id) == pp->ide_product) 116 break; 117 118 if (pp->chip_map == NULL) 119 return NULL; 120 return pp; 121 } 122 123 void 124 pciide_common_attach(struct pciide_softc *sc, struct pci_attach_args *pa, const struct pciide_product_desc *pp) 125 { 126 pci_chipset_tag_t pc = pa->pa_pc; 127 pcitag_t tag = pa->pa_tag; 128 #if NATA_DMA 129 pcireg_t csr; 130 #endif 131 char devinfo[256]; 132 const char *displaydev; 133 134 aprint_naive(": disk controller\n"); 135 aprint_normal("\n"); 136 137 sc->sc_pci_id = pa->pa_id; 138 if (pp == NULL) { 139 /* should only happen for generic pciide devices */ 140 sc->sc_pp = &default_product_desc; 141 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 142 displaydev = devinfo; 143 } else { 144 sc->sc_pp = pp; 145 displaydev = sc->sc_pp->ide_name; 146 } 147 148 /* if displaydev == NULL, printf is done in chip-specific map */ 149 if (displaydev) 150 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 151 "%s (rev. 0x%02x)\n", displaydev, 152 PCI_REVISION(pa->pa_class)); 153 154 sc->sc_pc = pa->pa_pc; 155 sc->sc_tag = pa->pa_tag; 156 157 #if NATA_DMA 158 /* Set up DMA defaults; these might be adjusted by chip_map. */ 159 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 160 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 161 #endif 162 163 #ifdef ATADEBUG 164 if (atadebug_pciide_mask & DEBUG_PROBE) 165 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 166 #endif 167 sc->sc_pp->chip_map(sc, pa); 168 169 #if NATA_DMA 170 if (sc->sc_dma_ok) { 171 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 172 csr |= PCI_COMMAND_MASTER_ENABLE; 173 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 174 } 175 #endif 176 ATADEBUG_PRINT(("pciide: command/status register=%x\n", 177 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 178 } 179 180 /* tell whether the chip is enabled or not */ 181 int 182 pciide_chipen(struct pciide_softc *sc, struct pci_attach_args *pa) 183 { 184 pcireg_t csr; 185 186 if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) { 187 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 188 PCI_COMMAND_STATUS_REG); 189 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 190 "device disabled (at %s)\n", 191 (csr & PCI_COMMAND_IO_ENABLE) == 0 ? 192 "device" : "bridge"); 193 return 0; 194 } 195 return 1; 196 } 197 198 void 199 pciide_mapregs_compat(struct pci_attach_args *pa, struct pciide_channel *cp, int compatchan, bus_size_t *cmdsizep, bus_size_t *ctlsizep) 200 { 201 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 202 struct ata_channel *wdc_cp = &cp->ata_channel; 203 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 204 int i; 205 206 cp->compat = 1; 207 *cmdsizep = PCIIDE_COMPAT_CMD_SIZE; 208 *ctlsizep = PCIIDE_COMPAT_CTL_SIZE; 209 210 wdr->cmd_iot = pa->pa_iot; 211 if (bus_space_map(wdr->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 212 PCIIDE_COMPAT_CMD_SIZE, 0, &wdr->cmd_baseioh) != 0) { 213 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 214 "couldn't map %s channel cmd regs\n", cp->name); 215 goto bad; 216 } 217 218 wdr->ctl_iot = pa->pa_iot; 219 if (bus_space_map(wdr->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 220 PCIIDE_COMPAT_CTL_SIZE, 0, &wdr->ctl_ioh) != 0) { 221 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 222 "couldn't map %s channel ctl regs\n", cp->name); 223 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 224 PCIIDE_COMPAT_CMD_SIZE); 225 goto bad; 226 } 227 228 for (i = 0; i < WDC_NREG; i++) { 229 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 230 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 231 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 232 "couldn't subregion %s channel cmd regs\n", 233 cp->name); 234 goto bad; 235 } 236 } 237 wdc_init_shadow_regs(wdc_cp); 238 wdr->data32iot = wdr->cmd_iot; 239 wdr->data32ioh = wdr->cmd_iohs[0]; 240 return; 241 242 bad: 243 cp->ata_channel.ch_flags |= ATACH_DISABLED; 244 return; 245 } 246 247 void 248 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr) 249 struct pci_attach_args * pa; 250 struct pciide_channel *cp; 251 bus_size_t *cmdsizep, *ctlsizep; 252 int (*pci_intr)(void *); 253 { 254 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 255 struct ata_channel *wdc_cp = &cp->ata_channel; 256 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 257 const char *intrstr; 258 pci_intr_handle_t intrhandle; 259 int i; 260 261 cp->compat = 0; 262 263 if (sc->sc_pci_ih == NULL) { 264 if (pci_intr_map(pa, &intrhandle) != 0) { 265 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 266 "couldn't map native-PCI interrupt\n"); 267 goto bad; 268 } 269 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 270 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 271 intrhandle, IPL_BIO, pci_intr, sc); 272 if (sc->sc_pci_ih != NULL) { 273 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 274 "using %s for native-PCI interrupt\n", 275 intrstr ? intrstr : "unknown interrupt"); 276 } else { 277 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 278 "couldn't establish native-PCI interrupt"); 279 if (intrstr != NULL) 280 aprint_error(" at %s", intrstr); 281 aprint_error("\n"); 282 goto bad; 283 } 284 } 285 cp->ih = sc->sc_pci_ih; 286 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel), 287 PCI_MAPREG_TYPE_IO, 0, 288 &wdr->cmd_iot, &wdr->cmd_baseioh, NULL, cmdsizep) != 0) { 289 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 290 "couldn't map %s channel cmd regs\n", cp->name); 291 goto bad; 292 } 293 294 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel), 295 PCI_MAPREG_TYPE_IO, 0, 296 &wdr->ctl_iot, &cp->ctl_baseioh, NULL, ctlsizep) != 0) { 297 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 298 "couldn't map %s channel ctl regs\n", cp->name); 299 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 300 *cmdsizep); 301 goto bad; 302 } 303 /* 304 * In native mode, 4 bytes of I/O space are mapped for the control 305 * register, the control register is at offset 2. Pass the generic 306 * code a handle for only one byte at the right offset. 307 */ 308 if (bus_space_subregion(wdr->ctl_iot, cp->ctl_baseioh, 2, 1, 309 &wdr->ctl_ioh) != 0) { 310 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 311 "unable to subregion %s channel ctl regs\n", cp->name); 312 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 313 *cmdsizep); 314 bus_space_unmap(wdr->cmd_iot, cp->ctl_baseioh, *ctlsizep); 315 goto bad; 316 } 317 318 for (i = 0; i < WDC_NREG; i++) { 319 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 320 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 321 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 322 "couldn't subregion %s channel cmd regs\n", 323 cp->name); 324 goto bad; 325 } 326 } 327 wdc_init_shadow_regs(wdc_cp); 328 wdr->data32iot = wdr->cmd_iot; 329 wdr->data32ioh = wdr->cmd_iohs[0]; 330 return; 331 332 bad: 333 cp->ata_channel.ch_flags |= ATACH_DISABLED; 334 return; 335 } 336 337 #if NATA_DMA 338 void 339 pciide_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 340 { 341 pcireg_t maptype; 342 bus_addr_t addr; 343 struct pciide_channel *pc; 344 int reg, chan; 345 bus_size_t size; 346 347 /* 348 * Map DMA registers 349 * 350 * Note that sc_dma_ok is the right variable to test to see if 351 * DMA can be done. If the interface doesn't support DMA, 352 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 353 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 354 * non-zero if the interface supports DMA and the registers 355 * could be mapped. 356 * 357 * XXX Note that despite the fact that the Bus Master IDE specs 358 * XXX say that "The bus master IDE function uses 16 bytes of IO 359 * XXX space," some controllers (at least the United 360 * XXX Microelectronics UM8886BF) place it in memory space. 361 */ 362 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 363 PCIIDE_REG_BUS_MASTER_DMA); 364 365 switch (maptype) { 366 case PCI_MAPREG_TYPE_IO: 367 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 368 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 369 &addr, NULL, NULL) == 0); 370 if (sc->sc_dma_ok == 0) { 371 aprint_verbose( 372 ", but unused (couldn't query registers)"); 373 break; 374 } 375 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 376 && addr >= 0x10000) { 377 sc->sc_dma_ok = 0; 378 aprint_verbose( 379 ", but unused (registers at unsafe address " 380 "%#lx)", (unsigned long)addr); 381 break; 382 } 383 /* FALLTHROUGH */ 384 385 case PCI_MAPREG_MEM_TYPE_32BIT: 386 sc->sc_dma_ok = (pci_mapreg_map(pa, 387 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 388 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0); 389 sc->sc_dmat = pa->pa_dmat; 390 if (sc->sc_dma_ok == 0) { 391 aprint_verbose(", but unused (couldn't map registers)"); 392 } else { 393 sc->sc_wdcdev.dma_arg = sc; 394 sc->sc_wdcdev.dma_init = pciide_dma_init; 395 sc->sc_wdcdev.dma_start = pciide_dma_start; 396 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 397 } 398 399 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 400 PCIIDE_OPTIONS_NODMA) { 401 aprint_verbose( 402 ", but unused (forced off by config file)"); 403 sc->sc_dma_ok = 0; 404 } 405 break; 406 407 default: 408 sc->sc_dma_ok = 0; 409 aprint_verbose( 410 ", but unsupported register maptype (0x%x)", maptype); 411 } 412 413 if (sc->sc_dma_ok == 0) 414 return; 415 416 /* 417 * Set up the default handles for the DMA registers. 418 * Just reserve 32 bits for each handle, unless space 419 * doesn't permit it. 420 */ 421 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { 422 pc = &sc->pciide_channels[chan]; 423 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 424 size = 4; 425 if (size > (IDEDMA_SCH_OFFSET - reg)) 426 size = IDEDMA_SCH_OFFSET - reg; 427 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 428 IDEDMA_SCH_OFFSET * chan + reg, size, 429 &pc->dma_iohs[reg]) != 0) { 430 sc->sc_dma_ok = 0; 431 aprint_verbose(", but can't subregion offset %d " 432 "size %lu", reg, (u_long)size); 433 return; 434 } 435 } 436 } 437 } 438 #endif /* NATA_DMA */ 439 440 int 441 pciide_compat_intr(void *arg) 442 { 443 struct pciide_channel *cp = arg; 444 445 #ifdef DIAGNOSTIC 446 /* should only be called for a compat channel */ 447 if (cp->compat == 0) 448 panic("pciide compat intr called for non-compat chan %p", cp); 449 #endif 450 return (wdcintr(&cp->ata_channel)); 451 } 452 453 int 454 pciide_pci_intr(void *arg) 455 { 456 struct pciide_softc *sc = arg; 457 struct pciide_channel *cp; 458 struct ata_channel *wdc_cp; 459 int i, rv, crv; 460 461 rv = 0; 462 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 463 cp = &sc->pciide_channels[i]; 464 wdc_cp = &cp->ata_channel; 465 466 /* If a compat channel skip. */ 467 if (cp->compat) 468 continue; 469 /* if this channel not waiting for intr, skip */ 470 if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0) 471 continue; 472 473 crv = wdcintr(wdc_cp); 474 if (crv == 0) 475 ; /* leave rv alone */ 476 else if (crv == 1) 477 rv = 1; /* claim the intr */ 478 else if (rv == 0) /* crv should be -1 in this case */ 479 rv = crv; /* if we've done no better, take it */ 480 } 481 return (rv); 482 } 483 484 #if NATA_DMA 485 void 486 pciide_channel_dma_setup(struct pciide_channel *cp) 487 { 488 int drive, s; 489 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 490 struct ata_drive_datas *drvp; 491 492 KASSERT(cp->ata_channel.ch_ndrive != 0); 493 494 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 495 drvp = &cp->ata_channel.ch_drive[drive]; 496 /* If no drive, skip */ 497 if ((drvp->drive_flags & DRIVE) == 0) 498 continue; 499 /* setup DMA if needed */ 500 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 501 (drvp->drive_flags & DRIVE_UDMA) == 0) || 502 sc->sc_dma_ok == 0) { 503 s = splbio(); 504 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 505 splx(s); 506 continue; 507 } 508 if (pciide_dma_table_setup(sc, cp->ata_channel.ch_channel, 509 drive) != 0) { 510 /* Abort DMA setup */ 511 s = splbio(); 512 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 513 splx(s); 514 continue; 515 } 516 } 517 } 518 519 #define NIDEDMA_TABLES(sc) \ 520 (MAXPHYS/(min((sc)->sc_dma_maxsegsz, PAGE_SIZE)) + 1) 521 522 int 523 pciide_dma_table_setup(struct pciide_softc *sc, int channel, int drive) 524 { 525 bus_dma_segment_t seg; 526 int error, rseg; 527 const bus_size_t dma_table_size = 528 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc); 529 struct pciide_dma_maps *dma_maps = 530 &sc->pciide_channels[channel].dma_maps[drive]; 531 532 /* If table was already allocated, just return */ 533 if (dma_maps->dma_table) 534 return 0; 535 536 /* Allocate memory for the DMA tables and map it */ 537 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 538 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &seg, 1, &rseg, 539 BUS_DMA_NOWAIT)) != 0) { 540 aprint_error(dmaerrfmt, 541 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 542 "allocate", drive, error); 543 return error; 544 } 545 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 546 dma_table_size, 547 (void **)&dma_maps->dma_table, 548 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 549 aprint_error(dmaerrfmt, 550 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 551 "map", drive, error); 552 return error; 553 } 554 ATADEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 555 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 556 (unsigned long)seg.ds_addr), DEBUG_PROBE); 557 /* Create and load table DMA map for this disk */ 558 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 559 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 560 &dma_maps->dmamap_table)) != 0) { 561 aprint_error(dmaerrfmt, 562 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 563 "create", drive, error); 564 return error; 565 } 566 if ((error = bus_dmamap_load(sc->sc_dmat, 567 dma_maps->dmamap_table, 568 dma_maps->dma_table, 569 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 570 aprint_error(dmaerrfmt, 571 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 572 "load", drive, error); 573 return error; 574 } 575 ATADEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 576 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 577 DEBUG_PROBE); 578 /* Create a xfer DMA map for this drive */ 579 if ((error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 580 NIDEDMA_TABLES(sc), sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 581 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 582 &dma_maps->dmamap_xfer)) != 0) { 583 aprint_error(dmaerrfmt, 584 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 585 "create xfer", drive, error); 586 return error; 587 } 588 return 0; 589 } 590 591 int 592 pciide_dma_dmamap_setup(struct pciide_softc *sc, int channel, int drive, void *databuf, size_t datalen, int flags) 593 { 594 int error, seg; 595 struct pciide_channel *cp = &sc->pciide_channels[channel]; 596 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 597 598 error = bus_dmamap_load(sc->sc_dmat, 599 dma_maps->dmamap_xfer, 600 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 601 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 602 if (error) { 603 aprint_error(dmaerrfmt, 604 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 605 "load xfer", drive, error); 606 return error; 607 } 608 609 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 610 dma_maps->dmamap_xfer->dm_mapsize, 611 (flags & WDC_DMA_READ) ? 612 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 613 614 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 615 #ifdef DIAGNOSTIC 616 /* A segment must not cross a 64k boundary */ 617 { 618 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 619 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 620 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 621 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 622 printf("pciide_dma: segment %d physical addr 0x%lx" 623 " len 0x%lx not properly aligned\n", 624 seg, phys, len); 625 panic("pciide_dma: buf align"); 626 } 627 } 628 #endif 629 dma_maps->dma_table[seg].base_addr = 630 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 631 dma_maps->dma_table[seg].byte_count = 632 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 633 IDEDMA_BYTE_COUNT_MASK); 634 ATADEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 635 seg, le32toh(dma_maps->dma_table[seg].byte_count), 636 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 637 638 } 639 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 640 htole32(IDEDMA_BYTE_COUNT_EOT); 641 642 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 643 dma_maps->dmamap_table->dm_mapsize, 644 BUS_DMASYNC_PREWRITE); 645 646 #ifdef DIAGNOSTIC 647 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 648 printf("pciide_dma_dmamap_setup: addr 0x%lx " 649 "not properly aligned\n", 650 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 651 panic("pciide_dma_init: table align"); 652 } 653 #endif 654 /* remember flags */ 655 dma_maps->dma_flags = flags; 656 657 return 0; 658 } 659 660 int 661 pciide_dma_init(void *v, int channel, int drive, void *databuf, size_t datalen, int flags) 662 { 663 struct pciide_softc *sc = v; 664 int error; 665 struct pciide_channel *cp = &sc->pciide_channels[channel]; 666 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 667 668 if ((error = pciide_dma_dmamap_setup(sc, channel, drive, 669 databuf, datalen, flags)) != 0) 670 return error; 671 /* Maps are ready. Start DMA function */ 672 /* Clear status bits */ 673 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 674 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 675 /* Write table addr */ 676 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 677 dma_maps->dmamap_table->dm_segs[0].ds_addr); 678 /* set read/write */ 679 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 680 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 681 return 0; 682 } 683 684 void 685 pciide_dma_start(void *v, int channel, int drive) 686 { 687 struct pciide_softc *sc = v; 688 struct pciide_channel *cp = &sc->pciide_channels[channel]; 689 690 ATADEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 691 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 692 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 693 | IDEDMA_CMD_START); 694 } 695 696 int 697 pciide_dma_finish(void *v, int channel, int drive, int force) 698 { 699 struct pciide_softc *sc = v; 700 u_int8_t status; 701 int error = 0; 702 struct pciide_channel *cp = &sc->pciide_channels[channel]; 703 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 704 705 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0); 706 ATADEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 707 DEBUG_XFERS); 708 709 if (force == WDC_DMAEND_END && (status & IDEDMA_CTL_INTR) == 0) 710 return WDC_DMAST_NOIRQ; 711 712 /* stop DMA channel */ 713 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 714 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 715 & ~IDEDMA_CMD_START); 716 717 /* Unload the map of the data buffer */ 718 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 719 dma_maps->dmamap_xfer->dm_mapsize, 720 (dma_maps->dma_flags & WDC_DMA_READ) ? 721 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 722 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 723 724 if ((status & IDEDMA_CTL_ERR) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 725 aprint_error("%s:%d:%d: bus-master DMA error: status=0x%x\n", 726 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 727 drive, status); 728 error |= WDC_DMAST_ERR; 729 } 730 731 if ((status & IDEDMA_CTL_INTR) == 0 && force != WDC_DMAEND_ABRT_QUIET) { 732 aprint_error("%s:%d:%d: bus-master DMA error: missing " 733 "interrupt, status=0x%x\n", 734 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 735 channel, drive, status); 736 error |= WDC_DMAST_NOIRQ; 737 } 738 739 if ((status & IDEDMA_CTL_ACT) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 740 /* data underrun, may be a valid condition for ATAPI */ 741 error |= WDC_DMAST_UNDER; 742 } 743 return error; 744 } 745 746 void 747 pciide_irqack(struct ata_channel *chp) 748 { 749 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 750 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 751 752 /* clear status bits in IDE DMA registers */ 753 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 754 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 755 } 756 #endif /* NATA_DMA */ 757 758 /* some common code used by several chip_map */ 759 int 760 pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface) 761 { 762 struct pciide_channel *cp = &sc->pciide_channels[channel]; 763 sc->wdc_chanarray[channel] = &cp->ata_channel; 764 cp->name = PCIIDE_CHANNEL_NAME(channel); 765 cp->ata_channel.ch_channel = channel; 766 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 767 cp->ata_channel.ch_queue = 768 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 769 if (cp->ata_channel.ch_queue == NULL) { 770 aprint_error("%s %s channel: " 771 "can't allocate memory for command queue", 772 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 773 return 0; 774 } 775 cp->ata_channel.ch_ndrive = 2; 776 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 777 "%s channel %s to %s mode\n", cp->name, 778 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 779 "configured" : "wired", 780 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 781 "native-PCI" : "compatibility"); 782 return 1; 783 } 784 785 /* some common code used by several chip channel_map */ 786 void 787 pciide_mapchan(pa, cp, interface, cmdsizep, ctlsizep, pci_intr) 788 struct pci_attach_args *pa; 789 struct pciide_channel *cp; 790 pcireg_t interface; 791 bus_size_t *cmdsizep, *ctlsizep; 792 int (*pci_intr)(void *); 793 { 794 struct ata_channel *wdc_cp = &cp->ata_channel; 795 796 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) 797 pciide_mapregs_native(pa, cp, cmdsizep, ctlsizep, pci_intr); 798 else { 799 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel, cmdsizep, 800 ctlsizep); 801 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 802 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 803 } 804 wdcattach(wdc_cp); 805 } 806 807 /* 808 * generic code to map the compat intr. 809 */ 810 void 811 pciide_map_compat_intr(struct pci_attach_args *pa, struct pciide_channel *cp, int compatchan) 812 { 813 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 814 815 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 816 cp->ih = 817 pciide_machdep_compat_intr_establish(sc->sc_wdcdev.sc_atac.atac_dev, 818 pa, compatchan, pciide_compat_intr, cp); 819 if (cp->ih == NULL) { 820 #endif 821 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 822 "no compatibility interrupt for use by %s " 823 "channel\n", cp->name); 824 cp->ata_channel.ch_flags |= ATACH_DISABLED; 825 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 826 } 827 #endif 828 } 829 830 void 831 default_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 832 { 833 struct pciide_channel *cp; 834 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 835 pcireg_t csr; 836 int channel; 837 #if NATA_DMA 838 int drive; 839 u_int8_t idedma_ctl; 840 #endif 841 bus_size_t cmdsize, ctlsize; 842 const char *failreason; 843 struct wdc_regs *wdr; 844 845 if (pciide_chipen(sc, pa) == 0) 846 return; 847 848 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 849 #if NATA_DMA 850 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 851 "bus-master DMA support present"); 852 if (sc->sc_pp == &default_product_desc && 853 (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 854 PCIIDE_OPTIONS_DMA) == 0) { 855 aprint_verbose(", but unused (no driver support)"); 856 sc->sc_dma_ok = 0; 857 } else { 858 pciide_mapreg_dma(sc, pa); 859 if (sc->sc_dma_ok != 0) 860 aprint_verbose(", used without full driver " 861 "support"); 862 } 863 #else 864 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 865 "bus-master DMA support present, but unused (no driver " 866 "support)"); 867 #endif /* NATA_DMA */ 868 } else { 869 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 870 "hardware does not support DMA"); 871 #if NATA_DMA 872 sc->sc_dma_ok = 0; 873 #endif 874 } 875 aprint_verbose("\n"); 876 #if NATA_DMA 877 if (sc->sc_dma_ok) { 878 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 879 sc->sc_wdcdev.irqack = pciide_irqack; 880 } 881 #endif 882 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 883 #if NATA_DMA 884 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 885 #endif 886 887 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 888 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 889 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 890 891 wdc_allocate_regs(&sc->sc_wdcdev); 892 893 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 894 channel++) { 895 cp = &sc->pciide_channels[channel]; 896 if (pciide_chansetup(sc, channel, interface) == 0) 897 continue; 898 wdr = CHAN_TO_WDC_REGS(&cp->ata_channel); 899 if (interface & PCIIDE_INTERFACE_PCI(channel)) 900 pciide_mapregs_native(pa, cp, &cmdsize, &ctlsize, 901 pciide_pci_intr); 902 else 903 pciide_mapregs_compat(pa, cp, 904 cp->ata_channel.ch_channel, &cmdsize, &ctlsize); 905 if (cp->ata_channel.ch_flags & ATACH_DISABLED) 906 continue; 907 /* 908 * Check to see if something appears to be there. 909 */ 910 failreason = NULL; 911 /* 912 * In native mode, always enable the controller. It's 913 * not possible to have an ISA board using the same address 914 * anyway. 915 */ 916 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 917 wdcattach(&cp->ata_channel); 918 continue; 919 } 920 if (!wdcprobe(&cp->ata_channel)) { 921 failreason = "not responding; disabled or no drives?"; 922 goto next; 923 } 924 /* 925 * Now, make sure it's actually attributable to this PCI IDE 926 * channel by trying to access the channel again while the 927 * PCI IDE controller's I/O space is disabled. (If the 928 * channel no longer appears to be there, it belongs to 929 * this controller.) YUCK! 930 */ 931 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 932 PCI_COMMAND_STATUS_REG); 933 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 934 csr & ~PCI_COMMAND_IO_ENABLE); 935 if (wdcprobe(&cp->ata_channel)) 936 failreason = "other hardware responding at addresses"; 937 pci_conf_write(sc->sc_pc, sc->sc_tag, 938 PCI_COMMAND_STATUS_REG, csr); 939 next: 940 if (failreason) { 941 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 942 "%s channel ignored (%s)\n", cp->name, failreason); 943 cp->ata_channel.ch_flags |= ATACH_DISABLED; 944 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 945 cmdsize); 946 bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh, ctlsize); 947 } else { 948 pciide_map_compat_intr(pa, cp, 949 cp->ata_channel.ch_channel); 950 wdcattach(&cp->ata_channel); 951 } 952 } 953 954 #if NATA_DMA 955 if (sc->sc_dma_ok == 0) 956 return; 957 958 /* Allocate DMA maps */ 959 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 960 channel++) { 961 idedma_ctl = 0; 962 cp = &sc->pciide_channels[channel]; 963 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 964 /* 965 * we have not probed the drives yet, allocate 966 * ressources for all of them. 967 */ 968 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 969 /* Abort DMA setup */ 970 aprint_error( 971 "%s:%d:%d: can't allocate DMA maps, " 972 "using PIO transfers\n", 973 device_xname( 974 sc->sc_wdcdev.sc_atac.atac_dev), 975 channel, drive); 976 sc->sc_dma_ok = 0; 977 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA; 978 sc->sc_wdcdev.irqack = NULL; 979 break; 980 } 981 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 982 } 983 if (idedma_ctl != 0) { 984 /* Add software bits in status register */ 985 bus_space_write_1(sc->sc_dma_iot, 986 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 987 } 988 } 989 #endif /* NATA_DMA */ 990 } 991 992 void 993 sata_setup_channel(struct ata_channel *chp) 994 { 995 #if NATA_DMA 996 struct ata_drive_datas *drvp; 997 int drive; 998 #if NATA_UDMA 999 int s; 1000 #endif 1001 u_int32_t idedma_ctl; 1002 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 1003 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 1004 1005 /* setup DMA if needed */ 1006 pciide_channel_dma_setup(cp); 1007 1008 idedma_ctl = 0; 1009 1010 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 1011 drvp = &chp->ch_drive[drive]; 1012 /* If no drive, skip */ 1013 if ((drvp->drive_flags & DRIVE) == 0) 1014 continue; 1015 #if NATA_UDMA 1016 if (drvp->drive_flags & DRIVE_UDMA) { 1017 /* use Ultra/DMA */ 1018 s = splbio(); 1019 drvp->drive_flags &= ~DRIVE_DMA; 1020 splx(s); 1021 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1022 } else 1023 #endif /* NATA_UDMA */ 1024 if (drvp->drive_flags & DRIVE_DMA) { 1025 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1026 } 1027 } 1028 1029 /* 1030 * Nothing to do to setup modes; it is meaningless in S-ATA 1031 * (but many S-ATA drives still want to get the SET_FEATURE 1032 * command). 1033 */ 1034 if (idedma_ctl != 0) { 1035 /* Add software bits in status register */ 1036 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 1037 idedma_ctl); 1038 } 1039 #endif /* NATA_DMA */ 1040 } 1041
Indexes created Thu Oct 02 07:10:07 GMT 2025