pciide_common.c revision 1.48.2.1
1 /* $NetBSD: pciide_common.c,v 1.48.2.1 2011/06/06 09:08:25 jruoho Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 30 /* 31 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by Christopher G. Demetriou 44 * for the NetBSD Project. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * PCI IDE controller driver. 62 * 63 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 64 * sys/dev/pci/ppb.c, revision 1.16). 65 * 66 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 67 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 68 * 5/16/94" from the PCI SIG. 69 * 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.48.2.1 2011/06/06 09:08:25 jruoho Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/malloc.h> 77 78 #include <dev/pci/pcireg.h> 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcidevs.h> 81 #include <dev/pci/pciidereg.h> 82 #include <dev/pci/pciidevar.h> 83 84 #include <dev/ic/wdcreg.h> 85 86 #ifdef ATADEBUG 87 int atadebug_pciide_mask = 0; 88 #endif 89 90 #if NATA_DMA 91 static const char dmaerrfmt[] = 92 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 93 #endif 94 95 /* Default product description for devices not known from this controller */ 96 const struct pciide_product_desc default_product_desc = { 97 0, 98 0, 99 "Generic PCI IDE controller", 100 default_chip_map, 101 }; 102 103 const struct pciide_product_desc * 104 pciide_lookup_product(pcireg_t id, const struct pciide_product_desc *pp) 105 { 106 for (; pp->chip_map != NULL; pp++) 107 if (PCI_PRODUCT(id) == pp->ide_product) 108 break; 109 110 if (pp->chip_map == NULL) 111 return NULL; 112 return pp; 113 } 114 115 void 116 pciide_common_attach(struct pciide_softc *sc, const struct pci_attach_args *pa, const struct pciide_product_desc *pp) 117 { 118 pci_chipset_tag_t pc = pa->pa_pc; 119 pcitag_t tag = pa->pa_tag; 120 #if NATA_DMA 121 pcireg_t csr; 122 #endif 123 char devinfo[256]; 124 const char *displaydev; 125 126 aprint_naive(": disk controller\n"); 127 128 sc->sc_pci_id = pa->pa_id; 129 if (pp == NULL) { 130 /* should only happen for generic pciide devices */ 131 sc->sc_pp = &default_product_desc; 132 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 133 displaydev = devinfo; 134 } else { 135 sc->sc_pp = pp; 136 displaydev = sc->sc_pp->ide_name; 137 } 138 139 /* if displaydev == NULL, printf is done in chip-specific map */ 140 if (displaydev) 141 aprint_normal(": %s (rev. 0x%02x)\n", displaydev, 142 PCI_REVISION(pa->pa_class)); 143 else 144 aprint_normal("\n"); 145 146 sc->sc_pc = pa->pa_pc; 147 sc->sc_tag = pa->pa_tag; 148 149 #if NATA_DMA 150 /* Set up DMA defaults; these might be adjusted by chip_map. */ 151 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 152 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 153 #endif 154 155 #ifdef ATADEBUG 156 if (atadebug_pciide_mask & DEBUG_PROBE) 157 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 158 #endif 159 sc->sc_pp->chip_map(sc, pa); 160 161 #if NATA_DMA 162 if (sc->sc_dma_ok) { 163 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 164 csr |= PCI_COMMAND_MASTER_ENABLE; 165 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 166 } 167 #endif 168 ATADEBUG_PRINT(("pciide: command/status register=%x\n", 169 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 170 } 171 172 int 173 pciide_common_detach(struct pciide_softc *sc, int flags) 174 { 175 struct pciide_channel *cp; 176 struct ata_channel *wdc_cp; 177 struct wdc_regs *wdr; 178 int channel, drive; 179 int rv; 180 181 rv = wdcdetach(sc->sc_wdcdev.sc_atac.atac_dev, flags); 182 if (rv) 183 return rv; 184 185 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 186 channel++) { 187 cp = &sc->pciide_channels[channel]; 188 wdc_cp = &cp->ata_channel; 189 wdr = CHAN_TO_WDC_REGS(wdc_cp); 190 191 if (wdc_cp->ch_flags & ATACH_DISABLED) 192 continue; 193 194 if (wdr->cmd_ios != 0) 195 bus_space_unmap(wdr->cmd_iot, 196 wdr->cmd_baseioh, wdr->cmd_ios); 197 if (cp->compat != 0) { 198 if (wdr->ctl_ios != 0) 199 bus_space_unmap(wdr->ctl_iot, 200 wdr->ctl_ioh, wdr->ctl_ios); 201 } else { 202 if (cp->ctl_ios != 0) 203 bus_space_unmap(wdr->ctl_iot, 204 cp->ctl_baseioh, cp->ctl_ios); 205 } 206 207 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 208 #if NATA_DMA 209 pciide_dma_table_teardown(sc, channel, drive); 210 #endif 211 } 212 213 free(cp->ata_channel.ch_queue, M_DEVBUF); 214 cp->ata_channel.atabus = NULL; 215 } 216 217 #if NATA_DMA 218 if (sc->sc_dma_ios != 0) 219 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios); 220 if (sc->sc_ba5_ss != 0) 221 bus_space_unmap(sc->sc_ba5_st, sc->sc_ba5_sh, sc->sc_ba5_ss); 222 #endif 223 224 return 0; 225 } 226 227 int 228 pciide_detach(device_t self, int flags) 229 { 230 struct pciide_softc *sc = device_private(self); 231 struct pciide_channel *cp; 232 int channel; 233 #ifndef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH 234 bool has_compat_chan; 235 236 has_compat_chan = false; 237 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 238 channel++) { 239 cp = &sc->pciide_channels[channel]; 240 if (cp->compat != 0) { 241 has_compat_chan = true; 242 } 243 } 244 245 if (has_compat_chan != false) 246 return EBUSY; 247 #endif 248 249 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 250 channel++) { 251 cp = &sc->pciide_channels[channel]; 252 if (cp->compat != 0) 253 if (cp->ih != NULL) 254 pciide_unmap_compat_intr(sc->sc_pc, cp, channel); 255 } 256 257 if (sc->sc_pci_ih != NULL) 258 pci_intr_disestablish(sc->sc_pc, sc->sc_pci_ih); 259 260 return pciide_common_detach(sc, flags); 261 } 262 263 /* tell whether the chip is enabled or not */ 264 int 265 pciide_chipen(struct pciide_softc *sc, const struct pci_attach_args *pa) 266 { 267 pcireg_t csr; 268 269 if ((pa->pa_flags & PCI_FLAGS_IO_OKAY) == 0) { 270 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 271 "I/O access disabled at bridge\n"); 272 return 0; 273 } 274 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 275 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) { 276 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 277 "I/O access disabled at device\n"); 278 return 0; 279 } 280 return 1; 281 } 282 283 void 284 pciide_mapregs_compat(const struct pci_attach_args *pa, struct pciide_channel *cp, int compatchan) 285 { 286 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 287 struct ata_channel *wdc_cp = &cp->ata_channel; 288 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 289 int i; 290 291 cp->compat = 1; 292 293 wdr->cmd_iot = pa->pa_iot; 294 if (bus_space_map(wdr->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 295 PCIIDE_COMPAT_CMD_SIZE, 0, &wdr->cmd_baseioh) != 0) { 296 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 297 "couldn't map %s channel cmd regs\n", cp->name); 298 goto bad; 299 } 300 wdr->cmd_ios = PCIIDE_COMPAT_CMD_SIZE; 301 302 wdr->ctl_iot = pa->pa_iot; 303 if (bus_space_map(wdr->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 304 PCIIDE_COMPAT_CTL_SIZE, 0, &wdr->ctl_ioh) != 0) { 305 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 306 "couldn't map %s channel ctl regs\n", cp->name); 307 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 308 goto bad; 309 } 310 wdr->ctl_ios = PCIIDE_COMPAT_CTL_SIZE; 311 312 for (i = 0; i < WDC_NREG; i++) { 313 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 314 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 315 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 316 "couldn't subregion %s channel cmd regs\n", 317 cp->name); 318 goto bad; 319 } 320 } 321 wdc_init_shadow_regs(wdc_cp); 322 wdr->data32iot = wdr->cmd_iot; 323 wdr->data32ioh = wdr->cmd_iohs[0]; 324 return; 325 326 bad: 327 cp->ata_channel.ch_flags |= ATACH_DISABLED; 328 return; 329 } 330 331 void 332 pciide_mapregs_native(const struct pci_attach_args *pa, 333 struct pciide_channel *cp, int (*pci_intr)(void *)) 334 { 335 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 336 struct ata_channel *wdc_cp = &cp->ata_channel; 337 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 338 const char *intrstr; 339 pci_intr_handle_t intrhandle; 340 int i; 341 342 cp->compat = 0; 343 344 if (sc->sc_pci_ih == NULL) { 345 if (pci_intr_map(pa, &intrhandle) != 0) { 346 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 347 "couldn't map native-PCI interrupt\n"); 348 goto bad; 349 } 350 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 351 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 352 intrhandle, IPL_BIO, pci_intr, sc); 353 if (sc->sc_pci_ih != NULL) { 354 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 355 "using %s for native-PCI interrupt\n", 356 intrstr ? intrstr : "unknown interrupt"); 357 } else { 358 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 359 "couldn't establish native-PCI interrupt"); 360 if (intrstr != NULL) 361 aprint_error(" at %s", intrstr); 362 aprint_error("\n"); 363 goto bad; 364 } 365 } 366 cp->ih = sc->sc_pci_ih; 367 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel), 368 PCI_MAPREG_TYPE_IO, 0, 369 &wdr->cmd_iot, &wdr->cmd_baseioh, NULL, &wdr->cmd_ios) != 0) { 370 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 371 "couldn't map %s channel cmd regs\n", cp->name); 372 goto bad; 373 } 374 375 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel), 376 PCI_MAPREG_TYPE_IO, 0, 377 &wdr->ctl_iot, &cp->ctl_baseioh, NULL, &cp->ctl_ios) != 0) { 378 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 379 "couldn't map %s channel ctl regs\n", cp->name); 380 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 381 goto bad; 382 } 383 /* 384 * In native mode, 4 bytes of I/O space are mapped for the control 385 * register, the control register is at offset 2. Pass the generic 386 * code a handle for only one byte at the right offset. 387 */ 388 if (bus_space_subregion(wdr->ctl_iot, cp->ctl_baseioh, 2, 1, 389 &wdr->ctl_ioh) != 0) { 390 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 391 "unable to subregion %s channel ctl regs\n", cp->name); 392 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 393 bus_space_unmap(wdr->cmd_iot, cp->ctl_baseioh, cp->ctl_ios); 394 goto bad; 395 } 396 397 for (i = 0; i < WDC_NREG; i++) { 398 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 399 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 400 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 401 "couldn't subregion %s channel cmd regs\n", 402 cp->name); 403 goto bad; 404 } 405 } 406 wdc_init_shadow_regs(wdc_cp); 407 wdr->data32iot = wdr->cmd_iot; 408 wdr->data32ioh = wdr->cmd_iohs[0]; 409 return; 410 411 bad: 412 cp->ata_channel.ch_flags |= ATACH_DISABLED; 413 return; 414 } 415 416 #if NATA_DMA 417 void 418 pciide_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 419 { 420 pcireg_t maptype; 421 bus_addr_t addr; 422 struct pciide_channel *pc; 423 int reg, chan; 424 bus_size_t size; 425 426 /* 427 * Map DMA registers 428 * 429 * Note that sc_dma_ok is the right variable to test to see if 430 * DMA can be done. If the interface doesn't support DMA, 431 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 432 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 433 * non-zero if the interface supports DMA and the registers 434 * could be mapped. 435 * 436 * XXX Note that despite the fact that the Bus Master IDE specs 437 * XXX say that "The bus master IDE function uses 16 bytes of IO 438 * XXX space," some controllers (at least the United 439 * XXX Microelectronics UM8886BF) place it in memory space. 440 */ 441 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 442 PCIIDE_REG_BUS_MASTER_DMA); 443 444 switch (maptype) { 445 case PCI_MAPREG_TYPE_IO: 446 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 447 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 448 &addr, NULL, NULL) == 0); 449 if (sc->sc_dma_ok == 0) { 450 aprint_verbose( 451 ", but unused (couldn't query registers)"); 452 break; 453 } 454 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 455 && addr >= 0x10000) { 456 sc->sc_dma_ok = 0; 457 aprint_verbose( 458 ", but unused (registers at unsafe address " 459 "%#lx)", (unsigned long)addr); 460 break; 461 } 462 /* FALLTHROUGH */ 463 464 case PCI_MAPREG_MEM_TYPE_32BIT: 465 sc->sc_dma_ok = (pci_mapreg_map(pa, 466 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 467 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios) 468 == 0); 469 sc->sc_dmat = pa->pa_dmat; 470 if (sc->sc_dma_ok == 0) { 471 aprint_verbose(", but unused (couldn't map registers)"); 472 } else { 473 sc->sc_wdcdev.dma_arg = sc; 474 sc->sc_wdcdev.dma_init = pciide_dma_init; 475 sc->sc_wdcdev.dma_start = pciide_dma_start; 476 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 477 } 478 479 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 480 PCIIDE_OPTIONS_NODMA) { 481 aprint_verbose( 482 ", but unused (forced off by config file)"); 483 sc->sc_dma_ok = 0; 484 } 485 break; 486 487 default: 488 sc->sc_dma_ok = 0; 489 aprint_verbose( 490 ", but unsupported register maptype (0x%x)", maptype); 491 } 492 493 if (sc->sc_dma_ok == 0) 494 return; 495 496 /* 497 * Set up the default handles for the DMA registers. 498 * Just reserve 32 bits for each handle, unless space 499 * doesn't permit it. 500 */ 501 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { 502 pc = &sc->pciide_channels[chan]; 503 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 504 size = 4; 505 if (size > (IDEDMA_SCH_OFFSET - reg)) 506 size = IDEDMA_SCH_OFFSET - reg; 507 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 508 IDEDMA_SCH_OFFSET * chan + reg, size, 509 &pc->dma_iohs[reg]) != 0) { 510 sc->sc_dma_ok = 0; 511 aprint_verbose(", but can't subregion offset %d " 512 "size %lu", reg, (u_long)size); 513 return; 514 } 515 } 516 } 517 } 518 #endif /* NATA_DMA */ 519 520 int 521 pciide_compat_intr(void *arg) 522 { 523 struct pciide_channel *cp = arg; 524 525 #ifdef DIAGNOSTIC 526 /* should only be called for a compat channel */ 527 if (cp->compat == 0) 528 panic("pciide compat intr called for non-compat chan %p", cp); 529 #endif 530 return (wdcintr(&cp->ata_channel)); 531 } 532 533 int 534 pciide_pci_intr(void *arg) 535 { 536 struct pciide_softc *sc = arg; 537 struct pciide_channel *cp; 538 struct ata_channel *wdc_cp; 539 int i, rv, crv; 540 541 rv = 0; 542 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 543 cp = &sc->pciide_channels[i]; 544 wdc_cp = &cp->ata_channel; 545 546 /* If a compat channel skip. */ 547 if (cp->compat) 548 continue; 549 /* if this channel not waiting for intr, skip */ 550 if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0) 551 continue; 552 553 crv = wdcintr(wdc_cp); 554 if (crv == 0) 555 ; /* leave rv alone */ 556 else if (crv == 1) 557 rv = 1; /* claim the intr */ 558 else if (rv == 0) /* crv should be -1 in this case */ 559 rv = crv; /* if we've done no better, take it */ 560 } 561 return (rv); 562 } 563 564 #if NATA_DMA 565 void 566 pciide_channel_dma_setup(struct pciide_channel *cp) 567 { 568 int drive, s; 569 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 570 struct ata_drive_datas *drvp; 571 572 KASSERT(cp->ata_channel.ch_ndrive != 0); 573 574 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 575 drvp = &cp->ata_channel.ch_drive[drive]; 576 /* If no drive, skip */ 577 if ((drvp->drive_flags & DRIVE) == 0) 578 continue; 579 /* setup DMA if needed */ 580 if (((drvp->drive_flags & DRIVE_DMA) == 0 && 581 (drvp->drive_flags & DRIVE_UDMA) == 0) || 582 sc->sc_dma_ok == 0) { 583 s = splbio(); 584 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 585 splx(s); 586 continue; 587 } 588 if (pciide_dma_table_setup(sc, cp->ata_channel.ch_channel, 589 drive) != 0) { 590 /* Abort DMA setup */ 591 s = splbio(); 592 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 593 splx(s); 594 continue; 595 } 596 } 597 } 598 599 #define NIDEDMA_TABLES(sc) \ 600 (MAXPHYS/(min((sc)->sc_dma_maxsegsz, PAGE_SIZE)) + 1) 601 602 int 603 pciide_dma_table_setup(struct pciide_softc *sc, int channel, int drive) 604 { 605 int error; 606 const bus_size_t dma_table_size = 607 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc); 608 struct pciide_dma_maps *dma_maps = 609 &sc->pciide_channels[channel].dma_maps[drive]; 610 611 /* If table was already allocated, just return */ 612 if (dma_maps->dma_table) 613 return 0; 614 615 /* Allocate memory for the DMA tables and map it */ 616 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 617 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &dma_maps->dmamap_table_seg, 618 1, &dma_maps->dmamap_table_nseg, BUS_DMA_NOWAIT)) != 0) { 619 aprint_error(dmaerrfmt, 620 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 621 "allocate", drive, error); 622 return error; 623 } 624 if ((error = bus_dmamem_map(sc->sc_dmat, &dma_maps->dmamap_table_seg, 625 dma_maps->dmamap_table_nseg, dma_table_size, 626 (void **)&dma_maps->dma_table, 627 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 628 aprint_error(dmaerrfmt, 629 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 630 "map", drive, error); 631 return error; 632 } 633 ATADEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 634 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 635 (unsigned long)dma_maps->dmamap_table_seg.ds_addr), DEBUG_PROBE); 636 /* Create and load table DMA map for this disk */ 637 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 638 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 639 &dma_maps->dmamap_table)) != 0) { 640 aprint_error(dmaerrfmt, 641 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 642 "create", drive, error); 643 return error; 644 } 645 if ((error = bus_dmamap_load(sc->sc_dmat, 646 dma_maps->dmamap_table, 647 dma_maps->dma_table, 648 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 649 aprint_error(dmaerrfmt, 650 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 651 "load", drive, error); 652 return error; 653 } 654 ATADEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 655 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 656 DEBUG_PROBE); 657 /* Create a xfer DMA map for this drive */ 658 if ((error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 659 NIDEDMA_TABLES(sc), sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 660 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 661 &dma_maps->dmamap_xfer)) != 0) { 662 aprint_error(dmaerrfmt, 663 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 664 "create xfer", drive, error); 665 return error; 666 } 667 return 0; 668 } 669 670 void 671 pciide_dma_table_teardown(struct pciide_softc *sc, int channel, int drive) 672 { 673 struct pciide_channel *cp; 674 struct pciide_dma_maps *dma_maps; 675 676 cp = &sc->pciide_channels[channel]; 677 dma_maps = &cp->dma_maps[drive]; 678 679 if (dma_maps->dma_table == NULL) 680 return; 681 682 bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_xfer); 683 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_table); 684 bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_table); 685 bus_dmamem_unmap(sc->sc_dmat, dma_maps->dma_table, 686 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc)); 687 bus_dmamem_free(sc->sc_dmat, &dma_maps->dmamap_table_seg, 688 dma_maps->dmamap_table_nseg); 689 690 dma_maps->dma_table = NULL; 691 692 return; 693 } 694 695 int 696 pciide_dma_dmamap_setup(struct pciide_softc *sc, int channel, int drive, void *databuf, size_t datalen, int flags) 697 { 698 int error, seg; 699 struct pciide_channel *cp = &sc->pciide_channels[channel]; 700 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 701 702 error = bus_dmamap_load(sc->sc_dmat, 703 dma_maps->dmamap_xfer, 704 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 705 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 706 if (error) { 707 aprint_error(dmaerrfmt, 708 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 709 "load xfer", drive, error); 710 return error; 711 } 712 713 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 714 dma_maps->dmamap_xfer->dm_mapsize, 715 (flags & WDC_DMA_READ) ? 716 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 717 718 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 719 #ifdef DIAGNOSTIC 720 /* A segment must not cross a 64k boundary */ 721 { 722 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 723 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 724 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 725 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 726 printf("pciide_dma: segment %d physical addr 0x%lx" 727 " len 0x%lx not properly aligned\n", 728 seg, phys, len); 729 panic("pciide_dma: buf align"); 730 } 731 } 732 #endif 733 dma_maps->dma_table[seg].base_addr = 734 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 735 dma_maps->dma_table[seg].byte_count = 736 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 737 IDEDMA_BYTE_COUNT_MASK); 738 ATADEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 739 seg, le32toh(dma_maps->dma_table[seg].byte_count), 740 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 741 742 } 743 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 744 htole32(IDEDMA_BYTE_COUNT_EOT); 745 746 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 747 dma_maps->dmamap_table->dm_mapsize, 748 BUS_DMASYNC_PREWRITE); 749 750 #ifdef DIAGNOSTIC 751 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 752 printf("pciide_dma_dmamap_setup: addr 0x%lx " 753 "not properly aligned\n", 754 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 755 panic("pciide_dma_init: table align"); 756 } 757 #endif 758 /* remember flags */ 759 dma_maps->dma_flags = flags; 760 761 return 0; 762 } 763 764 int 765 pciide_dma_init(void *v, int channel, int drive, void *databuf, size_t datalen, int flags) 766 { 767 struct pciide_softc *sc = v; 768 int error; 769 struct pciide_channel *cp = &sc->pciide_channels[channel]; 770 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 771 772 if ((error = pciide_dma_dmamap_setup(sc, channel, drive, 773 databuf, datalen, flags)) != 0) 774 return error; 775 /* Maps are ready. Start DMA function */ 776 /* Clear status bits */ 777 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 778 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 779 /* Write table addr */ 780 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 781 dma_maps->dmamap_table->dm_segs[0].ds_addr); 782 /* set read/write */ 783 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 784 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 785 return 0; 786 } 787 788 void 789 pciide_dma_start(void *v, int channel, int drive) 790 { 791 struct pciide_softc *sc = v; 792 struct pciide_channel *cp = &sc->pciide_channels[channel]; 793 794 ATADEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 795 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 796 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 797 | IDEDMA_CMD_START); 798 } 799 800 int 801 pciide_dma_finish(void *v, int channel, int drive, int force) 802 { 803 struct pciide_softc *sc = v; 804 u_int8_t status; 805 int error = 0; 806 struct pciide_channel *cp = &sc->pciide_channels[channel]; 807 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 808 809 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0); 810 ATADEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 811 DEBUG_XFERS); 812 813 if (force == WDC_DMAEND_END && (status & IDEDMA_CTL_INTR) == 0) 814 return WDC_DMAST_NOIRQ; 815 816 /* stop DMA channel */ 817 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 818 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 819 & ~IDEDMA_CMD_START); 820 821 /* Unload the map of the data buffer */ 822 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 823 dma_maps->dmamap_xfer->dm_mapsize, 824 (dma_maps->dma_flags & WDC_DMA_READ) ? 825 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 826 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 827 828 if ((status & IDEDMA_CTL_ERR) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 829 aprint_error("%s:%d:%d: bus-master DMA error: status=0x%x\n", 830 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 831 drive, status); 832 error |= WDC_DMAST_ERR; 833 } 834 835 if ((status & IDEDMA_CTL_INTR) == 0 && force != WDC_DMAEND_ABRT_QUIET) { 836 aprint_error("%s:%d:%d: bus-master DMA error: missing " 837 "interrupt, status=0x%x\n", 838 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 839 channel, drive, status); 840 error |= WDC_DMAST_NOIRQ; 841 } 842 843 if ((status & IDEDMA_CTL_ACT) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 844 /* data underrun, may be a valid condition for ATAPI */ 845 error |= WDC_DMAST_UNDER; 846 } 847 return error; 848 } 849 850 void 851 pciide_irqack(struct ata_channel *chp) 852 { 853 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 854 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 855 856 /* clear status bits in IDE DMA registers */ 857 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 858 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 859 } 860 #endif /* NATA_DMA */ 861 862 /* some common code used by several chip_map */ 863 int 864 pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface) 865 { 866 struct pciide_channel *cp = &sc->pciide_channels[channel]; 867 sc->wdc_chanarray[channel] = &cp->ata_channel; 868 cp->name = PCIIDE_CHANNEL_NAME(channel); 869 cp->ata_channel.ch_channel = channel; 870 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 871 cp->ata_channel.ch_queue = 872 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 873 if (cp->ata_channel.ch_queue == NULL) { 874 aprint_error("%s %s channel: " 875 "can't allocate memory for command queue", 876 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 877 return 0; 878 } 879 cp->ata_channel.ch_ndrive = 2; 880 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 881 "%s channel %s to %s mode\n", cp->name, 882 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 883 "configured" : "wired", 884 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 885 "native-PCI" : "compatibility"); 886 return 1; 887 } 888 889 /* some common code used by several chip channel_map */ 890 void 891 pciide_mapchan(const struct pci_attach_args *pa, 892 struct pciide_channel *cp, 893 pcireg_t interface, int (*pci_intr)(void *)) 894 { 895 struct ata_channel *wdc_cp = &cp->ata_channel; 896 897 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) 898 pciide_mapregs_native(pa, cp, pci_intr); 899 else { 900 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 901 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 902 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 903 } 904 wdcattach(wdc_cp); 905 } 906 907 /* 908 * generic code to map the compat intr. 909 */ 910 void 911 pciide_map_compat_intr(const struct pci_attach_args *pa, struct pciide_channel *cp, int compatchan) 912 { 913 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 914 915 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 916 cp->ih = 917 pciide_machdep_compat_intr_establish(sc->sc_wdcdev.sc_atac.atac_dev, 918 pa, compatchan, pciide_compat_intr, cp); 919 if (cp->ih == NULL) { 920 #endif 921 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 922 "no compatibility interrupt for use by %s " 923 "channel\n", cp->name); 924 cp->ata_channel.ch_flags |= ATACH_DISABLED; 925 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 926 } 927 #endif 928 } 929 930 void 931 pciide_unmap_compat_intr(pci_chipset_tag_t pc, struct pciide_channel *cp, int compatchan) 932 { 933 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH 934 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 935 936 pciide_machdep_compat_intr_disestablish(sc->sc_wdcdev.sc_atac.atac_dev, 937 sc->sc_pc, compatchan, cp->ih); 938 #endif 939 } 940 941 void 942 default_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 943 { 944 struct pciide_channel *cp; 945 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 946 pcireg_t csr; 947 int channel; 948 #if NATA_DMA 949 int drive; 950 u_int8_t idedma_ctl; 951 #endif 952 const char *failreason; 953 struct wdc_regs *wdr; 954 955 if (pciide_chipen(sc, pa) == 0) 956 return; 957 958 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 959 #if NATA_DMA 960 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 961 "bus-master DMA support present"); 962 if (sc->sc_pp == &default_product_desc && 963 (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 964 PCIIDE_OPTIONS_DMA) == 0) { 965 aprint_verbose(", but unused (no driver support)"); 966 sc->sc_dma_ok = 0; 967 } else { 968 pciide_mapreg_dma(sc, pa); 969 if (sc->sc_dma_ok != 0) 970 aprint_verbose(", used without full driver " 971 "support"); 972 } 973 #else 974 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 975 "bus-master DMA support present, but unused (no driver " 976 "support)"); 977 #endif /* NATA_DMA */ 978 } else { 979 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 980 "hardware does not support DMA"); 981 #if NATA_DMA 982 sc->sc_dma_ok = 0; 983 #endif 984 } 985 aprint_verbose("\n"); 986 #if NATA_DMA 987 if (sc->sc_dma_ok) { 988 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 989 sc->sc_wdcdev.irqack = pciide_irqack; 990 } 991 #endif 992 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 993 #if NATA_DMA 994 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 995 #endif 996 997 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 998 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 999 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 1000 1001 wdc_allocate_regs(&sc->sc_wdcdev); 1002 1003 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1004 channel++) { 1005 cp = &sc->pciide_channels[channel]; 1006 if (pciide_chansetup(sc, channel, interface) == 0) 1007 continue; 1008 wdr = CHAN_TO_WDC_REGS(&cp->ata_channel); 1009 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1010 pciide_mapregs_native(pa, cp, pciide_pci_intr); 1011 else 1012 pciide_mapregs_compat(pa, cp, 1013 cp->ata_channel.ch_channel); 1014 if (cp->ata_channel.ch_flags & ATACH_DISABLED) 1015 continue; 1016 /* 1017 * Check to see if something appears to be there. 1018 */ 1019 failreason = NULL; 1020 /* 1021 * In native mode, always enable the controller. It's 1022 * not possible to have an ISA board using the same address 1023 * anyway. 1024 */ 1025 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1026 wdcattach(&cp->ata_channel); 1027 continue; 1028 } 1029 if (!wdcprobe(&cp->ata_channel)) { 1030 failreason = "not responding; disabled or no drives?"; 1031 goto next; 1032 } 1033 /* 1034 * Now, make sure it's actually attributable to this PCI IDE 1035 * channel by trying to access the channel again while the 1036 * PCI IDE controller's I/O space is disabled. (If the 1037 * channel no longer appears to be there, it belongs to 1038 * this controller.) YUCK! 1039 */ 1040 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1041 PCI_COMMAND_STATUS_REG); 1042 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1043 csr & ~PCI_COMMAND_IO_ENABLE); 1044 if (wdcprobe(&cp->ata_channel)) 1045 failreason = "other hardware responding at addresses"; 1046 pci_conf_write(sc->sc_pc, sc->sc_tag, 1047 PCI_COMMAND_STATUS_REG, csr); 1048 next: 1049 if (failreason) { 1050 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1051 "%s channel ignored (%s)\n", cp->name, failreason); 1052 cp->ata_channel.ch_flags |= ATACH_DISABLED; 1053 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 1054 wdr->cmd_ios); 1055 bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh, 1056 wdr->ctl_ios); 1057 } else { 1058 pciide_map_compat_intr(pa, cp, 1059 cp->ata_channel.ch_channel); 1060 wdcattach(&cp->ata_channel); 1061 } 1062 } 1063 1064 #if NATA_DMA 1065 if (sc->sc_dma_ok == 0) 1066 return; 1067 1068 /* Allocate DMA maps */ 1069 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1070 channel++) { 1071 idedma_ctl = 0; 1072 cp = &sc->pciide_channels[channel]; 1073 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 1074 /* 1075 * we have not probed the drives yet, allocate 1076 * ressources for all of them. 1077 */ 1078 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1079 /* Abort DMA setup */ 1080 aprint_error( 1081 "%s:%d:%d: can't allocate DMA maps, " 1082 "using PIO transfers\n", 1083 device_xname( 1084 sc->sc_wdcdev.sc_atac.atac_dev), 1085 channel, drive); 1086 sc->sc_dma_ok = 0; 1087 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA; 1088 sc->sc_wdcdev.irqack = NULL; 1089 break; 1090 } 1091 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1092 } 1093 if (idedma_ctl != 0) { 1094 /* Add software bits in status register */ 1095 bus_space_write_1(sc->sc_dma_iot, 1096 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 1097 } 1098 } 1099 #endif /* NATA_DMA */ 1100 } 1101 1102 void 1103 sata_setup_channel(struct ata_channel *chp) 1104 { 1105 #if NATA_DMA 1106 struct ata_drive_datas *drvp; 1107 int drive; 1108 #if NATA_UDMA 1109 int s; 1110 #endif 1111 u_int32_t idedma_ctl; 1112 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 1113 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 1114 1115 /* setup DMA if needed */ 1116 pciide_channel_dma_setup(cp); 1117 1118 idedma_ctl = 0; 1119 1120 for (drive = 0; drive < cp->ata_channel.ch_ndrive; drive++) { 1121 drvp = &chp->ch_drive[drive]; 1122 /* If no drive, skip */ 1123 if ((drvp->drive_flags & DRIVE) == 0) 1124 continue; 1125 #if NATA_UDMA 1126 if (drvp->drive_flags & DRIVE_UDMA) { 1127 /* use Ultra/DMA */ 1128 s = splbio(); 1129 drvp->drive_flags &= ~DRIVE_DMA; 1130 splx(s); 1131 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1132 } else 1133 #endif /* NATA_UDMA */ 1134 if (drvp->drive_flags & DRIVE_DMA) { 1135 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1136 } 1137 } 1138 1139 /* 1140 * Nothing to do to setup modes; it is meaningless in S-ATA 1141 * (but many S-ATA drives still want to get the SET_FEATURE 1142 * command). 1143 */ 1144 if (idedma_ctl != 0) { 1145 /* Add software bits in status register */ 1146 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 1147 idedma_ctl); 1148 } 1149 #endif /* NATA_DMA */ 1150 } 1151
Indexes created Thu Oct 02 07:10:07 GMT 2025