pciide_common.c revision 1.51.4.3
1 /* $NetBSD: pciide_common.c,v 1.51.4.3 2013/01/16 05:33:30 yamt Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 30 /* 31 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by Christopher G. Demetriou 44 * for the NetBSD Project. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * PCI IDE controller driver. 62 * 63 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 64 * sys/dev/pci/ppb.c, revision 1.16). 65 * 66 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 67 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 68 * 5/16/94" from the PCI SIG. 69 * 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.51.4.3 2013/01/16 05:33:30 yamt Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/malloc.h> 77 78 #include <dev/pci/pcireg.h> 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcidevs.h> 81 #include <dev/pci/pciidereg.h> 82 #include <dev/pci/pciidevar.h> 83 84 #include <dev/ic/wdcreg.h> 85 86 #ifdef ATADEBUG 87 int atadebug_pciide_mask = 0; 88 #endif 89 90 #if NATA_DMA 91 static const char dmaerrfmt[] = 92 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 93 #endif 94 95 /* Default product description for devices not known from this controller */ 96 const struct pciide_product_desc default_product_desc = { 97 0, 98 0, 99 "Generic PCI IDE controller", 100 default_chip_map, 101 }; 102 103 const struct pciide_product_desc * 104 pciide_lookup_product(pcireg_t id, const struct pciide_product_desc *pp) 105 { 106 for (; pp->chip_map != NULL; pp++) 107 if (PCI_PRODUCT(id) == pp->ide_product) 108 break; 109 110 if (pp->chip_map == NULL) 111 return NULL; 112 return pp; 113 } 114 115 void 116 pciide_common_attach(struct pciide_softc *sc, const struct pci_attach_args *pa, const struct pciide_product_desc *pp) 117 { 118 pci_chipset_tag_t pc = pa->pa_pc; 119 pcitag_t tag = pa->pa_tag; 120 #if NATA_DMA 121 pcireg_t csr; 122 #endif 123 const char *displaydev = NULL; 124 int dontprint = 0; 125 126 sc->sc_pci_id = pa->pa_id; 127 if (pp == NULL) { 128 /* should only happen for generic pciide devices */ 129 sc->sc_pp = &default_product_desc; 130 } else { 131 sc->sc_pp = pp; 132 /* if ide_name == NULL, printf is done in chip-specific map */ 133 if (pp->ide_name) 134 displaydev = pp->ide_name; 135 else 136 dontprint = 1; 137 } 138 139 if (dontprint) { 140 aprint_naive("disk controller\n"); 141 aprint_normal("\n"); /* ??? */ 142 } else 143 pci_aprint_devinfo_fancy(pa, "disk controller", displaydev, 1); 144 145 sc->sc_pc = pa->pa_pc; 146 sc->sc_tag = pa->pa_tag; 147 148 #if NATA_DMA 149 /* Set up DMA defaults; these might be adjusted by chip_map. */ 150 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 151 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 152 #endif 153 154 #ifdef ATADEBUG 155 if (atadebug_pciide_mask & DEBUG_PROBE) 156 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 157 #endif 158 sc->sc_pp->chip_map(sc, pa); 159 160 #if NATA_DMA 161 if (sc->sc_dma_ok) { 162 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 163 csr |= PCI_COMMAND_MASTER_ENABLE; 164 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 165 } 166 #endif 167 ATADEBUG_PRINT(("pciide: command/status register=%x\n", 168 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 169 } 170 171 int 172 pciide_common_detach(struct pciide_softc *sc, int flags) 173 { 174 struct pciide_channel *cp; 175 struct ata_channel *wdc_cp; 176 struct wdc_regs *wdr; 177 int channel, drive; 178 int rv; 179 180 rv = wdcdetach(sc->sc_wdcdev.sc_atac.atac_dev, flags); 181 if (rv) 182 return rv; 183 184 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 185 channel++) { 186 cp = &sc->pciide_channels[channel]; 187 wdc_cp = &cp->ata_channel; 188 wdr = CHAN_TO_WDC_REGS(wdc_cp); 189 190 if (wdc_cp->ch_flags & ATACH_DISABLED) 191 continue; 192 193 if (wdr->cmd_ios != 0) 194 bus_space_unmap(wdr->cmd_iot, 195 wdr->cmd_baseioh, wdr->cmd_ios); 196 if (cp->compat != 0) { 197 if (wdr->ctl_ios != 0) 198 bus_space_unmap(wdr->ctl_iot, 199 wdr->ctl_ioh, wdr->ctl_ios); 200 } else { 201 if (cp->ctl_ios != 0) 202 bus_space_unmap(wdr->ctl_iot, 203 cp->ctl_baseioh, cp->ctl_ios); 204 } 205 206 for (drive = 0; drive < sc->sc_wdcdev.wdc_maxdrives; drive++) { 207 #if NATA_DMA 208 pciide_dma_table_teardown(sc, channel, drive); 209 #endif 210 } 211 212 free(cp->ata_channel.ch_queue, M_DEVBUF); 213 cp->ata_channel.atabus = NULL; 214 } 215 216 #if NATA_DMA 217 if (sc->sc_dma_ios != 0) 218 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios); 219 if (sc->sc_ba5_ss != 0) 220 bus_space_unmap(sc->sc_ba5_st, sc->sc_ba5_sh, sc->sc_ba5_ss); 221 #endif 222 223 return 0; 224 } 225 226 int 227 pciide_detach(device_t self, int flags) 228 { 229 struct pciide_softc *sc = device_private(self); 230 struct pciide_channel *cp; 231 int channel; 232 #ifndef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH 233 bool has_compat_chan; 234 235 has_compat_chan = false; 236 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 237 channel++) { 238 cp = &sc->pciide_channels[channel]; 239 if (cp->compat != 0) { 240 has_compat_chan = true; 241 } 242 } 243 244 if (has_compat_chan != false) 245 return EBUSY; 246 #endif 247 248 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 249 channel++) { 250 cp = &sc->pciide_channels[channel]; 251 if (cp->compat != 0) 252 if (cp->ih != NULL) { 253 pciide_unmap_compat_intr(sc->sc_pc, cp, channel); 254 cp->ih = NULL; 255 } 256 } 257 258 if (sc->sc_pci_ih != NULL) { 259 pci_intr_disestablish(sc->sc_pc, sc->sc_pci_ih); 260 sc->sc_pci_ih = NULL; 261 } 262 263 return pciide_common_detach(sc, flags); 264 } 265 266 /* tell whether the chip is enabled or not */ 267 int 268 pciide_chipen(struct pciide_softc *sc, const struct pci_attach_args *pa) 269 { 270 pcireg_t csr; 271 272 if ((pa->pa_flags & PCI_FLAGS_IO_OKAY) == 0) { 273 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 274 "I/O access disabled at bridge\n"); 275 return 0; 276 } 277 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 278 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) { 279 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 280 "I/O access disabled at device\n"); 281 return 0; 282 } 283 return 1; 284 } 285 286 void 287 pciide_mapregs_compat(const struct pci_attach_args *pa, struct pciide_channel *cp, int compatchan) 288 { 289 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 290 struct ata_channel *wdc_cp = &cp->ata_channel; 291 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 292 int i; 293 294 cp->compat = 1; 295 296 wdr->cmd_iot = pa->pa_iot; 297 if (bus_space_map(wdr->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 298 PCIIDE_COMPAT_CMD_SIZE, 0, &wdr->cmd_baseioh) != 0) { 299 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 300 "couldn't map %s channel cmd regs\n", cp->name); 301 goto bad; 302 } 303 wdr->cmd_ios = PCIIDE_COMPAT_CMD_SIZE; 304 305 wdr->ctl_iot = pa->pa_iot; 306 if (bus_space_map(wdr->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 307 PCIIDE_COMPAT_CTL_SIZE, 0, &wdr->ctl_ioh) != 0) { 308 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 309 "couldn't map %s channel ctl regs\n", cp->name); 310 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 311 goto bad; 312 } 313 wdr->ctl_ios = PCIIDE_COMPAT_CTL_SIZE; 314 315 for (i = 0; i < WDC_NREG; i++) { 316 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 317 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 318 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 319 "couldn't subregion %s channel cmd regs\n", 320 cp->name); 321 goto bad; 322 } 323 } 324 wdc_init_shadow_regs(wdc_cp); 325 wdr->data32iot = wdr->cmd_iot; 326 wdr->data32ioh = wdr->cmd_iohs[0]; 327 return; 328 329 bad: 330 cp->ata_channel.ch_flags |= ATACH_DISABLED; 331 return; 332 } 333 334 void 335 pciide_mapregs_native(const struct pci_attach_args *pa, 336 struct pciide_channel *cp, int (*pci_intr)(void *)) 337 { 338 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 339 struct ata_channel *wdc_cp = &cp->ata_channel; 340 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 341 const char *intrstr; 342 pci_intr_handle_t intrhandle; 343 int i; 344 345 cp->compat = 0; 346 347 if (sc->sc_pci_ih == NULL) { 348 if (pci_intr_map(pa, &intrhandle) != 0) { 349 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 350 "couldn't map native-PCI interrupt\n"); 351 goto bad; 352 } 353 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 354 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 355 intrhandle, IPL_BIO, pci_intr, sc); 356 if (sc->sc_pci_ih != NULL) { 357 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 358 "using %s for native-PCI interrupt\n", 359 intrstr ? intrstr : "unknown interrupt"); 360 } else { 361 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 362 "couldn't establish native-PCI interrupt"); 363 if (intrstr != NULL) 364 aprint_error(" at %s", intrstr); 365 aprint_error("\n"); 366 goto bad; 367 } 368 } 369 cp->ih = sc->sc_pci_ih; 370 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel), 371 PCI_MAPREG_TYPE_IO, 0, 372 &wdr->cmd_iot, &wdr->cmd_baseioh, NULL, &wdr->cmd_ios) != 0) { 373 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 374 "couldn't map %s channel cmd regs\n", cp->name); 375 goto bad; 376 } 377 378 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel), 379 PCI_MAPREG_TYPE_IO, 0, 380 &wdr->ctl_iot, &cp->ctl_baseioh, NULL, &cp->ctl_ios) != 0) { 381 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 382 "couldn't map %s channel ctl regs\n", cp->name); 383 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 384 goto bad; 385 } 386 /* 387 * In native mode, 4 bytes of I/O space are mapped for the control 388 * register, the control register is at offset 2. Pass the generic 389 * code a handle for only one byte at the right offset. 390 */ 391 if (bus_space_subregion(wdr->ctl_iot, cp->ctl_baseioh, 2, 1, 392 &wdr->ctl_ioh) != 0) { 393 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 394 "unable to subregion %s channel ctl regs\n", cp->name); 395 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 396 bus_space_unmap(wdr->cmd_iot, cp->ctl_baseioh, cp->ctl_ios); 397 goto bad; 398 } 399 400 for (i = 0; i < WDC_NREG; i++) { 401 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 402 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 403 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 404 "couldn't subregion %s channel cmd regs\n", 405 cp->name); 406 goto bad; 407 } 408 } 409 wdc_init_shadow_regs(wdc_cp); 410 wdr->data32iot = wdr->cmd_iot; 411 wdr->data32ioh = wdr->cmd_iohs[0]; 412 return; 413 414 bad: 415 cp->ata_channel.ch_flags |= ATACH_DISABLED; 416 return; 417 } 418 419 #if NATA_DMA 420 void 421 pciide_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 422 { 423 pcireg_t maptype; 424 bus_addr_t addr; 425 struct pciide_channel *pc; 426 int reg, chan; 427 bus_size_t size; 428 429 /* 430 * Map DMA registers 431 * 432 * Note that sc_dma_ok is the right variable to test to see if 433 * DMA can be done. If the interface doesn't support DMA, 434 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 435 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 436 * non-zero if the interface supports DMA and the registers 437 * could be mapped. 438 * 439 * XXX Note that despite the fact that the Bus Master IDE specs 440 * XXX say that "The bus master IDE function uses 16 bytes of IO 441 * XXX space," some controllers (at least the United 442 * XXX Microelectronics UM8886BF) place it in memory space. 443 */ 444 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 445 PCIIDE_REG_BUS_MASTER_DMA); 446 447 switch (maptype) { 448 case PCI_MAPREG_TYPE_IO: 449 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 450 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 451 &addr, NULL, NULL) == 0); 452 if (sc->sc_dma_ok == 0) { 453 aprint_verbose( 454 ", but unused (couldn't query registers)"); 455 break; 456 } 457 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 458 && addr >= 0x10000) { 459 sc->sc_dma_ok = 0; 460 aprint_verbose( 461 ", but unused (registers at unsafe address " 462 "%#lx)", (unsigned long)addr); 463 break; 464 } 465 /* FALLTHROUGH */ 466 467 case PCI_MAPREG_MEM_TYPE_32BIT: 468 sc->sc_dma_ok = (pci_mapreg_map(pa, 469 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 470 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios) 471 == 0); 472 sc->sc_dmat = pa->pa_dmat; 473 if (sc->sc_dma_ok == 0) { 474 aprint_verbose(", but unused (couldn't map registers)"); 475 } else { 476 sc->sc_wdcdev.dma_arg = sc; 477 sc->sc_wdcdev.dma_init = pciide_dma_init; 478 sc->sc_wdcdev.dma_start = pciide_dma_start; 479 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 480 } 481 482 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 483 PCIIDE_OPTIONS_NODMA) { 484 aprint_verbose( 485 ", but unused (forced off by config file)"); 486 sc->sc_dma_ok = 0; 487 } 488 break; 489 490 default: 491 sc->sc_dma_ok = 0; 492 aprint_verbose( 493 ", but unsupported register maptype (0x%x)", maptype); 494 } 495 496 if (sc->sc_dma_ok == 0) 497 return; 498 499 /* 500 * Set up the default handles for the DMA registers. 501 * Just reserve 32 bits for each handle, unless space 502 * doesn't permit it. 503 */ 504 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { 505 pc = &sc->pciide_channels[chan]; 506 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 507 size = 4; 508 if (size > (IDEDMA_SCH_OFFSET - reg)) 509 size = IDEDMA_SCH_OFFSET - reg; 510 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 511 IDEDMA_SCH_OFFSET * chan + reg, size, 512 &pc->dma_iohs[reg]) != 0) { 513 sc->sc_dma_ok = 0; 514 aprint_verbose(", but can't subregion offset %d " 515 "size %lu", reg, (u_long)size); 516 return; 517 } 518 } 519 } 520 } 521 #endif /* NATA_DMA */ 522 523 int 524 pciide_compat_intr(void *arg) 525 { 526 struct pciide_channel *cp = arg; 527 528 #ifdef DIAGNOSTIC 529 /* should only be called for a compat channel */ 530 if (cp->compat == 0) 531 panic("pciide compat intr called for non-compat chan %p", cp); 532 #endif 533 return (wdcintr(&cp->ata_channel)); 534 } 535 536 int 537 pciide_pci_intr(void *arg) 538 { 539 struct pciide_softc *sc = arg; 540 struct pciide_channel *cp; 541 struct ata_channel *wdc_cp; 542 int i, rv, crv; 543 544 rv = 0; 545 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 546 cp = &sc->pciide_channels[i]; 547 wdc_cp = &cp->ata_channel; 548 549 /* If a compat channel skip. */ 550 if (cp->compat) 551 continue; 552 /* if this channel not waiting for intr, skip */ 553 if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0) 554 continue; 555 556 crv = wdcintr(wdc_cp); 557 if (crv == 0) 558 ; /* leave rv alone */ 559 else if (crv == 1) 560 rv = 1; /* claim the intr */ 561 else if (rv == 0) /* crv should be -1 in this case */ 562 rv = crv; /* if we've done no better, take it */ 563 } 564 return (rv); 565 } 566 567 #if NATA_DMA 568 void 569 pciide_channel_dma_setup(struct pciide_channel *cp) 570 { 571 int drive, s; 572 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 573 struct ata_drive_datas *drvp; 574 575 KASSERT(cp->ata_channel.ch_ndrives != 0); 576 577 for (drive = 0; drive < cp->ata_channel.ch_ndrives; drive++) { 578 drvp = &cp->ata_channel.ch_drive[drive]; 579 /* If no drive, skip */ 580 if (drvp->drive_type == ATA_DRIVET_NONE) 581 continue; 582 /* setup DMA if needed */ 583 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 584 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0) || 585 sc->sc_dma_ok == 0) { 586 s = splbio(); 587 drvp->drive_flags &= ~(ATA_DRIVE_DMA | ATA_DRIVE_UDMA); 588 splx(s); 589 continue; 590 } 591 if (pciide_dma_table_setup(sc, cp->ata_channel.ch_channel, 592 drive) != 0) { 593 /* Abort DMA setup */ 594 s = splbio(); 595 drvp->drive_flags &= ~(ATA_DRIVE_DMA | ATA_DRIVE_UDMA); 596 splx(s); 597 continue; 598 } 599 } 600 } 601 602 #define NIDEDMA_TABLES(sc) \ 603 (MAXPHYS/(min((sc)->sc_dma_maxsegsz, PAGE_SIZE)) + 1) 604 605 int 606 pciide_dma_table_setup(struct pciide_softc *sc, int channel, int drive) 607 { 608 int error; 609 const bus_size_t dma_table_size = 610 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc); 611 struct pciide_dma_maps *dma_maps = 612 &sc->pciide_channels[channel].dma_maps[drive]; 613 614 /* If table was already allocated, just return */ 615 if (dma_maps->dma_table) 616 return 0; 617 618 /* Allocate memory for the DMA tables and map it */ 619 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 620 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &dma_maps->dmamap_table_seg, 621 1, &dma_maps->dmamap_table_nseg, BUS_DMA_NOWAIT)) != 0) { 622 aprint_error(dmaerrfmt, 623 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 624 "allocate", drive, error); 625 return error; 626 } 627 if ((error = bus_dmamem_map(sc->sc_dmat, &dma_maps->dmamap_table_seg, 628 dma_maps->dmamap_table_nseg, dma_table_size, 629 (void **)&dma_maps->dma_table, 630 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 631 aprint_error(dmaerrfmt, 632 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 633 "map", drive, error); 634 return error; 635 } 636 ATADEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 637 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 638 (unsigned long)dma_maps->dmamap_table_seg.ds_addr), DEBUG_PROBE); 639 /* Create and load table DMA map for this disk */ 640 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 641 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 642 &dma_maps->dmamap_table)) != 0) { 643 aprint_error(dmaerrfmt, 644 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 645 "create", drive, error); 646 return error; 647 } 648 if ((error = bus_dmamap_load(sc->sc_dmat, 649 dma_maps->dmamap_table, 650 dma_maps->dma_table, 651 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 652 aprint_error(dmaerrfmt, 653 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 654 "load", drive, error); 655 return error; 656 } 657 ATADEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 658 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 659 DEBUG_PROBE); 660 /* Create a xfer DMA map for this drive */ 661 if ((error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 662 NIDEDMA_TABLES(sc), sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 663 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 664 &dma_maps->dmamap_xfer)) != 0) { 665 aprint_error(dmaerrfmt, 666 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 667 "create xfer", drive, error); 668 return error; 669 } 670 return 0; 671 } 672 673 void 674 pciide_dma_table_teardown(struct pciide_softc *sc, int channel, int drive) 675 { 676 struct pciide_channel *cp; 677 struct pciide_dma_maps *dma_maps; 678 679 cp = &sc->pciide_channels[channel]; 680 dma_maps = &cp->dma_maps[drive]; 681 682 if (dma_maps->dma_table == NULL) 683 return; 684 685 bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_xfer); 686 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_table); 687 bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_table); 688 bus_dmamem_unmap(sc->sc_dmat, dma_maps->dma_table, 689 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc)); 690 bus_dmamem_free(sc->sc_dmat, &dma_maps->dmamap_table_seg, 691 dma_maps->dmamap_table_nseg); 692 693 dma_maps->dma_table = NULL; 694 695 return; 696 } 697 698 int 699 pciide_dma_dmamap_setup(struct pciide_softc *sc, int channel, int drive, void *databuf, size_t datalen, int flags) 700 { 701 int error, seg; 702 struct pciide_channel *cp = &sc->pciide_channels[channel]; 703 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 704 705 error = bus_dmamap_load(sc->sc_dmat, 706 dma_maps->dmamap_xfer, 707 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 708 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 709 if (error) { 710 aprint_error(dmaerrfmt, 711 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 712 "load xfer", drive, error); 713 return error; 714 } 715 716 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 717 dma_maps->dmamap_xfer->dm_mapsize, 718 (flags & WDC_DMA_READ) ? 719 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 720 721 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 722 #ifdef DIAGNOSTIC 723 /* A segment must not cross a 64k boundary */ 724 { 725 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 726 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 727 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 728 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 729 printf("pciide_dma: segment %d physical addr 0x%lx" 730 " len 0x%lx not properly aligned\n", 731 seg, phys, len); 732 panic("pciide_dma: buf align"); 733 } 734 } 735 #endif 736 dma_maps->dma_table[seg].base_addr = 737 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 738 dma_maps->dma_table[seg].byte_count = 739 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 740 IDEDMA_BYTE_COUNT_MASK); 741 ATADEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 742 seg, le32toh(dma_maps->dma_table[seg].byte_count), 743 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 744 745 } 746 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 747 htole32(IDEDMA_BYTE_COUNT_EOT); 748 749 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 750 dma_maps->dmamap_table->dm_mapsize, 751 BUS_DMASYNC_PREWRITE); 752 753 #ifdef DIAGNOSTIC 754 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 755 printf("pciide_dma_dmamap_setup: addr 0x%lx " 756 "not properly aligned\n", 757 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 758 panic("pciide_dma_init: table align"); 759 } 760 #endif 761 /* remember flags */ 762 dma_maps->dma_flags = flags; 763 764 return 0; 765 } 766 767 int 768 pciide_dma_init(void *v, int channel, int drive, void *databuf, size_t datalen, int flags) 769 { 770 struct pciide_softc *sc = v; 771 int error; 772 struct pciide_channel *cp = &sc->pciide_channels[channel]; 773 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 774 775 if ((error = pciide_dma_dmamap_setup(sc, channel, drive, 776 databuf, datalen, flags)) != 0) 777 return error; 778 /* Maps are ready. Start DMA function */ 779 /* Clear status bits */ 780 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 781 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 782 /* Write table addr */ 783 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 784 dma_maps->dmamap_table->dm_segs[0].ds_addr); 785 /* set read/write */ 786 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 787 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 788 return 0; 789 } 790 791 void 792 pciide_dma_start(void *v, int channel, int drive) 793 { 794 struct pciide_softc *sc = v; 795 struct pciide_channel *cp = &sc->pciide_channels[channel]; 796 797 ATADEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 798 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 799 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 800 | IDEDMA_CMD_START); 801 } 802 803 int 804 pciide_dma_finish(void *v, int channel, int drive, int force) 805 { 806 struct pciide_softc *sc = v; 807 u_int8_t status; 808 int error = 0; 809 struct pciide_channel *cp = &sc->pciide_channels[channel]; 810 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 811 812 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0); 813 ATADEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 814 DEBUG_XFERS); 815 816 if (force == WDC_DMAEND_END && (status & IDEDMA_CTL_INTR) == 0) 817 return WDC_DMAST_NOIRQ; 818 819 /* stop DMA channel */ 820 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 821 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 822 & ~IDEDMA_CMD_START); 823 824 /* Unload the map of the data buffer */ 825 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 826 dma_maps->dmamap_xfer->dm_mapsize, 827 (dma_maps->dma_flags & WDC_DMA_READ) ? 828 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 829 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 830 831 if ((status & IDEDMA_CTL_ERR) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 832 aprint_error("%s:%d:%d: bus-master DMA error: status=0x%x\n", 833 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 834 drive, status); 835 error |= WDC_DMAST_ERR; 836 } 837 838 if ((status & IDEDMA_CTL_INTR) == 0 && force != WDC_DMAEND_ABRT_QUIET) { 839 aprint_error("%s:%d:%d: bus-master DMA error: missing " 840 "interrupt, status=0x%x\n", 841 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 842 channel, drive, status); 843 error |= WDC_DMAST_NOIRQ; 844 } 845 846 if ((status & IDEDMA_CTL_ACT) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 847 /* data underrun, may be a valid condition for ATAPI */ 848 error |= WDC_DMAST_UNDER; 849 } 850 return error; 851 } 852 853 void 854 pciide_irqack(struct ata_channel *chp) 855 { 856 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 857 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 858 859 /* clear status bits in IDE DMA registers */ 860 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 861 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 862 } 863 #endif /* NATA_DMA */ 864 865 /* some common code used by several chip_map */ 866 int 867 pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface) 868 { 869 struct pciide_channel *cp = &sc->pciide_channels[channel]; 870 sc->wdc_chanarray[channel] = &cp->ata_channel; 871 cp->name = PCIIDE_CHANNEL_NAME(channel); 872 cp->ata_channel.ch_channel = channel; 873 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 874 cp->ata_channel.ch_queue = 875 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 876 if (cp->ata_channel.ch_queue == NULL) { 877 aprint_error("%s %s channel: " 878 "can't allocate memory for command queue", 879 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 880 return 0; 881 } 882 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 883 "%s channel %s to %s mode\n", cp->name, 884 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 885 "configured" : "wired", 886 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 887 "native-PCI" : "compatibility"); 888 return 1; 889 } 890 891 /* some common code used by several chip channel_map */ 892 void 893 pciide_mapchan(const struct pci_attach_args *pa, 894 struct pciide_channel *cp, 895 pcireg_t interface, int (*pci_intr)(void *)) 896 { 897 struct ata_channel *wdc_cp = &cp->ata_channel; 898 899 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) 900 pciide_mapregs_native(pa, cp, pci_intr); 901 else { 902 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 903 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 904 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 905 } 906 wdcattach(wdc_cp); 907 } 908 909 /* 910 * generic code to map the compat intr. 911 */ 912 void 913 pciide_map_compat_intr(const struct pci_attach_args *pa, struct pciide_channel *cp, int compatchan) 914 { 915 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 916 917 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 918 cp->ih = 919 pciide_machdep_compat_intr_establish(sc->sc_wdcdev.sc_atac.atac_dev, 920 pa, compatchan, pciide_compat_intr, cp); 921 if (cp->ih == NULL) { 922 #endif 923 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 924 "no compatibility interrupt for use by %s " 925 "channel\n", cp->name); 926 cp->ata_channel.ch_flags |= ATACH_DISABLED; 927 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 928 } 929 #endif 930 } 931 932 void 933 pciide_unmap_compat_intr(pci_chipset_tag_t pc, struct pciide_channel *cp, int compatchan) 934 { 935 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH 936 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 937 938 pciide_machdep_compat_intr_disestablish(sc->sc_wdcdev.sc_atac.atac_dev, 939 sc->sc_pc, compatchan, cp->ih); 940 #endif 941 } 942 943 void 944 default_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 945 { 946 struct pciide_channel *cp; 947 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 948 pcireg_t csr; 949 int channel; 950 #if NATA_DMA 951 int drive; 952 u_int8_t idedma_ctl; 953 #endif 954 const char *failreason; 955 struct wdc_regs *wdr; 956 957 if (pciide_chipen(sc, pa) == 0) 958 return; 959 960 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 961 #if NATA_DMA 962 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 963 "bus-master DMA support present"); 964 if (sc->sc_pp == &default_product_desc && 965 (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 966 PCIIDE_OPTIONS_DMA) == 0) { 967 aprint_verbose(", but unused (no driver support)"); 968 sc->sc_dma_ok = 0; 969 } else { 970 pciide_mapreg_dma(sc, pa); 971 if (sc->sc_dma_ok != 0) 972 aprint_verbose(", used without full driver " 973 "support"); 974 } 975 #else 976 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 977 "bus-master DMA support present, but unused (no driver " 978 "support)"); 979 #endif /* NATA_DMA */ 980 } else { 981 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 982 "hardware does not support DMA"); 983 #if NATA_DMA 984 sc->sc_dma_ok = 0; 985 #endif 986 } 987 aprint_verbose("\n"); 988 #if NATA_DMA 989 if (sc->sc_dma_ok) { 990 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 991 sc->sc_wdcdev.irqack = pciide_irqack; 992 } 993 #endif 994 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 995 #if NATA_DMA 996 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 997 #endif 998 999 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 1000 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 1001 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 1002 sc->sc_wdcdev.wdc_maxdrives = 2; 1003 1004 wdc_allocate_regs(&sc->sc_wdcdev); 1005 1006 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1007 channel++) { 1008 cp = &sc->pciide_channels[channel]; 1009 if (pciide_chansetup(sc, channel, interface) == 0) 1010 continue; 1011 wdr = CHAN_TO_WDC_REGS(&cp->ata_channel); 1012 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1013 pciide_mapregs_native(pa, cp, pciide_pci_intr); 1014 else 1015 pciide_mapregs_compat(pa, cp, 1016 cp->ata_channel.ch_channel); 1017 if (cp->ata_channel.ch_flags & ATACH_DISABLED) 1018 continue; 1019 /* 1020 * Check to see if something appears to be there. 1021 */ 1022 failreason = NULL; 1023 /* 1024 * In native mode, always enable the controller. It's 1025 * not possible to have an ISA board using the same address 1026 * anyway. 1027 */ 1028 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1029 wdcattach(&cp->ata_channel); 1030 continue; 1031 } 1032 if (!wdcprobe(&cp->ata_channel)) { 1033 failreason = "not responding; disabled or no drives?"; 1034 goto next; 1035 } 1036 /* 1037 * Now, make sure it's actually attributable to this PCI IDE 1038 * channel by trying to access the channel again while the 1039 * PCI IDE controller's I/O space is disabled. (If the 1040 * channel no longer appears to be there, it belongs to 1041 * this controller.) YUCK! 1042 */ 1043 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1044 PCI_COMMAND_STATUS_REG); 1045 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1046 csr & ~PCI_COMMAND_IO_ENABLE); 1047 if (wdcprobe(&cp->ata_channel)) 1048 failreason = "other hardware responding at addresses"; 1049 pci_conf_write(sc->sc_pc, sc->sc_tag, 1050 PCI_COMMAND_STATUS_REG, csr); 1051 next: 1052 if (failreason) { 1053 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1054 "%s channel ignored (%s)\n", cp->name, failreason); 1055 cp->ata_channel.ch_flags |= ATACH_DISABLED; 1056 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 1057 wdr->cmd_ios); 1058 bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh, 1059 wdr->ctl_ios); 1060 } else { 1061 pciide_map_compat_intr(pa, cp, 1062 cp->ata_channel.ch_channel); 1063 wdcattach(&cp->ata_channel); 1064 } 1065 } 1066 1067 #if NATA_DMA 1068 if (sc->sc_dma_ok == 0) 1069 return; 1070 1071 /* Allocate DMA maps */ 1072 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1073 channel++) { 1074 idedma_ctl = 0; 1075 cp = &sc->pciide_channels[channel]; 1076 for (drive = 0; drive < sc->sc_wdcdev.wdc_maxdrives; drive++) { 1077 /* 1078 * we have not probed the drives yet, allocate 1079 * ressources for all of them. 1080 */ 1081 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1082 /* Abort DMA setup */ 1083 aprint_error( 1084 "%s:%d:%d: can't allocate DMA maps, " 1085 "using PIO transfers\n", 1086 device_xname( 1087 sc->sc_wdcdev.sc_atac.atac_dev), 1088 channel, drive); 1089 sc->sc_dma_ok = 0; 1090 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA; 1091 sc->sc_wdcdev.irqack = NULL; 1092 break; 1093 } 1094 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1095 } 1096 if (idedma_ctl != 0) { 1097 /* Add software bits in status register */ 1098 bus_space_write_1(sc->sc_dma_iot, 1099 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 1100 } 1101 } 1102 #endif /* NATA_DMA */ 1103 } 1104 1105 void 1106 sata_setup_channel(struct ata_channel *chp) 1107 { 1108 #if NATA_DMA 1109 struct ata_drive_datas *drvp; 1110 int drive; 1111 #if NATA_UDMA 1112 int s; 1113 #endif 1114 u_int32_t idedma_ctl; 1115 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 1116 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 1117 1118 /* setup DMA if needed */ 1119 pciide_channel_dma_setup(cp); 1120 1121 idedma_ctl = 0; 1122 1123 KASSERT(cp->ata_channel.ch_ndrives != 0); 1124 for (drive = 0; drive < cp->ata_channel.ch_ndrives; drive++) { 1125 drvp = &chp->ch_drive[drive]; 1126 /* If no drive, skip */ 1127 if (drvp->drive_type == ATA_DRIVET_NONE) 1128 continue; 1129 #if NATA_UDMA 1130 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 1131 /* use Ultra/DMA */ 1132 s = splbio(); 1133 drvp->drive_flags &= ~ATA_DRIVE_DMA; 1134 splx(s); 1135 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1136 } else 1137 #endif /* NATA_UDMA */ 1138 if (drvp->drive_flags & ATA_DRIVE_DMA) { 1139 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1140 } 1141 } 1142 1143 /* 1144 * Nothing to do to setup modes; it is meaningless in S-ATA 1145 * (but many S-ATA drives still want to get the SET_FEATURE 1146 * command). 1147 */ 1148 if (idedma_ctl != 0) { 1149 /* Add software bits in status register */ 1150 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 1151 idedma_ctl); 1152 } 1153 #endif /* NATA_DMA */ 1154 } 1155
Indexes created Thu Oct 02 07:10:07 GMT 2025