pciide_common.c revision 1.57.2.3
1 /* $NetBSD: pciide_common.c,v 1.57.2.3 2014/08/20 00:03:48 tls Exp $ */ 2 3 4 /* 5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 30 /* 31 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 2. Redistributions in binary form must reproduce the above copyright 39 * notice, this list of conditions and the following disclaimer in the 40 * documentation and/or other materials provided with the distribution. 41 * 3. All advertising materials mentioning features or use of this software 42 * must display the following acknowledgement: 43 * This product includes software developed by Christopher G. Demetriou 44 * for the NetBSD Project. 45 * 4. The name of the author may not be used to endorse or promote products 46 * derived from this software without specific prior written permission 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 58 */ 59 60 /* 61 * PCI IDE controller driver. 62 * 63 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD 64 * sys/dev/pci/ppb.c, revision 1.16). 65 * 66 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and 67 * "Programming Interface for Bus Master IDE Controller, Revision 1.0 68 * 5/16/94" from the PCI SIG. 69 * 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.57.2.3 2014/08/20 00:03:48 tls Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/malloc.h> 77 78 #include <dev/pci/pcireg.h> 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcidevs.h> 81 #include <dev/pci/pciidereg.h> 82 #include <dev/pci/pciidevar.h> 83 84 #include <dev/ic/wdcreg.h> 85 86 #ifdef ATADEBUG 87 int atadebug_pciide_mask = 0; 88 #endif 89 90 #if NATA_DMA 91 static const char dmaerrfmt[] = 92 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n"; 93 #endif 94 95 /* Default product description for devices not known from this controller */ 96 const struct pciide_product_desc default_product_desc = { 97 0, 98 0, 99 "Generic PCI IDE controller", 100 default_chip_map, 101 }; 102 103 const struct pciide_product_desc * 104 pciide_lookup_product(pcireg_t id, const struct pciide_product_desc *pp) 105 { 106 for (; pp->chip_map != NULL; pp++) 107 if (PCI_PRODUCT(id) == pp->ide_product) 108 break; 109 110 if (pp->chip_map == NULL) 111 return NULL; 112 return pp; 113 } 114 115 void 116 pciide_common_attach(struct pciide_softc *sc, const struct pci_attach_args *pa, const struct pciide_product_desc *pp) 117 { 118 pci_chipset_tag_t pc = pa->pa_pc; 119 pcitag_t tag = pa->pa_tag; 120 #if NATA_DMA 121 pcireg_t csr; 122 #endif 123 const char *displaydev = NULL; 124 int dontprint = 0; 125 126 sc->sc_pci_id = pa->pa_id; 127 if (pp == NULL) { 128 /* should only happen for generic pciide devices */ 129 sc->sc_pp = &default_product_desc; 130 } else { 131 sc->sc_pp = pp; 132 /* if ide_name == NULL, printf is done in chip-specific map */ 133 if (pp->ide_name) 134 displaydev = pp->ide_name; 135 else 136 dontprint = 1; 137 } 138 139 if (dontprint) { 140 aprint_naive("disk controller\n"); 141 aprint_normal("\n"); /* ??? */ 142 } else 143 pci_aprint_devinfo_fancy(pa, "disk controller", displaydev, 1); 144 145 sc->sc_pc = pa->pa_pc; 146 sc->sc_tag = pa->pa_tag; 147 148 #if NATA_DMA 149 /* Set up DMA defaults; these might be adjusted by chip_map. */ 150 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX; 151 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN; 152 #endif 153 154 #ifdef ATADEBUG 155 if (atadebug_pciide_mask & DEBUG_PROBE) 156 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL); 157 #endif 158 sc->sc_pp->chip_map(sc, pa); 159 160 #if NATA_DMA 161 if (sc->sc_dma_ok) { 162 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 163 csr |= PCI_COMMAND_MASTER_ENABLE; 164 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 165 } 166 #endif 167 ATADEBUG_PRINT(("pciide: command/status register=%x\n", 168 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE); 169 } 170 171 int 172 pciide_common_detach(struct pciide_softc *sc, int flags) 173 { 174 struct pciide_channel *cp; 175 struct ata_channel *wdc_cp; 176 struct wdc_regs *wdr; 177 int channel, drive; 178 int rv; 179 180 rv = wdcdetach(sc->sc_wdcdev.sc_atac.atac_dev, flags); 181 if (rv) 182 return rv; 183 184 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 185 channel++) { 186 cp = &sc->pciide_channels[channel]; 187 wdc_cp = &cp->ata_channel; 188 wdr = CHAN_TO_WDC_REGS(wdc_cp); 189 190 if (wdc_cp->ch_flags & ATACH_DISABLED) 191 continue; 192 193 if (wdr->cmd_ios != 0) 194 bus_space_unmap(wdr->cmd_iot, 195 wdr->cmd_baseioh, wdr->cmd_ios); 196 if (cp->compat != 0) { 197 if (wdr->ctl_ios != 0) 198 bus_space_unmap(wdr->ctl_iot, 199 wdr->ctl_ioh, wdr->ctl_ios); 200 } else { 201 if (cp->ctl_ios != 0) 202 bus_space_unmap(wdr->ctl_iot, 203 cp->ctl_baseioh, cp->ctl_ios); 204 } 205 206 for (drive = 0; drive < sc->sc_wdcdev.wdc_maxdrives; drive++) { 207 #if NATA_DMA 208 pciide_dma_table_teardown(sc, channel, drive); 209 #endif 210 } 211 212 free(cp->ata_channel.ch_queue, M_DEVBUF); 213 cp->ata_channel.atabus = NULL; 214 } 215 216 #if NATA_DMA 217 if (sc->sc_dma_ios != 0) 218 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios); 219 if (sc->sc_ba5_ss != 0) 220 bus_space_unmap(sc->sc_ba5_st, sc->sc_ba5_sh, sc->sc_ba5_ss); 221 #endif 222 223 return 0; 224 } 225 226 int 227 pciide_detach(device_t self, int flags) 228 { 229 struct pciide_softc *sc = device_private(self); 230 struct pciide_channel *cp; 231 int channel; 232 #ifndef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH 233 bool has_compat_chan; 234 235 has_compat_chan = false; 236 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 237 channel++) { 238 cp = &sc->pciide_channels[channel]; 239 if (cp->compat != 0) { 240 has_compat_chan = true; 241 } 242 } 243 244 if (has_compat_chan != false) 245 return EBUSY; 246 #endif 247 248 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 249 channel++) { 250 cp = &sc->pciide_channels[channel]; 251 if (cp->compat != 0) 252 if (cp->ih != NULL) { 253 pciide_unmap_compat_intr(sc->sc_pc, cp, channel); 254 cp->ih = NULL; 255 } 256 } 257 258 if (sc->sc_pci_ih != NULL) { 259 pci_intr_disestablish(sc->sc_pc, sc->sc_pci_ih); 260 sc->sc_pci_ih = NULL; 261 } 262 263 return pciide_common_detach(sc, flags); 264 } 265 266 /* tell whether the chip is enabled or not */ 267 int 268 pciide_chipen(struct pciide_softc *sc, const struct pci_attach_args *pa) 269 { 270 pcireg_t csr; 271 272 if ((pa->pa_flags & PCI_FLAGS_IO_OKAY) == 0) { 273 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 274 "I/O access disabled at bridge\n"); 275 return 0; 276 } 277 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG); 278 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) { 279 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 280 "I/O access disabled at device\n"); 281 return 0; 282 } 283 return 1; 284 } 285 286 void 287 pciide_mapregs_compat(const struct pci_attach_args *pa, struct pciide_channel *cp, int compatchan) 288 { 289 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 290 struct ata_channel *wdc_cp = &cp->ata_channel; 291 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 292 int i; 293 294 cp->compat = 1; 295 296 wdr->cmd_iot = pa->pa_iot; 297 if (bus_space_map(wdr->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan), 298 PCIIDE_COMPAT_CMD_SIZE, 0, &wdr->cmd_baseioh) != 0) { 299 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 300 "couldn't map %s channel cmd regs\n", cp->name); 301 goto bad; 302 } 303 wdr->cmd_ios = PCIIDE_COMPAT_CMD_SIZE; 304 305 wdr->ctl_iot = pa->pa_iot; 306 if (bus_space_map(wdr->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan), 307 PCIIDE_COMPAT_CTL_SIZE, 0, &wdr->ctl_ioh) != 0) { 308 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 309 "couldn't map %s channel ctl regs\n", cp->name); 310 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 311 goto bad; 312 } 313 wdr->ctl_ios = PCIIDE_COMPAT_CTL_SIZE; 314 315 for (i = 0; i < WDC_NREG; i++) { 316 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 317 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 318 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 319 "couldn't subregion %s channel cmd regs\n", 320 cp->name); 321 goto bad; 322 } 323 } 324 wdc_init_shadow_regs(wdc_cp); 325 wdr->data32iot = wdr->cmd_iot; 326 wdr->data32ioh = wdr->cmd_iohs[0]; 327 return; 328 329 bad: 330 cp->ata_channel.ch_flags |= ATACH_DISABLED; 331 return; 332 } 333 334 void 335 pciide_mapregs_native(const struct pci_attach_args *pa, 336 struct pciide_channel *cp, int (*pci_intr)(void *)) 337 { 338 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 339 struct ata_channel *wdc_cp = &cp->ata_channel; 340 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 341 const char *intrstr; 342 pci_intr_handle_t intrhandle; 343 int i; 344 char intrbuf[PCI_INTRSTR_LEN]; 345 346 cp->compat = 0; 347 348 if (sc->sc_pci_ih == NULL) { 349 if (pci_intr_map(pa, &intrhandle) != 0) { 350 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 351 "couldn't map native-PCI interrupt\n"); 352 goto bad; 353 } 354 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 355 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, 356 intrhandle, IPL_BIO, pci_intr, sc); 357 if (sc->sc_pci_ih != NULL) { 358 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 359 "using %s for native-PCI interrupt\n", 360 intrstr ? intrstr : "unknown interrupt"); 361 } else { 362 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 363 "couldn't establish native-PCI interrupt"); 364 if (intrstr != NULL) 365 aprint_error(" at %s", intrstr); 366 aprint_error("\n"); 367 goto bad; 368 } 369 } 370 cp->ih = sc->sc_pci_ih; 371 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel), 372 PCI_MAPREG_TYPE_IO, 0, 373 &wdr->cmd_iot, &wdr->cmd_baseioh, NULL, &wdr->cmd_ios) != 0) { 374 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 375 "couldn't map %s channel cmd regs\n", cp->name); 376 goto bad; 377 } 378 379 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel), 380 PCI_MAPREG_TYPE_IO, 0, 381 &wdr->ctl_iot, &cp->ctl_baseioh, NULL, &cp->ctl_ios) != 0) { 382 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 383 "couldn't map %s channel ctl regs\n", cp->name); 384 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 385 goto bad; 386 } 387 /* 388 * In native mode, 4 bytes of I/O space are mapped for the control 389 * register, the control register is at offset 2. Pass the generic 390 * code a handle for only one byte at the right offset. 391 */ 392 if (bus_space_subregion(wdr->ctl_iot, cp->ctl_baseioh, 2, 1, 393 &wdr->ctl_ioh) != 0) { 394 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 395 "unable to subregion %s channel ctl regs\n", cp->name); 396 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios); 397 bus_space_unmap(wdr->cmd_iot, cp->ctl_baseioh, cp->ctl_ios); 398 goto bad; 399 } 400 401 for (i = 0; i < WDC_NREG; i++) { 402 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i, 403 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) { 404 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 405 "couldn't subregion %s channel cmd regs\n", 406 cp->name); 407 goto bad; 408 } 409 } 410 wdc_init_shadow_regs(wdc_cp); 411 wdr->data32iot = wdr->cmd_iot; 412 wdr->data32ioh = wdr->cmd_iohs[0]; 413 return; 414 415 bad: 416 cp->ata_channel.ch_flags |= ATACH_DISABLED; 417 return; 418 } 419 420 #if NATA_DMA 421 void 422 pciide_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 423 { 424 pcireg_t maptype; 425 bus_addr_t addr; 426 struct pciide_channel *pc; 427 int reg, chan; 428 bus_size_t size; 429 430 /* 431 * Map DMA registers 432 * 433 * Note that sc_dma_ok is the right variable to test to see if 434 * DMA can be done. If the interface doesn't support DMA, 435 * sc_dma_ok will never be non-zero. If the DMA regs couldn't 436 * be mapped, it'll be zero. I.e., sc_dma_ok will only be 437 * non-zero if the interface supports DMA and the registers 438 * could be mapped. 439 * 440 * XXX Note that despite the fact that the Bus Master IDE specs 441 * XXX say that "The bus master IDE function uses 16 bytes of IO 442 * XXX space," some controllers (at least the United 443 * XXX Microelectronics UM8886BF) place it in memory space. 444 */ 445 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 446 PCIIDE_REG_BUS_MASTER_DMA); 447 448 switch (maptype) { 449 case PCI_MAPREG_TYPE_IO: 450 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag, 451 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 452 &addr, NULL, NULL) == 0); 453 if (sc->sc_dma_ok == 0) { 454 aprint_verbose( 455 ", but unused (couldn't query registers)"); 456 break; 457 } 458 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE) 459 && addr >= 0x10000) { 460 sc->sc_dma_ok = 0; 461 aprint_verbose( 462 ", but unused (registers at unsafe address " 463 "%#lx)", (unsigned long)addr); 464 break; 465 } 466 /* FALLTHROUGH */ 467 468 case PCI_MAPREG_MEM_TYPE_32BIT: 469 sc->sc_dma_ok = (pci_mapreg_map(pa, 470 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0, 471 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios) 472 == 0); 473 sc->sc_dmat = pa->pa_dmat; 474 if (sc->sc_dma_ok == 0) { 475 aprint_verbose(", but unused (couldn't map registers)"); 476 } else { 477 sc->sc_wdcdev.dma_arg = sc; 478 sc->sc_wdcdev.dma_init = pciide_dma_init; 479 sc->sc_wdcdev.dma_start = pciide_dma_start; 480 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 481 } 482 483 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 484 PCIIDE_OPTIONS_NODMA) { 485 aprint_verbose( 486 ", but unused (forced off by config file)"); 487 sc->sc_dma_ok = 0; 488 } 489 break; 490 491 default: 492 sc->sc_dma_ok = 0; 493 aprint_verbose( 494 ", but unsupported register maptype (0x%x)", maptype); 495 } 496 497 if (sc->sc_dma_ok == 0) 498 return; 499 500 /* 501 * Set up the default handles for the DMA registers. 502 * Just reserve 32 bits for each handle, unless space 503 * doesn't permit it. 504 */ 505 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) { 506 pc = &sc->pciide_channels[chan]; 507 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 508 size = 4; 509 if (size > (IDEDMA_SCH_OFFSET - reg)) 510 size = IDEDMA_SCH_OFFSET - reg; 511 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh, 512 IDEDMA_SCH_OFFSET * chan + reg, size, 513 &pc->dma_iohs[reg]) != 0) { 514 sc->sc_dma_ok = 0; 515 aprint_verbose(", but can't subregion offset %d " 516 "size %lu", reg, (u_long)size); 517 return; 518 } 519 } 520 } 521 } 522 #endif /* NATA_DMA */ 523 524 int 525 pciide_compat_intr(void *arg) 526 { 527 struct pciide_channel *cp = arg; 528 529 #ifdef DIAGNOSTIC 530 /* should only be called for a compat channel */ 531 if (cp->compat == 0) 532 panic("pciide compat intr called for non-compat chan %p", cp); 533 #endif 534 return (wdcintr(&cp->ata_channel)); 535 } 536 537 int 538 pciide_pci_intr(void *arg) 539 { 540 struct pciide_softc *sc = arg; 541 struct pciide_channel *cp; 542 struct ata_channel *wdc_cp; 543 int i, rv, crv; 544 545 rv = 0; 546 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 547 cp = &sc->pciide_channels[i]; 548 wdc_cp = &cp->ata_channel; 549 550 /* If a compat channel skip. */ 551 if (cp->compat) 552 continue; 553 /* if this channel not waiting for intr, skip */ 554 if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0) 555 continue; 556 557 crv = wdcintr(wdc_cp); 558 if (crv == 0) 559 ; /* leave rv alone */ 560 else if (crv == 1) 561 rv = 1; /* claim the intr */ 562 else if (rv == 0) /* crv should be -1 in this case */ 563 rv = crv; /* if we've done no better, take it */ 564 } 565 return (rv); 566 } 567 568 #if NATA_DMA 569 void 570 pciide_channel_dma_setup(struct pciide_channel *cp) 571 { 572 int drive, s; 573 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 574 struct ata_drive_datas *drvp; 575 576 KASSERT(cp->ata_channel.ch_ndrives != 0); 577 578 for (drive = 0; drive < cp->ata_channel.ch_ndrives; drive++) { 579 drvp = &cp->ata_channel.ch_drive[drive]; 580 /* If no drive, skip */ 581 if (drvp->drive_type == ATA_DRIVET_NONE) 582 continue; 583 /* setup DMA if needed */ 584 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 585 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0) || 586 sc->sc_dma_ok == 0) { 587 s = splbio(); 588 drvp->drive_flags &= ~(ATA_DRIVE_DMA | ATA_DRIVE_UDMA); 589 splx(s); 590 continue; 591 } 592 if (pciide_dma_table_setup(sc, cp->ata_channel.ch_channel, 593 drive) != 0) { 594 /* Abort DMA setup */ 595 s = splbio(); 596 drvp->drive_flags &= ~(ATA_DRIVE_DMA | ATA_DRIVE_UDMA); 597 splx(s); 598 continue; 599 } 600 } 601 } 602 603 #define NIDEDMA_TABLES(sc) \ 604 (sc->sc_wdcdev.sc_atac.atac_dev->dv_maxphys / \ 605 (min((sc)->sc_dma_maxsegsz, PAGE_SIZE)) + 1) 606 607 int 608 pciide_dma_table_setup(struct pciide_softc *sc, int channel, int drive) 609 { 610 int error; 611 const bus_size_t dma_table_size = 612 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc); 613 struct pciide_dma_maps *dma_maps = 614 &sc->pciide_channels[channel].dma_maps[drive]; 615 616 /* If table was already allocated, just return */ 617 if (dma_maps->dma_table) 618 return 0; 619 620 /* Allocate memory for the DMA tables and map it */ 621 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size, 622 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &dma_maps->dmamap_table_seg, 623 1, &dma_maps->dmamap_table_nseg, BUS_DMA_NOWAIT)) != 0) { 624 aprint_error(dmaerrfmt, 625 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 626 "allocate", drive, error); 627 return error; 628 } 629 if ((error = bus_dmamem_map(sc->sc_dmat, &dma_maps->dmamap_table_seg, 630 dma_maps->dmamap_table_nseg, dma_table_size, 631 (void **)&dma_maps->dma_table, 632 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 633 aprint_error(dmaerrfmt, 634 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 635 "map", drive, error); 636 return error; 637 } 638 ATADEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, " 639 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size, 640 (unsigned long)dma_maps->dmamap_table_seg.ds_addr), DEBUG_PROBE); 641 /* Create and load table DMA map for this disk */ 642 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size, 643 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT, 644 &dma_maps->dmamap_table)) != 0) { 645 aprint_error(dmaerrfmt, 646 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 647 "create", drive, error); 648 return error; 649 } 650 if ((error = bus_dmamap_load(sc->sc_dmat, 651 dma_maps->dmamap_table, 652 dma_maps->dma_table, 653 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) { 654 aprint_error(dmaerrfmt, 655 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 656 "load", drive, error); 657 return error; 658 } 659 ATADEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n", 660 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr), 661 DEBUG_PROBE); 662 /* Create a xfer DMA map for this drive */ 663 if ((error = bus_dmamap_create(sc->sc_dmat, 664 sc->sc_wdcdev.sc_atac.atac_dev->dv_maxphys, 665 NIDEDMA_TABLES(sc), sc->sc_dma_maxsegsz, sc->sc_dma_boundary, 666 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 667 &dma_maps->dmamap_xfer)) != 0) { 668 aprint_error(dmaerrfmt, 669 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 670 "create xfer", drive, error); 671 return error; 672 } 673 return 0; 674 } 675 676 void 677 pciide_dma_table_teardown(struct pciide_softc *sc, int channel, int drive) 678 { 679 struct pciide_channel *cp; 680 struct pciide_dma_maps *dma_maps; 681 682 cp = &sc->pciide_channels[channel]; 683 dma_maps = &cp->dma_maps[drive]; 684 685 if (dma_maps->dma_table == NULL) 686 return; 687 688 bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_xfer); 689 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_table); 690 bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_table); 691 bus_dmamem_unmap(sc->sc_dmat, dma_maps->dma_table, 692 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc)); 693 bus_dmamem_free(sc->sc_dmat, &dma_maps->dmamap_table_seg, 694 dma_maps->dmamap_table_nseg); 695 696 dma_maps->dma_table = NULL; 697 698 return; 699 } 700 701 int 702 pciide_dma_dmamap_setup(struct pciide_softc *sc, int channel, int drive, void *databuf, size_t datalen, int flags) 703 { 704 int error, seg; 705 struct pciide_channel *cp = &sc->pciide_channels[channel]; 706 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 707 708 error = bus_dmamap_load(sc->sc_dmat, 709 dma_maps->dmamap_xfer, 710 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 711 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)); 712 if (error) { 713 aprint_error(dmaerrfmt, 714 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 715 "load xfer", drive, error); 716 return error; 717 } 718 719 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 720 dma_maps->dmamap_xfer->dm_mapsize, 721 (flags & WDC_DMA_READ) ? 722 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 723 724 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) { 725 #ifdef DIAGNOSTIC 726 /* A segment must not cross a 64k boundary */ 727 { 728 u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr; 729 u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len; 730 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) != 731 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) { 732 printf("pciide_dma: segment %d physical addr 0x%lx" 733 " len 0x%lx not properly aligned\n", 734 seg, phys, len); 735 panic("pciide_dma: buf align"); 736 } 737 } 738 #endif 739 dma_maps->dma_table[seg].base_addr = 740 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr); 741 dma_maps->dma_table[seg].byte_count = 742 htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len & 743 IDEDMA_BYTE_COUNT_MASK); 744 ATADEBUG_PRINT(("\t seg %d len %d addr 0x%x\n", 745 seg, le32toh(dma_maps->dma_table[seg].byte_count), 746 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA); 747 748 } 749 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |= 750 htole32(IDEDMA_BYTE_COUNT_EOT); 751 752 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0, 753 dma_maps->dmamap_table->dm_mapsize, 754 BUS_DMASYNC_PREWRITE); 755 756 #ifdef DIAGNOSTIC 757 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) { 758 printf("pciide_dma_dmamap_setup: addr 0x%lx " 759 "not properly aligned\n", 760 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr); 761 panic("pciide_dma_init: table align"); 762 } 763 #endif 764 /* remember flags */ 765 dma_maps->dma_flags = flags; 766 767 return 0; 768 } 769 770 int 771 pciide_dma_init(void *v, int channel, int drive, void *databuf, size_t datalen, int flags) 772 { 773 struct pciide_softc *sc = v; 774 int error; 775 struct pciide_channel *cp = &sc->pciide_channels[channel]; 776 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 777 778 if ((error = pciide_dma_dmamap_setup(sc, channel, drive, 779 databuf, datalen, flags)) != 0) 780 return error; 781 /* Maps are ready. Start DMA function */ 782 /* Clear status bits */ 783 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 784 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 785 /* Write table addr */ 786 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0, 787 dma_maps->dmamap_table->dm_segs[0].ds_addr); 788 /* set read/write */ 789 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 790 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd); 791 return 0; 792 } 793 794 void 795 pciide_dma_start(void *v, int channel, int drive) 796 { 797 struct pciide_softc *sc = v; 798 struct pciide_channel *cp = &sc->pciide_channels[channel]; 799 800 ATADEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS); 801 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 802 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 803 | IDEDMA_CMD_START); 804 } 805 806 int 807 pciide_dma_finish(void *v, int channel, int drive, int force) 808 { 809 struct pciide_softc *sc = v; 810 u_int8_t status; 811 int error = 0; 812 struct pciide_channel *cp = &sc->pciide_channels[channel]; 813 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive]; 814 815 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0); 816 ATADEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status), 817 DEBUG_XFERS); 818 819 if (force == WDC_DMAEND_END && (status & IDEDMA_CTL_INTR) == 0) 820 return WDC_DMAST_NOIRQ; 821 822 /* stop DMA channel */ 823 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0, 824 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0) 825 & ~IDEDMA_CMD_START); 826 827 /* Unload the map of the data buffer */ 828 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0, 829 dma_maps->dmamap_xfer->dm_mapsize, 830 (dma_maps->dma_flags & WDC_DMA_READ) ? 831 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 832 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer); 833 834 if ((status & IDEDMA_CTL_ERR) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 835 aprint_error("%s:%d:%d: bus-master DMA error: status=0x%x\n", 836 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel, 837 drive, status); 838 error |= WDC_DMAST_ERR; 839 } 840 841 if ((status & IDEDMA_CTL_INTR) == 0 && force != WDC_DMAEND_ABRT_QUIET) { 842 aprint_error("%s:%d:%d: bus-master DMA error: missing " 843 "interrupt, status=0x%x\n", 844 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), 845 channel, drive, status); 846 error |= WDC_DMAST_NOIRQ; 847 } 848 849 if ((status & IDEDMA_CTL_ACT) != 0 && force != WDC_DMAEND_ABRT_QUIET) { 850 /* data underrun, may be a valid condition for ATAPI */ 851 error |= WDC_DMAST_UNDER; 852 } 853 return error; 854 } 855 856 void 857 pciide_irqack(struct ata_channel *chp) 858 { 859 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 860 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 861 862 /* clear status bits in IDE DMA registers */ 863 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 864 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0)); 865 } 866 #endif /* NATA_DMA */ 867 868 /* some common code used by several chip_map */ 869 int 870 pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface) 871 { 872 struct pciide_channel *cp = &sc->pciide_channels[channel]; 873 sc->wdc_chanarray[channel] = &cp->ata_channel; 874 cp->name = PCIIDE_CHANNEL_NAME(channel); 875 cp->ata_channel.ch_channel = channel; 876 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 877 cp->ata_channel.ch_queue = 878 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT|M_ZERO); 879 if (cp->ata_channel.ch_queue == NULL) { 880 aprint_error("%s %s channel: " 881 "can't allocate memory for command queue", 882 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 883 return 0; 884 } 885 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 886 "%s channel %s to %s mode\n", cp->name, 887 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ? 888 "configured" : "wired", 889 (interface & PCIIDE_INTERFACE_PCI(channel)) ? 890 "native-PCI" : "compatibility"); 891 return 1; 892 } 893 894 /* some common code used by several chip channel_map */ 895 void 896 pciide_mapchan(const struct pci_attach_args *pa, 897 struct pciide_channel *cp, 898 pcireg_t interface, int (*pci_intr)(void *)) 899 { 900 struct ata_channel *wdc_cp = &cp->ata_channel; 901 902 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel)) 903 pciide_mapregs_native(pa, cp, pci_intr); 904 else { 905 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel); 906 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0) 907 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel); 908 } 909 wdcattach(wdc_cp); 910 } 911 912 /* 913 * generic code to map the compat intr. 914 */ 915 void 916 pciide_map_compat_intr(const struct pci_attach_args *pa, struct pciide_channel *cp, int compatchan) 917 { 918 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 919 920 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 921 cp->ih = 922 pciide_machdep_compat_intr_establish(sc->sc_wdcdev.sc_atac.atac_dev, 923 pa, compatchan, pciide_compat_intr, cp); 924 if (cp->ih == NULL) { 925 #endif 926 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 927 "no compatibility interrupt for use by %s " 928 "channel\n", cp->name); 929 cp->ata_channel.ch_flags |= ATACH_DISABLED; 930 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH 931 } 932 #endif 933 } 934 935 void 936 pciide_unmap_compat_intr(pci_chipset_tag_t pc, struct pciide_channel *cp, int compatchan) 937 { 938 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH 939 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel); 940 941 pciide_machdep_compat_intr_disestablish(sc->sc_wdcdev.sc_atac.atac_dev, 942 sc->sc_pc, compatchan, cp->ih); 943 #endif 944 } 945 946 void 947 default_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 948 { 949 struct pciide_channel *cp; 950 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 951 pcireg_t csr; 952 int channel; 953 #if NATA_DMA 954 int drive; 955 u_int8_t idedma_ctl; 956 #endif 957 const char *failreason; 958 struct wdc_regs *wdr; 959 960 if (pciide_chipen(sc, pa) == 0) 961 return; 962 963 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) { 964 #if NATA_DMA 965 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 966 "bus-master DMA support present"); 967 if (sc->sc_pp == &default_product_desc && 968 (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 969 PCIIDE_OPTIONS_DMA) == 0) { 970 aprint_verbose(", but unused (no driver support)"); 971 sc->sc_dma_ok = 0; 972 } else { 973 pciide_mapreg_dma(sc, pa); 974 if (sc->sc_dma_ok != 0) 975 aprint_verbose(", used without full driver " 976 "support"); 977 } 978 #else 979 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 980 "bus-master DMA support present, but unused (no driver " 981 "support)"); 982 #endif /* NATA_DMA */ 983 } else { 984 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 985 "hardware does not support DMA"); 986 #if NATA_DMA 987 sc->sc_dma_ok = 0; 988 #endif 989 } 990 aprint_verbose("\n"); 991 #if NATA_DMA 992 if (sc->sc_dma_ok) { 993 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 994 sc->sc_wdcdev.irqack = pciide_irqack; 995 } 996 #endif 997 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0; 998 #if NATA_DMA 999 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0; 1000 #endif 1001 1002 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 1003 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 1004 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16; 1005 sc->sc_wdcdev.wdc_maxdrives = 2; 1006 1007 wdc_allocate_regs(&sc->sc_wdcdev); 1008 1009 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1010 channel++) { 1011 cp = &sc->pciide_channels[channel]; 1012 if (pciide_chansetup(sc, channel, interface) == 0) 1013 continue; 1014 wdr = CHAN_TO_WDC_REGS(&cp->ata_channel); 1015 if (interface & PCIIDE_INTERFACE_PCI(channel)) 1016 pciide_mapregs_native(pa, cp, pciide_pci_intr); 1017 else 1018 pciide_mapregs_compat(pa, cp, 1019 cp->ata_channel.ch_channel); 1020 if (cp->ata_channel.ch_flags & ATACH_DISABLED) 1021 continue; 1022 /* 1023 * Check to see if something appears to be there. 1024 */ 1025 failreason = NULL; 1026 /* 1027 * In native mode, always enable the controller. It's 1028 * not possible to have an ISA board using the same address 1029 * anyway. 1030 */ 1031 if (interface & PCIIDE_INTERFACE_PCI(channel)) { 1032 wdcattach(&cp->ata_channel); 1033 continue; 1034 } 1035 if (!wdcprobe(&cp->ata_channel)) { 1036 failreason = "not responding; disabled or no drives?"; 1037 goto next; 1038 } 1039 /* 1040 * Now, make sure it's actually attributable to this PCI IDE 1041 * channel by trying to access the channel again while the 1042 * PCI IDE controller's I/O space is disabled. (If the 1043 * channel no longer appears to be there, it belongs to 1044 * this controller.) YUCK! 1045 */ 1046 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, 1047 PCI_COMMAND_STATUS_REG); 1048 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1049 csr & ~PCI_COMMAND_IO_ENABLE); 1050 if (wdcprobe(&cp->ata_channel)) 1051 failreason = "other hardware responding at addresses"; 1052 pci_conf_write(sc->sc_pc, sc->sc_tag, 1053 PCI_COMMAND_STATUS_REG, csr); 1054 next: 1055 if (failreason) { 1056 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 1057 "%s channel ignored (%s)\n", cp->name, failreason); 1058 cp->ata_channel.ch_flags |= ATACH_DISABLED; 1059 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, 1060 wdr->cmd_ios); 1061 bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh, 1062 wdr->ctl_ios); 1063 } else { 1064 pciide_map_compat_intr(pa, cp, 1065 cp->ata_channel.ch_channel); 1066 wdcattach(&cp->ata_channel); 1067 } 1068 } 1069 1070 #if NATA_DMA 1071 if (sc->sc_dma_ok == 0) 1072 return; 1073 1074 /* Allocate DMA maps */ 1075 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 1076 channel++) { 1077 idedma_ctl = 0; 1078 cp = &sc->pciide_channels[channel]; 1079 for (drive = 0; drive < sc->sc_wdcdev.wdc_maxdrives; drive++) { 1080 /* 1081 * we have not probed the drives yet, allocate 1082 * ressources for all of them. 1083 */ 1084 if (pciide_dma_table_setup(sc, channel, drive) != 0) { 1085 /* Abort DMA setup */ 1086 aprint_error( 1087 "%s:%d:%d: can't allocate DMA maps, " 1088 "using PIO transfers\n", 1089 device_xname( 1090 sc->sc_wdcdev.sc_atac.atac_dev), 1091 channel, drive); 1092 sc->sc_dma_ok = 0; 1093 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA; 1094 sc->sc_wdcdev.irqack = NULL; 1095 break; 1096 } 1097 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1098 } 1099 if (idedma_ctl != 0) { 1100 /* Add software bits in status register */ 1101 bus_space_write_1(sc->sc_dma_iot, 1102 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl); 1103 } 1104 } 1105 #endif /* NATA_DMA */ 1106 } 1107 1108 void 1109 sata_setup_channel(struct ata_channel *chp) 1110 { 1111 #if NATA_DMA 1112 struct ata_drive_datas *drvp; 1113 int drive; 1114 #if NATA_UDMA 1115 int s; 1116 #endif 1117 u_int32_t idedma_ctl; 1118 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 1119 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 1120 1121 /* setup DMA if needed */ 1122 pciide_channel_dma_setup(cp); 1123 1124 idedma_ctl = 0; 1125 1126 KASSERT(cp->ata_channel.ch_ndrives != 0); 1127 for (drive = 0; drive < cp->ata_channel.ch_ndrives; drive++) { 1128 drvp = &chp->ch_drive[drive]; 1129 /* If no drive, skip */ 1130 if (drvp->drive_type == ATA_DRIVET_NONE) 1131 continue; 1132 #if NATA_UDMA 1133 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 1134 /* use Ultra/DMA */ 1135 s = splbio(); 1136 drvp->drive_flags &= ~ATA_DRIVE_DMA; 1137 splx(s); 1138 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1139 } else 1140 #endif /* NATA_UDMA */ 1141 if (drvp->drive_flags & ATA_DRIVE_DMA) { 1142 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 1143 } 1144 } 1145 1146 /* 1147 * Nothing to do to setup modes; it is meaningless in S-ATA 1148 * (but many S-ATA drives still want to get the SET_FEATURE 1149 * command). 1150 */ 1151 if (idedma_ctl != 0) { 1152 /* Add software bits in status register */ 1153 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 1154 idedma_ctl); 1155 } 1156 #endif /* NATA_DMA */ 1157 } 1158
Indexes created Thu Oct 02 07:10:07 GMT 2025